Merge branch 'pxa' into devel

66 files changed, 7135 insertions, 519 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fcd1d8f95a21..0a0c88d0039c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -339,14 +339,14 @@ config ARCH_PNX4008
           This enables support for Philips PNX4008 mobile platform.
 
 config ARCH_PXA
-        bool "PXA2xx-based"
+        bool "PXA2xx/PXA3xx-based"
         depends on MMU
         select ARCH_MTD_XIP
         select GENERIC_GPIO
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
         help
-          Support for Intel's PXA2XX processor line.
+          Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 
 config ARCH_RPC
         bool "RiscPC"
@@ -489,7 +489,7 @@ source arch/arm/mm/Kconfig
 config IWMMXT
         bool "Enable iWMMXt support"
         depends on CPU_XSCALE || CPU_XSC3
-        default y if PXA27x
+        default y if PXA27x || PXA3xx
         help
           Enable support for iWMMXt context switching at run time if
           running on a CPU that supports it.
diff --git a/arch/arm/boot/compressed/head-xscale.S b/arch/arm/boot/compressed/head-xscale.S
index 236bbe578312..67ea99ef6521 100644
--- a/arch/arm/boot/compressed/head-xscale.S
+++ b/arch/arm/boot/compressed/head-xscale.S
@@ -33,10 +33,6 @@ __XScale_start:
                 bic     r0, r0, #0x1000         @ clear Icache
                 mcr     p15, 0, r0, c1, c0, 0
 
-#ifdef CONFIG_ARCH_LUBBOCK
-                mov     r7, #MACH_TYPE_LUBBOCK
-#endif
-
 #ifdef CONFIG_ARCH_COTULLA_IDP
                 mov     r7, #MACH_TYPE_COTULLA_IDP
 #endif
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index e1289a256ce5..3d0b9fa42f84 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_SHARPSL_PM)	+= sharpsl_pm.o
 obj-$(CONFIG_SHARP_SCOOP)       += scoop.o
 obj-$(CONFIG_ARCH_IXP2000)      += uengine.o
 obj-$(CONFIG_ARCH_IXP23XX)      += uengine.o
+obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
new file mode 100644
index 000000000000..c03de9bfd76b
--- /dev/null
+++ b/arch/arm/common/it8152.c
@@ -0,0 +1,387 @@
+/*
+ * linux/arch/arm/common/it8152.c
+ *
+ * Copyright Compulab Ltd, 2002-2007
+ * Mike Rapoport <mike@compulab.co.il>
+ *
+ * The DMA bouncing part is taken from arch/arm/mach-ixp4xx/common-pci.c
+ * (see this file for respective copyrights)
+ *
+ * Thanks to Guennadi Liakhovetski <gl@dsa-ac.de> for IRQ enumberation
+ * and demux code.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/ptrace.h>
+#include <linux/interrupt.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+
+#include <asm/mach/pci.h>
+#include <asm/hardware/it8152.h>
+
+#define MAX_SLOTS               21
+
+static void it8152_mask_irq(unsigned int irq)
+{
+       if (irq >= IT8152_LD_IRQ(0)) {
+               __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) |
+                            (1 << (irq - IT8152_LD_IRQ(0)))),
+                            IT8152_INTC_LDCNIMR);
+       } else if (irq >= IT8152_LP_IRQ(0)) {
+               __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) |
+                            (1 << (irq - IT8152_LP_IRQ(0)))),
+                            IT8152_INTC_LPCNIMR);
+       } else if (irq >= IT8152_PD_IRQ(0)) {
+               __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) |
+                            (1 << (irq - IT8152_PD_IRQ(0)))),
+                            IT8152_INTC_PDCNIMR);
+       }
+}
+
+static void it8152_unmask_irq(unsigned int irq)
+{
+       if (irq >= IT8152_LD_IRQ(0)) {
+               __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) &
+                             ~(1 << (irq - IT8152_LD_IRQ(0)))),
+                            IT8152_INTC_LDCNIMR);
+       } else if (irq >= IT8152_LP_IRQ(0)) {
+               __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) &
+                             ~(1 << (irq - IT8152_LP_IRQ(0)))),
+                            IT8152_INTC_LPCNIMR);
+       } else if (irq >= IT8152_PD_IRQ(0)) {
+               __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) &
+                             ~(1 << (irq - IT8152_PD_IRQ(0)))),
+                            IT8152_INTC_PDCNIMR);
+       }
+}
+
+static inline void it8152_irq(int irq)
+{
+        struct irq_desc *desc;
+
+        printk(KERN_DEBUG "===> %s: irq=%d\n", __FUNCTION__, irq);
+
+        desc = irq_desc + irq;
+        desc_handle_irq(irq, desc);
+}
+
+static struct irq_chip it8152_irq_chip = {
+        .name           = "it8152",
+        .ack            = it8152_mask_irq,
+        .mask           = it8152_mask_irq,
+        .unmask         = it8152_unmask_irq,
+};
+
+void it8152_init_irq(void)
+{
+        int irq;
+
+        __raw_writel((0xffff), IT8152_INTC_PDCNIMR);
+        __raw_writel((0), IT8152_INTC_PDCNIRR);
+        __raw_writel((0xffff), IT8152_INTC_LPCNIMR);
+        __raw_writel((0), IT8152_INTC_LPCNIRR);
+        __raw_writel((0xffff), IT8152_INTC_LDCNIMR);
+        __raw_writel((0), IT8152_INTC_LDCNIRR);
+
+        for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
+                set_irq_chip(irq, &it8152_irq_chip);
+                set_irq_handler(irq, handle_level_irq);
+                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+        }
+}
+
+void it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
+{
+       int bits_pd, bits_lp, bits_ld;
+       int i;
+
+       printk(KERN_DEBUG "=> %s: irq = %d\n", __FUNCTION__, irq);
+
+       while (1) {
+               /* Read all */
+               bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
+               bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
+               bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
+
+               /* Ack */
+               __raw_writel((~bits_pd), IT8152_INTC_PDCNIRR);
+               __raw_writel((~bits_lp), IT8152_INTC_LPCNIRR);
+               __raw_writel((~bits_ld), IT8152_INTC_LDCNIRR);
+
+               if (!(bits_ld | bits_lp | bits_pd)) {
+                       /* Re-read to guarantee, that there was a moment of
+                          time, when they all three were 0. */
+                       bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
+                       bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
+                       if (!(bits_ld | bits_lp | bits_pd))
+                               return;
+               }
+
+               bits_pd &= ((1 << IT8152_PD_IRQ_COUNT) - 1);
+               while (bits_pd) {
+                       i = __ffs(bits_pd);
+                       it8152_irq(IT8152_PD_IRQ(i));
+                       bits_pd &= ~(1 << i);
+               }
+
+               bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1);
+               while (bits_lp) {
+                       i = __ffs(bits_pd);
+                       it8152_irq(IT8152_LP_IRQ(i));
+                       bits_lp &= ~(1 << i);
+               }
+
+               bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1);
+               while (bits_ld) {
+                       i = __ffs(bits_pd);
+                       it8152_irq(IT8152_LD_IRQ(i));
+                       bits_ld &= ~(1 << i);
+               }
+       }
+}
+
+/* mapping for on-chip devices */
+int __init it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
+            (dev->device == PCI_DEVICE_ID_ITE_8152)) {
+                if ((dev->class >> 8) == PCI_CLASS_MULTIMEDIA_AUDIO)
+                        return IT8152_AUDIO_INT;
+                if ((dev->class >> 8) == PCI_CLASS_SERIAL_USB)
+                        return IT8152_USB_INT;
+                if ((dev->class >> 8) == PCI_CLASS_SYSTEM_DMA)
+                        return IT8152_CDMA_INT;
+        }
+
+        return 0;
+}
+
+static unsigned long it8152_pci_dev_base_address(struct pci_bus *bus,
+                                                 unsigned int devfn)
+{
+        unsigned long addr = 0;
+
+        if (bus->number == 0) {
+                        if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
+                                addr = (devfn << 8);
+        } else
+                addr = (bus->number << 16) | (devfn << 8);
+
+        return addr;
+}
+
+static int it8152_pci_read_config(struct pci_bus *bus,
+                                  unsigned int devfn, int where,
+                                  int size, u32 *value)
+{
+        unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
+        u32 v;
+        int shift;
+
+        shift = (where & 3);
+
+        __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
+        v = (__raw_readl(IT8152_PCI_CFG_DATA)  >> (8 * (shift)));
+
+        *value = v;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int it8152_pci_write_config(struct pci_bus *bus,
+                                   unsigned int devfn, int where,
+                                   int size, u32 value)
+{
+        unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
+        u32 v, vtemp, mask = 0;
+        int shift;
+
+        if (size == 1)
+                mask = 0xff;
+        if (size == 2)
+                mask = 0xffff;
+
+        shift = (where & 3);
+
+        __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
+        vtemp = __raw_readl(IT8152_PCI_CFG_DATA);
+
+        if (mask)
+                vtemp &= ~(mask << (8 * shift));
+        else
+                vtemp = 0;
+
+        v = (value << (8 * shift));
+        __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
+        __raw_writel((v | vtemp), IT8152_PCI_CFG_DATA);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops it8152_ops = {
+        .read = it8152_pci_read_config,
+        .write = it8152_pci_write_config,
+};
+
+static struct resource it8152_io = {
+        .name   = "IT8152 PCI I/O region",
+        .flags  = IORESOURCE_IO,
+};
+
+static struct resource it8152_mem = {
+        .name   = "IT8152 PCI memory region",
+        .start  = 0x10000000,
+        .end    = 0x13e00000,
+        .flags  = IORESOURCE_MEM,
+};
+
+/*
+ * The following functions are needed for DMA bouncing.
+ * ITE8152 chip can addrees up to 64MByte, so all the devices
+ * connected to ITE8152 (PCI and USB) should have limited DMA window
+ */
+
+/*
+ * Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all
+ * other devices.
+ */
+static int it8152_pci_platform_notify(struct device *dev)
+{
+        if (dev->bus == &pci_bus_type) {
+                if (dev->dma_mask)
+                        *dev->dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
+                dev->coherent_dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
+                dmabounce_register_dev(dev, 2048, 4096);
+        }
+        return 0;
+}
+
+static int it8152_pci_platform_notify_remove(struct device *dev)
+{
+        if (dev->bus == &pci_bus_type)
+                dmabounce_unregister_dev(dev);
+
+        return 0;
+}
+
+int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
+{
+        dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
+                __FUNCTION__, dma_addr, size);
+        return (dev->bus == &pci_bus_type) &&
+                ((dma_addr + size - PHYS_OFFSET) >= SZ_64M);
+}
+
+/*
+ * We override these so we properly do dmabounce otherwise drivers
+ * are able to set the dma_mask to 0xffffffff and we can no longer
+ * trap bounces. :(
+ *
+ * We just return true on everyhing except for < 64MB in which case
+ * we will fail miseralby and die since we can't handle that case.
+ */
+int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
+{
+        printk(KERN_DEBUG "%s: %s %llx\n",
+               __FUNCTION__, dev->dev.bus_id, mask);
+        if (mask >= PHYS_OFFSET + SZ_64M - 1)
+                return 0;
+
+        return -EIO;
+}
+
+int
+pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
+{
+        printk(KERN_DEBUG "%s: %s %llx\n",
+               __FUNCTION__, dev->dev.bus_id, mask);
+        if (mask >= PHYS_OFFSET + SZ_64M - 1)
+                return 0;
+
+        return -EIO;
+}
+
+int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
+{
+        it8152_io.start = IT8152_IO_BASE + 0x12000;
+        it8152_io.end   = IT8152_IO_BASE + 0x12000 + 0x100000;
+
+        sys->mem_offset = 0x10000000;
+        sys->io_offset  = IT8152_IO_BASE;
+
+        if (request_resource(&ioport_resource, &it8152_io)) {
+                printk(KERN_ERR "PCI: unable to allocate IO region\n");
+                goto err0;
+        }
+        if (request_resource(&iomem_resource, &it8152_mem)) {
+                printk(KERN_ERR "PCI: unable to allocate memory region\n");
+                goto err1;
+        }
+
+        sys->resource[0] = &it8152_io;
+        sys->resource[1] = &it8152_mem;
+
+        if (platform_notify || platform_notify_remove) {
+                printk(KERN_ERR "PCI: Can't use platform_notify\n");
+                goto err2;
+        }
+
+        platform_notify = it8152_pci_platform_notify;
+        platform_notify_remove = it8152_pci_platform_notify_remove;
+
+        return 1;
+
+err2:
+        release_resource(&it8152_io);
+err1:
+        release_resource(&it8152_mem);
+err0:
+        return -EBUSY;
+}
+
+/*
+ * If we set up a device for bus mastering, we need to check the latency
+ * timer as we don't have even crappy BIOSes to set it properly.
+ * The implementation is from arch/i386/pci/i386.c
+ */
+unsigned int pcibios_max_latency = 255;
+
+void pcibios_set_master(struct pci_dev *dev)
+{
+        u8 lat;
+
+        /* no need to update on-chip OHCI controller */
+        if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
+            (dev->device == PCI_DEVICE_ID_ITE_8152) &&
+            ((dev->class >> 8) == PCI_CLASS_SERIAL_USB))
+                return;
+
+        pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
+        if (lat < 16)
+                lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
+        else if (lat > pcibios_max_latency)
+                lat = pcibios_max_latency;
+        else
+                return;
+        printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
+               pci_name(dev), lat);
+        pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
+}
+
+
+struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys)
+{
+        return pci_scan_bus(nr, &it8152_ops, sys);
+}
+
diff --git a/arch/arm/configs/cm_x270_defconfig b/arch/arm/configs/cm_x270_defconfig
new file mode 100644
index 000000000000..5cab08397ae7
--- /dev/null
+++ b/arch/arm/configs/cm_x270_defconfig
@@ -0,0 +1,1410 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.22
+# Wed Jul 18 14:11:48 2007
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+# CONFIG_EPOLL is not set
+# CONFIG_SIGNALFD is not set
+# CONFIG_TIMERFD is not set
+# CONFIG_EVENTFD is not set
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_PNX4008 is not set
+CONFIG_ARCH_PXA=y
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+CONFIG_DMABOUNCE=y
+
+#
+# Intel PXA2xx Implementations
+#
+# CONFIG_ARCH_LUBBOCK is not set
+# CONFIG_MACH_LOGICPD_PXA270 is not set
+# CONFIG_MACH_MAINSTONE is not set
+# CONFIG_ARCH_PXA_IDP is not set
+# CONFIG_PXA_SHARPSL is not set
+# CONFIG_MACH_TRIZEPS4 is not set
+CONFIG_MACH_ARMCORE=y
+CONFIG_PXA27x=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+CONFIG_IWMMXT=y
+CONFIG_XSCALE_PMU=y
+
+#
+# Bus support
+#
+CONFIG_PCI=y
+CONFIG_PCI_SYSCALL=y
+CONFIG_PCI_HOST_ITE8152=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCI_DEBUG is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_LEGACY is not set
+# CONFIG_PM_DEBUG is not set
+# CONFIG_PM_SYSFS_DEPRECATED is not set
+# CONFIG_APM_EMULATION is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+CONFIG_IEEE80211_CRYPT_CCMP=m
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+# CONFIG_IEEE80211_SOFTMAC is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=m
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=m
+CONFIG_MTD_BLKDEVS=m
+CONFIG_MTD_BLOCK=m
+# CONFIG_MTD_BLOCK_RO is not set
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_SHARP_SL is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=m
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_H1900 is not set
+CONFIG_MTD_NAND_IDS=m
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_SHARPSL is not set
+# CONFIG_MTD_NAND_CAFE is not set
+CONFIG_MTD_NAND_CM_X270=m
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=12000
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_IDE=m
+CONFIG_IDE_MAX_HWIFS=4
+CONFIG_BLK_DEV_IDE=m
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=m
+# CONFIG_IDEDISK_MULTI_MODE is not set
+CONFIG_BLK_DEV_IDECD=m
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDEPCI_PCIBUS_ORDER is not set
+# CONFIG_IDE_ARM is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+# CONFIG_FUSION_SPI is not set
+# CONFIG_FUSION_FC is not set
+# CONFIG_FUSION_SAS is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ARCNET is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_SMC91X is not set
+CONFIG_DM9000=y
+# CONFIG_SMC911X is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_DGRS is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+CONFIG_8139TOO=m
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+CONFIG_NETDEV_10000=y
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_CHELSIO_T3 is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+# CONFIG_MYRI10GE is not set
+# CONFIG_NETXEN_NIC is not set
+# CONFIG_MLX4_CORE is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET_MII is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+CONFIG_TOUCHSCREEN_UCB1400=m
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_PXA=y
+CONFIG_SERIAL_PXA_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_HW_RANDOM=m
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_HWMON is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# LED devices
+#
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+CONFIG_LEDS_CM_X270=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
+
+#
+# Graphics support
+#
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+CONFIG_FB_PXA=y
+# CONFIG_FB_PXA_PARAMETERS is not set
+CONFIG_FB_MBX=m
+# CONFIG_FB_VIRTUAL is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+
+#
+# Sound
+#
+CONFIG_SOUND=m
+
+#
+# Advanced Linux Sound Architecture
+#
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+
+#
+# Generic devices
+#
+CONFIG_SND_AC97_CODEC=m
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+
+#
+# PCI devices
+#
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_HDA_INTEL is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+# CONFIG_SND_AC97_POWER_SAVE is not set
+
+#
+# ALSA ARM devices
+#
+CONFIG_SND_PXA2XX_PCM=m
+CONFIG_SND_PXA2XX_AC97=m
+
+#
+# USB devices
+#
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_CAIAQ is not set
+
+#
+# System on Chip audio support
+#
+# CONFIG_SND_SOC is not set
+
+#
+# Open Sound System
+#
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=m
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_PERSIST is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+CONFIG_MMC=m
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=m
+CONFIG_MMC_BLOCK_BOUNCE=y
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_PXA=m
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_TIFM_SD is not set
+
+#
+# Real Time Clock
+#
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+CONFIG_RTC_DRV_V3020=y
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_SA1100=y
+
+#
+# DMA Engine support
+#
+# CONFIG_DMA_ENGINE is not set
+
+#
+# DMA Clients
+#
+
+#
+# DMA Devices
+#
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=y
+# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Distributed Lock Manager
+#
+# CONFIG_DLM is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index a2dd930d11ef..e5747547b44c 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -279,6 +279,25 @@ static void __devinit pci_fixup_cy82c693(struct pci_dev *dev)
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
 
+static void __init pci_fixup_it8152(struct pci_dev *dev)
+{
+        int i;
+        /* fixup for ITE 8152 devices */
+        /* FIXME: add defines for class 0x68000 and 0x80103 */
+        if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST ||
+            dev->class == 0x68000 ||
+            dev->class == 0x80103) {
+                for (i = 0; i < PCI_NUM_RESOURCES; i++) {
+                        dev->resource[i].start = 0;
+                        dev->resource[i].end   = 0;
+                        dev->resource[i].flags = 0;
+                }
+        }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);
+
+
+
 void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
 {
         if (debug_pci)
@@ -292,9 +311,12 @@ void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
  */
 static inline int pdev_bad_for_parity(struct pci_dev *dev)
 {
-        return (dev->vendor == PCI_VENDOR_ID_INTERG &&
-                (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
-                 dev->device == PCI_DEVICE_ID_INTERG_2010));
+        return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
+                 (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
+                  dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
+                (dev->vendor == PCI_VENDOR_ID_ITE &&
+                 dev->device == PCI_DEVICE_ID_ITE_8152));
+
 }
 
 /*
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 5ebec6d88b51..656d49661a29 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -1,6 +1,24 @@
 if ARCH_PXA
 
-menu "Intel PXA2xx Implementations"
+menu "Intel PXA2xx/PXA3xx Implementations"
+
+if PXA3xx
+
+menu "Supported PXA3xx Processor Variants"
+
+config CPU_PXA300
+        bool "PXA300 (codename Monahans-L)"
+
+config CPU_PXA310
+        bool "PXA310 (codename Monahans-LV)"
+        select CPU_PXA300
+
+config CPU_PXA320
+        bool "PXA320 (codename Monahans-P)"
+
+endmenu
+
+endif
 
 choice
         prompt "Select target board"
@@ -41,6 +59,15 @@ config MACH_EM_X270
         bool "CompuLab EM-x270 platform"
         select PXA27x
 
+config MACH_ZYLONITE
+        bool "PXA3xx Development Platform"
+        select PXA3xx
+
+config MACH_ARMCORE
+        bool "CompuLab CM-X270 modules"
+        select PXA27x
+        select IWMMXT
+
 endchoice
 
 if PXA_SHARPSL
@@ -130,6 +157,11 @@ config PXA27x
         help
           Select code specific to PXA27x variants
 
+config PXA3xx
+        bool
+        help
+          Select code specific to PXA3xx variants
+
 config PXA_SHARP_C7xx
         bool
         select PXA_SSP
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 7d6ab5c59ab9..4263527e5123 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -3,36 +3,51 @@
 #
 
 # Common support (must be linked before board specific support)
-obj-y += clock.o generic.o irq.o dma.o time.o
-obj-$(CONFIG_PXA25x) += pxa25x.o
-obj-$(CONFIG_PXA27x) += pxa27x.o
+obj-y                           += clock.o generic.o irq.o dma.o time.o
+obj-$(CONFIG_PXA25x)            += pxa25x.o
+obj-$(CONFIG_PXA27x)            += pxa27x.o
+obj-$(CONFIG_PXA3xx)            += pxa3xx.o mfp.o
+obj-$(CONFIG_CPU_PXA300)        += pxa300.o
+obj-$(CONFIG_CPU_PXA320)        += pxa320.o
 
 # Specific board support
-obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o
+obj-$(CONFIG_ARCH_LUBBOCK)      += lubbock.o
 obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o
-obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o
-obj-$(CONFIG_ARCH_PXA_IDP) += idp.o
+obj-$(CONFIG_MACH_MAINSTONE)    += mainstone.o
+obj-$(CONFIG_ARCH_PXA_IDP)      += idp.o
 obj-$(CONFIG_MACH_TRIZEPS4)     += trizeps4.o
 obj-$(CONFIG_PXA_SHARP_C7xx)    += corgi.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o corgi_pm.o
 obj-$(CONFIG_PXA_SHARP_Cxx00)   += spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o spitz_pm.o
 obj-$(CONFIG_MACH_AKITA)        += akita-ioexp.o
 obj-$(CONFIG_MACH_POODLE)       += poodle.o corgi_ssp.o
-obj-$(CONFIG_MACH_TOSA)         += tosa.o
-obj-$(CONFIG_MACH_EM_X270) += em-x270.o
+obj-$(CONFIG_MACH_TOSA)         += tosa.o
+obj-$(CONFIG_MACH_EM_X270)      += em-x270.o
+
+ifeq ($(CONFIG_MACH_ZYLONITE),y)
+  obj-y                         += zylonite.o
+  obj-$(CONFIG_CPU_PXA300)      += zylonite_pxa300.o
+  obj-$(CONFIG_CPU_PXA320)      += zylonite_pxa320.o
+endif
+
+obj-$(CONFIG_MACH_ARMCORE)      += cm-x270.o
 
 # Support for blinky lights
 led-y := leds.o
-led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o
-led-$(CONFIG_MACH_MAINSTONE) += leds-mainstone.o
-led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o
-led-$(CONFIG_MACH_TRIZEPS4) += leds-trizeps4.o
+led-$(CONFIG_ARCH_LUBBOCK)      += leds-lubbock.o
+led-$(CONFIG_MACH_MAINSTONE)    += leds-mainstone.o
+led-$(CONFIG_ARCH_PXA_IDP)      += leds-idp.o
+led-$(CONFIG_MACH_TRIZEPS4)     += leds-trizeps4.o
 
-obj-$(CONFIG_LEDS) += $(led-y)
+obj-$(CONFIG_LEDS)              += $(led-y)
 
 # Misc features
-obj-$(CONFIG_PM) += pm.o sleep.o
-obj-$(CONFIG_PXA_SSP) += ssp.o
+obj-$(CONFIG_PM)                += pm.o sleep.o
+obj-$(CONFIG_PXA_SSP)           += ssp.o
 
 ifeq ($(CONFIG_PXA27x),y)
-obj-$(CONFIG_PM) += standby.o
+obj-$(CONFIG_PM)                += standby.o
+endif
+
+ifeq ($(CONFIG_PCI),y)
+obj-$(CONFIG_MACH_ARMCORE) += cm-x270-pci.o
 endif
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index 34a31caa6f9d..83ef5ecaf432 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -9,19 +9,15 @@
 #include <linux/string.h>
 #include <linux/clk.h>
 #include <linux/spinlock.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
 
 #include <asm/arch/pxa-regs.h>
 #include <asm/hardware.h>
 
-struct clk {
-        struct list_head        node;
-        unsigned long           rate;
-        struct module           *owner;
-        const char              *name;
-        unsigned int            enabled;
-        void                    (*enable)(void);
-        void                    (*disable)(void);
-};
+#include "devices.h"
+#include "generic.h"
+#include "clock.h"
 
 static LIST_HEAD(clocks);
 static DEFINE_MUTEX(clocks_mutex);
@@ -33,7 +29,8 @@ struct clk *clk_get(struct device *dev, const char *id)
 
         mutex_lock(&clocks_mutex);
         list_for_each_entry(p, &clocks, node) {
-                if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
+                if (strcmp(id, p->name) == 0 &&
+                    (p->dev == NULL || p->dev == dev)) {
                         clk = p;
                         break;
                 }
@@ -46,7 +43,6 @@ EXPORT_SYMBOL(clk_get);
 
 void clk_put(struct clk *clk)
 {
-        module_put(clk->owner);
 }
 EXPORT_SYMBOL(clk_put);
 
@@ -56,8 +52,12 @@ int clk_enable(struct clk *clk)
 
         spin_lock_irqsave(&clocks_lock, flags);
         if (clk->enabled++ == 0)
-                clk->enable();
+                clk->ops->enable(clk);
         spin_unlock_irqrestore(&clocks_lock, flags);
+
+        if (clk->delay)
+                udelay(clk->delay);
+
         return 0;
 }
 EXPORT_SYMBOL(clk_enable);
@@ -70,54 +70,75 @@ void clk_disable(struct clk *clk)
 
         spin_lock_irqsave(&clocks_lock, flags);
         if (--clk->enabled == 0)
-                clk->disable();
+                clk->ops->disable(clk);
         spin_unlock_irqrestore(&clocks_lock, flags);
 }
 EXPORT_SYMBOL(clk_disable);
 
 unsigned long clk_get_rate(struct clk *clk)
 {
-        return clk->rate;
+        unsigned long rate;
+
+        rate = clk->rate;
+        if (clk->ops->getrate)
+                rate = clk->ops->getrate(clk);
+
+        return rate;
 }
 EXPORT_SYMBOL(clk_get_rate);
 
 
-static void clk_gpio27_enable(void)
+static void clk_gpio27_enable(struct clk *clk)
 {
         pxa_gpio_mode(GPIO11_3_6MHz_MD);
 }
 
-static void clk_gpio27_disable(void)
+static void clk_gpio27_disable(struct clk *clk)
 {
 }
 
-static struct clk clk_gpio27 = {
-        .name           = "GPIO27_CLK",
-        .rate           = 3686400,
+static const struct clkops clk_gpio27_ops = {
         .enable         = clk_gpio27_enable,
         .disable        = clk_gpio27_disable,
 };
 
-int clk_register(struct clk *clk)
+
+void clk_cken_enable(struct clk *clk)
 {
-        mutex_lock(&clocks_mutex);
-        list_add(&clk->node, &clocks);
-        mutex_unlock(&clocks_mutex);
-        return 0;
+        CKEN |= 1 << clk->cken;
 }
-EXPORT_SYMBOL(clk_register);
 
-void clk_unregister(struct clk *clk)
+void clk_cken_disable(struct clk *clk)
 {
+        CKEN &= ~(1 << clk->cken);
+}
+
+const struct clkops clk_cken_ops = {
+        .enable         = clk_cken_enable,
+        .disable        = clk_cken_disable,
+};
+
+static struct clk common_clks[] = {
+        {
+                .name           = "GPIO27_CLK",
+                .ops            = &clk_gpio27_ops,
+                .rate           = 3686400,
+        },
+};
+
+void clks_register(struct clk *clks, size_t num)
+{
+        int i;
+
         mutex_lock(&clocks_mutex);
-        list_del(&clk->node);
+        for (i = 0; i < num; i++)
+                list_add(&clks[i].node, &clocks);
         mutex_unlock(&clocks_mutex);
 }
-EXPORT_SYMBOL(clk_unregister);
 
 static int __init clk_init(void)
 {
-        clk_register(&clk_gpio27);
+        clks_register(common_clks, ARRAY_SIZE(common_clks));
         return 0;
 }
 arch_initcall(clk_init);
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
new file mode 100644
index 000000000000..bc6b77e1592e
--- /dev/null
+++ b/arch/arm/mach-pxa/clock.h
@@ -0,0 +1,43 @@
+struct clk;
+
+struct clkops {
+        void                    (*enable)(struct clk *);
+        void                    (*disable)(struct clk *);
+        unsigned long           (*getrate)(struct clk *);
+};
+
+struct clk {
+        struct list_head        node;
+        const char              *name;
+        struct device           *dev;
+        const struct clkops     *ops;
+        unsigned long           rate;
+        unsigned int            cken;
+        unsigned int            delay;
+        unsigned int            enabled;
+};
+
+#define INIT_CKEN(_name, _cken, _rate, _delay, _dev)    \
+        {                                               \
+                .name   = _name,                        \
+                .dev    = _dev,                         \
+                .ops    = &clk_cken_ops,                \
+                .rate   = _rate,                        \
+                .cken   = CKEN_##_cken,                 \
+                .delay  = _delay,                       \
+        }
+
+#define INIT_CK(_name, _cken, _ops, _dev)               \
+        {                                               \
+                .name   = _name,                        \
+                .dev    = _dev,                         \
+                .ops    = _ops,                         \
+                .cken   = CKEN_##_cken,                 \
+        }
+
+extern const struct clkops clk_cken_ops;
+
+void clk_cken_enable(struct clk *clk);
+void clk_cken_disable(struct clk *clk);
+
+void clks_register(struct clk *clks, size_t num);
diff --git a/arch/arm/mach-pxa/cm-x270-pci.c b/arch/arm/mach-pxa/cm-x270-pci.c
new file mode 100644
index 000000000000..878d3b9b8633
--- /dev/null
+++ b/arch/arm/mach-pxa/cm-x270-pci.c
@@ -0,0 +1,218 @@
+/*
+ * linux/arch/arm/mach-pxa/cm-x270-pci.c
+ *
+ * PCI bios-type initialisation for PCI machines
+ *
+ * Bits taken from various places.
+ *
+ * Copyright (C) 2007 Compulab, Ltd.
+ * Mike Rapoport <mike@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+
+#include <asm/mach/pci.h>
+#include <asm/arch/cm-x270.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/mach-types.h>
+
+#include <asm/hardware/it8152.h>
+
+unsigned long it8152_base_address = CMX270_IT8152_VIRT;
+
+/*
+ * Only first 64MB of memory can be accessed via PCI.
+ * We use GFP_DMA to allocate safe buffers to do map/unmap.
+ * This is really ugly and we need a better way of specifying
+ * DMA-capable regions of memory.
+ */
+void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size,
+        unsigned long *zhole_size)
+{
+        unsigned int sz = SZ_64M >> PAGE_SHIFT;
+
+        printk(KERN_INFO "Adjusting zones for CM-x270\n");
+
+        /*
+         * Only adjust if > 64M on current system
+         */
+        if (node || (zone_size[0] <= sz))
+                return;
+
+        zone_size[1] = zone_size[0] - sz;
+        zone_size[0] = sz;
+        zhole_size[1] = zhole_size[0];
+        zhole_size[0] = 0;
+}
+
+static void cmx270_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
+{
+        /* clear our parent irq */
+        GEDR(GPIO_IT8152_IRQ) = GPIO_bit(GPIO_IT8152_IRQ);
+
+        it8152_irq_demux(irq, desc);
+}
+
+void __cmx270_pci_init_irq(void)
+{
+        it8152_init_irq();
+        pxa_gpio_mode(IRQ_TO_GPIO(GPIO_IT8152_IRQ));
+        set_irq_type(IRQ_GPIO(GPIO_IT8152_IRQ), IRQT_RISING);
+
+        set_irq_chained_handler(IRQ_GPIO(GPIO_IT8152_IRQ),
+                                cmx270_it8152_irq_demux);
+}
+
+#ifdef CONFIG_PM
+static unsigned long sleep_save_ite[10];
+
+void __cmx270_pci_suspend(void)
+{
+        /* save ITE state */
+        sleep_save_ite[0] = __raw_readl(IT8152_INTC_PDCNIMR);
+        sleep_save_ite[1] = __raw_readl(IT8152_INTC_LPCNIMR);
+        sleep_save_ite[2] = __raw_readl(IT8152_INTC_LPNIAR);
+
+        /* Clear ITE IRQ's */
+        __raw_writel((0), IT8152_INTC_PDCNIRR);
+        __raw_writel((0), IT8152_INTC_LPCNIRR);
+}
+
+void __cmx270_pci_resume(void)
+{
+        /* restore IT8152 state */
+        __raw_writel((sleep_save_ite[0]), IT8152_INTC_PDCNIMR);
+        __raw_writel((sleep_save_ite[1]), IT8152_INTC_LPCNIMR);
+        __raw_writel((sleep_save_ite[2]), IT8152_INTC_LPNIAR);
+}
+#else
+void cmx270_pci_suspend(void) {}
+void cmx270_pci_resume(void) {}
+#endif
+
+/* PCI IRQ mapping*/
+static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int irq;
+
+        printk(KERN_DEBUG "===> %s: %s slot=%x, pin=%x\n", __FUNCTION__,
+               pci_name(dev), slot, pin);
+
+        irq = it8152_pci_map_irq(dev, slot, pin);
+        if (irq)
+                return irq;
+
+        /*
+          Here comes the ugly part. The routing is baseboard specific,
+          but defining a platform for each possible base of CM-x270 is
+          unrealistic. Here we keep mapping for ATXBase and SB-x270.
+        */
+        /* ATXBASE PCI slot */
+        if (slot == 7)
+                return IT8152_PCI_INTA;
+
+        /* ATXBase/SB-x270 CardBus */
+        if (slot == 8 || slot == 0)
+                return IT8152_PCI_INTB;
+
+        /* ATXBase Ethernet */
+        if (slot == 9)
+                return IT8152_PCI_INTA;
+
+        /* SB-x270 Ethernet */
+        if (slot == 16)
+                return IT8152_PCI_INTA;
+
+        /* PC104+ interrupt routing */
+        if ((slot == 17) || (slot == 19))
+                return IT8152_PCI_INTA;
+        if ((slot == 18) || (slot == 20))
+                return IT8152_PCI_INTB;
+
+        return(0);
+}
+
+static struct pci_bus * __init
+cmx270_pci_scan_bus(int nr, struct pci_sys_data *sys)
+{
+        printk(KERN_INFO "Initializing CM-X270 PCI subsystem\n");
+
+        __raw_writel(0x800, IT8152_PCI_CFG_ADDR);
+        if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) {
+                printk(KERN_INFO "PCI Bridge found.\n");
+
+                /* set PCI I/O base at 0 */
+                writel(0x848, IT8152_PCI_CFG_ADDR);
+                writel(0, IT8152_PCI_CFG_DATA);
+
+                /* set PCI memory base at 0 */
+                writel(0x840, IT8152_PCI_CFG_ADDR);
+                writel(0, IT8152_PCI_CFG_DATA);
+
+                writel(0x20, IT8152_GPIO_GPDR);
+
+                /* CardBus Controller on ATXbase baseboard */
+                writel(0x4000, IT8152_PCI_CFG_ADDR);
+                if (readl(IT8152_PCI_CFG_DATA) == 0xAC51104C) {
+                        printk(KERN_INFO "CardBus Bridge found.\n");
+
+                        /* Configure socket 0 */
+                        writel(0x408C, IT8152_PCI_CFG_ADDR);
+                        writel(0x1022, IT8152_PCI_CFG_DATA);
+
+                        writel(0x4080, IT8152_PCI_CFG_ADDR);
+                        writel(0x3844d060, IT8152_PCI_CFG_DATA);
+
+                        writel(0x4090, IT8152_PCI_CFG_ADDR);
+                        writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) |
+                                0x60440000),
+                               IT8152_PCI_CFG_DATA);
+
+                        writel(0x4018, IT8152_PCI_CFG_ADDR);
+                        writel(0xb0000000, IT8152_PCI_CFG_DATA);
+
+                        /* Configure socket 1 */
+                        writel(0x418C, IT8152_PCI_CFG_ADDR);
+                        writel(0x1022, IT8152_PCI_CFG_DATA);
+
+                        writel(0x4180, IT8152_PCI_CFG_ADDR);
+                        writel(0x3844d060, IT8152_PCI_CFG_DATA);
+
+                        writel(0x4190, IT8152_PCI_CFG_ADDR);
+                        writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) |
+                                0x60440000),
+                               IT8152_PCI_CFG_DATA);
+
+                        writel(0x4118, IT8152_PCI_CFG_ADDR);
+                        writel(0xb0000000, IT8152_PCI_CFG_DATA);
+                }
+        }
+        return it8152_pci_scan_bus(nr, sys);
+}
+
+static struct hw_pci cmx270_pci __initdata = {
+        .swizzle        = pci_std_swizzle,
+        .map_irq        = cmx270_pci_map_irq,
+        .nr_controllers = 1,
+        .setup          = it8152_pci_setup,
+        .scan           = cmx270_pci_scan_bus,
+};
+
+static int __init cmx270_init_pci(void)
+{
+        if (machine_is_armcore())
+                pci_common_init(&cmx270_pci);
+
+        return 0;
+}
+
+subsys_initcall(cmx270_init_pci);
diff --git a/arch/arm/mach-pxa/cm-x270-pci.h b/arch/arm/mach-pxa/cm-x270-pci.h
new file mode 100644
index 000000000000..ffe37b66f9a0
--- /dev/null
+++ b/arch/arm/mach-pxa/cm-x270-pci.h
@@ -0,0 +1,13 @@
+extern void __cmx270_pci_init_irq(void);
+extern void __cmx270_pci_suspend(void);
+extern void __cmx270_pci_resume(void);
+
+#ifdef CONFIG_PCI
+#define cmx270_pci_init_irq __cmx270_pci_init_irq
+#define cmx270_pci_suspend __cmx270_pci_suspend
+#define cmx270_pci_resume __cmx270_pci_resume
+#else
+#define cmx270_pci_init_irq() do {} while (0)
+#define cmx270_pci_suspend() do {} while (0)
+#define cmx270_pci_resume() do {} while (0)
+#endif
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
new file mode 100644
index 000000000000..177664ccb2e2
--- /dev/null
+++ b/arch/arm/mach-pxa/cm-x270.c
@@ -0,0 +1,645 @@
+/*
+ * linux/arch/arm/mach-pxa/cm-x270.c
+ *
+ * Copyright (C) 2007 CompuLab, Ltd.
+ * Mike Rapoport <mike@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/types.h>
+#include <linux/pm.h>
+#include <linux/fb.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+
+#include <linux/dm9000.h>
+#include <linux/rtc-v3020.h>
+#include <linux/serial_8250.h>
+
+#include <video/mbxfb.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <asm/mach/map.h>
+
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxafb.h>
+#include <asm/arch/ohci.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/bitfield.h>
+#include <asm/arch/cm-x270.h>
+
+#include <asm/hardware/it8152.h>
+
+#include "generic.h"
+#include "cm-x270-pci.h"
+
+#define RTC_PHYS_BASE           (PXA_CS1_PHYS + (5 << 22))
+#define DM9000_PHYS_BASE        (PXA_CS1_PHYS + (6 << 22))
+
+static struct resource cmx270_dm9k_resource[] = {
+        [0] = {
+                .start = DM9000_PHYS_BASE,
+                .end   = DM9000_PHYS_BASE + 4,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DM9000_PHYS_BASE + 8,
+                .end   = DM9000_PHYS_BASE + 8 + 500,
+                .flags = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start = CMX270_ETHIRQ,
+                .end   = CMX270_ETHIRQ,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+/* for the moment we limit ourselves to 32bit IO until some
+ * better IO routines can be written and tested
+ */
+static struct dm9000_plat_data cmx270_dm9k_platdata = {
+        .flags          = DM9000_PLATF_32BITONLY,
+};
+
+/* Ethernet device */
+static struct platform_device cmx270_device_dm9k = {
+        .name           = "dm9000",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(cmx270_dm9k_resource),
+        .resource       = cmx270_dm9k_resource,
+        .dev            = {
+                .platform_data = &cmx270_dm9k_platdata,
+        }
+};
+
+/* audio device */
+static struct platform_device cmx270_audio_device = {
+        .name           = "pxa2xx-ac97",
+        .id             = -1,
+};
+
+/* touchscreen controller */
+static struct platform_device cmx270_ts_device = {
+        .name           = "ucb1400_ts",
+        .id             = -1,
+};
+
+/* RTC */
+static struct resource cmx270_v3020_resource[] = {
+        [0] = {
+                .start = RTC_PHYS_BASE,
+                .end   = RTC_PHYS_BASE + 4,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+struct v3020_platform_data cmx270_v3020_pdata = {
+        .leftshift = 16,
+};
+
+static struct platform_device cmx270_rtc_device = {
+        .name           = "v3020",
+        .num_resources  = ARRAY_SIZE(cmx270_v3020_resource),
+        .resource       = cmx270_v3020_resource,
+        .id             = -1,
+        .dev            = {
+                .platform_data = &cmx270_v3020_pdata,
+        }
+};
+
+/*
+ * CM-X270 LEDs
+ */
+static struct platform_device cmx270_led_device = {
+        .name           = "cm-x270-led",
+        .id             = -1,
+};
+
+/* 2700G graphics */
+static u64 fb_dma_mask = ~(u64)0;
+
+static struct resource cmx270_2700G_resource[] = {
+        /* frame buffer memory including ODFB and External SDRAM */
+        [0] = {
+                .start = MARATHON_PHYS,
+                .end   = MARATHON_PHYS + 0x02000000,
+                .flags = IORESOURCE_MEM,
+        },
+        /* Marathon registers */
+        [1] = {
+                .start = MARATHON_PHYS + 0x03fe0000,
+                .end   = MARATHON_PHYS + 0x03ffffff,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+static unsigned long save_lcd_regs[10];
+
+static int cmx270_marathon_probe(struct fb_info *fb)
+{
+        /* save PXA-270 pin settings before enabling 2700G */
+        save_lcd_regs[0] = GPDR1;
+        save_lcd_regs[1] = GPDR2;
+        save_lcd_regs[2] = GAFR1_U;
+        save_lcd_regs[3] = GAFR2_L;
+        save_lcd_regs[4] = GAFR2_U;
+
+        /* Disable PXA-270 on-chip controller driving pins */
+        GPDR1 &= ~(0xfc000000);
+        GPDR2 &= ~(0x00c03fff);
+        GAFR1_U &= ~(0xfff00000);
+        GAFR2_L &= ~(0x0fffffff);
+        GAFR2_U &= ~(0x0000f000);
+        return 0;
+}
+
+static int cmx270_marathon_remove(struct fb_info *fb)
+{
+        GPDR1 =   save_lcd_regs[0];
+        GPDR2 =   save_lcd_regs[1];
+        GAFR1_U = save_lcd_regs[2];
+        GAFR2_L = save_lcd_regs[3];
+        GAFR2_U = save_lcd_regs[4];
+        return 0;
+}
+
+static struct mbxfb_platform_data cmx270_2700G_data = {
+        .xres = {
+                .min = 240,
+                .max = 1200,
+                .defval = 640,
+        },
+        .yres = {
+                .min = 240,
+                .max = 1200,
+                .defval = 480,
+        },
+        .bpp = {
+                .min = 16,
+                .max = 32,
+                .defval = 16,
+        },
+        .memsize = 8*1024*1024,
+        .probe = cmx270_marathon_probe,
+        .remove = cmx270_marathon_remove,
+};
+
+static struct platform_device cmx270_2700G = {
+        .name           = "mbx-fb",
+        .dev            = {
+                .platform_data  = &cmx270_2700G_data,
+                .dma_mask       = &fb_dma_mask,
+                .coherent_dma_mask = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(cmx270_2700G_resource),
+        .resource       = cmx270_2700G_resource,
+        .id             = -1,
+};
+
+static u64 ata_dma_mask = ~(u64)0;
+
+static struct platform_device cmx270_ata = {
+        .name = "pata_cm_x270",
+        .id = -1,
+        .dev            = {
+                .dma_mask       = &ata_dma_mask,
+                .coherent_dma_mask = 0xffffffff,
+        },
+};
+
+/* platform devices */
+static struct platform_device *platform_devices[] __initdata = {
+        &cmx270_device_dm9k,
+        &cmx270_audio_device,
+        &cmx270_rtc_device,
+        &cmx270_2700G,
+        &cmx270_led_device,
+        &cmx270_ts_device,
+        &cmx270_ata,
+};
+
+/* Map PCI companion and IDE/General Purpose CS statically */
+static struct map_desc cmx270_io_desc[] __initdata = {
+        [0] = { /* IDE/general purpose space */
+                .virtual        = CMX270_IDE104_VIRT,
+                .pfn            = __phys_to_pfn(CMX270_IDE104_PHYS),
+                .length         = SZ_64M - SZ_8M,
+                .type           = MT_DEVICE
+        },
+        [1] = { /* PCI bridge */
+                .virtual        = CMX270_IT8152_VIRT,
+                .pfn            = __phys_to_pfn(CMX270_IT8152_PHYS),
+                .length         = SZ_64M,
+                .type           = MT_DEVICE
+        },
+};
+
+/*
+  Display definitions
+  keep these for backwards compatibility, although symbolic names (as
+  e.g. in lpd270.c) looks better
+*/
+#define MTYPE_STN320x240        0
+#define MTYPE_TFT640x480        1
+#define MTYPE_CRT640x480        2
+#define MTYPE_CRT800x600        3
+#define MTYPE_TFT320x240        6
+#define MTYPE_STN640x480        7
+
+static struct pxafb_mode_info generic_stn_320x240_mode = {
+        .pixclock       = 76923,
+        .bpp            = 8,
+        .xres           = 320,
+        .yres           = 240,
+        .hsync_len      = 3,
+        .vsync_len      = 2,
+        .left_margin    = 3,
+        .upper_margin   = 0,
+        .right_margin   = 3,
+        .lower_margin   = 0,
+        .sync           = (FB_SYNC_HOR_HIGH_ACT |
+                           FB_SYNC_VERT_HIGH_ACT),
+        .cmap_greyscale = 0,
+};
+
+static struct pxafb_mach_info generic_stn_320x240 = {
+        .modes          = &generic_stn_320x240_mode,
+        .num_modes      = 1,
+        .lccr0          = 0,
+        .lccr3          = (LCCR3_PixClkDiv(0x03) |
+                           LCCR3_Acb(0xff) |
+                           LCCR3_PCP),
+        .cmap_inverse   = 0,
+        .cmap_static    = 0,
+};
+
+static struct pxafb_mode_info generic_tft_640x480_mode = {
+        .pixclock       = 38461,
+        .bpp            = 8,
+        .xres           = 640,
+        .yres           = 480,
+        .hsync_len      = 60,
+        .vsync_len      = 2,
+        .left_margin    = 70,
+        .upper_margin   = 10,
+        .right_margin   = 70,
+        .lower_margin   = 5,
+        .sync           = 0,
+        .cmap_greyscale = 0,
+};
+
+static struct pxafb_mach_info generic_tft_640x480 = {
+        .modes          = &generic_tft_640x480_mode,
+        .num_modes      = 1,
+        .lccr0          = (LCCR0_PAS),
+        .lccr3          = (LCCR3_PixClkDiv(0x01) |
+                           LCCR3_Acb(0xff) |
+                           LCCR3_PCP),
+        .cmap_inverse   = 0,
+        .cmap_static    = 0,
+};
+
+static struct pxafb_mode_info generic_crt_640x480_mode = {
+        .pixclock       = 38461,
+        .bpp            = 8,
+        .xres           = 640,
+        .yres           = 480,
+        .hsync_len      = 63,
+        .vsync_len      = 2,
+        .left_margin    = 81,
+        .upper_margin   = 33,
+        .right_margin   = 16,
+        .lower_margin   = 10,
+        .sync           = (FB_SYNC_HOR_HIGH_ACT |
+                           FB_SYNC_VERT_HIGH_ACT),
+        .cmap_greyscale = 0,
+};
+
+static struct pxafb_mach_info generic_crt_640x480 = {
+        .modes          = &generic_crt_640x480_mode,
+        .num_modes      = 1,
+        .lccr0          = (LCCR0_PAS),
+        .lccr3          = (LCCR3_PixClkDiv(0x01) |
+                           LCCR3_Acb(0xff)),
+        .cmap_inverse   = 0,
+        .cmap_static    = 0,
+};
+
+static struct pxafb_mode_info generic_crt_800x600_mode = {
+        .pixclock       = 28846,
+        .bpp            = 8,
+        .xres           = 800,
+        .yres           = 600,
+        .hsync_len      = 63,
+        .vsync_len      = 2,
+        .left_margin    = 26,
+        .upper_margin   = 21,
+        .right_margin   = 26,
+        .lower_margin   = 11,
+        .sync           = (FB_SYNC_HOR_HIGH_ACT |
+                           FB_SYNC_VERT_HIGH_ACT),
+        .cmap_greyscale = 0,
+};
+
+static struct pxafb_mach_info generic_crt_800x600 = {
+        .modes          = &generic_crt_800x600_mode,
+        .num_modes      = 1,
+        .lccr0          = (LCCR0_PAS),
+        .lccr3          = (LCCR3_PixClkDiv(0x02) |
+                           LCCR3_Acb(0xff)),
+        .cmap_inverse   = 0,
+        .cmap_static    = 0,
+};
+
+static struct pxafb_mode_info generic_tft_320x240_mode = {
+        .pixclock       = 134615,
+        .bpp            = 16,
+        .xres           = 320,
+        .yres           = 240,
+        .hsync_len      = 63,
+        .vsync_len      = 7,
+        .left_margin    = 75,
+        .upper_margin   = 0,
+        .right_margin   = 15,
+        .lower_margin   = 15,
+        .sync           = 0,
+        .cmap_greyscale = 0,
+};
+
+static struct pxafb_mach_info generic_tft_320x240 = {
+        .modes          = &generic_tft_320x240_mode,
+        .num_modes      = 1,
+        .lccr0          = (LCCR0_PAS),
+        .lccr3          = (LCCR3_PixClkDiv(0x06) |
+                           LCCR3_Acb(0xff) |
+                           LCCR3_PCP),
+        .cmap_inverse   = 0,
+        .cmap_static    = 0,
+};
+
+static struct pxafb_mode_info generic_stn_640x480_mode = {
+        .pixclock       = 57692,
+        .bpp            = 8,
+        .xres           = 640,
+        .yres           = 480,
+        .hsync_len      = 4,
+        .vsync_len      = 2,
+        .left_margin    = 10,
+        .upper_margin   = 5,
+        .right_margin   = 10,
+        .lower_margin   = 5,
+        .sync           = (FB_SYNC_HOR_HIGH_ACT |
+                           FB_SYNC_VERT_HIGH_ACT),
+        .cmap_greyscale = 0,
+};
+
+static struct pxafb_mach_info generic_stn_640x480 = {
+        .modes          = &generic_stn_640x480_mode,
+        .num_modes      = 1,
+        .lccr0          = 0,
+        .lccr3          = (LCCR3_PixClkDiv(0x02) |
+                           LCCR3_Acb(0xff)),
+        .cmap_inverse   = 0,
+        .cmap_static    = 0,
+};
+
+static struct pxafb_mach_info *cmx270_display = &generic_crt_640x480;
+
+static int __init cmx270_set_display(char *str)
+{
+        int disp_type = simple_strtol(str, NULL, 0);
+        switch (disp_type) {
+        case MTYPE_STN320x240:
+                cmx270_display = &generic_stn_320x240;
+                break;
+        case MTYPE_TFT640x480:
+                cmx270_display = &generic_tft_640x480;
+                break;
+        case MTYPE_CRT640x480:
+                cmx270_display = &generic_crt_640x480;
+                break;
+        case MTYPE_CRT800x600:
+                cmx270_display = &generic_crt_800x600;
+                break;
+        case MTYPE_TFT320x240:
+                cmx270_display = &generic_tft_320x240;
+                break;
+        case MTYPE_STN640x480:
+                cmx270_display = &generic_stn_640x480;
+                break;
+        default: /* fallback to CRT 640x480 */
+                cmx270_display = &generic_crt_640x480;
+                break;
+        }
+        return 1;
+}
+
+/*
+   This should be done really early to get proper configuration for
+   frame buffer.
+   Indeed, pxafb parameters can be used istead, but CM-X270 bootloader
+   has limitied line length for kernel command line, and also it will
+   break compatibitlty with proprietary releases already in field.
+*/
+__setup("monitor=", cmx270_set_display);
+
+/* PXA27x OHCI controller setup */
+static int cmx270_ohci_init(struct device *dev)
+{
+        /* Set the Power Control Polarity Low */
+        UHCHR = (UHCHR | UHCHR_PCPL) &
+                ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+
+        return 0;
+}
+
+static struct pxaohci_platform_data cmx270_ohci_platform_data = {
+        .port_mode      = PMM_PERPORT_MODE,
+        .init           = cmx270_ohci_init,
+};
+
+
+static int cmx270_mci_init(struct device *dev,
+                           irq_handler_t cmx270_detect_int,
+                           void *data)
+{
+        int err;
+
+        /*
+         * setup GPIO for PXA27x MMC controller
+         */
+        pxa_gpio_mode(GPIO32_MMCCLK_MD);
+        pxa_gpio_mode(GPIO112_MMCCMD_MD);
+        pxa_gpio_mode(GPIO92_MMCDAT0_MD);
+        pxa_gpio_mode(GPIO109_MMCDAT1_MD);
+        pxa_gpio_mode(GPIO110_MMCDAT2_MD);
+        pxa_gpio_mode(GPIO111_MMCDAT3_MD);
+
+        /* SB-X270 uses GPIO105 as SD power enable */
+        pxa_gpio_mode(105 | GPIO_OUT);
+
+        /* card detect IRQ on GPIO 83 */
+        pxa_gpio_mode(IRQ_TO_GPIO(CMX270_MMC_IRQ));
+        set_irq_type(CMX270_MMC_IRQ, IRQT_FALLING);
+
+        err = request_irq(CMX270_MMC_IRQ, cmx270_detect_int,
+                          IRQF_DISABLED | IRQF_TRIGGER_FALLING,
+                          "MMC card detect", data);
+        if (err) {
+                printk(KERN_ERR "cmx270_mci_init: MMC/SD: can't"
+                       " request MMC card detect IRQ\n");
+                return -1;
+        }
+
+        return 0;
+}
+
+static void cmx270_mci_setpower(struct device *dev, unsigned int vdd)
+{
+        struct pxamci_platform_data *p_d = dev->platform_data;
+
+        if ((1 << vdd) & p_d->ocr_mask) {
+                printk(KERN_DEBUG "%s: on\n", __FUNCTION__);
+                GPCR(105) = GPIO_bit(105);
+        } else {
+                GPSR(105) = GPIO_bit(105);
+                printk(KERN_DEBUG "%s: off\n", __FUNCTION__);
+        }
+}
+
+static void cmx270_mci_exit(struct device *dev, void *data)
+{
+        free_irq(CMX270_MMC_IRQ, data);
+}
+
+static struct pxamci_platform_data cmx270_mci_platform_data = {
+        .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
+        .init           = cmx270_mci_init,
+        .setpower       = cmx270_mci_setpower,
+        .exit           = cmx270_mci_exit,
+};
+
+#ifdef CONFIG_PM
+static unsigned long sleep_save_msc[10];
+
+static int cmx270_suspend(struct sys_device *dev, pm_message_t state)
+{
+        cmx270_pci_suspend();
+
+        /* save MSC registers */
+        sleep_save_msc[0] = MSC0;
+        sleep_save_msc[1] = MSC1;
+        sleep_save_msc[2] = MSC2;
+
+        /* setup power saving mode registers */
+        PCFR = 0x0;
+        PSLR = 0xff400000;
+        PMCR  = 0x00000005;
+        PWER  = 0x80000000;
+        PFER  = 0x00000000;
+        PRER  = 0x00000000;
+        PGSR0 = 0xC0018800;
+        PGSR1 = 0x004F0002;
+        PGSR2 = 0x6021C000;
+        PGSR3 = 0x00020000;
+
+        return 0;
+}
+
+static int cmx270_resume(struct sys_device *dev)
+{
+        cmx270_pci_resume();
+
+        /* restore MSC registers */
+        MSC0 = sleep_save_msc[0];
+        MSC1 = sleep_save_msc[1];
+        MSC2 = sleep_save_msc[2];
+
+        return 0;
+}
+
+static struct sysdev_class cmx270_pm_sysclass = {
+        set_kset_name("pm"),
+        .resume = cmx270_resume,
+        .suspend = cmx270_suspend,
+};
+
+static struct sys_device cmx270_pm_device = {
+        .cls = &cmx270_pm_sysclass,
+};
+
+static int __init cmx270_pm_init(void)
+{
+        int error;
+        error = sysdev_class_register(&cmx270_pm_sysclass);
+        if (error == 0)
+                error = sysdev_register(&cmx270_pm_device);
+        return error;
+}
+#else
+static int __init cmx270_pm_init(void) { return 0; }
+#endif
+
+static void __init cmx270_init(void)
+{
+        cmx270_pm_init();
+
+        set_pxa_fb_info(cmx270_display);
+
+        /* register CM-X270 platform devices */
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+
+        /* set MCI and OHCI platform parameters */
+        pxa_set_mci_info(&cmx270_mci_platform_data);
+        pxa_set_ohci_info(&cmx270_ohci_platform_data);
+
+        /* This enables the STUART */
+        pxa_gpio_mode(GPIO46_STRXD_MD);
+        pxa_gpio_mode(GPIO47_STTXD_MD);
+
+        /* This enables the BTUART  */
+        pxa_gpio_mode(GPIO42_BTRXD_MD);
+        pxa_gpio_mode(GPIO43_BTTXD_MD);
+        pxa_gpio_mode(GPIO44_BTCTS_MD);
+        pxa_gpio_mode(GPIO45_BTRTS_MD);
+}
+
+static void __init cmx270_init_irq(void)
+{
+        pxa27x_init_irq();
+
+
+        cmx270_pci_init_irq();
+
+        /* Setup interrupt for dm9000 */
+        pxa_gpio_mode(IRQ_TO_GPIO(CMX270_ETHIRQ));
+        set_irq_type(CMX270_ETHIRQ, IRQT_RISING);
+
+        /* Setup interrupt for 2700G */
+        pxa_gpio_mode(IRQ_TO_GPIO(CMX270_GFXIRQ));
+        set_irq_type(CMX270_GFXIRQ, IRQT_FALLING);
+}
+
+static void __init cmx270_map_io(void)
+{
+        pxa_map_io();
+        iotable_init(cmx270_io_desc, ARRAY_SIZE(cmx270_io_desc));
+}
+
+
+MACHINE_START(ARMCORE, "Compulab CM-x270")
+        .boot_params    = 0xa0000100,
+        .phys_io        = 0x40000000,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .map_io         = cmx270_map_io,
+        .init_irq       = cmx270_init_irq,
+        .timer          = &pxa_timer,
+        .init_machine   = cmx270_init,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index 636fdb1c049c..94c8d5cdd60a 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -9,3 +9,6 @@ extern struct platform_device pxa_device_i2c;
 extern struct platform_device pxa_device_i2s;
 extern struct platform_device pxa_device_ficp;
 extern struct platform_device pxa_device_rtc;
+
+extern struct platform_device pxa27x_device_i2c_power;
+extern struct platform_device pxa27x_device_ohci;
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 5510f6fdce55..1c34946ee16e 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -25,10 +25,6 @@
 #include <linux/pm.h>
 #include <linux/string.h>
 
-#include <linux/sched.h>
-#include <asm/cnt32_to_63.h>
-#include <asm/div64.h>
-
 #include <asm/hardware.h>
 #include <asm/irq.h>
 #include <asm/system.h>
@@ -47,66 +43,39 @@
 #include "generic.h"
 
 /*
- * This is the PXA2xx sched_clock implementation. This has a resolution
- * of at least 308ns and a maximum value that depends on the value of
- * CLOCK_TICK_RATE.
- *
- * The return value is guaranteed to be monotonic in that range as
- * long as there is always less than 582 seconds between successive
- * calls to this function.
+ * Get the clock frequency as reflected by CCCR and the turbo flag.
+ * We assume these values have been applied via a fcs.
+ * If info is not 0 we also display the current settings.
  */
-unsigned long long sched_clock(void)
+unsigned int get_clk_frequency_khz(int info)
 {
-        unsigned long long v = cnt32_to_63(OSCR);
-        /* Note: top bit ov v needs cleared unless multiplier is even. */
-
-#if     CLOCK_TICK_RATE == 3686400
-        /* 1E9 / 3686400 => 78125 / 288, max value = 32025597s (370 days). */
-        /* The <<1 is used to get rid of tick.hi top bit */
-        v *= 78125<<1;
-        do_div(v, 288<<1);
-#elif   CLOCK_TICK_RATE == 3250000
-        /* 1E9 / 3250000 => 4000 / 13, max value = 709490156s (8211 days) */
-        v *= 4000;
-        do_div(v, 13);
-#elif   CLOCK_TICK_RATE == 3249600
-        /* 1E9 / 3249600 => 625000 / 2031, max value = 4541295s (52 days) */
-        v *= 625000;
-        do_div(v, 2031);
-#else
-#warning "consider fixing sched_clock for your value of CLOCK_TICK_RATE"
-        /*
-         * 96-bit math to perform tick * NSEC_PER_SEC / CLOCK_TICK_RATE for
-         * any value of CLOCK_TICK_RATE. Max value is in the 80 thousand
-         * years range and truncation to unsigned long long limits it to
-         * sched_clock's max range of ~584 years.  This is nice but with
-         * higher computation cost.
-         */
-        {
-                union {
-                        unsigned long long val;
-                        struct { unsigned long lo, hi; };
-                } x;
-                unsigned long long y;
-
-                x.val = v;
-                x.hi &= 0x7fffffff;
-                y = (unsigned long long)x.lo * NSEC_PER_SEC;
-                x.lo = y;
-                y = (y >> 32) + (unsigned long long)x.hi * NSEC_PER_SEC;
-                x.hi = do_div(y, CLOCK_TICK_RATE);
-                do_div(x.val, CLOCK_TICK_RATE);
-                x.hi += y;
-                v = x.val;
-        }
-#endif
+        if (cpu_is_pxa21x() || cpu_is_pxa25x())
+                return pxa25x_get_clk_frequency_khz(info);
+        else if (cpu_is_pxa27x())
+                return pxa27x_get_clk_frequency_khz(info);
+        else
+                return pxa3xx_get_clk_frequency_khz(info);
+}
+EXPORT_SYMBOL(get_clk_frequency_khz);
 
-        return v;
+/*
+ * Return the current memory clock frequency in units of 10kHz
+ */
+unsigned int get_memclk_frequency_10khz(void)
+{
+        if (cpu_is_pxa21x() || cpu_is_pxa25x())
+                return pxa25x_get_memclk_frequency_10khz();
+        else if (cpu_is_pxa27x())
+                return pxa27x_get_memclk_frequency_10khz();
+        else
+                return pxa3xx_get_memclk_frequency_10khz();
 }
+EXPORT_SYMBOL(get_memclk_frequency_10khz);
 
 /*
  * Handy function to set GPIO alternate functions
  */
+int pxa_last_gpio;
 
 int pxa_gpio_mode(int gpio_mode)
 {
@@ -115,7 +84,7 @@ int pxa_gpio_mode(int gpio_mode)
         int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
         int gafr;
 
-        if (gpio > PXA_LAST_GPIO)
+        if (gpio > pxa_last_gpio)
                 return -EINVAL;
 
         local_irq_save(flags);
@@ -136,6 +105,44 @@ int pxa_gpio_mode(int gpio_mode)
 
 EXPORT_SYMBOL(pxa_gpio_mode);
 
+int gpio_direction_input(unsigned gpio)
+{
+        unsigned long flags;
+        u32 mask;
+
+        if (gpio > pxa_last_gpio)
+                return -EINVAL;
+
+        mask = GPIO_bit(gpio);
+        local_irq_save(flags);
+        GPDR(gpio) &= ~mask;
+        local_irq_restore(flags);
+
+        return 0;
+}
+EXPORT_SYMBOL(gpio_direction_input);
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+        unsigned long flags;
+        u32 mask;
+
+        if (gpio > pxa_last_gpio)
+                return -EINVAL;
+
+        mask = GPIO_bit(gpio);
+        local_irq_save(flags);
+        if (value)
+                GPSR(gpio) = mask;
+        else
+                GPCR(gpio) = mask;
+        GPDR(gpio) |= mask;
+        local_irq_restore(flags);
+
+        return 0;
+}
+EXPORT_SYMBOL(gpio_direction_output);
+
 /*
  * Return GPIO level
  */
@@ -159,7 +166,7 @@ EXPORT_SYMBOL(pxa_gpio_set_value);
 /*
  * Routine to safely enable or disable a clock in the CKEN
  */
-void pxa_set_cken(int clock, int enable)
+void __pxa_set_cken(int clock, int enable)
 {
         unsigned long flags;
         local_irq_save(flags);
@@ -172,7 +179,7 @@ void pxa_set_cken(int clock, int enable)
         local_irq_restore(flags);
 }
 
-EXPORT_SYMBOL(pxa_set_cken);
+EXPORT_SYMBOL(__pxa_set_cken);
 
 /*
  * Intel PXA2xx internal register mapping.
@@ -329,21 +336,80 @@ void __init set_pxa_fb_parent(struct device *parent_dev)
         pxa_device_fb.dev.parent = parent_dev;
 }
 
+static struct resource pxa_resource_ffuart[] = {
+        {
+                .start  = __PREG(FFUART),
+                .end    = __PREG(FFUART) + 35,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_FFUART,
+                .end    = IRQ_FFUART,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
 struct platform_device pxa_device_ffuart= {
         .name           = "pxa2xx-uart",
         .id             = 0,
+        .resource       = pxa_resource_ffuart,
+        .num_resources  = ARRAY_SIZE(pxa_resource_ffuart),
 };
+
+static struct resource pxa_resource_btuart[] = {
+        {
+                .start  = __PREG(BTUART),
+                .end    = __PREG(BTUART) + 35,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_BTUART,
+                .end    = IRQ_BTUART,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
 struct platform_device pxa_device_btuart = {
         .name           = "pxa2xx-uart",
         .id             = 1,
+        .resource       = pxa_resource_btuart,
+        .num_resources  = ARRAY_SIZE(pxa_resource_btuart),
 };
+
+static struct resource pxa_resource_stuart[] = {
+        {
+                .start  = __PREG(STUART),
+                .end    = __PREG(STUART) + 35,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_STUART,
+                .end    = IRQ_STUART,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
 struct platform_device pxa_device_stuart = {
         .name           = "pxa2xx-uart",
         .id             = 2,
+        .resource       = pxa_resource_stuart,
+        .num_resources  = ARRAY_SIZE(pxa_resource_stuart),
 };
+
+static struct resource pxa_resource_hwuart[] = {
+        {
+                .start  = __PREG(HWUART),
+                .end    = __PREG(HWUART) + 47,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_HWUART,
+                .end    = IRQ_HWUART,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
 struct platform_device pxa_device_hwuart = {
         .name           = "pxa2xx-uart",
         .id             = 3,
+        .resource       = pxa_resource_hwuart,
+        .num_resources  = ARRAY_SIZE(pxa_resource_hwuart),
 };
 
 static struct resource pxai2c_resources[] = {
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index 91ab2ad8b34b..b30f240a16c7 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -15,14 +15,40 @@ extern struct sys_timer pxa_timer;
 extern void __init pxa_init_irq_low(void);
 extern void __init pxa_init_irq_high(void);
 extern void __init pxa_init_irq_gpio(int gpio_nr);
+extern void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int));
 extern void __init pxa25x_init_irq(void);
 extern void __init pxa27x_init_irq(void);
+extern void __init pxa3xx_init_irq(void);
 extern void __init pxa_map_io(void);
 
 extern unsigned int get_clk_frequency_khz(int info);
+extern int pxa_last_gpio;
 
 #define SET_BANK(__nr,__start,__size) \
         mi->bank[__nr].start = (__start), \
         mi->bank[__nr].size = (__size), \
         mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27)
 
+#ifdef CONFIG_PXA25x
+extern unsigned pxa25x_get_clk_frequency_khz(int);
+extern unsigned pxa25x_get_memclk_frequency_10khz(void);
+#else
+#define pxa25x_get_clk_frequency_khz(x)         (0)
+#define pxa25x_get_memclk_frequency_10khz()     (0)
+#endif
+
+#ifdef CONFIG_PXA27x
+extern unsigned pxa27x_get_clk_frequency_khz(int);
+extern unsigned pxa27x_get_memclk_frequency_10khz(void);
+#else
+#define pxa27x_get_clk_frequency_khz(x)         (0)
+#define pxa27x_get_memclk_frequency_10khz()     (0)
+#endif
+
+#ifdef CONFIG_PXA3xx
+extern unsigned pxa3xx_get_clk_frequency_khz(int);
+extern unsigned pxa3xx_get_memclk_frequency_10khz(void);
+#else
+#define pxa3xx_get_clk_frequency_khz(x)         (0)
+#define pxa3xx_get_memclk_frequency_10khz()     (0)
+#endif
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index ae2ae08032d7..07acb45b16ea 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -38,33 +38,11 @@ static void pxa_unmask_low_irq(unsigned int irq)
         ICMR |= (1 << irq);
 }
 
-static int pxa_set_wake(unsigned int irq, unsigned int on)
-{
-        u32     mask;
-
-        switch (irq) {
-        case IRQ_RTCAlrm:
-                mask = PWER_RTC;
-                break;
-#ifdef CONFIG_PXA27x
-        /* REVISIT can handle USBH1, USBH2, USB, MSL, USIM, ... */
-#endif
-        default:
-                return -EINVAL;
-        }
-        if (on)
-                PWER |= mask;
-        else
-                PWER &= ~mask;
-        return 0;
-}
-
 static struct irq_chip pxa_internal_chip_low = {
         .name           = "SC",
         .ack            = pxa_mask_low_irq,
         .mask           = pxa_mask_low_irq,
         .unmask         = pxa_unmask_low_irq,
-        .set_wake       = pxa_set_wake,
 };
 
 void __init pxa_init_irq_low(void)
@@ -87,7 +65,7 @@ void __init pxa_init_irq_low(void)
         }
 }
 
-#ifdef CONFIG_PXA27x
+#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 
 /*
  * This is for the second set of internal IRQs as found on the PXA27x.
@@ -125,26 +103,6 @@ void __init pxa_init_irq_high(void)
 }
 #endif
 
-/* Note that if an input/irq line ever gets changed to an output during
- * suspend, the relevant PWER, PRER, and PFER bits should be cleared.
- */
-#ifdef CONFIG_PXA27x
-
-/* PXA27x:  Various gpios can issue wakeup events.  This logic only
- * handles the simple cases, not the WEMUX2 and WEMUX3 options
- */
-#define PXA27x_GPIO_NOWAKE_MASK \
-        ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2))
-#define WAKEMASK(gpio) \
-        (((gpio) <= 15) \
-                ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \
-                : ((gpio == 35) ? (1 << 24) : 0))
-#else
-
-/* pxa 210, 250, 255, 26x:  gpios 0..15 can issue wakeups */
-#define WAKEMASK(gpio) (((gpio) <= 15) ? (1 << (gpio)) : 0)
-#endif
-
 /*
  * PXA GPIO edge detection for IRQs:
  * IRQs are generated on Falling-Edge, Rising-Edge, or both.
@@ -158,11 +116,9 @@ static long GPIO_IRQ_mask[4];
 static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
 {
         int gpio, idx;
-        u32 mask;
 
         gpio = IRQ_TO_GPIO(irq);
         idx = gpio >> 5;
-        mask = WAKEMASK(gpio);
 
         if (type == IRQT_PROBE) {
             /* Don't mess with enabled GPIOs using preconfigured edges or
@@ -182,19 +138,15 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
         if (type & __IRQT_RISEDGE) {
                 /* printk("rising "); */
                 __set_bit (gpio, GPIO_IRQ_rising_edge);
-                PRER |= mask;
         } else {
                 __clear_bit (gpio, GPIO_IRQ_rising_edge);
-                PRER &= ~mask;
         }
 
         if (type & __IRQT_FALEDGE) {
                 /* printk("falling "); */
                 __set_bit (gpio, GPIO_IRQ_falling_edge);
-                PFER |= mask;
         } else {
                 __clear_bit (gpio, GPIO_IRQ_falling_edge);
-                PFER &= ~mask;
         }
 
         /* printk("edges\n"); */
@@ -213,29 +165,12 @@ static void pxa_ack_low_gpio(unsigned int irq)
         GEDR0 = (1 << (irq - IRQ_GPIO0));
 }
 
-static int pxa_set_gpio_wake(unsigned int irq, unsigned int on)
-{
-        int     gpio = IRQ_TO_GPIO(irq);
-        u32     mask = WAKEMASK(gpio);
-
-        if (!mask)
-                return -EINVAL;
-
-        if (on)
-                PWER |= mask;
-        else
-                PWER &= ~mask;
-        return 0;
-}
-
-
 static struct irq_chip pxa_low_gpio_chip = {
         .name           = "GPIO-l",
         .ack            = pxa_ack_low_gpio,
         .mask           = pxa_mask_low_irq,
         .unmask         = pxa_unmask_low_irq,
         .set_type       = pxa_gpio_irq_type,
-        .set_wake       = pxa_set_gpio_wake,
 };
 
 /*
@@ -342,13 +277,14 @@ static struct irq_chip pxa_muxed_gpio_chip = {
         .mask           = pxa_mask_muxed_gpio,
         .unmask         = pxa_unmask_muxed_gpio,
         .set_type       = pxa_gpio_irq_type,
-        .set_wake       = pxa_set_gpio_wake,
 };
 
 void __init pxa_init_irq_gpio(int gpio_nr)
 {
         int irq, i;
 
+        pxa_last_gpio = gpio_nr - 1;
+
         /* clear all GPIO edge detects */
         for (i = 0; i < gpio_nr; i += 32) {
                 GFER(i) = 0;
@@ -375,3 +311,13 @@ void __init pxa_init_irq_gpio(int gpio_nr)
         set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low);
         set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
 }
+
+void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int))
+{
+        pxa_internal_chip_low.set_wake = set_wake;
+#ifdef CONFIG_PXA27x
+        pxa_internal_chip_high.set_wake = set_wake;
+#endif
+        pxa_low_gpio_chip.set_wake = set_wake;
+        pxa_muxed_gpio_chip.set_wake = set_wake;
+}
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index e70048fd00a5..011a1a72b61c 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -512,6 +512,25 @@ static void __init lubbock_map_io(void)
         pxa_gpio_mode(GPIO44_BTCTS_MD);
         pxa_gpio_mode(GPIO45_BTRTS_MD);
 
+        GPSR(GPIO48_nPOE) =
+                GPIO_bit(GPIO48_nPOE) |
+                GPIO_bit(GPIO49_nPWE) |
+                GPIO_bit(GPIO50_nPIOR) |
+                GPIO_bit(GPIO51_nPIOW) |
+                GPIO_bit(GPIO52_nPCE_1) |
+                GPIO_bit(GPIO53_nPCE_2);
+
+        pxa_gpio_mode(GPIO48_nPOE_MD);
+        pxa_gpio_mode(GPIO49_nPWE_MD);
+        pxa_gpio_mode(GPIO50_nPIOR_MD);
+        pxa_gpio_mode(GPIO51_nPIOW_MD);
+        pxa_gpio_mode(GPIO52_nPCE_1_MD);
+        pxa_gpio_mode(GPIO53_nPCE_2_MD);
+        pxa_gpio_mode(GPIO54_pSKTSEL_MD);
+        pxa_gpio_mode(GPIO55_nPREG_MD);
+        pxa_gpio_mode(GPIO56_nPWAIT_MD);
+        pxa_gpio_mode(GPIO57_nIOIS16_MD);
+
         /* This is for the SMC chip select */
         pxa_gpio_mode(GPIO79_nCS_3_MD);
 
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index b02c79c7e6a3..a4bc3483cbb3 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -444,6 +444,25 @@ static void __init mainstone_init(void)
          */
         pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
 
+        GPSR(GPIO48_nPOE) =
+                GPIO_bit(GPIO48_nPOE) |
+                GPIO_bit(GPIO49_nPWE) |
+                GPIO_bit(GPIO50_nPIOR) |
+                GPIO_bit(GPIO51_nPIOW) |
+                GPIO_bit(GPIO85_nPCE_1) |
+                GPIO_bit(GPIO54_nPCE_2);
+
+        pxa_gpio_mode(GPIO48_nPOE_MD);
+        pxa_gpio_mode(GPIO49_nPWE_MD);
+        pxa_gpio_mode(GPIO50_nPIOR_MD);
+        pxa_gpio_mode(GPIO51_nPIOW_MD);
+        pxa_gpio_mode(GPIO85_nPCE_1_MD);
+        pxa_gpio_mode(GPIO54_nPCE_2_MD);
+        pxa_gpio_mode(GPIO79_pSKTSEL_MD);
+        pxa_gpio_mode(GPIO55_nPREG_MD);
+        pxa_gpio_mode(GPIO56_nPWAIT_MD);
+        pxa_gpio_mode(GPIO57_nIOIS16_MD);
+
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 
         /* reading Mainstone's "Virtual Configuration Register"
diff --git a/arch/arm/mach-pxa/mfp.c b/arch/arm/mach-pxa/mfp.c
new file mode 100644
index 000000000000..5cd3cadbbd10
--- /dev/null
+++ b/arch/arm/mach-pxa/mfp.c
@@ -0,0 +1,235 @@
+/*
+ * linux/arch/arm/mach-pxa/mfp.c
+ *
+ * PXA3xx Multi-Function Pin Support
+ *
+ * Copyright (C) 2007 Marvell Internation Ltd.
+ *
+ * 2007-08-21: eric miao <eric.y.miao@gmail.com>
+ *             initial version
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include <asm/hardware.h>
+#include <asm/arch/mfp.h>
+
+/* mfp_spin_lock is used to ensure that MFP register configuration
+ * (most likely a read-modify-write operation) is atomic, and that
+ * mfp_table[] is consistent
+ */
+static DEFINE_SPINLOCK(mfp_spin_lock);
+
+static void __iomem *mfpr_mmio_base = (void __iomem *)&__REG(MFPR_BASE);
+static struct pxa3xx_mfp_pin mfp_table[MFP_PIN_MAX];
+
+#define mfpr_readl(off)                 \
+        __raw_readl(mfpr_mmio_base + (off))
+
+#define mfpr_writel(off, val)           \
+        __raw_writel(val, mfpr_mmio_base + (off))
+
+/*
+ * perform a read-back of any MFPR register to make sure the
+ * previous writings are finished
+ */
+#define mfpr_sync()     (void)__raw_readl(mfpr_mmio_base + 0)
+
+static inline void __mfp_config(int pin, unsigned long val)
+{
+        unsigned long off = mfp_table[pin].mfpr_off;
+
+        mfp_table[pin].mfpr_val = val;
+        mfpr_writel(off, val);
+}
+
+void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num)
+{
+        int i, pin;
+        unsigned long val, flags;
+        mfp_cfg_t *mfp_cfg = mfp_cfgs;
+
+        spin_lock_irqsave(&mfp_spin_lock, flags);
+
+        for (i = 0; i < num; i++, mfp_cfg++) {
+                pin = MFP_CFG_PIN(*mfp_cfg);
+                val = MFP_CFG_VAL(*mfp_cfg);
+
+                BUG_ON(pin >= MFP_PIN_MAX);
+
+                __mfp_config(pin, val);
+        }
+
+        mfpr_sync();
+        spin_unlock_irqrestore(&mfp_spin_lock, flags);
+}
+
+unsigned long pxa3xx_mfp_read(int mfp)
+{
+        unsigned long val, flags;
+
+        BUG_ON(mfp >= MFP_PIN_MAX);
+
+        spin_lock_irqsave(&mfp_spin_lock, flags);
+        val = mfpr_readl(mfp_table[mfp].mfpr_off);
+        spin_unlock_irqrestore(&mfp_spin_lock, flags);
+
+        return val;
+}
+
+void pxa3xx_mfp_write(int mfp, unsigned long val)
+{
+        unsigned long flags;
+
+        BUG_ON(mfp >= MFP_PIN_MAX);
+
+        spin_lock_irqsave(&mfp_spin_lock, flags);
+        mfpr_writel(mfp_table[mfp].mfpr_off, val);
+        mfpr_sync();
+        spin_unlock_irqrestore(&mfp_spin_lock, flags);
+}
+
+void pxa3xx_mfp_set_afds(int mfp, int af, int ds)
+{
+        uint32_t mfpr_off, mfpr_val;
+        unsigned long flags;
+
+        BUG_ON(mfp >= MFP_PIN_MAX);
+
+        spin_lock_irqsave(&mfp_spin_lock, flags);
+        mfpr_off = mfp_table[mfp].mfpr_off;
+
+        mfpr_val = mfpr_readl(mfpr_off);
+        mfpr_val &= ~(MFPR_AF_MASK | MFPR_DRV_MASK);
+        mfpr_val |= (((af & 0x7) << MFPR_ALT_OFFSET) |
+                     ((ds & 0x7) << MFPR_DRV_OFFSET));
+
+        mfpr_writel(mfpr_off, mfpr_val);
+        mfpr_sync();
+
+        spin_unlock_irqrestore(&mfp_spin_lock, flags);
+}
+
+void pxa3xx_mfp_set_rdh(int mfp, int rdh)
+{
+        uint32_t mfpr_off, mfpr_val;
+        unsigned long flags;
+
+        BUG_ON(mfp >= MFP_PIN_MAX);
+
+        spin_lock_irqsave(&mfp_spin_lock, flags);
+
+        mfpr_off = mfp_table[mfp].mfpr_off;
+
+        mfpr_val = mfpr_readl(mfpr_off);
+        mfpr_val &= ~MFPR_RDH_MASK;
+
+        if (likely(rdh))
+                mfpr_val |= (1u << MFPR_SS_OFFSET);
+
+        mfpr_writel(mfpr_off, mfpr_val);
+        mfpr_sync();
+
+        spin_unlock_irqrestore(&mfp_spin_lock, flags);
+}
+
+void pxa3xx_mfp_set_lpm(int mfp, int lpm)
+{
+        uint32_t mfpr_off, mfpr_val;
+        unsigned long flags;
+
+        BUG_ON(mfp >= MFP_PIN_MAX);
+
+        spin_lock_irqsave(&mfp_spin_lock, flags);
+
+        mfpr_off = mfp_table[mfp].mfpr_off;
+        mfpr_val = mfpr_readl(mfpr_off);
+        mfpr_val &= ~MFPR_LPM_MASK;
+
+        if (lpm & 0x1) mfpr_val |= 1u << MFPR_SON_OFFSET;
+        if (lpm & 0x2) mfpr_val |= 1u << MFPR_SD_OFFSET;
+        if (lpm & 0x4) mfpr_val |= 1u << MFPR_PU_OFFSET;
+        if (lpm & 0x8) mfpr_val |= 1u << MFPR_PD_OFFSET;
+        if (lpm &0x10) mfpr_val |= 1u << MFPR_PS_OFFSET;
+
+        mfpr_writel(mfpr_off, mfpr_val);
+        mfpr_sync();
+
+        spin_unlock_irqrestore(&mfp_spin_lock, flags);
+}
+
+void pxa3xx_mfp_set_pull(int mfp, int pull)
+{
+        uint32_t mfpr_off, mfpr_val;
+        unsigned long flags;
+
+        BUG_ON(mfp >= MFP_PIN_MAX);
+
+        spin_lock_irqsave(&mfp_spin_lock, flags);
+
+        mfpr_off = mfp_table[mfp].mfpr_off;
+        mfpr_val = mfpr_readl(mfpr_off);
+        mfpr_val &= ~MFPR_PULL_MASK;
+        mfpr_val |= ((pull & 0x7u) << MFPR_PD_OFFSET);
+
+        mfpr_writel(mfpr_off, mfpr_val);
+        mfpr_sync();
+
+        spin_unlock_irqrestore(&mfp_spin_lock, flags);
+}
+
+void pxa3xx_mfp_set_edge(int mfp, int edge)
+{
+        uint32_t mfpr_off, mfpr_val;
+        unsigned long flags;
+
+        BUG_ON(mfp >= MFP_PIN_MAX);
+
+        spin_lock_irqsave(&mfp_spin_lock, flags);
+
+        mfpr_off = mfp_table[mfp].mfpr_off;
+        mfpr_val = mfpr_readl(mfpr_off);
+
+        mfpr_val &= ~MFPR_EDGE_MASK;
+        mfpr_val |= (edge & 0x3u) << MFPR_ERE_OFFSET;
+        mfpr_val |= (!edge & 0x1) << MFPR_EC_OFFSET;
+
+        mfpr_writel(mfpr_off, mfpr_val);
+        mfpr_sync();
+
+        spin_unlock_irqrestore(&mfp_spin_lock, flags);
+}
+
+void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *map)
+{
+        struct pxa3xx_mfp_addr_map *p;
+        unsigned long offset, flags;
+        int i;
+
+        spin_lock_irqsave(&mfp_spin_lock, flags);
+
+        for (p = map; p->start != MFP_PIN_INVALID; p++) {
+                offset = p->offset;
+                i = p->start;
+
+                do {
+                        mfp_table[i].mfpr_off = offset;
+                        mfp_table[i].mfpr_val = 0;
+                        offset += 4; i++;
+                } while ((i <= p->end) && (p->end != -1));
+        }
+
+        spin_unlock_irqrestore(&mfp_spin_lock, flags);
+}
+
+void __init pxa3xx_init_mfp(void)
+{
+        memset(mfp_table, 0, sizeof(mfp_table));
+}
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 6dfcca72e90f..0d6a72504caa 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -30,6 +30,7 @@
 
 #include "generic.h"
 #include "devices.h"
+#include "clock.h"
 
 /*
  * Various clock factors driven by the CCCR register.
@@ -53,7 +54,7 @@ static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
  * We assume these values have been applied via a fcs.
  * If info is not 0 we also display the current settings.
  */
-unsigned int get_clk_frequency_khz(int info)
+unsigned int pxa25x_get_clk_frequency_khz(int info)
 {
         unsigned long cccr, turbo;
         unsigned int l, L, m, M, n2, N;
@@ -86,27 +87,48 @@ unsigned int get_clk_frequency_khz(int info)
         return (turbo & 1) ? (N/1000) : (M/1000);
 }
 
-EXPORT_SYMBOL(get_clk_frequency_khz);
-
 /*
  * Return the current memory clock frequency in units of 10kHz
  */
-unsigned int get_memclk_frequency_10khz(void)
+unsigned int pxa25x_get_memclk_frequency_10khz(void)
 {
         return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
 }
 
-EXPORT_SYMBOL(get_memclk_frequency_10khz);
-
-/*
- * Return the current LCD clock frequency in units of 10kHz
- */
-unsigned int get_lcdclk_frequency_10khz(void)
+static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk)
 {
-        return get_memclk_frequency_10khz();
+        return pxa25x_get_memclk_frequency_10khz() * 10000;
 }
 
-EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
+static const struct clkops clk_pxa25x_lcd_ops = {
+        .enable         = clk_cken_enable,
+        .disable        = clk_cken_disable,
+        .getrate        = clk_pxa25x_lcd_getrate,
+};
+
+/*
+ * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
+ * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
+ * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
+ */
+static struct clk pxa25x_clks[] = {
+        INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev),
+        INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev),
+        INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
+        INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
+        INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL),
+        INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev),
+        INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
+        INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),
+        /*
+        INIT_CKEN("PWMCLK",  PWM0, 3686400,  0, NULL),
+        INIT_CKEN("PWMCLK",  PWM0, 3686400,  0, NULL),
+        INIT_CKEN("SSPCLK",  SSP,  3686400,  0, NULL),
+        INIT_CKEN("I2SCLK",  I2S,  14745600, 0, NULL),
+        INIT_CKEN("NSSPCLK", NSSP, 3686400,  0, NULL),
+        */
+        INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
+};
 
 #ifdef CONFIG_PM
 
@@ -205,10 +227,52 @@ static void __init pxa25x_init_pm(void)
 }
 #endif
 
+/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
+ */
+
+static int pxa25x_set_wake(unsigned int irq, unsigned int on)
+{
+        int gpio = IRQ_TO_GPIO(irq);
+        uint32_t gpio_bit, mask = 0;
+
+        if (gpio >= 0 && gpio <= 15) {
+                gpio_bit = GPIO_bit(gpio);
+                mask = gpio_bit;
+                if (on) {
+                        if (GRER(gpio) | gpio_bit)
+                                PRER |= gpio_bit;
+                        else
+                                PRER &= ~gpio_bit;
+
+                        if (GFER(gpio) | gpio_bit)
+                                PFER |= gpio_bit;
+                        else
+                                PFER &= ~gpio_bit;
+                }
+                goto set_pwer;
+        }
+
+        if (irq == IRQ_RTCAlrm) {
+                mask = PWER_RTC;
+                goto set_pwer;
+        }
+
+        return -EINVAL;
+
+set_pwer:
+        if (on)
+                PWER |= mask;
+        else
+                PWER &=~mask;
+
+        return 0;
+}
+
 void __init pxa25x_init_irq(void)
 {
         pxa_init_irq_low();
         pxa_init_irq_gpio(85);
+        pxa_init_irq_set_wake(pxa25x_set_wake);
 }
 
 static struct platform_device *pxa25x_devices[] __initdata = {
@@ -229,6 +293,8 @@ static int __init pxa25x_init(void)
         int ret = 0;
 
         if (cpu_is_pxa21x() || cpu_is_pxa25x()) {
+                clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks));
+
                 if ((ret = pxa_init_dma(16)))
                         return ret;
 #ifdef CONFIG_PM
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 203371ab19db..2d7fc39732e4 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -27,6 +27,7 @@
 
 #include "generic.h"
 #include "devices.h"
+#include "clock.h"
 
 /* Crystal clock: 13MHz */
 #define BASE_CLK        13000000
@@ -36,7 +37,7 @@
  * We assume these values have been applied via a fcs.
  * If info is not 0 we also display the current settings.
  */
-unsigned int get_clk_frequency_khz( int info)
+unsigned int pxa27x_get_clk_frequency_khz(int info)
 {
         unsigned long ccsr, clkcfg;
         unsigned int l, L, m, M, n2, N, S;
@@ -79,7 +80,7 @@ unsigned int get_clk_frequency_khz( int info)
  * Return the current mem clock frequency in units of 10kHz as
  * reflected by CCCR[A], B, and L
  */
-unsigned int get_memclk_frequency_10khz(void)
+unsigned int pxa27x_get_memclk_frequency_10khz(void)
 {
         unsigned long ccsr, clkcfg;
         unsigned int l, L, m, M;
@@ -104,7 +105,7 @@ unsigned int get_memclk_frequency_10khz(void)
 /*
  * Return the current LCD clock frequency in units of 10kHz as
  */
-unsigned int get_lcdclk_frequency_10khz(void)
+static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
 {
         unsigned long ccsr;
         unsigned int l, L, k, K;
@@ -120,9 +121,47 @@ unsigned int get_lcdclk_frequency_10khz(void)
         return (K / 10000);
 }
 
-EXPORT_SYMBOL(get_clk_frequency_khz);
-EXPORT_SYMBOL(get_memclk_frequency_10khz);
-EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
+static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
+{
+        return pxa27x_get_lcdclk_frequency_10khz() * 10000;
+}
+
+static const struct clkops clk_pxa27x_lcd_ops = {
+        .enable         = clk_cken_enable,
+        .disable        = clk_cken_disable,
+        .getrate        = clk_pxa27x_lcd_getrate,
+};
+
+static struct clk pxa27x_clks[] = {
+        INIT_CK("LCDCLK", LCD,    &clk_pxa27x_lcd_ops, &pxa_device_fb.dev),
+        INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_ops, NULL),
+
+        INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
+        INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
+        INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
+
+        INIT_CKEN("I2SCLK",  I2S,  14682000, 0, &pxa_device_i2s.dev),
+        INIT_CKEN("I2CCLK",  I2C,  32842000, 0, &pxa_device_i2c.dev),
+        INIT_CKEN("UDCCLK",  USB,  48000000, 5, &pxa_device_udc.dev),
+        INIT_CKEN("MMCCLK",  MMC,  19500000, 0, &pxa_device_mci.dev),
+        INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev),
+
+        INIT_CKEN("USBCLK", USB,    48000000, 0, &pxa27x_device_ohci.dev),
+        INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev),
+        INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL),
+
+        /*
+        INIT_CKEN("PWMCLK",  PWM0, 13000000, 0, NULL),
+        INIT_CKEN("SSPCLK",  SSP1, 13000000, 0, NULL),
+        INIT_CKEN("SSPCLK",  SSP2, 13000000, 0, NULL),
+        INIT_CKEN("SSPCLK",  SSP3, 13000000, 0, NULL),
+        INIT_CKEN("MSLCLK",  MSL,  48000000, 0, NULL),
+        INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL),
+        INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL),
+        INIT_CKEN("IMCLK",   IM,   0, 0, NULL),
+        INIT_CKEN("MEMCLK",  MEMC, 0, 0, NULL),
+        */
+};
 
 #ifdef CONFIG_PM
 
@@ -267,6 +306,69 @@ static void __init pxa27x_init_pm(void)
 }
 #endif
 
+/* PXA27x:  Various gpios can issue wakeup events.  This logic only
+ * handles the simple cases, not the WEMUX2 and WEMUX3 options
+ */
+#define PXA27x_GPIO_NOWAKE_MASK \
+        ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2))
+#define WAKEMASK(gpio) \
+        (((gpio) <= 15) \
+                 ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \
+                 : ((gpio == 35) ? (1 << 24) : 0))
+
+static int pxa27x_set_wake(unsigned int irq, unsigned int on)
+{
+        int gpio = IRQ_TO_GPIO(irq);
+        uint32_t mask;
+
+        if ((gpio >= 0 && gpio <= 15) || (gpio == 35)) {
+                if (WAKEMASK(gpio) == 0)
+                        return -EINVAL;
+
+                mask = WAKEMASK(gpio);
+
+                if (on) {
+                        if (GRER(gpio) | GPIO_bit(gpio))
+                                PRER |= mask;
+                        else
+                                PRER &= ~mask;
+
+                        if (GFER(gpio) | GPIO_bit(gpio))
+                                PFER |= mask;
+                        else
+                                PFER &= ~mask;
+                }
+                goto set_pwer;
+        }
+
+        switch (irq) {
+        case IRQ_RTCAlrm:
+                mask = PWER_RTC;
+                break;
+        case IRQ_USB:
+                mask = 1u << 26;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+set_pwer:
+        if (on)
+                PWER |= mask;
+        else
+                PWER &=~mask;
+
+        return 0;
+}
+
+void __init pxa27x_init_irq(void)
+{
+        pxa_init_irq_low();
+        pxa_init_irq_high();
+        pxa_init_irq_gpio(128);
+        pxa_init_irq_set_wake(pxa27x_set_wake);
+}
+
 /*
  * device registration specific to PXA27x.
  */
@@ -286,7 +388,7 @@ static struct resource pxa27x_ohci_resources[] = {
         },
 };
 
-static struct platform_device pxa27x_device_ohci = {
+struct platform_device pxa27x_device_ohci = {
         .name           = "pxa27x-ohci",
         .id             = -1,
         .dev            = {
@@ -314,7 +416,7 @@ static struct resource i2c_power_resources[] = {
         },
 };
 
-static struct platform_device pxa27x_device_i2c_power = {
+struct platform_device pxa27x_device_i2c_power = {
         .name           = "pxa2xx-i2c",
         .id             = 1,
         .resource       = i2c_power_resources,
@@ -336,17 +438,12 @@ static struct platform_device *devices[] __initdata = {
         &pxa27x_device_ohci,
 };
 
-void __init pxa27x_init_irq(void)
-{
-        pxa_init_irq_low();
-        pxa_init_irq_high();
-        pxa_init_irq_gpio(128);
-}
-
 static int __init pxa27x_init(void)
 {
         int ret = 0;
         if (cpu_is_pxa27x()) {
+                clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks));
+
                 if ((ret = pxa_init_dma(32)))
                         return ret;
 #ifdef CONFIG_PM
diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c
new file mode 100644
index 000000000000..5363b1322652
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa300.c
@@ -0,0 +1,93 @@
+/*
+ * linux/arch/arm/mach-pxa/pxa300.c
+ *
+ * Code specific to PXA300/PXA310
+ *
+ * Copyright (C) 2007 Marvell Internation Ltd.
+ *
+ * 2007-08-21: eric miao <eric.y.miao@gmail.com>
+ *             initial version
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+
+#include <asm/hardware.h>
+#include <asm/arch/mfp-pxa300.h>
+
+static struct pxa3xx_mfp_addr_map pxa300_mfp_addr_map[] __initdata = {
+
+        MFP_ADDR_X(GPIO0,   GPIO2,   0x00b4),
+        MFP_ADDR_X(GPIO3,   GPIO26,  0x027c),
+        MFP_ADDR_X(GPIO27,  GPIO127, 0x0400),
+        MFP_ADDR_X(GPIO0_2, GPIO6_2, 0x02ec),
+
+        MFP_ADDR(nBE0, 0x0204),
+        MFP_ADDR(nBE1, 0x0208),
+
+        MFP_ADDR(nLUA, 0x0244),
+        MFP_ADDR(nLLA, 0x0254),
+
+        MFP_ADDR(DF_CLE_nOE, 0x0240),
+        MFP_ADDR(DF_nRE_nOE, 0x0200),
+        MFP_ADDR(DF_ALE_nWE, 0x020C),
+        MFP_ADDR(DF_INT_RnB, 0x00C8),
+        MFP_ADDR(DF_nCS0, 0x0248),
+        MFP_ADDR(DF_nCS1, 0x0278),
+        MFP_ADDR(DF_nWE, 0x00CC),
+
+        MFP_ADDR(DF_ADDR0, 0x0210),
+        MFP_ADDR(DF_ADDR1, 0x0214),
+        MFP_ADDR(DF_ADDR2, 0x0218),
+        MFP_ADDR(DF_ADDR3, 0x021C),
+
+        MFP_ADDR(DF_IO0, 0x0220),
+        MFP_ADDR(DF_IO1, 0x0228),
+        MFP_ADDR(DF_IO2, 0x0230),
+        MFP_ADDR(DF_IO3, 0x0238),
+        MFP_ADDR(DF_IO4, 0x0258),
+        MFP_ADDR(DF_IO5, 0x0260),
+        MFP_ADDR(DF_IO6, 0x0268),
+        MFP_ADDR(DF_IO7, 0x0270),
+        MFP_ADDR(DF_IO8, 0x0224),
+        MFP_ADDR(DF_IO9, 0x022C),
+        MFP_ADDR(DF_IO10, 0x0234),
+        MFP_ADDR(DF_IO11, 0x023C),
+        MFP_ADDR(DF_IO12, 0x025C),
+        MFP_ADDR(DF_IO13, 0x0264),
+        MFP_ADDR(DF_IO14, 0x026C),
+        MFP_ADDR(DF_IO15, 0x0274),
+
+        MFP_ADDR_END,
+};
+
+/* override pxa300 MFP register addresses */
+static struct pxa3xx_mfp_addr_map pxa310_mfp_addr_map[] __initdata = {
+        MFP_ADDR_X(GPIO30,  GPIO98,   0x0418),
+        MFP_ADDR_X(GPIO7_2, GPIO12_2, 0x052C),
+
+        MFP_ADDR(ULPI_STP, 0x040C),
+        MFP_ADDR(ULPI_NXT, 0x0410),
+        MFP_ADDR(ULPI_DIR, 0x0414),
+
+        MFP_ADDR_END,
+};
+
+static int __init pxa300_init(void)
+{
+        if (cpu_is_pxa300() || cpu_is_pxa310()) {
+                pxa3xx_init_mfp();
+                pxa3xx_mfp_init_addr(pxa300_mfp_addr_map);
+        }
+
+        if (cpu_is_pxa310())
+                pxa3xx_mfp_init_addr(pxa310_mfp_addr_map);
+
+        return 0;
+}
+
+core_initcall(pxa300_init);
diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c
new file mode 100644
index 000000000000..cd9eba5b3df9
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa320.c
@@ -0,0 +1,88 @@
+/*
+ * linux/arch/arm/mach-pxa/pxa320.c
+ *
+ * Code specific to PXA320
+ *
+ * Copyright (C) 2007 Marvell Internation Ltd.
+ *
+ * 2007-08-21: eric miao <eric.y.miao@gmail.com>
+ *             initial version
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+
+#include <asm/hardware.h>
+#include <asm/arch/mfp.h>
+#include <asm/arch/mfp-pxa320.h>
+
+static struct pxa3xx_mfp_addr_map pxa320_mfp_addr_map[] __initdata = {
+
+        MFP_ADDR_X(GPIO0,  GPIO4,   0x0124),
+        MFP_ADDR_X(GPIO5,  GPIO26,  0x028C),
+        MFP_ADDR_X(GPIO27, GPIO62,  0x0400),
+        MFP_ADDR_X(GPIO63, GPIO73,  0x04B4),
+        MFP_ADDR_X(GPIO74, GPIO98,  0x04F0),
+        MFP_ADDR_X(GPIO99, GPIO127, 0x0600),
+        MFP_ADDR_X(GPIO0_2,  GPIO5_2,   0x0674),
+        MFP_ADDR_X(GPIO6_2,  GPIO13_2,  0x0494),
+        MFP_ADDR_X(GPIO14_2, GPIO17_2, 0x04E0),
+
+        MFP_ADDR(nXCVREN, 0x0138),
+        MFP_ADDR(DF_CLE_nOE, 0x0204),
+        MFP_ADDR(DF_nADV1_ALE, 0x0208),
+        MFP_ADDR(DF_SCLK_S, 0x020C),
+        MFP_ADDR(DF_SCLK_E, 0x0210),
+        MFP_ADDR(nBE0, 0x0214),
+        MFP_ADDR(nBE1, 0x0218),
+        MFP_ADDR(DF_nADV2_ALE, 0x021C),
+        MFP_ADDR(DF_INT_RnB, 0x0220),
+        MFP_ADDR(DF_nCS0, 0x0224),
+        MFP_ADDR(DF_nCS1, 0x0228),
+        MFP_ADDR(DF_nWE, 0x022C),
+        MFP_ADDR(DF_nRE_nOE, 0x0230),
+        MFP_ADDR(nLUA, 0x0234),
+        MFP_ADDR(nLLA, 0x0238),
+        MFP_ADDR(DF_ADDR0, 0x023C),
+        MFP_ADDR(DF_ADDR1, 0x0240),
+        MFP_ADDR(DF_ADDR2, 0x0244),
+        MFP_ADDR(DF_ADDR3, 0x0248),
+        MFP_ADDR(DF_IO0, 0x024C),
+        MFP_ADDR(DF_IO8, 0x0250),
+        MFP_ADDR(DF_IO1, 0x0254),
+        MFP_ADDR(DF_IO9, 0x0258),
+        MFP_ADDR(DF_IO2, 0x025C),
+        MFP_ADDR(DF_IO10, 0x0260),
+        MFP_ADDR(DF_IO3, 0x0264),
+        MFP_ADDR(DF_IO11, 0x0268),
+        MFP_ADDR(DF_IO4, 0x026C),
+        MFP_ADDR(DF_IO12, 0x0270),
+        MFP_ADDR(DF_IO5, 0x0274),
+        MFP_ADDR(DF_IO13, 0x0278),
+        MFP_ADDR(DF_IO6, 0x027C),
+        MFP_ADDR(DF_IO14, 0x0280),
+        MFP_ADDR(DF_IO7, 0x0284),
+        MFP_ADDR(DF_IO15, 0x0288),
+
+        MFP_ADDR_END,
+};
+
+static void __init pxa320_init_mfp(void)
+{
+        pxa3xx_init_mfp();
+        pxa3xx_mfp_init_addr(pxa320_mfp_addr_map);
+}
+
+static int __init pxa320_init(void)
+{
+        if (cpu_is_pxa320())
+                pxa320_init_mfp();
+
+        return 0;
+}
+
+core_initcall(pxa320_init);
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
new file mode 100644
index 000000000000..39f0de8c189e
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -0,0 +1,216 @@
+/*
+ * linux/arch/arm/mach-pxa/pxa3xx.c
+ *
+ * code specific to pxa3xx aka Monahans
+ *
+ * Copyright (C) 2006 Marvell International Ltd.
+ *
+ * 2007-09-02: eric miao <eric.y.miao@gmail.com>
+ *             initial version
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pm.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+
+#include <asm/hardware.h>
+#include <asm/arch/pxa3xx-regs.h>
+#include <asm/arch/ohci.h>
+#include <asm/arch/pm.h>
+#include <asm/arch/dma.h>
+#include <asm/arch/ssp.h>
+
+#include "generic.h"
+#include "devices.h"
+#include "clock.h"
+
+/* Crystal clock: 13MHz */
+#define BASE_CLK        13000000
+
+/* Ring Oscillator Clock: 60MHz */
+#define RO_CLK          60000000
+
+#define ACCR_D0CS       (1 << 26)
+
+/* crystal frequency to static memory controller multiplier (SMCFS) */
+static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
+
+/* crystal frequency to HSIO bus frequency multiplier (HSS) */
+static unsigned char hss_mult[4] = { 8, 12, 16, 0 };
+
+/*
+ * Get the clock frequency as reflected by CCSR and the turbo flag.
+ * We assume these values have been applied via a fcs.
+ * If info is not 0 we also display the current settings.
+ */
+unsigned int pxa3xx_get_clk_frequency_khz(int info)
+{
+        unsigned long acsr, xclkcfg;
+        unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
+
+        /* Read XCLKCFG register turbo bit */
+        __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
+        t = xclkcfg & 0x1;
+
+        acsr = ACSR;
+
+        xl  = acsr & 0x1f;
+        xn  = (acsr >> 8) & 0x7;
+        hss = (acsr >> 14) & 0x3;
+
+        XL = xl * BASE_CLK;
+        XN = xn * XL;
+
+        ro = acsr & ACCR_D0CS;
+
+        CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
+        HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
+
+        if (info) {
+                pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
+                        RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
+                        (ro) ? "" : "in");
+                pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
+                        XL / 1000000, (XL % 1000000) / 10000, xl);
+                pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
+                        XN / 1000000, (XN % 1000000) / 10000, xn,
+                        (t) ? "" : "in");
+                pr_info("HSIO bus clock: %d.%02dMHz\n",
+                        HSS / 1000000, (HSS % 1000000) / 10000);
+        }
+
+        return CLK;
+}
+
+/*
+ * Return the current static memory controller clock frequency
+ * in units of 10kHz
+ */
+unsigned int pxa3xx_get_memclk_frequency_10khz(void)
+{
+        unsigned long acsr;
+        unsigned int smcfs, clk = 0;
+
+        acsr = ACSR;
+
+        smcfs = (acsr >> 23) & 0x7;
+        clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
+
+        return (clk / 10000);
+}
+
+/*
+ * Return the current HSIO bus clock frequency
+ */
+static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
+{
+        unsigned long acsr;
+        unsigned int hss, hsio_clk;
+
+        acsr = ACSR;
+
+        hss = (acsr >> 14) & 0x3;
+        hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
+
+        return hsio_clk;
+}
+
+static void clk_pxa3xx_cken_enable(struct clk *clk)
+{
+        unsigned long mask = 1ul << (clk->cken & 0x1f);
+
+        local_irq_disable();
+
+        if (clk->cken < 32)
+                CKENA |= mask;
+        else
+                CKENB |= mask;
+
+        local_irq_enable();
+}
+
+static void clk_pxa3xx_cken_disable(struct clk *clk)
+{
+        unsigned long mask = 1ul << (clk->cken & 0x1f);
+
+        local_irq_disable();
+
+        if (clk->cken < 32)
+                CKENA &= ~mask;
+        else
+                CKENB &= ~mask;
+
+        local_irq_enable();
+}
+
+static const struct clkops clk_pxa3xx_hsio_ops = {
+        .enable         = clk_pxa3xx_cken_enable,
+        .disable        = clk_pxa3xx_cken_disable,
+        .getrate        = clk_pxa3xx_hsio_getrate,
+};
+
+static struct clk pxa3xx_clks[] = {
+        INIT_CK("LCDCLK", LCD,    &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
+        INIT_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL),
+
+        INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
+        INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
+        INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
+
+        INIT_CKEN("I2CCLK",  I2C,  32842000, 0, &pxa_device_i2c.dev),
+        INIT_CKEN("UDCCLK",  UDC,  48000000, 5, &pxa_device_udc.dev),
+};
+
+void __init pxa3xx_init_irq(void)
+{
+        /* enable CP6 access */
+        u32 value;
+        __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
+        value |= (1 << 6);
+        __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
+
+        pxa_init_irq_low();
+        pxa_init_irq_high();
+        pxa_init_irq_gpio(128);
+}
+
+/*
+ * device registration specific to PXA3xx.
+ */
+
+static struct platform_device *devices[] __initdata = {
+        &pxa_device_mci,
+        &pxa_device_udc,
+        &pxa_device_fb,
+        &pxa_device_ffuart,
+        &pxa_device_btuart,
+        &pxa_device_stuart,
+        &pxa_device_i2c,
+        &pxa_device_i2s,
+        &pxa_device_ficp,
+        &pxa_device_rtc,
+};
+
+static int __init pxa3xx_init(void)
+{
+        int ret = 0;
+
+        if (cpu_is_pxa3xx()) {
+                clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));
+
+                if ((ret = pxa_init_dma(32)))
+                        return ret;
+
+                return platform_add_devices(devices, ARRAY_SIZE(devices));
+        }
+        return 0;
+}
+
+subsys_initcall(pxa3xx_init);
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 98d27e646b09..ec4286c7931c 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -16,10 +16,48 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/clockchips.h>
+#include <linux/sched.h>
 
+#include <asm/div64.h>
+#include <asm/cnt32_to_63.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/mach-types.h>
+
+/*
+ * This is PXA's sched_clock implementation. This has a resolution
+ * of at least 308 ns and a maximum value of 208 days.
+ *
+ * The return value is guaranteed to be monotonic in that range as
+ * long as there is always less than 582 seconds between successive
+ * calls to sched_clock() which should always be the case in practice.
+ */
+
+#define OSCR2NS_SCALE_FACTOR 10
+
+static unsigned long oscr2ns_scale;
+
+static void __init set_oscr2ns_scale(unsigned long oscr_rate)
+{
+        unsigned long long v = 1000000000ULL << OSCR2NS_SCALE_FACTOR;
+        do_div(v, oscr_rate);
+        oscr2ns_scale = v;
+        /*
+         * We want an even value to automatically clear the top bit
+         * returned by cnt32_to_63() without an additional run time
+         * instruction. So if the LSB is 1 then round it up.
+         */
+        if (oscr2ns_scale & 1)
+                oscr2ns_scale++;
+}
+
+unsigned long long sched_clock(void)
+{
+        unsigned long long v = cnt32_to_63(OSCR);
+        return (v * oscr2ns_scale) >> OSCR2NS_SCALE_FACTOR;
+}
+
 
 static irqreturn_t
 pxa_ost0_interrupt(int irq, void *dev_id)
@@ -149,18 +187,29 @@ static struct irqaction pxa_ost0_irq = {
 
 static void __init pxa_timer_init(void)
 {
+        unsigned long clock_tick_rate;
+
         OIER = 0;
         OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
 
+        if (cpu_is_pxa21x() || cpu_is_pxa25x())
+                clock_tick_rate = 3686400;
+        else if (machine_is_mainstone())
+                clock_tick_rate = 3249600;
+        else
+                clock_tick_rate = 3250000;
+
+        set_oscr2ns_scale(clock_tick_rate);
+
         ckevt_pxa_osmr0.mult =
-                div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
+                div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
         ckevt_pxa_osmr0.max_delta_ns =
                 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
         ckevt_pxa_osmr0.min_delta_ns =
                 clockevent_delta2ns(MIN_OSCR_DELTA, &ckevt_pxa_osmr0) + 1;
 
         cksrc_pxa_oscr0.mult =
-                clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_pxa_oscr0.shift);
+                clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift);
 
         setup_irq(IRQ_OST0, &pxa_ost0_irq);
 
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
new file mode 100644
index 000000000000..3f18d760dd1b
--- /dev/null
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -0,0 +1,184 @@
+/*
+ * linux/arch/arm/mach-pxa/zylonite.c
+ *
+ * Support for the PXA3xx Development Platform (aka Zylonite)
+ *
+ * Copyright (C) 2006 Marvell International Ltd.
+ *
+ * 2007-09-04: eric miao <eric.y.miao@gmail.com>
+ *             rewrite to align with latest kernel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pxafb.h>
+#include <asm/arch/zylonite.h>
+
+#include "generic.h"
+
+int gpio_backlight;
+int gpio_eth_irq;
+
+int lcd_id;
+int lcd_orientation;
+
+static struct resource smc91x_resources[] = {
+        [0] = {
+                .start  = ZYLONITE_ETH_PHYS + 0x300,
+                .end    = ZYLONITE_ETH_PHYS + 0xfffff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = -1,   /* for run-time assignment */
+                .end    = -1,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static struct platform_device smc91x_device = {
+        .name           = "smc91x",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(smc91x_resources),
+        .resource       = smc91x_resources,
+};
+
+#if defined(CONFIG_FB_PXA) || (CONFIG_FB_PXA_MODULES)
+static void zylonite_backlight_power(int on)
+{
+        gpio_set_value(gpio_backlight, on);
+}
+
+static struct pxafb_mode_info toshiba_ltm035a776c_mode = {
+        .pixclock               = 110000,
+        .xres                   = 240,
+        .yres                   = 320,
+        .bpp                    = 16,
+        .hsync_len              = 4,
+        .left_margin            = 6,
+        .right_margin           = 4,
+        .vsync_len              = 2,
+        .upper_margin           = 2,
+        .lower_margin           = 3,
+        .sync                   = FB_SYNC_VERT_HIGH_ACT,
+};
+
+static struct pxafb_mode_info toshiba_ltm04c380k_mode = {
+        .pixclock               = 50000,
+        .xres                   = 640,
+        .yres                   = 480,
+        .bpp                    = 16,
+        .hsync_len              = 1,
+        .left_margin            = 0x9f,
+        .right_margin           = 1,
+        .vsync_len              = 44,
+        .upper_margin           = 0,
+        .lower_margin           = 0,
+        .sync                   = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
+};
+
+static struct pxafb_mach_info zylonite_toshiba_lcd_info = {
+        .num_modes              = 1,
+        .lccr0                  = LCCR0_Act,
+        .lccr3                  = LCCR3_PCP,
+        .pxafb_backlight_power  = zylonite_backlight_power,
+};
+
+static struct pxafb_mode_info sharp_ls037_modes[] = {
+        [0] = {
+                .pixclock       = 158000,
+                .xres           = 240,
+                .yres           = 320,
+                .bpp            = 16,
+                .hsync_len      = 4,
+                .left_margin    = 39,
+                .right_margin   = 39,
+                .vsync_len      = 1,
+                .upper_margin   = 2,
+                .lower_margin   = 3,
+                .sync           = 0,
+        },
+        [1] = {
+                .pixclock       = 39700,
+                .xres           = 480,
+                .yres           = 640,
+                .bpp            = 16,
+                .hsync_len      = 8,
+                .left_margin    = 81,
+                .right_margin   = 81,
+                .vsync_len      = 1,
+                .upper_margin   = 2,
+                .lower_margin   = 7,
+                .sync           = 0,
+        },
+};
+
+static struct pxafb_mach_info zylonite_sharp_lcd_info = {
+        .modes                  = sharp_ls037_modes,
+        .num_modes              = 2,
+        .lccr0                  = LCCR0_Act,
+        .lccr3                  = LCCR3_PCP | LCCR3_HSP | LCCR3_VSP,
+        .pxafb_backlight_power  = zylonite_backlight_power,
+};
+
+static void __init zylonite_init_lcd(void)
+{
+        /* backlight GPIO: output, default on */
+        gpio_direction_output(gpio_backlight, 1);
+
+        if (lcd_id & 0x20) {
+                set_pxa_fb_info(&zylonite_sharp_lcd_info);
+                return;
+        }
+
+        /* legacy LCD panels, it would be handy here if LCD panel type can
+         * be decided at run-time
+         */
+        if (1)
+                zylonite_toshiba_lcd_info.modes = &toshiba_ltm035a776c_mode;
+        else
+                zylonite_toshiba_lcd_info.modes = &toshiba_ltm04c380k_mode;
+
+        set_pxa_fb_info(&zylonite_toshiba_lcd_info);
+}
+#else
+static inline void zylonite_init_lcd(void) {}
+#endif
+
+static void __init zylonite_init(void)
+{
+        /* board-processor specific initialization */
+        zylonite_pxa300_init();
+        zylonite_pxa320_init();
+
+        /*
+         * Note: We depend that the bootloader set
+         * the correct value to MSC register for SMC91x.
+         */
+        smc91x_resources[1].start = gpio_to_irq(gpio_eth_irq);
+        smc91x_resources[1].end   = gpio_to_irq(gpio_eth_irq);
+        platform_device_register(&smc91x_device);
+
+        zylonite_init_lcd();
+}
+
+MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
+        .phys_io        = 0x40000000,
+        .boot_params    = 0xa0000100,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa3xx_init_irq,
+        .timer          = &pxa_timer,
+        .init_machine   = zylonite_init,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c
new file mode 100644
index 000000000000..b5fbd2f4c693
--- /dev/null
+++ b/arch/arm/mach-pxa/zylonite_pxa300.c
@@ -0,0 +1,188 @@
+/*
+ * linux/arch/arm/mach-pxa/zylonite_pxa300.c
+ *
+ * PXA300/PXA310 specific support code for the
+ * PXA3xx Development Platform (aka Zylonite)
+ *
+ * Copyright (C) 2007 Marvell Internation Ltd.
+ * 2007-08-21: eric miao <eric.y.miao@gmail.com>
+ *             initial version
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/gpio.h>
+#include <asm/arch/mfp-pxa300.h>
+#include <asm/arch/zylonite.h>
+
+#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
+
+/* PXA300/PXA310 common configurations */
+static mfp_cfg_t common_mfp_cfg[] __initdata = {
+        /* LCD */
+        GPIO54_LCD_LDD_0,
+        GPIO55_LCD_LDD_1,
+        GPIO56_LCD_LDD_2,
+        GPIO57_LCD_LDD_3,
+        GPIO58_LCD_LDD_4,
+        GPIO59_LCD_LDD_5,
+        GPIO60_LCD_LDD_6,
+        GPIO61_LCD_LDD_7,
+        GPIO62_LCD_LDD_8,
+        GPIO63_LCD_LDD_9,
+        GPIO64_LCD_LDD_10,
+        GPIO65_LCD_LDD_11,
+        GPIO66_LCD_LDD_12,
+        GPIO67_LCD_LDD_13,
+        GPIO68_LCD_LDD_14,
+        GPIO69_LCD_LDD_15,
+        GPIO70_LCD_LDD_16,
+        GPIO71_LCD_LDD_17,
+        GPIO72_LCD_FCLK,
+        GPIO73_LCD_LCLK,
+        GPIO74_LCD_PCLK,
+        GPIO75_LCD_BIAS,
+        GPIO76_LCD_VSYNC,
+        GPIO127_LCD_CS_N,
+
+        /* BTUART */
+        GPIO111_UART2_RTS,
+        GPIO112_UART2_RXD,
+        GPIO113_UART2_TXD,
+        GPIO114_UART2_CTS,
+
+        /* STUART */
+        GPIO109_UART3_TXD,
+        GPIO110_UART3_RXD,
+
+        /* AC97 */
+        GPIO23_AC97_nACRESET,
+        GPIO24_AC97_SYSCLK,
+        GPIO29_AC97_BITCLK,
+        GPIO25_AC97_SDATA_IN_0,
+        GPIO27_AC97_SDATA_OUT,
+        GPIO28_AC97_SYNC,
+
+        /* Keypad */
+        GPIO107_KP_DKIN_0,
+        GPIO108_KP_DKIN_1,
+        GPIO115_KP_MKIN_0,
+        GPIO116_KP_MKIN_1,
+        GPIO117_KP_MKIN_2,
+        GPIO118_KP_MKIN_3,
+        GPIO119_KP_MKIN_4,
+        GPIO120_KP_MKIN_5,
+        GPIO2_2_KP_MKIN_6,
+        GPIO3_2_KP_MKIN_7,
+        GPIO121_KP_MKOUT_0,
+        GPIO122_KP_MKOUT_1,
+        GPIO123_KP_MKOUT_2,
+        GPIO124_KP_MKOUT_3,
+        GPIO125_KP_MKOUT_4,
+        GPIO4_2_KP_MKOUT_5,
+        GPIO5_2_KP_MKOUT_6,
+        GPIO6_2_KP_MKOUT_7,
+};
+
+static mfp_cfg_t pxa300_mfp_cfg[] __initdata = {
+        /* FFUART */
+        GPIO30_UART1_RXD,
+        GPIO31_UART1_TXD,
+        GPIO32_UART1_CTS,
+        GPIO37_UART1_RTS,
+        GPIO33_UART1_DCD,
+        GPIO34_UART1_DSR,
+        GPIO35_UART1_RI,
+        GPIO36_UART1_DTR,
+
+        /* Ethernet */
+        GPIO2_nCS3,
+        GPIO99_GPIO,
+};
+
+static mfp_cfg_t pxa310_mfp_cfg[] __initdata = {
+        /* FFUART */
+        GPIO99_UART1_RXD,
+        GPIO100_UART1_TXD,
+        GPIO101_UART1_CTS,
+        GPIO106_UART1_RTS,
+
+        /* Ethernet */
+        GPIO2_nCS3,
+        GPIO102_GPIO,
+};
+
+#define NUM_LCD_DETECT_PINS     7
+
+static int lcd_detect_pins[] __initdata = {
+        MFP_PIN_GPIO71, /* LCD_LDD_17 - ORIENT */
+        MFP_PIN_GPIO70, /* LCD_LDD_16 - LCDID[5] */
+        MFP_PIN_GPIO75, /* LCD_BIAS   - LCDID[4] */
+        MFP_PIN_GPIO73, /* LCD_LCLK   - LCDID[3] */
+        MFP_PIN_GPIO72, /* LCD_FCLK   - LCDID[2] */
+        MFP_PIN_GPIO127,/* LCD_CS_N   - LCDID[1] */
+        MFP_PIN_GPIO76, /* LCD_VSYNC  - LCDID[0] */
+};
+
+static void __init zylonite_detect_lcd_panel(void)
+{
+        unsigned long mfpr_save[NUM_LCD_DETECT_PINS];
+        int i, gpio, id = 0;
+
+        /* save the original MFP settings of these pins and configure
+         * them as GPIO Input, DS01X, Pull Neither, Edge Clear
+         */
+        for (i = 0; i < NUM_LCD_DETECT_PINS; i++) {
+                mfpr_save[i] = pxa3xx_mfp_read(lcd_detect_pins[i]);
+                pxa3xx_mfp_write(lcd_detect_pins[i], 0x8440);
+        }
+
+        for (i = 0; i < NUM_LCD_DETECT_PINS; i++) {
+                id = id << 1;
+                gpio = mfp_to_gpio(lcd_detect_pins[i]);
+                gpio_direction_input(gpio);
+
+                if (gpio_get_value(gpio))
+                        id = id | 0x1;
+        }
+
+        /* lcd id, flush out bit 1 */
+        lcd_id = id & 0x3d;
+
+        /* lcd orientation, portrait or landscape */
+        lcd_orientation = (id >> 6) & 0x1;
+
+        /* restore the original MFP settings */
+        for (i = 0; i < NUM_LCD_DETECT_PINS; i++)
+                pxa3xx_mfp_write(lcd_detect_pins[i], mfpr_save[i]);
+}
+
+void __init zylonite_pxa300_init(void)
+{
+        if (cpu_is_pxa300() || cpu_is_pxa310()) {
+                /* initialize MFP */
+                pxa3xx_mfp_config(ARRAY_AND_SIZE(common_mfp_cfg));
+
+                /* detect LCD panel */
+                zylonite_detect_lcd_panel();
+
+                /* GPIO pin assignment */
+                gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO20);
+        }
+
+        if (cpu_is_pxa300()) {
+                pxa3xx_mfp_config(ARRAY_AND_SIZE(pxa300_mfp_cfg));
+                gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO99);
+        }
+
+        if (cpu_is_pxa310()) {
+                pxa3xx_mfp_config(ARRAY_AND_SIZE(pxa310_mfp_cfg));
+                gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO102);
+        }
+}
diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c
new file mode 100644
index 000000000000..63cb36be086b
--- /dev/null
+++ b/arch/arm/mach-pxa/zylonite_pxa320.c
@@ -0,0 +1,173 @@
+/*
+ * linux/arch/arm/mach-pxa/zylonite_pxa320.c
+ *
+ * PXA320 specific support code for the
+ * PXA3xx Development Platform (aka Zylonite)
+ *
+ * Copyright (C) 2007 Marvell Internation Ltd.
+ * 2007-08-21: eric miao <eric.y.miao@gmail.com>
+ *             initial version
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/arch/gpio.h>
+#include <asm/arch/mfp-pxa320.h>
+#include <asm/arch/zylonite.h>
+
+#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
+
+static mfp_cfg_t mfp_cfg[] __initdata = {
+        /* LCD */
+        GPIO6_2_LCD_LDD_0,
+        GPIO7_2_LCD_LDD_1,
+        GPIO8_2_LCD_LDD_2,
+        GPIO9_2_LCD_LDD_3,
+        GPIO10_2_LCD_LDD_4,
+        GPIO11_2_LCD_LDD_5,
+        GPIO12_2_LCD_LDD_6,
+        GPIO13_2_LCD_LDD_7,
+        GPIO63_LCD_LDD_8,
+        GPIO64_LCD_LDD_9,
+        GPIO65_LCD_LDD_10,
+        GPIO66_LCD_LDD_11,
+        GPIO67_LCD_LDD_12,
+        GPIO68_LCD_LDD_13,
+        GPIO69_LCD_LDD_14,
+        GPIO70_LCD_LDD_15,
+        GPIO71_LCD_LDD_16,
+        GPIO72_LCD_LDD_17,
+        GPIO73_LCD_CS_N,
+        GPIO74_LCD_VSYNC,
+        GPIO14_2_LCD_FCLK,
+        GPIO15_2_LCD_LCLK,
+        GPIO16_2_LCD_PCLK,
+        GPIO17_2_LCD_BIAS,
+
+        /* FFUART */
+        GPIO41_UART1_RXD,
+        GPIO42_UART1_TXD,
+        GPIO43_UART1_CTS,
+        GPIO44_UART1_DCD,
+        GPIO45_UART1_DSR,
+        GPIO46_UART1_RI,
+        GPIO47_UART1_DTR,
+        GPIO48_UART1_RTS,
+
+        /* AC97 */
+        GPIO34_AC97_SYSCLK,
+        GPIO35_AC97_SDATA_IN_0,
+        GPIO37_AC97_SDATA_OUT,
+        GPIO38_AC97_SYNC,
+        GPIO39_AC97_BITCLK,
+        GPIO40_AC97_nACRESET,
+
+        /* I2C */
+        GPIO32_I2C_SCL,
+        GPIO33_I2C_SDA,
+
+        /* Keypad */
+        GPIO105_KP_DKIN_0,
+        GPIO106_KP_DKIN_1,
+        GPIO113_KP_MKIN_0,
+        GPIO114_KP_MKIN_1,
+        GPIO115_KP_MKIN_2,
+        GPIO116_KP_MKIN_3,
+        GPIO117_KP_MKIN_4,
+        GPIO118_KP_MKIN_5,
+        GPIO119_KP_MKIN_6,
+        GPIO120_KP_MKIN_7,
+        GPIO121_KP_MKOUT_0,
+        GPIO122_KP_MKOUT_1,
+        GPIO123_KP_MKOUT_2,
+        GPIO124_KP_MKOUT_3,
+        GPIO125_KP_MKOUT_4,
+        GPIO126_KP_MKOUT_5,
+        GPIO127_KP_MKOUT_6,
+        GPIO5_2_KP_MKOUT_7,
+
+        /* Ethernet */
+        GPIO4_nCS3,
+        GPIO90_GPIO,
+};
+
+#define NUM_LCD_DETECT_PINS     7
+
+static int lcd_detect_pins[] __initdata = {
+        MFP_PIN_GPIO72,   /* LCD_LDD_17 - ORIENT */
+        MFP_PIN_GPIO71,   /* LCD_LDD_16 - LCDID[5] */
+        MFP_PIN_GPIO17_2, /* LCD_BIAS   - LCDID[4] */
+        MFP_PIN_GPIO15_2, /* LCD_LCLK   - LCDID[3] */
+        MFP_PIN_GPIO14_2, /* LCD_FCLK   - LCDID[2] */
+        MFP_PIN_GPIO73,   /* LCD_CS_N   - LCDID[1] */
+        MFP_PIN_GPIO74,   /* LCD_VSYNC  - LCDID[0] */
+        /*
+         * set the MFP_PIN_GPIO 14/15/17 to alternate function other than
+         * GPIO to avoid input level confliction with 14_2, 15_2, 17_2
+         */
+        MFP_PIN_GPIO14,
+        MFP_PIN_GPIO15,
+        MFP_PIN_GPIO17,
+};
+
+static int lcd_detect_mfpr[] __initdata = {
+        /* AF0, DS 1X, Pull Neither, Edge Clear */
+        0x8440, 0x8440, 0x8440, 0x8440, 0x8440, 0x8440, 0x8440,
+        0xc442, /* Backlight, Pull-Up, AF2 */
+        0x8445, /* AF5 */
+        0x8445, /* AF5 */
+};
+
+static void __init zylonite_detect_lcd_panel(void)
+{
+        unsigned long mfpr_save[ARRAY_SIZE(lcd_detect_pins)];
+        int i, gpio, id = 0;
+
+        /* save the original MFP settings of these pins and configure them
+         * as GPIO Input, DS01X, Pull Neither, Edge Clear
+         */
+        for (i = 0; i < ARRAY_SIZE(lcd_detect_pins); i++) {
+                mfpr_save[i] = pxa3xx_mfp_read(lcd_detect_pins[i]);
+                pxa3xx_mfp_write(lcd_detect_pins[i], lcd_detect_mfpr[i]);
+        }
+
+        for (i = 0; i < NUM_LCD_DETECT_PINS; i++) {
+                id = id << 1;
+                gpio = mfp_to_gpio(lcd_detect_pins[i]);
+                gpio_direction_input(gpio);
+
+                if (gpio_get_value(gpio))
+                        id = id | 0x1;
+        }
+
+        /* lcd id, flush out bit 1 */
+        lcd_id = id & 0x3d;
+
+        /* lcd orientation, portrait or landscape */
+        lcd_orientation = (id >> 6) & 0x1;
+
+        /* restore the original MFP settings */
+        for (i = 0; i < ARRAY_SIZE(lcd_detect_pins); i++)
+                pxa3xx_mfp_write(lcd_detect_pins[i], mfpr_save[i]);
+}
+
+void __init zylonite_pxa320_init(void)
+{
+        if (cpu_is_pxa320()) {
+                /* initialize MFP */
+                pxa3xx_mfp_config(ARRAY_AND_SIZE(mfp_cfg));
+
+                /* detect LCD panel */
+                zylonite_detect_lcd_panel();
+
+                /* GPIO pin assignment */
+                gpio_backlight  = mfp_to_gpio(MFP_PIN_GPIO14);
+                gpio_eth_irq    = mfp_to_gpio(MFP_PIN_GPIO9);
+        }
+}
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 12161ae445da..7868f4dc1d00 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -322,7 +322,7 @@ config CPU_SA1100
 # XScale
 config CPU_XSCALE
         bool
-        depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000
+        depends on ARCH_IOP32X || ARCH_IOP33X || PXA25x || PXA27x || ARCH_IXP4XX || ARCH_IXP2000
         default y
         select CPU_32v5
         select CPU_ABRT_EV5T
@@ -333,7 +333,7 @@ config CPU_XSCALE
 # XScale Core Version 3
 config CPU_XSC3
         bool
-        depends on ARCH_IXP23XX || ARCH_IOP13XX
+        depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx
         default y
         select CPU_32v5
         select CPU_ABRT_EV5T
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index bb5466b27b59..00fad11733ad 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -31,6 +31,8 @@
 #include <linux/interrupt.h>
 #include <linux/i2c-pxa.h>
 #include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
 
 #include <asm/hardware.h>
 #include <asm/irq.h>
@@ -48,6 +50,7 @@ struct pxa_i2c {
         unsigned int            slave_addr;
 
         struct i2c_adapter      adap;
+        struct clk              *clk;
 #ifdef CONFIG_I2C_PXA_SLAVE
         struct i2c_slave_client *slave;
 #endif
@@ -869,6 +872,12 @@ static int i2c_pxa_probe(struct platform_device *dev)
 
         sprintf(i2c->adap.name, "pxa_i2c-i2c.%u", dev->id);
 
+        i2c->clk = clk_get(&dev->dev, "I2CCLK");
+        if (IS_ERR(i2c->clk)) {
+                ret = PTR_ERR(i2c->clk);
+                goto eclk;
+        }
+
         i2c->reg_base = ioremap(res->start, res_len(res));
         if (!i2c->reg_base) {
                 ret = -EIO;
@@ -889,22 +898,19 @@ static int i2c_pxa_probe(struct platform_device *dev)
         }
 #endif
 
+        clk_enable(i2c->clk);
+#ifdef CONFIG_PXA27x
         switch (dev->id) {
         case 0:
-#ifdef CONFIG_PXA27x
                 pxa_gpio_mode(GPIO117_I2CSCL_MD);
                 pxa_gpio_mode(GPIO118_I2CSDA_MD);
-#endif
-                pxa_set_cken(CKEN_I2C, 1);
                 break;
-#ifdef CONFIG_PXA27x
         case 1:
                 local_irq_disable();
                 PCFR |= PCFR_PI2CEN;
                 local_irq_enable();
-                pxa_set_cken(CKEN_PWRI2C, 1);
-#endif
         }
+#endif
 
         ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED,
                           i2c->adap.name, i2c);
@@ -948,19 +954,18 @@ static int i2c_pxa_probe(struct platform_device *dev)
 eadapt:
         free_irq(irq, i2c);
 ereqirq:
-        switch (dev->id) {
-        case 0:
-                pxa_set_cken(CKEN_I2C, 0);
-                break;
+        clk_disable(i2c->clk);
+
 #ifdef CONFIG_PXA27x
-        case 1:
-                pxa_set_cken(CKEN_PWRI2C, 0);
+        if (dev->id == 1) {
                 local_irq_disable();
                 PCFR &= ~PCFR_PI2CEN;
                 local_irq_enable();
-#endif
         }
+#endif
 eremap:
+        clk_put(i2c->clk);
+eclk:
         kfree(i2c);
 emalloc:
         release_mem_region(res->start, res_len(res));
@@ -975,18 +980,18 @@ static int i2c_pxa_remove(struct platform_device *dev)
 
         i2c_del_adapter(&i2c->adap);
         free_irq(i2c->irq, i2c);
-        switch (dev->id) {
-        case 0:
-                pxa_set_cken(CKEN_I2C, 0);
-                break;
+
+        clk_disable(i2c->clk);
+        clk_put(i2c->clk);
+
 #ifdef CONFIG_PXA27x
-        case 1:
-                pxa_set_cken(CKEN_PWRI2C, 0);
+        if (dev->id == 1) {
                 local_irq_disable();
                 PCFR &= ~PCFR_PI2CEN;
                 local_irq_enable();
-#endif
         }
+#endif
+
         release_mem_region(i2c->iobase, i2c->iosize);
         kfree(i2c);
 
diff --git a/drivers/input/keyboard/pxa27x_keyboard.c b/drivers/input/keyboard/pxa27x_keyboard.c
index ebe5eacf2990..b7061aa38816 100644
--- a/drivers/input/keyboard/pxa27x_keyboard.c
+++ b/drivers/input/keyboard/pxa27x_keyboard.c
@@ -23,6 +23,8 @@
 #include <linux/input.h>
 #include <linux/device.h>
 #include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -40,6 +42,8 @@
                                  col/2 == 2 ? KPASMKP2 : KPASMKP3)
 #define KPASMKPx_MKC(row, col)  (1 << (row + 16 * (col % 2)))
 
+static struct clk *pxakbd_clk;
+
 static irqreturn_t pxakbd_irq_handler(int irq, void *dev_id)
 {
         struct platform_device *pdev = dev_id;
@@ -104,7 +108,7 @@ static int pxakbd_open(struct input_dev *dev)
         KPREC = 0x7F;
 
         /* Enable unit clock */
-        pxa_set_cken(CKEN_KEYPAD, 1);
+        clk_enable(pxakbd_clk);
 
         return 0;
 }
@@ -112,7 +116,7 @@ static int pxakbd_open(struct input_dev *dev)
 static void pxakbd_close(struct input_dev *dev)
 {
         /* Disable clock unit */
-        pxa_set_cken(CKEN_KEYPAD, 0);
+        clk_disable(pxakbd_clk);
 }
 
 #ifdef CONFIG_PM
@@ -140,7 +144,8 @@ static int pxakbd_resume(struct platform_device *pdev)
                 KPREC = pdata->reg_kprec;
 
                 /* Enable unit clock */
-                pxa_set_cken(CKEN_KEYPAD, 1);
+                clk_disable(pxakbd_clk);
+                clk_enable(pxakbd_clk);
         }
 
         mutex_unlock(&input_dev->mutex);
@@ -158,11 +163,18 @@ static int __devinit pxakbd_probe(struct platform_device *pdev)
         struct input_dev *input_dev;
         int i, row, col, error;
 
+        pxakbd_clk = clk_get(&pdev->dev, "KBDCLK");
+        if (IS_ERR(pxakbd_clk)) {
+                error = PTR_ERR(pxakbd_clk);
+                goto err_clk;
+        }
+
         /* Create and register the input driver. */
         input_dev = input_allocate_device();
         if (!input_dev) {
                 printk(KERN_ERR "Cannot request keypad device\n");
-                return -ENOMEM;
+                error = -ENOMEM;
+                goto err_alloc;
         }
 
         input_dev->name = DRIVER_NAME;
@@ -185,7 +197,6 @@ static int __devinit pxakbd_probe(struct platform_device *pdev)
                             DRIVER_NAME, pdev);
         if (error) {
                 printk(KERN_ERR "Cannot request keypad IRQ\n");
-                pxa_set_cken(CKEN_KEYPAD, 0);
                 goto err_free_dev;
         }
 
@@ -217,6 +228,9 @@ static int __devinit pxakbd_probe(struct platform_device *pdev)
         free_irq(IRQ_KEYPAD, pdev);
  err_free_dev:
         input_free_device(input_dev);
+ err_alloc:
+        clk_put(pxakbd_clk);
+ err_clk:
         return error;
 }
 
@@ -226,6 +240,7 @@ static int __devexit pxakbd_remove(struct platform_device *pdev)
 
         input_unregister_device(input_dev);
         free_irq(IRQ_KEYPAD, pdev);
+        clk_put(pxakbd_clk);
         platform_set_drvdata(pdev, NULL);
 
         return 0;
diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index 3cb23210b912..257b44094e4c 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -108,6 +108,12 @@ config LEDS_GPIO
           outputs. To be useful the particular board must have LEDs
           and they must be connected to the GPIO lines.
 
+config LEDS_CM_X270
+        tristate "LED Support for the CM-X270 LEDs"
+        depends on LEDS_CLASS && MACH_ARMCORE
+        help
+          This option enables support for the CM-X270 LEDs.
+
 comment "LED Triggers"
 
 config LEDS_TRIGGERS
diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
index d2ca1abbc3d2..a60de1b46c2c 100644
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_LEDS_H1940)		+= leds-h1940.o
 obj-$(CONFIG_LEDS_COBALT_QUBE)          += leds-cobalt-qube.o
 obj-$(CONFIG_LEDS_COBALT_RAQ)           += leds-cobalt-raq.o
 obj-$(CONFIG_LEDS_GPIO)                 += leds-gpio.o
+obj-$(CONFIG_LEDS_CM_X270)              += leds-cm-x270.o
 
 # LED Triggers
 obj-$(CONFIG_LEDS_TRIGGER_TIMER)        += ledtrig-timer.o
diff --git a/drivers/leds/leds-cm-x270.c b/drivers/leds/leds-cm-x270.c
new file mode 100644
index 000000000000..9aebef02a974
--- /dev/null
+++ b/drivers/leds/leds-cm-x270.c
@@ -0,0 +1,122 @@
+/*
+ * drivers/leds/leds-cm-x270.c
+ *
+ * Copyright 2007 CompuLab Ltd.
+ * Author: Mike Rapoport <mike@compulab.co.il>
+ *
+ * Based on leds-corgi.c
+ * Author: Richard Purdie <rpurdie@openedhand.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/pxa-regs.h>
+
+#define GPIO_RED_LED                    (93)
+#define GPIO_GREEN_LED                  (94)
+
+static void cmx270_red_set(struct led_classdev *led_cdev,
+                           enum led_brightness value)
+{
+        if (value)
+                GPCR(GPIO_RED_LED) = GPIO_bit(GPIO_RED_LED);
+        else
+                GPSR(GPIO_RED_LED) = GPIO_bit(GPIO_RED_LED);
+}
+
+static void cmx270_green_set(struct led_classdev *led_cdev,
+                             enum led_brightness value)
+{
+        if (value)
+                GPCR(GPIO_GREEN_LED) = GPIO_bit(GPIO_GREEN_LED);
+        else
+                GPSR(GPIO_GREEN_LED) = GPIO_bit(GPIO_GREEN_LED);
+}
+
+static struct led_classdev cmx270_red_led = {
+        .name                   = "cm-x270:red",
+        .default_trigger        = "nand-disk",
+        .brightness_set         = cmx270_red_set,
+};
+
+static struct led_classdev cmx270_green_led = {
+        .name                   = "cm-x270:green",
+        .default_trigger        = "heartbeat",
+        .brightness_set         = cmx270_green_set,
+};
+
+#ifdef CONFIG_PM
+static int cmx270led_suspend(struct platform_device *dev, pm_message_t state)
+{
+        led_classdev_suspend(&cmx270_red_led);
+        led_classdev_suspend(&cmx270_green_led);
+        return 0;
+}
+
+static int cmx270led_resume(struct platform_device *dev)
+{
+        led_classdev_resume(&cmx270_red_led);
+        led_classdev_resume(&cmx270_green_led);
+        return 0;
+}
+#endif
+
+static int cmx270led_probe(struct platform_device *pdev)
+{
+        int ret;
+
+        ret = led_classdev_register(&pdev->dev, &cmx270_red_led);
+        if (ret < 0)
+                return ret;
+
+        ret = led_classdev_register(&pdev->dev, &cmx270_green_led);
+        if (ret < 0)
+                led_classdev_unregister(&cmx270_red_led);
+
+        return ret;
+}
+
+static int cmx270led_remove(struct platform_device *pdev)
+{
+        led_classdev_unregister(&cmx270_red_led);
+        led_classdev_unregister(&cmx270_green_led);
+        return 0;
+}
+
+static struct platform_driver cmx270led_driver = {
+        .probe          = cmx270led_probe,
+        .remove         = cmx270led_remove,
+#ifdef CONFIG_PM
+        .suspend        = cmx270led_suspend,
+        .resume         = cmx270led_resume,
+#endif
+        .driver         = {
+                .name           = "cm-x270-led",
+        },
+};
+
+static int __init cmx270led_init(void)
+{
+        return platform_driver_register(&cmx270led_driver);
+}
+
+static void __exit cmx270led_exit(void)
+{
+        platform_driver_unregister(&cmx270led_driver);
+}
+
+module_init(cmx270led_init);
+module_exit(cmx270led_exit);
+
+MODULE_AUTHOR("Mike Rapoport <mike@compulab.co.il>");
+MODULE_DESCRIPTION("CM-x270 LED driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
index 657901eecfce..0601e01aa2c2 100644
--- a/drivers/mmc/host/pxamci.c
+++ b/drivers/mmc/host/pxamci.c
@@ -23,6 +23,8 @@
 #include <linux/delay.h>
 #include <linux/interrupt.h>
 #include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/err.h>
 #include <linux/mmc/host.h>
 
 #include <asm/dma.h>
@@ -44,6 +46,8 @@ struct pxamci_host {
         spinlock_t              lock;
         struct resource         *res;
         void __iomem            *base;
+        struct clk              *clk;
+        unsigned long           clkrate;
         int                     irq;
         int                     dma;
         unsigned int            clkrt;
@@ -119,7 +123,7 @@ static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
         writel(nob, host->base + MMC_NOB);
         writel(data->blksz, host->base + MMC_BLKLEN);
 
-        clks = (unsigned long long)data->timeout_ns * CLOCKRATE;
+        clks = (unsigned long long)data->timeout_ns * host->clkrate;
         do_div(clks, 1000000000UL);
         timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
         writel((timeout + 255) / 256, host->base + MMC_RDTO);
@@ -365,18 +369,25 @@ static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
         struct pxamci_host *host = mmc_priv(mmc);
 
         if (ios->clock) {
-                unsigned int clk = CLOCKRATE / ios->clock;
-                if (CLOCKRATE / clk > ios->clock)
+                unsigned long rate = host->clkrate;
+                unsigned int clk = rate / ios->clock;
+
+                /*
+                 * clk might result in a lower divisor than we
+                 * desire.  check for that condition and adjust
+                 * as appropriate.
+                 */
+                if (rate / clk > ios->clock)
                         clk <<= 1;
                 host->clkrt = fls(clk) - 1;
-                pxa_set_cken(CKEN_MMC, 1);
+                clk_enable(host->clk);
 
                 /*
                  * we write clkrt on the next command
                  */
         } else {
                 pxamci_stop_clock(host);
-                pxa_set_cken(CKEN_MMC, 0);
+                clk_disable(host->clk);
         }
 
         if (host->power_mode != ios->power_mode) {
@@ -462,8 +473,6 @@ static int pxamci_probe(struct platform_device *pdev)
         }
 
         mmc->ops = &pxamci_ops;
-        mmc->f_min = CLOCKRATE_MIN;
-        mmc->f_max = CLOCKRATE_MAX;
 
         /*
          * We can do SG-DMA, but we don't because we never know how much
@@ -490,6 +499,22 @@ static int pxamci_probe(struct platform_device *pdev)
         host->mmc = mmc;
         host->dma = -1;
         host->pdata = pdev->dev.platform_data;
+
+        host->clk = clk_get(&pdev->dev, "MMCCLK");
+        if (IS_ERR(host->clk)) {
+                ret = PTR_ERR(host->clk);
+                host->clk = NULL;
+                goto out;
+        }
+
+        host->clkrate = clk_get_rate(host->clk);
+
+        /*
+         * Calculate minimum clock rate, rounding up.
+         */
+        mmc->f_min = (host->clkrate + 63) / 64;
+        mmc->f_max = host->clkrate;
+
         mmc->ocr_avail = host->pdata ?
                          host->pdata->ocr_mask :
                          MMC_VDD_32_33|MMC_VDD_33_34;
@@ -554,6 +579,8 @@ static int pxamci_probe(struct platform_device *pdev)
                         iounmap(host->base);
                 if (host->sg_cpu)
                         dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
+                if (host->clk)
+                        clk_put(host->clk);
         }
         if (mmc)
                 mmc_free_host(mmc);
@@ -588,6 +615,8 @@ static int pxamci_remove(struct platform_device *pdev)
                 iounmap(host->base);
                 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
 
+                clk_put(host->clk);
+
                 release_resource(host->res);
 
                 mmc_free_host(mmc);
diff --git a/drivers/mmc/host/pxamci.h b/drivers/mmc/host/pxamci.h
index 3153e779d46a..748c7706f237 100644
--- a/drivers/mmc/host/pxamci.h
+++ b/drivers/mmc/host/pxamci.h
@@ -88,17 +88,3 @@
 #define MMC_RXFIFO      0x0040  /* 8 bit */
 
 #define MMC_TXFIFO      0x0044  /* 8 bit */
-
-/*
- * The base MMC clock rate
- */
-#ifdef CONFIG_PXA27x
-#define CLOCKRATE_MIN   304688
-#define CLOCKRATE_MAX   19500000
-#else
-#define CLOCKRATE_MIN   312500
-#define CLOCKRATE_MAX   20000000
-#endif
-
-#define CLOCKRATE       CLOCKRATE_MAX
-
diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c
index 55ff0fbe525a..8c09344f58dc 100644
--- a/drivers/net/irda/pxaficp_ir.c
+++ b/drivers/net/irda/pxaficp_ir.c
@@ -23,6 +23,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <linux/pm.h>
+#include <linux/clk.h>
 
 #include <net/irda/irda.h>
 #include <net/irda/irmod.h>
@@ -87,8 +88,30 @@ struct pxa_irda {
 
         struct device           *dev;
         struct pxaficp_platform_data *pdata;
+        struct clk              *fir_clk;
+        struct clk              *sir_clk;
+        struct clk              *cur_clk;
 };
 
+static inline void pxa_irda_disable_clk(struct pxa_irda *si)
+{
+        if (si->cur_clk)
+                clk_disable(si->cur_clk);
+        si->cur_clk = NULL;
+}
+
+static inline void pxa_irda_enable_firclk(struct pxa_irda *si)
+{
+        si->cur_clk = si->fir_clk;
+        clk_enable(si->fir_clk);
+}
+
+static inline void pxa_irda_enable_sirclk(struct pxa_irda *si)
+{
+        si->cur_clk = si->sir_clk;
+        clk_enable(si->sir_clk);
+}
+
 
 #define IS_FIR(si)              ((si)->speed >= 4000000)
 #define IRDA_FRAME_SIZE_LIMIT   2047
@@ -134,7 +157,7 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed)
                         DCSR(si->rxdma) &= ~DCSR_RUN;
                         /* disable FICP */
                         ICCR0 = 0;
-                        pxa_set_cken(CKEN_FICP, 0);
+                        pxa_irda_disable_clk(si);
 
                         /* set board transceiver to SIR mode */
                         si->pdata->transceiver_mode(si->dev, IR_SIRMODE);
@@ -144,7 +167,7 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed)
                         pxa_gpio_mode(GPIO47_STTXD_MD);
 
                         /* enable the STUART clock */
-                        pxa_set_cken(CKEN_STUART, 1);
+                        pxa_irda_enable_sirclk(si);
                 }
 
                 /* disable STUART first */
@@ -169,7 +192,7 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed)
                 /* disable STUART */
                 STIER = 0;
                 STISR = 0;
-                pxa_set_cken(CKEN_STUART, 0);
+                pxa_irda_disable_clk(si);
 
                 /* disable FICP first */
                 ICCR0 = 0;
@@ -182,7 +205,7 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed)
                 pxa_gpio_mode(GPIO47_ICPTXD_MD);
 
                 /* enable the FICP clock */
-                pxa_set_cken(CKEN_FICP, 1);
+                pxa_irda_enable_firclk(si);
 
                 si->speed = speed;
                 pxa_irda_fir_dma_rx_start(si);
@@ -592,16 +615,15 @@ static void pxa_irda_shutdown(struct pxa_irda *si)
         STIER = 0;
         /* disable STUART SIR mode */
         STISR = 0;
-        /* disable the STUART clock */
-        pxa_set_cken(CKEN_STUART, 0);
 
         /* disable DMA */
         DCSR(si->txdma) &= ~DCSR_RUN;
         DCSR(si->rxdma) &= ~DCSR_RUN;
         /* disable FICP */
         ICCR0 = 0;
-        /* disable the FICP clock */
-        pxa_set_cken(CKEN_FICP, 0);
+
+        /* disable the STUART or FICP clocks */
+        pxa_irda_disable_clk(si);
 
         DRCMR17 = 0;
         DRCMR18 = 0;
@@ -792,6 +814,13 @@ static int pxa_irda_probe(struct platform_device *pdev)
         si->dev = &pdev->dev;
         si->pdata = pdev->dev.platform_data;
 
+        si->sir_clk = clk_get(&pdev->dev, "UARTCLK");
+        si->fir_clk = clk_get(&pdev->dev, "FICPCLK");
+        if (IS_ERR(si->sir_clk) || IS_ERR(si->fir_clk)) {
+                err = PTR_ERR(IS_ERR(si->sir_clk) ? si->sir_clk : si->fir_clk);
+                goto err_mem_4;
+        }
+
         /*
          * Initialise the SIR buffers
          */
@@ -831,6 +860,10 @@ static int pxa_irda_probe(struct platform_device *pdev)
 err_mem_5:
                 kfree(si->rx_buff.head);
 err_mem_4:
+                if (si->sir_clk && !IS_ERR(si->sir_clk))
+                        clk_put(si->sir_clk);
+                if (si->fir_clk && !IS_ERR(si->fir_clk))
+                        clk_put(si->fir_clk);
                 free_netdev(dev);
 err_mem_3:
                 release_mem_region(__PREG(FICP), 0x1c);
@@ -850,6 +883,8 @@ static int pxa_irda_remove(struct platform_device *_dev)
                 unregister_netdev(dev);
                 kfree(si->tx_buff.head);
                 kfree(si->rx_buff.head);
+                clk_put(si->fir_clk);
+                clk_put(si->sir_clk);
                 free_netdev(dev);
         }
 
diff --git a/drivers/net/smc91x.c b/drivers/net/smc91x.c
index 24e610e711e8..7da7589d45dd 100644
--- a/drivers/net/smc91x.c
+++ b/drivers/net/smc91x.c
@@ -173,49 +173,6 @@ MODULE_LICENSE("GPL");
  */
 #define MII_DELAY               1
 
-/* store this information for the driver.. */
-struct smc_local {
-        /*
-         * If I have to wait until memory is available to send a
-         * packet, I will store the skbuff here, until I get the
-         * desired memory.  Then, I'll send it out and free it.
-         */
-        struct sk_buff *pending_tx_skb;
-        struct tasklet_struct tx_task;
-
-        /* version/revision of the SMC91x chip */
-        int     version;
-
-        /* Contains the current active transmission mode */
-        int     tcr_cur_mode;
-
-        /* Contains the current active receive mode */
-        int     rcr_cur_mode;
-
-        /* Contains the current active receive/phy mode */
-        int     rpc_cur_mode;
-        int     ctl_rfduplx;
-        int     ctl_rspeed;
-
-        u32     msg_enable;
-        u32     phy_type;
-        struct mii_if_info mii;
-
-        /* work queue */
-        struct work_struct phy_configure;
-        struct net_device *dev;
-        int     work_pending;
-
-        spinlock_t lock;
-
-#ifdef SMC_USE_PXA_DMA
-        /* DMA needs the physical address of the chip */
-        u_long physaddr;
-#endif
-        void __iomem *base;
-        void __iomem *datacs;
-};
-
 #if SMC_DEBUG > 0
 #define DBG(n, args...)                                 \
         do {                                            \
@@ -2215,17 +2172,19 @@ static int smc_drv_probe(struct platform_device *pdev)
                 goto out_release_attrib;
         }
 
-        platform_set_drvdata(pdev, ndev);
-        ret = smc_probe(ndev, addr);
-        if (ret != 0)
-                goto out_iounmap;
 #ifdef SMC_USE_PXA_DMA
-        else {
+        {
                 struct smc_local *lp = netdev_priv(ndev);
+                lp->device = &pdev->dev;
                 lp->physaddr = res->start;
         }
 #endif
 
+        platform_set_drvdata(pdev, ndev);
+        ret = smc_probe(ndev, addr);
+        if (ret != 0)
+                goto out_iounmap;
+
         smc_request_datacs(pdev, ndev);
 
         return 0;
diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h
index af9e6bf59552..729fd28c08b5 100644
--- a/drivers/net/smc91x.h
+++ b/drivers/net/smc91x.h
@@ -462,6 +462,52 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r,
 
 #endif
 
+
+/* store this information for the driver.. */
+struct smc_local {
+        /*
+         * If I have to wait until memory is available to send a
+         * packet, I will store the skbuff here, until I get the
+         * desired memory.  Then, I'll send it out and free it.
+         */
+        struct sk_buff *pending_tx_skb;
+        struct tasklet_struct tx_task;
+
+        /* version/revision of the SMC91x chip */
+        int     version;
+
+        /* Contains the current active transmission mode */
+        int     tcr_cur_mode;
+
+        /* Contains the current active receive mode */
+        int     rcr_cur_mode;
+
+        /* Contains the current active receive/phy mode */
+        int     rpc_cur_mode;
+        int     ctl_rfduplx;
+        int     ctl_rspeed;
+
+        u32     msg_enable;
+        u32     phy_type;
+        struct mii_if_info mii;
+
+        /* work queue */
+        struct work_struct phy_configure;
+        struct net_device *dev;
+        int     work_pending;
+
+        spinlock_t lock;
+
+#ifdef SMC_USE_PXA_DMA
+        /* DMA needs the physical address of the chip */
+        u_long physaddr;
+        struct device *device;
+#endif
+        void __iomem *base;
+        void __iomem *datacs;
+};
+
+
 #ifdef SMC_USE_PXA_DMA
 /*
  * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
@@ -476,11 +522,12 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r,
 #ifdef SMC_insl
 #undef SMC_insl
 #define SMC_insl(a, r, p, l) \
-        smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l)
+        smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
 static inline void
-smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
+smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
                  u_char *buf, int len)
 {
+        u_long physaddr = lp->physaddr;
         dma_addr_t dmabuf;
 
         /* fallback if no DMA available */
@@ -497,7 +544,7 @@ smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
         }
 
         len *= 4;
-        dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
+        dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
         DCSR(dma) = DCSR_NODESC;
         DTADR(dma) = dmabuf;
         DSADR(dma) = physaddr + reg;
@@ -507,18 +554,19 @@ smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
         while (!(DCSR(dma) & DCSR_STOPSTATE))
                 cpu_relax();
         DCSR(dma) = 0;
-        dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
+        dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
 }
 #endif
 
 #ifdef SMC_insw
 #undef SMC_insw
 #define SMC_insw(a, r, p, l) \
-        smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l)
+        smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
 static inline void
-smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
+smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
                  u_char *buf, int len)
 {
+        u_long physaddr = lp->physaddr;
         dma_addr_t dmabuf;
 
         /* fallback if no DMA available */
@@ -535,7 +583,7 @@ smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
         }
 
         len *= 2;
-        dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
+        dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
         DCSR(dma) = DCSR_NODESC;
         DTADR(dma) = dmabuf;
         DSADR(dma) = physaddr + reg;
@@ -545,7 +593,7 @@ smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
         while (!(DCSR(dma) & DCSR_STOPSTATE))
                 cpu_relax();
         DCSR(dma) = 0;
-        dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
+        dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
 }
 #endif
 
diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
index 4276965517f2..dc7a4cb5d270 100644
--- a/drivers/pcmcia/Makefile
+++ b/drivers/pcmcia/Makefile
@@ -69,4 +69,5 @@ sa1100_cs-$(CONFIG_SA1100_SIMPAD)		+= sa1100_simpad.o
 pxa2xx_cs-$(CONFIG_ARCH_LUBBOCK)                += pxa2xx_lubbock.o sa1111_generic.o
 pxa2xx_cs-$(CONFIG_MACH_MAINSTONE)              += pxa2xx_mainstone.o
 pxa2xx_cs-$(CONFIG_PXA_SHARPSL)                 += pxa2xx_sharpsl.o
+pxa2xx_cs-$(CONFIG_MACH_ARMCORE)                += pxa2xx_cm_x270.o
 
diff --git a/drivers/pcmcia/pxa2xx_cm_x270.c b/drivers/pcmcia/pxa2xx_cm_x270.c
new file mode 100644
index 000000000000..fbf2f3a6984c
--- /dev/null
+++ b/drivers/pcmcia/pxa2xx_cm_x270.c
@@ -0,0 +1,175 @@
+/*
+ * linux/drivers/pcmcia/pxa/pxa_cm_x270.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Compulab Ltd., 2003, 2007
+ * Mike Rapoport <mike@compulab.co.il>
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+
+#include <pcmcia/ss.h>
+#include <asm/hardware.h>
+
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/cm-x270.h>
+
+#include "soc_common.h"
+
+static struct pcmcia_irqs irqs[] = {
+        { 0, PCMCIA_S0_CD_VALID, "PCMCIA0 CD" },
+        { 1, PCMCIA_S1_CD_VALID, "PCMCIA1 CD" },
+};
+
+static int cmx270_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
+{
+        GPSR(GPIO48_nPOE) = GPIO_bit(GPIO48_nPOE) |
+                GPIO_bit(GPIO49_nPWE) |
+                GPIO_bit(GPIO50_nPIOR) |
+                GPIO_bit(GPIO51_nPIOW) |
+                GPIO_bit(GPIO85_nPCE_1) |
+                GPIO_bit(GPIO54_nPCE_2);
+
+        pxa_gpio_mode(GPIO48_nPOE_MD);
+        pxa_gpio_mode(GPIO49_nPWE_MD);
+        pxa_gpio_mode(GPIO50_nPIOR_MD);
+        pxa_gpio_mode(GPIO51_nPIOW_MD);
+        pxa_gpio_mode(GPIO85_nPCE_1_MD);
+        pxa_gpio_mode(GPIO54_nPCE_2_MD);
+        pxa_gpio_mode(GPIO55_nPREG_MD);
+        pxa_gpio_mode(GPIO56_nPWAIT_MD);
+        pxa_gpio_mode(GPIO57_nIOIS16_MD);
+
+        /* Reset signal */
+        pxa_gpio_mode(GPIO53_nPCE_2 | GPIO_OUT);
+        GPCR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
+
+        set_irq_type(PCMCIA_S0_CD_VALID, IRQ_TYPE_EDGE_BOTH);
+        set_irq_type(PCMCIA_S1_CD_VALID, IRQ_TYPE_EDGE_BOTH);
+
+        /* irq's for slots: */
+        set_irq_type(PCMCIA_S0_RDYINT, IRQ_TYPE_EDGE_FALLING);
+        set_irq_type(PCMCIA_S1_RDYINT, IRQ_TYPE_EDGE_FALLING);
+
+        skt->irq = (skt->nr == 0) ? PCMCIA_S0_RDYINT : PCMCIA_S1_RDYINT;
+        return soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs));
+}
+
+static void cmx270_pcmcia_shutdown(struct soc_pcmcia_socket *skt)
+{
+        soc_pcmcia_free_irqs(skt, irqs, ARRAY_SIZE(irqs));
+
+        set_irq_type(IRQ_TO_GPIO(PCMCIA_S0_CD_VALID), IRQ_TYPE_NONE);
+        set_irq_type(IRQ_TO_GPIO(PCMCIA_S1_CD_VALID), IRQ_TYPE_NONE);
+
+        set_irq_type(IRQ_TO_GPIO(PCMCIA_S0_RDYINT), IRQ_TYPE_NONE);
+        set_irq_type(IRQ_TO_GPIO(PCMCIA_S1_RDYINT), IRQ_TYPE_NONE);
+}
+
+
+static void cmx270_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
+                                       struct pcmcia_state *state)
+{
+        state->detect = (PCC_DETECT(skt->nr) == 0) ? 1 : 0;
+        state->ready  = (PCC_READY(skt->nr) == 0) ? 0 : 1;
+        state->bvd1   = 1;
+        state->bvd2   = 1;
+        state->vs_3v  = 0;
+        state->vs_Xv  = 0;
+        state->wrprot = 0;  /* not available */
+}
+
+
+static int cmx270_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
+                                          const socket_state_t *state)
+{
+        GPSR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
+        pxa_gpio_mode(GPIO49_nPWE | GPIO_OUT);
+
+        switch (skt->nr) {
+        case 0:
+                if (state->flags & SS_RESET) {
+                        GPCR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
+                        GPSR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
+                        udelay(10);
+                        GPCR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
+                        GPSR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
+                }
+                break;
+        case 1:
+                if (state->flags & SS_RESET) {
+                        GPCR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
+                        GPSR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
+                        udelay(10);
+                        GPCR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
+                        GPSR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
+                }
+                break;
+        }
+
+        pxa_gpio_mode(GPIO49_nPWE_MD);
+
+        return 0;
+}
+
+static void cmx270_pcmcia_socket_init(struct soc_pcmcia_socket *skt)
+{
+}
+
+static void cmx270_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
+{
+}
+
+
+static struct pcmcia_low_level cmx270_pcmcia_ops = {
+        .owner                  = THIS_MODULE,
+        .hw_init                = cmx270_pcmcia_hw_init,
+        .hw_shutdown            = cmx270_pcmcia_shutdown,
+        .socket_state           = cmx270_pcmcia_socket_state,
+        .configure_socket       = cmx270_pcmcia_configure_socket,
+        .socket_init            = cmx270_pcmcia_socket_init,
+        .socket_suspend         = cmx270_pcmcia_socket_suspend,
+        .nr                     = 2,
+};
+
+static struct platform_device *cmx270_pcmcia_device;
+
+static int __init cmx270_pcmcia_init(void)
+{
+        int ret;
+
+        cmx270_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1);
+
+        if (!cmx270_pcmcia_device)
+                return -ENOMEM;
+
+        cmx270_pcmcia_device->dev.platform_data = &cmx270_pcmcia_ops;
+
+        printk(KERN_INFO "Registering cm-x270 PCMCIA interface.\n");
+        ret = platform_device_add(cmx270_pcmcia_device);
+
+        if (ret)
+                platform_device_put(cmx270_pcmcia_device);
+
+        return ret;
+}
+
+static void __exit cmx270_pcmcia_exit(void)
+{
+        platform_device_unregister(cmx270_pcmcia_device);
+}
+
+module_init(cmx270_pcmcia_init);
+module_exit(cmx270_pcmcia_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Mike Rapoport <mike@compulab.co.il>");
+MODULE_DESCRIPTION("CM-x270 PCMCIA driver");
diff --git a/drivers/pcmcia/pxa2xx_lubbock.c b/drivers/pcmcia/pxa2xx_lubbock.c
index 5e9b9a3fd027..1510d6cde3e2 100644
--- a/drivers/pcmcia/pxa2xx_lubbock.c
+++ b/drivers/pcmcia/pxa2xx_lubbock.c
@@ -30,35 +30,6 @@
 #include "sa1111_generic.h"
 
 static int
-lubbock_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
-{
-        /*
-         * Setup default state of GPIO outputs
-         * before we enable them as outputs.
-         */
-        GPSR(GPIO48_nPOE) =
-                GPIO_bit(GPIO48_nPOE) |
-                GPIO_bit(GPIO49_nPWE) |
-                GPIO_bit(GPIO50_nPIOR) |
-                GPIO_bit(GPIO51_nPIOW) |
-                GPIO_bit(GPIO52_nPCE_1) |
-                GPIO_bit(GPIO53_nPCE_2);
-
-        pxa_gpio_mode(GPIO48_nPOE_MD);
-        pxa_gpio_mode(GPIO49_nPWE_MD);
-        pxa_gpio_mode(GPIO50_nPIOR_MD);
-        pxa_gpio_mode(GPIO51_nPIOW_MD);
-        pxa_gpio_mode(GPIO52_nPCE_1_MD);
-        pxa_gpio_mode(GPIO53_nPCE_2_MD);
-        pxa_gpio_mode(GPIO54_pSKTSEL_MD);
-        pxa_gpio_mode(GPIO55_nPREG_MD);
-        pxa_gpio_mode(GPIO56_nPWAIT_MD);
-        pxa_gpio_mode(GPIO57_nIOIS16_MD);
-
-        return sa1111_pcmcia_hw_init(skt);
-}
-
-static int
 lubbock_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
                                 const socket_state_t *state)
 {
@@ -230,7 +201,7 @@ lubbock_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
 
 static struct pcmcia_low_level lubbock_pcmcia_ops = {
         .owner                  = THIS_MODULE,
-        .hw_init                = lubbock_pcmcia_hw_init,
+        .hw_init                = sa1111_pcmcia_hw_init,
         .hw_shutdown            = sa1111_pcmcia_hw_shutdown,
         .socket_state           = sa1111_pcmcia_socket_state,
         .configure_socket       = lubbock_pcmcia_configure_socket,
diff --git a/drivers/pcmcia/pxa2xx_mainstone.c b/drivers/pcmcia/pxa2xx_mainstone.c
index 383107ba4bd3..36c671c5fb65 100644
--- a/drivers/pcmcia/pxa2xx_mainstone.c
+++ b/drivers/pcmcia/pxa2xx_mainstone.c
@@ -43,24 +43,6 @@ static int mst_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
          * Setup default state of GPIO outputs
          * before we enable them as outputs.
          */
-        GPSR(GPIO48_nPOE) =
-                GPIO_bit(GPIO48_nPOE) |
-                GPIO_bit(GPIO49_nPWE) |
-                GPIO_bit(GPIO50_nPIOR) |
-                GPIO_bit(GPIO51_nPIOW) |
-                GPIO_bit(GPIO85_nPCE_1) |
-                GPIO_bit(GPIO54_nPCE_2);
-
-        pxa_gpio_mode(GPIO48_nPOE_MD);
-        pxa_gpio_mode(GPIO49_nPWE_MD);
-        pxa_gpio_mode(GPIO50_nPIOR_MD);
-        pxa_gpio_mode(GPIO51_nPIOW_MD);
-        pxa_gpio_mode(GPIO85_nPCE_1_MD);
-        pxa_gpio_mode(GPIO54_nPCE_2_MD);
-        pxa_gpio_mode(GPIO79_pSKTSEL_MD);
-        pxa_gpio_mode(GPIO55_nPREG_MD);
-        pxa_gpio_mode(GPIO56_nPWAIT_MD);
-        pxa_gpio_mode(GPIO57_nIOIS16_MD);
 
         skt->irq = (skt->nr == 0) ? MAINSTONE_S0_IRQ : MAINSTONE_S1_IRQ;
         return soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs));
diff --git a/drivers/serial/pxa.c b/drivers/serial/pxa.c
index e9c6cb391a23..af3a011b2b24 100644
--- a/drivers/serial/pxa.c
+++ b/drivers/serial/pxa.c
@@ -42,6 +42,7 @@
 #include <linux/tty.h>
 #include <linux/tty_flip.h>
 #include <linux/serial_core.h>
+#include <linux/clk.h>
 
 #include <asm/io.h>
 #include <asm/hardware.h>
@@ -55,7 +56,7 @@ struct uart_pxa_port {
         unsigned char           lcr;
         unsigned char           mcr;
         unsigned int            lsr_break_flag;
-        unsigned int            cken;
+        struct clk              *clk;
         char                    *name;
 };
 
@@ -351,6 +352,8 @@ static int serial_pxa_startup(struct uart_port *port)
         else
                 up->mcr = 0;
 
+        up->port.uartclk = clk_get_rate(up->clk);
+
         /*
          * Allocate the IRQ
          */
@@ -546,9 +549,11 @@ serial_pxa_pm(struct uart_port *port, unsigned int state,
               unsigned int oldstate)
 {
         struct uart_pxa_port *up = (struct uart_pxa_port *)port;
-        pxa_set_cken(up->cken, !state);
+
         if (!state)
-                udelay(1);
+                clk_enable(up->clk);
+        else
+                clk_disable(up->clk);
 }
 
 static void serial_pxa_release_port(struct uart_port *port)
@@ -582,7 +587,7 @@ serial_pxa_type(struct uart_port *port)
 
 #ifdef CONFIG_SERIAL_PXA_CONSOLE
 
-static struct uart_pxa_port serial_pxa_ports[];
+static struct uart_pxa_port *serial_pxa_ports[4];
 static struct uart_driver serial_pxa_reg;
 
 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
@@ -632,9 +637,11 @@ static void serial_pxa_console_putchar(struct uart_port *port, int ch)
 static void
 serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
 {
-        struct uart_pxa_port *up = &serial_pxa_ports[co->index];
+        struct uart_pxa_port *up = serial_pxa_ports[co->index];
         unsigned int ier;
 
+        clk_enable(up->clk);
+
         /*
          *      First save the IER then disable the interrupts
          */
@@ -649,6 +656,8 @@ serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
          */
         wait_for_xmitr(up);
         serial_out(up, UART_IER, ier);
+
+        clk_disable(up->clk);
 }
 
 static int __init
@@ -662,7 +671,9 @@ serial_pxa_console_setup(struct console *co, char *options)
 
         if (co->index == -1 || co->index >= serial_pxa_reg.nr)
                 co->index = 0;
-        up = &serial_pxa_ports[co->index];
+        up = serial_pxa_ports[co->index];
+        if (!up)
+                return -ENODEV;
 
         if (options)
                 uart_parse_options(options, &baud, &parity, &bits, &flow);
@@ -680,15 +691,6 @@ static struct console serial_pxa_console = {
         .data           = &serial_pxa_reg,
 };
 
-static int __init
-serial_pxa_console_init(void)
-{
-        register_console(&serial_pxa_console);
-        return 0;
-}
-
-console_initcall(serial_pxa_console_init);
-
 #define PXA_CONSOLE     &serial_pxa_console
 #else
 #define PXA_CONSOLE     NULL
@@ -714,73 +716,13 @@ struct uart_ops serial_pxa_pops = {
         .verify_port    = serial_pxa_verify_port,
 };
 
-static struct uart_pxa_port serial_pxa_ports[] = {
-     {  /* FFUART */
-        .name   = "FFUART",
-        .cken   = CKEN_FFUART,
-        .port   = {
-                .type           = PORT_PXA,
-                .iotype         = UPIO_MEM,
-                .membase        = (void *)&FFUART,
-                .mapbase        = __PREG(FFUART),
-                .irq            = IRQ_FFUART,
-                .uartclk        = 921600 * 16,
-                .fifosize       = 64,
-                .ops            = &serial_pxa_pops,
-                .line           = 0,
-        },
-  }, {  /* BTUART */
-        .name   = "BTUART",
-        .cken   = CKEN_BTUART,
-        .port   = {
-                .type           = PORT_PXA,
-                .iotype         = UPIO_MEM,
-                .membase        = (void *)&BTUART,
-                .mapbase        = __PREG(BTUART),
-                .irq            = IRQ_BTUART,
-                .uartclk        = 921600 * 16,
-                .fifosize       = 64,
-                .ops            = &serial_pxa_pops,
-                .line           = 1,
-        },
-  }, {  /* STUART */
-        .name   = "STUART",
-        .cken   = CKEN_STUART,
-        .port   = {
-                .type           = PORT_PXA,
-                .iotype         = UPIO_MEM,
-                .membase        = (void *)&STUART,
-                .mapbase        = __PREG(STUART),
-                .irq            = IRQ_STUART,
-                .uartclk        = 921600 * 16,
-                .fifosize       = 64,
-                .ops            = &serial_pxa_pops,
-                .line           = 2,
-        },
-  }, {  /* HWUART */
-        .name   = "HWUART",
-        .cken   = CKEN_HWUART,
-        .port = {
-                .type           = PORT_PXA,
-                .iotype         = UPIO_MEM,
-                .membase        = (void *)&HWUART,
-                .mapbase        = __PREG(HWUART),
-                .irq            = IRQ_HWUART,
-                .uartclk        = 921600 * 16,
-                .fifosize       = 64,
-                .ops            = &serial_pxa_pops,
-                .line           = 3,
-        },
-  }
-};
-
 static struct uart_driver serial_pxa_reg = {
         .owner          = THIS_MODULE,
         .driver_name    = "PXA serial",
         .dev_name       = "ttyS",
         .major          = TTY_MAJOR,
         .minor          = 64,
-        .nr             = ARRAY_SIZE(serial_pxa_ports),
+        .nr             = 4,
         .cons           = PXA_CONSOLE,
 };
 
@@ -806,10 +748,68 @@ static int serial_pxa_resume(struct platform_device *dev)
 
 static int serial_pxa_probe(struct platform_device *dev)
 {
-        serial_pxa_ports[dev->id].port.dev = &dev->dev;
-        uart_add_one_port(&serial_pxa_reg, &serial_pxa_ports[dev->id].port);
-        platform_set_drvdata(dev, &serial_pxa_ports[dev->id]);
+        struct uart_pxa_port *sport;
+        struct resource *mmres, *irqres;
+        int ret;
+
+        mmres = platform_get_resource(dev, IORESOURCE_MEM, 0);
+        irqres = platform_get_resource(dev, IORESOURCE_IRQ, 0);
+        if (!mmres || !irqres)
+                return -ENODEV;
+
+        sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL);
+        if (!sport)
+                return -ENOMEM;
+
+        sport->clk = clk_get(&dev->dev, "UARTCLK");
+        if (IS_ERR(sport->clk)) {
+                ret = PTR_ERR(sport->clk);
+                goto err_free;
+        }
+
+        sport->port.type = PORT_PXA;
+        sport->port.iotype = UPIO_MEM;
+        sport->port.mapbase = mmres->start;
+        sport->port.irq = irqres->start;
+        sport->port.fifosize = 64;
+        sport->port.ops = &serial_pxa_pops;
+        sport->port.line = dev->id;
+        sport->port.dev = &dev->dev;
+        sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
+        sport->port.uartclk = clk_get_rate(sport->clk);
+
+        /*
+         * Is it worth keeping this?
+         */
+        if (mmres->start == __PREG(FFUART))
+                sport->name = "FFUART";
+        else if (mmres->start == __PREG(BTUART))
+                sport->name = "BTUART";
+        else if (mmres->start == __PREG(STUART))
+                sport->name = "STUART";
+        else if (mmres->start == __PREG(HWUART))
+                sport->name = "HWUART";
+        else
+                sport->name = "???";
+
+        sport->port.membase = ioremap(mmres->start, mmres->end - mmres->start + 1);
+        if (!sport->port.membase) {
+                ret = -ENOMEM;
+                goto err_clk;
+        }
+
+        serial_pxa_ports[dev->id] = sport;
+
+        uart_add_one_port(&serial_pxa_reg, &sport->port);
+        platform_set_drvdata(dev, sport);
+
         return 0;
+
+ err_clk:
+        clk_put(sport->clk);
+ err_free:
+        kfree(sport);
+        return ret;
 }
 
 static int serial_pxa_remove(struct platform_device *dev)
@@ -818,8 +818,9 @@ static int serial_pxa_remove(struct platform_device *dev)
 
         platform_set_drvdata(dev, NULL);
 
-        if (sport)
-                uart_remove_one_port(&serial_pxa_reg, &sport->port);
+        uart_remove_one_port(&serial_pxa_reg, &sport->port);
+        clk_put(sport->clk);
+        kfree(sport);
 
         return 0;
 }
diff --git a/drivers/serial/serial_core.c b/drivers/serial/serial_core.c
index a055f58f342f..a3bd3a3f41f3 100644
--- a/drivers/serial/serial_core.c
+++ b/drivers/serial/serial_core.c
@@ -2127,6 +2127,14 @@ uart_configure_port(struct uart_driver *drv, struct uart_state *state,
                 spin_unlock_irqrestore(&port->lock, flags);
 
                 /*
+                 * If this driver supports console, and it hasn't been
+                 * successfully registered yet, try to re-register it.
+                 * It may be that the port was not available.
+                 */
+                if (port->cons && !(port->cons->flags & CON_ENABLED))
+                        register_console(port->cons);
+
+                /*
                  * Power down all ports by default, except the
                  * console if we have one.
                  */
@@ -2286,6 +2294,7 @@ int uart_add_one_port(struct uart_driver *drv, struct uart_port *port)
         }
 
         state->port = port;
+        state->pm_state = -1;
 
         port->cons = drv->cons;
         port->info = state->info;
@@ -2308,15 +2317,6 @@ int uart_add_one_port(struct uart_driver *drv, struct uart_port *port)
         tty_register_device(drv->tty_driver, port->line, port->dev);
 
         /*
-         * If this driver supports console, and it hasn't been
-         * successfully registered yet, try to re-register it.
-         * It may be that the port was not available.
-         */
-        if (port->type != PORT_UNKNOWN &&
-            port->cons && !(port->cons->flags & CON_ENABLED))
-                register_console(port->cons);
-
-        /*
          * Ensure UPF_DEAD is not set.
          */
         port->flags &= ~UPF_DEAD;
diff --git a/drivers/usb/gadget/pxa2xx_udc.c b/drivers/usb/gadget/pxa2xx_udc.c
index 1407ad1c8128..90d0d086b9b8 100644
--- a/drivers/usb/gadget/pxa2xx_udc.c
+++ b/drivers/usb/gadget/pxa2xx_udc.c
@@ -43,6 +43,8 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/irq.h>
+#include <linux/clk.h>
+#include <linux/err.h>
 
 #include <asm/byteorder.h>
 #include <asm/dma.h>
@@ -1157,7 +1159,7 @@ static void udc_disable(struct pxa2xx_udc *dev)
 
 #ifdef  CONFIG_ARCH_PXA
         /* Disable clock for USB device */
-        pxa_set_cken(CKEN_USB, 0);
+        clk_disable(dev->clk);
 #endif
 
         ep0_idle (dev);
@@ -1202,8 +1204,7 @@ static void udc_enable (struct pxa2xx_udc *dev)
 
 #ifdef  CONFIG_ARCH_PXA
         /* Enable clock for USB device */
-        pxa_set_cken(CKEN_USB, 1);
-        udelay(5);
+        clk_enable(dev->clk);
 #endif
 
         /* try to clear these bits before we enable the udc */
@@ -2137,6 +2138,14 @@ static int __init pxa2xx_udc_probe(struct platform_device *pdev)
         if (irq < 0)
                 return -ENODEV;
 
+#ifdef  CONFIG_ARCH_PXA
+        dev->clk = clk_get(&pdev->dev, "UDCCLK");
+        if (IS_ERR(dev->clk)) {
+                retval = PTR_ERR(dev->clk);
+                goto err_clk;
+        }
+#endif
+
         pr_debug("%s: IRQ %d%s%s\n", driver_name, irq,
                 dev->has_cfr ? "" : " (!cfr)",
                 SIZE_STR "(pio)"
@@ -2152,11 +2161,10 @@ static int __init pxa2xx_udc_probe(struct platform_device *pdev)
                         dev_dbg(&pdev->dev,
                                 "can't get vbus gpio %d, err: %d\n",
                                 dev->mach->gpio_vbus, retval);
-                        return -EBUSY;
+                        goto err_gpio_vbus;
                 }
                 gpio_direction_input(dev->mach->gpio_vbus);
                 vbus_irq = gpio_to_irq(dev->mach->gpio_vbus);
-                set_irq_type(vbus_irq, IRQT_BOTHEDGE);
         } else
                 vbus_irq = 0;
 
@@ -2166,9 +2174,7 @@ static int __init pxa2xx_udc_probe(struct platform_device *pdev)
                         dev_dbg(&pdev->dev,
                                 "can't get pullup gpio %d, err: %d\n",
                                 dev->mach->gpio_pullup, retval);
-                        if (dev->mach->gpio_vbus)
-                                gpio_free(dev->mach->gpio_vbus);
-                        return -EBUSY;
+                        goto err_gpio_pullup;
                 }
                 gpio_direction_output(dev->mach->gpio_pullup, 0);
         }
@@ -2195,11 +2201,7 @@ static int __init pxa2xx_udc_probe(struct platform_device *pdev)
         if (retval != 0) {
                 printk(KERN_ERR "%s: can't get irq %d, err %d\n",
                         driver_name, irq, retval);
-                if (dev->mach->gpio_pullup)
-                        gpio_free(dev->mach->gpio_pullup);
-                if (dev->mach->gpio_vbus)
-                        gpio_free(dev->mach->gpio_vbus);
-                return -EBUSY;
+                goto err_irq1;
         }
         dev->got_irq = 1;
 
@@ -2213,12 +2215,7 @@ static int __init pxa2xx_udc_probe(struct platform_device *pdev)
                         printk(KERN_ERR "%s: can't get irq %i, err %d\n",
                                 driver_name, LUBBOCK_USB_DISC_IRQ, retval);
 lubbock_fail0:
-                        free_irq(irq, dev);
-                        if (dev->mach->gpio_pullup)
-                                gpio_free(dev->mach->gpio_pullup);
-                        if (dev->mach->gpio_vbus)
-                                gpio_free(dev->mach->gpio_vbus);
-                        return -EBUSY;
+                        goto err_irq_lub;
                 }
                 retval = request_irq(LUBBOCK_USB_IRQ,
                                 lubbock_vbus_irq,
@@ -2234,22 +2231,37 @@ lubbock_fail0:
 #endif
         if (vbus_irq) {
                 retval = request_irq(vbus_irq, udc_vbus_irq,
-                                IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
+                                IRQF_DISABLED | IRQF_SAMPLE_RANDOM |
+                                IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
                                 driver_name, dev);
                 if (retval != 0) {
                         printk(KERN_ERR "%s: can't get irq %i, err %d\n",
                                 driver_name, vbus_irq, retval);
-                        free_irq(irq, dev);
-                        if (dev->mach->gpio_pullup)
-                                gpio_free(dev->mach->gpio_pullup);
-                        if (dev->mach->gpio_vbus)
-                                gpio_free(dev->mach->gpio_vbus);
-                        return -EBUSY;
+                        goto err_vbus_irq;
                 }
         }
         create_proc_files();
 
         return 0;
+
+ err_vbus_irq:
+#ifdef  CONFIG_ARCH_LUBBOCK
+        free_irq(LUBBOCK_USB_DISC_IRQ, dev);
+ err_irq_lub:
+#endif
+        free_irq(irq, dev);
+ err_irq1:
+        if (dev->mach->gpio_pullup)
+                gpio_free(dev->mach->gpio_pullup);
+ err_gpio_pullup:
+        if (dev->mach->gpio_vbus)
+                gpio_free(dev->mach->gpio_vbus);
+ err_gpio_vbus:
+#ifdef  CONFIG_ARCH_PXA
+        clk_put(dev->clk);
+ err_clk:
+#endif
+        return retval;
 }
 
 static void pxa2xx_udc_shutdown(struct platform_device *_dev)
@@ -2284,6 +2296,10 @@ static int __exit pxa2xx_udc_remove(struct platform_device *pdev)
         if (dev->mach->gpio_pullup)
                 gpio_free(dev->mach->gpio_pullup);
 
+#ifdef  CONFIG_ARCH_PXA
+        clk_put(dev->clk);
+#endif
+
         platform_set_drvdata(pdev, NULL);
         the_controller = NULL;
         return 0;
diff --git a/drivers/usb/gadget/pxa2xx_udc.h b/drivers/usb/gadget/pxa2xx_udc.h
index 0e5d0e6fb0e2..1db46d705777 100644
--- a/drivers/usb/gadget/pxa2xx_udc.h
+++ b/drivers/usb/gadget/pxa2xx_udc.h
@@ -125,6 +125,7 @@ struct pxa2xx_udc {
         struct timer_list                       timer;
 
         struct device                           *dev;
+        struct clk                              *clk;
         struct pxa2xx_udc_mach_info             *mach;
         u64                                     dma_mask;
         struct pxa2xx_ep                        ep [PXA_UDC_NUM_ENDPOINTS];
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index a280a52f8efe..f9b12ab59642 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c
@@ -37,6 +37,8 @@
 #include <linux/cpufreq.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/err.h>
 
 #include <asm/hardware.h>
 #include <asm/io.h>
@@ -506,15 +508,15 @@ static struct fb_ops pxafb_ops = {
  *
  * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
  */
-static inline unsigned int get_pcd(unsigned int pixclock)
+static inline unsigned int get_pcd(struct pxafb_info *fbi, unsigned int pixclock)
 {
         unsigned long long pcd;
 
         /* FIXME: Need to take into account Double Pixel Clock mode
-         * (DPC) bit? or perhaps set it based on the various clock
-         * speeds */
-
-        pcd = (unsigned long long)get_lcdclk_frequency_10khz() * pixclock;
+         * (DPC) bit? or perhaps set it based on the various clock
+         * speeds */
+        pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
+        pcd *= pixclock;
         do_div(pcd, 100000000 * 2);
         /* no need for this, since we should subtract 1 anyway. they cancel */
         /* pcd += 1; */ /* make up for integer math truncations */
@@ -523,19 +525,21 @@ static inline unsigned int get_pcd(unsigned int pixclock)
 
 /*
  * Some touchscreens need hsync information from the video driver to
- * function correctly. We export it here.
+ * function correctly. We export it here.  Note that 'hsync_time' and
+ * the value returned from pxafb_get_hsync_time() is the *reciprocal*
+ * of the hsync period in seconds.
  */
 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
 {
-        unsigned long long htime;
+        unsigned long htime;
 
         if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
                 fbi->hsync_time=0;
                 return;
         }
 
-        htime = (unsigned long long)get_lcdclk_frequency_10khz() * 10000;
-        do_div(htime, pcd * fbi->fb.var.hsync_len);
+        htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
+
         fbi->hsync_time = htime;
 }
 
@@ -560,7 +564,7 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *
 {
         struct pxafb_lcd_reg new_regs;
         u_long flags;
-        u_int lines_per_panel, pcd = get_pcd(var->pixclock);
+        u_int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
 
         pr_debug("pxafb: Configuring PXA LCD\n");
 
@@ -803,7 +807,7 @@ static void pxafb_enable_controller(struct pxafb_info *fbi)
         pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
 
         /* enable LCD controller clock */
-        pxa_set_cken(CKEN_LCD, 1);
+        clk_enable(fbi->clk);
 
         /* Sequence from 11.7.10 */
         LCCR3 = fbi->reg_lccr3;
@@ -840,7 +844,7 @@ static void pxafb_disable_controller(struct pxafb_info *fbi)
         remove_wait_queue(&fbi->ctrlr_wait, &wait);
 
         /* disable LCD controller clock */
-        pxa_set_cken(CKEN_LCD, 0);
+        clk_disable(fbi->clk);
 }
 
 /*
@@ -994,7 +998,7 @@ pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
                 break;
 
         case CPUFREQ_POSTCHANGE:
-                pcd = get_pcd(fbi->fb.var.pixclock);
+                pcd = get_pcd(fbi, fbi->fb.var.pixclock);
                 set_hsync_time(fbi, pcd);
                 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
                 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
@@ -1119,6 +1123,12 @@ static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
         memset(fbi, 0, sizeof(struct pxafb_info));
         fbi->dev = dev;
 
+        fbi->clk = clk_get(dev, "LCDCLK");
+        if (IS_ERR(fbi->clk)) {
+                kfree(fbi);
+                return NULL;
+        }
+
         strcpy(fbi->fb.fix.id, PXA_NAME);
 
         fbi->fb.fix.type        = FB_TYPE_PACKED_PIXELS;
diff --git a/drivers/video/pxafb.h b/drivers/video/pxafb.h
index 7499a1c4bf79..f8605b807b0a 100644
--- a/drivers/video/pxafb.h
+++ b/drivers/video/pxafb.h
@@ -40,6 +40,7 @@ struct pxafb_dma_descriptor {
 struct pxafb_info {
         struct fb_info          fb;
         struct device           *dev;
+        struct clk              *clk;
 
         /*
          * These are the addresses we mapped
diff --git a/include/asm-arm/arch-pxa/cm-x270.h b/include/asm-arm/arch-pxa/cm-x270.h
new file mode 100644
index 000000000000..f8fac9e18009
--- /dev/null
+++ b/include/asm-arm/arch-pxa/cm-x270.h
@@ -0,0 +1,50 @@
+/*
+ * linux/include/asm/arch-pxa/cm-x270.h
+ *
+ * Copyright Compulab Ltd., 2003, 2007
+ * Mike Rapoport <mike@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+/* CM-x270 device physical addresses */
+#define CMX270_CS1_PHYS         (PXA_CS1_PHYS)
+#define MARATHON_PHYS           (PXA_CS2_PHYS)
+#define CMX270_IDE104_PHYS      (PXA_CS3_PHYS)
+#define CMX270_IT8152_PHYS      (PXA_CS4_PHYS)
+
+/* Statically mapped regions */
+#define CMX270_VIRT_BASE                (0xe8000000)
+#define CMX270_IT8152_VIRT              (CMX270_VIRT_BASE)
+#define CMX270_IDE104_VIRT              (CMX270_IT8152_VIRT + SZ_64M)
+
+/* GPIO related definitions */
+#define GPIO_IT8152_IRQ                 (22)
+
+#define IRQ_GPIO_IT8152_IRQ     IRQ_GPIO(GPIO_IT8152_IRQ)
+#define PME_IRQ                 IRQ_GPIO(0)
+#define CMX270_IDE_IRQ          IRQ_GPIO(100)
+#define CMX270_GPIRQ1           IRQ_GPIO(101)
+#define CMX270_TOUCHIRQ         IRQ_GPIO(96)
+#define CMX270_ETHIRQ           IRQ_GPIO(10)
+#define CMX270_GFXIRQ           IRQ_GPIO(95)
+#define CMX270_NANDIRQ          IRQ_GPIO(89)
+#define CMX270_MMC_IRQ          IRQ_GPIO(83)
+
+/* PCMCIA related definitions */
+#define PCC_DETECT(x)   (GPLR(84 - (x)) & GPIO_bit(84 - (x)))
+#define PCC_READY(x)    (GPLR(82 - (x)) & GPIO_bit(82 - (x)))
+
+#define PCMCIA_S0_CD_VALID              IRQ_GPIO(84)
+#define PCMCIA_S0_CD_VALID_EDGE         GPIO_BOTH_EDGES
+
+#define PCMCIA_S1_CD_VALID              IRQ_GPIO(83)
+#define PCMCIA_S1_CD_VALID_EDGE         GPIO_BOTH_EDGES
+
+#define PCMCIA_S0_RDYINT                IRQ_GPIO(82)
+#define PCMCIA_S1_RDYINT                IRQ_GPIO(81)
+
+#define PCMCIA_RESET_GPIO               53
diff --git a/include/asm-arm/arch-pxa/dma.h b/include/asm-arm/arch-pxa/dma.h
index 3280ee2ddfa5..dbe110ee2666 100644
--- a/include/asm-arm/arch-pxa/dma.h
+++ b/include/asm-arm/arch-pxa/dma.h
@@ -30,6 +30,10 @@ typedef enum {
         DMA_PRIO_LOW = 2
 } pxa_dma_prio;
 
+#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
+#define HAVE_ARCH_PCI_SET_DMA_MASK      1
+#endif
+
 /*
  * DMA registration
  */
diff --git a/include/asm-arm/arch-pxa/gpio.h b/include/asm-arm/arch-pxa/gpio.h
index 9e99241f3edf..9dbc2dc794f7 100644
--- a/include/asm-arm/arch-pxa/gpio.h
+++ b/include/asm-arm/arch-pxa/gpio.h
@@ -38,16 +38,8 @@ static inline void gpio_free(unsigned gpio)
         return;
 }
 
-static inline int gpio_direction_input(unsigned gpio)
-{
-        return pxa_gpio_mode(gpio | GPIO_IN);
-}
-
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
-        return pxa_gpio_mode(gpio | GPIO_OUT |
-                         (value ? GPIO_DFLT_HIGH : GPIO_DFLT_LOW));
-}
+extern int gpio_direction_input(unsigned gpio);
+extern int gpio_direction_output(unsigned gpio, int value);
 
 static inline int __gpio_get_value(unsigned gpio)
 {
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index 386121746417..ab2d963e742a 100644
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -62,6 +62,7 @@
 
 #ifndef __ASSEMBLY__
 
+#ifdef CONFIG_PXA25x
 #define __cpu_is_pxa21x(id)                             \
         ({                                              \
                 unsigned int _id = (id) >> 4 & 0xf3f;   \
@@ -73,12 +74,50 @@
                 unsigned int _id = (id) >> 4 & 0xfff;   \
                 _id == 0x2d0 || _id == 0x290;           \
         })
+#else
+#define __cpu_is_pxa21x(id)     (0)
+#define __cpu_is_pxa25x(id)     (0)
+#endif
 
+#ifdef CONFIG_PXA27x
 #define __cpu_is_pxa27x(id)                             \
         ({                                              \
                 unsigned int _id = (id) >> 4 & 0xfff;   \
                 _id == 0x411;                           \
         })
+#else
+#define __cpu_is_pxa27x(id)     (0)
+#endif
+
+#ifdef CONFIG_CPU_PXA300
+#define __cpu_is_pxa300(id)                             \
+        ({                                              \
+                unsigned int _id = (id) >> 4 & 0xfff;   \
+                _id == 0x688;                           \
+         })
+#else
+#define __cpu_is_pxa300(id)     (0)
+#endif
+
+#ifdef CONFIG_CPU_PXA310
+#define __cpu_is_pxa310(id)                             \
+        ({                                              \
+                unsigned int _id = (id) >> 4 & 0xfff;   \
+                _id == 0x689;                           \
+         })
+#else
+#define __cpu_is_pxa310(id)     (0)
+#endif
+
+#ifdef CONFIG_CPU_PXA320
+#define __cpu_is_pxa320(id)                             \
+        ({                                              \
+                unsigned int _id = (id) >> 4 & 0xfff;   \
+                _id == 0x603 || _id == 0x682;           \
+         })
+#else
+#define __cpu_is_pxa320(id)     (0)
+#endif
 
 #define cpu_is_pxa21x()                                 \
         ({                                              \
@@ -98,6 +137,53 @@
                 __cpu_is_pxa27x(id);                    \
         })
 
+#define cpu_is_pxa300()                                 \
+        ({                                              \
+                unsigned int id = read_cpuid(CPUID_ID); \
+                __cpu_is_pxa300(id);                    \
+         })
+
+#define cpu_is_pxa310()                                 \
+        ({                                              \
+                unsigned int id = read_cpuid(CPUID_ID); \
+                __cpu_is_pxa310(id);                    \
+         })
+
+#define cpu_is_pxa320()                                 \
+        ({                                              \
+                unsigned int id = read_cpuid(CPUID_ID); \
+                __cpu_is_pxa320(id);                    \
+         })
+
+/*
+ * CPUID Core Generation Bit
+ * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
+ * == 0x3 for pxa300/pxa310/pxa320
+ */
+#define __cpu_is_pxa2xx(id)                             \
+        ({                                              \
+                unsigned int _id = (id) >> 13 & 0x7;    \
+                _id <= 0x2;                             \
+         })
+
+#define __cpu_is_pxa3xx(id)                             \
+        ({                                              \
+                unsigned int _id = (id) >> 13 & 0x7;    \
+                _id == 0x3;                             \
+         })
+
+#define cpu_is_pxa2xx()                                 \
+        ({                                              \
+                unsigned int id = read_cpuid(CPUID_ID); \
+                __cpu_is_pxa2xx(id);                    \
+         })
+
+#define cpu_is_pxa3xx()                                 \
+        ({                                              \
+                unsigned int id = read_cpuid(CPUID_ID); \
+                __cpu_is_pxa3xx(id);                    \
+         })
+
 /*
  * Handy routine to set GPIO alternate functions
  */
@@ -116,14 +202,23 @@ extern void pxa_gpio_set_value(unsigned gpio, int value);
 /*
  * Routine to enable or disable CKEN
  */
-extern void pxa_set_cken(int clock, int enable);
+static inline void __deprecated pxa_set_cken(int clock, int enable)
+{
+        extern void __pxa_set_cken(int clock, int enable);
+        __pxa_set_cken(clock, enable);
+}
 
 /*
  * return current memory and LCD clock frequency in units of 10kHz
  */
 extern unsigned int get_memclk_frequency_10khz(void);
-extern unsigned int get_lcdclk_frequency_10khz(void);
 
 #endif
 
+#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
+#define PCIBIOS_MIN_IO          0
+#define PCIBIOS_MIN_MEM         0
+#define pcibios_assign_all_busses()     1
+#endif
+
 #endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h
index a07fe0f928cd..6238dbf7a236 100644
--- a/include/asm-arm/arch-pxa/irqs.h
+++ b/include/asm-arm/arch-pxa/irqs.h
@@ -66,12 +66,6 @@
 #define IRQ_TO_GPIO_2_x(i)      ((i) - PXA_GPIO_IRQ_BASE)
 #define IRQ_TO_GPIO(i)  (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i))
 
-#if defined(CONFIG_PXA25x)
-#define PXA_LAST_GPIO   84
-#elif defined(CONFIG_PXA27x)
-#define PXA_LAST_GPIO   127
-#endif
-
 /*
  * The next 16 interrupts are for board specific purposes.  Since
  * the kernel can only run on one machine at a time, we can re-use
@@ -216,3 +210,24 @@
 #define IRQ_LOCOMO_GPIO_BASE    (IRQ_BOARD_START + 1)
 #define IRQ_LOCOMO_LT_BASE      (IRQ_BOARD_START + 2)
 #define IRQ_LOCOMO_SPI_BASE     (IRQ_BOARD_START + 3)
+
+/* ITE8152 irqs */
+/* add IT8152 IRQs beyond BOARD_END */
+#ifdef CONFIG_PCI_HOST_ITE8152
+#define IT8152_IRQ(x)   (IRQ_GPIO(IRQ_BOARD_END) + 1 + (x))
+
+/* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */
+#define IT8152_LD_IRQ_COUNT     9
+#define IT8152_LP_IRQ_COUNT     16
+#define IT8152_PD_IRQ_COUNT     15
+
+/* Priorities: */
+#define IT8152_PD_IRQ(i)        IT8152_IRQ(i)
+#define IT8152_LP_IRQ(i)        (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT)
+#define IT8152_LD_IRQ(i)        (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT + IT8152_LP_IRQ_COUNT)
+
+#define IT8152_LAST_IRQ         IT8152_LD_IRQ(IT8152_LD_IRQ_COUNT - 1)
+
+#undef NR_IRQS
+#define NR_IRQS (IT8152_LAST_IRQ+1)
+#endif
diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h
index e17f9881faf0..bee81d66c184 100644
--- a/include/asm-arm/arch-pxa/memory.h
+++ b/include/asm-arm/arch-pxa/memory.h
@@ -39,4 +39,14 @@
  */
 #define NODE_MEM_SIZE_BITS      26
 
+#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
+void cmx270_pci_adjust_zones(int node, unsigned long *size,
+                             unsigned long *holes);
+
+#define arch_adjust_zones(node, size, holes) \
+        cmx270_pci_adjust_zones(node, size, holes)
+
+#define ISA_DMA_THRESHOLD       (PHYS_OFFSET + SZ_64M - 1)
+#endif
+
 #endif
diff --git a/include/asm-arm/arch-pxa/mfp-pxa300.h b/include/asm-arm/arch-pxa/mfp-pxa300.h
new file mode 100644
index 000000000000..7513c7a3402d
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mfp-pxa300.h
@@ -0,0 +1,574 @@
+/*
+ * linux/include/asm-arm/arch-pxa/mfp-pxa300.h
+ *
+ * PXA300/PXA310 specific MFP configuration definitions
+ *
+ * Copyright (C) 2007 Marvell International Ltd.
+ * 2007-08-21: eric miao <eric.y.miao@gmail.com>
+ *             initial version
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MFP_PXA300_H
+#define __ASM_ARCH_MFP_PXA300_H
+
+#include <asm/arch/mfp.h>
+
+/* GPIO */
+#define GPIO46_GPIO             MFP_CFG(GPIO46, AF1)
+#define GPIO49_GPIO             MFP_CFG(GPIO49, AF3)
+#define GPIO50_GPIO             MFP_CFG(GPIO50, AF2)
+#define GPIO51_GPIO             MFP_CFG(GPIO51, AF3)
+#define GPIO52_GPIO             MFP_CFG(GPIO52, AF3)
+#define GPIO56_GPIO             MFP_CFG(GPIO56, AF0)
+#define GPIO58_GPIO             MFP_CFG(GPIO58, AF0)
+#define GPIO59_GPIO             MFP_CFG(GPIO59, AF0)
+#define GPIO60_GPIO             MFP_CFG(GPIO60, AF0)
+#define GPIO61_GPIO             MFP_CFG(GPIO61, AF0)
+#define GPIO62_GPIO             MFP_CFG(GPIO62, AF0)
+
+#ifdef CONFIG_CPU_PXA310
+#define GPIO7_2_GPIO            MFP_CFG(GPIO7_2, AF0)
+#define GPIO8_2_GPIO            MFP_CFG(GPIO8_2, AF0)
+#define GPIO9_2_GPIO            MFP_CFG(GPIO9_2, AF0)
+#define GPIO10_2_GPIO           MFP_CFG(GPIO10_2, AF0)
+#define GPIO11_2_GPIO           MFP_CFG(GPIO11_2, AF0)
+#define GPIO12_2_GPIO           MFP_CFG(GPIO12_2, AF0)
+#endif
+
+/* Chip Select */
+#define GPIO2_nCS3              MFP_CFG(GPIO2,  AF1)
+
+/* AC97 */
+#define GPIO23_AC97_nACRESET    MFP_CFG(GPIO23, AF1)
+#define GPIO24_AC97_SYSCLK      MFP_CFG(GPIO24, AF1)
+#define GPIO29_AC97_BITCLK      MFP_CFG(GPIO29, AF1)
+#define GPIO25_AC97_SDATA_IN_0  MFP_CFG(GPIO25, AF1)
+#define GPIO26_AC97_SDATA_IN_1  MFP_CFG(GPIO26, AF1)
+#define GPIO17_AC97_SDATA_IN_2  MFP_CFG(GPIO17, AF3)
+#define GPIO21_AC97_SDATA_IN_2  MFP_CFG(GPIO21, AF2)
+#define GPIO18_AC97_SDATA_IN_3  MFP_CFG(GPIO18, AF3)
+#define GPIO22_AC97_SDATA_IN_3  MFP_CFG(GPIO22, AF2)
+#define GPIO27_AC97_SDATA_OUT   MFP_CFG(GPIO27, AF1)
+#define GPIO28_AC97_SYNC        MFP_CFG(GPIO28, AF1)
+
+/* I2C */
+#define GPIO21_I2C_SCL          MFP_CFG_LPM(GPIO21, AF1, PULL_HIGH)
+#define GPIO22_I2C_SDA          MFP_CFG_LPM(GPIO22, AF1, PULL_HIGH)
+
+/* QCI */
+#define GPIO39_CI_DD_0          MFP_CFG_DRV(GPIO39, AF1, DS04X)
+#define GPIO40_CI_DD_1          MFP_CFG_DRV(GPIO40, AF1, DS04X)
+#define GPIO41_CI_DD_2          MFP_CFG_DRV(GPIO41, AF1, DS04X)
+#define GPIO42_CI_DD_3          MFP_CFG_DRV(GPIO42, AF1, DS04X)
+#define GPIO43_CI_DD_4          MFP_CFG_DRV(GPIO43, AF1, DS04X)
+#define GPIO44_CI_DD_5          MFP_CFG_DRV(GPIO44, AF1, DS04X)
+#define GPIO45_CI_DD_6          MFP_CFG_DRV(GPIO45, AF1, DS04X)
+#define GPIO46_CI_DD_7          MFP_CFG_DRV(GPIO46, AF0, DS04X)
+#define GPIO47_CI_DD_8          MFP_CFG_DRV(GPIO47, AF1, DS04X)
+#define GPIO48_CI_DD_9          MFP_CFG_DRV(GPIO48, AF1, DS04X)
+#define GPIO52_CI_HSYNC         MFP_CFG_DRV(GPIO52, AF0, DS04X)
+#define GPIO51_CI_VSYNC         MFP_CFG_DRV(GPIO51, AF0, DS04X)
+#define GPIO49_CI_MCLK          MFP_CFG_DRV(GPIO49, AF0, DS04X)
+#define GPIO50_CI_PCLK          MFP_CFG_DRV(GPIO50, AF0, DS04X)
+
+/* KEYPAD */
+#define GPIO3_KP_DKIN_6         MFP_CFG_LPM(GPIO3,   AF2, FLOAT)
+#define GPIO4_KP_DKIN_7         MFP_CFG_LPM(GPIO4,   AF2, FLOAT)
+#define GPIO16_KP_DKIN_6        MFP_CFG_LPM(GPIO16,  AF6, FLOAT)
+#define GPIO83_KP_DKIN_2        MFP_CFG_LPM(GPIO83,  AF5, FLOAT)
+#define GPIO84_KP_DKIN_1        MFP_CFG_LPM(GPIO84,  AF5, FLOAT)
+#define GPIO85_KP_DKIN_0        MFP_CFG_LPM(GPIO85,  AF3, FLOAT)
+#define GPIO86_KP_DKIN_1        MFP_CFG_LPM(GPIO86,  AF3, FLOAT)
+#define GPIO87_KP_DKIN_2        MFP_CFG_LPM(GPIO87,  AF3, FLOAT)
+#define GPIO88_KP_DKIN_3        MFP_CFG_LPM(GPIO88,  AF3, FLOAT)
+#define GPIO89_KP_DKIN_3        MFP_CFG_LPM(GPIO89,  AF3, FLOAT)
+#define GPIO107_KP_DKIN_0       MFP_CFG_LPM(GPIO107, AF2, FLOAT)
+#define GPIO108_KP_DKIN_1       MFP_CFG_LPM(GPIO108, AF2, FLOAT)
+#define GPIO109_KP_DKIN_2       MFP_CFG_LPM(GPIO109, AF2, FLOAT)
+#define GPIO110_KP_DKIN_3       MFP_CFG_LPM(GPIO110, AF2, FLOAT)
+#define GPIO111_KP_DKIN_4       MFP_CFG_LPM(GPIO111, AF2, FLOAT)
+#define GPIO112_KP_DKIN_5       MFP_CFG_LPM(GPIO112, AF2, FLOAT)
+#define GPIO113_KP_DKIN_6       MFP_CFG_LPM(GPIO113, AF2, FLOAT)
+#define GPIO114_KP_DKIN_7       MFP_CFG_LPM(GPIO114, AF2, FLOAT)
+#define GPIO115_KP_DKIN_0       MFP_CFG_LPM(GPIO115, AF2, FLOAT)
+#define GPIO116_KP_DKIN_1       MFP_CFG_LPM(GPIO116, AF2, FLOAT)
+#define GPIO117_KP_DKIN_2       MFP_CFG_LPM(GPIO117, AF2, FLOAT)
+#define GPIO118_KP_DKIN_3       MFP_CFG_LPM(GPIO118, AF2, FLOAT)
+#define GPIO119_KP_DKIN_4       MFP_CFG_LPM(GPIO119, AF2, FLOAT)
+#define GPIO120_KP_DKIN_5       MFP_CFG_LPM(GPIO120, AF2, FLOAT)
+#define GPIO121_KP_DKIN_6       MFP_CFG_LPM(GPIO121, AF2, FLOAT)
+#define GPIO122_KP_DKIN_5       MFP_CFG_LPM(GPIO122, AF2, FLOAT)
+#define GPIO123_KP_DKIN_4       MFP_CFG_LPM(GPIO123, AF2, FLOAT)
+#define GPIO124_KP_DKIN_3       MFP_CFG_LPM(GPIO124, AF2, FLOAT)
+#define GPIO127_KP_DKIN_0       MFP_CFG_LPM(GPIO127, AF5, FLOAT)
+#define GPIO0_2_KP_DKIN_0       MFP_CFG_LPM(GPIO0_2, AF2, FLOAT)
+#define GPIO1_2_KP_DKIN_1       MFP_CFG_LPM(GPIO1_2, AF2, FLOAT)
+#define GPIO2_2_KP_DKIN_6       MFP_CFG_LPM(GPIO2_2, AF2, FLOAT)
+#define GPIO3_2_KP_DKIN_7       MFP_CFG_LPM(GPIO3_2, AF2, FLOAT)
+#define GPIO4_2_KP_DKIN_1       MFP_CFG_LPM(GPIO4_2, AF2, FLOAT)
+#define GPIO5_2_KP_DKIN_0       MFP_CFG_LPM(GPIO5_2, AF2, FLOAT)
+
+#define GPIO5_KP_MKIN_0         MFP_CFG_LPM(GPIO5,   AF2, FLOAT)
+#define GPIO6_KP_MKIN_1         MFP_CFG_LPM(GPIO6,   AF2, FLOAT)
+#define GPIO9_KP_MKIN_6         MFP_CFG_LPM(GPIO9,   AF3, FLOAT)
+#define GPIO10_KP_MKIN_7        MFP_CFG_LPM(GPIO10,  AF3, FLOAT)
+#define GPIO70_KP_MKIN_6        MFP_CFG_LPM(GPIO70,  AF3, FLOAT)
+#define GPIO71_KP_MKIN_7        MFP_CFG_LPM(GPIO71,  AF3, FLOAT)
+#define GPIO100_KP_MKIN_6       MFP_CFG_LPM(GPIO100, AF7, FLOAT)
+#define GPIO101_KP_MKIN_7       MFP_CFG_LPM(GPIO101, AF7, FLOAT)
+#define GPIO112_KP_MKIN_6       MFP_CFG_LPM(GPIO112, AF4, FLOAT)
+#define GPIO113_KP_MKIN_7       MFP_CFG_LPM(GPIO113, AF4, FLOAT)
+#define GPIO115_KP_MKIN_0       MFP_CFG_LPM(GPIO115, AF1, FLOAT)
+#define GPIO116_KP_MKIN_1       MFP_CFG_LPM(GPIO116, AF1, FLOAT)
+#define GPIO117_KP_MKIN_2       MFP_CFG_LPM(GPIO117, AF1, FLOAT)
+#define GPIO118_KP_MKIN_3       MFP_CFG_LPM(GPIO118, AF1, FLOAT)
+#define GPIO119_KP_MKIN_4       MFP_CFG_LPM(GPIO119, AF1, FLOAT)
+#define GPIO120_KP_MKIN_5       MFP_CFG_LPM(GPIO120, AF1, FLOAT)
+#define GPIO125_KP_MKIN_2       MFP_CFG_LPM(GPIO125, AF2, FLOAT)
+#define GPIO2_2_KP_MKIN_6       MFP_CFG_LPM(GPIO2_2, AF1, FLOAT)
+#define GPIO3_2_KP_MKIN_7       MFP_CFG_LPM(GPIO3_2, AF1, FLOAT)
+
+#define GPIO7_KP_MKOUT_5        MFP_CFG_LPM(GPIO7,   AF1, DRIVE_HIGH)
+#define GPIO11_KP_MKOUT_5       MFP_CFG_LPM(GPIO11,  AF3, DRIVE_HIGH)
+#define GPIO12_KP_MKOUT_6       MFP_CFG_LPM(GPIO12,  AF3, DRIVE_HIGH)
+#define GPIO13_KP_MKOUT_7       MFP_CFG_LPM(GPIO13,  AF3, DRIVE_HIGH)
+#define GPIO19_KP_MKOUT_4       MFP_CFG_LPM(GPIO19,  AF3, DRIVE_HIGH)
+#define GPIO20_KP_MKOUT_5       MFP_CFG_LPM(GPIO20,  AF3, DRIVE_HIGH)
+#define GPIO38_KP_MKOUT_5       MFP_CFG_LPM(GPIO38,  AF5, DRIVE_HIGH)
+#define GPIO53_KP_MKOUT_6       MFP_CFG_LPM(GPIO53,  AF5, DRIVE_HIGH)
+#define GPIO78_KP_MKOUT_7       MFP_CFG_LPM(GPIO78,  AF5, DRIVE_HIGH)
+#define GPIO85_KP_MKOUT_0       MFP_CFG_LPM(GPIO85,  AF2, DRIVE_HIGH)
+#define GPIO86_KP_MKOUT_1       MFP_CFG_LPM(GPIO86,  AF2, DRIVE_HIGH)
+#define GPIO87_KP_MKOUT_2       MFP_CFG_LPM(GPIO87,  AF2, DRIVE_HIGH)
+#define GPIO88_KP_MKOUT_3       MFP_CFG_LPM(GPIO88,  AF2, DRIVE_HIGH)
+#define GPIO104_KP_MKOUT_6      MFP_CFG_LPM(GPIO104, AF5, DRIVE_HIGH)
+#define GPIO105_KP_MKOUT_7      MFP_CFG_LPM(GPIO105, AF5, DRIVE_HIGH)
+#define GPIO121_KP_MKOUT_0      MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH)
+#define GPIO122_KP_MKOUT_1      MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH)
+#define GPIO123_KP_MKOUT_2      MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH)
+#define GPIO124_KP_MKOUT_3      MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH)
+#define GPIO125_KP_MKOUT_4      MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH)
+#define GPIO126_KP_MKOUT_7      MFP_CFG_LPM(GPIO126, AF4, DRIVE_HIGH)
+#define GPIO5_2_KP_MKOUT_6      MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH)
+#define GPIO4_2_KP_MKOUT_5      MFP_CFG_LPM(GPIO4_2, AF1, DRIVE_HIGH)
+#define GPIO6_2_KP_MKOUT_7      MFP_CFG_LPM(GPIO6_2, AF1, DRIVE_HIGH)
+
+/* LCD */
+#define GPIO54_LCD_LDD_0        MFP_CFG_DRV(GPIO54, AF1, DS01X)
+#define GPIO55_LCD_LDD_1        MFP_CFG_DRV(GPIO55, AF1, DS01X)
+#define GPIO56_LCD_LDD_2        MFP_CFG_DRV(GPIO56, AF1, DS01X)
+#define GPIO57_LCD_LDD_3        MFP_CFG_DRV(GPIO57, AF1, DS01X)
+#define GPIO58_LCD_LDD_4        MFP_CFG_DRV(GPIO58, AF1, DS01X)
+#define GPIO59_LCD_LDD_5        MFP_CFG_DRV(GPIO59, AF1, DS01X)
+#define GPIO60_LCD_LDD_6        MFP_CFG_DRV(GPIO60, AF1, DS01X)
+#define GPIO61_LCD_LDD_7        MFP_CFG_DRV(GPIO61, AF1, DS01X)
+#define GPIO62_LCD_LDD_8        MFP_CFG_DRV(GPIO62, AF1, DS01X)
+#define GPIO63_LCD_LDD_9        MFP_CFG_DRV(GPIO63, AF1, DS01X)
+#define GPIO64_LCD_LDD_10       MFP_CFG_DRV(GPIO64, AF1, DS01X)
+#define GPIO65_LCD_LDD_11       MFP_CFG_DRV(GPIO65, AF1, DS01X)
+#define GPIO66_LCD_LDD_12       MFP_CFG_DRV(GPIO66, AF1, DS01X)
+#define GPIO67_LCD_LDD_13       MFP_CFG_DRV(GPIO67, AF1, DS01X)
+#define GPIO68_LCD_LDD_14       MFP_CFG_DRV(GPIO68, AF1, DS01X)
+#define GPIO69_LCD_LDD_15       MFP_CFG_DRV(GPIO69, AF1, DS01X)
+#define GPIO70_LCD_LDD_16       MFP_CFG_DRV(GPIO70, AF1, DS01X)
+#define GPIO71_LCD_LDD_17       MFP_CFG_DRV(GPIO71, AF1, DS01X)
+#define GPIO62_LCD_CS_N         MFP_CFG_DRV(GPIO62, AF2, DS01X)
+#define GPIO72_LCD_FCLK         MFP_CFG_DRV(GPIO72, AF1, DS01X)
+#define GPIO73_LCD_LCLK         MFP_CFG_DRV(GPIO73, AF1, DS01X)
+#define GPIO74_LCD_PCLK         MFP_CFG_DRV(GPIO74, AF1, DS01X)
+#define GPIO75_LCD_BIAS         MFP_CFG_DRV(GPIO75, AF1, DS01X)
+#define GPIO76_LCD_VSYNC        MFP_CFG_DRV(GPIO76, AF2, DS01X)
+
+#define GPIO15_LCD_CS_N         MFP_CFG_DRV(GPIO15,  AF2, DS01X)
+#define GPIO127_LCD_CS_N        MFP_CFG_DRV(GPIO127, AF1, DS01X)
+#define GPIO63_LCD_VSYNC        MFP_CFG_DRV(GPIO63,  AF2, DS01X)
+
+/* Mini-LCD */
+#define GPIO72_MLCD_FCLK        MFP_CFG_DRV(GPIO72, AF7, DS08X)
+#define GPIO73_MLCD_LCLK        MFP_CFG_DRV(GPIO73, AF7, DS08X)
+#define GPIO54_MLCD_LDD_0       MFP_CFG_DRV(GPIO54, AF7, DS08X)
+#define GPIO55_MLCD_LDD_1       MFP_CFG_DRV(GPIO55, AF7, DS08X)
+#define GPIO56_MLCD_LDD_2       MFP_CFG_DRV(GPIO56, AF7, DS08X)
+#define GPIO57_MLCD_LDD_3       MFP_CFG_DRV(GPIO57, AF7, DS08X)
+#define GPIO58_MLCD_LDD_4       MFP_CFG_DRV(GPIO58, AF7, DS08X)
+#define GPIO59_MLCD_LDD_5       MFP_CFG_DRV(GPIO59, AF7, DS08X)
+#define GPIO60_MLCD_LDD_6       MFP_CFG_DRV(GPIO60, AF7, DS08X)
+#define GPIO61_MLCD_LDD_7       MFP_CFG_DRV(GPIO61, AF7, DS08X)
+#define GPIO62_MLCD_LDD_8       MFP_CFG_DRV(GPIO62, AF7, DS08X)
+#define GPIO63_MLCD_LDD_9       MFP_CFG_DRV(GPIO63, AF7, DS08X)
+#define GPIO64_MLCD_LDD_10      MFP_CFG_DRV(GPIO64, AF7, DS08X)
+#define GPIO65_MLCD_LDD_11      MFP_CFG_DRV(GPIO65, AF7, DS08X)
+#define GPIO66_MLCD_LDD_12      MFP_CFG_DRV(GPIO66, AF7, DS08X)
+#define GPIO67_MLCD_LDD_13      MFP_CFG_DRV(GPIO67, AF7, DS08X)
+#define GPIO68_MLCD_LDD_14      MFP_CFG_DRV(GPIO68, AF7, DS08X)
+#define GPIO69_MLCD_LDD_15      MFP_CFG_DRV(GPIO69, AF7, DS08X)
+#define GPIO74_MLCD_PCLK        MFP_CFG_DRV(GPIO74, AF7, DS08X)
+#define GPIO75_MLCD_BIAS        MFP_CFG_DRV(GPIO75, AF2, DS08X)
+
+/* MMC1 */
+#define GPIO7_MMC1_CLK          MFP_CFG_LPM(GPIO7,  AF4, DRIVE_HIGH)
+#define GPIO8_MMC1_CMD          MFP_CFG_LPM(GPIO8,  AF4, DRIVE_HIGH)
+#define GPIO14_MMC1_CMD         MFP_CFG_LPM(GPIO14, AF5, DRIVE_HIGH)
+#define GPIO15_MMC1_CMD         MFP_CFG_LPM(GPIO15, AF5, DRIVE_HIGH)
+#define GPIO3_MMC1_DAT0         MFP_CFG_LPM(GPIO3,  AF4, DRIVE_HIGH)
+#define GPIO4_MMC1_DAT1         MFP_CFG_LPM(GPIO4,  AF4, DRIVE_HIGH)
+#define GPIO5_MMC1_DAT2         MFP_CFG_LPM(GPIO5,  AF4, DRIVE_HIGH)
+#define GPIO6_MMC1_DAT3         MFP_CFG_LPM(GPIO6,  AF4, DRIVE_HIGH)
+
+/* MMC2 */
+#define GPIO9_MMC2_DAT0         MFP_CFG_LPM(GPIO9,  AF4, PULL_HIGH)
+#define GPIO10_MMC2_DAT1        MFP_CFG_LPM(GPIO10, AF4, PULL_HIGH)
+#define GPIO11_MMC2_DAT2        MFP_CFG_LPM(GPIO11, AF4, PULL_HIGH)
+#define GPIO12_MMC2_DAT3        MFP_CFG_LPM(GPIO12, AF4, PULL_HIGH)
+#define GPIO13_MMC2_CLK         MFP_CFG_LPM(GPIO13, AF4, PULL_HIGH)
+#define GPIO14_MMC2_CMD         MFP_CFG_LPM(GPIO14, AF4, PULL_HIGH)
+#define GPIO77_MMC2_DAT0        MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH)
+#define GPIO78_MMC2_DAT1        MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH)
+#define GPIO79_MMC2_DAT2        MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH)
+#define GPIO80_MMC2_DAT3        MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH)
+#define GPIO81_MMC2_CLK         MFP_CFG_LPM(GPIO81, AF4, PULL_HIGH)
+#define GPIO82_MMC2_CMD         MFP_CFG_LPM(GPIO82, AF4, PULL_HIGH)
+
+/* SSP1 */
+#define GPIO89_SSP1_EXTCLK      MFP_CFG(GPIO89, AF1)
+#define GPIO90_SSP1_SYSCLK      MFP_CFG(GPIO90, AF1)
+#define GPIO15_SSP1_SCLK        MFP_CFG(GPIO15, AF6)
+#define GPIO16_SSP1_FRM         MFP_CFG(GPIO16, AF2)
+#define GPIO33_SSP1_SCLK        MFP_CFG(GPIO33, AF5)
+#define GPIO34_SSP1_FRM         MFP_CFG(GPIO34, AF5)
+#define GPIO85_SSP1_SCLK        MFP_CFG(GPIO85, AF1)
+#define GPIO86_SSP1_FRM         MFP_CFG(GPIO86, AF1)
+#define GPIO18_SSP1_TXD         MFP_CFG(GPIO18, AF7)
+#define GPIO18_SSP1_RXD         MFP_CFG(GPIO18, AF2)
+#define GPIO20_SSP1_TXD         MFP_CFG(GPIO20, AF2)
+#define GPIO20_SSP1_RXD         MFP_CFG(GPIO20, AF7)
+#define GPIO35_SSP1_TXD         MFP_CFG(GPIO35, AF5)
+#define GPIO35_SSP1_RXD         MFP_CFG(GPIO35, AF4)
+#define GPIO36_SSP1_TXD         MFP_CFG(GPIO36, AF5)
+#define GPIO36_SSP1_RXD         MFP_CFG(GPIO36, AF6)
+#define GPIO87_SSP1_TXD         MFP_CFG(GPIO87, AF1)
+#define GPIO87_SSP1_RXD         MFP_CFG(GPIO87, AF6)
+#define GPIO88_SSP1_TXD         MFP_CFG(GPIO88, AF6)
+#define GPIO88_SSP1_RXD         MFP_CFG(GPIO88, AF1)
+
+/* SSP2 */
+#define GPIO29_SSP2_EXTCLK      MFP_CFG(GPIO29, AF2)
+#define GPIO23_SSP2_SCLK        MFP_CFG(GPIO23, AF2)
+#define GPIO17_SSP2_FRM         MFP_CFG(GPIO17, AF2)
+#define GPIO25_SSP2_SCLK        MFP_CFG(GPIO25, AF2)
+#define GPIO26_SSP2_FRM         MFP_CFG(GPIO26, AF2)
+#define GPIO33_SSP2_SCLK        MFP_CFG(GPIO33, AF6)
+#define GPIO34_SSP2_FRM         MFP_CFG(GPIO34, AF6)
+#define GPIO64_SSP2_SCLK        MFP_CFG(GPIO64, AF2)
+#define GPIO65_SSP2_FRM         MFP_CFG(GPIO65, AF2)
+#define GPIO19_SSP2_TXD         MFP_CFG(GPIO19, AF2)
+#define GPIO19_SSP2_RXD         MFP_CFG(GPIO19, AF7)
+#define GPIO24_SSP2_TXD         MFP_CFG(GPIO24, AF5)
+#define GPIO24_SSP2_RXD         MFP_CFG(GPIO24, AF4)
+#define GPIO27_SSP2_TXD         MFP_CFG(GPIO27, AF2)
+#define GPIO27_SSP2_RXD         MFP_CFG(GPIO27, AF5)
+#define GPIO28_SSP2_TXD         MFP_CFG(GPIO28, AF5)
+#define GPIO28_SSP2_RXD         MFP_CFG(GPIO28, AF2)
+#define GPIO35_SSP2_TXD         MFP_CFG(GPIO35, AF7)
+#define GPIO35_SSP2_RXD         MFP_CFG(GPIO35, AF6)
+#define GPIO66_SSP2_TXD         MFP_CFG(GPIO66, AF4)
+#define GPIO66_SSP2_RXD         MFP_CFG(GPIO66, AF2)
+#define GPIO67_SSP2_TXD         MFP_CFG(GPIO67, AF2)
+#define GPIO67_SSP2_RXD         MFP_CFG(GPIO67, AF4)
+#define GPIO36_SSP2_TXD         MFP_CFG(GPIO36, AF7)
+
+/* SSP3 */
+#define GPIO69_SSP3_FRM         MFP_CFG_X(GPIO69, AF2, DS08X, DRIVE_LOW)
+#define GPIO68_SSP3_SCLK        MFP_CFG_X(GPIO68, AF2, DS08X, FLOAT)
+#define GPIO92_SSP3_FRM         MFP_CFG_X(GPIO92, AF1, DS08X, DRIVE_LOW)
+#define GPIO91_SSP3_SCLK        MFP_CFG_X(GPIO91, AF1, DS08X, FLOAT)
+#define GPIO70_SSP3_TXD         MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW)
+#define GPIO70_SSP3_RXD         MFP_CFG_X(GPIO70, AF5, DS08X, FLOAT)
+#define GPIO71_SSP3_TXD         MFP_CFG_X(GPIO71, AF5, DS08X, DRIVE_LOW)
+#define GPIO71_SSP3_RXD         MFP_CFG_X(GPIO71, AF2, DS08X, FLOAT)
+#define GPIO93_SSP3_TXD         MFP_CFG_X(GPIO93, AF1, DS08X, DRIVE_LOW)
+#define GPIO93_SSP3_RXD         MFP_CFG_X(GPIO93, AF5, DS08X, FLOAT)
+#define GPIO94_SSP3_TXD         MFP_CFG_X(GPIO94, AF5, DS08X, DRIVE_LOW)
+#define GPIO94_SSP3_RXD         MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT)
+
+/* SSP4 */
+#define GPIO95_SSP4_SCLK        MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
+#define GPIO96_SSP4_FRM         MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
+#define GPIO97_SSP4_TXD         MFP_CFG_LPM(GPIO97, AF1, PULL_HIGH)
+#define GPIO97_SSP4_RXD         MFP_CFG_LPM(GPIO97, AF5, PULL_HIGH)
+#define GPIO98_SSP4_TXD         MFP_CFG_LPM(GPIO98, AF5, PULL_HIGH)
+#define GPIO98_SSP4_RXD         MFP_CFG_LPM(GPIO98, AF1, PULL_HIGH)
+
+/* UART1 */
+#define GPIO32_UART1_CTS        MFP_CFG_LPM(GPIO32,  AF2, FLOAT)
+#define GPIO37_UART1_CTS        MFP_CFG_LPM(GPIO37,  AF4, FLOAT)
+#define GPIO79_UART1_CTS        MFP_CFG_LPM(GPIO79,  AF1, FLOAT)
+#define GPIO84_UART1_CTS        MFP_CFG_LPM(GPIO84,  AF3, FLOAT)
+#define GPIO101_UART1_CTS       MFP_CFG_LPM(GPIO101, AF1, FLOAT)
+#define GPIO106_UART1_CTS       MFP_CFG_LPM(GPIO106, AF6, FLOAT)
+
+#define GPIO32_UART1_RTS        MFP_CFG_LPM(GPIO32,  AF4, FLOAT)
+#define GPIO37_UART1_RTS        MFP_CFG_LPM(GPIO37,  AF2, FLOAT)
+#define GPIO79_UART1_RTS        MFP_CFG_LPM(GPIO79,  AF3, FLOAT)
+#define GPIO84_UART1_RTS        MFP_CFG_LPM(GPIO84,  AF1, FLOAT)
+#define GPIO101_UART1_RTS       MFP_CFG_LPM(GPIO101, AF6, FLOAT)
+#define GPIO106_UART1_RTS       MFP_CFG_LPM(GPIO106, AF1, FLOAT)
+
+#define GPIO34_UART1_DSR        MFP_CFG_LPM(GPIO34,  AF2, FLOAT)
+#define GPIO36_UART1_DSR        MFP_CFG_LPM(GPIO36,  AF4, FLOAT)
+#define GPIO81_UART1_DSR        MFP_CFG_LPM(GPIO81,  AF1, FLOAT)
+#define GPIO83_UART1_DSR        MFP_CFG_LPM(GPIO83,  AF3, FLOAT)
+#define GPIO103_UART1_DSR       MFP_CFG_LPM(GPIO103, AF1, FLOAT)
+#define GPIO105_UART1_DSR       MFP_CFG_LPM(GPIO105, AF6, FLOAT)
+
+#define GPIO34_UART1_DTR        MFP_CFG_LPM(GPIO34,  AF4, FLOAT)
+#define GPIO36_UART1_DTR        MFP_CFG_LPM(GPIO36,  AF2, FLOAT)
+#define GPIO81_UART1_DTR        MFP_CFG_LPM(GPIO81,  AF3, FLOAT)
+#define GPIO83_UART1_DTR        MFP_CFG_LPM(GPIO83,  AF1, FLOAT)
+#define GPIO103_UART1_DTR       MFP_CFG_LPM(GPIO103, AF6, FLOAT)
+#define GPIO105_UART1_DTR       MFP_CFG_LPM(GPIO105, AF1, FLOAT)
+
+#define GPIO35_UART1_RI         MFP_CFG_LPM(GPIO35,  AF2, FLOAT)
+#define GPIO82_UART1_RI         MFP_CFG_LPM(GPIO82,  AF1, FLOAT)
+#define GPIO104_UART1_RI        MFP_CFG_LPM(GPIO104, AF1, FLOAT)
+
+#define GPIO33_UART1_DCD        MFP_CFG_LPM(GPIO33,  AF2, FLOAT)
+#define GPIO80_UART1_DCD        MFP_CFG_LPM(GPIO80,  AF1, FLOAT)
+#define GPIO102_UART1_DCD       MFP_CFG_LPM(GPIO102, AF1, FLOAT)
+
+#define GPIO30_UART1_RXD        MFP_CFG_LPM(GPIO30,  AF2, FLOAT)
+#define GPIO31_UART1_RXD        MFP_CFG_LPM(GPIO31,  AF4, FLOAT)
+#define GPIO77_UART1_RXD        MFP_CFG_LPM(GPIO77,  AF1, FLOAT)
+#define GPIO78_UART1_RXD        MFP_CFG_LPM(GPIO78,  AF3, FLOAT)
+#define GPIO99_UART1_RXD        MFP_CFG_LPM(GPIO99,  AF1, FLOAT)
+#define GPIO100_UART1_RXD       MFP_CFG_LPM(GPIO100, AF6, FLOAT)
+#define GPIO102_UART1_RXD       MFP_CFG_LPM(GPIO102, AF6, FLOAT)
+#define GPIO104_UART1_RXD       MFP_CFG_LPM(GPIO104, AF4, FLOAT)
+
+#define GPIO30_UART1_TXD        MFP_CFG_LPM(GPIO30,  AF4, FLOAT)
+#define GPIO31_UART1_TXD        MFP_CFG_LPM(GPIO31,  AF2, FLOAT)
+#define GPIO77_UART1_TXD        MFP_CFG_LPM(GPIO77,  AF3, FLOAT)
+#define GPIO78_UART1_TXD        MFP_CFG_LPM(GPIO78,  AF1, FLOAT)
+#define GPIO99_UART1_TXD        MFP_CFG_LPM(GPIO99,  AF6, FLOAT)
+#define GPIO100_UART1_TXD       MFP_CFG_LPM(GPIO100, AF1, FLOAT)
+#define GPIO102_UART1_TXD       MFP_CFG_LPM(GPIO102, AF4, FLOAT)
+
+/* UART2 */
+#define GPIO15_UART2_CTS        MFP_CFG_LPM(GPIO15,  AF3, FLOAT)
+#define GPIO16_UART2_CTS        MFP_CFG_LPM(GPIO16,  AF5, FLOAT)
+#define GPIO111_UART2_CTS       MFP_CFG_LPM(GPIO111, AF3, FLOAT)
+#define GPIO114_UART2_CTS       MFP_CFG_LPM(GPIO114, AF1, FLOAT)
+
+#define GPIO15_UART2_RTS        MFP_CFG_LPM(GPIO15,  AF4, FLOAT)
+#define GPIO16_UART2_RTS        MFP_CFG_LPM(GPIO16,  AF4, FLOAT)
+#define GPIO114_UART2_RTS       MFP_CFG_LPM(GPIO114, AF3, FLOAT)
+#define GPIO111_UART2_RTS       MFP_CFG_LPM(GPIO111, AF1, FLOAT)
+
+#define GPIO18_UART2_RXD        MFP_CFG_LPM(GPIO18,  AF5, FLOAT)
+#define GPIO19_UART2_RXD        MFP_CFG_LPM(GPIO19,  AF4, FLOAT)
+#define GPIO112_UART2_RXD       MFP_CFG_LPM(GPIO112, AF1, FLOAT)
+#define GPIO113_UART2_RXD       MFP_CFG_LPM(GPIO113, AF3, FLOAT)
+
+#define GPIO18_UART2_TXD        MFP_CFG_LPM(GPIO18,  AF4, FLOAT)
+#define GPIO19_UART2_TXD        MFP_CFG_LPM(GPIO19,  AF5, FLOAT)
+#define GPIO112_UART2_TXD       MFP_CFG_LPM(GPIO112, AF3, FLOAT)
+#define GPIO113_UART2_TXD       MFP_CFG_LPM(GPIO113, AF1, FLOAT)
+
+/* UART3 */
+#define GPIO91_UART3_CTS        MFP_CFG_LPM(GPIO91,  AF2, FLOAT)
+#define GPIO92_UART3_CTS        MFP_CFG_LPM(GPIO92,  AF4, FLOAT)
+#define GPIO107_UART3_CTS       MFP_CFG_LPM(GPIO107, AF1, FLOAT)
+#define GPIO108_UART3_CTS       MFP_CFG_LPM(GPIO108, AF3, FLOAT)
+
+#define GPIO91_UART3_RTS        MFP_CFG_LPM(GPIO91,  AF4, FLOAT)
+#define GPIO92_UART3_RTS        MFP_CFG_LPM(GPIO92,  AF2, FLOAT)
+#define GPIO107_UART3_RTS       MFP_CFG_LPM(GPIO107, AF3, FLOAT)
+#define GPIO108_UART3_RTS       MFP_CFG_LPM(GPIO108, AF1, FLOAT)
+
+#define GPIO7_UART3_RXD         MFP_CFG_LPM(GPIO7,   AF2, FLOAT)
+#define GPIO8_UART3_RXD         MFP_CFG_LPM(GPIO8,   AF6, FLOAT)
+#define GPIO93_UART3_RXD        MFP_CFG_LPM(GPIO93,  AF4, FLOAT)
+#define GPIO94_UART3_RXD        MFP_CFG_LPM(GPIO94,  AF2, FLOAT)
+#define GPIO109_UART3_RXD       MFP_CFG_LPM(GPIO109, AF3, FLOAT)
+#define GPIO110_UART3_RXD       MFP_CFG_LPM(GPIO110, AF1, FLOAT)
+
+#define GPIO7_UART3_TXD         MFP_CFG_LPM(GPIO7,   AF6, FLOAT)
+#define GPIO8_UART3_TXD         MFP_CFG_LPM(GPIO8,   AF2, FLOAT)
+#define GPIO93_UART3_TXD        MFP_CFG_LPM(GPIO93,  AF2, FLOAT)
+#define GPIO94_UART3_TXD        MFP_CFG_LPM(GPIO94,  AF4, FLOAT)
+#define GPIO109_UART3_TXD       MFP_CFG_LPM(GPIO109, AF1, FLOAT)
+#define GPIO110_UART3_TXD       MFP_CFG_LPM(GPIO110, AF3, FLOAT)
+
+/* USB Host */
+#define GPIO0_2_USBH_PEN        MFP_CFG(GPIO0_2, AF1)
+#define GPIO1_2_USBH_PWR        MFP_CFG(GPIO1_2, AF1)
+
+/* USB P3 */
+#define GPIO77_USB_P3_1         MFP_CFG(GPIO77,  AF2)
+#define GPIO78_USB_P3_2         MFP_CFG(GPIO78,  AF2)
+#define GPIO79_USB_P3_3         MFP_CFG(GPIO79,  AF2)
+#define GPIO80_USB_P3_4         MFP_CFG(GPIO80,  AF2)
+#define GPIO81_USB_P3_5         MFP_CFG(GPIO81,  AF2)
+#define GPIO82_USB_P3_6         MFP_CFG(GPIO82,  AF2)
+
+/* PWM */
+#define GPIO17_PWM0_OUT         MFP_CFG(GPIO17, AF1)
+#define GPIO18_PWM1_OUT         MFP_CFG(GPIO18, AF1)
+#define GPIO19_PWM2_OUT         MFP_CFG(GPIO19, AF1)
+#define GPIO20_PWM3_OUT         MFP_CFG(GPIO20, AF1)
+
+/* CIR */
+#define GPIO8_CIR_OUT           MFP_CFG(GPIO8, AF5)
+#define GPIO16_CIR_OUT          MFP_CFG(GPIO16, AF3)
+
+#define GPIO20_OW_DQ_IN         MFP_CFG(GPIO20, AF5)
+#define GPIO126_OW_DQ           MFP_CFG(GPIO126, AF2)
+
+#define GPIO0_DF_RDY            MFP_CFG(GPIO0, AF1)
+#define GPIO7_CLK_BYPASS_XSC    MFP_CFG(GPIO7, AF7)
+#define GPIO17_EXT_SYNC_MVT_0   MFP_CFG(GPIO17, AF6)
+#define GPIO18_EXT_SYNC_MVT_1   MFP_CFG(GPIO18, AF6)
+#define GPIO19_OST_CHOUT_MVT_0  MFP_CFG(GPIO19, AF6)
+#define GPIO20_OST_CHOUT_MVT_1  MFP_CFG(GPIO20, AF6)
+#define GPIO49_48M_CLK          MFP_CFG(GPIO49, AF2)
+#define GPIO126_EXT_CLK         MFP_CFG(GPIO126, AF3)
+#define GPIO127_CLK_BYPASS_GB   MFP_CFG(GPIO127, AF7)
+#define GPIO71_EXT_MATCH_MVT    MFP_CFG(GPIO71, AF6)
+
+#define GPIO3_uIO_IN            MFP_CFG(GPIO3, AF1)
+
+#define GPIO4_uSIM_CARD_STATE   MFP_CFG(GPIO4, AF1)
+#define GPIO5_uSIM_uCLK         MFP_CFG(GPIO5, AF1)
+#define GPIO6_uSIM_uRST         MFP_CFG(GPIO6, AF1)
+#define GPIO16_uSIM_UVS_0       MFP_CFG(GPIO16, AF1)
+
+#define GPIO9_SCIO              MFP_CFG(GPIO9, AF1)
+#define GPIO20_RTC_MVT          MFP_CFG(GPIO20, AF4)
+#define GPIO126_RTC_MVT         MFP_CFG(GPIO126, AF1)
+
+/*
+ * PXA300 specific MFP configurations
+ */
+#ifdef CONFIG_CPU_PXA300
+#define GPIO99_USB_P2_2         MFP_CFG(GPIO99, AF2)
+#define GPIO99_USB_P2_5         MFP_CFG(GPIO99, AF3)
+#define GPIO99_USB_P2_6         MFP_CFG(GPIO99, AF4)
+#define GPIO100_USB_P2_2        MFP_CFG(GPIO100, AF4)
+#define GPIO100_USB_P2_5        MFP_CFG(GPIO100, AF5)
+#define GPIO101_USB_P2_1        MFP_CFG(GPIO101, AF2)
+#define GPIO102_USB_P2_4        MFP_CFG(GPIO102, AF2)
+#define GPIO104_USB_P2_3        MFP_CFG(GPIO104, AF2)
+#define GPIO105_USB_P2_5        MFP_CFG(GPIO105, AF2)
+#define GPIO100_USB_P2_6        MFP_CFG(GPIO100, AF2)
+#define GPIO106_USB_P2_7        MFP_CFG(GPIO106, AF2)
+#define GPIO103_USB_P2_8        MFP_CFG(GPIO103, AF2)
+
+/* U2D UTMI */
+#define GPIO38_UTM_CLK          MFP_CFG(GPIO38,  AF1)
+#define GPIO26_U2D_RXERROR      MFP_CFG(GPIO26,  AF3)
+#define GPIO50_U2D_RXERROR      MFP_CFG(GPIO50,  AF1)
+#define GPIO89_U2D_RXERROR      MFP_CFG(GPIO89,  AF5)
+#define GPIO24_UTM_RXVALID      MFP_CFG(GPIO24,  AF3)
+#define GPIO48_UTM_RXVALID      MFP_CFG(GPIO48,  AF2)
+#define GPIO87_UTM_RXVALID      MFP_CFG(GPIO87,  AF5)
+#define GPIO25_UTM_RXACTIVE     MFP_CFG(GPIO25,  AF3)
+#define GPIO47_UTM_RXACTIVE     MFP_CFG(GPIO47,  AF2)
+#define GPIO49_UTM_RXACTIVE     MFP_CFG(GPIO49,  AF1)
+#define GPIO88_UTM_RXACTIVE     MFP_CFG(GPIO88,  AF5)
+#define GPIO53_UTM_TXREADY      MFP_CFG(GPIO53,  AF1)
+#define GPIO67_UTM_LINESTATE_0  MFP_CFG(GPIO67,  AF3)
+#define GPIO92_UTM_LINESTATE_0  MFP_CFG(GPIO92,  AF3)
+#define GPIO104_UTM_LINESTATE_0 MFP_CFG(GPIO104, AF3)
+#define GPIO109_UTM_LINESTATE_0 MFP_CFG(GPIO109, AF4)
+#define GPIO68_UTM_LINESTATE_1  MFP_CFG(GPIO68,  AF3)
+#define GPIO93_UTM_LINESTATE_1  MFP_CFG(GPIO93,  AF3)
+#define GPIO105_UTM_LINESTATE_1 MFP_CFG(GPIO105, AF3)
+#define GPIO27_U2D_OPMODE_0     MFP_CFG(GPIO27,  AF4)
+#define GPIO51_U2D_OPMODE_0     MFP_CFG(GPIO51,  AF2)
+#define GPIO90_U2D_OPMODE_0     MFP_CFG(GPIO90,  AF7)
+#define GPIO28_U2D_OPMODE_1     MFP_CFG(GPIO28,  AF4)
+#define GPIO52_U2D_OPMODE_1     MFP_CFG(GPIO52,  AF2)
+#define GPIO106_U2D_OPMODE_1    MFP_CFG(GPIO106, AF3)
+#define GPIO110_U2D_OPMODE_1    MFP_CFG(GPIO110, AF5)
+#define GPIO76_U2D_RESET        MFP_CFG(GPIO76,  AF1)
+#define GPIO95_U2D_RESET        MFP_CFG(GPIO95,  AF2)
+#define GPIO100_U2D_RESET       MFP_CFG(GPIO100, AF3)
+#define GPIO66_U2D_SUSPEND      MFP_CFG(GPIO66,  AF3)
+#define GPIO98_U2D_SUSPEND      MFP_CFG(GPIO98,  AF2)
+#define GPIO103_U2D_SUSPEND     MFP_CFG(GPIO103, AF3)
+#define GPIO65_U2D_TERM_SEL     MFP_CFG(GPIO65,  AF5)
+#define GPIO97_U2D_TERM_SEL     MFP_CFG(GPIO97,  AF3)
+#define GPIO102_U2D_TERM_SEL    MFP_CFG(GPIO102, AF5)
+#define GPIO29_U2D_TXVALID      MFP_CFG(GPIO29,  AF3)
+#define GPIO52_U2D_TXVALID      MFP_CFG(GPIO52,  AF4)
+#define GPIO69_U2D_TXVALID      MFP_CFG(GPIO69,  AF3)
+#define GPIO85_U2D_TXVALID      MFP_CFG(GPIO85,  AF7)
+#define GPIO64_U2D_XCVR_SEL     MFP_CFG(GPIO64,  AF5)
+#define GPIO96_U2D_XCVR_SEL     MFP_CFG(GPIO96,  AF3)
+#define GPIO101_U2D_XCVR_SEL    MFP_CFG(GPIO101, AF5)
+#define GPIO30_UTM_PHYDATA_0    MFP_CFG(GPIO30,  AF3)
+#define GPIO31_UTM_PHYDATA_1    MFP_CFG(GPIO31,  AF3)
+#define GPIO32_UTM_PHYDATA_2    MFP_CFG(GPIO32,  AF3)
+#define GPIO33_UTM_PHYDATA_3    MFP_CFG(GPIO33,  AF3)
+#define GPIO34_UTM_PHYDATA_4    MFP_CFG(GPIO34,  AF3)
+#define GPIO35_UTM_PHYDATA_5    MFP_CFG(GPIO35,  AF3)
+#define GPIO36_UTM_PHYDATA_6    MFP_CFG(GPIO36,  AF3)
+#define GPIO37_UTM_PHYDATA_7    MFP_CFG(GPIO37,  AF3)
+#define GPIO39_UTM_PHYDATA_0    MFP_CFG(GPIO39,  AF3)
+#define GPIO40_UTM_PHYDATA_1    MFP_CFG(GPIO40,  AF3)
+#define GPIO41_UTM_PHYDATA_2    MFP_CFG(GPIO41,  AF3)
+#define GPIO42_UTM_PHYDATA_3    MFP_CFG(GPIO42,  AF3)
+#define GPIO43_UTM_PHYDATA_4    MFP_CFG(GPIO43,  AF3)
+#define GPIO44_UTM_PHYDATA_5    MFP_CFG(GPIO44,  AF3)
+#define GPIO45_UTM_PHYDATA_6    MFP_CFG(GPIO45,  AF3)
+#define GPIO46_UTM_PHYDATA_7    MFP_CFG(GPIO46,  AF3)
+#endif /* CONFIG_CPU_PXA300 */
+
+/*
+ * PXA310 specific MFP configurations
+ */
+#ifdef CONFIG_CPU_PXA310
+/* USB P2 */
+#define GPIO36_USB_P2_1         MFP_CFG(GPIO36, AF1)
+#define GPIO30_USB_P2_2         MFP_CFG(GPIO30, AF1)
+#define GPIO35_USB_P2_3         MFP_CFG(GPIO35, AF1)
+#define GPIO32_USB_P2_4         MFP_CFG(GPIO32, AF1)
+#define GPIO34_USB_P2_5         MFP_CFG(GPIO34, AF1)
+#define GPIO31_USB_P2_6         MFP_CFG(GPIO31, AF1)
+
+/* MMC1 */
+#define GPIO24_MMC1_CMD         MFP_CFG(GPIO24, AF3)
+#define GPIO29_MMC1_DAT0        MFP_CFG(GPIO29, AF3)
+
+/* MMC3 */
+#define GPIO103_MMC3_CLK        MFP_CFG(GPIO103, AF2)
+#define GPIO105_MMC3_CMD        MFP_CFG(GPIO105, AF2)
+#define GPIO11_2_MMC3_CLK       MFP_CFG(GPIO11_2, AF1)
+#define GPIO12_2_MMC3_CMD       MFP_CFG(GPIO12_2, AF1)
+#define GPIO7_2_MMC3_DAT0       MFP_CFG(GPIO7_2, AF1)
+#define GPIO8_2_MMC3_DAT1       MFP_CFG(GPIO8_2, AF1)
+#define GPIO9_2_MMC3_DAT2       MFP_CFG(GPIO9_2, AF1)
+#define GPIO10_2_MMC3_DAT3      MFP_CFG(GPIO10_2, AF1)
+
+/* ULPI */
+#define GPIO38_ULPI_CLK         MFP_CFG(GPIO38, AF1)
+#define GPIO30_ULPI_DATA_OUT_0  MFP_CFG(GPIO30, AF3)
+#define GPIO31_ULPI_DATA_OUT_1  MFP_CFG(GPIO31, AF3)
+#define GPIO32_ULPI_DATA_OUT_2  MFP_CFG(GPIO32, AF3)
+#define GPIO33_ULPI_DATA_OUT_3  MFP_CFG(GPIO33, AF3)
+#define GPIO34_ULPI_DATA_OUT_4  MFP_CFG(GPIO34, AF3)
+#define GPIO35_ULPI_DATA_OUT_5  MFP_CFG(GPIO35, AF3)
+#define GPIO36_ULPI_DATA_OUT_6  MFP_CFG(GPIO36, AF3)
+#define GPIO37_ULPI_DATA_OUT_7  MFP_CFG(GPIO37, AF3)
+#define GPIO33_ULPI_OTG_INTR    MFP_CFG(GPIO33, AF1)
+
+#define ULPI_DIR        MFP_CFG_DRV(ULPI_DIR, MFP_AF0, MFP_DS01X)
+#define ULPI_NXT        MFP_CFG_DRV(ULPI_NXT, MFP_AF0, MFP_DS01X)
+#define ULPI_STP        MFP_CFG_DRV(ULPI_STP, MFP_AF0, MFP_DS01X)
+#endif /* CONFIG_CPU_PXA310 */
+
+#endif /* __ASM_ARCH_MFP_PXA300_H */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa320.h b/include/asm-arm/arch-pxa/mfp-pxa320.h
new file mode 100644
index 000000000000..ae8ba34194cf
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mfp-pxa320.h
@@ -0,0 +1,446 @@
+/*
+ * linux/include/asm-arm/arch-pxa/mfp-pxa320.h
+ *
+ * PXA320 specific MFP configuration definitions
+ *
+ * Copyright (C) 2007 Marvell International Ltd.
+ * 2007-08-21: eric miao <eric.y.miao@gmail.com>
+ *             initial version
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MFP_PXA320_H
+#define __ASM_ARCH_MFP_PXA320_H
+
+#include <asm/arch/mfp.h>
+
+/* GPIO */
+#define GPIO46_GPIO             MFP_CFG(GPIO6, AF0)
+#define GPIO49_GPIO             MFP_CFG(GPIO49, AF0)
+#define GPIO50_GPIO             MFP_CFG(GPIO50, AF0)
+#define GPIO51_GPIO             MFP_CFG(GPIO51, AF0)
+#define GPIO52_GPIO             MFP_CFG(GPIO52, AF0)
+
+#define GPIO7_2_GPIO            MFP_CFG(GPIO7_2, AF0)
+#define GPIO8_2_GPIO            MFP_CFG(GPIO8_2, AF0)
+#define GPIO9_2_GPIO            MFP_CFG(GPIO9_2, AF0)
+#define GPIO10_2_GPIO           MFP_CFG(GPIO10_2, AF0)
+#define GPIO11_2_GPIO           MFP_CFG(GPIO11_2, AF0)
+#define GPIO12_2_GPIO           MFP_CFG(GPIO12_2, AF0)
+#define GPIO13_2_GPIO           MFP_CFG(GPIO13_2, AF0)
+#define GPIO14_2_GPIO           MFP_CFG(GPIO14_2, AF0)
+#define GPIO15_2_GPIO           MFP_CFG(GPIO15_2, AF0)
+#define GPIO16_2_GPIO           MFP_CFG(GPIO16_2, AF0)
+#define GPIO17_2_GPIO           MFP_CFG(GPIO17_2, AF0)
+
+/* Chip Select */
+#define GPIO4_nCS3              MFP_CFG(GPIO4, AF1)
+
+/* AC97 */
+#define GPIO34_AC97_SYSCLK      MFP_CFG(GPIO34, AF1)
+#define GPIO39_AC97_BITCLK      MFP_CFG(GPIO39, AF1)
+#define GPIO40_AC97_nACRESET    MFP_CFG(GPIO40, AF1)
+#define GPIO35_AC97_SDATA_IN_0  MFP_CFG(GPIO35, AF1)
+#define GPIO36_AC97_SDATA_IN_1  MFP_CFG(GPIO36, AF1)
+#define GPIO32_AC97_SDATA_IN_2  MFP_CFG(GPIO32, AF2)
+#define GPIO33_AC97_SDATA_IN_3  MFP_CFG(GPIO33, AF2)
+#define GPIO11_AC97_SDATA_IN_2  MFP_CFG(GPIO11, AF3)
+#define GPIO12_AC97_SDATA_IN_3  MFP_CFG(GPIO12, AF3)
+#define GPIO37_AC97_SDATA_OUT   MFP_CFG(GPIO37, AF1)
+#define GPIO38_AC97_SYNC        MFP_CFG(GPIO38, AF1)
+
+/* I2C */
+#define GPIO32_I2C_SCL          MFP_CFG_LPM(GPIO32, AF1, PULL_HIGH)
+#define GPIO33_I2C_SDA          MFP_CFG_LPM(GPIO33, AF1, PULL_HIGH)
+
+/* QCI */
+#define GPIO49_CI_DD_0          MFP_CFG_DRV(GPIO49, AF1, DS04X)
+#define GPIO50_CI_DD_1          MFP_CFG_DRV(GPIO50, AF1, DS04X)
+#define GPIO51_CI_DD_2          MFP_CFG_DRV(GPIO51, AF1, DS04X)
+#define GPIO52_CI_DD_3          MFP_CFG_DRV(GPIO52, AF1, DS04X)
+#define GPIO53_CI_DD_4          MFP_CFG_DRV(GPIO53, AF1, DS04X)
+#define GPIO54_CI_DD_5          MFP_CFG_DRV(GPIO54, AF1, DS04X)
+#define GPIO55_CI_DD_6          MFP_CFG_DRV(GPIO55, AF1, DS04X)
+#define GPIO56_CI_DD_7          MFP_CFG_DRV(GPIO56, AF0, DS04X)
+#define GPIO57_CI_DD_8          MFP_CFG_DRV(GPIO57, AF1, DS04X)
+#define GPIO58_CI_DD_9          MFP_CFG_DRV(GPIO58, AF1, DS04X)
+#define GPIO59_CI_MCLK          MFP_CFG_DRV(GPIO59, AF0, DS04X)
+#define GPIO60_CI_PCLK          MFP_CFG_DRV(GPIO60, AF0, DS04X)
+#define GPIO61_CI_HSYNC         MFP_CFG_DRV(GPIO61, AF0, DS04X)
+#define GPIO62_CI_VSYNC         MFP_CFG_DRV(GPIO62, AF0, DS04X)
+
+#define GPIO31_CIR_OUT          MFP_CFG(GPIO31, AF5)
+
+#define GPIO0_2_CLK_EXT         MFP_CFG(GPIO0_2, AF3)
+#define GPIO0_DRQ               MFP_CFG(GPIO0, AF2)
+#define GPIO11_EXT_SYNC0        MFP_CFG(GPIO11, AF5)
+#define GPIO12_EXT_SYNC1        MFP_CFG(GPIO12, AF6)
+#define GPIO0_2_HZ_CLK          MFP_CFG(GPIO0_2, AF1)
+#define GPIO14_HZ_CLK           MFP_CFG(GPIO14, AF4)
+#define GPIO30_ICP_RXD          MFP_CFG(GPIO30, AF1)
+#define GPIO31_ICP_TXD          MFP_CFG(GPIO31, AF1)
+
+#define GPIO83_KP_DKIN_0        MFP_CFG_LPM(GPIO83, AF3, FLOAT)
+#define GPIO84_KP_DKIN_1        MFP_CFG_LPM(GPIO84, AF3, FLOAT)
+#define GPIO85_KP_DKIN_2        MFP_CFG_LPM(GPIO85, AF3, FLOAT)
+#define GPIO86_KP_DKIN_3        MFP_CFG_LPM(GPIO86, AF3, FLOAT)
+
+#define GPIO105_KP_DKIN_0       MFP_CFG_LPM(GPIO105, AF2, FLOAT)
+#define GPIO106_KP_DKIN_1       MFP_CFG_LPM(GPIO106, AF2, FLOAT)
+#define GPIO107_KP_DKIN_2       MFP_CFG_LPM(GPIO107, AF2, FLOAT)
+#define GPIO108_KP_DKIN_3       MFP_CFG_LPM(GPIO108, AF2, FLOAT)
+#define GPIO109_KP_DKIN_4       MFP_CFG_LPM(GPIO109, AF2, FLOAT)
+#define GPIO110_KP_DKIN_5       MFP_CFG_LPM(GPIO110, AF2, FLOAT)
+#define GPIO111_KP_DKIN_6       MFP_CFG_LPM(GPIO111, AF2, FLOAT)
+#define GPIO112_KP_DKIN_7       MFP_CFG_LPM(GPIO112, AF2, FLOAT)
+
+#define GPIO113_KP_DKIN_0       MFP_CFG_LPM(GPIO113, AF2, FLOAT)
+#define GPIO114_KP_DKIN_1       MFP_CFG_LPM(GPIO114, AF2, FLOAT)
+#define GPIO115_KP_DKIN_2       MFP_CFG_LPM(GPIO115, AF2, FLOAT)
+#define GPIO116_KP_DKIN_3       MFP_CFG_LPM(GPIO116, AF2, FLOAT)
+#define GPIO117_KP_DKIN_4       MFP_CFG_LPM(GPIO117, AF2, FLOAT)
+#define GPIO118_KP_DKIN_5       MFP_CFG_LPM(GPIO118, AF2, FLOAT)
+#define GPIO119_KP_DKIN_6       MFP_CFG_LPM(GPIO119, AF2, FLOAT)
+#define GPIO120_KP_DKIN_7       MFP_CFG_LPM(GPIO120, AF2, FLOAT)
+
+#define GPIO127_KP_DKIN_0       MFP_CFG_LPM(GPIO127, AF2, FLOAT)
+#define GPIO126_KP_DKIN_1       MFP_CFG_LPM(GPIO126, AF2, FLOAT)
+
+#define GPIO2_2_KP_DKIN_0       MFP_CFG_LPM(GPIO2_2, AF2, FLOAT)
+#define GPIO3_2_KP_DKIN_1       MFP_CFG_LPM(GPIO3_2, AF2, FLOAT)
+#define GPIO125_KP_DKIN_2       MFP_CFG_LPM(GPIO125, AF2, FLOAT)
+#define GPIO124_KP_DKIN_3       MFP_CFG_LPM(GPIO124, AF2, FLOAT)
+#define GPIO123_KP_DKIN_4       MFP_CFG_LPM(GPIO123, AF2, FLOAT)
+#define GPIO122_KP_DKIN_5       MFP_CFG_LPM(GPIO122, AF2, FLOAT)
+#define GPIO121_KP_DKIN_6       MFP_CFG_LPM(GPIO121, AF2, FLOAT)
+#define GPIO4_2_KP_DKIN_7       MFP_CFG_LPM(GPIO4_2, AF2, FLOAT)
+
+#define GPIO113_KP_MKIN_0       MFP_CFG_LPM(GPIO113, AF1, FLOAT)
+#define GPIO114_KP_MKIN_1       MFP_CFG_LPM(GPIO114, AF1, FLOAT)
+#define GPIO115_KP_MKIN_2       MFP_CFG_LPM(GPIO115, AF1, FLOAT)
+#define GPIO116_KP_MKIN_3       MFP_CFG_LPM(GPIO116, AF1, FLOAT)
+#define GPIO117_KP_MKIN_4       MFP_CFG_LPM(GPIO117, AF1, FLOAT)
+#define GPIO118_KP_MKIN_5       MFP_CFG_LPM(GPIO118, AF1, FLOAT)
+#define GPIO119_KP_MKIN_6       MFP_CFG_LPM(GPIO119, AF1, FLOAT)
+#define GPIO120_KP_MKIN_7       MFP_CFG_LPM(GPIO120, AF1, FLOAT)
+
+#define GPIO83_KP_MKOUT_0       MFP_CFG_LPM(GPIO83, AF2, DRIVE_HIGH)
+#define GPIO84_KP_MKOUT_1       MFP_CFG_LPM(GPIO84, AF2, DRIVE_HIGH)
+#define GPIO85_KP_MKOUT_2       MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH)
+#define GPIO86_KP_MKOUT_3       MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH)
+#define GPIO13_KP_MKOUT_4       MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH)
+#define GPIO14_KP_MKOUT_5       MFP_CFG_LPM(GPIO14, AF3, DRIVE_HIGH)
+
+#define GPIO121_KP_MKOUT_0      MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH)
+#define GPIO122_KP_MKOUT_1      MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH)
+#define GPIO123_KP_MKOUT_2      MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH)
+#define GPIO124_KP_MKOUT_3      MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH)
+#define GPIO125_KP_MKOUT_4      MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH)
+#define GPIO126_KP_MKOUT_5      MFP_CFG_LPM(GPIO126, AF1, DRIVE_HIGH)
+#define GPIO127_KP_MKOUT_6      MFP_CFG_LPM(GPIO127, AF1, DRIVE_HIGH)
+#define GPIO5_2_KP_MKOUT_7      MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH)
+
+/* LCD */
+#define GPIO6_2_LCD_LDD_0       MFP_CFG_DRV(GPIO6_2, AF1, DS01X)
+#define GPIO7_2_LCD_LDD_1       MFP_CFG_DRV(GPIO7_2, AF1, DS01X)
+#define GPIO8_2_LCD_LDD_2       MFP_CFG_DRV(GPIO8_2, AF1, DS01X)
+#define GPIO9_2_LCD_LDD_3       MFP_CFG_DRV(GPIO9_2, AF1, DS01X)
+#define GPIO10_2_LCD_LDD_4      MFP_CFG_DRV(GPIO10_2, AF1, DS01X)
+#define GPIO11_2_LCD_LDD_5      MFP_CFG_DRV(GPIO11_2, AF1, DS01X)
+#define GPIO12_2_LCD_LDD_6      MFP_CFG_DRV(GPIO12_2, AF1, DS01X)
+#define GPIO13_2_LCD_LDD_7      MFP_CFG_DRV(GPIO13_2, AF1, DS01X)
+#define GPIO63_LCD_LDD_8        MFP_CFG_DRV(GPIO63, AF1, DS01X)
+#define GPIO64_LCD_LDD_9        MFP_CFG_DRV(GPIO64, AF1, DS01X)
+#define GPIO65_LCD_LDD_10       MFP_CFG_DRV(GPIO65, AF1, DS01X)
+#define GPIO66_LCD_LDD_11       MFP_CFG_DRV(GPIO66, AF1, DS01X)
+#define GPIO67_LCD_LDD_12       MFP_CFG_DRV(GPIO67, AF1, DS01X)
+#define GPIO68_LCD_LDD_13       MFP_CFG_DRV(GPIO68, AF1, DS01X)
+#define GPIO69_LCD_LDD_14       MFP_CFG_DRV(GPIO69, AF1, DS01X)
+#define GPIO70_LCD_LDD_15       MFP_CFG_DRV(GPIO70, AF1, DS01X)
+#define GPIO71_LCD_LDD_16       MFP_CFG_DRV(GPIO71, AF1, DS01X)
+#define GPIO72_LCD_LDD_17       MFP_CFG_DRV(GPIO72, AF1, DS01X)
+#define GPIO73_LCD_CS_N         MFP_CFG_DRV(GPIO73, AF2, DS01X)
+#define GPIO74_LCD_VSYNC        MFP_CFG_DRV(GPIO74, AF2, DS01X)
+#define GPIO14_2_LCD_FCLK       MFP_CFG_DRV(GPIO14_2, AF1, DS01X)
+#define GPIO15_2_LCD_LCLK       MFP_CFG_DRV(GPIO15_2, AF1, DS01X)
+#define GPIO16_2_LCD_PCLK       MFP_CFG_DRV(GPIO16_2, AF1, DS01X)
+#define GPIO17_2_LCD_BIAS       MFP_CFG_DRV(GPIO17_2, AF1, DS01X)
+#define GPIO64_LCD_VSYNC        MFP_CFG_DRV(GPIO64, AF2, DS01X)
+#define GPIO63_LCD_CS_N         MFP_CFG_DRV(GPIO63, AF2, DS01X)
+
+#define GPIO6_2_MLCD_DD_0       MFP_CFG_DRV(GPIO6_2, AF7, DS08X)
+#define GPIO7_2_MLCD_DD_1       MFP_CFG_DRV(GPIO7_2, AF7, DS08X)
+#define GPIO8_2_MLCD_DD_2       MFP_CFG_DRV(GPIO8_2, AF7, DS08X)
+#define GPIO9_2_MLCD_DD_3       MFP_CFG_DRV(GPIO9_2, AF7, DS08X)
+#define GPIO10_2_MLCD_DD_4      MFP_CFG_DRV(GPIO10_2, AF7, DS08X)
+#define GPIO11_2_MLCD_DD_5      MFP_CFG_DRV(GPIO11_2, AF7, DS08X)
+#define GPIO12_2_MLCD_DD_6      MFP_CFG_DRV(GPIO12_2, AF7, DS08X)
+#define GPIO13_2_MLCD_DD_7      MFP_CFG_DRV(GPIO13_2, AF7, DS08X)
+#define GPIO63_MLCD_DD_8        MFP_CFG_DRV(GPIO63, AF7, DS08X)
+#define GPIO64_MLCD_DD_9        MFP_CFG_DRV(GPIO64, AF7, DS08X)
+#define GPIO65_MLCD_DD_10       MFP_CFG_DRV(GPIO65, AF7, DS08X)
+#define GPIO66_MLCD_DD_11       MFP_CFG_DRV(GPIO66, AF7, DS08X)
+#define GPIO67_MLCD_DD_12       MFP_CFG_DRV(GPIO67, AF7, DS08X)
+#define GPIO68_MLCD_DD_13       MFP_CFG_DRV(GPIO68, AF7, DS08X)
+#define GPIO69_MLCD_DD_14       MFP_CFG_DRV(GPIO69, AF7, DS08X)
+#define GPIO70_MLCD_DD_15       MFP_CFG_DRV(GPIO70, AF7, DS08X)
+#define GPIO71_MLCD_DD_16       MFP_CFG_DRV(GPIO71, AF7, DS08X)
+#define GPIO72_MLCD_DD_17       MFP_CFG_DRV(GPIO72, AF7, DS08X)
+#define GPIO73_MLCD_CS          MFP_CFG_DRV(GPIO73, AF7, DS08X)
+#define GPIO74_MLCD_VSYNC       MFP_CFG_DRV(GPIO74, AF7, DS08X)
+#define GPIO14_2_MLCD_FCLK      MFP_CFG_DRV(GPIO14_2, AF7, DS08X)
+#define GPIO15_2_MLCD_LCLK      MFP_CFG_DRV(GPIO15_2, AF7, DS08X)
+#define GPIO16_2_MLCD_PCLK      MFP_CFG_DRV(GPIO16_2, AF7, DS08X)
+#define GPIO17_2_MLCD_BIAS      MFP_CFG_DRV(GPIO17_2, AF7, DS08X)
+
+/* MMC1 */
+#define GPIO9_MMC1_CMD          MFP_CFG_LPM(GPIO9,  AF4, DRIVE_HIGH)
+#define GPIO22_MMC1_CLK         MFP_CFG_LPM(GPIO22, AF4, DRIVE_HIGH)
+#define GPIO23_MMC1_CMD         MFP_CFG_LPM(GPIO23, AF4, DRIVE_HIGH)
+#define GPIO30_MMC1_CLK         MFP_CFG_LPM(GPIO30, AF4, DRIVE_HIGH)
+#define GPIO31_MMC1_CMD         MFP_CFG_LPM(GPIO31, AF4, DRIVE_HIGH)
+#define GPIO5_MMC1_DAT0         MFP_CFG_LPM(GPIO5,  AF4, DRIVE_HIGH)
+#define GPIO6_MMC1_DAT1         MFP_CFG_LPM(GPIO6,  AF4, DRIVE_HIGH)
+#define GPIO7_MMC1_DAT2         MFP_CFG_LPM(GPIO7,  AF4, DRIVE_HIGH)
+#define GPIO8_MMC1_DAT3         MFP_CFG_LPM(GPIO8,  AF4, DRIVE_HIGH)
+#define GPIO18_MMC1_DAT0        MFP_CFG_LPM(GPIO18, AF4, DRIVE_HIGH)
+#define GPIO19_MMC1_DAT1        MFP_CFG_LPM(GPIO19, AF4, DRIVE_HIGH)
+#define GPIO20_MMC1_DAT2        MFP_CFG_LPM(GPIO20, AF4, DRIVE_HIGH)
+#define GPIO21_MMC1_DAT3        MFP_CFG_LPM(GPIO21, AF4, DRIVE_HIGH)
+
+#define GPIO28_MMC2_CLK         MFP_CFG_LPM(GPIO28, AF4, PULL_HIGH)
+#define GPIO29_MMC2_CMD         MFP_CFG_LPM(GPIO29, AF4, PULL_HIGH)
+#define GPIO30_MMC2_CLK         MFP_CFG_LPM(GPIO30, AF3, PULL_HIGH)
+#define GPIO31_MMC2_CMD         MFP_CFG_LPM(GPIO31, AF3, PULL_HIGH)
+#define GPIO79_MMC2_CLK         MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH)
+#define GPIO80_MMC2_CMD         MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH)
+
+#define GPIO5_MMC2_DAT0         MFP_CFG_LPM(GPIO5, AF2, PULL_HIGH)
+#define GPIO6_MMC2_DAT1         MFP_CFG_LPM(GPIO6, AF2, PULL_HIGH)
+#define GPIO7_MMC2_DAT2         MFP_CFG_LPM(GPIO7, AF2, PULL_HIGH)
+#define GPIO8_MMC2_DAT3         MFP_CFG_LPM(GPIO8, AF2, PULL_HIGH)
+#define GPIO24_MMC2_DAT0        MFP_CFG_LPM(GPIO24, AF4, PULL_HIGH)
+#define GPIO75_MMC2_DAT0        MFP_CFG_LPM(GPIO75, AF4, PULL_HIGH)
+#define GPIO25_MMC2_DAT1        MFP_CFG_LPM(GPIO25, AF4, PULL_HIGH)
+#define GPIO76_MMC2_DAT1        MFP_CFG_LPM(GPIO76, AF4, PULL_HIGH)
+#define GPIO26_MMC2_DAT2        MFP_CFG_LPM(GPIO26, AF4, PULL_HIGH)
+#define GPIO77_MMC2_DAT2        MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH)
+#define GPIO27_MMC2_DAT3        MFP_CFG_LPM(GPIO27, AF4, PULL_HIGH)
+#define GPIO78_MMC2_DAT3        MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH)
+
+/* 1-Wire */
+#define GPIO14_ONE_WIRE         MFP_CFG_LPM(GPIO14,  AF5, FLOAT)
+#define GPIO0_2_ONE_WIRE        MFP_CFG_LPM(GPIO0_2, AF2, FLOAT)
+
+/* SSP1 */
+#define GPIO87_SSP1_EXTCLK      MFP_CFG(GPIO87, AF1)
+#define GPIO88_SSP1_SYSCLK      MFP_CFG(GPIO88, AF1)
+#define GPIO83_SSP1_SCLK        MFP_CFG(GPIO83, AF1)
+#define GPIO84_SSP1_SFRM        MFP_CFG(GPIO84, AF1)
+#define GPIO85_SSP1_RXD         MFP_CFG(GPIO85, AF6)
+#define GPIO85_SSP1_TXD         MFP_CFG(GPIO85, AF1)
+#define GPIO86_SSP1_RXD         MFP_CFG(GPIO86, AF1)
+#define GPIO86_SSP1_TXD         MFP_CFG(GPIO86, AF6)
+
+/* SSP2 */
+#define GPIO39_SSP2_EXTCLK      MFP_CFG(GPIO39, AF2)
+#define GPIO40_SSP2_SYSCLK      MFP_CFG(GPIO40, AF2)
+#define GPIO12_SSP2_SCLK        MFP_CFG(GPIO12, AF2)
+#define GPIO35_SSP2_SCLK        MFP_CFG(GPIO35, AF2)
+#define GPIO36_SSP2_SFRM        MFP_CFG(GPIO36, AF2)
+#define GPIO37_SSP2_RXD         MFP_CFG(GPIO37, AF5)
+#define GPIO37_SSP2_TXD         MFP_CFG(GPIO37, AF2)
+#define GPIO38_SSP2_RXD         MFP_CFG(GPIO38, AF2)
+#define GPIO38_SSP2_TXD         MFP_CFG(GPIO38, AF5)
+
+#define GPIO69_SSP3_SCLK        MFP_CFG(GPIO69, AF2, DS08X, FLOAT)
+#define GPIO70_SSP3_FRM         MFP_CFG(GPIO70, AF2, DS08X, DRIVE_LOW)
+#define GPIO89_SSP3_SCLK        MFP_CFG(GPIO89, AF1, DS08X, FLOAT)
+#define GPIO90_SSP3_FRM         MFP_CFG(GPIO90, AF1, DS08X, DRIVE_LOW)
+#define GPIO71_SSP3_RXD         MFP_CFG_X(GPIO71, AF5, DS08X, FLOAT)
+#define GPIO71_SSP3_TXD         MFP_CFG_X(GPIO71, AF2, DS08X, DRIVE_LOW)
+#define GPIO72_SSP3_RXD         MFP_CFG_X(GPIO72, AF2, DS08X, FLOAT)
+#define GPIO72_SSP3_TXD         MFP_CFG_X(GPIO72, AF5, DS08X, DRIVE_LOW)
+#define GPIO91_SSP3_RXD         MFP_CFG_X(GPIO91, AF5, DS08X, FLOAT)
+#define GPIO91_SSP3_TXD         MFP_CFG_X(GPIO91, AF1, DS08X, DRIVE_LOW)
+#define GPIO92_SSP3_RXD         MFP_CFG_X(GPIO92, AF1, DS08X, FLOAT)
+#define GPIO92_SSP3_TXD         MFP_CFG_X(GPIO92, AF5, DS08X, DRIVE_LOW)
+
+#define GPIO93_SSP4_SCLK        MFP_CFG_LPM(GPIO93, AF1, PULL_HIGH)
+#define GPIO94_SSP4_FRM         MFP_CFG_LPM(GPIO94, AF1, PULL_HIGH)
+#define GPIO94_SSP4_RXD         MFP_CFG_LPM(GPIO94, AF5, PULL_HIGH)
+#define GPIO95_SSP4_RXD         MFP_CFG_LPM(GPIO95, AF5, PULL_HIGH)
+#define GPIO95_SSP4_TXD         MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
+#define GPIO96_SSP4_RXD         MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
+#define GPIO96_SSP4_TXD         MFP_CFG_LPM(GPIO96, AF5, PULL_HIGH)
+
+/* UART1 */
+#define GPIO41_UART1_RXD        MFP_CFG_LPM(GPIO41, AF2, FLOAT)
+#define GPIO41_UART1_TXD        MFP_CFG_LPM(GPIO41, AF4, FLOAT)
+#define GPIO42_UART1_RXD        MFP_CFG_LPM(GPIO42, AF4, FLOAT)
+#define GPIO42_UART1_TXD        MFP_CFG_LPM(GPIO42, AF2, FLOAT)
+#define GPIO97_UART1_RXD        MFP_CFG_LPM(GPIO97, AF1, FLOAT)
+#define GPIO97_UART1_TXD        MFP_CFG_LPM(GPIO97, AF6, FLOAT)
+#define GPIO98_UART1_RXD        MFP_CFG_LPM(GPIO98, AF6, FLOAT)
+#define GPIO98_UART1_TXD        MFP_CFG_LPM(GPIO98, AF1, FLOAT)
+#define GPIO43_UART1_CTS        MFP_CFG_LPM(GPIO43, AF2, FLOAT)
+#define GPIO43_UART1_RTS        MFP_CFG_LPM(GPIO43, AF4, FLOAT)
+#define GPIO48_UART1_CTS        MFP_CFG_LPM(GPIO48, AF4, FLOAT)
+#define GPIO48_UART1_RTS        MFP_CFG_LPM(GPIO48, AF2, FLOAT)
+#define GPIO99_UART1_CTS        MFP_CFG_LPM(GPIO99, AF1, FLOAT)
+#define GPIO99_UART1_RTS        MFP_CFG_LPM(GPIO99, AF6, FLOAT)
+#define GPIO104_UART1_CTS       MFP_CFG_LPM(GPIO104, AF6, FLOAT)
+#define GPIO104_UART1_RTS       MFP_CFG_LPM(GPIO104, AF1, FLOAT)
+#define GPIO45_UART1_DTR        MFP_CFG_LPM(GPIO45, AF4, FLOAT)
+#define GPIO45_UART1_DSR        MFP_CFG_LPM(GPIO45, AF2, FLOAT)
+#define GPIO47_UART1_DTR        MFP_CFG_LPM(GPIO47, AF2, FLOAT)
+#define GPIO47_UART1_DSR        MFP_CFG_LPM(GPIO47, AF4, FLOAT)
+#define GPIO101_UART1_DTR       MFP_CFG_LPM(GPIO101, AF6, FLOAT)
+#define GPIO101_UART1_DSR       MFP_CFG_LPM(GPIO101, AF1, FLOAT)
+#define GPIO103_UART1_DTR       MFP_CFG_LPM(GPIO103, AF1, FLOAT)
+#define GPIO103_UART1_DSR       MFP_CFG_LPM(GPIO103, AF6, FLOAT)
+#define GPIO44_UART1_DCD        MFP_CFG_LPM(GPIO44, AF2, FLOAT)
+#define GPIO100_UART1_DCD       MFP_CFG_LPM(GPIO100, AF1, FLOAT)
+#define GPIO46_UART1_RI         MFP_CFG_LPM(GPIO46, AF2, FLOAT)
+#define GPIO102_UART1_RI        MFP_CFG_LPM(GPIO102, AF1, FLOAT)
+
+/* UART2 */
+#define GPIO109_UART2_CTS       MFP_CFG_LPM(GPIO109, AF3, FLOAT)
+#define GPIO109_UART2_RTS       MFP_CFG_LPM(GPIO109, AF1, FLOAT)
+#define GPIO112_UART2_CTS       MFP_CFG_LPM(GPIO112, AF1, FLOAT)
+#define GPIO112_UART2_RTS       MFP_CFG_LPM(GPIO112, AF3, FLOAT)
+#define GPIO110_UART2_RXD       MFP_CFG_LPM(GPIO110, AF1, FLOAT)
+#define GPIO110_UART2_TXD       MFP_CFG_LPM(GPIO110, AF3, FLOAT)
+#define GPIO111_UART2_RXD       MFP_CFG_LPM(GPIO111, AF3, FLOAT)
+#define GPIO111_UART2_TXD       MFP_CFG_LPM(GPIO111, AF1, FLOAT)
+
+/* UART3 */
+#define GPIO89_UART3_CTS        MFP_CFG_LPM(GPIO89, AF2, FLOAT)
+#define GPIO89_UART3_RTS        MFP_CFG_LPM(GPIO89, AF4, FLOAT)
+#define GPIO90_UART3_CTS        MFP_CFG_LPM(GPIO90, AF4, FLOAT)
+#define GPIO90_UART3_RTS        MFP_CFG_LPM(GPIO90, AF2, FLOAT)
+#define GPIO105_UART3_CTS       MFP_CFG_LPM(GPIO105, AF1, FLOAT)
+#define GPIO105_UART3_RTS       MFP_CFG_LPM(GPIO105, AF3, FLOAT)
+#define GPIO106_UART3_CTS       MFP_CFG_LPM(GPIO106, AF3, FLOAT)
+#define GPIO106_UART3_RTS       MFP_CFG_LPM(GPIO106, AF1, FLOAT)
+#define GPIO30_UART3_RXD        MFP_CFG_LPM(GPIO30, AF2, FLOAT)
+#define GPIO30_UART3_TXD        MFP_CFG_LPM(GPIO30, AF6, FLOAT)
+#define GPIO31_UART3_RXD        MFP_CFG_LPM(GPIO31, AF6, FLOAT)
+#define GPIO31_UART3_TXD        MFP_CFG_LPM(GPIO31, AF2, FLOAT)
+#define GPIO91_UART3_RXD        MFP_CFG_LPM(GPIO91, AF4, FLOAT)
+#define GPIO91_UART3_TXD        MFP_CFG_LPM(GPIO91, AF2, FLOAT)
+#define GPIO92_UART3_RXD        MFP_CFG_LPM(GPIO92, AF2, FLOAT)
+#define GPIO92_UART3_TXD        MFP_CFG_LPM(GPIO92, AF4, FLOAT)
+#define GPIO107_UART3_RXD       MFP_CFG_LPM(GPIO107, AF3, FLOAT)
+#define GPIO107_UART3_TXD       MFP_CFG_LPM(GPIO107, AF1, FLOAT)
+#define GPIO108_UART3_RXD       MFP_CFG_LPM(GPIO108, AF1, FLOAT)
+#define GPIO108_UART3_TXD       MFP_CFG_LPM(GPIO108, AF3, FLOAT)
+
+
+/* USB 2.0 UTMI */
+#define GPIO10_UTM_CLK          MFP_CFG(GPIO10, AF1)
+#define GPIO36_U2D_RXERROR      MFP_CFG(GPIO36, AF3)
+#define GPIO60_U2D_RXERROR      MFP_CFG(GPIO60, AF1)
+#define GPIO87_U2D_RXERROR      MFP_CFG(GPIO87, AF5)
+#define GPIO34_UTM_RXVALID      MFP_CFG(GPIO34, AF3)
+#define GPIO58_UTM_RXVALID      MFP_CFG(GPIO58, AF2)
+#define GPIO85_UTM_RXVALID      MFP_CFG(GPIO85, AF5)
+#define GPIO35_UTM_RXACTIVE     MFP_CFG(GPIO35, AF3)
+#define GPIO59_UTM_RXACTIVE     MFP_CFG(GPIO59, AF1)
+#define GPIO86_UTM_RXACTIVE     MFP_CFG(GPIO86, AF5)
+#define GPIO73_UTM_TXREADY      MFP_CFG(GPIO73, AF1)
+#define GPIO68_UTM_LINESTATE_0  MFP_CFG(GPIO68, AF3)
+#define GPIO90_UTM_LINESTATE_0  MFP_CFG(GPIO90, AF3)
+#define GPIO102_UTM_LINESTATE_0 MFP_CFG(GPIO102, AF3)
+#define GPIO107_UTM_LINESTATE_0 MFP_CFG(GPIO107, AF4)
+#define GPIO69_UTM_LINESTATE_1  MFP_CFG(GPIO69, AF3)
+#define GPIO91_UTM_LINESTATE_1  MFP_CFG(GPIO91, AF3)
+#define GPIO103_UTM_LINESTATE_1 MFP_CFG(GPIO103, AF3)
+
+#define GPIO41_U2D_PHYDATA_0    MFP_CFG(GPIO41, AF3)
+#define GPIO42_U2D_PHYDATA_1    MFP_CFG(GPIO42, AF3)
+#define GPIO43_U2D_PHYDATA_2    MFP_CFG(GPIO43, AF3)
+#define GPIO44_U2D_PHYDATA_3    MFP_CFG(GPIO44, AF3)
+#define GPIO45_U2D_PHYDATA_4    MFP_CFG(GPIO45, AF3)
+#define GPIO46_U2D_PHYDATA_5    MFP_CFG(GPIO46, AF3)
+#define GPIO47_U2D_PHYDATA_6    MFP_CFG(GPIO47, AF3)
+#define GPIO48_U2D_PHYDATA_7    MFP_CFG(GPIO48, AF3)
+
+#define GPIO49_U2D_PHYDATA_0    MFP_CFG(GPIO49, AF3)
+#define GPIO50_U2D_PHYDATA_1    MFP_CFG(GPIO50, AF3)
+#define GPIO51_U2D_PHYDATA_2    MFP_CFG(GPIO51, AF3)
+#define GPIO52_U2D_PHYDATA_3    MFP_CFG(GPIO52, AF3)
+#define GPIO53_U2D_PHYDATA_4    MFP_CFG(GPIO53, AF3)
+#define GPIO54_U2D_PHYDATA_5    MFP_CFG(GPIO54, AF3)
+#define GPIO55_U2D_PHYDATA_6    MFP_CFG(GPIO55, AF3)
+#define GPIO56_U2D_PHYDATA_7    MFP_CFG(GPIO56, AF3)
+
+#define GPIO37_U2D_OPMODE0      MFP_CFG(GPIO37, AF4)
+#define GPIO61_U2D_OPMODE0      MFP_CFG(GPIO61, AF2)
+#define GPIO88_U2D_OPMODE0      MFP_CFG(GPIO88, AF7)
+
+#define GPIO38_U2D_OPMODE1      MFP_CFG(GPIO38, AF4)
+#define GPIO62_U2D_OPMODE1      MFP_CFG(GPIO62, AF2)
+#define GPIO104_U2D_OPMODE1     MFP_CFG(GPIO104, AF4)
+#define GPIO108_U2D_OPMODE1     MFP_CFG(GPIO108, AF5)
+
+#define GPIO74_U2D_RESET        MFP_CFG(GPIO74, AF1)
+#define GPIO93_U2D_RESET        MFP_CFG(GPIO93, AF2)
+#define GPIO98_U2D_RESET        MFP_CFG(GPIO98, AF3)
+
+#define GPIO67_U2D_SUSPEND      MFP_CFG(GPIO67, AF3)
+#define GPIO96_U2D_SUSPEND      MFP_CFG(GPIO96, AF2)
+#define GPIO101_U2D_SUSPEND     MFP_CFG(GPIO101, AF3)
+
+#define GPIO66_U2D_TERM_SEL     MFP_CFG(GPIO66, AF5)
+#define GPIO95_U2D_TERM_SEL     MFP_CFG(GPIO95, AF3)
+#define GPIO97_U2D_TERM_SEL     MFP_CFG(GPIO97, AF7)
+#define GPIO100_U2D_TERM_SEL    MFP_CFG(GPIO100, AF5)
+
+#define GPIO39_U2D_TXVALID      MFP_CFG(GPIO39, AF4)
+#define GPIO70_U2D_TXVALID      MFP_CFG(GPIO70, AF5)
+#define GPIO83_U2D_TXVALID      MFP_CFG(GPIO83, AF7)
+
+#define GPIO65_U2D_XCVR_SEL     MFP_CFG(GPIO65, AF5)
+#define GPIO94_U2D_XCVR_SEL     MFP_CFG(GPIO94, AF3)
+#define GPIO99_U2D_XCVR_SEL     MFP_CFG(GPIO99, AF5)
+
+/* USB Host 1.1 */
+#define GPIO2_2_USBH_PEN        MFP_CFG(GPIO2_2, AF1)
+#define GPIO3_2_USBH_PWR        MFP_CFG(GPIO3_2, AF1)
+
+/* USB P2 */
+#define GPIO97_USB_P2_2         MFP_CFG(GPIO97, AF2)
+#define GPIO97_USB_P2_6         MFP_CFG(GPIO97, AF4)
+#define GPIO98_USB_P2_2         MFP_CFG(GPIO98, AF4)
+#define GPIO98_USB_P2_6         MFP_CFG(GPIO98, AF2)
+#define GPIO99_USB_P2_1         MFP_CFG(GPIO99, AF2)
+#define GPIO100_USB_P2_4        MFP_CFG(GPIO100, AF2)
+#define GPIO101_USB_P2_8        MFP_CFG(GPIO101, AF2)
+#define GPIO102_USB_P2_3        MFP_CFG(GPIO102, AF2)
+#define GPIO103_USB_P2_5        MFP_CFG(GPIO103, AF2)
+#define GPIO104_USB_P2_7        MFP_CFG(GPIO104, AF2)
+
+/* USB P3 */
+#define GPIO75_USB_P3_1         MFP_CFG(GPIO75, AF2)
+#define GPIO76_USB_P3_2         MFP_CFG(GPIO76, AF2)
+#define GPIO77_USB_P3_3         MFP_CFG(GPIO77, AF2)
+#define GPIO78_USB_P3_4         MFP_CFG(GPIO78, AF2)
+#define GPIO79_USB_P3_5         MFP_CFG(GPIO79, AF2)
+#define GPIO80_USB_P3_6         MFP_CFG(GPIO80, AF2)
+
+#define GPIO13_CHOUT0           MFP_CFG(GPIO13, AF6)
+#define GPIO14_CHOUT1           MFP_CFG(GPIO14, AF6)
+
+#define GPIO2_RDY               MFP_CFG(GPIO2, AF1)
+#define GPIO5_NPIOR             MFP_CFG(GPIO5, AF3)
+
+#define GPIO11_PWM0_OUT         MFP_CFG(GPIO11, AF1)
+#define GPIO12_PWM1_OUT         MFP_CFG(GPIO12, AF1)
+#define GPIO13_PWM2_OUT         MFP_CFG(GPIO13, AF1)
+#define GPIO14_PWM3_OUT         MFP_CFG(GPIO14, AF1)
+
+#endif /* __ASM_ARCH_MFP_PXA320_H */
diff --git a/include/asm-arm/arch-pxa/mfp.h b/include/asm-arm/arch-pxa/mfp.h
new file mode 100644
index 000000000000..60291742ffdd
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mfp.h
@@ -0,0 +1,576 @@
+/*
+ * linux/include/asm-arm/arch-pxa/mfp.h
+ *
+ * Multi-Function Pin Definitions
+ *
+ * Copyright (C) 2007 Marvell International Ltd.
+ *
+ * 2007-8-21: eric miao <eric.y.miao@gmail.com>
+ *            initial version
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MFP_H
+#define __ASM_ARCH_MFP_H
+
+#define MFPR_BASE       (0x40e10000)
+#define MFPR_SIZE       (PAGE_SIZE)
+
+#define mfp_to_gpio(m)  ((m) % 128)
+
+/* list of all the configurable MFP pins */
+enum {
+        MFP_PIN_INVALID = -1,
+
+        MFP_PIN_GPIO0 = 0,
+        MFP_PIN_GPIO1,
+        MFP_PIN_GPIO2,
+        MFP_PIN_GPIO3,
+        MFP_PIN_GPIO4,
+        MFP_PIN_GPIO5,
+        MFP_PIN_GPIO6,
+        MFP_PIN_GPIO7,
+        MFP_PIN_GPIO8,
+        MFP_PIN_GPIO9,
+        MFP_PIN_GPIO10,
+        MFP_PIN_GPIO11,
+        MFP_PIN_GPIO12,
+        MFP_PIN_GPIO13,
+        MFP_PIN_GPIO14,
+        MFP_PIN_GPIO15,
+        MFP_PIN_GPIO16,
+        MFP_PIN_GPIO17,
+        MFP_PIN_GPIO18,
+        MFP_PIN_GPIO19,
+        MFP_PIN_GPIO20,
+        MFP_PIN_GPIO21,
+        MFP_PIN_GPIO22,
+        MFP_PIN_GPIO23,
+        MFP_PIN_GPIO24,
+        MFP_PIN_GPIO25,
+        MFP_PIN_GPIO26,
+        MFP_PIN_GPIO27,
+        MFP_PIN_GPIO28,
+        MFP_PIN_GPIO29,
+        MFP_PIN_GPIO30,
+        MFP_PIN_GPIO31,
+        MFP_PIN_GPIO32,
+        MFP_PIN_GPIO33,
+        MFP_PIN_GPIO34,
+        MFP_PIN_GPIO35,
+        MFP_PIN_GPIO36,
+        MFP_PIN_GPIO37,
+        MFP_PIN_GPIO38,
+        MFP_PIN_GPIO39,
+        MFP_PIN_GPIO40,
+        MFP_PIN_GPIO41,
+        MFP_PIN_GPIO42,
+        MFP_PIN_GPIO43,
+        MFP_PIN_GPIO44,
+        MFP_PIN_GPIO45,
+        MFP_PIN_GPIO46,
+        MFP_PIN_GPIO47,
+        MFP_PIN_GPIO48,
+        MFP_PIN_GPIO49,
+        MFP_PIN_GPIO50,
+        MFP_PIN_GPIO51,
+        MFP_PIN_GPIO52,
+        MFP_PIN_GPIO53,
+        MFP_PIN_GPIO54,
+        MFP_PIN_GPIO55,
+        MFP_PIN_GPIO56,
+        MFP_PIN_GPIO57,
+        MFP_PIN_GPIO58,
+        MFP_PIN_GPIO59,
+        MFP_PIN_GPIO60,
+        MFP_PIN_GPIO61,
+        MFP_PIN_GPIO62,
+        MFP_PIN_GPIO63,
+        MFP_PIN_GPIO64,
+        MFP_PIN_GPIO65,
+        MFP_PIN_GPIO66,
+        MFP_PIN_GPIO67,
+        MFP_PIN_GPIO68,
+        MFP_PIN_GPIO69,
+        MFP_PIN_GPIO70,
+        MFP_PIN_GPIO71,
+        MFP_PIN_GPIO72,
+        MFP_PIN_GPIO73,
+        MFP_PIN_GPIO74,
+        MFP_PIN_GPIO75,
+        MFP_PIN_GPIO76,
+        MFP_PIN_GPIO77,
+        MFP_PIN_GPIO78,
+        MFP_PIN_GPIO79,
+        MFP_PIN_GPIO80,
+        MFP_PIN_GPIO81,
+        MFP_PIN_GPIO82,
+        MFP_PIN_GPIO83,
+        MFP_PIN_GPIO84,
+        MFP_PIN_GPIO85,
+        MFP_PIN_GPIO86,
+        MFP_PIN_GPIO87,
+        MFP_PIN_GPIO88,
+        MFP_PIN_GPIO89,
+        MFP_PIN_GPIO90,
+        MFP_PIN_GPIO91,
+        MFP_PIN_GPIO92,
+        MFP_PIN_GPIO93,
+        MFP_PIN_GPIO94,
+        MFP_PIN_GPIO95,
+        MFP_PIN_GPIO96,
+        MFP_PIN_GPIO97,
+        MFP_PIN_GPIO98,
+        MFP_PIN_GPIO99,
+        MFP_PIN_GPIO100,
+        MFP_PIN_GPIO101,
+        MFP_PIN_GPIO102,
+        MFP_PIN_GPIO103,
+        MFP_PIN_GPIO104,
+        MFP_PIN_GPIO105,
+        MFP_PIN_GPIO106,
+        MFP_PIN_GPIO107,
+        MFP_PIN_GPIO108,
+        MFP_PIN_GPIO109,
+        MFP_PIN_GPIO110,
+        MFP_PIN_GPIO111,
+        MFP_PIN_GPIO112,
+        MFP_PIN_GPIO113,
+        MFP_PIN_GPIO114,
+        MFP_PIN_GPIO115,
+        MFP_PIN_GPIO116,
+        MFP_PIN_GPIO117,
+        MFP_PIN_GPIO118,
+        MFP_PIN_GPIO119,
+        MFP_PIN_GPIO120,
+        MFP_PIN_GPIO121,
+        MFP_PIN_GPIO122,
+        MFP_PIN_GPIO123,
+        MFP_PIN_GPIO124,
+        MFP_PIN_GPIO125,
+        MFP_PIN_GPIO126,
+        MFP_PIN_GPIO127,
+        MFP_PIN_GPIO0_2,
+        MFP_PIN_GPIO1_2,
+        MFP_PIN_GPIO2_2,
+        MFP_PIN_GPIO3_2,
+        MFP_PIN_GPIO4_2,
+        MFP_PIN_GPIO5_2,
+        MFP_PIN_GPIO6_2,
+        MFP_PIN_GPIO7_2,
+        MFP_PIN_GPIO8_2,
+        MFP_PIN_GPIO9_2,
+        MFP_PIN_GPIO10_2,
+        MFP_PIN_GPIO11_2,
+        MFP_PIN_GPIO12_2,
+        MFP_PIN_GPIO13_2,
+        MFP_PIN_GPIO14_2,
+        MFP_PIN_GPIO15_2,
+        MFP_PIN_GPIO16_2,
+        MFP_PIN_GPIO17_2,
+
+        MFP_PIN_ULPI_STP,
+        MFP_PIN_ULPI_NXT,
+        MFP_PIN_ULPI_DIR,
+
+        MFP_PIN_nXCVREN,
+        MFP_PIN_DF_CLE_nOE,
+        MFP_PIN_DF_nADV1_ALE,
+        MFP_PIN_DF_SCLK_E,
+        MFP_PIN_DF_SCLK_S,
+        MFP_PIN_nBE0,
+        MFP_PIN_nBE1,
+        MFP_PIN_DF_nADV2_ALE,
+        MFP_PIN_DF_INT_RnB,
+        MFP_PIN_DF_nCS0,
+        MFP_PIN_DF_nCS1,
+        MFP_PIN_nLUA,
+        MFP_PIN_nLLA,
+        MFP_PIN_DF_nWE,
+        MFP_PIN_DF_ALE_nWE,
+        MFP_PIN_DF_nRE_nOE,
+        MFP_PIN_DF_ADDR0,
+        MFP_PIN_DF_ADDR1,
+        MFP_PIN_DF_ADDR2,
+        MFP_PIN_DF_ADDR3,
+        MFP_PIN_DF_IO0,
+        MFP_PIN_DF_IO1,
+        MFP_PIN_DF_IO2,
+        MFP_PIN_DF_IO3,
+        MFP_PIN_DF_IO4,
+        MFP_PIN_DF_IO5,
+        MFP_PIN_DF_IO6,
+        MFP_PIN_DF_IO7,
+        MFP_PIN_DF_IO8,
+        MFP_PIN_DF_IO9,
+        MFP_PIN_DF_IO10,
+        MFP_PIN_DF_IO11,
+        MFP_PIN_DF_IO12,
+        MFP_PIN_DF_IO13,
+        MFP_PIN_DF_IO14,
+        MFP_PIN_DF_IO15,
+
+        MFP_PIN_MAX,
+};
+
+/*
+ * Table that determines the low power modes outputs, with actual settings
+ * used in parentheses for don't-care values. Except for the float output,
+ * the configured driven and pulled levels match, so if there is a need for
+ * non-LPM pulled output, the same configuration could probably be used.
+ *
+ * Output value  sleep_oe_n  sleep_data  pullup_en  pulldown_en  pull_sel
+ *                 (bit 7)    (bit 8)    (bit 14d)   (bit 13d)
+ *
+ * Drive 0          0          0           0           X (1)      0
+ * Drive 1          0          1           X (1)       0          0
+ * Pull hi (1)      1          X(1)        1           0          0
+ * Pull lo (0)      1          X(0)        0           1          0
+ * Z (float)        1          X(0)        0           0          0
+ */
+#define MFP_LPM_DRIVE_LOW       0x8
+#define MFP_LPM_DRIVE_HIGH      0x6
+#define MFP_LPM_PULL_HIGH       0x7
+#define MFP_LPM_PULL_LOW        0x9
+#define MFP_LPM_FLOAT           0x1
+#define MFP_LPM_PULL_NEITHER    0x0
+
+/*
+ * The pullup and pulldown state of the MFP pin is by default determined by
+ * selected alternate function. In case some buggy devices need to override
+ * this default behavior,  pxa3xx_mfp_set_pull() can be invoked with one of
+ * the following definition as the parameter.
+ *
+ * Definition       pull_sel  pullup_en  pulldown_en
+ * MFP_PULL_HIGH        1         1        0
+ * MFP_PULL_LOW         1         0        1
+ * MFP_PULL_BOTH        1         1        1
+ * MFP_PULL_NONE        1         0        0
+ * MFP_PULL_DEFAULT     0         X        X
+ *
+ * NOTE: pxa3xx_mfp_set_pull() will modify the PULLUP_EN and PULLDOWN_EN
+ * bits,  which will cause potential conflicts with the low power mode
+ * setting, device drivers should take care of this
+ */
+#define MFP_PULL_BOTH           (0x7u)
+#define MFP_PULL_HIGH           (0x6u)
+#define MFP_PULL_LOW            (0x5u)
+#define MFP_PULL_NONE           (0x4u)
+#define MFP_PULL_DEFAULT        (0x0u)
+
+#define MFP_AF0                 (0)
+#define MFP_AF1                 (1)
+#define MFP_AF2                 (2)
+#define MFP_AF3                 (3)
+#define MFP_AF4                 (4)
+#define MFP_AF5                 (5)
+#define MFP_AF6                 (6)
+#define MFP_AF7                 (7)
+
+#define MFP_DS01X               (0)
+#define MFP_DS02X               (1)
+#define MFP_DS03X               (2)
+#define MFP_DS04X               (3)
+#define MFP_DS06X               (4)
+#define MFP_DS08X               (5)
+#define MFP_DS10X               (6)
+#define MFP_DS12X               (7)
+
+#define MFP_EDGE_BOTH           0x3
+#define MFP_EDGE_RISE           0x2
+#define MFP_EDGE_FALL           0x1
+#define MFP_EDGE_NONE           0x0
+
+#define MFPR_AF_MASK            0x0007
+#define MFPR_DRV_MASK           0x1c00
+#define MFPR_RDH_MASK           0x0200
+#define MFPR_LPM_MASK           0xe180
+#define MFPR_PULL_MASK          0xe000
+#define MFPR_EDGE_MASK          0x0070
+
+#define MFPR_ALT_OFFSET         0
+#define MFPR_ERE_OFFSET         4
+#define MFPR_EFE_OFFSET         5
+#define MFPR_EC_OFFSET          6
+#define MFPR_SON_OFFSET         7
+#define MFPR_SD_OFFSET          8
+#define MFPR_SS_OFFSET          9
+#define MFPR_DRV_OFFSET         10
+#define MFPR_PD_OFFSET          13
+#define MFPR_PU_OFFSET          14
+#define MFPR_PS_OFFSET          15
+
+#define MFPR(af, drv, rdh, lpm, edge) \
+        (((af) & 0x7) | (((drv) & 0x7) << 10) |\
+         (((rdh) & 0x1) << 9) |\
+         (((lpm) & 0x3) << 7) |\
+         (((lpm) & 0x4) << 12)|\
+         (((lpm) & 0x8) << 10)|\
+         ((!(edge)) << 6) |\
+         (((edge) & 0x1) << 5) |\
+         (((edge) & 0x2) << 3))
+
+/*
+ * a possible MFP configuration is represented by a 32-bit integer
+ * bit  0..15 - MFPR value (16-bit)
+ * bit 16..31 - mfp pin index (used to obtain the MFPR offset)
+ *
+ * to facilitate the definition, the following macros are provided
+ *
+ * MFPR_DEFAULT - default MFPR value, with
+ *                alternate function = 0,
+ *                drive strength = fast 1mA (MFP_DS01X)
+ *                low power mode = default
+ *                release dalay hold = false (RDH bit)
+ *                edge detection = none
+ *
+ * MFP_CFG      - default MFPR value with alternate function
+ * MFP_CFG_DRV  - default MFPR value with alternate function and
+ *                pin drive strength
+ * MFP_CFG_LPM  - default MFPR value with alternate function and
+ *                low power mode
+ * MFP_CFG_X    - default MFPR value with alternate function,
+ *                pin drive strength and low power mode
+ *
+ * use
+ *
+ * MFP_CFG_PIN  - to get the MFP pin index
+ * MFP_CFG_VAL  - to get the corresponding MFPR value
+ */
+
+typedef uint32_t mfp_cfg_t;
+
+#define MFP_CFG_PIN(mfp_cfg)    (((mfp_cfg) >> 16) & 0xffff)
+#define MFP_CFG_VAL(mfp_cfg)    ((mfp_cfg) & 0xffff)
+
+#define MFPR_DEFAULT    (0x0000)
+
+#define MFP_CFG(pin, af)                \
+        ((MFP_PIN_##pin << 16) | MFPR_DEFAULT | (MFP_##af))
+
+#define MFP_CFG_DRV(pin, af, drv)       \
+        ((MFP_PIN_##pin << 16) | MFPR_DEFAULT |\
+         ((MFP_##drv) << 10) | (MFP_##af))
+
+#define MFP_CFG_LPM(pin, af, lpm)       \
+        ((MFP_PIN_##pin << 16) | MFPR_DEFAULT | (MFP_##af) |\
+         (((MFP_LPM_##lpm) & 0x3) << 7)  |\
+         (((MFP_LPM_##lpm) & 0x4) << 12) |\
+         (((MFP_LPM_##lpm) & 0x8) << 10))
+
+#define MFP_CFG_X(pin, af, drv, lpm)    \
+        ((MFP_PIN_##pin << 16) | MFPR_DEFAULT |\
+         ((MFP_##drv) << 10) | (MFP_##af) |\
+         (((MFP_LPM_##lpm) & 0x3) << 7)  |\
+         (((MFP_LPM_##lpm) & 0x4) << 12) |\
+         (((MFP_LPM_##lpm) & 0x8) << 10))
+
+/* common MFP configurations - processor specific ones defined
+ * in mfp-pxa3xx.h
+ */
+#define GPIO0_GPIO              MFP_CFG(GPIO0, AF0)
+#define GPIO1_GPIO              MFP_CFG(GPIO1, AF0)
+#define GPIO2_GPIO              MFP_CFG(GPIO2, AF0)
+#define GPIO3_GPIO              MFP_CFG(GPIO3, AF0)
+#define GPIO4_GPIO              MFP_CFG(GPIO4, AF0)
+#define GPIO5_GPIO              MFP_CFG(GPIO5, AF0)
+#define GPIO6_GPIO              MFP_CFG(GPIO6, AF0)
+#define GPIO7_GPIO              MFP_CFG(GPIO7, AF0)
+#define GPIO8_GPIO              MFP_CFG(GPIO8, AF0)
+#define GPIO9_GPIO              MFP_CFG(GPIO9, AF0)
+#define GPIO10_GPIO             MFP_CFG(GPIO10, AF0)
+#define GPIO11_GPIO             MFP_CFG(GPIO11, AF0)
+#define GPIO12_GPIO             MFP_CFG(GPIO12, AF0)
+#define GPIO13_GPIO             MFP_CFG(GPIO13, AF0)
+#define GPIO14_GPIO             MFP_CFG(GPIO14, AF0)
+#define GPIO15_GPIO             MFP_CFG(GPIO15, AF0)
+#define GPIO16_GPIO             MFP_CFG(GPIO16, AF0)
+#define GPIO17_GPIO             MFP_CFG(GPIO17, AF0)
+#define GPIO18_GPIO             MFP_CFG(GPIO18, AF0)
+#define GPIO19_GPIO             MFP_CFG(GPIO19, AF0)
+#define GPIO20_GPIO             MFP_CFG(GPIO20, AF0)
+#define GPIO21_GPIO             MFP_CFG(GPIO21, AF0)
+#define GPIO22_GPIO             MFP_CFG(GPIO22, AF0)
+#define GPIO23_GPIO             MFP_CFG(GPIO23, AF0)
+#define GPIO24_GPIO             MFP_CFG(GPIO24, AF0)
+#define GPIO25_GPIO             MFP_CFG(GPIO25, AF0)
+#define GPIO26_GPIO             MFP_CFG(GPIO26, AF0)
+#define GPIO27_GPIO             MFP_CFG(GPIO27, AF0)
+#define GPIO28_GPIO             MFP_CFG(GPIO28, AF0)
+#define GPIO29_GPIO             MFP_CFG(GPIO29, AF0)
+#define GPIO30_GPIO             MFP_CFG(GPIO30, AF0)
+#define GPIO31_GPIO             MFP_CFG(GPIO31, AF0)
+#define GPIO32_GPIO             MFP_CFG(GPIO32, AF0)
+#define GPIO33_GPIO             MFP_CFG(GPIO33, AF0)
+#define GPIO34_GPIO             MFP_CFG(GPIO34, AF0)
+#define GPIO35_GPIO             MFP_CFG(GPIO35, AF0)
+#define GPIO36_GPIO             MFP_CFG(GPIO36, AF0)
+#define GPIO37_GPIO             MFP_CFG(GPIO37, AF0)
+#define GPIO38_GPIO             MFP_CFG(GPIO38, AF0)
+#define GPIO39_GPIO             MFP_CFG(GPIO39, AF0)
+#define GPIO40_GPIO             MFP_CFG(GPIO40, AF0)
+#define GPIO41_GPIO             MFP_CFG(GPIO41, AF0)
+#define GPIO42_GPIO             MFP_CFG(GPIO42, AF0)
+#define GPIO43_GPIO             MFP_CFG(GPIO43, AF0)
+#define GPIO44_GPIO             MFP_CFG(GPIO44, AF0)
+#define GPIO45_GPIO             MFP_CFG(GPIO45, AF0)
+
+#define GPIO47_GPIO             MFP_CFG(GPIO47, AF0)
+#define GPIO48_GPIO             MFP_CFG(GPIO48, AF0)
+
+#define GPIO53_GPIO             MFP_CFG(GPIO53, AF0)
+#define GPIO54_GPIO             MFP_CFG(GPIO54, AF0)
+#define GPIO55_GPIO             MFP_CFG(GPIO55, AF0)
+
+#define GPIO57_GPIO             MFP_CFG(GPIO57, AF0)
+
+#define GPIO63_GPIO             MFP_CFG(GPIO63, AF0)
+#define GPIO64_GPIO             MFP_CFG(GPIO64, AF0)
+#define GPIO65_GPIO             MFP_CFG(GPIO65, AF0)
+#define GPIO66_GPIO             MFP_CFG(GPIO66, AF0)
+#define GPIO67_GPIO             MFP_CFG(GPIO67, AF0)
+#define GPIO68_GPIO             MFP_CFG(GPIO68, AF0)
+#define GPIO69_GPIO             MFP_CFG(GPIO69, AF0)
+#define GPIO70_GPIO             MFP_CFG(GPIO70, AF0)
+#define GPIO71_GPIO             MFP_CFG(GPIO71, AF0)
+#define GPIO72_GPIO             MFP_CFG(GPIO72, AF0)
+#define GPIO73_GPIO             MFP_CFG(GPIO73, AF0)
+#define GPIO74_GPIO             MFP_CFG(GPIO74, AF0)
+#define GPIO75_GPIO             MFP_CFG(GPIO75, AF0)
+#define GPIO76_GPIO             MFP_CFG(GPIO76, AF0)
+#define GPIO77_GPIO             MFP_CFG(GPIO77, AF0)
+#define GPIO78_GPIO             MFP_CFG(GPIO78, AF0)
+#define GPIO79_GPIO             MFP_CFG(GPIO79, AF0)
+#define GPIO80_GPIO             MFP_CFG(GPIO80, AF0)
+#define GPIO81_GPIO             MFP_CFG(GPIO81, AF0)
+#define GPIO82_GPIO             MFP_CFG(GPIO82, AF0)
+#define GPIO83_GPIO             MFP_CFG(GPIO83, AF0)
+#define GPIO84_GPIO             MFP_CFG(GPIO84, AF0)
+#define GPIO85_GPIO             MFP_CFG(GPIO85, AF0)
+#define GPIO86_GPIO             MFP_CFG(GPIO86, AF0)
+#define GPIO87_GPIO             MFP_CFG(GPIO87, AF0)
+#define GPIO88_GPIO             MFP_CFG(GPIO88, AF0)
+#define GPIO89_GPIO             MFP_CFG(GPIO89, AF0)
+#define GPIO90_GPIO             MFP_CFG(GPIO90, AF0)
+#define GPIO91_GPIO             MFP_CFG(GPIO91, AF0)
+#define GPIO92_GPIO             MFP_CFG(GPIO92, AF0)
+#define GPIO93_GPIO             MFP_CFG(GPIO93, AF0)
+#define GPIO94_GPIO             MFP_CFG(GPIO94, AF0)
+#define GPIO95_GPIO             MFP_CFG(GPIO95, AF0)
+#define GPIO96_GPIO             MFP_CFG(GPIO96, AF0)
+#define GPIO97_GPIO             MFP_CFG(GPIO97, AF0)
+#define GPIO98_GPIO             MFP_CFG(GPIO98, AF0)
+#define GPIO99_GPIO             MFP_CFG(GPIO99, AF0)
+#define GPIO100_GPIO            MFP_CFG(GPIO100, AF0)
+#define GPIO101_GPIO            MFP_CFG(GPIO101, AF0)
+#define GPIO102_GPIO            MFP_CFG(GPIO102, AF0)
+#define GPIO103_GPIO            MFP_CFG(GPIO103, AF0)
+#define GPIO104_GPIO            MFP_CFG(GPIO104, AF0)
+#define GPIO105_GPIO            MFP_CFG(GPIO105, AF0)
+#define GPIO106_GPIO            MFP_CFG(GPIO106, AF0)
+#define GPIO107_GPIO            MFP_CFG(GPIO107, AF0)
+#define GPIO108_GPIO            MFP_CFG(GPIO108, AF0)
+#define GPIO109_GPIO            MFP_CFG(GPIO109, AF0)
+#define GPIO110_GPIO            MFP_CFG(GPIO110, AF0)
+#define GPIO111_GPIO            MFP_CFG(GPIO111, AF0)
+#define GPIO112_GPIO            MFP_CFG(GPIO112, AF0)
+#define GPIO113_GPIO            MFP_CFG(GPIO113, AF0)
+#define GPIO114_GPIO            MFP_CFG(GPIO114, AF0)
+#define GPIO115_GPIO            MFP_CFG(GPIO115, AF0)
+#define GPIO116_GPIO            MFP_CFG(GPIO116, AF0)
+#define GPIO117_GPIO            MFP_CFG(GPIO117, AF0)
+#define GPIO118_GPIO            MFP_CFG(GPIO118, AF0)
+#define GPIO119_GPIO            MFP_CFG(GPIO119, AF0)
+#define GPIO120_GPIO            MFP_CFG(GPIO120, AF0)
+#define GPIO121_GPIO            MFP_CFG(GPIO121, AF0)
+#define GPIO122_GPIO            MFP_CFG(GPIO122, AF0)
+#define GPIO123_GPIO            MFP_CFG(GPIO123, AF0)
+#define GPIO124_GPIO            MFP_CFG(GPIO124, AF0)
+#define GPIO125_GPIO            MFP_CFG(GPIO125, AF0)
+#define GPIO126_GPIO            MFP_CFG(GPIO126, AF0)
+#define GPIO127_GPIO            MFP_CFG(GPIO127, AF0)
+
+#define GPIO0_2_GPIO            MFP_CFG(GPIO0_2, AF0)
+#define GPIO1_2_GPIO            MFP_CFG(GPIO1_2, AF0)
+#define GPIO2_2_GPIO            MFP_CFG(GPIO2_2, AF0)
+#define GPIO3_2_GPIO            MFP_CFG(GPIO3_2, AF0)
+#define GPIO4_2_GPIO            MFP_CFG(GPIO4_2, AF0)
+#define GPIO5_2_GPIO            MFP_CFG(GPIO5_2, AF0)
+#define GPIO6_2_GPIO            MFP_CFG(GPIO6_2, AF0)
+
+/*
+ * each MFP pin will have a MFPR register, since the offset of the
+ * register varies between processors, the processor specific code
+ * should initialize the pin offsets by pxa3xx_mfp_init_addr()
+ *
+ * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map"
+ * structure, which represents a range of MFP pins from "start" to
+ * "end", with the offset begining at "offset", to define a single
+ * pin, let "end" = -1
+ *
+ * use
+ *
+ * MFP_ADDR_X() to define a range of pins
+ * MFP_ADDR()   to define a single pin
+ * MFP_ADDR_END to signal the end of pin offset definitions
+ */
+struct pxa3xx_mfp_addr_map {
+        unsigned int    start;
+        unsigned int    end;
+        unsigned long   offset;
+};
+
+#define MFP_ADDR_X(start, end, offset) \
+        { MFP_PIN_##start, MFP_PIN_##end, offset }
+
+#define MFP_ADDR(pin, offset) \
+        { MFP_PIN_##pin, -1, offset }
+
+#define MFP_ADDR_END    { MFP_PIN_INVALID, 0 }
+
+struct pxa3xx_mfp_pin {
+        unsigned long   mfpr_off;       /* MFPRxx register offset */
+        unsigned long   mfpr_val;       /* MFPRxx register value */
+};
+
+/*
+ * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access
+ * to the MFPR register
+ */
+unsigned long pxa3xx_mfp_read(int mfp);
+void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val);
+
+/*
+ * pxa3xx_mfp_set_afds - set MFP alternate function and drive strength
+ * pxa3xx_mfp_set_rdh  - set MFP release delay hold on/off
+ * pxa3xx_mfp_set_lpm  - set MFP low power mode state
+ * pxa3xx_mfp_set_edge - set MFP edge detection in low power mode
+ *
+ * use these functions to override/change the default configuration
+ * done by pxa3xx_mfp_set_config(s)
+ */
+void pxa3xx_mfp_set_afds(int mfp, int af, int ds);
+void pxa3xx_mfp_set_rdh(int mfp, int rdh);
+void pxa3xx_mfp_set_lpm(int mfp, int lpm);
+void pxa3xx_mfp_set_edge(int mfp, int edge);
+
+/*
+ * pxa3xx_mfp_config - configure the MFPR registers
+ *
+ * used by board specific initialization code
+ */
+void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num);
+
+/*
+ * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin
+ * index and MFPR register offset
+ *
+ * used by processor specific code
+ */
+void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *);
+void __init pxa3xx_init_mfp(void);
+
+#endif /* __ASM_ARCH_MFP_H */
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index e68b593d69da..67f53e07db86 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1177,7 +1177,7 @@
 
 #define GPIO_bit(x)     (1 << ((x) & 0x1f))
 
-#ifdef CONFIG_PXA27x
+#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 
 /* Interrupt Controller */
 
diff --git a/include/asm-arm/arch-pxa/pxa3xx-regs.h b/include/asm-arm/arch-pxa/pxa3xx-regs.h
new file mode 100644
index 000000000000..3900a0ca0bc0
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa3xx-regs.h
@@ -0,0 +1,75 @@
+/*
+ * linux/include/asm-arm/arch-pxa/pxa3xx-regs.h
+ *
+ * PXA3xx specific register definitions
+ *
+ * Copyright (C) 2007 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_PXA3XX_REGS_H
+#define __ASM_ARCH_PXA3XX_REGS_H
+
+/*
+ * Application Subsystem Clock
+ */
+#define ACCR            __REG(0x41340000)       /* Application Subsystem Clock Configuration Register */
+#define ACSR            __REG(0x41340004)       /* Application Subsystem Clock Status Register */
+#define AICSR           __REG(0x41340008)       /* Application Subsystem Interrupt Control/Status Register */
+#define CKENA           __REG(0x4134000C)       /* A Clock Enable Register */
+#define CKENB           __REG(0x41340010)       /* B Clock Enable Register */
+#define AC97_DIV        __REG(0x41340014)       /* AC97 clock divisor value register */
+
+/*
+ * Clock Enable Bit
+ */
+#define CKEN_LCD        1       /* < LCD Clock Enable */
+#define CKEN_USBH       2       /* < USB host clock enable */
+#define CKEN_CAMERA     3       /* < Camera interface clock enable */
+#define CKEN_NAND       4       /* < NAND Flash Controller Clock Enable */
+#define CKEN_USB2       6       /* < USB 2.0 client clock enable. */
+#define CKEN_DMC        8       /* < Dynamic Memory Controller clock enable */
+#define CKEN_SMC        9       /* < Static Memory Controller clock enable */
+#define CKEN_ISC        10      /* < Internal SRAM Controller clock enable */
+#define CKEN_BOOT       11      /* < Boot rom clock enable */
+#define CKEN_MMC1       12      /* < MMC1 Clock enable */
+#define CKEN_MMC2       13      /* < MMC2 clock enable */
+#define CKEN_KEYPAD     14      /* < Keypand Controller Clock Enable */
+#define CKEN_CIR        15      /* < Consumer IR Clock Enable */
+#define CKEN_USIM0      17      /* < USIM[0] Clock Enable */
+#define CKEN_USIM1      18      /* < USIM[1] Clock Enable */
+#define CKEN_TPM        19      /* < TPM clock enable */
+#define CKEN_UDC        20      /* < UDC clock enable */
+#define CKEN_BTUART     21      /* < BTUART clock enable */
+#define CKEN_FFUART     22      /* < FFUART clock enable */
+#define CKEN_STUART     23      /* < STUART clock enable */
+#define CKEN_AC97       24      /* < AC97 clock enable */
+#define CKEN_TOUCH      25      /* < Touch screen Interface Clock Enable */
+#define CKEN_SSP1       26      /* < SSP1 clock enable */
+#define CKEN_SSP2       27      /* < SSP2 clock enable */
+#define CKEN_SSP3       28      /* < SSP3 clock enable */
+#define CKEN_SSP4       29      /* < SSP4 clock enable */
+#define CKEN_MSL0       30      /* < MSL0 clock enable */
+#define CKEN_PWM0       32      /* < PWM[0] clock enable */
+#define CKEN_PWM1       33      /* < PWM[1] clock enable */
+#define CKEN_I2C        36      /* < I2C clock enable */
+#define CKEN_INTC       38      /* < Interrupt controller clock enable */
+#define CKEN_GPIO       39      /* < GPIO clock enable */
+#define CKEN_1WIRE      40      /* < 1-wire clock enable */
+#define CKEN_HSIO2      41      /* < HSIO2 clock enable */
+#define CKEN_MINI_IM    48      /* < Mini-IM */
+#define CKEN_MINI_LCD   49      /* < Mini LCD */
+
+#if defined(CONFIG_CPU_PXA310)
+#define CKEN_MMC3       5       /* < MMC3 Clock Enable */
+#define CKEN_MVED       43      /* < MVED clock enable */
+#endif
+
+/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
+#define PXA300_CKEN_GRAPHICS    42      /* Graphics controller clock enable */
+#define PXA320_CKEN_GRAPHICS    7       /* Graphics controller clock enable */
+
+#endif /* __ASM_ARCH_PXA3XX_REGS_H */
diff --git a/include/asm-arm/arch-pxa/timex.h b/include/asm-arm/arch-pxa/timex.h
index 2473bb51d0a6..8d882f0b6a16 100644
--- a/include/asm-arm/arch-pxa/timex.h
+++ b/include/asm-arm/arch-pxa/timex.h
@@ -21,4 +21,6 @@
 #else
 #define CLOCK_TICK_RATE 3250000
 #endif
+#else
+#define CLOCK_TICK_RATE 3250000
 #endif
diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h
new file mode 100644
index 000000000000..f58b59162b82
--- /dev/null
+++ b/include/asm-arm/arch-pxa/zylonite.h
@@ -0,0 +1,35 @@
+#ifndef __ASM_ARCH_ZYLONITE_H
+#define __ASM_ARCH_ZYLONITE_H
+
+#define ZYLONITE_ETH_PHYS       0x14000000
+
+/* the following variables are processor specific and initialized
+ * by the corresponding zylonite_pxa3xx_init()
+ */
+extern int gpio_backlight;
+extern int gpio_eth_irq;
+
+extern int lcd_id;
+extern int lcd_orientation;
+
+#ifdef CONFIG_CPU_PXA300
+extern void zylonite_pxa300_init(void);
+#else
+static inline void zylonite_pxa300_init(void)
+{
+        if (cpu_is_pxa300() || cpu_is_pxa310())
+                panic("%s: PXA300/PXA310 not supported\n", __FUNCTION__);
+}
+#endif
+
+#ifdef CONFIG_CPU_PXA320
+extern void zylonite_pxa320_init(void);
+#else
+static inline void zylonite_pxa320_init(void)
+{
+        if (cpu_is_pxa320())
+                panic("%s: PXA320 not supported\n", __FUNCTION__);
+}
+#endif
+
+#endif /* __ASM_ARCH_ZYLONITE_H */
diff --git a/include/asm-arm/hardware/it8152.h b/include/asm-arm/hardware/it8152.h
new file mode 100644
index 000000000000..aaebb61aca48
--- /dev/null
+++ b/include/asm-arm/hardware/it8152.h
@@ -0,0 +1,99 @@
+/*
+ * linux/include/arm/hardware/it8152.h
+ *
+ * Copyright Compulab Ltd., 2006,2007
+ * Mike Rapoport <mike@compulab.co.il>
+ *
+ * ITE 8152 companion chip register definitions
+ */
+
+#ifndef __ASM_HARDWARE_IT8152_H
+#define __ASM_HARDWARE_IT8152_H
+extern unsigned long it8152_base_address;
+
+#define IT8152_IO_BASE                  (it8152_base_address + 0x03e00000)
+#define IT8152_CFGREG_BASE              (it8152_base_address + 0x03f00000)
+
+#define __REG_IT8152(x)                 (it8152_base_address + (x))
+
+#define IT8152_PCI_CFG_ADDR             __REG_IT8152(0x3f00800)
+#define IT8152_PCI_CFG_DATA             __REG_IT8152(0x3f00804)
+
+#define IT8152_INTC_LDCNIRR             __REG_IT8152(0x3f00300)
+#define IT8152_INTC_LDPNIRR             __REG_IT8152(0x3f00304)
+#define IT8152_INTC_LDCNIMR             __REG_IT8152(0x3f00308)
+#define IT8152_INTC_LDPNIMR             __REG_IT8152(0x3f0030C)
+#define IT8152_INTC_LDNITR              __REG_IT8152(0x3f00310)
+#define IT8152_INTC_LDNIAR              __REG_IT8152(0x3f00314)
+#define IT8152_INTC_LPCNIRR             __REG_IT8152(0x3f00320)
+#define IT8152_INTC_LPPNIRR             __REG_IT8152(0x3f00324)
+#define IT8152_INTC_LPCNIMR             __REG_IT8152(0x3f00328)
+#define IT8152_INTC_LPPNIMR             __REG_IT8152(0x3f0032C)
+#define IT8152_INTC_LPNITR              __REG_IT8152(0x3f00330)
+#define IT8152_INTC_LPNIAR              __REG_IT8152(0x3f00334)
+#define IT8152_INTC_PDCNIRR             __REG_IT8152(0x3f00340)
+#define IT8152_INTC_PDPNIRR             __REG_IT8152(0x3f00344)
+#define IT8152_INTC_PDCNIMR             __REG_IT8152(0x3f00348)
+#define IT8152_INTC_PDPNIMR             __REG_IT8152(0x3f0034C)
+#define IT8152_INTC_PDNITR              __REG_IT8152(0x3f00350)
+#define IT8152_INTC_PDNIAR              __REG_IT8152(0x3f00354)
+#define IT8152_INTC_INTC_TYPER          __REG_IT8152(0x3f003FC)
+
+#define IT8152_GPIO_GPDR                __REG_IT8152(0x3f00500)
+
+/*
+  Interrup contoler per register summary:
+  ---------------------------------------
+  LCDNIRR:
+  IT8152_LD_IRQ(8) PCICLK stop
+  IT8152_LD_IRQ(7) MCLK ready
+  IT8152_LD_IRQ(6) s/w
+  IT8152_LD_IRQ(5) UART
+  IT8152_LD_IRQ(4) GPIO
+  IT8152_LD_IRQ(3) TIMER 4
+  IT8152_LD_IRQ(2) TIMER 3
+  IT8152_LD_IRQ(1) TIMER 2
+  IT8152_LD_IRQ(0) TIMER 1
+
+  LPCNIRR:
+  IT8152_LP_IRQ(x) serial IRQ x
+
+  PCIDNIRR:
+  IT8152_PD_IRQ(14) PCISERR
+  IT8152_PD_IRQ(13) CPU/PCI bridge target abort (h2pTADR)
+  IT8152_PD_IRQ(12) CPU/PCI bridge master abort (h2pMADR)
+  IT8152_PD_IRQ(11) PCI INTD
+  IT8152_PD_IRQ(10) PCI INTC
+  IT8152_PD_IRQ(9)  PCI INTB
+  IT8152_PD_IRQ(8)  PCI INTA
+  IT8152_PD_IRQ(7)  serial INTD
+  IT8152_PD_IRQ(6)  serial INTC
+  IT8152_PD_IRQ(5)  serial INTB
+  IT8152_PD_IRQ(4)  serial INTA
+  IT8152_PD_IRQ(3)  serial IRQ IOCHK (IOCHKR)
+  IT8152_PD_IRQ(2)  chaining DMA (CDMAR)
+  IT8152_PD_IRQ(1)  USB (USBR)
+  IT8152_PD_IRQ(0)  Audio controller (ACR)
+ */
+/* frequently used interrupts */
+#define IT8152_PCISERR          IT8152_PD_IRQ(14)
+#define IT8152_H2PTADR          IT8152_PD_IRQ(13)
+#define IT8152_H2PMAR           IT8152_PD_IRQ(12)
+#define IT8152_PCI_INTD         IT8152_PD_IRQ(11)
+#define IT8152_PCI_INTC         IT8152_PD_IRQ(10)
+#define IT8152_PCI_INTB         IT8152_PD_IRQ(9)
+#define IT8152_PCI_INTA         IT8152_PD_IRQ(8)
+#define IT8152_CDMA_INT         IT8152_PD_IRQ(2)
+#define IT8152_USB_INT          IT8152_PD_IRQ(1)
+#define IT8152_AUDIO_INT        IT8152_PD_IRQ(0)
+
+struct pci_dev;
+struct pci_sys_data;
+
+extern void it8152_irq_demux(unsigned int irq, struct irq_desc *desc);
+extern void it8152_init_irq(void);
+extern int it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
+extern int it8152_pci_setup(int nr, struct pci_sys_data *sys);
+extern struct pci_bus *it8152_pci_scan_bus(int nr, struct pci_sys_data *sys);
+
+#endif /* __ASM_HARDWARE_IT8152_H */
diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h
index ed3f898191f4..75feb1574a69 100644
--- a/include/asm-arm/pci.h
+++ b/include/asm-arm/pci.h
@@ -8,10 +8,17 @@
 
 #define pcibios_scan_all_fns(a, b)      0
 
+#ifdef CONFIG_PCI_HOST_ITE8152
+/* ITE bridge requires setting latency timer to avoid early bus access
+   termination by PIC bus mater devices
+*/
+extern void pcibios_set_master(struct pci_dev *dev);
+#else
 static inline void pcibios_set_master(struct pci_dev *dev)
 {
         /* No special bus mastering setup handling */
 }
+#endif
 
 static inline void pcibios_penalize_isa_irq(int irq, int active)
 {
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 3948708c42ca..2bcb02d555e8 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1631,6 +1631,7 @@
 #define PCI_DEVICE_ID_ITE_8211          0x8211
 #define PCI_DEVICE_ID_ITE_8212          0x8212
 #define PCI_DEVICE_ID_ITE_8213          0x8213
+#define PCI_DEVICE_ID_ITE_8152          0x8152
 #define PCI_DEVICE_ID_ITE_8872          0x8872
 #define PCI_DEVICE_ID_ITE_IT8330G_0     0xe886