diff options
author | Cyrill Gorcunov <gorcunov@gmail.com> | 2008-08-16 15:21:50 -0400 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2008-08-17 08:41:47 -0400 |
commit | 6764014bc8bb4849f6a4f336477e873ad5861ed2 (patch) | |
tree | 309b739269798011b2ac1602219f41327e9061d3 | |
parent | 638c0411922540deaf8797cacf73513b17618405 (diff) |
x86: apic - unify clear_local_APIC
- Remove redundant masking of APIC_LVTTHMR register in apic_32.c
- Add masking of APIC_LVTTHMR register to apic_64.c. We use a bit
complicated #ifdef here: CONFIG_X86_MCE_P4THERMAL is 32bit specific
and X86_MCE_INTEL is 64bit specific so the appropriate config variable
will be set by Kconfig.
- the APIC_ESR register clearing in apic_64.c now uses not straightforward
way but this is allowed tradeoff.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
-rw-r--r-- | arch/x86/kernel/apic_32.c | 6 | ||||
-rw-r--r-- | arch/x86/kernel/apic_64.c | 17 |
2 files changed, 16 insertions, 7 deletions
diff --git a/arch/x86/kernel/apic_32.c b/arch/x86/kernel/apic_32.c index 16d9721788c1..3131603a4d6a 100644 --- a/arch/x86/kernel/apic_32.c +++ b/arch/x86/kernel/apic_32.c | |||
@@ -754,7 +754,7 @@ void clear_local_APIC(void) | |||
754 | } | 754 | } |
755 | 755 | ||
756 | /* lets not touch this if we didn't frob it */ | 756 | /* lets not touch this if we didn't frob it */ |
757 | #ifdef CONFIG_X86_MCE_P4THERMAL | 757 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) |
758 | if (maxlvt >= 5) { | 758 | if (maxlvt >= 5) { |
759 | v = apic_read(APIC_LVTTHMR); | 759 | v = apic_read(APIC_LVTTHMR); |
760 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | 760 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); |
@@ -771,10 +771,6 @@ void clear_local_APIC(void) | |||
771 | if (maxlvt >= 4) | 771 | if (maxlvt >= 4) |
772 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | 772 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); |
773 | 773 | ||
774 | #ifdef CONFIG_X86_MCE_P4THERMAL | ||
775 | if (maxlvt >= 5) | ||
776 | apic_write(APIC_LVTTHMR, APIC_LVT_MASKED); | ||
777 | #endif | ||
778 | /* Integrated APIC (!82489DX) ? */ | 774 | /* Integrated APIC (!82489DX) ? */ |
779 | if (lapic_is_integrated()) { | 775 | if (lapic_is_integrated()) { |
780 | if (maxlvt > 3) | 776 | if (maxlvt > 3) |
diff --git a/arch/x86/kernel/apic_64.c b/arch/x86/kernel/apic_64.c index 99d18b8976a5..d834b7583624 100644 --- a/arch/x86/kernel/apic_64.c +++ b/arch/x86/kernel/apic_64.c | |||
@@ -630,6 +630,13 @@ void clear_local_APIC(void) | |||
630 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | 630 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); |
631 | } | 631 | } |
632 | 632 | ||
633 | /* lets not touch this if we didn't frob it */ | ||
634 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) | ||
635 | if (maxlvt >= 5) { | ||
636 | v = apic_read(APIC_LVTTHMR); | ||
637 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | ||
638 | } | ||
639 | #endif | ||
633 | /* | 640 | /* |
634 | * Clean APIC state for other OSs: | 641 | * Clean APIC state for other OSs: |
635 | */ | 642 | */ |
@@ -640,8 +647,14 @@ void clear_local_APIC(void) | |||
640 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | 647 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); |
641 | if (maxlvt >= 4) | 648 | if (maxlvt >= 4) |
642 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | 649 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); |
643 | apic_write(APIC_ESR, 0); | 650 | |
644 | apic_read(APIC_ESR); | 651 | /* Integrated APIC (!82489DX) ? */ |
652 | if (lapic_is_integrated()) { | ||
653 | if (maxlvt > 3) | ||
654 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | ||
655 | apic_write(APIC_ESR, 0); | ||
656 | apic_read(APIC_ESR); | ||
657 | } | ||
645 | } | 658 | } |
646 | 659 | ||
647 | /** | 660 | /** |