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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-12-17 15:05:39 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-12-17 15:05:39 -0500
commitc95a44329e816d2f9da21b27e74615d5ee0d2333 (patch)
tree29eb5d2ec3b0bf2951886adff12b5f9c787815bd
parentc613bbba6f39c8804f1f26e96fb68a117cc9e282 (diff)
parent47fee6fedd3ea08e9b0f1172bc74e59ee7a6b3d9 (diff)
Merge branch 'rmk-devel-mxc-pu-v2' of git://pasiphae.extern.pengutronix.de/git/imx/linux-2.6 into devel
Diffstat
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/configs/mx31moboard_defconfig790
-rw-r--r--arch/arm/configs/mx31pdk_defconfig773
-rw-r--r--arch/arm/mach-mx1/Kconfig14
-rw-r--r--arch/arm/mach-mx1/Makefile10
-rw-r--r--arch/arm/mach-mx1/Makefile.boot4
-rw-r--r--arch/arm/mach-mx1/clock.c656
-rw-r--r--arch/arm/mach-mx1/crm_regs.h55
-rw-r--r--arch/arm/mach-mx1/devices.c260
-rw-r--r--arch/arm/mach-mx1/devices.h7
-rw-r--r--arch/arm/mach-mx1/generic.c43
-rw-r--r--arch/arm/mach-mx1/mx1ads.c148
-rw-r--r--arch/arm/mach-mx2/devices.c19
-rw-r--r--arch/arm/mach-mx2/devices.h1
-rw-r--r--arch/arm/mach-mx2/mx27ads.c61
-rw-r--r--arch/arm/mach-mx2/pcm038.c80
-rw-r--r--arch/arm/mach-mx3/Kconfig14
-rw-r--r--arch/arm/mach-mx3/Makefile2
-rw-r--r--arch/arm/mach-mx3/devices.c19
-rw-r--r--arch/arm/mach-mx3/devices.h1
-rw-r--r--arch/arm/mach-mx3/iomux.c9
-rw-r--r--arch/arm/mach-mx3/mx31moboard.c141
-rw-r--r--arch/arm/mach-mx3/mx31pdk.c115
-rw-r--r--arch/arm/mach-mx3/pcm037.c67
-rw-r--r--arch/arm/plat-mxc/Kconfig6
-rw-r--r--arch/arm/plat-mxc/Makefile1
-rw-r--r--arch/arm/plat-mxc/dma-mx1-mx2.c7
-rw-r--r--arch/arm/plat-mxc/gpio.c6
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx27ads.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31pdk.h19
-rw-r--r--arch/arm/plat-mxc/include/mach/debug-macro.S3
-rw-r--r--arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h10
-rw-r--r--arch/arm/plat-mxc/include/mach/hardware.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h68
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx3.h17
-rw-r--r--arch/arm/plat-mxc/include/mach/irqs.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/mtd-xip.h34
-rw-r--r--arch/arm/plat-mxc/include/mach/mx1.h197
-rw-r--r--arch/arm/plat-mxc/include/mach/mx27.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_timer.h4
-rw-r--r--arch/arm/plat-mxc/iomux-mx1-mx2.c37
-rw-r--r--arch/arm/plat-mxc/irq.c30
-rw-r--r--drivers/mmc/host/imxmmc.c459
-rw-r--r--drivers/mmc/host/imxmmc.h37
-rw-r--r--drivers/mtd/nand/Kconfig2
-rw-r--r--drivers/serial/imx.c6
46 files changed, 3887 insertions, 363 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 260864f3f010..c8548a187413 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -139,6 +139,7 @@ endif
139 plat-$(CONFIG_ARCH_MXC) := mxc 139 plat-$(CONFIG_ARCH_MXC) := mxc
140 machine-$(CONFIG_ARCH_MX2) := mx2 140 machine-$(CONFIG_ARCH_MX2) := mx2
141 machine-$(CONFIG_ARCH_MX3) := mx3 141 machine-$(CONFIG_ARCH_MX3) := mx3
142 machine-$(CONFIG_ARCH_MX1) := mx1
142 machine-$(CONFIG_ARCH_ORION5X) := orion5x 143 machine-$(CONFIG_ARCH_ORION5X) := orion5x
143 plat-$(CONFIG_PLAT_ORION) := orion 144 plat-$(CONFIG_PLAT_ORION) := orion
144 machine-$(CONFIG_ARCH_MSM) := msm 145 machine-$(CONFIG_ARCH_MSM) := msm
diff --git a/arch/arm/configs/mx31moboard_defconfig b/arch/arm/configs/mx31moboard_defconfig
new file mode 100644
index 000000000000..e90f86d6deef
--- /dev/null
+++ b/arch/arm/configs/mx31moboard_defconfig
@@ -0,0 +1,790 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.27-rc5
4# Fri Oct 24 11:41:22 2008
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_HAVE_LATENCYTOP_SUPPORT=y
16CONFIG_LOCKDEP_SUPPORT=y
17CONFIG_TRACE_IRQFLAGS_SUPPORT=y
18CONFIG_HARDIRQS_SW_RESEND=y
19CONFIG_GENERIC_IRQ_PROBE=y
20CONFIG_RWSEM_GENERIC_SPINLOCK=y
21# CONFIG_ARCH_HAS_ILOG2_U32 is not set
22# CONFIG_ARCH_HAS_ILOG2_U64 is not set
23CONFIG_GENERIC_HWEIGHT=y
24CONFIG_GENERIC_CALIBRATE_DELAY=y
25CONFIG_ARCH_SUPPORTS_AOUT=y
26CONFIG_ZONE_DMA=y
27CONFIG_ARCH_MTD_XIP=y
28CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
29CONFIG_VECTORS_BASE=0xffff0000
30CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
31
32#
33# General setup
34#
35CONFIG_EXPERIMENTAL=y
36CONFIG_BROKEN_ON_SMP=y
37CONFIG_LOCK_KERNEL=y
38CONFIG_INIT_ENV_ARG_LIMIT=32
39CONFIG_LOCALVERSION=""
40CONFIG_LOCALVERSION_AUTO=y
41CONFIG_SWAP=y
42CONFIG_SYSVIPC=y
43CONFIG_SYSVIPC_SYSCTL=y
44# CONFIG_POSIX_MQUEUE is not set
45# CONFIG_BSD_PROCESS_ACCT is not set
46# CONFIG_TASKSTATS is not set
47# CONFIG_AUDIT is not set
48CONFIG_IKCONFIG=y
49CONFIG_IKCONFIG_PROC=y
50CONFIG_LOG_BUF_SHIFT=14
51# CONFIG_CGROUPS is not set
52CONFIG_GROUP_SCHED=y
53CONFIG_FAIR_GROUP_SCHED=y
54# CONFIG_RT_GROUP_SCHED is not set
55CONFIG_USER_SCHED=y
56# CONFIG_CGROUP_SCHED is not set
57CONFIG_SYSFS_DEPRECATED=y
58CONFIG_SYSFS_DEPRECATED_V2=y
59# CONFIG_RELAY is not set
60# CONFIG_NAMESPACES is not set
61# CONFIG_BLK_DEV_INITRD is not set
62CONFIG_CC_OPTIMIZE_FOR_SIZE=y
63CONFIG_SYSCTL=y
64CONFIG_EMBEDDED=y
65CONFIG_UID16=y
66CONFIG_SYSCTL_SYSCALL=y
67CONFIG_KALLSYMS=y
68# CONFIG_KALLSYMS_EXTRA_PASS is not set
69CONFIG_HOTPLUG=y
70CONFIG_PRINTK=y
71CONFIG_BUG=y
72CONFIG_ELF_CORE=y
73CONFIG_COMPAT_BRK=y
74CONFIG_BASE_FULL=y
75CONFIG_FUTEX=y
76CONFIG_ANON_INODES=y
77CONFIG_EPOLL=y
78CONFIG_SIGNALFD=y
79CONFIG_TIMERFD=y
80CONFIG_EVENTFD=y
81CONFIG_SHMEM=y
82CONFIG_VM_EVENT_COUNTERS=y
83CONFIG_SLAB=y
84# CONFIG_SLUB is not set
85# CONFIG_SLOB is not set
86# CONFIG_PROFILING is not set
87# CONFIG_MARKERS is not set
88CONFIG_HAVE_OPROFILE=y
89# CONFIG_KPROBES is not set
90# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
91# CONFIG_HAVE_IOREMAP_PROT is not set
92CONFIG_HAVE_KPROBES=y
93CONFIG_HAVE_KRETPROBES=y
94# CONFIG_HAVE_ARCH_TRACEHOOK is not set
95# CONFIG_HAVE_DMA_ATTRS is not set
96# CONFIG_USE_GENERIC_SMP_HELPERS is not set
97# CONFIG_HAVE_CLK is not set
98CONFIG_PROC_PAGE_MONITOR=y
99CONFIG_HAVE_GENERIC_DMA_COHERENT=y
100CONFIG_SLABINFO=y
101CONFIG_RT_MUTEXES=y
102# CONFIG_TINY_SHMEM is not set
103CONFIG_BASE_SMALL=0
104CONFIG_MODULES=y
105# CONFIG_MODULE_FORCE_LOAD is not set
106CONFIG_MODULE_UNLOAD=y
107CONFIG_MODULE_FORCE_UNLOAD=y
108CONFIG_MODVERSIONS=y
109# CONFIG_MODULE_SRCVERSION_ALL is not set
110CONFIG_KMOD=y
111CONFIG_BLOCK=y
112# CONFIG_LBD is not set
113# CONFIG_BLK_DEV_IO_TRACE is not set
114# CONFIG_LSF is not set
115# CONFIG_BLK_DEV_BSG is not set
116# CONFIG_BLK_DEV_INTEGRITY is not set
117
118#
119# IO Schedulers
120#
121CONFIG_IOSCHED_NOOP=y
122CONFIG_IOSCHED_AS=y
123CONFIG_IOSCHED_DEADLINE=y
124CONFIG_IOSCHED_CFQ=y
125# CONFIG_DEFAULT_AS is not set
126# CONFIG_DEFAULT_DEADLINE is not set
127CONFIG_DEFAULT_CFQ=y
128# CONFIG_DEFAULT_NOOP is not set
129CONFIG_DEFAULT_IOSCHED="cfq"
130CONFIG_CLASSIC_RCU=y
131
132#
133# System Type
134#
135# CONFIG_ARCH_AAEC2000 is not set
136# CONFIG_ARCH_INTEGRATOR is not set
137# CONFIG_ARCH_REALVIEW is not set
138# CONFIG_ARCH_VERSATILE is not set
139# CONFIG_ARCH_AT91 is not set
140# CONFIG_ARCH_CLPS7500 is not set
141# CONFIG_ARCH_CLPS711X is not set
142# CONFIG_ARCH_EBSA110 is not set
143# CONFIG_ARCH_EP93XX is not set
144# CONFIG_ARCH_FOOTBRIDGE is not set
145# CONFIG_ARCH_NETX is not set
146# CONFIG_ARCH_H720X is not set
147# CONFIG_ARCH_IMX is not set
148# CONFIG_ARCH_IOP13XX is not set
149# CONFIG_ARCH_IOP32X is not set
150# CONFIG_ARCH_IOP33X is not set
151# CONFIG_ARCH_IXP23XX is not set
152# CONFIG_ARCH_IXP2000 is not set
153# CONFIG_ARCH_IXP4XX is not set
154# CONFIG_ARCH_L7200 is not set
155# CONFIG_ARCH_KIRKWOOD is not set
156# CONFIG_ARCH_KS8695 is not set
157# CONFIG_ARCH_NS9XXX is not set
158# CONFIG_ARCH_LOKI is not set
159# CONFIG_ARCH_MV78XX0 is not set
160CONFIG_ARCH_MXC=y
161# CONFIG_ARCH_ORION5X is not set
162# CONFIG_ARCH_PNX4008 is not set
163# CONFIG_ARCH_PXA is not set
164# CONFIG_ARCH_RPC is not set
165# CONFIG_ARCH_SA1100 is not set
166# CONFIG_ARCH_S3C2410 is not set
167# CONFIG_ARCH_SHARK is not set
168# CONFIG_ARCH_LH7A40X is not set
169# CONFIG_ARCH_DAVINCI is not set
170# CONFIG_ARCH_OMAP is not set
171# CONFIG_ARCH_MSM7X00A is not set
172
173#
174# Boot options
175#
176
177#
178# Power management
179#
180
181#
182# Freescale MXC Implementations
183#
184# CONFIG_ARCH_MX2 is not set
185CONFIG_ARCH_MX3=y
186
187#
188# MX3 Options
189#
190# CONFIG_MACH_MX31ADS is not set
191# CONFIG_MACH_PCM037 is not set
192# CONFIG_MACH_MX31LITE is not set
193CONFIG_MACH_MX31MOBOARD=y
194# CONFIG_MXC_IRQ_PRIOR is not set
195
196#
197# Processor Type
198#
199CONFIG_CPU_32=y
200CONFIG_CPU_V6=y
201# CONFIG_CPU_32v6K is not set
202CONFIG_CPU_32v6=y
203CONFIG_CPU_ABRT_EV6=y
204CONFIG_CPU_PABRT_NOIFAR=y
205CONFIG_CPU_CACHE_V6=y
206CONFIG_CPU_CACHE_VIPT=y
207CONFIG_CPU_COPY_V6=y
208CONFIG_CPU_TLB_V6=y
209CONFIG_CPU_HAS_ASID=y
210CONFIG_CPU_CP15=y
211CONFIG_CPU_CP15_MMU=y
212
213#
214# Processor Features
215#
216CONFIG_ARM_THUMB=y
217# CONFIG_CPU_ICACHE_DISABLE is not set
218# CONFIG_CPU_DCACHE_DISABLE is not set
219# CONFIG_CPU_BPREDICT_DISABLE is not set
220# CONFIG_OUTER_CACHE is not set
221
222#
223# Bus support
224#
225# CONFIG_PCI_SYSCALL is not set
226# CONFIG_ARCH_SUPPORTS_MSI is not set
227# CONFIG_PCCARD is not set
228
229#
230# Kernel Features
231#
232CONFIG_TICK_ONESHOT=y
233CONFIG_NO_HZ=y
234CONFIG_HIGH_RES_TIMERS=y
235CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
236CONFIG_PREEMPT=y
237CONFIG_HZ=100
238CONFIG_AEABI=y
239# CONFIG_OABI_COMPAT is not set
240CONFIG_ARCH_FLATMEM_HAS_HOLES=y
241# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
242CONFIG_SELECT_MEMORY_MODEL=y
243CONFIG_FLATMEM_MANUAL=y
244# CONFIG_DISCONTIGMEM_MANUAL is not set
245# CONFIG_SPARSEMEM_MANUAL is not set
246CONFIG_FLATMEM=y
247CONFIG_FLAT_NODE_MEM_MAP=y
248# CONFIG_SPARSEMEM_STATIC is not set
249# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
250CONFIG_PAGEFLAGS_EXTENDED=y
251CONFIG_SPLIT_PTLOCK_CPUS=4
252# CONFIG_RESOURCES_64BIT is not set
253CONFIG_ZONE_DMA_FLAG=1
254CONFIG_BOUNCE=y
255CONFIG_VIRT_TO_BUS=y
256CONFIG_ALIGNMENT_TRAP=y
257
258#
259# Boot options
260#
261CONFIG_ZBOOT_ROM_TEXT=0x0
262CONFIG_ZBOOT_ROM_BSS=0x0
263CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off"
264# CONFIG_XIP_KERNEL is not set
265# CONFIG_KEXEC is not set
266
267#
268# Floating point emulation
269#
270
271#
272# At least one emulation must be selected
273#
274CONFIG_VFP=y
275
276#
277# Userspace binary formats
278#
279CONFIG_BINFMT_ELF=y
280# CONFIG_BINFMT_AOUT is not set
281# CONFIG_BINFMT_MISC is not set
282
283#
284# Power management options
285#
286# CONFIG_PM is not set
287CONFIG_ARCH_SUSPEND_POSSIBLE=y
288CONFIG_NET=y
289
290#
291# Networking options
292#
293CONFIG_PACKET=y
294# CONFIG_PACKET_MMAP is not set
295CONFIG_UNIX=y
296# CONFIG_NET_KEY is not set
297CONFIG_INET=y
298# CONFIG_IP_MULTICAST is not set
299# CONFIG_IP_ADVANCED_ROUTER is not set
300CONFIG_IP_FIB_HASH=y
301CONFIG_IP_PNP=y
302CONFIG_IP_PNP_DHCP=y
303# CONFIG_IP_PNP_BOOTP is not set
304# CONFIG_IP_PNP_RARP is not set
305# CONFIG_NET_IPIP is not set
306# CONFIG_NET_IPGRE is not set
307# CONFIG_ARPD is not set
308# CONFIG_SYN_COOKIES is not set
309# CONFIG_INET_AH is not set
310# CONFIG_INET_ESP is not set
311# CONFIG_INET_IPCOMP is not set
312# CONFIG_INET_XFRM_TUNNEL is not set
313# CONFIG_INET_TUNNEL is not set
314# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
315# CONFIG_INET_XFRM_MODE_TUNNEL is not set
316# CONFIG_INET_XFRM_MODE_BEET is not set
317# CONFIG_INET_LRO is not set
318# CONFIG_INET_DIAG is not set
319# CONFIG_TCP_CONG_ADVANCED is not set
320CONFIG_TCP_CONG_CUBIC=y
321CONFIG_DEFAULT_TCP_CONG="cubic"
322# CONFIG_TCP_MD5SIG is not set
323# CONFIG_IPV6 is not set
324# CONFIG_NETWORK_SECMARK is not set
325# CONFIG_NETFILTER is not set
326# CONFIG_IP_DCCP is not set
327# CONFIG_IP_SCTP is not set
328# CONFIG_TIPC is not set
329# CONFIG_ATM is not set
330# CONFIG_BRIDGE is not set
331# CONFIG_VLAN_8021Q is not set
332# CONFIG_DECNET is not set
333# CONFIG_LLC2 is not set
334# CONFIG_IPX is not set
335# CONFIG_ATALK is not set
336# CONFIG_X25 is not set
337# CONFIG_LAPB is not set
338# CONFIG_ECONET is not set
339# CONFIG_WAN_ROUTER is not set
340# CONFIG_NET_SCHED is not set
341
342#
343# Network testing
344#
345# CONFIG_NET_PKTGEN is not set
346# CONFIG_HAMRADIO is not set
347# CONFIG_CAN is not set
348# CONFIG_IRDA is not set
349# CONFIG_BT is not set
350# CONFIG_AF_RXRPC is not set
351
352#
353# Wireless
354#
355# CONFIG_CFG80211 is not set
356# CONFIG_WIRELESS_EXT is not set
357# CONFIG_MAC80211 is not set
358# CONFIG_IEEE80211 is not set
359# CONFIG_RFKILL is not set
360# CONFIG_NET_9P is not set
361
362#
363# Device Drivers
364#
365
366#
367# Generic Driver Options
368#
369CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
370CONFIG_STANDALONE=y
371CONFIG_PREVENT_FIRMWARE_BUILD=y
372CONFIG_FW_LOADER=m
373CONFIG_FIRMWARE_IN_KERNEL=y
374CONFIG_EXTRA_FIRMWARE=""
375# CONFIG_SYS_HYPERVISOR is not set
376# CONFIG_CONNECTOR is not set
377CONFIG_MTD=y
378# CONFIG_MTD_DEBUG is not set
379# CONFIG_MTD_CONCAT is not set
380CONFIG_MTD_PARTITIONS=y
381CONFIG_MTD_REDBOOT_PARTS=y
382CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
383# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
384CONFIG_MTD_REDBOOT_PARTS_READONLY=y
385# CONFIG_MTD_CMDLINE_PARTS is not set
386# CONFIG_MTD_AFS_PARTS is not set
387# CONFIG_MTD_AR7_PARTS is not set
388
389#
390# User Modules And Translation Layers
391#
392CONFIG_MTD_CHAR=y
393CONFIG_MTD_BLKDEVS=y
394CONFIG_MTD_BLOCK=y
395# CONFIG_FTL is not set
396# CONFIG_NFTL is not set
397# CONFIG_INFTL is not set
398# CONFIG_RFD_FTL is not set
399# CONFIG_SSFDC is not set
400# CONFIG_MTD_OOPS is not set
401
402#
403# RAM/ROM/Flash chip drivers
404#
405CONFIG_MTD_CFI=y
406# CONFIG_MTD_JEDECPROBE is not set
407CONFIG_MTD_GEN_PROBE=y
408CONFIG_MTD_CFI_ADV_OPTIONS=y
409CONFIG_MTD_CFI_NOSWAP=y
410# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
411# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
412CONFIG_MTD_CFI_GEOMETRY=y
413# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
414CONFIG_MTD_MAP_BANK_WIDTH_2=y
415# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
416# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
417# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
418# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
419CONFIG_MTD_CFI_I1=y
420# CONFIG_MTD_CFI_I2 is not set
421# CONFIG_MTD_CFI_I4 is not set
422# CONFIG_MTD_CFI_I8 is not set
423# CONFIG_MTD_OTP is not set
424# CONFIG_MTD_CFI_INTELEXT is not set
425CONFIG_MTD_CFI_AMDSTD=y
426# CONFIG_MTD_CFI_STAA is not set
427CONFIG_MTD_CFI_UTIL=y
428# CONFIG_MTD_RAM is not set
429# CONFIG_MTD_ROM is not set
430# CONFIG_MTD_ABSENT is not set
431# CONFIG_MTD_XIP is not set
432
433#
434# Mapping drivers for chip access
435#
436# CONFIG_MTD_COMPLEX_MAPPINGS is not set
437CONFIG_MTD_PHYSMAP=y
438CONFIG_MTD_PHYSMAP_START=0x0
439CONFIG_MTD_PHYSMAP_LEN=0x0
440CONFIG_MTD_PHYSMAP_BANKWIDTH=2
441# CONFIG_MTD_ARM_INTEGRATOR is not set
442# CONFIG_MTD_PLATRAM is not set
443
444#
445# Self-contained MTD device drivers
446#
447# CONFIG_MTD_SLRAM is not set
448# CONFIG_MTD_PHRAM is not set
449# CONFIG_MTD_MTDRAM is not set
450# CONFIG_MTD_BLOCK2MTD is not set
451
452#
453# Disk-On-Chip Device Drivers
454#
455# CONFIG_MTD_DOC2000 is not set
456# CONFIG_MTD_DOC2001 is not set
457# CONFIG_MTD_DOC2001PLUS is not set
458# CONFIG_MTD_NAND is not set
459# CONFIG_MTD_ONENAND is not set
460
461#
462# UBI - Unsorted block images
463#
464# CONFIG_MTD_UBI is not set
465# CONFIG_PARPORT is not set
466# CONFIG_BLK_DEV is not set
467# CONFIG_MISC_DEVICES is not set
468CONFIG_HAVE_IDE=y
469# CONFIG_IDE is not set
470
471#
472# SCSI device support
473#
474# CONFIG_RAID_ATTRS is not set
475# CONFIG_SCSI is not set
476# CONFIG_SCSI_DMA is not set
477# CONFIG_SCSI_NETLINK is not set
478# CONFIG_ATA is not set
479# CONFIG_MD is not set
480CONFIG_NETDEVICES=y
481# CONFIG_DUMMY is not set
482# CONFIG_BONDING is not set
483# CONFIG_MACVLAN is not set
484# CONFIG_EQUALIZER is not set
485# CONFIG_TUN is not set
486# CONFIG_VETH is not set
487# CONFIG_PHYLIB is not set
488CONFIG_NET_ETHERNET=y
489CONFIG_MII=y
490# CONFIG_AX88796 is not set
491CONFIG_SMC91X=y
492# CONFIG_DM9000 is not set
493# CONFIG_IBM_NEW_EMAC_ZMII is not set
494# CONFIG_IBM_NEW_EMAC_RGMII is not set
495# CONFIG_IBM_NEW_EMAC_TAH is not set
496# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
497# CONFIG_B44 is not set
498# CONFIG_NETDEV_1000 is not set
499# CONFIG_NETDEV_10000 is not set
500
501#
502# Wireless LAN
503#
504# CONFIG_WLAN_PRE80211 is not set
505# CONFIG_WLAN_80211 is not set
506# CONFIG_IWLWIFI_LEDS is not set
507# CONFIG_WAN is not set
508# CONFIG_PPP is not set
509# CONFIG_SLIP is not set
510# CONFIG_NETCONSOLE is not set
511# CONFIG_NETPOLL is not set
512# CONFIG_NET_POLL_CONTROLLER is not set
513# CONFIG_ISDN is not set
514
515#
516# Input device support
517#
518# CONFIG_INPUT is not set
519
520#
521# Hardware I/O ports
522#
523# CONFIG_SERIO is not set
524# CONFIG_GAMEPORT is not set
525
526#
527# Character devices
528#
529# CONFIG_VT is not set
530CONFIG_DEVKMEM=y
531# CONFIG_SERIAL_NONSTANDARD is not set
532
533#
534# Serial drivers
535#
536# CONFIG_SERIAL_8250 is not set
537
538#
539# Non-8250 serial port support
540#
541CONFIG_SERIAL_IMX=y
542CONFIG_SERIAL_IMX_CONSOLE=y
543CONFIG_SERIAL_CORE=y
544CONFIG_SERIAL_CORE_CONSOLE=y
545CONFIG_UNIX98_PTYS=y
546# CONFIG_LEGACY_PTYS is not set
547# CONFIG_IPMI_HANDLER is not set
548# CONFIG_HW_RANDOM is not set
549# CONFIG_NVRAM is not set
550# CONFIG_R3964 is not set
551# CONFIG_RAW_DRIVER is not set
552# CONFIG_TCG_TPM is not set
553# CONFIG_I2C is not set
554# CONFIG_SPI is not set
555CONFIG_ARCH_REQUIRE_GPIOLIB=y
556CONFIG_GPIOLIB=y
557# CONFIG_GPIO_SYSFS is not set
558
559#
560# I2C GPIO expanders:
561#
562
563#
564# PCI GPIO expanders:
565#
566
567#
568# SPI GPIO expanders:
569#
570# CONFIG_W1 is not set
571# CONFIG_POWER_SUPPLY is not set
572# CONFIG_HWMON is not set
573# CONFIG_WATCHDOG is not set
574
575#
576# Sonics Silicon Backplane
577#
578CONFIG_SSB_POSSIBLE=y
579# CONFIG_SSB is not set
580
581#
582# Multifunction device drivers
583#
584# CONFIG_MFD_CORE is not set
585# CONFIG_MFD_SM501 is not set
586# CONFIG_HTC_EGPIO is not set
587# CONFIG_HTC_PASIC3 is not set
588# CONFIG_MFD_TMIO is not set
589# CONFIG_MFD_T7L66XB is not set
590# CONFIG_MFD_TC6387XB is not set
591# CONFIG_MFD_TC6393XB is not set
592
593#
594# Multimedia devices
595#
596
597#
598# Multimedia core support
599#
600# CONFIG_VIDEO_DEV is not set
601# CONFIG_DVB_CORE is not set
602# CONFIG_VIDEO_MEDIA is not set
603
604#
605# Multimedia drivers
606#
607# CONFIG_DAB is not set
608
609#
610# Graphics support
611#
612# CONFIG_VGASTATE is not set
613# CONFIG_VIDEO_OUTPUT_CONTROL is not set
614# CONFIG_FB is not set
615# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
616
617#
618# Display device support
619#
620# CONFIG_DISPLAY_SUPPORT is not set
621# CONFIG_SOUND is not set
622# CONFIG_USB_SUPPORT is not set
623# CONFIG_MMC is not set
624# CONFIG_NEW_LEDS is not set
625CONFIG_RTC_LIB=y
626# CONFIG_RTC_CLASS is not set
627# CONFIG_DMADEVICES is not set
628
629#
630# Voltage and Current regulators
631#
632# CONFIG_REGULATOR is not set
633# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
634# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
635# CONFIG_REGULATOR_BQ24022 is not set
636# CONFIG_UIO is not set
637
638#
639# File systems
640#
641# CONFIG_EXT2_FS is not set
642# CONFIG_EXT3_FS is not set
643# CONFIG_EXT4DEV_FS is not set
644# CONFIG_REISERFS_FS is not set
645# CONFIG_JFS_FS is not set
646# CONFIG_FS_POSIX_ACL is not set
647# CONFIG_XFS_FS is not set
648# CONFIG_OCFS2_FS is not set
649# CONFIG_DNOTIFY is not set
650CONFIG_INOTIFY=y
651CONFIG_INOTIFY_USER=y
652# CONFIG_QUOTA is not set
653# CONFIG_AUTOFS_FS is not set
654# CONFIG_AUTOFS4_FS is not set
655# CONFIG_FUSE_FS is not set
656
657#
658# CD-ROM/DVD Filesystems
659#
660# CONFIG_ISO9660_FS is not set
661# CONFIG_UDF_FS is not set
662
663#
664# DOS/FAT/NT Filesystems
665#
666# CONFIG_MSDOS_FS is not set
667# CONFIG_VFAT_FS is not set
668# CONFIG_NTFS_FS is not set
669
670#
671# Pseudo filesystems
672#
673CONFIG_PROC_FS=y
674CONFIG_PROC_SYSCTL=y
675CONFIG_SYSFS=y
676CONFIG_TMPFS=y
677# CONFIG_TMPFS_POSIX_ACL is not set
678# CONFIG_HUGETLB_PAGE is not set
679# CONFIG_CONFIGFS_FS is not set
680
681#
682# Miscellaneous filesystems
683#
684# CONFIG_ADFS_FS is not set
685# CONFIG_AFFS_FS is not set
686# CONFIG_HFS_FS is not set
687# CONFIG_HFSPLUS_FS is not set
688# CONFIG_BEFS_FS is not set
689# CONFIG_BFS_FS is not set
690# CONFIG_EFS_FS is not set
691CONFIG_JFFS2_FS=y
692CONFIG_JFFS2_FS_DEBUG=0
693CONFIG_JFFS2_FS_WRITEBUFFER=y
694# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
695# CONFIG_JFFS2_SUMMARY is not set
696# CONFIG_JFFS2_FS_XATTR is not set
697# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
698CONFIG_JFFS2_ZLIB=y
699# CONFIG_JFFS2_LZO is not set
700CONFIG_JFFS2_RTIME=y
701# CONFIG_JFFS2_RUBIN is not set
702# CONFIG_CRAMFS is not set
703# CONFIG_VXFS_FS is not set
704# CONFIG_MINIX_FS is not set
705# CONFIG_OMFS_FS is not set
706# CONFIG_HPFS_FS is not set
707# CONFIG_QNX4FS_FS is not set
708# CONFIG_ROMFS_FS is not set
709# CONFIG_SYSV_FS is not set
710# CONFIG_UFS_FS is not set
711CONFIG_NETWORK_FILESYSTEMS=y
712CONFIG_NFS_FS=y
713# CONFIG_NFS_V3 is not set
714# CONFIG_NFS_V4 is not set
715CONFIG_ROOT_NFS=y
716# CONFIG_NFSD is not set
717CONFIG_LOCKD=y
718CONFIG_NFS_COMMON=y
719CONFIG_SUNRPC=y
720# CONFIG_RPCSEC_GSS_KRB5 is not set
721# CONFIG_RPCSEC_GSS_SPKM3 is not set
722# CONFIG_SMB_FS is not set
723# CONFIG_CIFS is not set
724# CONFIG_NCP_FS is not set
725# CONFIG_CODA_FS is not set
726# CONFIG_AFS_FS is not set
727
728#
729# Partition Types
730#
731# CONFIG_PARTITION_ADVANCED is not set
732CONFIG_MSDOS_PARTITION=y
733# CONFIG_NLS is not set
734# CONFIG_DLM is not set
735
736#
737# Kernel hacking
738#
739# CONFIG_PRINTK_TIME is not set
740# CONFIG_ENABLE_WARN_DEPRECATED is not set
741# CONFIG_ENABLE_MUST_CHECK is not set
742CONFIG_FRAME_WARN=1024
743# CONFIG_MAGIC_SYSRQ is not set
744# CONFIG_UNUSED_SYMBOLS is not set
745# CONFIG_DEBUG_FS is not set
746# CONFIG_HEADERS_CHECK is not set
747# CONFIG_DEBUG_KERNEL is not set
748# CONFIG_DEBUG_BUGVERBOSE is not set
749# CONFIG_DEBUG_MEMORY_INIT is not set
750CONFIG_FRAME_POINTER=y
751# CONFIG_LATENCYTOP is not set
752CONFIG_SYSCTL_SYSCALL_CHECK=y
753CONFIG_HAVE_FTRACE=y
754CONFIG_HAVE_DYNAMIC_FTRACE=y
755# CONFIG_FTRACE is not set
756# CONFIG_IRQSOFF_TRACER is not set
757# CONFIG_PREEMPT_TRACER is not set
758# CONFIG_SCHED_TRACER is not set
759# CONFIG_CONTEXT_SWITCH_TRACER is not set
760# CONFIG_SAMPLES is not set
761CONFIG_HAVE_ARCH_KGDB=y
762# CONFIG_DEBUG_USER is not set
763
764#
765# Security options
766#
767# CONFIG_KEYS is not set
768# CONFIG_SECURITY is not set
769# CONFIG_SECURITY_FILE_CAPABILITIES is not set
770# CONFIG_CRYPTO is not set
771
772#
773# Library routines
774#
775CONFIG_BITREVERSE=y
776# CONFIG_GENERIC_FIND_FIRST_BIT is not set
777# CONFIG_GENERIC_FIND_NEXT_BIT is not set
778# CONFIG_CRC_CCITT is not set
779# CONFIG_CRC16 is not set
780# CONFIG_CRC_T10DIF is not set
781# CONFIG_CRC_ITU_T is not set
782CONFIG_CRC32=y
783# CONFIG_CRC7 is not set
784# CONFIG_LIBCRC32C is not set
785CONFIG_ZLIB_INFLATE=y
786CONFIG_ZLIB_DEFLATE=y
787CONFIG_PLIST=y
788CONFIG_HAS_IOMEM=y
789CONFIG_HAS_IOPORT=y
790CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/mx31pdk_defconfig b/arch/arm/configs/mx31pdk_defconfig
new file mode 100644
index 000000000000..95ffc0db95a0
--- /dev/null
+++ b/arch/arm/configs/mx31pdk_defconfig
@@ -0,0 +1,773 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.28-rc2
4# Sun Oct 26 15:55:29 2008
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_HAVE_LATENCYTOP_SUPPORT=y
16CONFIG_LOCKDEP_SUPPORT=y
17CONFIG_TRACE_IRQFLAGS_SUPPORT=y
18CONFIG_HARDIRQS_SW_RESEND=y
19CONFIG_GENERIC_IRQ_PROBE=y
20CONFIG_RWSEM_GENERIC_SPINLOCK=y
21# CONFIG_ARCH_HAS_ILOG2_U32 is not set
22# CONFIG_ARCH_HAS_ILOG2_U64 is not set
23CONFIG_GENERIC_HWEIGHT=y
24CONFIG_GENERIC_CALIBRATE_DELAY=y
25CONFIG_ARCH_MTD_XIP=y
26CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
27CONFIG_VECTORS_BASE=0xffff0000
28CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
29
30#
31# General setup
32#
33# CONFIG_EXPERIMENTAL is not set
34CONFIG_BROKEN_ON_SMP=y
35CONFIG_INIT_ENV_ARG_LIMIT=32
36CONFIG_LOCALVERSION=""
37# CONFIG_LOCALVERSION_AUTO is not set
38# CONFIG_SWAP is not set
39# CONFIG_SYSVIPC is not set
40# CONFIG_BSD_PROCESS_ACCT is not set
41# CONFIG_TASKSTATS is not set
42# CONFIG_AUDIT is not set
43# CONFIG_IKCONFIG is not set
44CONFIG_LOG_BUF_SHIFT=17
45# CONFIG_CGROUPS is not set
46# CONFIG_SYSFS_DEPRECATED_V2 is not set
47# CONFIG_RELAY is not set
48CONFIG_NAMESPACES=y
49# CONFIG_UTS_NS is not set
50# CONFIG_BLK_DEV_INITRD is not set
51# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
52CONFIG_SYSCTL=y
53# CONFIG_EMBEDDED is not set
54CONFIG_UID16=y
55CONFIG_SYSCTL_SYSCALL=y
56CONFIG_KALLSYMS=y
57# CONFIG_KALLSYMS_EXTRA_PASS is not set
58CONFIG_HOTPLUG=y
59CONFIG_PRINTK=y
60CONFIG_BUG=y
61CONFIG_ELF_CORE=y
62# CONFIG_COMPAT_BRK is not set
63CONFIG_BASE_FULL=y
64CONFIG_FUTEX=y
65CONFIG_ANON_INODES=y
66CONFIG_EPOLL=y
67CONFIG_SIGNALFD=y
68CONFIG_TIMERFD=y
69CONFIG_EVENTFD=y
70CONFIG_SHMEM=y
71CONFIG_AIO=y
72CONFIG_VM_EVENT_COUNTERS=y
73CONFIG_SLUB_DEBUG=y
74# CONFIG_SLAB is not set
75CONFIG_SLUB=y
76# CONFIG_SLOB is not set
77# CONFIG_PROFILING is not set
78# CONFIG_MARKERS is not set
79CONFIG_HAVE_OPROFILE=y
80CONFIG_HAVE_KPROBES=y
81CONFIG_HAVE_KRETPROBES=y
82CONFIG_HAVE_GENERIC_DMA_COHERENT=y
83CONFIG_SLABINFO=y
84CONFIG_RT_MUTEXES=y
85# CONFIG_TINY_SHMEM is not set
86CONFIG_BASE_SMALL=0
87# CONFIG_MODULES is not set
88CONFIG_BLOCK=y
89# CONFIG_LBD is not set
90# CONFIG_BLK_DEV_IO_TRACE is not set
91# CONFIG_LSF is not set
92# CONFIG_BLK_DEV_INTEGRITY is not set
93
94#
95# IO Schedulers
96#
97CONFIG_IOSCHED_NOOP=y
98# CONFIG_IOSCHED_AS is not set
99# CONFIG_IOSCHED_DEADLINE is not set
100# CONFIG_IOSCHED_CFQ is not set
101# CONFIG_DEFAULT_AS is not set
102# CONFIG_DEFAULT_DEADLINE is not set
103# CONFIG_DEFAULT_CFQ is not set
104CONFIG_DEFAULT_NOOP=y
105CONFIG_DEFAULT_IOSCHED="noop"
106CONFIG_CLASSIC_RCU=y
107# CONFIG_FREEZER is not set
108
109#
110# System Type
111#
112# CONFIG_ARCH_AAEC2000 is not set
113# CONFIG_ARCH_INTEGRATOR is not set
114# CONFIG_ARCH_REALVIEW is not set
115# CONFIG_ARCH_VERSATILE is not set
116# CONFIG_ARCH_AT91 is not set
117# CONFIG_ARCH_CLPS7500 is not set
118# CONFIG_ARCH_CLPS711X is not set
119# CONFIG_ARCH_EBSA110 is not set
120# CONFIG_ARCH_EP93XX is not set
121# CONFIG_ARCH_FOOTBRIDGE is not set
122# CONFIG_ARCH_NETX is not set
123# CONFIG_ARCH_H720X is not set
124# CONFIG_ARCH_IMX is not set
125# CONFIG_ARCH_IOP13XX is not set
126# CONFIG_ARCH_IOP32X is not set
127# CONFIG_ARCH_IOP33X is not set
128# CONFIG_ARCH_IXP23XX is not set
129# CONFIG_ARCH_IXP2000 is not set
130# CONFIG_ARCH_IXP4XX is not set
131# CONFIG_ARCH_L7200 is not set
132# CONFIG_ARCH_KIRKWOOD is not set
133# CONFIG_ARCH_KS8695 is not set
134# CONFIG_ARCH_NS9XXX is not set
135# CONFIG_ARCH_LOKI is not set
136# CONFIG_ARCH_MV78XX0 is not set
137CONFIG_ARCH_MXC=y
138# CONFIG_ARCH_ORION5X is not set
139# CONFIG_ARCH_PNX4008 is not set
140# CONFIG_ARCH_PXA is not set
141# CONFIG_ARCH_RPC is not set
142# CONFIG_ARCH_SA1100 is not set
143# CONFIG_ARCH_S3C2410 is not set
144# CONFIG_ARCH_SHARK is not set
145# CONFIG_ARCH_LH7A40X is not set
146# CONFIG_ARCH_DAVINCI is not set
147# CONFIG_ARCH_OMAP is not set
148# CONFIG_ARCH_MSM is not set
149
150#
151# Boot options
152#
153
154#
155# Power management
156#
157
158#
159# Freescale MXC Implementations
160#
161# CONFIG_ARCH_MX2 is not set
162CONFIG_ARCH_MX3=y
163
164#
165# MX3 Options
166#
167# CONFIG_MACH_MX31ADS is not set
168# CONFIG_MACH_PCM037 is not set
169# CONFIG_MACH_MX31LITE is not set
170CONFIG_MACH_MX31_3DS=y
171# CONFIG_MXC_IRQ_PRIOR is not set
172
173#
174# Processor Type
175#
176CONFIG_CPU_32=y
177CONFIG_CPU_V6=y
178# CONFIG_CPU_32v6K is not set
179CONFIG_CPU_32v6=y
180CONFIG_CPU_ABRT_EV6=y
181CONFIG_CPU_PABRT_NOIFAR=y
182CONFIG_CPU_CACHE_V6=y
183CONFIG_CPU_CACHE_VIPT=y
184CONFIG_CPU_COPY_V6=y
185CONFIG_CPU_TLB_V6=y
186CONFIG_CPU_HAS_ASID=y
187CONFIG_CPU_CP15=y
188CONFIG_CPU_CP15_MMU=y
189
190#
191# Processor Features
192#
193CONFIG_ARM_THUMB=y
194# CONFIG_CPU_ICACHE_DISABLE is not set
195# CONFIG_CPU_DCACHE_DISABLE is not set
196# CONFIG_CPU_BPREDICT_DISABLE is not set
197# CONFIG_OUTER_CACHE is not set
198
199#
200# Bus support
201#
202# CONFIG_PCI_SYSCALL is not set
203# CONFIG_ARCH_SUPPORTS_MSI is not set
204# CONFIG_PCCARD is not set
205
206#
207# Kernel Features
208#
209# CONFIG_NO_HZ is not set
210# CONFIG_HIGH_RES_TIMERS is not set
211CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
212CONFIG_VMSPLIT_3G=y
213# CONFIG_VMSPLIT_2G is not set
214# CONFIG_VMSPLIT_1G is not set
215CONFIG_PAGE_OFFSET=0xC0000000
216CONFIG_HZ=100
217CONFIG_AEABI=y
218CONFIG_ARCH_FLATMEM_HAS_HOLES=y
219# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
220# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
221CONFIG_FLATMEM=y
222CONFIG_FLAT_NODE_MEM_MAP=y
223CONFIG_PAGEFLAGS_EXTENDED=y
224CONFIG_SPLIT_PTLOCK_CPUS=4
225# CONFIG_RESOURCES_64BIT is not set
226# CONFIG_PHYS_ADDR_T_64BIT is not set
227CONFIG_ZONE_DMA_FLAG=0
228CONFIG_VIRT_TO_BUS=y
229# CONFIG_UNEVICTABLE_LRU is not set
230CONFIG_ALIGNMENT_TRAP=y
231
232#
233# Boot options
234#
235CONFIG_ZBOOT_ROM_TEXT=0
236CONFIG_ZBOOT_ROM_BSS=0
237CONFIG_CMDLINE=""
238# CONFIG_XIP_KERNEL is not set
239
240#
241# CPU Power Management
242#
243# CONFIG_CPU_IDLE is not set
244
245#
246# Floating point emulation
247#
248
249#
250# At least one emulation must be selected
251#
252# CONFIG_VFP is not set
253
254#
255# Userspace binary formats
256#
257CONFIG_BINFMT_ELF=y
258# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
259CONFIG_HAVE_AOUT=y
260# CONFIG_BINFMT_AOUT is not set
261# CONFIG_BINFMT_MISC is not set
262
263#
264# Power management options
265#
266# CONFIG_PM is not set
267CONFIG_ARCH_SUSPEND_POSSIBLE=y
268CONFIG_NET=y
269
270#
271# Networking options
272#
273CONFIG_PACKET=y
274# CONFIG_PACKET_MMAP is not set
275CONFIG_UNIX=y
276CONFIG_XFRM=y
277# CONFIG_XFRM_USER is not set
278CONFIG_NET_KEY=y
279CONFIG_INET=y
280# CONFIG_IP_MULTICAST is not set
281# CONFIG_IP_ADVANCED_ROUTER is not set
282CONFIG_IP_FIB_HASH=y
283CONFIG_IP_PNP=y
284CONFIG_IP_PNP_DHCP=y
285# CONFIG_IP_PNP_BOOTP is not set
286# CONFIG_IP_PNP_RARP is not set
287# CONFIG_NET_IPIP is not set
288# CONFIG_NET_IPGRE is not set
289# CONFIG_SYN_COOKIES is not set
290# CONFIG_INET_AH is not set
291# CONFIG_INET_ESP is not set
292# CONFIG_INET_IPCOMP is not set
293# CONFIG_INET_XFRM_TUNNEL is not set
294CONFIG_INET_TUNNEL=y
295CONFIG_INET_XFRM_MODE_TRANSPORT=y
296CONFIG_INET_XFRM_MODE_TUNNEL=y
297CONFIG_INET_XFRM_MODE_BEET=y
298# CONFIG_INET_LRO is not set
299CONFIG_INET_DIAG=y
300CONFIG_INET_TCP_DIAG=y
301# CONFIG_TCP_CONG_ADVANCED is not set
302CONFIG_TCP_CONG_CUBIC=y
303CONFIG_DEFAULT_TCP_CONG="cubic"
304CONFIG_IPV6=y
305# CONFIG_IPV6_PRIVACY is not set
306# CONFIG_IPV6_ROUTER_PREF is not set
307# CONFIG_INET6_AH is not set
308# CONFIG_INET6_ESP is not set
309# CONFIG_INET6_IPCOMP is not set
310# CONFIG_INET6_XFRM_TUNNEL is not set
311# CONFIG_INET6_TUNNEL is not set
312CONFIG_INET6_XFRM_MODE_TRANSPORT=y
313CONFIG_INET6_XFRM_MODE_TUNNEL=y
314CONFIG_INET6_XFRM_MODE_BEET=y
315CONFIG_IPV6_SIT=y
316CONFIG_IPV6_NDISC_NODETYPE=y
317# CONFIG_IPV6_TUNNEL is not set
318# CONFIG_NETWORK_SECMARK is not set
319# CONFIG_NETFILTER is not set
320# CONFIG_ATM is not set
321# CONFIG_BRIDGE is not set
322# CONFIG_VLAN_8021Q is not set
323# CONFIG_DECNET is not set
324# CONFIG_LLC2 is not set
325# CONFIG_IPX is not set
326# CONFIG_ATALK is not set
327# CONFIG_NET_SCHED is not set
328
329#
330# Network testing
331#
332# CONFIG_NET_PKTGEN is not set
333# CONFIG_HAMRADIO is not set
334# CONFIG_CAN is not set
335# CONFIG_IRDA is not set
336# CONFIG_BT is not set
337# CONFIG_PHONET is not set
338CONFIG_WIRELESS=y
339# CONFIG_CFG80211 is not set
340CONFIG_WIRELESS_OLD_REGULATORY=y
341# CONFIG_WIRELESS_EXT is not set
342# CONFIG_MAC80211 is not set
343# CONFIG_IEEE80211 is not set
344# CONFIG_RFKILL is not set
345
346#
347# Device Drivers
348#
349
350#
351# Generic Driver Options
352#
353CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
354CONFIG_STANDALONE=y
355# CONFIG_PREVENT_FIRMWARE_BUILD is not set
356CONFIG_FW_LOADER=y
357# CONFIG_FIRMWARE_IN_KERNEL is not set
358CONFIG_EXTRA_FIRMWARE=""
359# CONFIG_SYS_HYPERVISOR is not set
360# CONFIG_CONNECTOR is not set
361# CONFIG_MTD is not set
362# CONFIG_PARPORT is not set
363# CONFIG_BLK_DEV is not set
364# CONFIG_MISC_DEVICES is not set
365CONFIG_HAVE_IDE=y
366# CONFIG_IDE is not set
367
368#
369# SCSI device support
370#
371# CONFIG_RAID_ATTRS is not set
372# CONFIG_SCSI is not set
373# CONFIG_SCSI_DMA is not set
374# CONFIG_SCSI_NETLINK is not set
375# CONFIG_ATA is not set
376# CONFIG_MD is not set
377CONFIG_NETDEVICES=y
378# CONFIG_DUMMY is not set
379# CONFIG_BONDING is not set
380# CONFIG_EQUALIZER is not set
381# CONFIG_TUN is not set
382# CONFIG_VETH is not set
383# CONFIG_PHYLIB is not set
384CONFIG_NET_ETHERNET=y
385# CONFIG_MII is not set
386# CONFIG_AX88796 is not set
387# CONFIG_SMC91X is not set
388# CONFIG_DM9000 is not set
389# CONFIG_SMC911X is not set
390# CONFIG_IBM_NEW_EMAC_ZMII is not set
391# CONFIG_IBM_NEW_EMAC_RGMII is not set
392# CONFIG_IBM_NEW_EMAC_TAH is not set
393# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
394# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
395# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
396# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
397# CONFIG_B44 is not set
398CONFIG_NETDEV_1000=y
399CONFIG_NETDEV_10000=y
400
401#
402# Wireless LAN
403#
404# CONFIG_WLAN_PRE80211 is not set
405# CONFIG_WLAN_80211 is not set
406# CONFIG_IWLWIFI_LEDS is not set
407# CONFIG_WAN is not set
408# CONFIG_PPP is not set
409# CONFIG_SLIP is not set
410# CONFIG_NETPOLL is not set
411# CONFIG_NET_POLL_CONTROLLER is not set
412# CONFIG_ISDN is not set
413
414#
415# Input device support
416#
417CONFIG_INPUT=y
418# CONFIG_INPUT_FF_MEMLESS is not set
419# CONFIG_INPUT_POLLDEV is not set
420
421#
422# Userland interfaces
423#
424CONFIG_INPUT_MOUSEDEV=y
425# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
426CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
427CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
428# CONFIG_INPUT_JOYDEV is not set
429# CONFIG_INPUT_EVDEV is not set
430# CONFIG_INPUT_EVBUG is not set
431
432#
433# Input Device Drivers
434#
435# CONFIG_INPUT_KEYBOARD is not set
436# CONFIG_INPUT_MOUSE is not set
437# CONFIG_INPUT_JOYSTICK is not set
438# CONFIG_INPUT_TABLET is not set
439# CONFIG_INPUT_TOUCHSCREEN is not set
440# CONFIG_INPUT_MISC is not set
441
442#
443# Hardware I/O ports
444#
445# CONFIG_SERIO is not set
446# CONFIG_GAMEPORT is not set
447
448#
449# Character devices
450#
451CONFIG_VT=y
452CONFIG_CONSOLE_TRANSLATIONS=y
453CONFIG_VT_CONSOLE=y
454CONFIG_HW_CONSOLE=y
455# CONFIG_VT_HW_CONSOLE_BINDING is not set
456# CONFIG_DEVKMEM is not set
457# CONFIG_SERIAL_NONSTANDARD is not set
458
459#
460# Serial drivers
461#
462# CONFIG_SERIAL_8250 is not set
463
464#
465# Non-8250 serial port support
466#
467CONFIG_SERIAL_IMX=y
468CONFIG_SERIAL_IMX_CONSOLE=y
469CONFIG_SERIAL_CORE=y
470CONFIG_SERIAL_CORE_CONSOLE=y
471CONFIG_UNIX98_PTYS=y
472# CONFIG_LEGACY_PTYS is not set
473# CONFIG_IPMI_HANDLER is not set
474# CONFIG_HW_RANDOM is not set
475# CONFIG_NVRAM is not set
476# CONFIG_R3964 is not set
477# CONFIG_RAW_DRIVER is not set
478# CONFIG_I2C is not set
479# CONFIG_SPI is not set
480CONFIG_ARCH_REQUIRE_GPIOLIB=y
481CONFIG_GPIOLIB=y
482
483#
484# I2C GPIO expanders:
485#
486
487#
488# PCI GPIO expanders:
489#
490
491#
492# SPI GPIO expanders:
493#
494# CONFIG_W1 is not set
495# CONFIG_POWER_SUPPLY is not set
496# CONFIG_HWMON is not set
497# CONFIG_THERMAL is not set
498# CONFIG_THERMAL_HWMON is not set
499# CONFIG_WATCHDOG is not set
500
501#
502# Sonics Silicon Backplane
503#
504CONFIG_SSB_POSSIBLE=y
505# CONFIG_SSB is not set
506
507#
508# Multifunction device drivers
509#
510# CONFIG_MFD_CORE is not set
511# CONFIG_MFD_SM501 is not set
512# CONFIG_MFD_ASIC3 is not set
513# CONFIG_HTC_EGPIO is not set
514# CONFIG_HTC_PASIC3 is not set
515# CONFIG_MFD_TMIO is not set
516# CONFIG_MFD_T7L66XB is not set
517# CONFIG_MFD_TC6387XB is not set
518# CONFIG_MFD_TC6393XB is not set
519# CONFIG_MFD_WM8400 is not set
520
521#
522# Multimedia devices
523#
524
525#
526# Multimedia core support
527#
528# CONFIG_VIDEO_DEV is not set
529# CONFIG_DVB_CORE is not set
530# CONFIG_VIDEO_MEDIA is not set
531
532#
533# Multimedia drivers
534#
535# CONFIG_DAB is not set
536
537#
538# Graphics support
539#
540# CONFIG_VGASTATE is not set
541# CONFIG_VIDEO_OUTPUT_CONTROL is not set
542# CONFIG_FB is not set
543# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
544
545#
546# Display device support
547#
548# CONFIG_DISPLAY_SUPPORT is not set
549
550#
551# Console display driver support
552#
553# CONFIG_VGA_CONSOLE is not set
554CONFIG_DUMMY_CONSOLE=y
555# CONFIG_SOUND is not set
556# CONFIG_HID_SUPPORT is not set
557# CONFIG_USB_SUPPORT is not set
558# CONFIG_MMC is not set
559# CONFIG_MEMSTICK is not set
560# CONFIG_ACCESSIBILITY is not set
561# CONFIG_NEW_LEDS is not set
562CONFIG_RTC_LIB=y
563# CONFIG_RTC_CLASS is not set
564# CONFIG_DMADEVICES is not set
565
566#
567# Voltage and Current regulators
568#
569# CONFIG_REGULATOR is not set
570# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
571# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
572# CONFIG_REGULATOR_BQ24022 is not set
573# CONFIG_UIO is not set
574
575#
576# File systems
577#
578# CONFIG_EXT2_FS is not set
579# CONFIG_EXT3_FS is not set
580# CONFIG_EXT4_FS is not set
581# CONFIG_REISERFS_FS is not set
582# CONFIG_JFS_FS is not set
583# CONFIG_FS_POSIX_ACL is not set
584CONFIG_FILE_LOCKING=y
585# CONFIG_XFS_FS is not set
586# CONFIG_OCFS2_FS is not set
587# CONFIG_DNOTIFY is not set
588# CONFIG_INOTIFY is not set
589# CONFIG_QUOTA is not set
590# CONFIG_AUTOFS_FS is not set
591# CONFIG_AUTOFS4_FS is not set
592# CONFIG_FUSE_FS is not set
593
594#
595# CD-ROM/DVD Filesystems
596#
597# CONFIG_ISO9660_FS is not set
598# CONFIG_UDF_FS is not set
599
600#
601# DOS/FAT/NT Filesystems
602#
603# CONFIG_MSDOS_FS is not set
604# CONFIG_VFAT_FS is not set
605# CONFIG_NTFS_FS is not set
606
607#
608# Pseudo filesystems
609#
610CONFIG_PROC_FS=y
611CONFIG_PROC_SYSCTL=y
612CONFIG_PROC_PAGE_MONITOR=y
613CONFIG_SYSFS=y
614# CONFIG_TMPFS is not set
615# CONFIG_HUGETLB_PAGE is not set
616# CONFIG_CONFIGFS_FS is not set
617
618#
619# Miscellaneous filesystems
620#
621# CONFIG_HFSPLUS_FS is not set
622# CONFIG_CRAMFS is not set
623# CONFIG_VXFS_FS is not set
624# CONFIG_MINIX_FS is not set
625# CONFIG_OMFS_FS is not set
626# CONFIG_HPFS_FS is not set
627# CONFIG_QNX4FS_FS is not set
628# CONFIG_ROMFS_FS is not set
629# CONFIG_SYSV_FS is not set
630# CONFIG_UFS_FS is not set
631CONFIG_NETWORK_FILESYSTEMS=y
632# CONFIG_NFS_FS is not set
633# CONFIG_NFSD is not set
634# CONFIG_SMB_FS is not set
635# CONFIG_CIFS is not set
636# CONFIG_NCP_FS is not set
637# CONFIG_CODA_FS is not set
638
639#
640# Partition Types
641#
642# CONFIG_PARTITION_ADVANCED is not set
643CONFIG_MSDOS_PARTITION=y
644# CONFIG_NLS is not set
645
646#
647# Kernel hacking
648#
649# CONFIG_PRINTK_TIME is not set
650# CONFIG_ENABLE_WARN_DEPRECATED is not set
651# CONFIG_ENABLE_MUST_CHECK is not set
652CONFIG_FRAME_WARN=1024
653# CONFIG_MAGIC_SYSRQ is not set
654# CONFIG_UNUSED_SYMBOLS is not set
655# CONFIG_DEBUG_FS is not set
656# CONFIG_HEADERS_CHECK is not set
657# CONFIG_DEBUG_KERNEL is not set
658# CONFIG_SLUB_DEBUG_ON is not set
659# CONFIG_SLUB_STATS is not set
660CONFIG_DEBUG_BUGVERBOSE=y
661CONFIG_DEBUG_MEMORY_INIT=y
662CONFIG_FRAME_POINTER=y
663# CONFIG_RCU_CPU_STALL_DETECTOR is not set
664# CONFIG_LATENCYTOP is not set
665# CONFIG_SYSCTL_SYSCALL_CHECK is not set
666CONFIG_NOP_TRACER=y
667CONFIG_HAVE_FTRACE=y
668CONFIG_HAVE_DYNAMIC_FTRACE=y
669# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
670# CONFIG_SAMPLES is not set
671CONFIG_HAVE_ARCH_KGDB=y
672# CONFIG_DEBUG_USER is not set
673
674#
675# Security options
676#
677# CONFIG_KEYS is not set
678# CONFIG_SECURITY is not set
679# CONFIG_SECURITYFS is not set
680# CONFIG_SECURITY_FILE_CAPABILITIES is not set
681CONFIG_CRYPTO=y
682
683#
684# Crypto core or helper
685#
686# CONFIG_CRYPTO_FIPS is not set
687# CONFIG_CRYPTO_MANAGER is not set
688# CONFIG_CRYPTO_NULL is not set
689# CONFIG_CRYPTO_CRYPTD is not set
690# CONFIG_CRYPTO_AUTHENC is not set
691
692#
693# Authenticated Encryption with Associated Data
694#
695# CONFIG_CRYPTO_CCM is not set
696# CONFIG_CRYPTO_GCM is not set
697# CONFIG_CRYPTO_SEQIV is not set
698
699#
700# Block modes
701#
702# CONFIG_CRYPTO_CBC is not set
703# CONFIG_CRYPTO_CTR is not set
704# CONFIG_CRYPTO_CTS is not set
705# CONFIG_CRYPTO_ECB is not set
706# CONFIG_CRYPTO_PCBC is not set
707
708#
709# Hash modes
710#
711# CONFIG_CRYPTO_HMAC is not set
712
713#
714# Digest
715#
716# CONFIG_CRYPTO_CRC32C is not set
717# CONFIG_CRYPTO_MD4 is not set
718# CONFIG_CRYPTO_MD5 is not set
719# CONFIG_CRYPTO_MICHAEL_MIC is not set
720# CONFIG_CRYPTO_RMD128 is not set
721# CONFIG_CRYPTO_RMD160 is not set
722# CONFIG_CRYPTO_RMD256 is not set
723# CONFIG_CRYPTO_RMD320 is not set
724# CONFIG_CRYPTO_SHA1 is not set
725# CONFIG_CRYPTO_SHA256 is not set
726# CONFIG_CRYPTO_SHA512 is not set
727# CONFIG_CRYPTO_TGR192 is not set
728# CONFIG_CRYPTO_WP512 is not set
729
730#
731# Ciphers
732#
733# CONFIG_CRYPTO_AES is not set
734# CONFIG_CRYPTO_ANUBIS is not set
735# CONFIG_CRYPTO_ARC4 is not set
736# CONFIG_CRYPTO_BLOWFISH is not set
737# CONFIG_CRYPTO_CAMELLIA is not set
738# CONFIG_CRYPTO_CAST5 is not set
739# CONFIG_CRYPTO_CAST6 is not set
740# CONFIG_CRYPTO_DES is not set
741# CONFIG_CRYPTO_FCRYPT is not set
742# CONFIG_CRYPTO_KHAZAD is not set
743# CONFIG_CRYPTO_SEED is not set
744# CONFIG_CRYPTO_SERPENT is not set
745# CONFIG_CRYPTO_TEA is not set
746# CONFIG_CRYPTO_TWOFISH is not set
747
748#
749# Compression
750#
751# CONFIG_CRYPTO_DEFLATE is not set
752# CONFIG_CRYPTO_LZO is not set
753
754#
755# Random Number Generation
756#
757# CONFIG_CRYPTO_ANSI_CPRNG is not set
758CONFIG_CRYPTO_HW=y
759
760#
761# Library routines
762#
763# CONFIG_CRC_CCITT is not set
764# CONFIG_CRC16 is not set
765# CONFIG_CRC_T10DIF is not set
766# CONFIG_CRC_ITU_T is not set
767# CONFIG_CRC32 is not set
768# CONFIG_CRC7 is not set
769# CONFIG_LIBCRC32C is not set
770CONFIG_PLIST=y
771CONFIG_HAS_IOMEM=y
772CONFIG_HAS_IOPORT=y
773CONFIG_HAS_DMA=y
diff --git a/arch/arm/mach-mx1/Kconfig b/arch/arm/mach-mx1/Kconfig
new file mode 100644
index 000000000000..2b59fc74784f
--- /dev/null
+++ b/arch/arm/mach-mx1/Kconfig
@@ -0,0 +1,14 @@
1if ARCH_MX1
2
3comment "MX1 Platforms"
4
5config MACH_MXLADS
6 bool
7
8config ARCH_MX1ADS
9 bool "MX1ADS platform"
10 select MACH_MXLADS
11 help
12 Say Y here if you are using Motorola MX1ADS/MXLADS boards
13
14endif
diff --git a/arch/arm/mach-mx1/Makefile b/arch/arm/mach-mx1/Makefile
new file mode 100644
index 000000000000..b969719011fa
--- /dev/null
+++ b/arch/arm/mach-mx1/Makefile
@@ -0,0 +1,10 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Object file lists.
6
7obj-y += generic.o clock.o devices.o
8
9# Specific board support
10obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o
diff --git a/arch/arm/mach-mx1/Makefile.boot b/arch/arm/mach-mx1/Makefile.boot
new file mode 100644
index 000000000000..8ed1492288a2
--- /dev/null
+++ b/arch/arm/mach-mx1/Makefile.boot
@@ -0,0 +1,4 @@
1 zreladdr-y := 0x08008000
2params_phys-y := 0x08000100
3initrd_phys-y := 0x08800000
4
diff --git a/arch/arm/mach-mx1/clock.c b/arch/arm/mach-mx1/clock.c
new file mode 100644
index 000000000000..4bcd1ece55f5
--- /dev/null
+++ b/arch/arm/mach-mx1/clock.c
@@ -0,0 +1,656 @@
1/*
2 * Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/math64.h>
22#include <linux/err.h>
23#include <linux/clk.h>
24#include <linux/io.h>
25
26#include <mach/clock.h>
27#include <mach/hardware.h>
28#include "crm_regs.h"
29
30static int _clk_enable(struct clk *clk)
31{
32 unsigned int reg;
33
34 reg = __raw_readl(clk->enable_reg);
35 reg |= 1 << clk->enable_shift;
36 __raw_writel(reg, clk->enable_reg);
37
38 return 0;
39}
40
41static void _clk_disable(struct clk *clk)
42{
43 unsigned int reg;
44
45 reg = __raw_readl(clk->enable_reg);
46 reg &= ~(1 << clk->enable_shift);
47 __raw_writel(reg, clk->enable_reg);
48}
49
50static int _clk_can_use_parent(const struct clk *clk_arr[], unsigned int size,
51 struct clk *parent)
52{
53 int i;
54
55 for (i = 0; i < size; i++)
56 if (parent == clk_arr[i])
57 return i;
58
59 return -EINVAL;
60}
61
62static unsigned long
63_clk_simple_round_rate(struct clk *clk, unsigned long rate, unsigned int limit)
64{
65 int div;
66 unsigned long parent_rate;
67
68 parent_rate = clk_get_rate(clk->parent);
69
70 div = parent_rate / rate;
71 if (parent_rate % rate)
72 div++;
73
74 if (div > limit)
75 div = limit;
76
77 return parent_rate / div;
78}
79
80static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate)
81{
82 return clk->parent->round_rate(clk->parent, rate);
83}
84
85static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
86{
87 return clk->parent->set_rate(clk->parent, rate);
88}
89
90/*
91 * get the system pll clock in Hz
92 *
93 * mfi + mfn / (mfd +1)
94 * f = 2 * f_ref * --------------------
95 * pd + 1
96 */
97static unsigned long mx1_decode_pll(unsigned int pll, u32 f_ref)
98{
99 unsigned long long ll;
100 unsigned long quot;
101
102 u32 mfi = (pll >> 10) & 0xf;
103 u32 mfn = pll & 0x3ff;
104 u32 mfd = (pll >> 16) & 0x3ff;
105 u32 pd = (pll >> 26) & 0xf;
106
107 mfi = mfi <= 5 ? 5 : mfi;
108
109 ll = 2 * (unsigned long long)f_ref *
110 ((mfi << 16) + (mfn << 16) / (mfd + 1));
111 quot = (pd + 1) * (1 << 16);
112 ll += quot / 2;
113 do_div(ll, quot);
114 return (unsigned long)ll;
115}
116
117static unsigned long clk16m_get_rate(struct clk *clk)
118{
119 return 16000000;
120}
121
122static struct clk clk16m = {
123 .name = "CLK16M",
124 .get_rate = clk16m_get_rate,
125 .enable = _clk_enable,
126 .enable_reg = CCM_CSCR,
127 .enable_shift = CCM_CSCR_OSC_EN_SHIFT,
128 .disable = _clk_disable,
129};
130
131/* in Hz */
132static unsigned long clk32_rate;
133
134static unsigned long clk32_get_rate(struct clk *clk)
135{
136 return clk32_rate;
137}
138
139static struct clk clk32 = {
140 .name = "CLK32",
141 .get_rate = clk32_get_rate,
142};
143
144static unsigned long clk32_premult_get_rate(struct clk *clk)
145{
146 return clk_get_rate(clk->parent) * 512;
147}
148
149static struct clk clk32_premult = {
150 .name = "CLK32_premultiplier",
151 .parent = &clk32,
152 .get_rate = clk32_premult_get_rate,
153};
154
155static const struct clk *prem_clk_clocks[] = {
156 &clk32_premult,
157 &clk16m,
158};
159
160static int prem_clk_set_parent(struct clk *clk, struct clk *parent)
161{
162 int i;
163 unsigned int reg = __raw_readl(CCM_CSCR);
164
165 i = _clk_can_use_parent(prem_clk_clocks, ARRAY_SIZE(prem_clk_clocks),
166 parent);
167
168 switch (i) {
169 case 0:
170 reg &= ~CCM_CSCR_SYSTEM_SEL;
171 break;
172 case 1:
173 reg |= CCM_CSCR_SYSTEM_SEL;
174 break;
175 default:
176 return i;
177 }
178
179 __raw_writel(reg, CCM_CSCR);
180
181 return 0;
182}
183
184static struct clk prem_clk = {
185 .name = "prem_clk",
186 .set_parent = prem_clk_set_parent,
187};
188
189static unsigned long system_clk_get_rate(struct clk *clk)
190{
191 return mx1_decode_pll(__raw_readl(CCM_SPCTL0),
192 clk_get_rate(clk->parent));
193}
194
195static struct clk system_clk = {
196 .name = "system_clk",
197 .parent = &prem_clk,
198 .get_rate = system_clk_get_rate,
199};
200
201static unsigned long mcu_clk_get_rate(struct clk *clk)
202{
203 return mx1_decode_pll(__raw_readl(CCM_MPCTL0),
204 clk_get_rate(clk->parent));
205}
206
207static struct clk mcu_clk = {
208 .name = "mcu_clk",
209 .parent = &clk32_premult,
210 .get_rate = mcu_clk_get_rate,
211};
212
213static unsigned long fclk_get_rate(struct clk *clk)
214{
215 unsigned long fclk = clk_get_rate(clk->parent);
216
217 if (__raw_readl(CCM_CSCR) & CCM_CSCR_PRESC)
218 fclk /= 2;
219
220 return fclk;
221}
222
223static struct clk fclk = {
224 .name = "fclk",
225 .parent = &mcu_clk,
226 .get_rate = fclk_get_rate,
227};
228
229/*
230 * get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA )
231 */
232static unsigned long hclk_get_rate(struct clk *clk)
233{
234 return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) &
235 CCM_CSCR_BCLK_MASK) >> CCM_CSCR_BCLK_OFFSET) + 1);
236}
237
238static unsigned long hclk_round_rate(struct clk *clk, unsigned long rate)
239{
240 return _clk_simple_round_rate(clk, rate, 16);
241}
242
243static int hclk_set_rate(struct clk *clk, unsigned long rate)
244{
245 unsigned int div;
246 unsigned int reg;
247 unsigned long parent_rate;
248
249 parent_rate = clk_get_rate(clk->parent);
250
251 div = parent_rate / rate;
252
253 if (div > 16 || div < 1 || ((parent_rate / div) != rate))
254 return -EINVAL;
255
256 div--;
257
258 reg = __raw_readl(CCM_CSCR);
259 reg &= ~CCM_CSCR_BCLK_MASK;
260 reg |= div << CCM_CSCR_BCLK_OFFSET;
261 __raw_writel(reg, CCM_CSCR);
262
263 return 0;
264}
265
266static struct clk hclk = {
267 .name = "hclk",
268 .parent = &system_clk,
269 .get_rate = hclk_get_rate,
270 .round_rate = hclk_round_rate,
271 .set_rate = hclk_set_rate,
272};
273
274static unsigned long clk48m_get_rate(struct clk *clk)
275{
276 return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) &
277 CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET) + 1);
278}
279
280static unsigned long clk48m_round_rate(struct clk *clk, unsigned long rate)
281{
282 return _clk_simple_round_rate(clk, rate, 8);
283}
284
285static int clk48m_set_rate(struct clk *clk, unsigned long rate)
286{
287 unsigned int div;
288 unsigned int reg;
289 unsigned long parent_rate;
290
291 parent_rate = clk_get_rate(clk->parent);
292
293 div = parent_rate / rate;
294
295 if (div > 8 || div < 1 || ((parent_rate / div) != rate))
296 return -EINVAL;
297
298 div--;
299
300 reg = __raw_readl(CCM_CSCR);
301 reg &= ~CCM_CSCR_USB_MASK;
302 reg |= div << CCM_CSCR_USB_OFFSET;
303 __raw_writel(reg, CCM_CSCR);
304
305 return 0;
306}
307
308static struct clk clk48m = {
309 .name = "CLK48M",
310 .parent = &system_clk,
311 .get_rate = clk48m_get_rate,
312 .round_rate = clk48m_round_rate,
313 .set_rate = clk48m_set_rate,
314};
315
316/*
317 * get peripheral clock 1 ( UART[12], Timer[12], PWM )
318 */
319static unsigned long perclk1_get_rate(struct clk *clk)
320{
321 return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
322 CCM_PCDR_PCLK1_MASK) >> CCM_PCDR_PCLK1_OFFSET) + 1);
323}
324
325static unsigned long perclk1_round_rate(struct clk *clk, unsigned long rate)
326{
327 return _clk_simple_round_rate(clk, rate, 16);
328}
329
330static int perclk1_set_rate(struct clk *clk, unsigned long rate)
331{
332 unsigned int div;
333 unsigned int reg;
334 unsigned long parent_rate;
335
336 parent_rate = clk_get_rate(clk->parent);
337
338 div = parent_rate / rate;
339
340 if (div > 16 || div < 1 || ((parent_rate / div) != rate))
341 return -EINVAL;
342
343 div--;
344
345 reg = __raw_readl(CCM_PCDR);
346 reg &= ~CCM_PCDR_PCLK1_MASK;
347 reg |= div << CCM_PCDR_PCLK1_OFFSET;
348 __raw_writel(reg, CCM_PCDR);
349
350 return 0;
351}
352
353/*
354 * get peripheral clock 2 ( LCD, SD, SPI[12] )
355 */
356static unsigned long perclk2_get_rate(struct clk *clk)
357{
358 return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
359 CCM_PCDR_PCLK2_MASK) >> CCM_PCDR_PCLK2_OFFSET) + 1);
360}
361
362static unsigned long perclk2_round_rate(struct clk *clk, unsigned long rate)
363{
364 return _clk_simple_round_rate(clk, rate, 16);
365}
366
367static int perclk2_set_rate(struct clk *clk, unsigned long rate)
368{
369 unsigned int div;
370 unsigned int reg;
371 unsigned long parent_rate;
372
373 parent_rate = clk_get_rate(clk->parent);
374
375 div = parent_rate / rate;
376
377 if (div > 16 || div < 1 || ((parent_rate / div) != rate))
378 return -EINVAL;
379
380 div--;
381
382 reg = __raw_readl(CCM_PCDR);
383 reg &= ~CCM_PCDR_PCLK2_MASK;
384 reg |= div << CCM_PCDR_PCLK2_OFFSET;
385 __raw_writel(reg, CCM_PCDR);
386
387 return 0;
388}
389
390/*
391 * get peripheral clock 3 ( SSI )
392 */
393static unsigned long perclk3_get_rate(struct clk *clk)
394{
395 return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
396 CCM_PCDR_PCLK3_MASK) >> CCM_PCDR_PCLK3_OFFSET) + 1);
397}
398
399static unsigned long perclk3_round_rate(struct clk *clk, unsigned long rate)
400{
401 return _clk_simple_round_rate(clk, rate, 128);
402}
403
404static int perclk3_set_rate(struct clk *clk, unsigned long rate)
405{
406 unsigned int div;
407 unsigned int reg;
408 unsigned long parent_rate;
409
410 parent_rate = clk_get_rate(clk->parent);
411
412 div = parent_rate / rate;
413
414 if (div > 128 || div < 1 || ((parent_rate / div) != rate))
415 return -EINVAL;
416
417 div--;
418
419 reg = __raw_readl(CCM_PCDR);
420 reg &= ~CCM_PCDR_PCLK3_MASK;
421 reg |= div << CCM_PCDR_PCLK3_OFFSET;
422 __raw_writel(reg, CCM_PCDR);
423
424 return 0;
425}
426
427static struct clk perclk[] = {
428 {
429 .name = "perclk",
430 .id = 0,
431 .parent = &system_clk,
432 .get_rate = perclk1_get_rate,
433 .round_rate = perclk1_round_rate,
434 .set_rate = perclk1_set_rate,
435 }, {
436 .name = "perclk",
437 .id = 1,
438 .parent = &system_clk,
439 .get_rate = perclk2_get_rate,
440 .round_rate = perclk2_round_rate,
441 .set_rate = perclk2_set_rate,
442 }, {
443 .name = "perclk",
444 .id = 2,
445 .parent = &system_clk,
446 .get_rate = perclk3_get_rate,
447 .round_rate = perclk3_round_rate,
448 .set_rate = perclk3_set_rate,
449 }
450};
451
452static const struct clk *clko_clocks[] = {
453 &perclk[0],
454 &hclk,
455 &clk48m,
456 &clk16m,
457 &prem_clk,
458 &fclk,
459};
460
461static int clko_set_parent(struct clk *clk, struct clk *parent)
462{
463 int i;
464 unsigned int reg;
465
466 i = _clk_can_use_parent(clko_clocks, ARRAY_SIZE(clko_clocks), parent);
467 if (i < 0)
468 return i;
469
470 reg = __raw_readl(CCM_CSCR) & ~CCM_CSCR_CLKO_MASK;
471 reg |= i << CCM_CSCR_CLKO_OFFSET;
472 __raw_writel(reg, CCM_CSCR);
473
474 if (clko_clocks[i]->set_rate && clko_clocks[i]->round_rate) {
475 clk->set_rate = _clk_parent_set_rate;
476 clk->round_rate = _clk_parent_round_rate;
477 } else {
478 clk->set_rate = NULL;
479 clk->round_rate = NULL;
480 }
481
482 return 0;
483}
484
485static struct clk clko_clk = {
486 .name = "clko_clk",
487 .set_parent = clko_set_parent,
488};
489
490static struct clk dma_clk = {
491 .name = "dma_clk",
492 .parent = &hclk,
493 .round_rate = _clk_parent_round_rate,
494 .set_rate = _clk_parent_set_rate,
495 .enable = _clk_enable,
496 .enable_reg = SCM_GCCR,
497 .enable_shift = SCM_GCCR_DMA_CLK_EN_OFFSET,
498 .disable = _clk_disable,
499};
500
501static struct clk csi_clk = {
502 .name = "csi_clk",
503 .parent = &hclk,
504 .round_rate = _clk_parent_round_rate,
505 .set_rate = _clk_parent_set_rate,
506 .enable = _clk_enable,
507 .enable_reg = SCM_GCCR,
508 .enable_shift = SCM_GCCR_CSI_CLK_EN_OFFSET,
509 .disable = _clk_disable,
510};
511
512static struct clk mma_clk = {
513 .name = "mma_clk",
514 .parent = &hclk,
515 .round_rate = _clk_parent_round_rate,
516 .set_rate = _clk_parent_set_rate,
517 .enable = _clk_enable,
518 .enable_reg = SCM_GCCR,
519 .enable_shift = SCM_GCCR_MMA_CLK_EN_OFFSET,
520 .disable = _clk_disable,
521};
522
523static struct clk usbd_clk = {
524 .name = "usbd_clk",
525 .parent = &clk48m,
526 .round_rate = _clk_parent_round_rate,
527 .set_rate = _clk_parent_set_rate,
528 .enable = _clk_enable,
529 .enable_reg = SCM_GCCR,
530 .enable_shift = SCM_GCCR_USBD_CLK_EN_OFFSET,
531 .disable = _clk_disable,
532};
533
534static struct clk gpt_clk = {
535 .name = "gpt_clk",
536 .parent = &perclk[0],
537 .round_rate = _clk_parent_round_rate,
538 .set_rate = _clk_parent_set_rate,
539};
540
541static struct clk uart_clk = {
542 .name = "uart_clk",
543 .parent = &perclk[0],
544 .round_rate = _clk_parent_round_rate,
545 .set_rate = _clk_parent_set_rate,
546};
547
548static struct clk i2c_clk = {
549 .name = "i2c_clk",
550 .parent = &hclk,
551 .round_rate = _clk_parent_round_rate,
552 .set_rate = _clk_parent_set_rate,
553};
554
555static struct clk spi_clk = {
556 .name = "spi_clk",
557 .parent = &perclk[1],
558 .round_rate = _clk_parent_round_rate,
559 .set_rate = _clk_parent_set_rate,
560};
561
562static struct clk sdhc_clk = {
563 .name = "sdhc_clk",
564 .parent = &perclk[1],
565 .round_rate = _clk_parent_round_rate,
566 .set_rate = _clk_parent_set_rate,
567};
568
569static struct clk lcdc_clk = {
570 .name = "lcdc_clk",
571 .parent = &perclk[1],
572 .round_rate = _clk_parent_round_rate,
573 .set_rate = _clk_parent_set_rate,
574};
575
576static struct clk mshc_clk = {
577 .name = "mshc_clk",
578 .parent = &hclk,
579 .round_rate = _clk_parent_round_rate,
580 .set_rate = _clk_parent_set_rate,
581};
582
583static struct clk ssi_clk = {
584 .name = "ssi_clk",
585 .parent = &perclk[2],
586 .round_rate = _clk_parent_round_rate,
587 .set_rate = _clk_parent_set_rate,
588};
589
590static struct clk rtc_clk = {
591 .name = "rtc_clk",
592 .parent = &clk32,
593};
594
595static struct clk *mxc_clks[] = {
596 &clk16m,
597 &clk32,
598 &clk32_premult,
599 &prem_clk,
600 &system_clk,
601 &mcu_clk,
602 &fclk,
603 &hclk,
604 &clk48m,
605 &perclk[0],
606 &perclk[1],
607 &perclk[2],
608 &clko_clk,
609 &dma_clk,
610 &csi_clk,
611 &mma_clk,
612 &usbd_clk,
613 &gpt_clk,
614 &uart_clk,
615 &i2c_clk,
616 &spi_clk,
617 &sdhc_clk,
618 &lcdc_clk,
619 &mshc_clk,
620 &ssi_clk,
621 &rtc_clk,
622};
623
624int __init mxc_clocks_init(unsigned long fref)
625{
626 struct clk **clkp;
627 unsigned int reg;
628
629 /* disable clocks we are able to */
630 __raw_writel(0, SCM_GCCR);
631
632 clk32_rate = fref;
633 reg = __raw_readl(CCM_CSCR);
634
635 /* detect clock reference for system PLL */
636 if (reg & CCM_CSCR_SYSTEM_SEL) {
637 prem_clk.parent = &clk16m;
638 } else {
639 /* ensure that oscillator is disabled */
640 reg &= ~(1 << CCM_CSCR_OSC_EN_SHIFT);
641 __raw_writel(reg, CCM_CSCR);
642 prem_clk.parent = &clk32_premult;
643 }
644
645 /* detect reference for CLKO */
646 reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET;
647 clko_clk.parent = (struct clk *)clko_clocks[reg];
648
649 for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++)
650 clk_register(*clkp);
651
652 clk_enable(&hclk);
653 clk_enable(&fclk);
654
655 return 0;
656}
diff --git a/arch/arm/mach-mx1/crm_regs.h b/arch/arm/mach-mx1/crm_regs.h
new file mode 100644
index 000000000000..22e866ff0c09
--- /dev/null
+++ b/arch/arm/mach-mx1/crm_regs.h
@@ -0,0 +1,55 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
4 *
5 * This file may be distributed under the terms of the GNU General
6 * Public License, version 2.
7 */
8
9#ifndef __ARCH_ARM_MACH_MX1_CRM_REGS_H__
10#define __ARCH_ARM_MACH_MX1_CRM_REGS_H__
11
12#define CCM_BASE IO_ADDRESS(CCM_BASE_ADDR)
13#define SCM_BASE IO_ADDRESS(SCM_BASE_ADDR)
14
15/* CCM register addresses */
16#define CCM_CSCR (CCM_BASE + 0x0)
17#define CCM_MPCTL0 (CCM_BASE + 0x4)
18#define CCM_MPCTL1 (CCM_BASE + 0x8)
19#define CCM_SPCTL0 (CCM_BASE + 0xC)
20#define CCM_SPCTL1 (CCM_BASE + 0x10)
21#define CCM_PCDR (CCM_BASE + 0x20)
22
23#define CCM_CSCR_CLKO_OFFSET 29
24#define CCM_CSCR_CLKO_MASK (0x7 << 29)
25#define CCM_CSCR_USB_OFFSET 26
26#define CCM_CSCR_USB_MASK (0x7 << 26)
27#define CCM_CSCR_SPLL_RESTART (1 << 22)
28#define CCM_CSCR_MPLL_RESTART (1 << 21)
29#define CCM_CSCR_OSC_EN_SHIFT 17
30#define CCM_CSCR_SYSTEM_SEL (1 << 16)
31#define CCM_CSCR_BCLK_OFFSET 10
32#define CCM_CSCR_BCLK_MASK (0xF << 10)
33#define CCM_CSCR_PRESC (1 << 15)
34#define CCM_CSCR_SPEN (1 << 1)
35#define CCM_CSCR_MPEN (1 << 0)
36
37#define CCM_PCDR_PCLK3_OFFSET 16
38#define CCM_PCDR_PCLK3_MASK (0x7F << 16)
39#define CCM_PCDR_PCLK2_OFFSET 4
40#define CCM_PCDR_PCLK2_MASK (0xF << 4)
41#define CCM_PCDR_PCLK1_OFFSET 0
42#define CCM_PCDR_PCLK1_MASK 0xF
43
44/* SCM register addresses */
45#define SCM_SIDR (SCM_BASE + 0x0)
46#define SCM_FMCR (SCM_BASE + 0x4)
47#define SCM_GPCR (SCM_BASE + 0x8)
48#define SCM_GCCR (SCM_BASE + 0xC)
49
50#define SCM_GCCR_DMA_CLK_EN_OFFSET 3
51#define SCM_GCCR_CSI_CLK_EN_OFFSET 2
52#define SCM_GCCR_MMA_CLK_EN_OFFSET 1
53#define SCM_GCCR_USBD_CLK_EN_OFFSET 0
54
55#endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */
diff --git a/arch/arm/mach-mx1/devices.c b/arch/arm/mach-mx1/devices.c
new file mode 100644
index 000000000000..ad4679b90870
--- /dev/null
+++ b/arch/arm/mach-mx1/devices.c
@@ -0,0 +1,260 @@
1/*
2 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
5 * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
19 * Boston, MA 02110-1301, USA.
20 */
21
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/platform_device.h>
25#include <linux/gpio.h>
26#include <mach/hardware.h>
27
28static struct resource imx_csi_resources[] = {
29 [0] = {
30 .start = 0x00224000,
31 .end = 0x00224010,
32 .flags = IORESOURCE_MEM,
33 },
34 [1] = {
35 .start = CSI_INT,
36 .end = CSI_INT,
37 .flags = IORESOURCE_IRQ,
38 },
39};
40
41static u64 imx_csi_dmamask = 0xffffffffUL;
42
43struct platform_device imx_csi_device = {
44 .name = "imx-csi",
45 .id = 0, /* This is used to put cameras on this interface */
46 .dev = {
47 .dma_mask = &imx_csi_dmamask,
48 .coherent_dma_mask = 0xffffffff,
49 },
50 .resource = imx_csi_resources,
51 .num_resources = ARRAY_SIZE(imx_csi_resources),
52};
53
54static struct resource imx_i2c_resources[] = {
55 [0] = {
56 .start = 0x00217000,
57 .end = 0x00217010,
58 .flags = IORESOURCE_MEM,
59 },
60 [1] = {
61 .start = I2C_INT,
62 .end = I2C_INT,
63 .flags = IORESOURCE_IRQ,
64 },
65};
66
67struct platform_device imx_i2c_device = {
68 .name = "imx-i2c",
69 .id = 0,
70 .resource = imx_i2c_resources,
71 .num_resources = ARRAY_SIZE(imx_i2c_resources),
72};
73
74static struct resource imx_uart1_resources[] = {
75 [0] = {
76 .start = UART1_BASE_ADDR,
77 .end = UART1_BASE_ADDR + 0xD0,
78 .flags = IORESOURCE_MEM,
79 },
80 [1] = {
81 .start = UART1_MINT_RX,
82 .end = UART1_MINT_RX,
83 .flags = IORESOURCE_IRQ,
84 },
85 [2] = {
86 .start = UART1_MINT_TX,
87 .end = UART1_MINT_TX,
88 .flags = IORESOURCE_IRQ,
89 },
90 [3] = {
91 .start = UART1_MINT_RTS,
92 .end = UART1_MINT_RTS,
93 .flags = IORESOURCE_IRQ,
94 },
95};
96
97struct platform_device imx_uart1_device = {
98 .name = "imx-uart",
99 .id = 0,
100 .num_resources = ARRAY_SIZE(imx_uart1_resources),
101 .resource = imx_uart1_resources,
102};
103
104static struct resource imx_uart2_resources[] = {
105 [0] = {
106 .start = UART2_BASE_ADDR,
107 .end = UART2_BASE_ADDR + 0xD0,
108 .flags = IORESOURCE_MEM,
109 },
110 [1] = {
111 .start = UART2_MINT_RX,
112 .end = UART2_MINT_RX,
113 .flags = IORESOURCE_IRQ,
114 },
115 [2] = {
116 .start = UART2_MINT_TX,
117 .end = UART2_MINT_TX,
118 .flags = IORESOURCE_IRQ,
119 },
120 [3] = {
121 .start = UART2_MINT_RTS,
122 .end = UART2_MINT_RTS,
123 .flags = IORESOURCE_IRQ,
124 },
125};
126
127struct platform_device imx_uart2_device = {
128 .name = "imx-uart",
129 .id = 1,
130 .num_resources = ARRAY_SIZE(imx_uart2_resources),
131 .resource = imx_uart2_resources,
132};
133
134static struct resource imx_rtc_resources[] = {
135 [0] = {
136 .start = 0x00204000,
137 .end = 0x00204024,
138 .flags = IORESOURCE_MEM,
139 },
140 [1] = {
141 .start = RTC_INT,
142 .end = RTC_INT,
143 .flags = IORESOURCE_IRQ,
144 },
145 [2] = {
146 .start = RTC_SAMINT,
147 .end = RTC_SAMINT,
148 .flags = IORESOURCE_IRQ,
149 },
150};
151
152struct platform_device imx_rtc_device = {
153 .name = "rtc-imx",
154 .id = 0,
155 .resource = imx_rtc_resources,
156 .num_resources = ARRAY_SIZE(imx_rtc_resources),
157};
158
159static struct resource imx_wdt_resources[] = {
160 [0] = {
161 .start = 0x00201000,
162 .end = 0x00201008,
163 .flags = IORESOURCE_MEM,
164 },
165 [1] = {
166 .start = WDT_INT,
167 .end = WDT_INT,
168 .flags = IORESOURCE_IRQ,
169 },
170};
171
172struct platform_device imx_wdt_device = {
173 .name = "imx-wdt",
174 .id = 0,
175 .resource = imx_wdt_resources,
176 .num_resources = ARRAY_SIZE(imx_wdt_resources),
177};
178
179static struct resource imx_usb_resources[] = {
180 [0] = {
181 .start = 0x00212000,
182 .end = 0x00212148,
183 .flags = IORESOURCE_MEM,
184 },
185 [1] = {
186 .start = USBD_INT0,
187 .end = USBD_INT0,
188 .flags = IORESOURCE_IRQ,
189 },
190 [2] = {
191 .start = USBD_INT1,
192 .end = USBD_INT1,
193 .flags = IORESOURCE_IRQ,
194 },
195 [3] = {
196 .start = USBD_INT2,
197 .end = USBD_INT2,
198 .flags = IORESOURCE_IRQ,
199 },
200 [4] = {
201 .start = USBD_INT3,
202 .end = USBD_INT3,
203 .flags = IORESOURCE_IRQ,
204 },
205 [5] = {
206 .start = USBD_INT4,
207 .end = USBD_INT4,
208 .flags = IORESOURCE_IRQ,
209 },
210 [6] = {
211 .start = USBD_INT5,
212 .end = USBD_INT5,
213 .flags = IORESOURCE_IRQ,
214 },
215 [7] = {
216 .start = USBD_INT6,
217 .end = USBD_INT6,
218 .flags = IORESOURCE_IRQ,
219 },
220};
221
222struct platform_device imx_usb_device = {
223 .name = "imx_udc",
224 .id = 0,
225 .num_resources = ARRAY_SIZE(imx_usb_resources),
226 .resource = imx_usb_resources,
227};
228
229/* GPIO port description */
230static struct mxc_gpio_port imx_gpio_ports[] = {
231 [0] = {
232 .chip.label = "gpio-0",
233 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR),
234 .irq = GPIO_INT_PORTA,
235 .virtual_irq_start = MXC_MAX_INT_LINES
236 },
237 [1] = {
238 .chip.label = "gpio-1",
239 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
240 .irq = GPIO_INT_PORTB,
241 .virtual_irq_start = MXC_MAX_INT_LINES + 32
242 },
243 [2] = {
244 .chip.label = "gpio-2",
245 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
246 .irq = GPIO_INT_PORTC,
247 .virtual_irq_start = MXC_MAX_INT_LINES + 64
248 },
249 [3] = {
250 .chip.label = "gpio-3",
251 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
252 .irq = GPIO_INT_PORTD,
253 .virtual_irq_start = MXC_MAX_INT_LINES + 96
254 }
255};
256
257int __init mxc_register_gpios(void)
258{
259 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
260}
diff --git a/arch/arm/mach-mx1/devices.h b/arch/arm/mach-mx1/devices.h
new file mode 100644
index 000000000000..0da5d7cce3a2
--- /dev/null
+++ b/arch/arm/mach-mx1/devices.h
@@ -0,0 +1,7 @@
1extern struct platform_device imx_csi_device;
2extern struct platform_device imx_i2c_device;
3extern struct platform_device imx_uart1_device;
4extern struct platform_device imx_uart2_device;
5extern struct platform_device imx_rtc_device;
6extern struct platform_device imx_wdt_device;
7extern struct platform_device imx_usb_device;
diff --git a/arch/arm/mach-mx1/generic.c b/arch/arm/mach-mx1/generic.c
new file mode 100644
index 000000000000..0dec6f300ffc
--- /dev/null
+++ b/arch/arm/mach-mx1/generic.c
@@ -0,0 +1,43 @@
1/*
2 * author: Sascha Hauer
3 * Created: april 20th, 2004
4 * Copyright: Synertronixx GmbH
5 *
6 * Common code for i.MX machines
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23#include <linux/kernel.h>
24#include <linux/init.h>
25#include <linux/io.h>
26
27#include <asm/mach/map.h>
28
29#include <mach/hardware.h>
30
31static struct map_desc imx_io_desc[] __initdata = {
32 {
33 .virtual = IMX_IO_BASE,
34 .pfn = __phys_to_pfn(IMX_IO_PHYS),
35 .length = IMX_IO_SIZE,
36 .type = MT_DEVICE
37 }
38};
39
40void __init mxc_map_io(void)
41{
42 iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
43}
diff --git a/arch/arm/mach-mx1/mx1ads.c b/arch/arm/mach-mx1/mx1ads.c
new file mode 100644
index 000000000000..2e4b185fe4a9
--- /dev/null
+++ b/arch/arm/mach-mx1/mx1ads.c
@@ -0,0 +1,148 @@
1/*
2 * arch/arm/mach-imx/mx1ads.c
3 *
4 * Initially based on:
5 * linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c
6 * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de>
7 *
8 * 2004 (c) MontaVista Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/mtd/physmap.h>
19
20#include <asm/mach-types.h>
21#include <asm/mach/arch.h>
22#include <asm/mach/time.h>
23
24#include <mach/hardware.h>
25#include <mach/common.h>
26#include <mach/imx-uart.h>
27#include <mach/iomux-mx1-mx2.h>
28#include "devices.h"
29
30/*
31 * UARTs platform data
32 */
33static int mxc_uart1_pins[] = {
34 PC9_PF_UART1_CTS,
35 PC10_PF_UART1_RTS,
36 PC11_PF_UART1_TXD,
37 PC12_PF_UART1_RXD,
38};
39
40static int uart1_mxc_init(struct platform_device *pdev)
41{
42 return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
43 ARRAY_SIZE(mxc_uart1_pins), "UART1");
44}
45
46static int uart1_mxc_exit(struct platform_device *pdev)
47{
48 mxc_gpio_release_multiple_pins(mxc_uart1_pins,
49 ARRAY_SIZE(mxc_uart1_pins));
50 return 0;
51}
52
53static int mxc_uart2_pins[] = {
54 PB28_PF_UART2_CTS,
55 PB29_PF_UART2_RTS,
56 PB30_PF_UART2_TXD,
57 PB31_PF_UART2_RXD,
58};
59
60static int uart2_mxc_init(struct platform_device *pdev)
61{
62 return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
63 ARRAY_SIZE(mxc_uart2_pins), "UART2");
64}
65
66static int uart2_mxc_exit(struct platform_device *pdev)
67{
68 mxc_gpio_release_multiple_pins(mxc_uart2_pins,
69 ARRAY_SIZE(mxc_uart2_pins));
70 return 0;
71}
72
73static struct imxuart_platform_data uart_pdata[] = {
74 {
75 .init = uart1_mxc_init,
76 .exit = uart1_mxc_exit,
77 .flags = IMXUART_HAVE_RTSCTS,
78 }, {
79 .init = uart2_mxc_init,
80 .exit = uart2_mxc_exit,
81 .flags = IMXUART_HAVE_RTSCTS,
82 },
83};
84
85/*
86 * Physmap flash
87 */
88
89static struct physmap_flash_data mx1ads_flash_data = {
90 .width = 4, /* bankwidth in bytes */
91};
92
93static struct resource flash_resource = {
94 .start = IMX_CS0_PHYS,
95 .end = IMX_CS0_PHYS + SZ_32M - 1,
96 .flags = IORESOURCE_MEM,
97};
98
99static struct platform_device flash_device = {
100 .name = "physmap-flash",
101 .id = 0,
102 .resource = &flash_resource,
103 .num_resources = 1,
104};
105
106/*
107 * Board init
108 */
109static void __init mx1ads_init(void)
110{
111 /* UART */
112 mxc_register_device(&imx_uart1_device, &uart_pdata[0]);
113 mxc_register_device(&imx_uart2_device, &uart_pdata[1]);
114
115 /* Physmap flash */
116 mxc_register_device(&flash_device, &mx1ads_flash_data);
117}
118
119static void __init mx1ads_timer_init(void)
120{
121 mxc_clocks_init(32000);
122 mxc_timer_init("gpt_clk");
123}
124
125struct sys_timer mx1ads_timer = {
126 .init = mx1ads_timer_init,
127};
128
129MACHINE_START(MX1ADS, "Freescale MX1ADS")
130 /* Maintainer: Sascha Hauer, Pengutronix */
131 .phys_io = IMX_IO_PHYS,
132 .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc,
133 .boot_params = PHYS_OFFSET + 0x100,
134 .map_io = mxc_map_io,
135 .init_irq = mxc_init_irq,
136 .timer = &mx1ads_timer,
137 .init_machine = mx1ads_init,
138MACHINE_END
139
140MACHINE_START(MXLADS, "Freescale MXLADS")
141 .phys_io = IMX_IO_PHYS,
142 .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc,
143 .boot_params = PHYS_OFFSET + 0x100,
144 .map_io = mxc_map_io,
145 .init_irq = mxc_init_irq,
146 .timer = &mx1ads_timer,
147 .init_machine = mx1ads_init,
148MACHINE_END
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
index 092e09baeefa..0bad86527743 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-mx2/devices.c
@@ -205,6 +205,25 @@ struct platform_device mxc_w1_master_device = {
205 .resource = mxc_w1_master_resources, 205 .resource = mxc_w1_master_resources,
206}; 206};
207 207
208static struct resource mxc_nand_resources[] = {
209 {
210 .start = NFC_BASE_ADDR,
211 .end = NFC_BASE_ADDR + 0xfff,
212 .flags = IORESOURCE_MEM
213 }, {
214 .start = MXC_INT_NANDFC,
215 .end = MXC_INT_NANDFC,
216 .flags = IORESOURCE_IRQ
217 },
218};
219
220struct platform_device mxc_nand_device = {
221 .name = "mxc_nand",
222 .id = 0,
223 .num_resources = ARRAY_SIZE(mxc_nand_resources),
224 .resource = mxc_nand_resources,
225};
226
208/* GPIO port description */ 227/* GPIO port description */
209static struct mxc_gpio_port imx_gpio_ports[] = { 228static struct mxc_gpio_port imx_gpio_ports[] = {
210 [0] = { 229 [0] = {
diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h
index 5683c4574325..1e8cb577a642 100644
--- a/arch/arm/mach-mx2/devices.h
+++ b/arch/arm/mach-mx2/devices.h
@@ -13,3 +13,4 @@ extern struct platform_device mxc_uart_device3;
13extern struct platform_device mxc_uart_device4; 13extern struct platform_device mxc_uart_device4;
14extern struct platform_device mxc_uart_device5; 14extern struct platform_device mxc_uart_device5;
15extern struct platform_device mxc_w1_master_device; 15extern struct platform_device mxc_w1_master_device;
16extern struct platform_device mxc_nand_device;
diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mx27ads.c
index 56e22d3ca075..a06497674436 100644
--- a/arch/arm/mach-mx2/mx27ads.c
+++ b/arch/arm/mach-mx2/mx27ads.c
@@ -68,15 +68,14 @@ static int mxc_uart0_pins[] = {
68static int uart_mxc_port0_init(struct platform_device *pdev) 68static int uart_mxc_port0_init(struct platform_device *pdev)
69{ 69{
70 return mxc_gpio_setup_multiple_pins(mxc_uart0_pins, 70 return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
71 ARRAY_SIZE(mxc_uart0_pins), 71 ARRAY_SIZE(mxc_uart0_pins), "UART0");
72 MXC_GPIO_ALLOC_MODE_NORMAL, "UART0");
73} 72}
74 73
75static int uart_mxc_port0_exit(struct platform_device *pdev) 74static int uart_mxc_port0_exit(struct platform_device *pdev)
76{ 75{
77 return mxc_gpio_setup_multiple_pins(mxc_uart0_pins, 76 mxc_gpio_release_multiple_pins(mxc_uart0_pins,
78 ARRAY_SIZE(mxc_uart0_pins), 77 ARRAY_SIZE(mxc_uart0_pins));
79 MXC_GPIO_ALLOC_MODE_RELEASE, "UART0"); 78 return 0;
80} 79}
81 80
82static int mxc_uart1_pins[] = { 81static int mxc_uart1_pins[] = {
@@ -89,15 +88,14 @@ static int mxc_uart1_pins[] = {
89static int uart_mxc_port1_init(struct platform_device *pdev) 88static int uart_mxc_port1_init(struct platform_device *pdev)
90{ 89{
91 return mxc_gpio_setup_multiple_pins(mxc_uart1_pins, 90 return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
92 ARRAY_SIZE(mxc_uart1_pins), 91 ARRAY_SIZE(mxc_uart1_pins), "UART1");
93 MXC_GPIO_ALLOC_MODE_NORMAL, "UART1");
94} 92}
95 93
96static int uart_mxc_port1_exit(struct platform_device *pdev) 94static int uart_mxc_port1_exit(struct platform_device *pdev)
97{ 95{
98 return mxc_gpio_setup_multiple_pins(mxc_uart1_pins, 96 mxc_gpio_setup_release_pins(mxc_uart1_pins,
99 ARRAY_SIZE(mxc_uart1_pins), 97 ARRAY_SIZE(mxc_uart1_pins));
100 MXC_GPIO_ALLOC_MODE_RELEASE, "UART1"); 98 return 0;
101} 99}
102 100
103static int mxc_uart2_pins[] = { 101static int mxc_uart2_pins[] = {
@@ -110,15 +108,14 @@ static int mxc_uart2_pins[] = {
110static int uart_mxc_port2_init(struct platform_device *pdev) 108static int uart_mxc_port2_init(struct platform_device *pdev)
111{ 109{
112 return mxc_gpio_setup_multiple_pins(mxc_uart2_pins, 110 return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
113 ARRAY_SIZE(mxc_uart2_pins), 111 ARRAY_SIZE(mxc_uart2_pins), "UART2");
114 MXC_GPIO_ALLOC_MODE_NORMAL, "UART2");
115} 112}
116 113
117static int uart_mxc_port2_exit(struct platform_device *pdev) 114static int uart_mxc_port2_exit(struct platform_device *pdev)
118{ 115{
119 return mxc_gpio_setup_multiple_pins(mxc_uart2_pins, 116 mxc_gpio_release_multiple_pins(mxc_uart2_pins,
120 ARRAY_SIZE(mxc_uart2_pins), 117 ARRAY_SIZE(mxc_uart2_pins));
121 MXC_GPIO_ALLOC_MODE_RELEASE, "UART2"); 118 return 0;
122} 119}
123 120
124static int mxc_uart3_pins[] = { 121static int mxc_uart3_pins[] = {
@@ -131,15 +128,13 @@ static int mxc_uart3_pins[] = {
131static int uart_mxc_port3_init(struct platform_device *pdev) 128static int uart_mxc_port3_init(struct platform_device *pdev)
132{ 129{
133 return mxc_gpio_setup_multiple_pins(mxc_uart3_pins, 130 return mxc_gpio_setup_multiple_pins(mxc_uart3_pins,
134 ARRAY_SIZE(mxc_uart3_pins), 131 ARRAY_SIZE(mxc_uart3_pins), "UART3");
135 MXC_GPIO_ALLOC_MODE_NORMAL, "UART3");
136} 132}
137 133
138static int uart_mxc_port3_exit(struct platform_device *pdev) 134static int uart_mxc_port3_exit(struct platform_device *pdev)
139{ 135{
140 return mxc_gpio_setup_multiple_pins(mxc_uart3_pins, 136 mxc_gpio_release_multiple_pins(mxc_uart3_pins,
141 ARRAY_SIZE(mxc_uart3_pins), 137 ARRAY_SIZE(mxc_uart3_pins));
142 MXC_GPIO_ALLOC_MODE_RELEASE, "UART3");
143} 138}
144 139
145static int mxc_uart4_pins[] = { 140static int mxc_uart4_pins[] = {
@@ -152,15 +147,14 @@ static int mxc_uart4_pins[] = {
152static int uart_mxc_port4_init(struct platform_device *pdev) 147static int uart_mxc_port4_init(struct platform_device *pdev)
153{ 148{
154 return mxc_gpio_setup_multiple_pins(mxc_uart4_pins, 149 return mxc_gpio_setup_multiple_pins(mxc_uart4_pins,
155 ARRAY_SIZE(mxc_uart4_pins), 150 ARRAY_SIZE(mxc_uart4_pins), "UART4");
156 MXC_GPIO_ALLOC_MODE_NORMAL, "UART4");
157} 151}
158 152
159static int uart_mxc_port4_exit(struct platform_device *pdev) 153static int uart_mxc_port4_exit(struct platform_device *pdev)
160{ 154{
161 return mxc_gpio_setup_multiple_pins(mxc_uart4_pins, 155 mxc_gpio_release_multiple_pins(mxc_uart4_pins,
162 ARRAY_SIZE(mxc_uart4_pins), 156 ARRAY_SIZE(mxc_uart4_pins));
163 MXC_GPIO_ALLOC_MODE_RELEASE, "UART4"); 157 return 0;
164} 158}
165 159
166static int mxc_uart5_pins[] = { 160static int mxc_uart5_pins[] = {
@@ -173,15 +167,14 @@ static int mxc_uart5_pins[] = {
173static int uart_mxc_port5_init(struct platform_device *pdev) 167static int uart_mxc_port5_init(struct platform_device *pdev)
174{ 168{
175 return mxc_gpio_setup_multiple_pins(mxc_uart5_pins, 169 return mxc_gpio_setup_multiple_pins(mxc_uart5_pins,
176 ARRAY_SIZE(mxc_uart5_pins), 170 ARRAY_SIZE(mxc_uart5_pins), "UART5");
177 MXC_GPIO_ALLOC_MODE_NORMAL, "UART5");
178} 171}
179 172
180static int uart_mxc_port5_exit(struct platform_device *pdev) 173static int uart_mxc_port5_exit(struct platform_device *pdev)
181{ 174{
182 return mxc_gpio_setup_multiple_pins(mxc_uart5_pins, 175 mxc_gpio_release_multiple_pins(mxc_uart5_pins,
183 ARRAY_SIZE(mxc_uart5_pins), 176 ARRAY_SIZE(mxc_uart5_pins));
184 MXC_GPIO_ALLOC_MODE_RELEASE, "UART5"); 177 return 0;
185} 178}
186 179
187static struct platform_device *platform_devices[] __initdata = { 180static struct platform_device *platform_devices[] __initdata = {
@@ -212,15 +205,13 @@ static int mxc_fec_pins[] = {
212static void gpio_fec_active(void) 205static void gpio_fec_active(void)
213{ 206{
214 mxc_gpio_setup_multiple_pins(mxc_fec_pins, 207 mxc_gpio_setup_multiple_pins(mxc_fec_pins,
215 ARRAY_SIZE(mxc_fec_pins), 208 ARRAY_SIZE(mxc_fec_pins), "FEC");
216 MXC_GPIO_ALLOC_MODE_NORMAL, "FEC");
217} 209}
218 210
219static void gpio_fec_inactive(void) 211static void gpio_fec_inactive(void)
220{ 212{
221 mxc_gpio_setup_multiple_pins(mxc_fec_pins, 213 mxc_gpio_release_multiple_pins(mxc_fec_pins,
222 ARRAY_SIZE(mxc_fec_pins), 214 ARRAY_SIZE(mxc_fec_pins));
223 MXC_GPIO_ALLOC_MODE_RELEASE, "FEC");
224} 215}
225 216
226static struct imxuart_platform_data uart_pdata[] = { 217static struct imxuart_platform_data uart_pdata[] = {
diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/pcm038.c
index ac516b1d3f77..dfd4156da7d5 100644
--- a/arch/arm/mach-mx2/pcm038.c
+++ b/arch/arm/mach-mx2/pcm038.c
@@ -19,6 +19,7 @@
19 19
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/mtd/physmap.h> 21#include <linux/mtd/physmap.h>
22#include <linux/mtd/plat-ram.h>
22#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
23#include <asm/mach-types.h> 24#include <asm/mach-types.h>
24#include <mach/common.h> 25#include <mach/common.h>
@@ -27,10 +28,36 @@
27#include <asm/mach/time.h> 28#include <asm/mach/time.h>
28#include <mach/imx-uart.h> 29#include <mach/imx-uart.h>
29#include <mach/board-pcm038.h> 30#include <mach/board-pcm038.h>
31#include <mach/mxc_nand.h>
30 32
31#include "devices.h" 33#include "devices.h"
32 34
33/* 35/*
36 * Phytec's PCM038 comes with 2MiB battery buffered SRAM,
37 * 16 bit width
38 */
39
40static struct platdata_mtd_ram pcm038_sram_data = {
41 .bankwidth = 2,
42};
43
44static struct resource pcm038_sram_resource = {
45 .start = CS1_BASE_ADDR,
46 .end = CS1_BASE_ADDR + 512 * 1024 - 1,
47 .flags = IORESOURCE_MEM,
48};
49
50static struct platform_device pcm038_sram_mtd_device = {
51 .name = "mtd-ram",
52 .id = 0,
53 .dev = {
54 .platform_data = &pcm038_sram_data,
55 },
56 .num_resources = 1,
57 .resource = &pcm038_sram_resource,
58};
59
60/*
34 * Phytec's phyCORE-i.MX27 comes with 32MiB flash, 61 * Phytec's phyCORE-i.MX27 comes with 32MiB flash,
35 * 16 bit width 62 * 16 bit width
36 */ 63 */
@@ -64,15 +91,14 @@ static int mxc_uart0_pins[] = {
64static int uart_mxc_port0_init(struct platform_device *pdev) 91static int uart_mxc_port0_init(struct platform_device *pdev)
65{ 92{
66 return mxc_gpio_setup_multiple_pins(mxc_uart0_pins, 93 return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
67 ARRAY_SIZE(mxc_uart0_pins), 94 ARRAY_SIZE(mxc_uart0_pins), "UART0");
68 MXC_GPIO_ALLOC_MODE_NORMAL, "UART0");
69} 95}
70 96
71static int uart_mxc_port0_exit(struct platform_device *pdev) 97static int uart_mxc_port0_exit(struct platform_device *pdev)
72{ 98{
73 return mxc_gpio_setup_multiple_pins(mxc_uart0_pins, 99 mxc_gpio_release_multiple_pins(mxc_uart0_pins,
74 ARRAY_SIZE(mxc_uart0_pins), 100 ARRAY_SIZE(mxc_uart0_pins));
75 MXC_GPIO_ALLOC_MODE_RELEASE, "UART0"); 101 return 0;
76} 102}
77 103
78static int mxc_uart1_pins[] = { 104static int mxc_uart1_pins[] = {
@@ -85,15 +111,14 @@ static int mxc_uart1_pins[] = {
85static int uart_mxc_port1_init(struct platform_device *pdev) 111static int uart_mxc_port1_init(struct platform_device *pdev)
86{ 112{
87 return mxc_gpio_setup_multiple_pins(mxc_uart1_pins, 113 return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
88 ARRAY_SIZE(mxc_uart1_pins), 114 ARRAY_SIZE(mxc_uart1_pins), "UART1");
89 MXC_GPIO_ALLOC_MODE_NORMAL, "UART1");
90} 115}
91 116
92static int uart_mxc_port1_exit(struct platform_device *pdev) 117static int uart_mxc_port1_exit(struct platform_device *pdev)
93{ 118{
94 return mxc_gpio_setup_multiple_pins(mxc_uart1_pins, 119 mxc_gpio_release_multiple_pins(mxc_uart1_pins,
95 ARRAY_SIZE(mxc_uart1_pins), 120 ARRAY_SIZE(mxc_uart1_pins));
96 MXC_GPIO_ALLOC_MODE_RELEASE, "UART1"); 121 return 0;
97} 122}
98 123
99static int mxc_uart2_pins[] = { PE10_PF_UART3_CTS, 124static int mxc_uart2_pins[] = { PE10_PF_UART3_CTS,
@@ -104,15 +129,14 @@ static int mxc_uart2_pins[] = { PE10_PF_UART3_CTS,
104static int uart_mxc_port2_init(struct platform_device *pdev) 129static int uart_mxc_port2_init(struct platform_device *pdev)
105{ 130{
106 return mxc_gpio_setup_multiple_pins(mxc_uart2_pins, 131 return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
107 ARRAY_SIZE(mxc_uart2_pins), 132 ARRAY_SIZE(mxc_uart2_pins), "UART2");
108 MXC_GPIO_ALLOC_MODE_NORMAL, "UART2");
109} 133}
110 134
111static int uart_mxc_port2_exit(struct platform_device *pdev) 135static int uart_mxc_port2_exit(struct platform_device *pdev)
112{ 136{
113 return mxc_gpio_setup_multiple_pins(mxc_uart2_pins, 137 mxc_gpio_release_multiple_pins(mxc_uart2_pins,
114 ARRAY_SIZE(mxc_uart2_pins), 138 ARRAY_SIZE(mxc_uart2_pins));
115 MXC_GPIO_ALLOC_MODE_RELEASE, "UART2"); 139 return 0;
116} 140}
117 141
118static struct imxuart_platform_data uart_pdata[] = { 142static struct imxuart_platform_data uart_pdata[] = {
@@ -155,30 +179,46 @@ static int mxc_fec_pins[] = {
155static void gpio_fec_active(void) 179static void gpio_fec_active(void)
156{ 180{
157 mxc_gpio_setup_multiple_pins(mxc_fec_pins, 181 mxc_gpio_setup_multiple_pins(mxc_fec_pins,
158 ARRAY_SIZE(mxc_fec_pins), 182 ARRAY_SIZE(mxc_fec_pins), "FEC");
159 MXC_GPIO_ALLOC_MODE_NORMAL, "FEC");
160} 183}
161 184
162static void gpio_fec_inactive(void) 185static void gpio_fec_inactive(void)
163{ 186{
164 mxc_gpio_setup_multiple_pins(mxc_fec_pins, 187 mxc_gpio_release_multiple_pins(mxc_fec_pins,
165 ARRAY_SIZE(mxc_fec_pins), 188 ARRAY_SIZE(mxc_fec_pins));
166 MXC_GPIO_ALLOC_MODE_RELEASE, "FEC");
167} 189}
168 190
191static struct mxc_nand_platform_data pcm038_nand_board_info = {
192 .width = 1,
193 .hw_ecc = 1,
194};
195
169static struct platform_device *platform_devices[] __initdata = { 196static struct platform_device *platform_devices[] __initdata = {
170 &pcm038_nor_mtd_device, 197 &pcm038_nor_mtd_device,
171 &mxc_w1_master_device, 198 &mxc_w1_master_device,
199 &pcm038_sram_mtd_device,
172}; 200};
173 201
202/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and
203 * setup other stuffs to access the sram. */
204static void __init pcm038_init_sram(void)
205{
206 __raw_writel(0x0000d843, CSCR_U(1));
207 __raw_writel(0x22252521, CSCR_L(1));
208 __raw_writel(0x22220a00, CSCR_A(1));
209}
210
174static void __init pcm038_init(void) 211static void __init pcm038_init(void)
175{ 212{
176 gpio_fec_active(); 213 gpio_fec_active();
214 pcm038_init_sram();
177 215
178 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); 216 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
179 mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); 217 mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
180 mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); 218 mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
219
181 mxc_gpio_mode(PE16_AF_RTCK); /* OWIRE */ 220 mxc_gpio_mode(PE16_AF_RTCK); /* OWIRE */
221 mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info);
182 222
183 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 223 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
184 224
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index db9431dee1b4..e79659e8176e 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -21,5 +21,19 @@ config MACH_MX31LITE
21 Include support for MX31 LITEKIT platform. This includes specific 21 Include support for MX31 LITEKIT platform. This includes specific
22 configurations for the board and its peripherals. 22 configurations for the board and its peripherals.
23 23
24config MACH_MX31_3DS
25 bool "Support MX31PDK (3DS)"
26 default n
27 help
28 Include support for MX31PDK (3DS) platform. This includes specific
29 configurations for the board and its peripherals.
30
31config MACH_MX31MOBOARD
32 bool "Support mx31moboard platforms (EPFL Mobots group)"
33 default n
34 help
35 Include support for mx31moboard platform. This includes specific
36 configurations for the board and its peripherals.
37
24endmenu 38endmenu
25 39
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 8b21abb71fb0..5a151540fe83 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -8,3 +8,5 @@ obj-y := mm.o clock.o devices.o iomux.o
8obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o 8obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o
9obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o 9obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o
10obj-$(CONFIG_MACH_PCM037) += pcm037.o 10obj-$(CONFIG_MACH_PCM037) += pcm037.o
11obj-$(CONFIG_MACH_MX31_3DS) += mx31pdk.o
12obj-$(CONFIG_MACH_MX31MOBOARD) += mx31moboard.o
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index 12b3e3c00460..3e61ff4646fe 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -160,3 +160,22 @@ struct platform_device mxc_w1_master_device = {
160 .num_resources = ARRAY_SIZE(mxc_w1_master_resources), 160 .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
161 .resource = mxc_w1_master_resources, 161 .resource = mxc_w1_master_resources,
162}; 162};
163
164static struct resource mxc_nand_resources[] = {
165 {
166 .start = NFC_BASE_ADDR,
167 .end = NFC_BASE_ADDR + 0xfff,
168 .flags = IORESOURCE_MEM
169 }, {
170 .start = MXC_INT_NANDFC,
171 .end = MXC_INT_NANDFC,
172 .flags = IORESOURCE_IRQ
173 },
174};
175
176struct platform_device mxc_nand_device = {
177 .name = "mxc_nand",
178 .id = 0,
179 .num_resources = ARRAY_SIZE(mxc_nand_resources),
180 .resource = mxc_nand_resources,
181};
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index cb1459c7c960..9949ef4e0694 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -5,3 +5,4 @@ extern struct platform_device mxc_uart_device2;
5extern struct platform_device mxc_uart_device3; 5extern struct platform_device mxc_uart_device3;
6extern struct platform_device mxc_uart_device4; 6extern struct platform_device mxc_uart_device4;
7extern struct platform_device mxc_w1_master_device; 7extern struct platform_device mxc_w1_master_device;
8extern struct platform_device mxc_nand_device;
diff --git a/arch/arm/mach-mx3/iomux.c b/arch/arm/mach-mx3/iomux.c
index 6e664be8cc13..7a5088b519a8 100644
--- a/arch/arm/mach-mx3/iomux.c
+++ b/arch/arm/mach-mx3/iomux.c
@@ -74,17 +74,18 @@ void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
74 u32 field, l; 74 u32 field, l;
75 void __iomem *reg; 75 void __iomem *reg;
76 76
77 reg = IOMUXSW_PAD_CTL + (pin + 2) / 3; 77 pin &= IOMUX_PADNUM_MASK;
78 reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
78 field = (pin + 2) % 3; 79 field = (pin + 2) % 3;
79 80
80 pr_debug("%s: reg offset = 0x%x field = %d\n", 81 pr_debug("%s: reg offset = 0x%x, field = %d\n",
81 __func__, (pin + 2) / 3, field); 82 __func__, (pin + 2) / 3, field);
82 83
83 spin_lock(&gpio_mux_lock); 84 spin_lock(&gpio_mux_lock);
84 85
85 l = __raw_readl(reg); 86 l = __raw_readl(reg);
86 l &= ~(0x1ff << (field * 9)); 87 l &= ~(0x1ff << (field * 10));
87 l |= config << (field * 9); 88 l |= config << (field * 10);
88 __raw_writel(l, reg); 89 __raw_writel(l, reg);
89 90
90 spin_unlock(&gpio_mux_lock); 91 spin_unlock(&gpio_mux_lock);
diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c
new file mode 100644
index 000000000000..c29098af7394
--- /dev/null
+++ b/arch/arm/mach-mx3/mx31moboard.c
@@ -0,0 +1,141 @@
1/*
2 * Copyright (C) 2008 Valentin Longchamp, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#include <linux/types.h>
20#include <linux/init.h>
21
22#include <linux/platform_device.h>
23#include <linux/mtd/physmap.h>
24#include <linux/mtd/partitions.h>
25#include <linux/memory.h>
26
27#include <mach/hardware.h>
28#include <asm/mach-types.h>
29#include <asm/mach/arch.h>
30#include <asm/mach/time.h>
31#include <asm/mach/map.h>
32#include <mach/common.h>
33#include <mach/imx-uart.h>
34#include <mach/iomux-mx3.h>
35
36#include "devices.h"
37
38static struct physmap_flash_data mx31moboard_flash_data = {
39 .width = 2,
40};
41
42static struct resource mx31moboard_flash_resource = {
43 .start = 0xa0000000,
44 .end = 0xa1ffffff,
45 .flags = IORESOURCE_MEM,
46};
47
48static struct platform_device mx31moboard_flash = {
49 .name = "physmap-flash",
50 .id = 0,
51 .dev = {
52 .platform_data = &mx31moboard_flash_data,
53 },
54 .resource = &mx31moboard_flash_resource,
55 .num_resources = 1,
56};
57
58static struct imxuart_platform_data uart_pdata = {
59 .flags = IMXUART_HAVE_RTSCTS,
60};
61
62static struct platform_device *devices[] __initdata = {
63 &mx31moboard_flash,
64};
65
66/*
67 * Board specific initialization.
68 */
69static void __init mxc_board_init(void)
70{
71 platform_add_devices(devices, ARRAY_SIZE(devices));
72
73 mxc_iomux_mode(MX31_PIN_CTS1__CTS1);
74 mxc_iomux_mode(MX31_PIN_RTS1__RTS1);
75 mxc_iomux_mode(MX31_PIN_TXD1__TXD1);
76 mxc_iomux_mode(MX31_PIN_RXD1__RXD1);
77
78 mxc_register_device(&mxc_uart_device0, &uart_pdata);
79
80 mxc_iomux_mode(MX31_PIN_CTS2__CTS2);
81 mxc_iomux_mode(MX31_PIN_RTS2__RTS2);
82 mxc_iomux_mode(MX31_PIN_TXD2__TXD2);
83 mxc_iomux_mode(MX31_PIN_RXD2__RXD2);
84
85 mxc_register_device(&mxc_uart_device1, &uart_pdata);
86
87 mxc_iomux_mode(MX31_PIN_PC_RST__CTS5);
88 mxc_iomux_mode(MX31_PIN_PC_VS2__RTS5);
89 mxc_iomux_mode(MX31_PIN_PC_BVD2__TXD5);
90 mxc_iomux_mode(MX31_PIN_PC_BVD1__RXD5);
91
92 mxc_register_device(&mxc_uart_device4, &uart_pdata);
93}
94
95/*
96 * This structure defines static mappings for the mx31moboard.
97 */
98static struct map_desc mx31moboard_io_desc[] __initdata = {
99 {
100 .virtual = AIPS1_BASE_ADDR_VIRT,
101 .pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
102 .length = AIPS1_SIZE,
103 .type = MT_DEVICE_NONSHARED
104 }, {
105 .virtual = AIPS2_BASE_ADDR_VIRT,
106 .pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
107 .length = AIPS2_SIZE,
108 .type = MT_DEVICE_NONSHARED
109 },
110};
111
112/*
113 * Set up static virtual mappings.
114 */
115void __init mx31moboard_map_io(void)
116{
117 mxc_map_io();
118 iotable_init(mx31moboard_io_desc, ARRAY_SIZE(mx31moboard_io_desc));
119}
120
121static void __init mx31moboard_timer_init(void)
122{
123 mxc_clocks_init(26000000);
124 mxc_timer_init("ipg_clk.0");
125}
126
127struct sys_timer mx31moboard_timer = {
128 .init = mx31moboard_timer_init,
129};
130
131MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
132 /* Maintainer: Valentin Longchamp, EPFL Mobots group */
133 .phys_io = AIPS1_BASE_ADDR,
134 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
135 .boot_params = PHYS_OFFSET + 0x100,
136 .map_io = mx31moboard_map_io,
137 .init_irq = mxc_init_irq,
138 .init_machine = mxc_board_init,
139 .timer = &mx31moboard_timer,
140MACHINE_END
141
diff --git a/arch/arm/mach-mx3/mx31pdk.c b/arch/arm/mach-mx3/mx31pdk.c
new file mode 100644
index 000000000000..d464d068a4a6
--- /dev/null
+++ b/arch/arm/mach-mx3/mx31pdk.c
@@ -0,0 +1,115 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#include <linux/types.h>
20#include <linux/init.h>
21#include <linux/clk.h>
22#include <linux/irq.h>
23
24#include <mach/hardware.h>
25#include <asm/mach-types.h>
26#include <asm/mach/arch.h>
27#include <asm/mach/time.h>
28#include <asm/memory.h>
29#include <asm/mach/map.h>
30#include <mach/common.h>
31#include <mach/board-mx31pdk.h>
32#include <mach/imx-uart.h>
33#include <mach/iomux-mx3.h>
34#include "devices.h"
35
36/*!
37 * @file mx31pdk.c
38 *
39 * @brief This file contains the board-specific initialization routines.
40 *
41 * @ingroup System
42 */
43
44static struct imxuart_platform_data uart_pdata = {
45 .flags = IMXUART_HAVE_RTSCTS,
46};
47
48static inline void mxc_init_imx_uart(void)
49{
50 mxc_iomux_mode(MX31_PIN_CTS1__CTS1);
51 mxc_iomux_mode(MX31_PIN_RTS1__RTS1);
52 mxc_iomux_mode(MX31_PIN_TXD1__TXD1);
53 mxc_iomux_mode(MX31_PIN_RXD1__RXD1);
54
55 mxc_register_device(&mxc_uart_device0, &uart_pdata);
56}
57
58/*!
59 * This structure defines static mappings for the i.MX31PDK board.
60 */
61static struct map_desc mx31pdk_io_desc[] __initdata = {
62 {
63 .virtual = AIPS1_BASE_ADDR_VIRT,
64 .pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
65 .length = AIPS1_SIZE,
66 .type = MT_DEVICE_NONSHARED
67 }, {
68 .virtual = AIPS2_BASE_ADDR_VIRT,
69 .pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
70 .length = AIPS2_SIZE,
71 .type = MT_DEVICE_NONSHARED
72 },
73};
74
75/*!
76 * Set up static virtual mappings.
77 */
78static void __init mx31pdk_map_io(void)
79{
80 mxc_map_io();
81 iotable_init(mx31pdk_io_desc, ARRAY_SIZE(mx31pdk_io_desc));
82}
83
84/*!
85 * Board specific initialization.
86 */
87static void __init mxc_board_init(void)
88{
89 mxc_init_imx_uart();
90}
91
92static void __init mx31pdk_timer_init(void)
93{
94 mxc_clocks_init(26000000);
95 mxc_timer_init("ipg_clk.0");
96}
97
98static struct sys_timer mx31pdk_timer = {
99 .init = mx31pdk_timer_init,
100};
101
102/*
103 * The following uses standard kernel macros defined in arch.h in order to
104 * initialize __mach_desc_MX31PDK data structure.
105 */
106MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
107 /* Maintainer: Freescale Semiconductor, Inc. */
108 .phys_io = AIPS1_BASE_ADDR,
109 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
110 .boot_params = PHYS_OFFSET + 0x100,
111 .map_io = mx31pdk_map_io,
112 .init_irq = mxc_init_irq,
113 .init_machine = mxc_board_init,
114 .timer = &mx31pdk_timer,
115MACHINE_END
diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c
index 8cd1fdf1897c..8cea82587222 100644
--- a/arch/arm/mach-mx3/pcm037.c
+++ b/arch/arm/mach-mx3/pcm037.c
@@ -21,7 +21,11 @@
21 21
22#include <linux/platform_device.h> 22#include <linux/platform_device.h>
23#include <linux/mtd/physmap.h> 23#include <linux/mtd/physmap.h>
24#include <linux/mtd/plat-ram.h>
24#include <linux/memory.h> 25#include <linux/memory.h>
26#include <linux/gpio.h>
27#include <linux/smc911x.h>
28#include <linux/interrupt.h>
25 29
26#include <mach/hardware.h> 30#include <mach/hardware.h>
27#include <asm/mach-types.h> 31#include <asm/mach-types.h>
@@ -32,6 +36,7 @@
32#include <mach/imx-uart.h> 36#include <mach/imx-uart.h>
33#include <mach/iomux-mx3.h> 37#include <mach/iomux-mx3.h>
34#include <mach/board-pcm037.h> 38#include <mach/board-pcm037.h>
39#include <mach/mxc_nand.h>
35 40
36#include "devices.h" 41#include "devices.h"
37 42
@@ -59,8 +64,63 @@ static struct imxuart_platform_data uart_pdata = {
59 .flags = IMXUART_HAVE_RTSCTS, 64 .flags = IMXUART_HAVE_RTSCTS,
60}; 65};
61 66
67static struct resource smc911x_resources[] = {
68 [0] = {
69 .start = CS1_BASE_ADDR + 0x300,
70 .end = CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
71 .flags = IORESOURCE_MEM,
72 },
73 [1] = {
74 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
75 .end = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
76 .flags = IORESOURCE_IRQ,
77 },
78};
79
80static struct smc911x_platdata smc911x_info = {
81 .flags = SMC911X_USE_32BIT,
82 .irq_flags = IRQF_SHARED | IRQF_TRIGGER_LOW,
83};
84
85static struct platform_device pcm037_eth = {
86 .name = "smc911x",
87 .id = -1,
88 .num_resources = ARRAY_SIZE(smc911x_resources),
89 .resource = smc911x_resources,
90 .dev = {
91 .platform_data = &smc911x_info,
92 },
93};
94
95static struct platdata_mtd_ram pcm038_sram_data = {
96 .bankwidth = 2,
97};
98
99static struct resource pcm038_sram_resource = {
100 .start = CS4_BASE_ADDR,
101 .end = CS4_BASE_ADDR + 512 * 1024 - 1,
102 .flags = IORESOURCE_MEM,
103};
104
105static struct platform_device pcm037_sram_device = {
106 .name = "mtd-ram",
107 .id = 0,
108 .dev = {
109 .platform_data = &pcm038_sram_data,
110 },
111 .num_resources = 1,
112 .resource = &pcm038_sram_resource,
113};
114
115static struct mxc_nand_platform_data pcm037_nand_board_info = {
116 .width = 1,
117 .hw_ecc = 1,
118};
119
62static struct platform_device *devices[] __initdata = { 120static struct platform_device *devices[] __initdata = {
63 &pcm037_flash, 121 &pcm037_flash,
122 &pcm037_eth,
123 &pcm037_sram_device,
64}; 124};
65 125
66/* 126/*
@@ -84,6 +144,13 @@ static void __init mxc_board_init(void)
84 144
85 mxc_iomux_mode(MX31_PIN_BATT_LINE__OWIRE); 145 mxc_iomux_mode(MX31_PIN_BATT_LINE__OWIRE);
86 mxc_register_device(&mxc_w1_master_device, NULL); 146 mxc_register_device(&mxc_w1_master_device, NULL);
147
148 /* SMSC9215 IRQ pin */
149 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO));
150 if (!gpio_request(MX31_PIN_GPIO3_1, "pcm037-eth"))
151 gpio_direction_input(MX31_PIN_GPIO3_1);
152
153 mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
87} 154}
88 155
89/* 156/*
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index a1612958a59e..16cb07cd9162 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -6,6 +6,11 @@ choice
6 prompt "MXC/iMX Base Type" 6 prompt "MXC/iMX Base Type"
7 default ARCH_MX3 7 default ARCH_MX3
8 8
9config ARCH_MX1
10 bool "MX1-based"
11 help
12 This enables support for systems based on the Freescale i.MX1 family
13
9config ARCH_MX2 14config ARCH_MX2
10 bool "MX2-based" 15 bool "MX2-based"
11 select CPU_ARM926T 16 select CPU_ARM926T
@@ -20,6 +25,7 @@ config ARCH_MX3
20 25
21endchoice 26endchoice
22 27
28source "arch/arm/mach-mx1/Kconfig"
23source "arch/arm/mach-mx2/Kconfig" 29source "arch/arm/mach-mx2/Kconfig"
24source "arch/arm/mach-mx3/Kconfig" 30source "arch/arm/mach-mx3/Kconfig"
25 31
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 067556f7c91f..db74a929179d 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -5,4 +5,5 @@
5# Common support 5# Common support
6obj-y := irq.o clock.o gpio.o time.o devices.o 6obj-y := irq.o clock.o gpio.o time.o devices.o
7 7
8obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o
8obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o 9obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o
diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c
index 214274344442..e1c2eb497fbc 100644
--- a/arch/arm/plat-mxc/dma-mx1-mx2.c
+++ b/arch/arm/plat-mxc/dma-mx1-mx2.c
@@ -34,7 +34,6 @@
34#include <asm/system.h> 34#include <asm/system.h>
35#include <asm/irq.h> 35#include <asm/irq.h>
36#include <mach/hardware.h> 36#include <mach/hardware.h>
37#include <mach/dma.h>
38#include <mach/dma-mx1-mx2.h> 37#include <mach/dma-mx1-mx2.h>
39 38
40#define DMA_DCR 0x00 /* Control Register */ 39#define DMA_DCR 0x00 /* Control Register */
@@ -114,7 +113,7 @@ struct imx_dma_channel {
114 void (*err_handler) (int, void *, int errcode); 113 void (*err_handler) (int, void *, int errcode);
115 void (*prog_handler) (int, void *, struct scatterlist *); 114 void (*prog_handler) (int, void *, struct scatterlist *);
116 void *data; 115 void *data;
117 dmamode_t dma_mode; 116 unsigned int dma_mode;
118 struct scatterlist *sg; 117 struct scatterlist *sg;
119 unsigned int resbytes; 118 unsigned int resbytes;
120 int dma_num; 119 int dma_num;
@@ -193,7 +192,7 @@ static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
193int 192int
194imx_dma_setup_single(int channel, dma_addr_t dma_address, 193imx_dma_setup_single(int channel, dma_addr_t dma_address,
195 unsigned int dma_length, unsigned int dev_addr, 194 unsigned int dma_length, unsigned int dev_addr,
196 dmamode_t dmamode) 195 unsigned int dmamode)
197{ 196{
198 struct imx_dma_channel *imxdma = &imx_dma_channels[channel]; 197 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
199 198
@@ -288,7 +287,7 @@ int
288imx_dma_setup_sg(int channel, 287imx_dma_setup_sg(int channel,
289 struct scatterlist *sg, unsigned int sgcount, 288 struct scatterlist *sg, unsigned int sgcount,
290 unsigned int dma_length, unsigned int dev_addr, 289 unsigned int dma_length, unsigned int dev_addr,
291 dmamode_t dmamode) 290 unsigned int dmamode)
292{ 291{
293 struct imx_dma_channel *imxdma = &imx_dma_channels[channel]; 292 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
294 293
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index de5c4747453f..ccbd94adc668 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -115,8 +115,8 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
115 } 115 }
116} 116}
117 117
118#ifdef CONFIG_ARCH_MX3 118#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1)
119/* MX3 has one interrupt *per* gpio port */ 119/* MX1 and MX3 has one interrupt *per* gpio port */
120static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) 120static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
121{ 121{
122 u32 irq_stat; 122 u32 irq_stat;
@@ -237,7 +237,7 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
237 /* its a serious configuration bug when it fails */ 237 /* its a serious configuration bug when it fails */
238 BUG_ON( gpiochip_add(&port[i].chip) < 0 ); 238 BUG_ON( gpiochip_add(&port[i].chip) < 0 );
239 239
240#ifdef CONFIG_ARCH_MX3 240#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1)
241 /* setup one handler for each entry */ 241 /* setup one handler for each entry */
242 set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); 242 set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
243 set_irq_data(port[i].irq, &port[i]); 243 set_irq_data(port[i].irq, &port[i]);
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
index 61e66dac90ef..0c748a8e157b 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
@@ -28,11 +28,6 @@
28/* 28/*
29 * MXC UART EVB board level configurations 29 * MXC UART EVB board level configurations
30 */ 30 */
31
32#define MXC_LL_EXTUART_PADDR (CS4_BASE_ADDR + 0x20000)
33#define MXC_LL_EXTUART_VADDR (CS4_BASE_ADDR_VIRT + 0x20000)
34#define MXC_LL_EXTUART_16BIT_BUS
35
36#define MXC_LL_UART_PADDR UART1_BASE_ADDR 31#define MXC_LL_UART_PADDR UART1_BASE_ADDR
37#define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR) 32#define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR)
38 33
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31pdk.h b/arch/arm/plat-mxc/include/mach/board-mx31pdk.h
new file mode 100644
index 000000000000..2b6b316d0f51
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-mx31pdk.h
@@ -0,0 +1,19 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_MX31PDK_H__
12#define __ASM_ARCH_MXC_BOARD_MX31PDK_H__
13
14/* mandatory for CONFIG_LL_DEBUG */
15
16#define MXC_LL_UART_PADDR UART1_BASE_ADDR
17#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
18
19#endif /* __ASM_ARCH_MXC_BOARD_MX31PDK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index b9907bebba3b..602768b427e2 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -28,6 +28,9 @@
28#ifdef CONFIG_MACH_PCM038 28#ifdef CONFIG_MACH_PCM038
29#include <mach/board-pcm038.h> 29#include <mach/board-pcm038.h>
30#endif 30#endif
31#ifdef CONFIG_MACH_MX31_3DS
32#include <mach/board-mx31pdk.h>
33#endif
31 .macro addruart,rx 34 .macro addruart,rx
32 mrc p15, 0, \rx, c1, c0 35 mrc p15, 0, \rx, c1, c0
33 tst \rx, #1 @ MMU enabled? 36 tst \rx, #1 @ MMU enabled?
diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
index 6cc6f0c8cb25..b3876cc238ca 100644
--- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
+++ b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
@@ -22,13 +22,15 @@
22 * MA 02110-1301, USA. 22 * MA 02110-1301, USA.
23 */ 23 */
24 24
25#include <mach/dma.h>
26
27#ifndef __ASM_ARCH_MXC_DMA_H 25#ifndef __ASM_ARCH_MXC_DMA_H
28#define __ASM_ARCH_MXC_DMA_H 26#define __ASM_ARCH_MXC_DMA_H
29 27
30#define IMX_DMA_CHANNELS 16 28#define IMX_DMA_CHANNELS 16
31 29
30#define DMA_MODE_READ 0
31#define DMA_MODE_WRITE 1
32#define DMA_MODE_MASK 1
33
32#define DMA_BASE IO_ADDRESS(DMA_BASE_ADDR) 34#define DMA_BASE IO_ADDRESS(DMA_BASE_ADDR)
33 35
34#define IMX_DMA_MEMSIZE_32 (0 << 4) 36#define IMX_DMA_MEMSIZE_32 (0 << 4)
@@ -54,12 +56,12 @@ imx_dma_config_burstlen(int channel, unsigned int burstlen);
54int 56int
55imx_dma_setup_single(int channel, dma_addr_t dma_address, 57imx_dma_setup_single(int channel, dma_addr_t dma_address,
56 unsigned int dma_length, unsigned int dev_addr, 58 unsigned int dma_length, unsigned int dev_addr,
57 dmamode_t dmamode); 59 unsigned int dmamode);
58 60
59int 61int
60imx_dma_setup_sg(int channel, struct scatterlist *sg, 62imx_dma_setup_sg(int channel, struct scatterlist *sg,
61 unsigned int sgcount, unsigned int dma_length, 63 unsigned int sgcount, unsigned int dma_length,
62 unsigned int dev_addr, dmamode_t dmamode); 64 unsigned int dev_addr, unsigned int dmamode);
63 65
64int 66int
65imx_dma_setup_handlers(int channel, 67imx_dma_setup_handlers(int channel,
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index 3caadeeda701..a612d8bb73c8 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -32,6 +32,10 @@
32# endif 32# endif
33#endif 33#endif
34 34
35#ifdef CONFIG_ARCH_MX1
36# include <mach/mx1.h>
37#endif
38
35#include <mach/mxc.h> 39#include <mach/mxc.h>
36 40
37#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ 41#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
index 3d09bfd6c53d..60b3c9b6ef7d 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
@@ -21,12 +21,6 @@
21 21
22#include <linux/io.h> 22#include <linux/io.h>
23 23
24#define MXC_GPIO_ALLOC_MODE_NORMAL 0
25#define MXC_GPIO_ALLOC_MODE_NO_ALLOC 1
26#define MXC_GPIO_ALLOC_MODE_TRY_ALLOC 2
27#define MXC_GPIO_ALLOC_MODE_ALLOC_ONLY 4
28#define MXC_GPIO_ALLOC_MODE_RELEASE 8
29
30/* 24/*
31 * GPIO Module and I/O Multiplexer 25 * GPIO Module and I/O Multiplexer
32 * x = 0..3 for reg_A, reg_B, reg_C, reg_D 26 * x = 0..3 for reg_A, reg_B, reg_C, reg_D
@@ -103,7 +97,8 @@
103 97
104extern void mxc_gpio_mode(int gpio_mode); 98extern void mxc_gpio_mode(int gpio_mode);
105extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, 99extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
106 int alloc_mode, const char *label); 100 const char *label);
101extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
107 102
108/*-------------------------------------------------------------------------*/ 103/*-------------------------------------------------------------------------*/
109 104
@@ -113,9 +108,9 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
113 * missing on some (many) pins 108 * missing on some (many) pins
114 */ 109 */
115#ifdef CONFIG_ARCH_MX1 110#ifdef CONFIG_ARCH_MX1
116#define PA0_AIN_SPI2_CLK (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0) 111#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_OUT | 0)
117#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0) 112#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0)
118#define PA1_AOUT_SPI2_RXD (GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1) 113#define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_IN | 1)
119#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1) 114#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1)
120#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 2) 115#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 2)
121#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3) 116#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3)
@@ -133,7 +128,7 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
133#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15) 128#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15)
134#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16) 129#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16)
135#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17) 130#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17)
136#define PA17_AIN_SPI2_SS (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17) 131#define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_OUT | 17)
137#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18) 132#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18)
138#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19) 133#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19)
139#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20) 134#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20)
@@ -201,27 +196,27 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
201#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15) 196#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15)
202#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16) 197#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16)
203#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17) 198#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17)
204#define PC24_BIN_UART3_RI (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24) 199#define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24)
205#define PC25_BIN_UART3_DSR (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25) 200#define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25)
206#define PC26_AOUT_UART3_DTR (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26) 201#define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_IN | 26)
207#define PC27_BIN_UART3_DCD (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27) 202#define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27)
208#define PC28_BIN_UART3_CTS (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28) 203#define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28)
209#define PC29_AOUT_UART3_RTS (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29) 204#define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_IN | 29)
210#define PC30_BIN_UART3_TX (GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30) 205#define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30)
211#define PC31_AOUT_UART3_RX (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31) 206#define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_IN | 31)
212#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 6) 207#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 6)
213#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7) 208#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7)
214#define PD7_AF_UART2_DTR (GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7) 209#define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_IN | GPIO_AF | 7)
215#define PD7_AIN_SPI2_SCLK (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7) 210#define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7)
216#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8) 211#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8)
217#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_OUT | GPIO_AF | 8) 212#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_OUT | GPIO_AF | 8)
218#define PD8_AIN_SPI2_SS (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8) 213#define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8)
219#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9) 214#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9)
220#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_OUT | GPIO_AF | 9) 215#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_OUT | GPIO_AF | 9)
221#define PD9_AOUT_SPI2_RXD (GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9) 216#define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_IN | 9)
222#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_OUT | GPIO_PF | 10) 217#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_OUT | GPIO_PF | 10)
223#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_OUT | GPIO_AF | 10) 218#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_OUT | GPIO_AF | 10)
224#define PD10_AIN_SPI2_TXD (GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10) 219#define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_OUT | 10)
225#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_OUT | GPIO_PF | 11) 220#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_OUT | GPIO_PF | 11)
226#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_OUT | GPIO_PF | 12) 221#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_OUT | GPIO_PF | 12)
227#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_OUT | GPIO_PF | 13) 222#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_OUT | GPIO_PF | 13)
@@ -243,7 +238,7 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
243#define PD29_PF_LD14 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29) 238#define PD29_PF_LD14 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29)
244#define PD30_PF_LD15 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 30) 239#define PD30_PF_LD15 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 30)
245#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31) 240#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31)
246#define PD31_BIN_SPI2_TXD (GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31) 241#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31)
247#endif 242#endif
248 243
249#ifdef CONFIG_ARCH_MX2 244#ifdef CONFIG_ARCH_MX2
@@ -279,6 +274,12 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
279#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_OUT | GPIO_PF | 29) 274#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_OUT | GPIO_PF | 29)
280#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_OUT | GPIO_PF | 30) 275#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_OUT | GPIO_PF | 30)
281#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_OUT | GPIO_PF | 31) 276#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_OUT | GPIO_PF | 31)
277#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4)
278#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5)
279#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6)
280#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7)
281#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8)
282#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9)
282#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 10) 283#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 10)
283#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 10) 284#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 10)
284#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 11) 285#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 11)
@@ -315,6 +316,13 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
315#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 31) 316#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 31)
316#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_IN | GPIO_PF | 5) 317#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_IN | GPIO_PF | 5)
317#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_IN | GPIO_PF | 6) 318#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_IN | GPIO_PF | 6)
319#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7)
320#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8)
321#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
322#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10)
323#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
324#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12)
325#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13)
318#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 16) 326#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 16)
319#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 17) 327#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 17)
320#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 18) 328#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 18)
@@ -365,6 +373,9 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
365#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_IN | GPIO_PF | 30) 373#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_IN | GPIO_PF | 30)
366#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_OUT | GPIO_PF | 31) 374#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_OUT | GPIO_PF | 31)
367#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23) 375#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
376#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0)
377#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1)
378#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2)
368#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3) 379#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
369#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4) 380#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4)
370#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6) 381#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
@@ -379,10 +390,18 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
379#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15) 390#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15)
380#define PE16_AF_RTCK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 16) 391#define PE16_AF_RTCK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 16)
381#define PE16_PF_RTCK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 16) 392#define PE16_PF_RTCK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 16)
393#define PE18_PF_SDHC1_D0 (GPIO_PORTE | GPIO_PF | 18)
382#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_IN | GPIO_AF | 18) 394#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_IN | GPIO_AF | 18)
395#define PE19_PF_SDHC1_D1 (GPIO_PORTE | GPIO_PF | 19)
396#define PE20_PF_SDHC1_D2 (GPIO_PORTE | GPIO_PF | 20)
397#define PE21_PF_SDHC1_D3 (GPIO_PORTE | GPIO_PF | 21)
383#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_OUT | GPIO_AF | 21) 398#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_OUT | GPIO_AF | 21)
399#define PE22_PF_SDHC1_CMD (GPIO_PORTE | GPIO_PF | 22)
384#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_OUT | GPIO_AF | 22) 400#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_OUT | GPIO_AF | 22)
401#define PE22_PF_SDHC1_CLK (GPIO_PORTE | GPIO_PF | 23)
385#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 23) 402#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 23)
403#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24)
404#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25)
386#endif 405#endif
387 406
388/* decode irq number to use with IMR(x), ISR(x) and friends */ 407/* decode irq number to use with IMR(x), ISR(x) and friends */
@@ -392,5 +411,6 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
392#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x) 411#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
393#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) 412#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
394#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x) 413#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
414#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x)
395 415
396#endif /* _MXC_GPIO_MX1_MX2_H */ 416#endif /* _MXC_GPIO_MX1_MX2_H */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index c9f39c2fb8c6..20e5c4c63314 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -491,6 +491,14 @@ enum iomux_pins {
491#define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC) 491#define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
492#define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC) 492#define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
493#define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC) 493#define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
494#define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC)
495#define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC)
496#define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC)
497#define MX31_PIN_RXD2__RXD2 IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC)
498#define MX31_PIN_PC_RST__CTS5 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2)
499#define MX31_PIN_PC_VS2__RTS5 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2)
500#define MX31_PIN_PC_BVD2__TXD5 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2)
501#define MX31_PIN_PC_BVD1__RXD5 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT2)
494#define MX31_PIN_CSPI1_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_FUNC) 502#define MX31_PIN_CSPI1_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_FUNC)
495#define MX31_PIN_CSPI1_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_FUNC) 503#define MX31_PIN_CSPI1_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_FUNC)
496#define MX31_PIN_CSPI1_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_FUNC) 504#define MX31_PIN_CSPI1_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_FUNC)
@@ -509,6 +517,15 @@ enum iomux_pins {
509#define MX31_PIN_CSPI3_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_FUNC) 517#define MX31_PIN_CSPI3_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_FUNC)
510#define MX31_PIN_CSPI3_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_FUNC) 518#define MX31_PIN_CSPI3_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_FUNC)
511#define MX31_PIN_CSPI3_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_FUNC) 519#define MX31_PIN_CSPI3_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_FUNC)
520#define MX31_PIN_BATT_LINE__OWIRE IOMUX_MODE(MX31_PIN_BATT_LINE, IOMUX_CONFIG_FUNC)
521#define MX31_PIN_CS4__CS4 IOMUX_MODE(MX31_PIN_CS4, IOMUX_CONFIG_FUNC)
522#define MX31_PIN_SD1_DATA3__SD1_DATA3 IOMUX_MODE(MX31_PIN_SD1_DATA3, IOMUX_CONFIG_FUNC)
523#define MX31_PIN_SD1_DATA2__SD1_DATA2 IOMUX_MODE(MX31_PIN_SD1_DATA2, IOMUX_CONFIG_FUNC)
524#define MX31_PIN_SD1_DATA1__SD1_DATA1 IOMUX_MODE(MX31_PIN_SD1_DATA1, IOMUX_CONFIG_FUNC)
525#define MX31_PIN_SD1_DATA0__SD1_DATA0 IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC)
526#define MX31_PIN_SD1_CLK__SD1_CLK IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC)
527#define MX31_PIN_SD1_CMD__SD1_CMD IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC)
528
512/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 529/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0
513 * cspi1_ss1*/ 530 * cspi1_ss1*/
514 531
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index b55bba35e18a..b8ac91608a4f 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -14,4 +14,9 @@
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15extern void imx_irq_set_priority(unsigned char irq, unsigned char prio); 15extern void imx_irq_set_priority(unsigned char irq, unsigned char prio);
16 16
17/* all normal IRQs can be FIQs */
18#define FIQ_START 0
19/* switch betwean IRQ and FIQ */
20extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type);
21
17#endif /* __ASM_ARCH_MXC_IRQS_H__ */ 22#endif /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mtd-xip.h b/arch/arm/plat-mxc/include/mach/mtd-xip.h
new file mode 100644
index 000000000000..1ab1bba5688d
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mtd-xip.h
@@ -0,0 +1,34 @@
1/*
2 * MTD primitives for XIP support. Architecture specific functions
3 *
4 * Do not include this file directly. It's included from linux/mtd/xip.h
5 *
6 * Copyright (C) 2008 Darius Augulis <augulis.darius@gmail.com>, Teltonika, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#include <mach/mxc_timer.h>
15
16#ifndef __ARCH_IMX_MTD_XIP_H__
17#define __ARCH_IMX_MTD_XIP_H__
18
19#ifdef CONFIG_ARCH_MX1
20/* AITC registers */
21#define AITC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
22#define NIPNDH (AITC_BASE + 0x58)
23#define NIPNDL (AITC_BASE + 0x5C)
24#define INTENABLEH (AITC_BASE + 0x10)
25#define INTENABLEL (AITC_BASE + 0x14)
26/* MTD macros */
27#define xip_irqpending() ((__raw_readl(INTENABLEH) & __raw_readl(NIPNDH)) \
28 || (__raw_readl(INTENABLEL) & __raw_readl(NIPNDL)))
29#define xip_currtime() (__raw_readl(TIMER_BASE + MXC_TCN))
30#define xip_elapsed_since(x) (signed)((__raw_readl(TIMER_BASE + MXC_TCN) - (x)) / 96)
31#define xip_cpu_idle() asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (0))
32#endif /* CONFIG_ARCH_MX1 */
33
34#endif /* __ARCH_IMX_MTD_XIP_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
new file mode 100644
index 000000000000..e7f6d00009a7
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -0,0 +1,197 @@
1/*
2 * Copyright (C) 1997,1998 Russell King
3 * Copyright (C) 1999 ARM Limited
4 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __ASM_ARCH_MXC_MX1_H__
13#define __ASM_ARCH_MXC_MX1_H__
14
15#ifndef __ASM_ARCH_MXC_HARDWARE_H__
16#error "Do not include directly."
17#endif
18
19#include <mach/vmalloc.h>
20
21/*
22 * defines the hardware clock tick rate
23 */
24#define CLOCK_TICK_RATE 16000000
25
26#define PHYS_OFFSET UL(0x08000000)
27
28/*
29 * Memory map
30 */
31#define IMX_IO_PHYS 0x00200000
32#define IMX_IO_SIZE 0x00100000
33#define IMX_IO_BASE VMALLOC_END
34
35#define IMX_CS0_PHYS 0x10000000
36#define IMX_CS0_SIZE 0x02000000
37
38#define IMX_CS1_PHYS 0x12000000
39#define IMX_CS1_SIZE 0x01000000
40
41#define IMX_CS2_PHYS 0x13000000
42#define IMX_CS2_SIZE 0x01000000
43
44#define IMX_CS3_PHYS 0x14000000
45#define IMX_CS3_SIZE 0x01000000
46
47#define IMX_CS4_PHYS 0x15000000
48#define IMX_CS4_SIZE 0x01000000
49
50#define IMX_CS5_PHYS 0x16000000
51#define IMX_CS5_SIZE 0x01000000
52
53/*
54 * Register BASEs, based on OFFSETs
55 */
56#define AIPI1_BASE_ADDR (0x00000 + IMX_IO_PHYS)
57#define WDT_BASE_ADDR (0x01000 + IMX_IO_PHYS)
58#define TIM1_BASE_ADDR (0x02000 + IMX_IO_PHYS)
59#define TIM2_BASE_ADDR (0x03000 + IMX_IO_PHYS)
60#define RTC_BASE_ADDR (0x04000 + IMX_IO_PHYS)
61#define LCDC_BASE_ADDR (0x05000 + IMX_IO_PHYS)
62#define UART1_BASE_ADDR (0x06000 + IMX_IO_PHYS)
63#define UART2_BASE_ADDR (0x07000 + IMX_IO_PHYS)
64#define PWM_BASE_ADDR (0x08000 + IMX_IO_PHYS)
65#define DMA_BASE_ADDR (0x09000 + IMX_IO_PHYS)
66#define AIPI2_BASE_ADDR (0x10000 + IMX_IO_PHYS)
67#define SIM_BASE_ADDR (0x11000 + IMX_IO_PHYS)
68#define USBD_BASE_ADDR (0x12000 + IMX_IO_PHYS)
69#define SPI1_BASE_ADDR (0x13000 + IMX_IO_PHYS)
70#define MMC_BASE_ADDR (0x14000 + IMX_IO_PHYS)
71#define ASP_BASE_ADDR (0x15000 + IMX_IO_PHYS)
72#define BTA_BASE_ADDR (0x16000 + IMX_IO_PHYS)
73#define I2C_BASE_ADDR (0x17000 + IMX_IO_PHYS)
74#define SSI_BASE_ADDR (0x18000 + IMX_IO_PHYS)
75#define SPI2_BASE_ADDR (0x19000 + IMX_IO_PHYS)
76#define MSHC_BASE_ADDR (0x1A000 + IMX_IO_PHYS)
77#define CCM_BASE_ADDR (0x1B000 + IMX_IO_PHYS)
78#define SCM_BASE_ADDR (0x1B804 + IMX_IO_PHYS)
79#define GPIO_BASE_ADDR (0x1C000 + IMX_IO_PHYS)
80#define EIM_BASE_ADDR (0x20000 + IMX_IO_PHYS)
81#define SDRAMC_BASE_ADDR (0x21000 + IMX_IO_PHYS)
82#define MMA_BASE_ADDR (0x22000 + IMX_IO_PHYS)
83#define AVIC_BASE_ADDR (0x23000 + IMX_IO_PHYS)
84#define CSI_BASE_ADDR (0x24000 + IMX_IO_PHYS)
85
86/* macro to get at IO space when running virtually */
87#define IO_ADDRESS(x) ((x) - IMX_IO_PHYS + IMX_IO_BASE)
88
89/* define macros needed for entry-macro.S */
90#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x)
91
92/* fixed interrput numbers */
93#define INT_SOFTINT 0
94#define CSI_INT 6
95#define DSPA_MAC_INT 7
96#define DSPA_INT 8
97#define COMP_INT 9
98#define MSHC_XINT 10
99#define GPIO_INT_PORTA 11
100#define GPIO_INT_PORTB 12
101#define GPIO_INT_PORTC 13
102#define LCDC_INT 14
103#define SIM_INT 15
104#define SIM_DATA_INT 16
105#define RTC_INT 17
106#define RTC_SAMINT 18
107#define UART2_MINT_PFERR 19
108#define UART2_MINT_RTS 20
109#define UART2_MINT_DTR 21
110#define UART2_MINT_UARTC 22
111#define UART2_MINT_TX 23
112#define UART2_MINT_RX 24
113#define UART1_MINT_PFERR 25
114#define UART1_MINT_RTS 26
115#define UART1_MINT_DTR 27
116#define UART1_MINT_UARTC 28
117#define UART1_MINT_TX 29
118#define UART1_MINT_RX 30
119#define VOICE_DAC_INT 31
120#define VOICE_ADC_INT 32
121#define PEN_DATA_INT 33
122#define PWM_INT 34
123#define SDHC_INT 35
124#define I2C_INT 39
125#define CSPI_INT 41
126#define SSI_TX_INT 42
127#define SSI_TX_ERR_INT 43
128#define SSI_RX_INT 44
129#define SSI_RX_ERR_INT 45
130#define TOUCH_INT 46
131#define USBD_INT0 47
132#define USBD_INT1 48
133#define USBD_INT2 49
134#define USBD_INT3 50
135#define USBD_INT4 51
136#define USBD_INT5 52
137#define USBD_INT6 53
138#define BTSYS_INT 55
139#define BTTIM_INT 56
140#define BTWUI_INT 57
141#define TIM2_INT 58
142#define TIM1_INT 59
143#define DMA_ERR 60
144#define DMA_INT 61
145#define GPIO_INT_PORTD 62
146#define WDT_INT 63
147
148#define MXC_MAX_INT_LINES 64
149
150#define NR_IRQS 256
151
152/* gpio and gpio based interrupt handling */
153#define GPIO_DR 0x1C
154#define GPIO_GDIR 0x00
155#define GPIO_PSR 0x24
156#define GPIO_ICR1 0x28
157#define GPIO_ICR2 0x2C
158#define GPIO_IMR 0x30
159#define GPIO_ISR 0x34
160#define GPIO_INT_LOW_LEV 0x3
161#define GPIO_INT_HIGH_LEV 0x2
162#define GPIO_INT_RISE_EDGE 0x0
163#define GPIO_INT_FALL_EDGE 0x1
164#define GPIO_INT_NONE 0x4
165
166/* DMA */
167#define DMA_REQ_UART3_T 2
168#define DMA_REQ_UART3_R 3
169#define DMA_REQ_SSI2_T 4
170#define DMA_REQ_SSI2_R 5
171#define DMA_REQ_CSI_STAT 6
172#define DMA_REQ_CSI_R 7
173#define DMA_REQ_MSHC 8
174#define DMA_REQ_DSPA_DCT_DOUT 9
175#define DMA_REQ_DSPA_DCT_DIN 10
176#define DMA_REQ_DSPA_MAC 11
177#define DMA_REQ_EXT 12
178#define DMA_REQ_SDHC 13
179#define DMA_REQ_SPI1_R 14
180#define DMA_REQ_SPI1_T 15
181#define DMA_REQ_SSI_T 16
182#define DMA_REQ_SSI_R 17
183#define DMA_REQ_ASP_DAC 18
184#define DMA_REQ_ASP_ADC 19
185#define DMA_REQ_USP_EP(x) (20 + (x))
186#define DMA_REQ_SPI2_R 26
187#define DMA_REQ_SPI2_T 27
188#define DMA_REQ_UART2_T 28
189#define DMA_REQ_UART2_R 29
190#define DMA_REQ_UART1_T 30
191#define DMA_REQ_UART1_R 31
192
193/* mandatory for CONFIG_LL_DEBUG */
194#define MXC_LL_UART_PADDR UART1_BASE_ADDR
195#define MXC_LL_UART_VADDR IO_ADDRESS(UART1_BASE_ADDR)
196
197#endif /* __ASM_ARCH_MXC_MX1_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index a86db64744a1..aade46d90e73 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -72,7 +72,8 @@
72/* for mx27*/ 72/* for mx27*/
73#define OTG_BASE_ADDR USBOTG_BASE_ADDR 73#define OTG_BASE_ADDR USBOTG_BASE_ADDR
74#define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000) 74#define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000)
75#define EMMA_BASE_ADDR (AIPI_BASE_ADDR + 0x26400) 75#define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000)
76#define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400)
76#define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000) 77#define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000)
77#define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800) 78#define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800)
78#define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000) 79#define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000)
diff --git a/arch/arm/plat-mxc/include/mach/mxc_timer.h b/arch/arm/plat-mxc/include/mach/mxc_timer.h
index 130aebfbe168..6c19a134744b 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_timer.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_timer.h
@@ -26,7 +26,7 @@
26#include <linux/clk.h> 26#include <linux/clk.h>
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28 28
29#ifdef CONFIG_ARCH_IMX 29#ifdef CONFIG_ARCH_MX1
30#define TIMER_BASE IO_ADDRESS(TIM1_BASE_ADDR) 30#define TIMER_BASE IO_ADDRESS(TIM1_BASE_ADDR)
31#define TIMER_INTERRUPT TIM1_INT 31#define TIMER_INTERRUPT TIM1_INT
32 32
@@ -65,7 +65,7 @@ static void gpt_irq_acknowledge(void)
65{ 65{
66 __raw_writel(0, TIMER_BASE + MXC_TSTAT); 66 __raw_writel(0, TIMER_BASE + MXC_TSTAT);
67} 67}
68#endif /* CONFIG_ARCH_IMX */ 68#endif /* CONFIG_ARCH_MX1 */
69 69
70#ifdef CONFIG_ARCH_MX2 70#ifdef CONFIG_ARCH_MX2
71#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR) 71#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR)
diff --git a/arch/arm/plat-mxc/iomux-mx1-mx2.c b/arch/arm/plat-mxc/iomux-mx1-mx2.c
index d97387aa9a42..df6f18395686 100644
--- a/arch/arm/plat-mxc/iomux-mx1-mx2.c
+++ b/arch/arm/plat-mxc/iomux-mx1-mx2.c
@@ -110,12 +110,13 @@ void mxc_gpio_mode(int gpio_mode)
110EXPORT_SYMBOL(mxc_gpio_mode); 110EXPORT_SYMBOL(mxc_gpio_mode);
111 111
112int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, 112int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
113 int alloc_mode, const char *label) 113 const char *label)
114{ 114{
115 const int *p = pin_list; 115 const int *p = pin_list;
116 int i; 116 int i;
117 unsigned gpio; 117 unsigned gpio;
118 unsigned mode; 118 unsigned mode;
119 int ret = -EINVAL;
119 120
120 for (i = 0; i < count; i++) { 121 for (i = 0; i < count; i++) {
121 gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK); 122 gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK);
@@ -124,33 +125,33 @@ int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
124 if (gpio >= (GPIO_PORT_MAX + 1) * 32) 125 if (gpio >= (GPIO_PORT_MAX + 1) * 32)
125 goto setup_error; 126 goto setup_error;
126 127
127 if (alloc_mode & MXC_GPIO_ALLOC_MODE_RELEASE) 128 ret = gpio_request(gpio, label);
128 gpio_free(gpio); 129 if (ret)
129 else if (!(alloc_mode & MXC_GPIO_ALLOC_MODE_NO_ALLOC)) 130 goto setup_error;
130 if (gpio_request(gpio, label)
131 && !(alloc_mode & MXC_GPIO_ALLOC_MODE_TRY_ALLOC))
132 goto setup_error;
133 131
134 if (!(alloc_mode & (MXC_GPIO_ALLOC_MODE_ALLOC_ONLY | 132 mxc_gpio_mode(gpio | mode);
135 MXC_GPIO_ALLOC_MODE_RELEASE)))
136 mxc_gpio_mode(gpio | mode);
137 133
138 p++; 134 p++;
139 } 135 }
140 return 0; 136 return 0;
141 137
142setup_error: 138setup_error:
143 if (alloc_mode & (MXC_GPIO_ALLOC_MODE_NO_ALLOC | 139 mxc_gpio_release_multiple_pins(pin_list, i);
144 MXC_GPIO_ALLOC_MODE_TRY_ALLOC)) 140 return ret;
145 return -EINVAL; 141}
142EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins);
146 143
147 while (p != pin_list) { 144void mxc_gpio_release_multiple_pins(const int *pin_list, int count)
148 p--; 145{
149 gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK); 146 const int *p = pin_list;
147 int i;
148
149 for (i = 0; i < count; i++) {
150 unsigned gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK);
150 gpio_free(gpio); 151 gpio_free(gpio);
152 p++;
151 } 153 }
152 154
153 return -EINVAL;
154} 155}
155EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins); 156EXPORT_SYMBOL(mxc_gpio_release_multiple_pins);
156 157
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index d862c9e5f8db..e937c8759a97 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -17,9 +17,11 @@
17 * MA 02110-1301, USA. 17 * MA 02110-1301, USA.
18 */ 18 */
19 19
20#include <linux/module.h>
20#include <linux/irq.h> 21#include <linux/irq.h>
21#include <linux/io.h> 22#include <linux/io.h>
22#include <mach/common.h> 23#include <mach/common.h>
24#include <asm/mach/irq.h>
23 25
24#define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR) 26#define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
25#define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */ 27#define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */
@@ -65,6 +67,28 @@ void imx_irq_set_priority(unsigned char irq, unsigned char prio)
65EXPORT_SYMBOL(imx_irq_set_priority); 67EXPORT_SYMBOL(imx_irq_set_priority);
66#endif 68#endif
67 69
70#ifdef CONFIG_FIQ
71int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
72{
73 unsigned int irqt;
74
75 if (irq >= MXC_MAX_INT_LINES)
76 return -EINVAL;
77
78 if (irq < MXC_MAX_INT_LINES / 2) {
79 irqt = __raw_readl(AVIC_INTTYPEL) & ~(1 << irq);
80 __raw_writel(irqt | (!!type << irq), AVIC_INTTYPEL);
81 } else {
82 irq -= MXC_MAX_INT_LINES / 2;
83 irqt = __raw_readl(AVIC_INTTYPEH) & ~(1 << irq);
84 __raw_writel(irqt | (!!type << irq), AVIC_INTTYPEH);
85 }
86
87 return 0;
88}
89EXPORT_SYMBOL(mxc_set_irq_fiq);
90#endif /* CONFIG_FIQ */
91
68/* Disable interrupt number "irq" in the AVIC */ 92/* Disable interrupt number "irq" in the AVIC */
69static void mxc_mask_irq(unsigned int irq) 93static void mxc_mask_irq(unsigned int irq)
70{ 94{
@@ -91,7 +115,6 @@ static struct irq_chip mxc_avic_chip = {
91void __init mxc_init_irq(void) 115void __init mxc_init_irq(void)
92{ 116{
93 int i; 117 int i;
94 u32 reg;
95 118
96 /* put the AVIC into the reset value with 119 /* put the AVIC into the reset value with
97 * all interrupts disabled 120 * all interrupts disabled
@@ -119,5 +142,10 @@ void __init mxc_init_irq(void)
119 /* init architectures chained interrupt handler */ 142 /* init architectures chained interrupt handler */
120 mxc_register_gpios(); 143 mxc_register_gpios();
121 144
145#ifdef CONFIG_FIQ
146 /* Initialize FIQ */
147 init_FIQ();
148#endif
149
122 printk(KERN_INFO "MXC IRQ initialized\n"); 150 printk(KERN_INFO "MXC IRQ initialized\n");
123} 151}
diff --git a/drivers/mmc/host/imxmmc.c b/drivers/mmc/host/imxmmc.c
index 2f0fcdb869b7..eb29b1d933ac 100644
--- a/drivers/mmc/host/imxmmc.c
+++ b/drivers/mmc/host/imxmmc.c
@@ -10,20 +10,6 @@
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 * 12 *
13 * 2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz>
14 * Changed to conform redesigned i.MX scatter gather DMA interface
15 *
16 * 2005-11-04 Pavel Pisa <pisa@cmp.felk.cvut.cz>
17 * Updated for 2.6.14 kernel
18 *
19 * 2005-12-13 Jay Monkman <jtm@smoothsmoothie.com>
20 * Found and corrected problems in the write path
21 *
22 * 2005-12-30 Pavel Pisa <pisa@cmp.felk.cvut.cz>
23 * The event handling rewritten right way in softirq.
24 * Added many ugly hacks and delays to overcome SDHC
25 * deficiencies
26 *
27 */ 13 */
28 14
29#include <linux/module.h> 15#include <linux/module.h>
@@ -37,9 +23,9 @@
37#include <linux/mmc/card.h> 23#include <linux/mmc/card.h>
38#include <linux/delay.h> 24#include <linux/delay.h>
39#include <linux/clk.h> 25#include <linux/clk.h>
26#include <linux/io.h>
40 27
41#include <asm/dma.h> 28#include <asm/dma.h>
42#include <asm/io.h>
43#include <asm/irq.h> 29#include <asm/irq.h>
44#include <asm/sizes.h> 30#include <asm/sizes.h>
45#include <mach/mmc.h> 31#include <mach/mmc.h>
@@ -50,17 +36,16 @@
50#define DRIVER_NAME "imx-mmc" 36#define DRIVER_NAME "imx-mmc"
51 37
52#define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \ 38#define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \
53 INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \ 39 INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
54 INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO) 40 INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
55 41
56struct imxmci_host { 42struct imxmci_host {
57 struct mmc_host *mmc; 43 struct mmc_host *mmc;
58 spinlock_t lock; 44 spinlock_t lock;
59 struct resource *res; 45 struct resource *res;
46 void __iomem *base;
60 int irq; 47 int irq;
61 imx_dmach_t dma; 48 imx_dmach_t dma;
62 unsigned int clkrt;
63 unsigned int cmdat;
64 volatile unsigned int imask; 49 volatile unsigned int imask;
65 unsigned int power_mode; 50 unsigned int power_mode;
66 unsigned int present; 51 unsigned int present;
@@ -74,7 +59,7 @@ struct imxmci_host {
74 struct tasklet_struct tasklet; 59 struct tasklet_struct tasklet;
75 unsigned int status_reg; 60 unsigned int status_reg;
76 unsigned long pending_events; 61 unsigned long pending_events;
77 /* Next to fields are there for CPU driven transfers to overcome SDHC deficiencies */ 62 /* Next two fields are there for CPU driven transfers to overcome SDHC deficiencies */
78 u16 *data_ptr; 63 u16 *data_ptr;
79 unsigned int data_cnt; 64 unsigned int data_cnt;
80 atomic_t stuck_timeout; 65 atomic_t stuck_timeout;
@@ -114,14 +99,22 @@ struct imxmci_host {
114static void imxmci_stop_clock(struct imxmci_host *host) 99static void imxmci_stop_clock(struct imxmci_host *host)
115{ 100{
116 int i = 0; 101 int i = 0;
117 MMC_STR_STP_CLK &= ~STR_STP_CLK_START_CLK; 102 u16 reg;
118 while(i < 0x1000) { 103
119 if(!(i & 0x7f)) 104 reg = readw(host->base + MMC_REG_STR_STP_CLK);
120 MMC_STR_STP_CLK |= STR_STP_CLK_STOP_CLK; 105 writew(reg & ~STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
106 while (i < 0x1000) {
107 if (!(i & 0x7f)) {
108 reg = readw(host->base + MMC_REG_STR_STP_CLK);
109 writew(reg | STR_STP_CLK_STOP_CLK,
110 host->base + MMC_REG_STR_STP_CLK);
111 }
121 112
122 if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) { 113 reg = readw(host->base + MMC_REG_STATUS);
114 if (!(reg & STATUS_CARD_BUS_CLK_RUN)) {
123 /* Check twice before cut */ 115 /* Check twice before cut */
124 if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) 116 reg = readw(host->base + MMC_REG_STATUS);
117 if (!(reg & STATUS_CARD_BUS_CLK_RUN))
125 return; 118 return;
126 } 119 }
127 120
@@ -135,8 +128,10 @@ static int imxmci_start_clock(struct imxmci_host *host)
135 unsigned int trials = 0; 128 unsigned int trials = 0;
136 unsigned int delay_limit = 128; 129 unsigned int delay_limit = 128;
137 unsigned long flags; 130 unsigned long flags;
131 u16 reg;
138 132
139 MMC_STR_STP_CLK &= ~STR_STP_CLK_STOP_CLK; 133 reg = readw(host->base + MMC_REG_STR_STP_CLK);
134 writew(reg & ~STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
140 135
141 clear_bit(IMXMCI_PEND_STARTED_b, &host->pending_events); 136 clear_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
142 137
@@ -145,18 +140,21 @@ static int imxmci_start_clock(struct imxmci_host *host)
145 * then 6 delay loops, but during card detection (low clockrate) 140 * then 6 delay loops, but during card detection (low clockrate)
146 * it takes up to 5000 delay loops and sometimes fails for the first time 141 * it takes up to 5000 delay loops and sometimes fails for the first time
147 */ 142 */
148 MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK; 143 reg = readw(host->base + MMC_REG_STR_STP_CLK);
144 writew(reg | STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
149 145
150 do { 146 do {
151 unsigned int delay = delay_limit; 147 unsigned int delay = delay_limit;
152 148
153 while(delay--){ 149 while (delay--) {
154 if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN) 150 reg = readw(host->base + MMC_REG_STATUS);
151 if (reg & STATUS_CARD_BUS_CLK_RUN)
155 /* Check twice before cut */ 152 /* Check twice before cut */
156 if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN) 153 reg = readw(host->base + MMC_REG_STATUS);
154 if (reg & STATUS_CARD_BUS_CLK_RUN)
157 return 0; 155 return 0;
158 156
159 if(test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) 157 if (test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
160 return 0; 158 return 0;
161 } 159 }
162 160
@@ -167,58 +165,59 @@ static int imxmci_start_clock(struct imxmci_host *host)
167 * IRQ or schedule delays this function execution and the clocks has 165 * IRQ or schedule delays this function execution and the clocks has
168 * been already stopped by other means (response processing, SDHC HW) 166 * been already stopped by other means (response processing, SDHC HW)
169 */ 167 */
170 if(!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) 168 if (!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) {
171 MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK; 169 reg = readw(host->base + MMC_REG_STR_STP_CLK);
170 writew(reg | STR_STP_CLK_START_CLK,
171 host->base + MMC_REG_STR_STP_CLK);
172 }
172 local_irq_restore(flags); 173 local_irq_restore(flags);
173 174
174 } while(++trials<256); 175 } while (++trials < 256);
175 176
176 dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n"); 177 dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n");
177 178
178 return -1; 179 return -1;
179} 180}
180 181
181static void imxmci_softreset(void) 182static void imxmci_softreset(struct imxmci_host *host)
182{ 183{
184 int i;
185
183 /* reset sequence */ 186 /* reset sequence */
184 MMC_STR_STP_CLK = 0x8; 187 writew(0x08, host->base + MMC_REG_STR_STP_CLK);
185 MMC_STR_STP_CLK = 0xD; 188 writew(0x0D, host->base + MMC_REG_STR_STP_CLK);
186 MMC_STR_STP_CLK = 0x5; 189
187 MMC_STR_STP_CLK = 0x5; 190 for (i = 0; i < 8; i++)
188 MMC_STR_STP_CLK = 0x5; 191 writew(0x05, host->base + MMC_REG_STR_STP_CLK);
189 MMC_STR_STP_CLK = 0x5; 192
190 MMC_STR_STP_CLK = 0x5; 193 writew(0xff, host->base + MMC_REG_RES_TO);
191 MMC_STR_STP_CLK = 0x5; 194 writew(512, host->base + MMC_REG_BLK_LEN);
192 MMC_STR_STP_CLK = 0x5; 195 writew(1, host->base + MMC_REG_NOB);
193 MMC_STR_STP_CLK = 0x5;
194
195 MMC_RES_TO = 0xff;
196 MMC_BLK_LEN = 512;
197 MMC_NOB = 1;
198} 196}
199 197
200static int imxmci_busy_wait_for_status(struct imxmci_host *host, 198static int imxmci_busy_wait_for_status(struct imxmci_host *host,
201 unsigned int *pstat, unsigned int stat_mask, 199 unsigned int *pstat, unsigned int stat_mask,
202 int timeout, const char *where) 200 int timeout, const char *where)
203{ 201{
204 int loops=0; 202 int loops = 0;
205 while(!(*pstat & stat_mask)) { 203
206 loops+=2; 204 while (!(*pstat & stat_mask)) {
207 if(loops >= timeout) { 205 loops += 2;
206 if (loops >= timeout) {
208 dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n", 207 dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n",
209 where, *pstat, stat_mask); 208 where, *pstat, stat_mask);
210 return -1; 209 return -1;
211 } 210 }
212 udelay(2); 211 udelay(2);
213 *pstat |= MMC_STATUS; 212 *pstat |= readw(host->base + MMC_REG_STATUS);
214 } 213 }
215 if(!loops) 214 if (!loops)
216 return 0; 215 return 0;
217 216
218 /* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */ 217 /* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */
219 if(!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock>=8000000)) 218 if (!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock >= 8000000))
220 dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n", 219 dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
221 loops, where, *pstat, stat_mask); 220 loops, where, *pstat, stat_mask);
222 return loops; 221 return loops;
223} 222}
224 223
@@ -235,8 +234,8 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
235 host->data = data; 234 host->data = data;
236 data->bytes_xfered = 0; 235 data->bytes_xfered = 0;
237 236
238 MMC_NOB = nob; 237 writew(nob, host->base + MMC_REG_NOB);
239 MMC_BLK_LEN = blksz; 238 writew(blksz, host->base + MMC_REG_BLK_LEN);
240 239
241 /* 240 /*
242 * DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise. 241 * DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise.
@@ -252,14 +251,14 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
252 host->dma_dir = DMA_FROM_DEVICE; 251 host->dma_dir = DMA_FROM_DEVICE;
253 252
254 /* Hack to enable read SCR */ 253 /* Hack to enable read SCR */
255 MMC_NOB = 1; 254 writew(1, host->base + MMC_REG_NOB);
256 MMC_BLK_LEN = 512; 255 writew(512, host->base + MMC_REG_BLK_LEN);
257 } else { 256 } else {
258 host->dma_dir = DMA_TO_DEVICE; 257 host->dma_dir = DMA_TO_DEVICE;
259 } 258 }
260 259
261 /* Convert back to virtual address */ 260 /* Convert back to virtual address */
262 host->data_ptr = (u16*)sg_virt(data->sg); 261 host->data_ptr = (u16 *)sg_virt(data->sg);
263 host->data_cnt = 0; 262 host->data_cnt = 0;
264 263
265 clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events); 264 clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
@@ -271,10 +270,11 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
271 if (data->flags & MMC_DATA_READ) { 270 if (data->flags & MMC_DATA_READ) {
272 host->dma_dir = DMA_FROM_DEVICE; 271 host->dma_dir = DMA_FROM_DEVICE;
273 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg, 272 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
274 data->sg_len, host->dma_dir); 273 data->sg_len, host->dma_dir);
275 274
276 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz, 275 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
277 host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_READ); 276 host->res->start + MMC_REG_BUFFER_ACCESS,
277 DMA_MODE_READ);
278 278
279 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/ 279 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/
280 CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN; 280 CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN;
@@ -282,10 +282,11 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
282 host->dma_dir = DMA_TO_DEVICE; 282 host->dma_dir = DMA_TO_DEVICE;
283 283
284 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg, 284 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
285 data->sg_len, host->dma_dir); 285 data->sg_len, host->dma_dir);
286 286
287 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz, 287 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
288 host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_WRITE); 288 host->res->start + MMC_REG_BUFFER_ACCESS,
289 DMA_MODE_WRITE);
289 290
290 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/ 291 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/
291 CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN; 292 CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN;
@@ -293,12 +294,12 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
293 294
294#if 1 /* This code is there only for consistency checking and can be disabled in future */ 295#if 1 /* This code is there only for consistency checking and can be disabled in future */
295 host->dma_size = 0; 296 host->dma_size = 0;
296 for(i=0; i<host->dma_nents; i++) 297 for (i = 0; i < host->dma_nents; i++)
297 host->dma_size+=data->sg[i].length; 298 host->dma_size += data->sg[i].length;
298 299
299 if (datasz > host->dma_size) { 300 if (datasz > host->dma_size) {
300 dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n", 301 dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n",
301 datasz, host->dma_size); 302 datasz, host->dma_size);
302 } 303 }
303#endif 304#endif
304 305
@@ -306,7 +307,7 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
306 307
307 wmb(); 308 wmb();
308 309
309 if(host->actual_bus_width == MMC_BUS_WIDTH_4) 310 if (host->actual_bus_width == MMC_BUS_WIDTH_4)
310 BLR(host->dma) = 0; /* burst 64 byte read / 64 bytes write */ 311 BLR(host->dma) = 0; /* burst 64 byte read / 64 bytes write */
311 else 312 else
312 BLR(host->dma) = 16; /* burst 16 byte read / 16 bytes write */ 313 BLR(host->dma) = 16; /* burst 16 byte read / 16 bytes write */
@@ -317,9 +318,8 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
317 clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events); 318 clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
318 319
319 /* start DMA engine for read, write is delayed after initial response */ 320 /* start DMA engine for read, write is delayed after initial response */
320 if (host->dma_dir == DMA_FROM_DEVICE) { 321 if (host->dma_dir == DMA_FROM_DEVICE)
321 imx_dma_enable(host->dma); 322 imx_dma_enable(host->dma);
322 }
323} 323}
324 324
325static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat) 325static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat)
@@ -351,16 +351,16 @@ static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd,
351 break; 351 break;
352 } 352 }
353 353
354 if ( test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events) ) 354 if (test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events))
355 cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */ 355 cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */
356 356
357 if ( host->actual_bus_width == MMC_BUS_WIDTH_4 ) 357 if (host->actual_bus_width == MMC_BUS_WIDTH_4)
358 cmdat |= CMD_DAT_CONT_BUS_WIDTH_4; 358 cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
359 359
360 MMC_CMD = cmd->opcode; 360 writew(cmd->opcode, host->base + MMC_REG_CMD);
361 MMC_ARGH = cmd->arg >> 16; 361 writew(cmd->arg >> 16, host->base + MMC_REG_ARGH);
362 MMC_ARGL = cmd->arg & 0xffff; 362 writew(cmd->arg & 0xffff, host->base + MMC_REG_ARGL);
363 MMC_CMD_DAT_CONT = cmdat; 363 writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT);
364 364
365 atomic_set(&host->stuck_timeout, 0); 365 atomic_set(&host->stuck_timeout, 0);
366 set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events); 366 set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events);
@@ -368,18 +368,18 @@ static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd,
368 368
369 imask = IMXMCI_INT_MASK_DEFAULT; 369 imask = IMXMCI_INT_MASK_DEFAULT;
370 imask &= ~INT_MASK_END_CMD_RES; 370 imask &= ~INT_MASK_END_CMD_RES;
371 if ( cmdat & CMD_DAT_CONT_DATA_ENABLE ) { 371 if (cmdat & CMD_DAT_CONT_DATA_ENABLE) {
372 /*imask &= ~INT_MASK_BUF_READY;*/ 372 /* imask &= ~INT_MASK_BUF_READY; */
373 imask &= ~INT_MASK_DATA_TRAN; 373 imask &= ~INT_MASK_DATA_TRAN;
374 if ( cmdat & CMD_DAT_CONT_WRITE ) 374 if (cmdat & CMD_DAT_CONT_WRITE)
375 imask &= ~INT_MASK_WRITE_OP_DONE; 375 imask &= ~INT_MASK_WRITE_OP_DONE;
376 if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) 376 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
377 imask &= ~INT_MASK_BUF_READY; 377 imask &= ~INT_MASK_BUF_READY;
378 } 378 }
379 379
380 spin_lock_irqsave(&host->lock, flags); 380 spin_lock_irqsave(&host->lock, flags);
381 host->imask = imask; 381 host->imask = imask;
382 MMC_INT_MASK = host->imask; 382 writew(host->imask, host->base + MMC_REG_INT_MASK);
383 spin_unlock_irqrestore(&host->lock, flags); 383 spin_unlock_irqrestore(&host->lock, flags);
384 384
385 dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n", 385 dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n",
@@ -395,14 +395,14 @@ static void imxmci_finish_request(struct imxmci_host *host, struct mmc_request *
395 spin_lock_irqsave(&host->lock, flags); 395 spin_lock_irqsave(&host->lock, flags);
396 396
397 host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m | 397 host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m |
398 IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m); 398 IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m);
399 399
400 host->imask = IMXMCI_INT_MASK_DEFAULT; 400 host->imask = IMXMCI_INT_MASK_DEFAULT;
401 MMC_INT_MASK = host->imask; 401 writew(host->imask, host->base + MMC_REG_INT_MASK);
402 402
403 spin_unlock_irqrestore(&host->lock, flags); 403 spin_unlock_irqrestore(&host->lock, flags);
404 404
405 if(req && req->cmd) 405 if (req && req->cmd)
406 host->prev_cmd_code = req->cmd->opcode; 406 host->prev_cmd_code = req->cmd->opcode;
407 407
408 host->req = NULL; 408 host->req = NULL;
@@ -416,17 +416,17 @@ static int imxmci_finish_data(struct imxmci_host *host, unsigned int stat)
416 struct mmc_data *data = host->data; 416 struct mmc_data *data = host->data;
417 int data_error; 417 int data_error;
418 418
419 if(test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)){ 419 if (test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
420 imx_dma_disable(host->dma); 420 imx_dma_disable(host->dma);
421 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents, 421 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
422 host->dma_dir); 422 host->dma_dir);
423 } 423 }
424 424
425 if ( stat & STATUS_ERR_MASK ) { 425 if (stat & STATUS_ERR_MASK) {
426 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",stat); 426 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", stat);
427 if(stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR)) 427 if (stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR))
428 data->error = -EILSEQ; 428 data->error = -EILSEQ;
429 else if(stat & STATUS_TIME_OUT_READ) 429 else if (stat & STATUS_TIME_OUT_READ)
430 data->error = -ETIMEDOUT; 430 data->error = -ETIMEDOUT;
431 else 431 else
432 data->error = -EIO; 432 data->error = -EIO;
@@ -445,7 +445,7 @@ static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
445{ 445{
446 struct mmc_command *cmd = host->cmd; 446 struct mmc_command *cmd = host->cmd;
447 int i; 447 int i;
448 u32 a,b,c; 448 u32 a, b, c;
449 struct mmc_data *data = host->data; 449 struct mmc_data *data = host->data;
450 450
451 if (!cmd) 451 if (!cmd)
@@ -461,18 +461,18 @@ static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
461 cmd->error = -EILSEQ; 461 cmd->error = -EILSEQ;
462 } 462 }
463 463
464 if(cmd->flags & MMC_RSP_PRESENT) { 464 if (cmd->flags & MMC_RSP_PRESENT) {
465 if(cmd->flags & MMC_RSP_136) { 465 if (cmd->flags & MMC_RSP_136) {
466 for (i = 0; i < 4; i++) { 466 for (i = 0; i < 4; i++) {
467 u32 a = MMC_RES_FIFO & 0xffff; 467 a = readw(host->base + MMC_REG_RES_FIFO);
468 u32 b = MMC_RES_FIFO & 0xffff; 468 b = readw(host->base + MMC_REG_RES_FIFO);
469 cmd->resp[i] = a<<16 | b; 469 cmd->resp[i] = a << 16 | b;
470 } 470 }
471 } else { 471 } else {
472 a = MMC_RES_FIFO & 0xffff; 472 a = readw(host->base + MMC_REG_RES_FIFO);
473 b = MMC_RES_FIFO & 0xffff; 473 b = readw(host->base + MMC_REG_RES_FIFO);
474 c = MMC_RES_FIFO & 0xffff; 474 c = readw(host->base + MMC_REG_RES_FIFO);
475 cmd->resp[0] = a<<24 | b<<8 | c>>8; 475 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
476 } 476 }
477 } 477 }
478 478
@@ -484,36 +484,34 @@ static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
484 484
485 /* Wait for FIFO to be empty before starting DMA write */ 485 /* Wait for FIFO to be empty before starting DMA write */
486 486
487 stat = MMC_STATUS; 487 stat = readw(host->base + MMC_REG_STATUS);
488 if(imxmci_busy_wait_for_status(host, &stat, 488 if (imxmci_busy_wait_for_status(host, &stat,
489 STATUS_APPL_BUFF_FE, 489 STATUS_APPL_BUFF_FE,
490 40, "imxmci_cmd_done DMA WR") < 0) { 490 40, "imxmci_cmd_done DMA WR") < 0) {
491 cmd->error = -EIO; 491 cmd->error = -EIO;
492 imxmci_finish_data(host, stat); 492 imxmci_finish_data(host, stat);
493 if(host->req) 493 if (host->req)
494 imxmci_finish_request(host, host->req); 494 imxmci_finish_request(host, host->req);
495 dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n", 495 dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n",
496 stat); 496 stat);
497 return 0; 497 return 0;
498 } 498 }
499 499
500 if(test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) { 500 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
501 imx_dma_enable(host->dma); 501 imx_dma_enable(host->dma);
502 }
503 } 502 }
504 } else { 503 } else {
505 struct mmc_request *req; 504 struct mmc_request *req;
506 imxmci_stop_clock(host); 505 imxmci_stop_clock(host);
507 req = host->req; 506 req = host->req;
508 507
509 if(data) 508 if (data)
510 imxmci_finish_data(host, stat); 509 imxmci_finish_data(host, stat);
511 510
512 if( req ) { 511 if (req)
513 imxmci_finish_request(host, req); 512 imxmci_finish_request(host, req);
514 } else { 513 else
515 dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n"); 514 dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n");
516 }
517 } 515 }
518 516
519 return 1; 517 return 1;
@@ -535,11 +533,10 @@ static int imxmci_data_done(struct imxmci_host *host, unsigned int stat)
535 } else { 533 } else {
536 struct mmc_request *req; 534 struct mmc_request *req;
537 req = host->req; 535 req = host->req;
538 if( req ) { 536 if (req)
539 imxmci_finish_request(host, req); 537 imxmci_finish_request(host, req);
540 } else { 538 else
541 dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n"); 539 dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n");
542 }
543 } 540 }
544 541
545 return 1; 542 return 1;
@@ -552,7 +549,7 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
552 int trans_done = 0; 549 int trans_done = 0;
553 unsigned int stat = *pstat; 550 unsigned int stat = *pstat;
554 551
555 if(host->actual_bus_width != MMC_BUS_WIDTH_4) 552 if (host->actual_bus_width != MMC_BUS_WIDTH_4)
556 burst_len = 16; 553 burst_len = 16;
557 else 554 else
558 burst_len = 64; 555 burst_len = 64;
@@ -563,44 +560,44 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
563 560
564 udelay(20); /* required for clocks < 8MHz*/ 561 udelay(20); /* required for clocks < 8MHz*/
565 562
566 if(host->dma_dir == DMA_FROM_DEVICE) { 563 if (host->dma_dir == DMA_FROM_DEVICE) {
567 imxmci_busy_wait_for_status(host, &stat, 564 imxmci_busy_wait_for_status(host, &stat,
568 STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE | 565 STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE |
569 STATUS_TIME_OUT_READ, 566 STATUS_TIME_OUT_READ,
570 50, "imxmci_cpu_driven_data read"); 567 50, "imxmci_cpu_driven_data read");
571 568
572 while((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) && 569 while ((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) &&
573 !(stat & STATUS_TIME_OUT_READ) && 570 !(stat & STATUS_TIME_OUT_READ) &&
574 (host->data_cnt < 512)) { 571 (host->data_cnt < 512)) {
575 572
576 udelay(20); /* required for clocks < 8MHz*/ 573 udelay(20); /* required for clocks < 8MHz*/
577 574
578 for(i = burst_len; i>=2 ; i-=2) { 575 for (i = burst_len; i >= 2 ; i -= 2) {
579 u16 data; 576 u16 data;
580 data = MMC_BUFFER_ACCESS; 577 data = readw(host->base + MMC_REG_BUFFER_ACCESS);
581 udelay(10); /* required for clocks < 8MHz*/ 578 udelay(10); /* required for clocks < 8MHz*/
582 if(host->data_cnt+2 <= host->dma_size) { 579 if (host->data_cnt+2 <= host->dma_size) {
583 *(host->data_ptr++) = data; 580 *(host->data_ptr++) = data;
584 } else { 581 } else {
585 if(host->data_cnt < host->dma_size) 582 if (host->data_cnt < host->dma_size)
586 *(u8*)(host->data_ptr) = data; 583 *(u8 *)(host->data_ptr) = data;
587 } 584 }
588 host->data_cnt += 2; 585 host->data_cnt += 2;
589 } 586 }
590 587
591 stat = MMC_STATUS; 588 stat = readw(host->base + MMC_REG_STATUS);
592 589
593 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n", 590 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n",
594 host->data_cnt, burst_len, stat); 591 host->data_cnt, burst_len, stat);
595 } 592 }
596 593
597 if((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512)) 594 if ((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512))
598 trans_done = 1; 595 trans_done = 1;
599 596
600 if(host->dma_size & 0x1ff) 597 if (host->dma_size & 0x1ff)
601 stat &= ~STATUS_CRC_READ_ERR; 598 stat &= ~STATUS_CRC_READ_ERR;
602 599
603 if(stat & STATUS_TIME_OUT_READ) { 600 if (stat & STATUS_TIME_OUT_READ) {
604 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n", 601 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n",
605 stat); 602 stat);
606 trans_done = -1; 603 trans_done = -1;
@@ -608,12 +605,12 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
608 605
609 } else { 606 } else {
610 imxmci_busy_wait_for_status(host, &stat, 607 imxmci_busy_wait_for_status(host, &stat,
611 STATUS_APPL_BUFF_FE, 608 STATUS_APPL_BUFF_FE,
612 20, "imxmci_cpu_driven_data write"); 609 20, "imxmci_cpu_driven_data write");
613 610
614 while((stat & STATUS_APPL_BUFF_FE) && 611 while ((stat & STATUS_APPL_BUFF_FE) &&
615 (host->data_cnt < host->dma_size)) { 612 (host->data_cnt < host->dma_size)) {
616 if(burst_len >= host->dma_size - host->data_cnt) { 613 if (burst_len >= host->dma_size - host->data_cnt) {
617 burst_len = host->dma_size - host->data_cnt; 614 burst_len = host->dma_size - host->data_cnt;
618 host->data_cnt = host->dma_size; 615 host->data_cnt = host->dma_size;
619 trans_done = 1; 616 trans_done = 1;
@@ -621,10 +618,10 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
621 host->data_cnt += burst_len; 618 host->data_cnt += burst_len;
622 } 619 }
623 620
624 for(i = burst_len; i>0 ; i-=2) 621 for (i = burst_len; i > 0 ; i -= 2)
625 MMC_BUFFER_ACCESS = *(host->data_ptr++); 622 writew(*(host->data_ptr++), host->base + MMC_REG_BUFFER_ACCESS);
626 623
627 stat = MMC_STATUS; 624 stat = readw(host->base + MMC_REG_STATUS);
628 625
629 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n", 626 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n",
630 burst_len, stat); 627 burst_len, stat);
@@ -639,7 +636,7 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
639static void imxmci_dma_irq(int dma, void *devid) 636static void imxmci_dma_irq(int dma, void *devid)
640{ 637{
641 struct imxmci_host *host = devid; 638 struct imxmci_host *host = devid;
642 uint32_t stat = MMC_STATUS; 639 u32 stat = readw(host->base + MMC_REG_STATUS);
643 640
644 atomic_set(&host->stuck_timeout, 0); 641 atomic_set(&host->stuck_timeout, 0);
645 host->status_reg = stat; 642 host->status_reg = stat;
@@ -650,10 +647,11 @@ static void imxmci_dma_irq(int dma, void *devid)
650static irqreturn_t imxmci_irq(int irq, void *devid) 647static irqreturn_t imxmci_irq(int irq, void *devid)
651{ 648{
652 struct imxmci_host *host = devid; 649 struct imxmci_host *host = devid;
653 uint32_t stat = MMC_STATUS; 650 u32 stat = readw(host->base + MMC_REG_STATUS);
654 int handled = 1; 651 int handled = 1;
655 652
656 MMC_INT_MASK = host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT; 653 writew(host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT,
654 host->base + MMC_REG_INT_MASK);
657 655
658 atomic_set(&host->stuck_timeout, 0); 656 atomic_set(&host->stuck_timeout, 0);
659 host->status_reg = stat; 657 host->status_reg = stat;
@@ -671,10 +669,10 @@ static void imxmci_tasklet_fnc(unsigned long data)
671 unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */ 669 unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */
672 int timeout = 0; 670 int timeout = 0;
673 671
674 if(atomic_read(&host->stuck_timeout) > 4) { 672 if (atomic_read(&host->stuck_timeout) > 4) {
675 char *what; 673 char *what;
676 timeout = 1; 674 timeout = 1;
677 stat = MMC_STATUS; 675 stat = readw(host->base + MMC_REG_STATUS);
678 host->status_reg = stat; 676 host->status_reg = stat;
679 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) 677 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
680 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) 678 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
@@ -683,29 +681,37 @@ static void imxmci_tasklet_fnc(unsigned long data)
683 what = "RESP"; 681 what = "RESP";
684 else 682 else
685 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) 683 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
686 if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events)) 684 if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events))
687 what = "DATA"; 685 what = "DATA";
688 else 686 else
689 what = "DMA"; 687 what = "DMA";
690 else 688 else
691 what = "???"; 689 what = "???";
692 690
693 dev_err(mmc_dev(host->mmc), "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n", 691 dev_err(mmc_dev(host->mmc),
694 what, stat, MMC_INT_MASK); 692 "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
695 dev_err(mmc_dev(host->mmc), "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n", 693 what, stat,
696 MMC_CMD_DAT_CONT, MMC_BLK_LEN, MMC_NOB, CCR(host->dma)); 694 readw(host->base + MMC_REG_INT_MASK));
695 dev_err(mmc_dev(host->mmc),
696 "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
697 readw(host->base + MMC_REG_CMD_DAT_CONT),
698 readw(host->base + MMC_REG_BLK_LEN),
699 readw(host->base + MMC_REG_NOB),
700 CCR(host->dma));
697 dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n", 701 dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n",
698 host->cmd?host->cmd->opcode:0, host->prev_cmd_code, 1<<host->actual_bus_width, host->dma_size); 702 host->cmd ? host->cmd->opcode : 0,
703 host->prev_cmd_code,
704 1 << host->actual_bus_width, host->dma_size);
699 } 705 }
700 706
701 if(!host->present || timeout) 707 if (!host->present || timeout)
702 host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ | 708 host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ |
703 STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR; 709 STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR;
704 710
705 if(test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) { 711 if (test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) {
706 clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events); 712 clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
707 713
708 stat = MMC_STATUS; 714 stat = readw(host->base + MMC_REG_STATUS);
709 /* 715 /*
710 * This is not required in theory, but there is chance to miss some flag 716 * This is not required in theory, but there is chance to miss some flag
711 * which clears automatically by mask write, FreeScale original code keeps 717 * which clears automatically by mask write, FreeScale original code keeps
@@ -713,63 +719,62 @@ static void imxmci_tasklet_fnc(unsigned long data)
713 */ 719 */
714 stat |= host->status_reg; 720 stat |= host->status_reg;
715 721
716 if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) 722 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
717 stat &= ~STATUS_CRC_READ_ERR; 723 stat &= ~STATUS_CRC_READ_ERR;
718 724
719 if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) { 725 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
720 imxmci_busy_wait_for_status(host, &stat, 726 imxmci_busy_wait_for_status(host, &stat,
721 STATUS_END_CMD_RESP | STATUS_ERR_MASK, 727 STATUS_END_CMD_RESP | STATUS_ERR_MASK,
722 20, "imxmci_tasklet_fnc resp (ERRATUM #4)"); 728 20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
723 } 729 }
724 730
725 if(stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) { 731 if (stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) {
726 if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) 732 if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
727 imxmci_cmd_done(host, stat); 733 imxmci_cmd_done(host, stat);
728 if(host->data && (stat & STATUS_ERR_MASK)) 734 if (host->data && (stat & STATUS_ERR_MASK))
729 imxmci_data_done(host, stat); 735 imxmci_data_done(host, stat);
730 } 736 }
731 737
732 if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) { 738 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) {
733 stat |= MMC_STATUS; 739 stat |= readw(host->base + MMC_REG_STATUS);
734 if(imxmci_cpu_driven_data(host, &stat)){ 740 if (imxmci_cpu_driven_data(host, &stat)) {
735 if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) 741 if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
736 imxmci_cmd_done(host, stat); 742 imxmci_cmd_done(host, stat);
737 atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m, 743 atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m,
738 &host->pending_events); 744 &host->pending_events);
739 imxmci_data_done(host, stat); 745 imxmci_data_done(host, stat);
740 } 746 }
741 } 747 }
742 } 748 }
743 749
744 if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) && 750 if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) &&
745 !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) { 751 !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
746 752
747 stat = MMC_STATUS; 753 stat = readw(host->base + MMC_REG_STATUS);
748 /* Same as above */ 754 /* Same as above */
749 stat |= host->status_reg; 755 stat |= host->status_reg;
750 756
751 if(host->dma_dir == DMA_TO_DEVICE) { 757 if (host->dma_dir == DMA_TO_DEVICE)
752 data_dir_mask = STATUS_WRITE_OP_DONE; 758 data_dir_mask = STATUS_WRITE_OP_DONE;
753 } else { 759 else
754 data_dir_mask = STATUS_DATA_TRANS_DONE; 760 data_dir_mask = STATUS_DATA_TRANS_DONE;
755 }
756 761
757 if(stat & data_dir_mask) { 762 if (stat & data_dir_mask) {
758 clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events); 763 clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
759 imxmci_data_done(host, stat); 764 imxmci_data_done(host, stat);
760 } 765 }
761 } 766 }
762 767
763 if(test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) { 768 if (test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) {
764 769
765 if(host->cmd) 770 if (host->cmd)
766 imxmci_cmd_done(host, STATUS_TIME_OUT_RESP); 771 imxmci_cmd_done(host, STATUS_TIME_OUT_RESP);
767 772
768 if(host->data) 773 if (host->data)
769 imxmci_data_done(host, STATUS_TIME_OUT_READ | 774 imxmci_data_done(host, STATUS_TIME_OUT_READ |
770 STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR); 775 STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR);
771 776
772 if(host->req) 777 if (host->req)
773 imxmci_finish_request(host, host->req); 778 imxmci_finish_request(host, host->req);
774 779
775 mmc_detect_change(host->mmc, msecs_to_jiffies(100)); 780 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
@@ -796,9 +801,8 @@ static void imxmci_request(struct mmc_host *mmc, struct mmc_request *req)
796 if (req->data->flags & MMC_DATA_WRITE) 801 if (req->data->flags & MMC_DATA_WRITE)
797 cmdat |= CMD_DAT_CONT_WRITE; 802 cmdat |= CMD_DAT_CONT_WRITE;
798 803
799 if (req->data->flags & MMC_DATA_STREAM) { 804 if (req->data->flags & MMC_DATA_STREAM)
800 cmdat |= CMD_DAT_CONT_STREAM_BLOCK; 805 cmdat |= CMD_DAT_CONT_STREAM_BLOCK;
801 }
802 } 806 }
803 807
804 imxmci_start_cmd(host, req->cmd, cmdat); 808 imxmci_start_cmd(host, req->cmd, cmdat);
@@ -811,36 +815,37 @@ static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
811 struct imxmci_host *host = mmc_priv(mmc); 815 struct imxmci_host *host = mmc_priv(mmc);
812 int prescaler; 816 int prescaler;
813 817
814 if( ios->bus_width==MMC_BUS_WIDTH_4 ) { 818 if (ios->bus_width == MMC_BUS_WIDTH_4) {
815 host->actual_bus_width = MMC_BUS_WIDTH_4; 819 host->actual_bus_width = MMC_BUS_WIDTH_4;
816 imx_gpio_mode(PB11_PF_SD_DAT3); 820 imx_gpio_mode(PB11_PF_SD_DAT3);
817 }else{ 821 } else {
818 host->actual_bus_width = MMC_BUS_WIDTH_1; 822 host->actual_bus_width = MMC_BUS_WIDTH_1;
819 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11); 823 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
820 } 824 }
821 825
822 if ( host->power_mode != ios->power_mode ) { 826 if (host->power_mode != ios->power_mode) {
823 switch (ios->power_mode) { 827 switch (ios->power_mode) {
824 case MMC_POWER_OFF: 828 case MMC_POWER_OFF:
825 break; 829 break;
826 case MMC_POWER_UP: 830 case MMC_POWER_UP:
827 set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events); 831 set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
828 break; 832 break;
829 case MMC_POWER_ON: 833 case MMC_POWER_ON:
830 break; 834 break;
831 } 835 }
832 host->power_mode = ios->power_mode; 836 host->power_mode = ios->power_mode;
833 } 837 }
834 838
835 if ( ios->clock ) { 839 if (ios->clock) {
836 unsigned int clk; 840 unsigned int clk;
841 u16 reg;
837 842
838 /* The prescaler is 5 for PERCLK2 equal to 96MHz 843 /* The prescaler is 5 for PERCLK2 equal to 96MHz
839 * then 96MHz / 5 = 19.2 MHz 844 * then 96MHz / 5 = 19.2 MHz
840 */ 845 */
841 clk = clk_get_rate(host->clk); 846 clk = clk_get_rate(host->clk);
842 prescaler=(clk+(CLK_RATE*7)/8)/CLK_RATE; 847 prescaler = (clk + (CLK_RATE * 7) / 8) / CLK_RATE;
843 switch(prescaler) { 848 switch (prescaler) {
844 case 0: 849 case 0:
845 case 1: prescaler = 0; 850 case 1: prescaler = 0;
846 break; 851 break;
@@ -858,24 +863,29 @@ static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
858 dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n", 863 dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n",
859 clk, prescaler); 864 clk, prescaler);
860 865
861 for(clk=0; clk<8; clk++) { 866 for (clk = 0; clk < 8; clk++) {
862 int x; 867 int x;
863 x = CLK_RATE / (1<<clk); 868 x = CLK_RATE / (1 << clk);
864 if( x <= ios->clock) 869 if (x <= ios->clock)
865 break; 870 break;
866 } 871 }
867 872
868 MMC_STR_STP_CLK |= STR_STP_CLK_ENABLE; /* enable controller */ 873 /* enable controller */
874 reg = readw(host->base + MMC_REG_STR_STP_CLK);
875 writew(reg | STR_STP_CLK_ENABLE,
876 host->base + MMC_REG_STR_STP_CLK);
869 877
870 imxmci_stop_clock(host); 878 imxmci_stop_clock(host);
871 MMC_CLK_RATE = (prescaler<<3) | clk; 879 writew((prescaler << 3) | clk, host->base + MMC_REG_CLK_RATE);
872 /* 880 /*
873 * Under my understanding, clock should not be started there, because it would 881 * Under my understanding, clock should not be started there, because it would
874 * initiate SDHC sequencer and send last or random command into card 882 * initiate SDHC sequencer and send last or random command into card
875 */ 883 */
876 /*imxmci_start_clock(host);*/ 884 /* imxmci_start_clock(host); */
877 885
878 dev_dbg(mmc_dev(host->mmc), "MMC_CLK_RATE: 0x%08x\n", MMC_CLK_RATE); 886 dev_dbg(mmc_dev(host->mmc),
887 "MMC_CLK_RATE: 0x%08x\n",
888 readw(host->base + MMC_REG_CLK_RATE));
879 } else { 889 } else {
880 imxmci_stop_clock(host); 890 imxmci_stop_clock(host);
881 } 891 }
@@ -915,10 +925,10 @@ static void imxmci_check_status(unsigned long data)
915 tasklet_schedule(&host->tasklet); 925 tasklet_schedule(&host->tasklet);
916 } 926 }
917 927
918 if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) || 928 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) ||
919 test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) { 929 test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
920 atomic_inc(&host->stuck_timeout); 930 atomic_inc(&host->stuck_timeout);
921 if(atomic_read(&host->stuck_timeout) > 4) 931 if (atomic_read(&host->stuck_timeout) > 4)
922 tasklet_schedule(&host->tasklet); 932 tasklet_schedule(&host->tasklet);
923 } else { 933 } else {
924 atomic_set(&host->stuck_timeout, 0); 934 atomic_set(&host->stuck_timeout, 0);
@@ -934,6 +944,7 @@ static int imxmci_probe(struct platform_device *pdev)
934 struct imxmci_host *host = NULL; 944 struct imxmci_host *host = NULL;
935 struct resource *r; 945 struct resource *r;
936 int ret = 0, irq; 946 int ret = 0, irq;
947 u16 rev_no;
937 948
938 printk(KERN_INFO "i.MX mmc driver\n"); 949 printk(KERN_INFO "i.MX mmc driver\n");
939 950
@@ -942,7 +953,8 @@ static int imxmci_probe(struct platform_device *pdev)
942 if (!r || irq < 0) 953 if (!r || irq < 0)
943 return -ENXIO; 954 return -ENXIO;
944 955
945 if (!request_mem_region(r->start, 0x100, pdev->name)) 956 r = request_mem_region(r->start, resource_size(r), pdev->name);
957 if (!r)
946 return -EBUSY; 958 return -EBUSY;
947 959
948 mmc = mmc_alloc_host(sizeof(struct imxmci_host), &pdev->dev); 960 mmc = mmc_alloc_host(sizeof(struct imxmci_host), &pdev->dev);
@@ -966,6 +978,12 @@ static int imxmci_probe(struct platform_device *pdev)
966 mmc->max_blk_count = 65535; 978 mmc->max_blk_count = 65535;
967 979
968 host = mmc_priv(mmc); 980 host = mmc_priv(mmc);
981 host->base = ioremap(r->start, resource_size(r));
982 if (!host->base) {
983 ret = -ENOMEM;
984 goto out;
985 }
986
969 host->mmc = mmc; 987 host->mmc = mmc;
970 host->dma_allocated = 0; 988 host->dma_allocated = 0;
971 host->pdata = pdev->dev.platform_data; 989 host->pdata = pdev->dev.platform_data;
@@ -993,18 +1011,20 @@ static int imxmci_probe(struct platform_device *pdev)
993 imx_gpio_mode(PB12_PF_SD_CLK); 1011 imx_gpio_mode(PB12_PF_SD_CLK);
994 imx_gpio_mode(PB13_PF_SD_CMD); 1012 imx_gpio_mode(PB13_PF_SD_CMD);
995 1013
996 imxmci_softreset(); 1014 imxmci_softreset(host);
997 1015
998 if ( MMC_REV_NO != 0x390 ) { 1016 rev_no = readw(host->base + MMC_REG_REV_NO);
1017 if (rev_no != 0x390) {
999 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n", 1018 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
1000 MMC_REV_NO); 1019 readw(host->base + MMC_REG_REV_NO));
1001 goto out; 1020 goto out;
1002 } 1021 }
1003 1022
1004 MMC_READ_TO = 0x2db4; /* recommended in data sheet */ 1023 /* recommended in data sheet */
1024 writew(0x2db4, host->base + MMC_REG_READ_TO);
1005 1025
1006 host->imask = IMXMCI_INT_MASK_DEFAULT; 1026 host->imask = IMXMCI_INT_MASK_DEFAULT;
1007 MMC_INT_MASK = host->imask; 1027 writew(host->imask, host->base + MMC_REG_INT_MASK);
1008 1028
1009 host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW); 1029 host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
1010 if(host->dma < 0) { 1030 if(host->dma < 0) {
@@ -1012,7 +1032,7 @@ static int imxmci_probe(struct platform_device *pdev)
1012 ret = -EBUSY; 1032 ret = -EBUSY;
1013 goto out; 1033 goto out;
1014 } 1034 }
1015 host->dma_allocated=1; 1035 host->dma_allocated = 1;
1016 imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host); 1036 imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host);
1017 1037
1018 tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host); 1038 tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host);
@@ -1032,7 +1052,7 @@ static int imxmci_probe(struct platform_device *pdev)
1032 host->timer.data = (unsigned long)host; 1052 host->timer.data = (unsigned long)host;
1033 host->timer.function = imxmci_check_status; 1053 host->timer.function = imxmci_check_status;
1034 add_timer(&host->timer); 1054 add_timer(&host->timer);
1035 mod_timer(&host->timer, jiffies + (HZ>>1)); 1055 mod_timer(&host->timer, jiffies + (HZ >> 1));
1036 1056
1037 platform_set_drvdata(pdev, mmc); 1057 platform_set_drvdata(pdev, mmc);
1038 1058
@@ -1042,18 +1062,20 @@ static int imxmci_probe(struct platform_device *pdev)
1042 1062
1043out: 1063out:
1044 if (host) { 1064 if (host) {
1045 if(host->dma_allocated){ 1065 if (host->dma_allocated) {
1046 imx_dma_free(host->dma); 1066 imx_dma_free(host->dma);
1047 host->dma_allocated=0; 1067 host->dma_allocated = 0;
1048 } 1068 }
1049 if (host->clk) { 1069 if (host->clk) {
1050 clk_disable(host->clk); 1070 clk_disable(host->clk);
1051 clk_put(host->clk); 1071 clk_put(host->clk);
1052 } 1072 }
1073 if (host->base)
1074 iounmap(host->base);
1053 } 1075 }
1054 if (mmc) 1076 if (mmc)
1055 mmc_free_host(mmc); 1077 mmc_free_host(mmc);
1056 release_mem_region(r->start, 0x100); 1078 release_mem_region(r->start, resource_size(r));
1057 return ret; 1079 return ret;
1058} 1080}
1059 1081
@@ -1072,9 +1094,10 @@ static int imxmci_remove(struct platform_device *pdev)
1072 mmc_remove_host(mmc); 1094 mmc_remove_host(mmc);
1073 1095
1074 free_irq(host->irq, host); 1096 free_irq(host->irq, host);
1075 if(host->dma_allocated){ 1097 iounmap(host->base);
1098 if (host->dma_allocated) {
1076 imx_dma_free(host->dma); 1099 imx_dma_free(host->dma);
1077 host->dma_allocated=0; 1100 host->dma_allocated = 0;
1078 } 1101 }
1079 1102
1080 tasklet_kill(&host->tasklet); 1103 tasklet_kill(&host->tasklet);
@@ -1082,7 +1105,7 @@ static int imxmci_remove(struct platform_device *pdev)
1082 clk_disable(host->clk); 1105 clk_disable(host->clk);
1083 clk_put(host->clk); 1106 clk_put(host->clk);
1084 1107
1085 release_mem_region(host->res->start, 0x100); 1108 release_mem_region(host->res->start, resource_size(host->res));
1086 1109
1087 mmc_free_host(mmc); 1110 mmc_free_host(mmc);
1088 } 1111 }
@@ -1109,7 +1132,7 @@ static int imxmci_resume(struct platform_device *dev)
1109 1132
1110 if (mmc) { 1133 if (mmc) {
1111 host = mmc_priv(mmc); 1134 host = mmc_priv(mmc);
1112 if(host) 1135 if (host)
1113 set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events); 1136 set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
1114 ret = mmc_resume_host(mmc); 1137 ret = mmc_resume_host(mmc);
1115 } 1138 }
diff --git a/drivers/mmc/host/imxmmc.h b/drivers/mmc/host/imxmmc.h
index e5339e334dbb..09d5d4ee3a77 100644
--- a/drivers/mmc/host/imxmmc.h
+++ b/drivers/mmc/host/imxmmc.h
@@ -1,24 +1,21 @@
1#define MMC_REG_STR_STP_CLK 0x00
2#define MMC_REG_STATUS 0x04
3#define MMC_REG_CLK_RATE 0x08
4#define MMC_REG_CMD_DAT_CONT 0x0C
5#define MMC_REG_RES_TO 0x10
6#define MMC_REG_READ_TO 0x14
7#define MMC_REG_BLK_LEN 0x18
8#define MMC_REG_NOB 0x1C
9#define MMC_REG_REV_NO 0x20
10#define MMC_REG_INT_MASK 0x24
11#define MMC_REG_CMD 0x28
12#define MMC_REG_ARGH 0x2C
13#define MMC_REG_ARGL 0x30
14#define MMC_REG_RES_FIFO 0x34
15#define MMC_REG_BUFFER_ACCESS 0x38
1 16
2# define __REG16(x) (*((volatile u16 *)IO_ADDRESS(x))) 17#define STR_STP_CLK_IPG_CLK_GATE_DIS (1<<15)
3 18#define STR_STP_CLK_IPG_PERCLK_GATE_DIS (1<<14)
4#define MMC_STR_STP_CLK __REG16(IMX_MMC_BASE + 0x00)
5#define MMC_STATUS __REG16(IMX_MMC_BASE + 0x04)
6#define MMC_CLK_RATE __REG16(IMX_MMC_BASE + 0x08)
7#define MMC_CMD_DAT_CONT __REG16(IMX_MMC_BASE + 0x0C)
8#define MMC_RES_TO __REG16(IMX_MMC_BASE + 0x10)
9#define MMC_READ_TO __REG16(IMX_MMC_BASE + 0x14)
10#define MMC_BLK_LEN __REG16(IMX_MMC_BASE + 0x18)
11#define MMC_NOB __REG16(IMX_MMC_BASE + 0x1C)
12#define MMC_REV_NO __REG16(IMX_MMC_BASE + 0x20)
13#define MMC_INT_MASK __REG16(IMX_MMC_BASE + 0x24)
14#define MMC_CMD __REG16(IMX_MMC_BASE + 0x28)
15#define MMC_ARGH __REG16(IMX_MMC_BASE + 0x2C)
16#define MMC_ARGL __REG16(IMX_MMC_BASE + 0x30)
17#define MMC_RES_FIFO __REG16(IMX_MMC_BASE + 0x34)
18#define MMC_BUFFER_ACCESS __REG16(IMX_MMC_BASE + 0x38)
19#define MMC_BUFFER_ACCESS_OFS 0x38
20
21
22#define STR_STP_CLK_ENDIAN (1<<5) 19#define STR_STP_CLK_ENDIAN (1<<5)
23#define STR_STP_CLK_RESET (1<<3) 20#define STR_STP_CLK_RESET (1<<3)
24#define STR_STP_CLK_ENABLE (1<<2) 21#define STR_STP_CLK_ENABLE (1<<2)
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 1c2e9450d663..f8ae0400c49c 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -408,7 +408,7 @@ config MTD_NAND_FSL_UPM
408 408
409config MTD_NAND_MXC 409config MTD_NAND_MXC
410 tristate "MXC NAND support" 410 tristate "MXC NAND support"
411 depends on ARCH_MX2 411 depends on ARCH_MX2 || ARCH_MX3
412 help 412 help
413 This enables the driver for the NAND flash controller on the 413 This enables the driver for the NAND flash controller on the
414 MXC processors. 414 MXC processors.
diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c
index 3f90f1bbbbcd..73dea88cceb3 100644
--- a/drivers/serial/imx.c
+++ b/drivers/serial/imx.c
@@ -66,7 +66,7 @@
66#define ONEMS 0xb0 /* One Millisecond register */ 66#define ONEMS 0xb0 /* One Millisecond register */
67#define UTS 0xb4 /* UART Test Register */ 67#define UTS 0xb4 /* UART Test Register */
68#endif 68#endif
69#ifdef CONFIG_ARCH_IMX 69#if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1)
70#define BIPR1 0xb0 /* Incremental Preset Register 1 */ 70#define BIPR1 0xb0 /* Incremental Preset Register 1 */
71#define BIPR2 0xb4 /* Incremental Preset Register 2 */ 71#define BIPR2 0xb4 /* Incremental Preset Register 2 */
72#define BIPR3 0xb8 /* Incremental Preset Register 3 */ 72#define BIPR3 0xb8 /* Incremental Preset Register 3 */
@@ -96,7 +96,7 @@
96#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 96#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
97#define UCR1_SNDBRK (1<<4) /* Send break */ 97#define UCR1_SNDBRK (1<<4) /* Send break */
98#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 98#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
99#ifdef CONFIG_ARCH_IMX 99#if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1)
100#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ 100#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
101#endif 101#endif
102#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2 102#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
@@ -187,7 +187,7 @@
187#define MAX_INTERNAL_IRQ IMX_IRQS 187#define MAX_INTERNAL_IRQ IMX_IRQS
188#endif 188#endif
189 189
190#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2 190#ifdef CONFIG_ARCH_MXC
191#define SERIAL_IMX_MAJOR 207 191#define SERIAL_IMX_MAJOR 207
192#define MINOR_START 16 192#define MINOR_START 16
193#define DEV_NAME "ttymxc" 193#define DEV_NAME "ttymxc"
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 12:59:42 -0500