diff options
author | Eric Miao <eric.miao@marvell.com> | 2008-08-06 03:57:04 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-10-07 14:12:59 -0400 |
commit | 5c52de4a6623ac14790d42df69a509631f4db5f6 (patch) | |
tree | 96c657d12046330bf8f1edb941cfeaf927b9ba63 | |
parent | 0d1bde9ed102cf90165adaf7efcff7bb77658eaa (diff) |
[ARM] pxa: add missing ACCR bit definitions to pxa3xx-regs.h
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r-- | arch/arm/mach-pxa/include/mach/pxa3xx-regs.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h index 39eb68319e28..b1fcd10ab6c6 100644 --- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h | |||
@@ -131,6 +131,28 @@ | |||
131 | #define CKENB __REG(0x41340010) /* B Clock Enable Register */ | 131 | #define CKENB __REG(0x41340010) /* B Clock Enable Register */ |
132 | #define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ | 132 | #define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ |
133 | 133 | ||
134 | #define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */ | ||
135 | #define ACCR_SPDIS (1 << 30) /* System PLL Output Disable */ | ||
136 | #define ACCR_D0CS (1 << 26) /* D0 Mode Clock Select */ | ||
137 | #define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */ | ||
138 | #define ACCR_DDR_D0CS (1 << 7) /* DDR SDRAM clock frequency in D0CS (PXA31x only) */ | ||
139 | |||
140 | #define ACCR_SMCFS_MASK (0x7 << 23) /* Static Memory Controller Frequency Select */ | ||
141 | #define ACCR_SFLFS_MASK (0x3 << 18) /* Frequency Select for Internal Memory Controller */ | ||
142 | #define ACCR_XSPCLK_MASK (0x3 << 16) /* Core Frequency during Frequency Change */ | ||
143 | #define ACCR_HSS_MASK (0x3 << 14) /* System Bus-Clock Frequency Select */ | ||
144 | #define ACCR_DMCFS_MASK (0x3 << 12) /* Dynamic Memory Controller Clock Frequency Select */ | ||
145 | #define ACCR_XN_MASK (0x7 << 8) /* Core PLL Turbo-Mode-to-Run-Mode Ratio */ | ||
146 | #define ACCR_XL_MASK (0x1f) /* Core PLL Run-Mode-to-Oscillator Ratio */ | ||
147 | |||
148 | #define ACCR_SMCFS(x) (((x) & 0x7) << 23) | ||
149 | #define ACCR_SFLFS(x) (((x) & 0x3) << 18) | ||
150 | #define ACCR_XSPCLK(x) (((x) & 0x3) << 16) | ||
151 | #define ACCR_HSS(x) (((x) & 0x3) << 14) | ||
152 | #define ACCR_DMCFS(x) (((x) & 0x3) << 12) | ||
153 | #define ACCR_XN(x) (((x) & 0x7) << 8) | ||
154 | #define ACCR_XL(x) ((x) & 0x1f) | ||
155 | |||
134 | /* | 156 | /* |
135 | * Clock Enable Bit | 157 | * Clock Enable Bit |
136 | */ | 158 | */ |