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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-10-29 17:06:55 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-10-29 17:06:55 -0400
commit82798a17ad40df827d465329a20ace80497f9b32 (patch)
tree449ba69dc5a5e19a56b2a9d12d218f9486e5316d
parentdb8185360d91c01f6e482db5ee402c0ad90dec52 (diff)
parent1a3b7920fe55247d39c3e1ac1e9b8aca607d0188 (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (34 commits) [MIPS] tb0219: Update copyright message. [MIPS] MT: Fix bug in multithreaded kernels. [MIPS] Alchemy: Remove CONFIG_TS_AU1X00_ADS7846 from defconfigs. Author: Ralf Baechle <ralf@linux-mips.org> [MIPS] sb1250: Enable GenBus IDE in defconfig. [MIPS] vmlinux.ld.S: correctly indent .data section [MIPS] c-r3k: Implement flush_cache_range() [MIPS] Store sign-extend register values for PTRACE_GETREGS [MIPS] Alchemy: Register platform devices [MIPS] Add len and addr validation for MAP_FIXED mappings. [MIPS] IRIX: Fix off-by-one error in signal compat code. [MIPS] time: Replace plat_timer_setup with modern APIs. [MIPS] time: Fix cut'n'paste bug in Sibyte clockevent driver. [MIPS] time: Make c0_compare_int_usable faster [MIPS] time: Fix cevt-r4k.c for 64-bit kernel [MIPS] Sibyte: Delete {sb1250,bcm1480}_steal_irq(). [MIPS] txx9tmr clockevent/clocksource driver [MIPS] Add mips_hpt_frequency check to mips_clockevent_init(). [MIPS] IP32: Fixes after interrupt renumbering. [MIPS] IP27: Fix slice logic to work for arbitrary number of slices. ...
Diffstat
-rw-r--r--arch/mips/Kconfig6
-rw-r--r--arch/mips/au1000/common/irq.c32
-rw-r--r--arch/mips/au1000/common/time.c22
-rw-r--r--arch/mips/au1000/mtx-1/Makefile1
-rw-r--r--arch/mips/au1000/mtx-1/platform.c86
-rw-r--r--arch/mips/basler/excite/excite_setup.c21
-rw-r--r--arch/mips/configs/db1000_defconfig1
-rw-r--r--arch/mips/configs/db1100_defconfig1
-rw-r--r--arch/mips/configs/db1200_defconfig1
-rw-r--r--arch/mips/configs/db1500_defconfig1
-rw-r--r--arch/mips/configs/db1550_defconfig1
-rw-r--r--arch/mips/configs/pb1100_defconfig1
-rw-r--r--arch/mips/configs/pb1500_defconfig1
-rw-r--r--arch/mips/configs/pb1550_defconfig1
-rw-r--r--arch/mips/configs/sb1250-swarm_defconfig2
-rw-r--r--arch/mips/gt64120/wrppmc/time.c6
-rw-r--r--arch/mips/jmr3927/rbhma3100/setup.c83
-rw-r--r--arch/mips/kernel/Makefile1
-rw-r--r--arch/mips/kernel/cevt-gt641xx.c12
-rw-r--r--arch/mips/kernel/cevt-r4k.c45
-rw-r--r--arch/mips/kernel/cevt-txx9.c171
-rw-r--r--arch/mips/kernel/irixsig.c8
-rw-r--r--arch/mips/kernel/ptrace.c18
-rw-r--r--arch/mips/kernel/ptrace32.c4
-rw-r--r--arch/mips/kernel/smtc.c57
-rw-r--r--arch/mips/kernel/syscall.c9
-rw-r--r--arch/mips/kernel/time.c17
-rw-r--r--arch/mips/kernel/vmlinux.lds.S32
-rw-r--r--arch/mips/kernel/vpe.c4
-rw-r--r--arch/mips/lasat/setup.c7
-rw-r--r--arch/mips/mips-boards/generic/time.c52
-rw-r--r--arch/mips/mipssim/sim_time.c52
-rw-r--r--arch/mips/mm/c-r3k.c60
-rw-r--r--arch/mips/mm/c-r4k.c21
-rw-r--r--arch/mips/mm/dma-default.c2
-rw-r--r--arch/mips/pci/fixup-pmcmsp.c2
-rw-r--r--arch/mips/pci/fixup-tb0219.c2
-rw-r--r--arch/mips/pci/ops-pmcmsp.c2
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_serial.c2
-rw-r--r--arch/mips/sgi-ip27/ip27-timer.c11
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c128
-rw-r--r--arch/mips/sibyte/bcm1480/irq.c24
-rw-r--r--arch/mips/sibyte/bcm1480/time.c5
-rw-r--r--arch/mips/sibyte/sb1250/irq.c24
-rw-r--r--arch/mips/sibyte/sb1250/time.c5
-rw-r--r--arch/mips/sni/time.c80
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c17
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/setup.c19
-rw-r--r--include/asm-mips/ip32/ip32_ints.h4
-rw-r--r--include/asm-mips/jmr3927/jmr3927.h9
-rw-r--r--include/asm-mips/jmr3927/tx3927.h4
-rw-r--r--include/asm-mips/jmr3927/txx927.h37
-rw-r--r--include/asm-mips/time.h2
-rw-r--r--include/asm-mips/tx4927/tx4927_pci.h3
-rw-r--r--include/asm-mips/tx4938/tx4938.h1
-rw-r--r--include/asm-mips/txx9tmr.h67
56 files changed, 773 insertions, 514 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 61262c5f9c62..97da953eb5d0 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -583,6 +583,7 @@ config SNI_RM
583 583
584config TOSHIBA_JMR3927 584config TOSHIBA_JMR3927
585 bool "Toshiba JMR-TX3927 board" 585 bool "Toshiba JMR-TX3927 board"
586 select CEVT_TXX9
586 select DMA_NONCOHERENT 587 select DMA_NONCOHERENT
587 select HW_HAS_PCI 588 select HW_HAS_PCI
588 select MIPS_TX3927 589 select MIPS_TX3927
@@ -597,6 +598,7 @@ config TOSHIBA_JMR3927
597config TOSHIBA_RBTX4927 598config TOSHIBA_RBTX4927
598 bool "Toshiba RBTX49[23]7 board" 599 bool "Toshiba RBTX49[23]7 board"
599 select CEVT_R4K 600 select CEVT_R4K
601 select CEVT_TXX9
600 select DMA_NONCOHERENT 602 select DMA_NONCOHERENT
601 select HAS_TXX9_SERIAL 603 select HAS_TXX9_SERIAL
602 select HW_HAS_PCI 604 select HW_HAS_PCI
@@ -618,6 +620,7 @@ config TOSHIBA_RBTX4927
618config TOSHIBA_RBTX4938 620config TOSHIBA_RBTX4938
619 bool "Toshiba RBTX4938 board" 621 bool "Toshiba RBTX4938 board"
620 select CEVT_R4K 622 select CEVT_R4K
623 select CEVT_TXX9
621 select DMA_NONCOHERENT 624 select DMA_NONCOHERENT
622 select HAS_TXX9_SERIAL 625 select HAS_TXX9_SERIAL
623 select HW_HAS_PCI 626 select HW_HAS_PCI
@@ -736,6 +739,9 @@ config CEVT_GT641XX
736config CEVT_R4K 739config CEVT_R4K
737 bool 740 bool
738 741
742config CEVT_TXX9
743 bool
744
739config CFE 745config CFE
740 bool 746 bool
741 747
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c
index 59e932a928d2..ddfb7f0a17a6 100644
--- a/arch/mips/au1000/common/irq.c
+++ b/arch/mips/au1000/common/irq.c
@@ -318,38 +318,6 @@ static struct irq_chip level_irq_type = {
318 .end = end_irq, 318 .end = end_irq,
319}; 319};
320 320
321#ifdef CONFIG_PM
322void startup_match20_interrupt(irq_handler_t handler)
323{
324 struct irq_desc *desc = &irq_desc[AU1000_TOY_MATCH2_INT];
325
326 static struct irqaction action;
327 memset(&action, 0, sizeof(struct irqaction));
328
329 /*
330 * This is a big problem.... since we didn't use request_irq
331 * when kernel/irq.c calls probe_irq_xxx this interrupt will
332 * be probed for usage. This will end up disabling the device :(
333 * Give it a bogus "action" pointer -- this will keep it from
334 * getting auto-probed!
335 *
336 * By setting the status to match that of request_irq() we
337 * can avoid it. --cgray
338 */
339 action.dev_id = handler;
340 action.flags = IRQF_DISABLED;
341 cpus_clear(action.mask);
342 action.name = "Au1xxx TOY";
343 action.handler = handler;
344 action.next = NULL;
345
346 desc->action = &action;
347 desc->status &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING | IRQ_INPROGRESS);
348
349 local_enable_irq(AU1000_TOY_MATCH2_INT);
350}
351#endif
352
353static void __init setup_local_irq(unsigned int irq_nr, int type, int int_req) 321static void __init setup_local_irq(unsigned int irq_nr, int type, int int_req)
354{ 322{
355 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 323 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c
index 2556399708ba..f113b512d7b1 100644
--- a/arch/mips/au1000/common/time.c
+++ b/arch/mips/au1000/common/time.c
@@ -67,7 +67,7 @@ static DEFINE_SPINLOCK(time_lock);
67unsigned long wtimer; 67unsigned long wtimer;
68 68
69#ifdef CONFIG_PM 69#ifdef CONFIG_PM
70irqreturn_t counter0_irq(int irq, void *dev_id) 70static irqreturn_t counter0_irq(int irq, void *dev_id)
71{ 71{
72 unsigned long pc0; 72 unsigned long pc0;
73 int time_elapsed; 73 int time_elapsed;
@@ -117,6 +117,13 @@ irqreturn_t counter0_irq(int irq, void *dev_id)
117 return IRQ_HANDLED; 117 return IRQ_HANDLED;
118} 118}
119 119
120struct irqaction counter0_action = {
121 .handler = counter0_irq,
122 .flags = IRQF_DISABLED,
123 .name = "alchemy-toy",
124 .dev_id = NULL,
125};
126
120/* When we wakeup from sleep, we have to "catch up" on all of the 127/* When we wakeup from sleep, we have to "catch up" on all of the
121 * timer ticks we have missed. 128 * timer ticks we have missed.
122 */ 129 */
@@ -221,7 +228,7 @@ unsigned long cal_r4koff(void)
221 return (cpu_speed / HZ); 228 return (cpu_speed / HZ);
222} 229}
223 230
224void __init plat_timer_setup(struct irqaction *irq) 231void __init plat_time_init(void)
225{ 232{
226 unsigned int est_freq; 233 unsigned int est_freq;
227 234
@@ -255,15 +262,10 @@ void __init plat_timer_setup(struct irqaction *irq)
255 * we do this. 262 * we do this.
256 */ 263 */
257 if (no_au1xxx_32khz) { 264 if (no_au1xxx_32khz) {
258 unsigned int c0_status;
259
260 printk("WARNING: no 32KHz clock found.\n"); 265 printk("WARNING: no 32KHz clock found.\n");
261 266
262 /* Ensure we get CPO_COUNTER interrupts. 267 /* Ensure we get CPO_COUNTER interrupts. */
263 */ 268 set_c0_status(IE_IRQ5);
264 c0_status = read_c0_status();
265 c0_status |= IE_IRQ5;
266 write_c0_status(c0_status);
267 } 269 }
268 else { 270 else {
269 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S); 271 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
@@ -280,7 +282,7 @@ void __init plat_timer_setup(struct irqaction *irq)
280 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2); 282 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
281 au_sync(); 283 au_sync();
282 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20); 284 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
283 startup_match20_interrupt(counter0_irq); 285 setup_irq(AU1000_TOY_MATCH2_INT, &counter0_action);
284 286
285 /* We can use the real 'wait' instruction. 287 /* We can use the real 'wait' instruction.
286 */ 288 */
diff --git a/arch/mips/au1000/mtx-1/Makefile b/arch/mips/au1000/mtx-1/Makefile
index 764bf9f7e281..afa7007d67f7 100644
--- a/arch/mips/au1000/mtx-1/Makefile
+++ b/arch/mips/au1000/mtx-1/Makefile
@@ -8,3 +8,4 @@
8# 8#
9 9
10lib-y := init.o board_setup.o irqmap.o 10lib-y := init.o board_setup.o irqmap.o
11obj-y := platform.o
diff --git a/arch/mips/au1000/mtx-1/platform.c b/arch/mips/au1000/mtx-1/platform.c
new file mode 100644
index 000000000000..01ebff677978
--- /dev/null
+++ b/arch/mips/au1000/mtx-1/platform.c
@@ -0,0 +1,86 @@
1/*
2 * MTX-1 platform devices registration
3 *
4 * Copyright (C) 2007, Florian Fainelli <florian@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22#include <linux/types.h>
23#include <linux/platform_device.h>
24#include <linux/leds.h>
25
26#include <asm/gpio.h>
27
28static struct resource mtx1_wdt_res[] = {
29 [0] = {
30 .start = 15,
31 .end = 15,
32 .name = "mtx1-wdt-gpio",
33 .flags = IORESOURCE_IRQ,
34 }
35};
36
37static struct resource mtx1_sys_btn[] = {
38 [0] = {
39 .start = 7,
40 .end = 7,
41 .name = "mtx1-sys-btn-gpio",
42 .flags = IORESOURCE_IRQ,
43 }
44};
45
46static struct platform_device mtx1_wdt = {
47 .name = "mtx1-wdt",
48 .id = 0,
49 .num_resources = ARRAY_SIZE(mtx1_wdt_res),
50 .resource = mtx1_wdt_res,
51};
52
53static struct gpio_led default_leds[] = {
54 {
55 .name = "mtx1:green",
56 .gpio = 211,
57 }, {
58 .name = "mtx1:red",
59 .gpio = 212,
60 },
61};
62
63static struct gpio_led_platform_data mtx1_led_data = {
64 .num_leds = ARRAY_SIZE(default_leds),
65 .leds = default_leds,
66};
67
68static struct platform_device mtx1_gpio_leds = {
69 .name = "leds-gpio",
70 .id = -1,
71 .dev = {
72 .platform_data = &mtx1_led_data,
73 }
74};
75
76static struct __initdata platform_device * mtx1_devs[] = {
77 &mtx1_gpio_leds,
78 &mtx1_wdt
79};
80
81static int __init mtx1_register_devices(void)
82{
83 return platform_add_devices(mtx1_devs, ARRAY_SIZE(mtx1_devs));
84}
85
86arch_initcall(mtx1_register_devices);
diff --git a/arch/mips/basler/excite/excite_setup.c b/arch/mips/basler/excite/excite_setup.c
index 404ca9284b30..24378b9223f9 100644
--- a/arch/mips/basler/excite/excite_setup.c
+++ b/arch/mips/basler/excite/excite_setup.c
@@ -68,24 +68,23 @@ DEFINE_SPINLOCK(titan_lock);
68int titan_irqflags; 68int titan_irqflags;
69 69
70 70
71/*
72 * The eXcite platform uses the alternate timer interrupt
73 *
74 * Fixme: At the time of this writing cevt-r4k.c doesn't yet know about how
75 * to handle the alternate timer interrupt of the RM9000.
76 */
71void __init plat_time_init(void) 77void __init plat_time_init(void)
72{ 78{
73 const u32 modebit5 = ocd_readl(0x00e4); 79 const u32 modebit5 = ocd_readl(0x00e4);
74 unsigned int 80 unsigned int mult = ((modebit5 >> 11) & 0x1f) + 2,
75 mult = ((modebit5 >> 11) & 0x1f) + 2, 81 unsigned int div = ((modebit5 >> 16) & 0x1f) + 2;
76 div = ((modebit5 >> 16) & 0x1f) + 2;
77 82
78 if (div == 33) div = 1; 83 if (div == 33)
84 div = 1;
79 mips_hpt_frequency = EXCITE_CPU_EXT_CLOCK * mult / div / 2; 85 mips_hpt_frequency = EXCITE_CPU_EXT_CLOCK * mult / div / 2;
80} 86}
81 87
82void __init plat_timer_setup(struct irqaction *irq)
83{
84 /* The eXcite platform uses the alternate timer interrupt */
85 set_c0_intcontrol(0x80);
86 setup_irq(TIMER_IRQ, irq);
87}
88
89static int __init excite_init_console(void) 88static int __init excite_init_console(void)
90{ 89{
91#if defined(CONFIG_SERIAL_8250) 90#if defined(CONFIG_SERIAL_8250)
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index 885b633647e9..5a8b7acb7dd7 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -738,7 +738,6 @@ CONFIG_HW_CONSOLE=y
738CONFIG_VT_HW_CONSOLE_BINDING=y 738CONFIG_VT_HW_CONSOLE_BINDING=y
739# CONFIG_SERIAL_NONSTANDARD is not set 739# CONFIG_SERIAL_NONSTANDARD is not set
740# CONFIG_AU1X00_GPIO is not set 740# CONFIG_AU1X00_GPIO is not set
741# CONFIG_TS_AU1X00_ADS7846 is not set
742 741
743# 742#
744# Serial drivers 743# Serial drivers
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index e3c3a07e8a7c..d4ed90bca269 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -714,7 +714,6 @@ CONFIG_HW_CONSOLE=y
714CONFIG_VT_HW_CONSOLE_BINDING=y 714CONFIG_VT_HW_CONSOLE_BINDING=y
715# CONFIG_SERIAL_NONSTANDARD is not set 715# CONFIG_SERIAL_NONSTANDARD is not set
716# CONFIG_AU1X00_GPIO is not set 716# CONFIG_AU1X00_GPIO is not set
717# CONFIG_TS_AU1X00_ADS7846 is not set
718 717
719# 718#
720# Serial drivers 719# Serial drivers
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index 9aa7c3ebfa3f..a055657e6983 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -775,7 +775,6 @@ CONFIG_HW_CONSOLE=y
775CONFIG_VT_HW_CONSOLE_BINDING=y 775CONFIG_VT_HW_CONSOLE_BINDING=y
776# CONFIG_SERIAL_NONSTANDARD is not set 776# CONFIG_SERIAL_NONSTANDARD is not set
777# CONFIG_AU1X00_GPIO is not set 777# CONFIG_AU1X00_GPIO is not set
778# CONFIG_TS_AU1X00_ADS7846 is not set
779 778
780# 779#
781# Serial drivers 780# Serial drivers
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index 99240668bca1..0ad08cf446ec 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -811,7 +811,6 @@ CONFIG_SERIO_RAW=m
811# CONFIG_VT is not set 811# CONFIG_VT is not set
812# CONFIG_SERIAL_NONSTANDARD is not set 812# CONFIG_SERIAL_NONSTANDARD is not set
813# CONFIG_AU1X00_GPIO is not set 813# CONFIG_AU1X00_GPIO is not set
814# CONFIG_TS_AU1X00_ADS7846 is not set
815 814
816# 815#
817# Serial drivers 816# Serial drivers
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index 19992f76c60d..057c7d429c80 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -856,7 +856,6 @@ CONFIG_SERIO_RAW=m
856# CONFIG_VT is not set 856# CONFIG_VT is not set
857# CONFIG_SERIAL_NONSTANDARD is not set 857# CONFIG_SERIAL_NONSTANDARD is not set
858# CONFIG_AU1X00_GPIO is not set 858# CONFIG_AU1X00_GPIO is not set
859# CONFIG_TS_AU1X00_ADS7846 is not set
860 859
861# 860#
862# Serial drivers 861# Serial drivers
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index d53fa8f8e099..703d28db05b9 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -731,7 +731,6 @@ CONFIG_HW_CONSOLE=y
731CONFIG_VT_HW_CONSOLE_BINDING=y 731CONFIG_VT_HW_CONSOLE_BINDING=y
732# CONFIG_SERIAL_NONSTANDARD is not set 732# CONFIG_SERIAL_NONSTANDARD is not set
733# CONFIG_AU1X00_GPIO is not set 733# CONFIG_AU1X00_GPIO is not set
734# CONFIG_TS_AU1X00_ADS7846 is not set
735 734
736# 735#
737# Serial drivers 736# Serial drivers
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index dc4aa0c66847..82f0c5cee0dc 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -849,7 +849,6 @@ CONFIG_SERIO_RAW=m
849# CONFIG_VT is not set 849# CONFIG_VT is not set
850# CONFIG_SERIAL_NONSTANDARD is not set 850# CONFIG_SERIAL_NONSTANDARD is not set
851# CONFIG_AU1X00_GPIO is not set 851# CONFIG_AU1X00_GPIO is not set
852# CONFIG_TS_AU1X00_ADS7846 is not set
853 852
854# 853#
855# Serial drivers 854# Serial drivers
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index 24428e13002b..147a4fc7fdd8 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -842,7 +842,6 @@ CONFIG_SERIO_RAW=m
842# CONFIG_VT is not set 842# CONFIG_VT is not set
843# CONFIG_SERIAL_NONSTANDARD is not set 843# CONFIG_SERIAL_NONSTANDARD is not set
844# CONFIG_AU1X00_GPIO is not set 844# CONFIG_AU1X00_GPIO is not set
845# CONFIG_TS_AU1X00_ADS7846 is not set
846 845
847# 846#
848# Serial drivers 847# Serial drivers
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
index 49dfcef2518c..c2798229cbfb 100644
--- a/arch/mips/configs/sb1250-swarm_defconfig
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -468,7 +468,7 @@ CONFIG_BLK_DEV_IDEFLOPPY=y
468# 468#
469CONFIG_IDE_GENERIC=y 469CONFIG_IDE_GENERIC=y
470# CONFIG_BLK_DEV_IDEPCI is not set 470# CONFIG_BLK_DEV_IDEPCI is not set
471# CONFIG_BLK_DEV_IDE_SWARM is not set 471CONFIG_BLK_DEV_IDE_SWARM=y
472# CONFIG_IDE_ARM is not set 472# CONFIG_IDE_ARM is not set
473# CONFIG_BLK_DEV_IDEDMA is not set 473# CONFIG_BLK_DEV_IDEDMA is not set
474# CONFIG_IDEDMA_AUTO is not set 474# CONFIG_IDEDMA_AUTO is not set
diff --git a/arch/mips/gt64120/wrppmc/time.c b/arch/mips/gt64120/wrppmc/time.c
index b207e7f1417a..668dbd5f12c5 100644
--- a/arch/mips/gt64120/wrppmc/time.c
+++ b/arch/mips/gt64120/wrppmc/time.c
@@ -19,12 +19,6 @@
19 19
20#define WRPPMC_CPU_CLK_FREQ 40000000 /* 40MHZ */ 20#define WRPPMC_CPU_CLK_FREQ 40000000 /* 40MHZ */
21 21
22void __init plat_timer_setup(struct irqaction *irq)
23{
24 /* Install ISR for timer interrupt */
25 setup_irq(WRPPMC_MIPS_TIMER_IRQ, irq);
26}
27
28/* 22/*
29 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect 23 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
30 * 24 *
diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c
index edb9e59248ec..06e01c8f4e3a 100644
--- a/arch/mips/jmr3927/rbhma3100/setup.c
+++ b/arch/mips/jmr3927/rbhma3100/setup.c
@@ -27,17 +27,13 @@
27 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) 27 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
28 */ 28 */
29 29
30#include <linux/clockchips.h>
31#include <linux/init.h> 30#include <linux/init.h>
32#include <linux/kernel.h> 31#include <linux/kernel.h>
33#include <linux/kdev_t.h> 32#include <linux/kdev_t.h>
34#include <linux/types.h> 33#include <linux/types.h>
35#include <linux/sched.h>
36#include <linux/pci.h> 34#include <linux/pci.h>
37#include <linux/ide.h> 35#include <linux/ide.h>
38#include <linux/irq.h>
39#include <linux/ioport.h> 36#include <linux/ioport.h>
40#include <linux/param.h> /* for HZ */
41#include <linux/delay.h> 37#include <linux/delay.h>
42#include <linux/pm.h> 38#include <linux/pm.h>
43#include <linux/platform_device.h> 39#include <linux/platform_device.h>
@@ -48,17 +44,13 @@
48#endif 44#endif
49 45
50#include <asm/addrspace.h> 46#include <asm/addrspace.h>
51#include <asm/time.h> 47#include <asm/txx9tmr.h>
52#include <asm/reboot.h> 48#include <asm/reboot.h>
53#include <asm/jmr3927/jmr3927.h> 49#include <asm/jmr3927/jmr3927.h>
54#include <asm/mipsregs.h> 50#include <asm/mipsregs.h>
55 51
56extern void puts(const char *cp); 52extern void puts(const char *cp);
57 53
58/* Tick Timer divider */
59#define JMR3927_TIMER_CCD 0 /* 1/2 */
60#define JMR3927_TIMER_CLK (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
61
62/* don't enable - see errata */ 54/* don't enable - see errata */
63static int jmr3927_ccfg_toeon; 55static int jmr3927_ccfg_toeon;
64 56
@@ -93,66 +85,12 @@ static void jmr3927_machine_power_off(void)
93 while (1); 85 while (1);
94} 86}
95 87
96static cycle_t jmr3927_hpt_read(void)
97{
98 /* We assume this function is called xtime_lock held. */
99 return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr;
100}
101
102static void jmr3927_set_mode(enum clock_event_mode mode,
103 struct clock_event_device *evt)
104{
105 /* Nothing to do here */
106}
107
108struct clock_event_device jmr3927_clock_event_device = {
109 .name = "MIPS",
110 .features = CLOCK_EVT_FEAT_PERIODIC,
111 .shift = 32,
112 .rating = 300,
113 .cpumask = CPU_MASK_CPU0,
114 .irq = JMR3927_IRQ_TICK,
115 .set_mode = jmr3927_set_mode,
116};
117
118static irqreturn_t jmr3927_timer_interrupt(int irq, void *dev_id)
119{
120 struct clock_event_device *cd = &jmr3927_clock_event_device;
121
122 jmr3927_tmrptr->tisr = 0; /* ack interrupt */
123
124 cd->event_handler(cd);
125
126 return IRQ_HANDLED;
127}
128
129static struct irqaction jmr3927_timer_irqaction = {
130 .handler = jmr3927_timer_interrupt,
131 .flags = IRQF_DISABLED | IRQF_PERCPU,
132 .name = "jmr3927-timer",
133};
134
135void __init plat_time_init(void) 88void __init plat_time_init(void)
136{ 89{
137 struct clock_event_device *cd; 90 txx9_clockevent_init(TX3927_TMR_REG(0),
138 91 TXX9_IRQ_BASE + JMR3927_IRQ_IRC_TMR(0),
139 clocksource_mips.read = jmr3927_hpt_read; 92 JMR3927_IMCLK);
140 mips_hpt_frequency = JMR3927_TIMER_CLK; 93 txx9_clocksource_init(TX3927_TMR_REG(1), JMR3927_IMCLK);
141
142 jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
143 jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
144 jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
145 jmr3927_tmrptr->tcr =
146 TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;
147
148 cd = &jmr3927_clock_event_device;
149 /* Calculate the min / max delta */
150 cd->mult = div_sc((unsigned long) JMR3927_IMCLK, NSEC_PER_SEC, 32);
151 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
152 cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
153 clockevents_register_device(cd);
154
155 setup_irq(JMR3927_IRQ_TICK, &jmr3927_timer_irqaction);
156} 94}
157 95
158#define DO_WRITE_THROUGH 96#define DO_WRITE_THROUGH
@@ -317,15 +255,8 @@ static void __init tx3927_setup(void)
317 tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg); 255 tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
318 256
319 /* TMR */ 257 /* TMR */
320 /* disable all timers */ 258 for (i = 0; i < TX3927_NR_TMR; i++)
321 for (i = 0; i < TX3927_NR_TMR; i++) { 259 txx9_tmr_init(TX3927_TMR_REG(i));
322 tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE;
323 tx3927_tmrptr(i)->tisr = 0;
324 tx3927_tmrptr(i)->cpra = 0xffffffff;
325 tx3927_tmrptr(i)->itmr = 0;
326 tx3927_tmrptr(i)->ccdr = 0;
327 tx3927_tmrptr(i)->pgmr = 0;
328 }
329 260
330 /* DMA */ 261 /* DMA */
331 tx3927_dmaptr->mcr = 0; 262 tx3927_dmaptr->mcr = 0;
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index d7745c8976f6..3196509a28d5 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -10,6 +10,7 @@ obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
10 10
11obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o 11obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o
12obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o 12obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o
13obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
13 14
14binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \ 15binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \
15 irix5sys.o sysirix.o 16 irix5sys.o sysirix.o
diff --git a/arch/mips/kernel/cevt-gt641xx.c b/arch/mips/kernel/cevt-gt641xx.c
index 4c651b2680f9..c36772631fe0 100644
--- a/arch/mips/kernel/cevt-gt641xx.c
+++ b/arch/mips/kernel/cevt-gt641xx.c
@@ -49,10 +49,9 @@ int gt641xx_timer0_state(void)
49static int gt641xx_timer0_set_next_event(unsigned long delta, 49static int gt641xx_timer0_set_next_event(unsigned long delta,
50 struct clock_event_device *evt) 50 struct clock_event_device *evt)
51{ 51{
52 unsigned long flags;
53 u32 ctrl; 52 u32 ctrl;
54 53
55 spin_lock_irqsave(&gt641xx_timer_lock, flags); 54 spin_lock(&gt641xx_timer_lock);
56 55
57 ctrl = GT_READ(GT_TC_CONTROL_OFS); 56 ctrl = GT_READ(GT_TC_CONTROL_OFS);
58 ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK); 57 ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
@@ -61,7 +60,7 @@ static int gt641xx_timer0_set_next_event(unsigned long delta,
61 GT_WRITE(GT_TC0_OFS, delta); 60 GT_WRITE(GT_TC0_OFS, delta);
62 GT_WRITE(GT_TC_CONTROL_OFS, ctrl); 61 GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
63 62
64 spin_unlock_irqrestore(&gt641xx_timer_lock, flags); 63 spin_unlock(&gt641xx_timer_lock);
65 64
66 return 0; 65 return 0;
67} 66}
@@ -69,10 +68,9 @@ static int gt641xx_timer0_set_next_event(unsigned long delta,
69static void gt641xx_timer0_set_mode(enum clock_event_mode mode, 68static void gt641xx_timer0_set_mode(enum clock_event_mode mode,
70 struct clock_event_device *evt) 69 struct clock_event_device *evt)
71{ 70{
72 unsigned long flags;
73 u32 ctrl; 71 u32 ctrl;
74 72
75 spin_lock_irqsave(&gt641xx_timer_lock, flags); 73 spin_lock(&gt641xx_timer_lock);
76 74
77 ctrl = GT_READ(GT_TC_CONTROL_OFS); 75 ctrl = GT_READ(GT_TC_CONTROL_OFS);
78 ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK); 76 ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
@@ -90,7 +88,7 @@ static void gt641xx_timer0_set_mode(enum clock_event_mode mode,
90 88
91 GT_WRITE(GT_TC_CONTROL_OFS, ctrl); 89 GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
92 90
93 spin_unlock_irqrestore(&gt641xx_timer_lock, flags); 91 spin_unlock(&gt641xx_timer_lock);
94} 92}
95 93
96static void gt641xx_timer0_event_handler(struct clock_event_device *dev) 94static void gt641xx_timer0_event_handler(struct clock_event_device *dev)
@@ -133,9 +131,9 @@ static int __init gt641xx_timer0_clockevent_init(void)
133 131
134 cd = &gt641xx_timer0_clockevent; 132 cd = &gt641xx_timer0_clockevent;
135 cd->rating = 200 + gt641xx_base_clock / 10000000; 133 cd->rating = 200 + gt641xx_base_clock / 10000000;
134 clockevent_set_clock(cd, gt641xx_base_clock);
136 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd); 135 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
137 cd->min_delta_ns = clockevent_delta2ns(0x300, cd); 136 cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
138 clockevent_set_clock(cd, gt641xx_base_clock);
139 137
140 clockevents_register_device(&gt641xx_timer0_clockevent); 138 clockevents_register_device(&gt641xx_timer0_clockevent);
141 139
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index ae2984fff580..bab935a3d74b 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -28,7 +28,7 @@ static int mips_next_event(unsigned long delta,
28 cnt = read_c0_count(); 28 cnt = read_c0_count();
29 cnt += delta; 29 cnt += delta;
30 write_c0_compare(cnt); 30 write_c0_compare(cnt);
31 res = ((long)(read_c0_count() - cnt ) > 0) ? -ETIME : 0; 31 res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
32#ifdef CONFIG_MIPS_MT_SMTC 32#ifdef CONFIG_MIPS_MT_SMTC
33 evpe(vpflags); 33 evpe(vpflags);
34 local_irq_restore(flags); 34 local_irq_restore(flags);
@@ -179,7 +179,7 @@ static int c0_compare_int_pending(void)
179 179
180static int c0_compare_int_usable(void) 180static int c0_compare_int_usable(void)
181{ 181{
182 const unsigned int delta = 0x300000; 182 unsigned int delta;
183 unsigned int cnt; 183 unsigned int cnt;
184 184
185 /* 185 /*
@@ -192,11 +192,17 @@ static int c0_compare_int_usable(void)
192 return 0; 192 return 0;
193 } 193 }
194 194
195 cnt = read_c0_count(); 195 for (delta = 0x10; delta <= 0x400000; delta <<= 1) {
196 cnt += delta; 196 cnt = read_c0_count();
197 write_c0_compare(cnt); 197 cnt += delta;
198 write_c0_compare(cnt);
199 irq_disable_hazard();
200 if ((int)(read_c0_count() - cnt) < 0)
201 break;
202 /* increase delta if the timer was already expired */
203 }
198 204
199 while ((long)(read_c0_count() - cnt) <= 0) 205 while ((int)(read_c0_count() - cnt) <= 0)
200 ; /* Wait for expiry */ 206 ; /* Wait for expiry */
201 207
202 if (!c0_compare_int_pending()) 208 if (!c0_compare_int_pending())
@@ -218,9 +224,9 @@ void __cpuinit mips_clockevent_init(void)
218 uint64_t mips_freq = mips_hpt_frequency; 224 uint64_t mips_freq = mips_hpt_frequency;
219 unsigned int cpu = smp_processor_id(); 225 unsigned int cpu = smp_processor_id();
220 struct clock_event_device *cd; 226 struct clock_event_device *cd;
221 unsigned int irq = MIPS_CPU_IRQ_BASE + 7; 227 unsigned int irq;
222 228
223 if (!cpu_has_counter) 229 if (!cpu_has_counter || !mips_hpt_frequency)
224 return; 230 return;
225 231
226#ifdef CONFIG_MIPS_MT_SMTC 232#ifdef CONFIG_MIPS_MT_SMTC
@@ -237,6 +243,15 @@ void __cpuinit mips_clockevent_init(void)
237 if (!c0_compare_int_usable()) 243 if (!c0_compare_int_usable())
238 return; 244 return;
239 245
246 /*
247 * With vectored interrupts things are getting platform specific.
248 * get_c0_compare_int is a hook to allow a platform to return the
249 * interrupt number of it's liking.
250 */
251 irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
252 if (get_c0_compare_int)
253 irq = get_c0_compare_int();
254
240 cd = &per_cpu(mips_clockevent_device, cpu); 255 cd = &per_cpu(mips_clockevent_device, cpu);
241 256
242 cd->name = "MIPS"; 257 cd->name = "MIPS";
@@ -261,13 +276,15 @@ void __cpuinit mips_clockevent_init(void)
261 276
262 clockevents_register_device(cd); 277 clockevents_register_device(cd);
263 278
264 if (!cp0_timer_irq_installed) { 279 if (!cp0_timer_irq_installed)
280 return;
281
282 cp0_timer_irq_installed = 1;
283
265#ifdef CONFIG_MIPS_MT_SMTC 284#ifdef CONFIG_MIPS_MT_SMTC
266#define CPUCTR_IMASKBIT (0x100 << cp0_compare_irq) 285#define CPUCTR_IMASKBIT (0x100 << cp0_compare_irq)
267 setup_irq_smtc(irq, &c0_compare_irqaction, CPUCTR_IMASKBIT); 286 setup_irq_smtc(irq, &c0_compare_irqaction, CPUCTR_IMASKBIT);
268#else 287#else
269 setup_irq(irq, &c0_compare_irqaction); 288 setup_irq(irq, &c0_compare_irqaction);
270#endif /* CONFIG_MIPS_MT_SMTC */ 289#endif
271 cp0_timer_irq_installed = 1;
272 }
273} 290}
diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c
new file mode 100644
index 000000000000..795cb8fb0d74
--- /dev/null
+++ b/arch/mips/kernel/cevt-txx9.c
@@ -0,0 +1,171 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Based on linux/arch/mips/kernel/cevt-r4k.c,
7 * linux/arch/mips/jmr3927/rbhma3100/setup.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 * Copyright (C) 2000-2001 Toshiba Corporation
11 * Copyright (C) 2007 MIPS Technologies, Inc.
12 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
13 */
14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <asm/time.h>
17#include <asm/txx9tmr.h>
18
19#define TCR_BASE (TXx9_TMTCR_CCDE | TXx9_TMTCR_CRE | TXx9_TMTCR_TMODE_ITVL)
20#define TIMER_CCD 0 /* 1/2 */
21#define TIMER_CLK(imclk) ((imclk) / (2 << TIMER_CCD))
22
23static struct txx9_tmr_reg __iomem *txx9_cs_tmrptr;
24
25static cycle_t txx9_cs_read(void)
26{
27 return __raw_readl(&txx9_cs_tmrptr->trr);
28}
29
30/* Use 1 bit smaller width to use full bits in that width */
31#define TXX9_CLOCKSOURCE_BITS (TXX9_TIMER_BITS - 1)
32
33static struct clocksource txx9_clocksource = {
34 .name = "TXx9",
35 .rating = 200,
36 .read = txx9_cs_read,
37 .mask = CLOCKSOURCE_MASK(TXX9_CLOCKSOURCE_BITS),
38 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
39};
40
41void __init txx9_clocksource_init(unsigned long baseaddr,
42 unsigned int imbusclk)
43{
44 struct txx9_tmr_reg __iomem *tmrptr;
45
46 clocksource_set_clock(&txx9_clocksource, TIMER_CLK(imbusclk));
47 clocksource_register(&txx9_clocksource);
48
49 tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
50 __raw_writel(TCR_BASE, &tmrptr->tcr);
51 __raw_writel(0, &tmrptr->tisr);
52 __raw_writel(TIMER_CCD, &tmrptr->ccdr);
53 __raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr);
54 __raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra);
55 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
56 txx9_cs_tmrptr = tmrptr;
57}
58
59static struct txx9_tmr_reg __iomem *txx9_tmrptr;
60
61static void txx9tmr_stop_and_clear(struct txx9_tmr_reg __iomem *tmrptr)
62{
63 /* stop and reset counter */
64 __raw_writel(TCR_BASE, &tmrptr->tcr);
65 /* clear pending interrupt */
66 __raw_writel(0, &tmrptr->tisr);
67}
68
69static void txx9tmr_set_mode(enum clock_event_mode mode,
70 struct clock_event_device *evt)
71{
72 struct txx9_tmr_reg __iomem *tmrptr = txx9_tmrptr;
73
74 txx9tmr_stop_and_clear(tmrptr);
75 switch (mode) {
76 case CLOCK_EVT_MODE_PERIODIC:
77 __raw_writel(TXx9_TMITMR_TIIE | TXx9_TMITMR_TZCE,
78 &tmrptr->itmr);
79 /* start timer */
80 __raw_writel(((u64)(NSEC_PER_SEC / HZ) * evt->mult) >>
81 evt->shift,
82 &tmrptr->cpra);
83 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
84 break;
85 case CLOCK_EVT_MODE_SHUTDOWN:
86 case CLOCK_EVT_MODE_UNUSED:
87 __raw_writel(0, &tmrptr->itmr);
88 break;
89 case CLOCK_EVT_MODE_ONESHOT:
90 __raw_writel(TXx9_TMITMR_TIIE, &tmrptr->itmr);
91 break;
92 case CLOCK_EVT_MODE_RESUME:
93 __raw_writel(TIMER_CCD, &tmrptr->ccdr);
94 __raw_writel(0, &tmrptr->itmr);
95 break;
96 }
97}
98
99static int txx9tmr_set_next_event(unsigned long delta,
100 struct clock_event_device *evt)
101{
102 struct txx9_tmr_reg __iomem *tmrptr = txx9_tmrptr;
103
104 txx9tmr_stop_and_clear(tmrptr);
105 /* start timer */
106 __raw_writel(delta, &tmrptr->cpra);
107 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
108 return 0;
109}
110
111static struct clock_event_device txx9tmr_clock_event_device = {
112 .name = "TXx9",
113 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
114 .rating = 200,
115 .cpumask = CPU_MASK_CPU0,
116 .set_mode = txx9tmr_set_mode,
117 .set_next_event = txx9tmr_set_next_event,
118};
119
120static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id)
121{
122 struct clock_event_device *cd = &txx9tmr_clock_event_device;
123 struct txx9_tmr_reg __iomem *tmrptr = txx9_tmrptr;
124
125 __raw_writel(0, &tmrptr->tisr); /* ack interrupt */
126 cd->event_handler(cd);
127 return IRQ_HANDLED;
128}
129
130static struct irqaction txx9tmr_irq = {
131 .handler = txx9tmr_interrupt,
132 .flags = IRQF_DISABLED | IRQF_PERCPU,
133 .name = "txx9tmr",
134};
135
136void __init txx9_clockevent_init(unsigned long baseaddr, int irq,
137 unsigned int imbusclk)
138{
139 struct clock_event_device *cd = &txx9tmr_clock_event_device;
140 struct txx9_tmr_reg __iomem *tmrptr;
141
142 tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
143 txx9tmr_stop_and_clear(tmrptr);
144 __raw_writel(TIMER_CCD, &tmrptr->ccdr);
145 __raw_writel(0, &tmrptr->itmr);
146 txx9_tmrptr = tmrptr;
147
148 clockevent_set_clock(cd, TIMER_CLK(imbusclk));
149 cd->max_delta_ns =
150 clockevent_delta2ns(0xffffffff >> (32 - TXX9_TIMER_BITS), cd);
151 cd->min_delta_ns = clockevent_delta2ns(0xf, cd);
152 cd->irq = irq;
153 clockevents_register_device(cd);
154 setup_irq(irq, &txx9tmr_irq);
155 printk(KERN_INFO "TXx9: clockevent device at 0x%lx, irq %d\n",
156 baseaddr, irq);
157}
158
159void __init txx9_tmr_init(unsigned long baseaddr)
160{
161 struct txx9_tmr_reg __iomem *tmrptr;
162
163 tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
164 __raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr);
165 __raw_writel(0, &tmrptr->tisr);
166 __raw_writel(0xffffffff, &tmrptr->cpra);
167 __raw_writel(0, &tmrptr->itmr);
168 __raw_writel(0, &tmrptr->ccdr);
169 __raw_writel(0, &tmrptr->pgmr);
170 iounmap(tmrptr);
171}
diff --git a/arch/mips/kernel/irixsig.c b/arch/mips/kernel/irixsig.c
index a0a91056fda7..33506ff25910 100644
--- a/arch/mips/kernel/irixsig.c
+++ b/arch/mips/kernel/irixsig.c
@@ -24,8 +24,12 @@
24 24
25#define _BLOCKABLE (~(_S(SIGKILL) | _S(SIGSTOP))) 25#define _BLOCKABLE (~(_S(SIGKILL) | _S(SIGSTOP)))
26 26
27#define _IRIX_NSIG 128
28#define _IRIX_NSIG_BPW BITS_PER_LONG
29#define _IRIX_NSIG_WORDS (_IRIX_NSIG / _IRIX_NSIG_BPW)
30
27typedef struct { 31typedef struct {
28 unsigned long sig[4]; 32 unsigned long sig[_IRIX_NSIG_WORDS];
29} irix_sigset_t; 33} irix_sigset_t;
30 34
31struct sigctx_irix5 { 35struct sigctx_irix5 {
@@ -527,7 +531,7 @@ asmlinkage int irix_sigpoll_sys(unsigned long __user *set,
527 531
528 expire = schedule_timeout_interruptible(expire); 532 expire = schedule_timeout_interruptible(expire);
529 533
530 for (i=0; i<=4; i++) 534 for (i=0; i < _IRIX_NSIG_WORDS; i++)
531 tmp |= (current->pending.signal.sig[i] & kset.sig[i]); 535 tmp |= (current->pending.signal.sig[i] & kset.sig[i]);
532 536
533 if (tmp) 537 if (tmp)
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index 999f7853de26..35234b92b9a5 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -65,13 +65,13 @@ int ptrace_getregs(struct task_struct *child, __s64 __user *data)
65 regs = task_pt_regs(child); 65 regs = task_pt_regs(child);
66 66
67 for (i = 0; i < 32; i++) 67 for (i = 0; i < 32; i++)
68 __put_user(regs->regs[i], data + i); 68 __put_user((long)regs->regs[i], data + i);
69 __put_user(regs->lo, data + EF_LO - EF_R0); 69 __put_user((long)regs->lo, data + EF_LO - EF_R0);
70 __put_user(regs->hi, data + EF_HI - EF_R0); 70 __put_user((long)regs->hi, data + EF_HI - EF_R0);
71 __put_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0); 71 __put_user((long)regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
72 __put_user(regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0); 72 __put_user((long)regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0);
73 __put_user(regs->cp0_status, data + EF_CP0_STATUS - EF_R0); 73 __put_user((long)regs->cp0_status, data + EF_CP0_STATUS - EF_R0);
74 __put_user(regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0); 74 __put_user((long)regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0);
75 75
76 return 0; 76 return 0;
77} 77}
@@ -390,11 +390,11 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
390 } 390 }
391 391
392 case PTRACE_GETREGS: 392 case PTRACE_GETREGS:
393 ret = ptrace_getregs(child, (__u64 __user *) data); 393 ret = ptrace_getregs(child, (__s64 __user *) data);
394 break; 394 break;
395 395
396 case PTRACE_SETREGS: 396 case PTRACE_SETREGS:
397 ret = ptrace_setregs(child, (__u64 __user *) data); 397 ret = ptrace_setregs(child, (__s64 __user *) data);
398 break; 398 break;
399 399
400 case PTRACE_GETFPREGS: 400 case PTRACE_GETFPREGS:
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index f2bffed94fa3..76818be6ba7c 100644
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -346,11 +346,11 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
346 } 346 }
347 347
348 case PTRACE_GETREGS: 348 case PTRACE_GETREGS:
349 ret = ptrace_getregs(child, (__u64 __user *) (__u64) data); 349 ret = ptrace_getregs(child, (__s64 __user *) (__u64) data);
350 break; 350 break;
351 351
352 case PTRACE_SETREGS: 352 case PTRACE_SETREGS:
353 ret = ptrace_setregs(child, (__u64 __user *) (__u64) data); 353 ret = ptrace_setregs(child, (__s64 __user *) (__u64) data);
354 break; 354 break;
355 355
356 case PTRACE_GETFPREGS: 356 case PTRACE_GETFPREGS:
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index a8c1a698d588..9c92d42996cb 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -88,11 +88,19 @@ unsigned int smtc_status = 0;
88 88
89/* Boot command line configuration overrides */ 89/* Boot command line configuration overrides */
90 90
91static int vpe0limit;
91static int ipibuffers = 0; 92static int ipibuffers = 0;
92static int nostlb = 0; 93static int nostlb = 0;
93static int asidmask = 0; 94static int asidmask = 0;
94unsigned long smtc_asid_mask = 0xff; 95unsigned long smtc_asid_mask = 0xff;
95 96
97static int __init vpe0tcs(char *str)
98{
99 get_option(&str, &vpe0limit);
100
101 return 1;
102}
103
96static int __init ipibufs(char *str) 104static int __init ipibufs(char *str)
97{ 105{
98 get_option(&str, &ipibuffers); 106 get_option(&str, &ipibuffers);
@@ -125,6 +133,7 @@ static int __init asidmask_set(char *str)
125 return 1; 133 return 1;
126} 134}
127 135
136__setup("vpe0tcs=", vpe0tcs);
128__setup("ipibufs=", ipibufs); 137__setup("ipibufs=", ipibufs);
129__setup("nostlb", stlb_disable); 138__setup("nostlb", stlb_disable);
130__setup("asidmask=", asidmask_set); 139__setup("asidmask=", asidmask_set);
@@ -340,7 +349,7 @@ static void smtc_tc_setup(int vpe, int tc, int cpu)
340 349
341void mipsmt_prepare_cpus(void) 350void mipsmt_prepare_cpus(void)
342{ 351{
343 int i, vpe, tc, ntc, nvpe, tcpervpe, slop, cpu; 352 int i, vpe, tc, ntc, nvpe, tcpervpe[NR_CPUS], slop, cpu;
344 unsigned long flags; 353 unsigned long flags;
345 unsigned long val; 354 unsigned long val;
346 int nipi; 355 int nipi;
@@ -401,8 +410,39 @@ void mipsmt_prepare_cpus(void)
401 ntc = NR_CPUS; 410 ntc = NR_CPUS;
402 if (tclimit > 0 && ntc > tclimit) 411 if (tclimit > 0 && ntc > tclimit)
403 ntc = tclimit; 412 ntc = tclimit;
404 tcpervpe = ntc / nvpe; 413 slop = ntc % nvpe;
405 slop = ntc % nvpe; /* Residual TCs, < NVPE */ 414 for (i = 0; i < nvpe; i++) {
415 tcpervpe[i] = ntc / nvpe;
416 if (slop) {
417 if((slop - i) > 0) tcpervpe[i]++;
418 }
419 }
420 /* Handle command line override for VPE0 */
421 if (vpe0limit > ntc) vpe0limit = ntc;
422 if (vpe0limit > 0) {
423 int slopslop;
424 if (vpe0limit < tcpervpe[0]) {
425 /* Reducing TC count - distribute to others */
426 slop = tcpervpe[0] - vpe0limit;
427 slopslop = slop % (nvpe - 1);
428 tcpervpe[0] = vpe0limit;
429 for (i = 1; i < nvpe; i++) {
430 tcpervpe[i] += slop / (nvpe - 1);
431 if(slopslop && ((slopslop - (i - 1) > 0)))
432 tcpervpe[i]++;
433 }
434 } else if (vpe0limit > tcpervpe[0]) {
435 /* Increasing TC count - steal from others */
436 slop = vpe0limit - tcpervpe[0];
437 slopslop = slop % (nvpe - 1);
438 tcpervpe[0] = vpe0limit;
439 for (i = 1; i < nvpe; i++) {
440 tcpervpe[i] -= slop / (nvpe - 1);
441 if(slopslop && ((slopslop - (i - 1) > 0)))
442 tcpervpe[i]--;
443 }
444 }
445 }
406 446
407 /* Set up shared TLB */ 447 /* Set up shared TLB */
408 smtc_configure_tlb(); 448 smtc_configure_tlb();
@@ -416,7 +456,7 @@ void mipsmt_prepare_cpus(void)
416 if (vpe != 0) 456 if (vpe != 0)
417 printk(", "); 457 printk(", ");
418 printk("VPE %d: TC", vpe); 458 printk("VPE %d: TC", vpe);
419 for (i = 0; i < tcpervpe; i++) { 459 for (i = 0; i < tcpervpe[vpe]; i++) {
420 /* 460 /*
421 * TC 0 is bound to VPE 0 at reset, 461 * TC 0 is bound to VPE 0 at reset,
422 * and is presumably executing this 462 * and is presumably executing this
@@ -429,15 +469,6 @@ void mipsmt_prepare_cpus(void)
429 printk(" %d", tc); 469 printk(" %d", tc);
430 tc++; 470 tc++;
431 } 471 }
432 if (slop) {
433 if (tc != 0) {
434 smtc_tc_setup(vpe, tc, cpu);
435 cpu++;
436 }
437 printk(" %d", tc);
438 tc++;
439 slop--;
440 }
441 if (vpe != 0) { 472 if (vpe != 0) {
442 /* 473 /*
443 * Clear any stale software interrupts from VPE's Cause 474 * Clear any stale software interrupts from VPE's Cause
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index b95fe93dd646..af1bdc897488 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -73,7 +73,14 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
73 73
74 task_size = STACK_TOP; 74 task_size = STACK_TOP;
75 75
76 if (len > task_size)
77 return -ENOMEM;
78
76 if (flags & MAP_FIXED) { 79 if (flags & MAP_FIXED) {
80 /* Even MAP_FIXED mappings must reside within task_size. */
81 if (task_size - len < addr)
82 return -EINVAL;
83
77 /* 84 /*
78 * We do not accept a shared mapping if it would violate 85 * We do not accept a shared mapping if it would violate
79 * cache aliasing constraints. 86 * cache aliasing constraints.
@@ -83,8 +90,6 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
83 return addr; 90 return addr;
84 } 91 }
85 92
86 if (len > task_size)
87 return -ENOMEM;
88 do_color_align = 0; 93 do_color_align = 0;
89 if (filp || (flags & MAP_SHARED)) 94 if (filp || (flags & MAP_SHARED))
90 do_color_align = 1; 95 do_color_align = 1;
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 6c6849a8f136..27228f583dae 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -11,6 +11,7 @@
11 * Free Software Foundation; either version 2 of the License, or (at your 11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version. 12 * option) any later version.
13 */ 13 */
14#include <linux/bug.h>
14#include <linux/clockchips.h> 15#include <linux/clockchips.h>
15#include <linux/types.h> 16#include <linux/types.h>
16#include <linux/kernel.h> 17#include <linux/kernel.h>
@@ -115,10 +116,6 @@ EXPORT_SYMBOL(perf_irq);
115 * (only needed if you intended to use cpu counter as timer interrupt 116 * (only needed if you intended to use cpu counter as timer interrupt
116 * source) 117 * source)
117 * 2) calculate a couple of cached variables for later usage 118 * 2) calculate a couple of cached variables for later usage
118 * 3) plat_timer_setup() -
119 * a) (optional) over-write any choices made above by time_init().
120 * b) machine specific code should setup the timer irqaction.
121 * c) enable the timer interrupt
122 */ 119 */
123 120
124unsigned int mips_hpt_frequency; 121unsigned int mips_hpt_frequency;
@@ -221,8 +218,18 @@ void __init __weak plat_time_init(void)
221{ 218{
222} 219}
223 220
224void __init __weak plat_timer_setup(struct irqaction *irq) 221/*
222 * This function exists in order to cause an error due to a duplicate
223 * definition if platform code should have its own implementation. The hook
224 * to use instead is plat_time_init. plat_time_init does not receive the
225 * irqaction pointer argument anymore. This is because any function which
226 * initializes an interrupt timer now takes care of its own request_irq rsp.
227 * setup_irq calls and each clock_event_device should use its own
228 * struct irqrequest.
229 */
230void __init plat_timer_setup(struct irqaction *irq)
225{ 231{
232 BUG();
226} 233}
227 234
228void __init time_init(void) 235void __init time_init(void)
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 2781cff1485e..5fc2398bdb76 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -63,21 +63,23 @@ SECTIONS
63 63
64 /* writeable */ 64 /* writeable */
65 .data : { /* Data */ 65 .data : { /* Data */
66 . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */ 66 . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */
67 /* 67 /*
68 * This ALIGN is needed as a workaround for a bug a gcc bug upto 4.1 which 68 * This ALIGN is needed as a workaround for a bug a
69 * limits the maximum alignment to at most 32kB and results in the following 69 * gcc bug upto 4.1 which limits the maximum alignment
70 * warning: 70 * to at most 32kB and results in the following
71 * 71 * warning:
72 * CC arch/mips/kernel/init_task.o 72 *
73 * arch/mips/kernel/init_task.c:30: warning: alignment of ‘init_thread_union’ 73 * CC arch/mips/kernel/init_task.o
74 * is greater than maximum object file alignment. Using 32768 74 * arch/mips/kernel/init_task.c:30: warning: alignment
75 */ 75 * of ‘init_thread_union’ is greater than maximum
76 . = ALIGN(_PAGE_SIZE); 76 * object file alignment. Using 32768
77 *(.data.init_task) 77 */
78 78 . = ALIGN(_PAGE_SIZE);
79 DATA_DATA 79 *(.data.init_task)
80 CONSTRUCTORS 80
81 DATA_DATA
82 CONSTRUCTORS
81 } 83 }
82 _gp = . + 0x8000; 84 _gp = . + 0x8000;
83 .lit8 : { 85 .lit8 : {
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index df8cbe4c7c0d..436a64ff3989 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -942,8 +942,8 @@ static int vpe_elfload(struct vpe * v)
942 if (phdr->p_type != PT_LOAD) 942 if (phdr->p_type != PT_LOAD)
943 continue; 943 continue;
944 944
945 memcpy((void *)phdr->p_vaddr, (char *)hdr + phdr->p_offset, phdr->p_filesz); 945 memcpy((void *)phdr->p_paddr, (char *)hdr + phdr->p_offset, phdr->p_filesz);
946 memset((void *)phdr->p_vaddr + phdr->p_filesz, 0, phdr->p_memsz - phdr->p_filesz); 946 memset((void *)phdr->p_paddr + phdr->p_filesz, 0, phdr->p_memsz - phdr->p_filesz);
947 phdr++; 947 phdr++;
948 } 948 }
949 949
diff --git a/arch/mips/lasat/setup.c b/arch/mips/lasat/setup.c
index 54827d0174bf..e072da4ff3b3 100644
--- a/arch/mips/lasat/setup.c
+++ b/arch/mips/lasat/setup.c
@@ -117,14 +117,11 @@ static struct notifier_block lasat_panic_block[] =
117 } 117 }
118}; 118};
119 119
120void plat_time_init(void) 120void __init plat_time_init(void)
121{ 121{
122 mips_hpt_frequency = lasat_board_info.li_cpu_hz / 2; 122 mips_hpt_frequency = lasat_board_info.li_cpu_hz / 2;
123}
124 123
125void __init plat_timer_setup(struct irqaction *irq) 124 change_c0_status(ST0_IM, IE_IRQ0);
126{
127 change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5);
128} 125}
129 126
130void __init plat_mem_setup(void) 127void __init plat_mem_setup(void)
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index 9d6243a8c15a..f02ce6308e51 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -127,26 +127,6 @@ unsigned long read_persistent_clock(void)
127 return mc146818_get_cmos_time(); 127 return mc146818_get_cmos_time();
128} 128}
129 129
130void __init plat_time_init(void)
131{
132 unsigned int est_freq;
133
134 /* Set Data mode - binary. */
135 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
136
137 est_freq = estimate_cpu_frequency();
138
139 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
140 (est_freq%1000000)*100/1000000);
141
142 cpu_khz = est_freq / 1000;
143
144 mips_scroll_message();
145#ifdef CONFIG_I8253 /* Only Malta has a PIT */
146 setup_pit_timer();
147#endif
148}
149
150void __init plat_perf_setup(void) 130void __init plat_perf_setup(void)
151{ 131{
152 cp0_perfcount_irq = -1; 132 cp0_perfcount_irq = -1;
@@ -166,14 +146,13 @@ void __init plat_perf_setup(void)
166 } 146 }
167} 147}
168 148
169void __init plat_timer_setup(struct irqaction *irq) 149unsigned int __init get_c0_compare_int(void)
170{ 150{
171#ifdef MSC01E_INT_BASE 151#ifdef MSC01E_INT_BASE
172 if (cpu_has_veic) { 152 if (cpu_has_veic) {
173 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); 153 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
174 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; 154 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
175 } 155 } else
176 else
177#endif 156#endif
178 { 157 {
179 if (cpu_has_vint) 158 if (cpu_has_vint)
@@ -181,13 +160,26 @@ void __init plat_timer_setup(struct irqaction *irq)
181 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; 160 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
182 } 161 }
183 162
184#ifdef CONFIG_MIPS_MT_SMTC 163 return mips_cpu_timer_irq;
185 setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << cp0_compare_irq); 164}
186#else 165
187 setup_irq(mips_cpu_timer_irq, irq); 166void __init plat_time_init(void)
188#endif /* CONFIG_MIPS_MT_SMTC */ 167{
189#ifdef CONFIG_SMP 168 unsigned int est_freq;
190 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); 169
170 /* Set Data mode - binary. */
171 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
172
173 est_freq = estimate_cpu_frequency();
174
175 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
176 (est_freq%1000000)*100/1000000);
177
178 cpu_khz = est_freq / 1000;
179
180 mips_scroll_message();
181#ifdef CONFIG_I8253 /* Only Malta has a PIT */
182 setup_pit_timer();
191#endif 183#endif
192 184
193 plat_perf_setup(); 185 plat_perf_setup();
diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c
index e7fa0d1078a3..bfaafa38846f 100644
--- a/arch/mips/mipssim/sim_time.c
+++ b/arch/mips/mipssim/sim_time.c
@@ -75,25 +75,6 @@ static unsigned int __init estimate_cpu_frequency(void)
75 return count; 75 return count;
76} 76}
77 77
78void __init plat_time_init(void)
79{
80 unsigned int est_freq, flags;
81
82 local_irq_save(flags);
83
84 /* Set Data mode - binary. */
85 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
86
87 est_freq = estimate_cpu_frequency();
88
89 printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000,
90 (est_freq % 1000000) * 100 / 1000000);
91
92 cpu_khz = est_freq / 1000;
93
94 local_irq_restore(flags);
95}
96
97static int mips_cpu_timer_irq; 78static int mips_cpu_timer_irq;
98 79
99static void mips_timer_dispatch(void) 80static void mips_timer_dispatch(void)
@@ -102,26 +83,37 @@ static void mips_timer_dispatch(void)
102} 83}
103 84
104 85
105void __init plat_timer_setup(struct irqaction *irq) 86unsigned __init get_c0_compare_int(void)
106{ 87{
88#ifdef MSC01E_INT_BASE
107 if (cpu_has_veic) { 89 if (cpu_has_veic) {
108 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); 90 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
109 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; 91 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
110 } else { 92 } else {
93#endif
111 if (cpu_has_vint) 94 if (cpu_has_vint)
112 set_vi_handler(cp0_compare_irq, mips_timer_dispatch); 95 set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
113 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; 96 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
114 } 97 }
115 98
116 /* we are using the cpu counter for timer interrupts */ 99 return mips_cpu_timer_irq;
117 setup_irq(mips_cpu_timer_irq, irq); 100}
118 101
119#ifdef CONFIG_SMP 102void __init plat_time_init(void)
120 /* irq_desc(riptor) is a global resource, when the interrupt overlaps 103{
121 on seperate cpu's the first one tries to handle the second interrupt. 104 unsigned int est_freq, flags;
122 The effect is that the int remains disabled on the second cpu. 105
123 Mark the interrupt with IRQ_PER_CPU to avoid any confusion */ 106 local_irq_save(flags);
124 irq_desc[mips_cpu_timer_irq].flags |= IRQ_PER_CPU; 107
125 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); 108 /* Set Data mode - binary. */
126#endif 109 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
110
111 est_freq = estimate_cpu_frequency();
112
113 printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000,
114 (est_freq % 1000000) * 100 / 1000000);
115
116 cpu_khz = est_freq / 1000;
117
118 local_irq_restore(flags);
127} 119}
diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c
index c55312f6fd3a..562abb77d1d5 100644
--- a/arch/mips/mm/c-r3k.c
+++ b/arch/mips/mm/c-r3k.c
@@ -7,7 +7,7 @@
7 * Tx39XX R4k style caches added. HK 7 * Tx39XX R4k style caches added. HK
8 * Copyright (C) 1998, 1999, 2000 Harald Koerfgen 8 * Copyright (C) 1998, 1999, 2000 Harald Koerfgen
9 * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov 9 * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
10 * Copyright (C) 2001, 2004 Maciej W. Rozycki 10 * Copyright (C) 2001, 2004, 2007 Maciej W. Rozycki
11 */ 11 */
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
@@ -26,8 +26,6 @@
26static unsigned long icache_size, dcache_size; /* Size in bytes */ 26static unsigned long icache_size, dcache_size; /* Size in bytes */
27static unsigned long icache_lsize, dcache_lsize; /* Size in bytes */ 27static unsigned long icache_lsize, dcache_lsize; /* Size in bytes */
28 28
29#undef DEBUG_CACHE
30
31unsigned long __init r3k_cache_size(unsigned long ca_flags) 29unsigned long __init r3k_cache_size(unsigned long ca_flags)
32{ 30{
33 unsigned long flags, status, dummy, size; 31 unsigned long flags, status, dummy, size;
@@ -217,26 +215,6 @@ static void r3k_flush_dcache_range(unsigned long start, unsigned long end)
217 write_c0_status(flags); 215 write_c0_status(flags);
218} 216}
219 217
220static inline unsigned long get_phys_page(unsigned long addr,
221 struct mm_struct *mm)
222{
223 pgd_t *pgd;
224 pud_t *pud;
225 pmd_t *pmd;
226 pte_t *pte;
227 unsigned long physpage;
228
229 pgd = pgd_offset(mm, addr);
230 pud = pud_offset(pgd, addr);
231 pmd = pmd_offset(pud, addr);
232 pte = pte_offset(pmd, addr);
233
234 if ((physpage = pte_val(*pte)) & _PAGE_VALID)
235 return KSEG0ADDR(physpage & PAGE_MASK);
236
237 return 0;
238}
239
240static inline void r3k_flush_cache_all(void) 218static inline void r3k_flush_cache_all(void)
241{ 219{
242} 220}
@@ -252,12 +230,40 @@ static void r3k_flush_cache_mm(struct mm_struct *mm)
252} 230}
253 231
254static void r3k_flush_cache_range(struct vm_area_struct *vma, 232static void r3k_flush_cache_range(struct vm_area_struct *vma,
255 unsigned long start, unsigned long end) 233 unsigned long start, unsigned long end)
256{ 234{
257} 235}
258 236
259static void r3k_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn) 237static void r3k_flush_cache_page(struct vm_area_struct *vma,
238 unsigned long addr, unsigned long pfn)
260{ 239{
240 unsigned long kaddr = KSEG0ADDR(pfn << PAGE_SHIFT);
241 int exec = vma->vm_flags & VM_EXEC;
242 struct mm_struct *mm = vma->vm_mm;
243 pgd_t *pgdp;
244 pud_t *pudp;
245 pmd_t *pmdp;
246 pte_t *ptep;
247
248 pr_debug("cpage[%08lx,%08lx]\n",
249 cpu_context(smp_processor_id(), mm), addr);
250
251 /* No ASID => no such page in the cache. */
252 if (cpu_context(smp_processor_id(), mm) == 0)
253 return;
254
255 pgdp = pgd_offset(mm, addr);
256 pudp = pud_offset(pgdp, addr);
257 pmdp = pmd_offset(pudp, addr);
258 ptep = pte_offset(pmdp, addr);
259
260 /* Invalid => no such page in the cache. */
261 if (!(pte_val(*ptep) & _PAGE_PRESENT))
262 return;
263
264 r3k_flush_dcache_range(kaddr, kaddr + PAGE_SIZE);
265 if (exec)
266 r3k_flush_icache_range(kaddr, kaddr + PAGE_SIZE);
261} 267}
262 268
263static void local_r3k_flush_data_cache_page(void *addr) 269static void local_r3k_flush_data_cache_page(void *addr)
@@ -272,9 +278,7 @@ static void r3k_flush_cache_sigtramp(unsigned long addr)
272{ 278{
273 unsigned long flags; 279 unsigned long flags;
274 280
275#ifdef DEBUG_CACHE 281 pr_debug("csigtramp[%08lx]\n", addr);
276 printk("csigtramp[%08lx]", addr);
277#endif
278 282
279 flags = read_c0_status(); 283 flags = read_c0_status();
280 284
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index d7088331fb0f..6806d58211b2 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -345,11 +345,26 @@ static void r4k___flush_cache_all(void)
345 r4k_on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1); 345 r4k_on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1);
346} 346}
347 347
348static inline int has_valid_asid(const struct mm_struct *mm)
349{
350#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
351 int i;
352
353 for_each_online_cpu(i)
354 if (cpu_context(i, mm))
355 return 1;
356
357 return 0;
358#else
359 return cpu_context(smp_processor_id(), mm);
360#endif
361}
362
348static inline void local_r4k_flush_cache_range(void * args) 363static inline void local_r4k_flush_cache_range(void * args)
349{ 364{
350 struct vm_area_struct *vma = args; 365 struct vm_area_struct *vma = args;
351 366
352 if (!(cpu_context(smp_processor_id(), vma->vm_mm))) 367 if (!(has_valid_asid(vma->vm_mm)))
353 return; 368 return;
354 369
355 r4k_blast_dcache(); 370 r4k_blast_dcache();
@@ -368,7 +383,7 @@ static inline void local_r4k_flush_cache_mm(void * args)
368{ 383{
369 struct mm_struct *mm = args; 384 struct mm_struct *mm = args;
370 385
371 if (!cpu_context(smp_processor_id(), mm)) 386 if (!has_valid_asid(mm))
372 return; 387 return;
373 388
374 /* 389 /*
@@ -420,7 +435,7 @@ static inline void local_r4k_flush_cache_page(void *args)
420 * If ownes no valid ASID yet, cannot possibly have gotten 435 * If ownes no valid ASID yet, cannot possibly have gotten
421 * this page into the cache. 436 * this page into the cache.
422 */ 437 */
423 if (cpu_context(smp_processor_id(), mm) == 0) 438 if (!has_valid_asid(mm))
424 return; 439 return;
425 440
426 addr &= PAGE_MASK; 441 addr &= PAGE_MASK;
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index b1b40527658b..33519ce49540 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -12,8 +12,8 @@
12#include <linux/dma-mapping.h> 12#include <linux/dma-mapping.h>
13#include <linux/mm.h> 13#include <linux/mm.h>
14#include <linux/module.h> 14#include <linux/module.h>
15#include <linux/string.h>
16#include <linux/scatterlist.h> 15#include <linux/scatterlist.h>
16#include <linux/string.h>
17 17
18#include <asm/cache.h> 18#include <asm/cache.h>
19#include <asm/io.h> 19#include <asm/io.h>
diff --git a/arch/mips/pci/fixup-pmcmsp.c b/arch/mips/pci/fixup-pmcmsp.c
index 00261211dbfa..65735b1b7665 100644
--- a/arch/mips/pci/fixup-pmcmsp.c
+++ b/arch/mips/pci/fixup-pmcmsp.c
@@ -202,7 +202,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
202 * RETURNS: IRQ number 202 * RETURNS: IRQ number
203 * 203 *
204 ****************************************************************************/ 204 ****************************************************************************/
205int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 205int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
206{ 206{
207#if !defined(CONFIG_PMC_MSP7120_GW) && !defined(CONFIG_PMC_MSP7120_EVAL) 207#if !defined(CONFIG_PMC_MSP7120_GW) && !defined(CONFIG_PMC_MSP7120_EVAL)
208 printk(KERN_WARNING "PCI: unknown board, no PCI IRQs assigned.\n"); 208 printk(KERN_WARNING "PCI: unknown board, no PCI IRQs assigned.\n");
diff --git a/arch/mips/pci/fixup-tb0219.c b/arch/mips/pci/fixup-tb0219.c
index 720a2b720c5c..ed87733f6796 100644
--- a/arch/mips/pci/fixup-tb0219.c
+++ b/arch/mips/pci/fixup-tb0219.c
@@ -2,7 +2,7 @@
2 * fixup-tb0219.c, The TANBAC TB0219 specific PCI fixups. 2 * fixup-tb0219.c, The TANBAC TB0219 specific PCI fixups.
3 * 3 *
4 * Copyright (C) 2003 Megasolution Inc. <matsu@megasolution.jp> 4 * Copyright (C) 2003 Megasolution Inc. <matsu@megasolution.jp>
5 * Copyright (C) 2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> 5 * Copyright (C) 2004-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
diff --git a/arch/mips/pci/ops-pmcmsp.c b/arch/mips/pci/ops-pmcmsp.c
index 059eade96f2e..109c95ca698b 100644
--- a/arch/mips/pci/ops-pmcmsp.c
+++ b/arch/mips/pci/ops-pmcmsp.c
@@ -404,7 +404,7 @@ int msp_pcibios_config_access(unsigned char access_type,
404 if (pciirqflag == 0) { 404 if (pciirqflag == 0) {
405 request_irq(MSP_INT_PCI,/* Hardcoded internal MSP7120 wiring */ 405 request_irq(MSP_INT_PCI,/* Hardcoded internal MSP7120 wiring */
406 bpci_interrupt, 406 bpci_interrupt,
407 SA_SHIRQ | SA_INTERRUPT, 407 IRQF_SHARED | IRQF_DISABLED,
408 "PMC MSP PCI Host", 408 "PMC MSP PCI Host",
409 preg); 409 preg);
410 pciirqflag = ~0; 410 pciirqflag = ~0;
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_serial.c b/arch/mips/pmc-sierra/msp71xx/msp_serial.c
index 15e7b8000b4c..9de34302e5f4 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_serial.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_serial.c
@@ -122,7 +122,7 @@ void __init msp_serial_setup(void)
122 up.uartclk = uartclk; 122 up.uartclk = uartclk;
123 up.regshift = 2; 123 up.regshift = 2;
124 up.iotype = UPIO_DWAPB; /* UPIO_MEM like */ 124 up.iotype = UPIO_DWAPB; /* UPIO_MEM like */
125 up.flags = STD_COM_FLAGS; 125 up.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
126 up.type = PORT_16550A; 126 up.type = PORT_16550A;
127 up.line = 0; 127 up.line = 0;
128 up.private_data = (void*)UART0_STATUS_REG; 128 up.private_data = (void*)UART0_STATUS_REG;
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index f5dccf01da11..dc59c3b708ed 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -131,12 +131,12 @@ static struct irq_chip rt_irq_type = {
131static int rt_next_event(unsigned long delta, struct clock_event_device *evt) 131static int rt_next_event(unsigned long delta, struct clock_event_device *evt)
132{ 132{
133 unsigned int cpu = smp_processor_id(); 133 unsigned int cpu = smp_processor_id();
134 int slice = cputoslice(cpu) == 0; 134 int slice putoslice(cpu);
135 unsigned long cnt; 135 unsigned long cnt;
136 136
137 cnt = LOCAL_HUB_L(PI_RT_COUNT); 137 cnt = LOCAL_HUB_L(PI_RT_COUNT);
138 cnt += delta; 138 cnt += delta;
139 LOCAL_HUB_S(slice ? PI_RT_COMPARE_A : PI_RT_COMPARE_B, cnt); 139 LOCAL_HUB_S(PI_RT_COMPARE_A + PI_COUNT_OFFSET * slice, cnt);
140 140
141 return LOCAL_HUB_L(PI_RT_COUNT) >= cnt ? -ETIME : 0; 141 return LOCAL_HUB_L(PI_RT_COUNT) >= cnt ? -ETIME : 0;
142} 142}
@@ -164,9 +164,12 @@ static irqreturn_t hub_rt_counter_handler(int irq, void *dev_id)
164{ 164{
165 struct clock_event_device *cd = dev_id; 165 struct clock_event_device *cd = dev_id;
166 unsigned int cpu = smp_processor_id(); 166 unsigned int cpu = smp_processor_id();
167 int slice = cputoslice(cpu) == 0; 167 int slice = cputoslice(cpu);
168 168
169 LOCAL_HUB_S(slice ? PI_RT_PEND_A : PI_RT_PEND_B, 0); /* Ack */ 169 /*
170 * Ack
171 */
172 LOCAL_HUB_S(PI_RT_PEND_A + PI_COUNT_OFFSET * slice, cnt);
170 cd->event_handler(cd); 173 cd->event_handler(cd);
171 174
172 return IRQ_HANDLED; 175 return IRQ_HANDLED;
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index 7e8094f617bf..aab17ddd2f30 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -40,13 +40,6 @@ static void inline flush_mace_bus(void)
40 mace->perif.ctrl.misc; 40 mace->perif.ctrl.misc;
41} 41}
42 42
43#undef DEBUG_IRQ
44#ifdef DEBUG_IRQ
45#define DBG(x...) printk(x)
46#else
47#define DBG(x...)
48#endif
49
50/* 43/*
51 * O2 irq map 44 * O2 irq map
52 * 45 *
@@ -125,6 +118,7 @@ struct irqaction memerr_irq = {
125 .mask = CPU_MASK_NONE, 118 .mask = CPU_MASK_NONE,
126 .name = "CRIME memory error", 119 .name = "CRIME memory error",
127}; 120};
121
128struct irqaction cpuerr_irq = { 122struct irqaction cpuerr_irq = {
129 .handler = crime_cpuerr_intr, 123 .handler = crime_cpuerr_intr,
130 .flags = IRQF_DISABLED, 124 .flags = IRQF_DISABLED,
@@ -139,46 +133,70 @@ struct irqaction cpuerr_irq = {
139 133
140static uint64_t crime_mask; 134static uint64_t crime_mask;
141 135
142static void enable_crime_irq(unsigned int irq) 136static inline void crime_enable_irq(unsigned int irq)
143{ 137{
144 crime_mask |= 1 << (irq - 1); 138 unsigned int bit = irq - CRIME_IRQ_BASE;
139
140 crime_mask |= 1 << bit;
145 crime->imask = crime_mask; 141 crime->imask = crime_mask;
146} 142}
147 143
148static void disable_crime_irq(unsigned int irq) 144static inline void crime_disable_irq(unsigned int irq)
149{ 145{
150 crime_mask &= ~(1 << (irq - 1)); 146 unsigned int bit = irq - CRIME_IRQ_BASE;
147
148 crime_mask &= ~(1 << bit);
151 crime->imask = crime_mask; 149 crime->imask = crime_mask;
152 flush_crime_bus(); 150 flush_crime_bus();
153} 151}
154 152
155static void mask_and_ack_crime_irq(unsigned int irq) 153static void crime_level_mask_and_ack_irq(unsigned int irq)
154{
155 crime_disable_irq(irq);
156}
157
158static void crime_level_end_irq(unsigned int irq)
159{
160 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
161 crime_enable_irq(irq);
162}
163
164static struct irq_chip crime_level_interrupt = {
165 .name = "IP32 CRIME",
166 .ack = crime_level_mask_and_ack_irq,
167 .mask = crime_disable_irq,
168 .mask_ack = crime_level_mask_and_ack_irq,
169 .unmask = crime_enable_irq,
170 .end = crime_level_end_irq,
171};
172
173static void crime_edge_mask_and_ack_irq(unsigned int irq)
156{ 174{
175 unsigned int bit = irq - CRIME_IRQ_BASE;
176 uint64_t crime_int;
177
157 /* Edge triggered interrupts must be cleared. */ 178 /* Edge triggered interrupts must be cleared. */
158 if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ) 179
159 || (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ) 180 crime_int = crime->hard_int;
160 || (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) { 181 crime_int &= ~(1 << bit);
161 uint64_t crime_int; 182 crime->hard_int = crime_int;
162 crime_int = crime->hard_int; 183
163 crime_int &= ~(1 << (irq - 1)); 184 crime_disable_irq(irq);
164 crime->hard_int = crime_int;
165 }
166 disable_crime_irq(irq);
167} 185}
168 186
169static void end_crime_irq(unsigned int irq) 187static void crime_edge_end_irq(unsigned int irq)
170{ 188{
171 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 189 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
172 enable_crime_irq(irq); 190 crime_enable_irq(irq);
173} 191}
174 192
175static struct irq_chip ip32_crime_interrupt = { 193static struct irq_chip crime_edge_interrupt = {
176 .name = "IP32 CRIME", 194 .name = "IP32 CRIME",
177 .ack = mask_and_ack_crime_irq, 195 .ack = crime_edge_mask_and_ack_irq,
178 .mask = disable_crime_irq, 196 .mask = crime_disable_irq,
179 .mask_ack = mask_and_ack_crime_irq, 197 .mask_ack = crime_edge_mask_and_ack_irq,
180 .unmask = enable_crime_irq, 198 .unmask = crime_enable_irq,
181 .end = end_crime_irq, 199 .end = crime_edge_end_irq,
182}; 200};
183 201
184/* 202/*
@@ -265,7 +283,7 @@ static void enable_maceisa_irq(unsigned int irq)
265{ 283{
266 unsigned int crime_int = 0; 284 unsigned int crime_int = 0;
267 285
268 DBG("maceisa enable: %u\n", irq); 286 pr_debug("maceisa enable: %u\n", irq);
269 287
270 switch (irq) { 288 switch (irq) {
271 case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ: 289 case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
@@ -278,7 +296,7 @@ static void enable_maceisa_irq(unsigned int irq)
278 crime_int = MACE_SUPERIO_INT; 296 crime_int = MACE_SUPERIO_INT;
279 break; 297 break;
280 } 298 }
281 DBG("crime_int %08x enabled\n", crime_int); 299 pr_debug("crime_int %08x enabled\n", crime_int);
282 crime_mask |= crime_int; 300 crime_mask |= crime_int;
283 crime->imask = crime_mask; 301 crime->imask = crime_mask;
284 maceisa_mask |= 1 << (irq - 33); 302 maceisa_mask |= 1 << (irq - 33);
@@ -290,11 +308,11 @@ static void disable_maceisa_irq(unsigned int irq)
290 unsigned int crime_int = 0; 308 unsigned int crime_int = 0;
291 309
292 maceisa_mask &= ~(1 << (irq - 33)); 310 maceisa_mask &= ~(1 << (irq - 33));
293 if(!(maceisa_mask & MACEISA_AUDIO_INT)) 311 if (!(maceisa_mask & MACEISA_AUDIO_INT))
294 crime_int |= MACE_AUDIO_INT; 312 crime_int |= MACE_AUDIO_INT;
295 if(!(maceisa_mask & MACEISA_MISC_INT)) 313 if (!(maceisa_mask & MACEISA_MISC_INT))
296 crime_int |= MACE_MISC_INT; 314 crime_int |= MACE_MISC_INT;
297 if(!(maceisa_mask & MACEISA_SUPERIO_INT)) 315 if (!(maceisa_mask & MACEISA_SUPERIO_INT))
298 crime_int |= MACE_SUPERIO_INT; 316 crime_int |= MACE_SUPERIO_INT;
299 crime_mask &= ~crime_int; 317 crime_mask &= ~crime_int;
300 crime->imask = crime_mask; 318 crime->imask = crime_mask;
@@ -327,12 +345,12 @@ static void end_maceisa_irq(unsigned irq)
327} 345}
328 346
329static struct irq_chip ip32_maceisa_interrupt = { 347static struct irq_chip ip32_maceisa_interrupt = {
330 .name = "IP32 MACE ISA", 348 .name = "IP32 MACE ISA",
331 .ack = mask_and_ack_maceisa_irq, 349 .ack = mask_and_ack_maceisa_irq,
332 .mask = disable_maceisa_irq, 350 .mask = disable_maceisa_irq,
333 .mask_ack = mask_and_ack_maceisa_irq, 351 .mask_ack = mask_and_ack_maceisa_irq,
334 .unmask = enable_maceisa_irq, 352 .unmask = enable_maceisa_irq,
335 .end = end_maceisa_irq, 353 .end = end_maceisa_irq,
336}; 354};
337 355
338/* This is used for regular non-ISA, non-PCI MACE interrupts. That means 356/* This is used for regular non-ISA, non-PCI MACE interrupts. That means
@@ -411,7 +429,7 @@ static void ip32_irq0(void)
411 irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ; 429 irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ;
412 } 430 }
413 431
414 DBG("*irq %u*\n", irq); 432 pr_debug("*irq %u*\n", irq);
415 do_IRQ(irq); 433 do_IRQ(irq);
416} 434}
417 435
@@ -472,23 +490,31 @@ void __init arch_init_irq(void)
472 490
473 mips_cpu_irq_init(); 491 mips_cpu_irq_init();
474 for (irq = MIPS_CPU_IRQ_BASE + 8; irq <= IP32_IRQ_MAX; irq++) { 492 for (irq = MIPS_CPU_IRQ_BASE + 8; irq <= IP32_IRQ_MAX; irq++) {
475 struct irq_chip *chip;
476
477 switch (irq) { 493 switch (irq) {
478 case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ: 494 case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
479 chip = &ip32_mace_interrupt; 495 set_irq_chip(irq, &ip32_mace_interrupt);
480 break; 496 break;
481 case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ: 497 case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ:
482 chip = &ip32_macepci_interrupt; 498 set_irq_chip(irq, &ip32_macepci_interrupt);
499 break;
500 case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
501 set_irq_chip(irq, &crime_edge_interrupt);
502 break;
503 case CRIME_CPUERR_IRQ:
504 case CRIME_MEMERR_IRQ:
505 set_irq_chip(irq, &crime_level_interrupt);
483 break; 506 break;
484 case CRIME_GBE0_IRQ ... CRIME_VICE_IRQ: 507 case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
485 chip = &ip32_crime_interrupt; 508 case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
509 set_irq_chip(irq, &crime_edge_interrupt);
510 break;
511 case CRIME_VICE_IRQ:
512 set_irq_chip(irq, &crime_edge_interrupt);
486 break; 513 break;
487 default: 514 default:
488 chip = &ip32_maceisa_interrupt; 515 set_irq_chip(irq, &ip32_maceisa_interrupt);
516 break;
489 } 517 }
490
491 set_irq_chip(irq, chip);
492 } 518 }
493 setup_irq(CRIME_MEMERR_IRQ, &memerr_irq); 519 setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
494 setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq); 520 setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 10299bafeab7..61790c4bfb60 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -280,27 +280,6 @@ static struct irqaction bcm1480_dummy_action = {
280 .dev_id = 0 280 .dev_id = 0
281}; 281};
282 282
283int bcm1480_steal_irq(int irq)
284{
285 struct irq_desc *desc = irq_desc + irq;
286 unsigned long flags;
287 int retval = 0;
288
289 if (irq >= BCM1480_NR_IRQS)
290 return -EINVAL;
291
292 spin_lock_irqsave(&desc->lock, flags);
293 /* Don't allow sharing at all for these */
294 if (desc->action != NULL)
295 retval = -EBUSY;
296 else {
297 desc->action = &bcm1480_dummy_action;
298 desc->depth = 0;
299 }
300 spin_unlock_irqrestore(&desc->lock, flags);
301 return 0;
302}
303
304/* 283/*
305 * init_IRQ is called early in the boot sequence from init/main.c. It 284 * init_IRQ is called early in the boot sequence from init/main.c. It
306 * is responsible for setting up the interrupt mapper and installing the 285 * is responsible for setting up the interrupt mapper and installing the
@@ -386,8 +365,6 @@ void __init arch_init_irq(void)
386 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L))); 365 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L)));
387 } 366 }
388 367
389 bcm1480_steal_irq(K_BCM1480_INT_MBOX_0_0);
390
391 /* 368 /*
392 * Note that the timer interrupts are also mapped, but this is 369 * Note that the timer interrupts are also mapped, but this is
393 * done in bcm1480_time_init(). Also, the profiling driver 370 * done in bcm1480_time_init(). Also, the profiling driver
@@ -411,7 +388,6 @@ void __init arch_init_irq(void)
411 /* QQQ FIXME */ 388 /* QQQ FIXME */
412 __raw_writeq(M_DUART_IMR_BRK, IO_SPACE_BASE + A_DUART_IMRREG(kgdb_port)); 389 __raw_writeq(M_DUART_IMR_BRK, IO_SPACE_BASE + A_DUART_IMRREG(kgdb_port));
413 390
414 bcm1480_steal_irq(kgdb_irq);
415 __raw_writeq(IMR_IP6_VAL, 391 __raw_writeq(IMR_IP6_VAL,
416 IO_SPACE_BASE + A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + 392 IO_SPACE_BASE + A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
417 (kgdb_irq<<3)); 393 (kgdb_irq<<3));
diff --git a/arch/mips/sibyte/bcm1480/time.c b/arch/mips/sibyte/bcm1480/time.c
index 610f0253954d..bbf19bfabccb 100644
--- a/arch/mips/sibyte/bcm1480/time.c
+++ b/arch/mips/sibyte/bcm1480/time.c
@@ -37,8 +37,6 @@
37#define IMR_IP3_VAL K_BCM1480_INT_MAP_I1 37#define IMR_IP3_VAL K_BCM1480_INT_MAP_I1
38#define IMR_IP4_VAL K_BCM1480_INT_MAP_I2 38#define IMR_IP4_VAL K_BCM1480_INT_MAP_I2
39 39
40extern int bcm1480_steal_irq(int irq);
41
42/* 40/*
43 * The general purpose timer ticks at 1MHz independent if 41 * The general purpose timer ticks at 1MHz independent if
44 * the rest of the system 42 * the rest of the system
@@ -121,7 +119,7 @@ void __cpuinit sb1480_clockevent_init(void)
121 sprintf(name, "bcm1480-counter %d", cpu); 119 sprintf(name, "bcm1480-counter %d", cpu);
122 cd->name = name; 120 cd->name = name;
123 cd->features = CLOCK_EVT_FEAT_PERIODIC | 121 cd->features = CLOCK_EVT_FEAT_PERIODIC |
124 CLOCK_EVT_MODE_ONESHOT; 122 CLOCK_EVT_FEAT_ONESHOT;
125 clockevent_set_clock(cd, V_SCD_TIMER_FREQ); 123 clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
126 cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd); 124 cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd);
127 cd->min_delta_ns = clockevent_delta2ns(1, cd); 125 cd->min_delta_ns = clockevent_delta2ns(1, cd);
@@ -142,7 +140,6 @@ void __cpuinit sb1480_clockevent_init(void)
142 R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (irq << 3))); 140 R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (irq << 3)));
143 141
144 bcm1480_unmask_irq(cpu, irq); 142 bcm1480_unmask_irq(cpu, irq);
145 bcm1480_steal_irq(irq);
146 143
147 action->handler = sibyte_counter_handler; 144 action->handler = sibyte_counter_handler;
148 action->flags = IRQF_DISABLED | IRQF_PERCPU; 145 action->flags = IRQF_DISABLED | IRQF_PERCPU;
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 53780a179d1d..52d18fc91f32 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -250,27 +250,6 @@ static struct irqaction sb1250_dummy_action = {
250 .dev_id = 0 250 .dev_id = 0
251}; 251};
252 252
253int sb1250_steal_irq(int irq)
254{
255 struct irq_desc *desc = irq_desc + irq;
256 unsigned long flags;
257 int retval = 0;
258
259 if (irq >= SB1250_NR_IRQS)
260 return -EINVAL;
261
262 spin_lock_irqsave(&desc->lock, flags);
263 /* Don't allow sharing at all for these */
264 if (desc->action != NULL)
265 retval = -EBUSY;
266 else {
267 desc->action = &sb1250_dummy_action;
268 desc->depth = 0;
269 }
270 spin_unlock_irqrestore(&desc->lock, flags);
271 return 0;
272}
273
274/* 253/*
275 * arch_init_irq is called early in the boot sequence from init/main.c via 254 * arch_init_irq is called early in the boot sequence from init/main.c via
276 * init_IRQ. It is responsible for setting up the interrupt mapper and 255 * init_IRQ. It is responsible for setting up the interrupt mapper and
@@ -342,8 +321,6 @@ void __init arch_init_irq(void)
342 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK))); 321 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
343 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK))); 322 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
344 323
345 sb1250_steal_irq(K_INT_MBOX_0);
346
347 /* 324 /*
348 * Note that the timer interrupts are also mapped, but this is 325 * Note that the timer interrupts are also mapped, but this is
349 * done in sb1250_time_init(). Also, the profiling driver 326 * done in sb1250_time_init(). Also, the profiling driver
@@ -367,7 +344,6 @@ void __init arch_init_irq(void)
367 __raw_writeq(M_DUART_IMR_BRK, 344 __raw_writeq(M_DUART_IMR_BRK,
368 IOADDR(A_DUART_IMRREG(kgdb_port))); 345 IOADDR(A_DUART_IMRREG(kgdb_port)));
369 346
370 sb1250_steal_irq(kgdb_irq);
371 __raw_writeq(IMR_IP6_VAL, 347 __raw_writeq(IMR_IP6_VAL,
372 IOADDR(A_IMR_REGISTER(0, 348 IOADDR(A_IMR_REGISTER(0,
373 R_IMR_INTERRUPT_MAP_BASE) + 349 R_IMR_INTERRUPT_MAP_BASE) +
diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c
index a41e908bc218..95ad34e3fbac 100644
--- a/arch/mips/sibyte/sb1250/time.c
+++ b/arch/mips/sibyte/sb1250/time.c
@@ -50,8 +50,6 @@
50#define SB1250_HPT_VALUE M_SCD_TIMER_CNT /* max value */ 50#define SB1250_HPT_VALUE M_SCD_TIMER_CNT /* max value */
51 51
52 52
53extern int sb1250_steal_irq(int irq);
54
55/* 53/*
56 * The general purpose timer ticks at 1 Mhz independent if 54 * The general purpose timer ticks at 1 Mhz independent if
57 * the rest of the system 55 * the rest of the system
@@ -139,7 +137,7 @@ void __cpuinit sb1250_clockevent_init(void)
139 sprintf(name, "bcm1480-counter %d", cpu); 137 sprintf(name, "bcm1480-counter %d", cpu);
140 cd->name = name; 138 cd->name = name;
141 cd->features = CLOCK_EVT_FEAT_PERIODIC | 139 cd->features = CLOCK_EVT_FEAT_PERIODIC |
142 CLOCK_EVT_MODE_ONESHOT; 140 CLOCK_EVT_FEAT_ONESHOT;
143 clockevent_set_clock(cd, V_SCD_TIMER_FREQ); 141 clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
144 cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd); 142 cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd);
145 cd->min_delta_ns = clockevent_delta2ns(1, cd); 143 cd->min_delta_ns = clockevent_delta2ns(1, cd);
@@ -159,7 +157,6 @@ void __cpuinit sb1250_clockevent_init(void)
159 cd->cpumask = cpumask_of_cpu(0); 157 cd->cpumask = cpumask_of_cpu(0);
160 158
161 sb1250_unmask_irq(cpu, irq); 159 sb1250_unmask_irq(cpu, irq);
162 sb1250_steal_irq(irq);
163 160
164 action->handler = sibyte_counter_handler; 161 action->handler = sibyte_counter_handler;
165 action->flags = IRQF_DISABLED | IRQF_PERCPU; 162 action->flags = IRQF_DISABLED | IRQF_PERCPU;
diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c
index 0910b35cb71f..60bc62ef0935 100644
--- a/arch/mips/sni/time.c
+++ b/arch/mips/sni/time.c
@@ -11,27 +11,78 @@
11#define SNI_COUNTER2_DIV 64 11#define SNI_COUNTER2_DIV 64
12#define SNI_COUNTER0_DIV ((SNI_CLOCK_TICK_RATE / SNI_COUNTER2_DIV) / HZ) 12#define SNI_COUNTER0_DIV ((SNI_CLOCK_TICK_RATE / SNI_COUNTER2_DIV) / HZ)
13 13
14static void sni_a20r_timer_ack(void) 14static void a20r_set_mode(enum clock_event_mode mode,
15 struct clock_event_device *evt)
15{ 16{
16 *(volatile u8 *)A20R_PT_TIM0_ACK = 0x0; wmb(); 17 switch (mode) {
18 case CLOCK_EVT_MODE_PERIODIC:
19 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0x34;
20 wmb();
21 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = SNI_COUNTER0_DIV;
22 wmb();
23 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = SNI_COUNTER0_DIV >> 8;
24 wmb();
25
26 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0xb4;
27 wmb();
28 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = SNI_COUNTER2_DIV;
29 wmb();
30 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = SNI_COUNTER2_DIV >> 8;
31 wmb();
32
33 break;
34 case CLOCK_EVT_MODE_ONESHOT:
35 case CLOCK_EVT_MODE_UNUSED:
36 case CLOCK_EVT_MODE_SHUTDOWN:
37 break;
38 case CLOCK_EVT_MODE_RESUME:
39 break;
40 }
17} 41}
18 42
43static struct clock_event_device a20r_clockevent_device = {
44 .name = "a20r-timer",
45 .features = CLOCK_EVT_FEAT_PERIODIC,
46
47 /* .mult, .shift, .max_delta_ns and .min_delta_ns left uninitialized */
48
49 .rating = 300,
50 .irq = SNI_A20R_IRQ_TIMER,
51 .set_mode = a20r_set_mode,
52};
53
54static irqreturn_t a20r_interrupt(int irq, void *dev_id)
55{
56 struct clock_event_device *cd = dev_id;
57
58 *(volatile u8 *)A20R_PT_TIM0_ACK = 0;
59 wmb();
60
61 cd->event_handler(cd);
62
63 return IRQ_HANDLED;
64}
65
66static struct irqaction a20r_irqaction = {
67 .handler = a20r_interrupt,
68 .flags = IRQF_DISABLED | IRQF_PERCPU,
69 .name = "a20r-timer",
70};
71
19/* 72/*
20 * a20r platform uses 2 counters to divide the input frequency. 73 * a20r platform uses 2 counters to divide the input frequency.
21 * Counter 2 output is connected to Counter 0 & 1 input. 74 * Counter 2 output is connected to Counter 0 & 1 input.
22 */ 75 */
23static void __init sni_a20r_timer_setup(struct irqaction *irq) 76static void __init sni_a20r_timer_setup(void)
24{ 77{
25 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0x34; wmb(); 78 struct clock_event_device *cd = &a20r_clockevent_device;
26 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = (SNI_COUNTER0_DIV) & 0xff; wmb(); 79 struct irqaction *action = &a20r_irqaction;
27 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = (SNI_COUNTER0_DIV >> 8) & 0xff; wmb(); 80 unsigned int cpu = smp_processor_id();
28 81
29 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0xb4; wmb(); 82 cd->cpumask = cpumask_of_cpu(cpu);
30 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = (SNI_COUNTER2_DIV) & 0xff; wmb();
31 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = (SNI_COUNTER2_DIV >> 8) & 0xff; wmb();
32 83
33 setup_irq(SNI_A20R_IRQ_TIMER, irq); 84 action->dev_id = cd;
34 mips_timer_ack = sni_a20r_timer_ack; 85 setup_irq(SNI_A20R_IRQ_TIMER, &a20r_irqaction);
35} 86}
36 87
37#define SNI_8254_TICK_RATE 1193182UL 88#define SNI_8254_TICK_RATE 1193182UL
@@ -119,17 +170,14 @@ void __init plat_time_init(void)
119 mips_hpt_frequency = r4k_tick * HZ; 170 mips_hpt_frequency = r4k_tick * HZ;
120 171
121 setup_pit_timer(); 172 setup_pit_timer();
122}
123 173
124void __init plat_timer_setup(struct irqaction *irq)
125{
126 switch (sni_brd_type) { 174 switch (sni_brd_type) {
127 case SNI_BRD_10: 175 case SNI_BRD_10:
128 case SNI_BRD_10NEW: 176 case SNI_BRD_10NEW:
129 case SNI_BRD_TOWER_OASIC: 177 case SNI_BRD_TOWER_OASIC:
130 case SNI_BRD_MINITOWER: 178 case SNI_BRD_MINITOWER:
131 sni_a20r_timer_setup(irq); 179 sni_a20r_timer_setup();
132 break; 180 break;
133 } 181 }
134} 182}
135 183
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
index c7470fba6180..0299595ce1c4 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
@@ -63,6 +63,7 @@
63#include <asm/processor.h> 63#include <asm/processor.h>
64#include <asm/reboot.h> 64#include <asm/reboot.h>
65#include <asm/time.h> 65#include <asm/time.h>
66#include <asm/txx9tmr.h>
66#include <linux/bootmem.h> 67#include <linux/bootmem.h>
67#include <linux/blkdev.h> 68#include <linux/blkdev.h>
68#ifdef CONFIG_TOSHIBA_FPCIB0 69#ifdef CONFIG_TOSHIBA_FPCIB0
@@ -93,7 +94,6 @@
93 94
94#define TOSHIBA_RBTX4927_SETUP_EFWFU ( 1 << 3 ) 95#define TOSHIBA_RBTX4927_SETUP_EFWFU ( 1 << 3 )
95#define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 ) 96#define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 )
96#define TOSHIBA_RBTX4927_SETUP_TIME_INIT ( 1 << 5 )
97#define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 ) 97#define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 )
98#define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 ) 98#define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 )
99#define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 ) 99#define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 )
@@ -130,7 +130,6 @@ extern void toshiba_rbtx4927_power_off(void);
130 130
131int tx4927_using_backplane = 0; 131int tx4927_using_backplane = 0;
132 132
133extern void gt64120_time_init(void);
134extern void toshiba_rbtx4927_irq_setup(void); 133extern void toshiba_rbtx4927_irq_setup(void);
135 134
136char *prom_getcmdline(void); 135char *prom_getcmdline(void);
@@ -721,6 +720,7 @@ void toshiba_rbtx4927_power_off(void)
721 720
722void __init toshiba_rbtx4927_setup(void) 721void __init toshiba_rbtx4927_setup(void)
723{ 722{
723 int i;
724 u32 cp0_config; 724 u32 cp0_config;
725 char *argptr; 725 char *argptr;
726 726
@@ -764,6 +764,9 @@ void __init toshiba_rbtx4927_setup(void)
764 _machine_halt = toshiba_rbtx4927_halt; 764 _machine_halt = toshiba_rbtx4927_halt;
765 pm_power_off = toshiba_rbtx4927_power_off; 765 pm_power_off = toshiba_rbtx4927_power_off;
766 766
767 for (i = 0; i < TX4927_NR_TMR; i++)
768 txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL);
769
767#ifdef CONFIG_PCI 770#ifdef CONFIG_PCI
768 771
769 /* PCIC */ 772 /* PCIC */
@@ -892,7 +895,6 @@ void __init toshiba_rbtx4927_setup(void)
892#ifdef CONFIG_SERIAL_TXX9 895#ifdef CONFIG_SERIAL_TXX9
893 { 896 {
894 extern int early_serial_txx9_setup(struct uart_port *port); 897 extern int early_serial_txx9_setup(struct uart_port *port);
895 int i;
896 struct uart_port req; 898 struct uart_port req;
897 for(i = 0; i < 2; i++) { 899 for(i = 0; i < 2; i++) {
898 memset(&req, 0, sizeof(req)); 900 memset(&req, 0, sizeof(req));
@@ -937,12 +939,11 @@ void __init toshiba_rbtx4927_setup(void)
937void __init 939void __init
938toshiba_rbtx4927_time_init(void) 940toshiba_rbtx4927_time_init(void)
939{ 941{
940 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "-\n");
941
942 mips_hpt_frequency = tx4927_cpu_clock / 2; 942 mips_hpt_frequency = tx4927_cpu_clock / 2;
943 943 if (tx4927_ccfgptr->ccfg & TX4927_CCFG_TINTDIS)
944 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "+\n"); 944 txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL,
945 945 TXX9_IRQ_BASE + 17,
946 50000000);
946} 947}
947 948
948static int __init toshiba_rbtx4927_rtc_init(void) 949static int __init toshiba_rbtx4927_rtc_init(void)
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
index ceecaf498957..4a8152375efe 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/setup.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
@@ -26,6 +26,7 @@
26#include <asm/reboot.h> 26#include <asm/reboot.h>
27#include <asm/irq.h> 27#include <asm/irq.h>
28#include <asm/time.h> 28#include <asm/time.h>
29#include <asm/txx9tmr.h>
29#include <asm/uaccess.h> 30#include <asm/uaccess.h>
30#include <asm/io.h> 31#include <asm/io.h>
31#include <asm/bootinfo.h> 32#include <asm/bootinfo.h>
@@ -773,15 +774,8 @@ void __init tx4938_board_setup(void)
773 } 774 }
774 775
775 /* TMR */ 776 /* TMR */
776 /* disable all timers */ 777 for (i = 0; i < TX4938_NR_TMR; i++)
777 for (i = 0; i < TX4938_NR_TMR; i++) { 778 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
778 tx4938_tmrptr(i)->tcr = 0x00000020;
779 tx4938_tmrptr(i)->tisr = 0;
780 tx4938_tmrptr(i)->cpra = 0xffffffff;
781 tx4938_tmrptr(i)->itmr = 0;
782 tx4938_tmrptr(i)->ccdr = 0;
783 tx4938_tmrptr(i)->pgmr = 0;
784 }
785 779
786 /* enable DMA */ 780 /* enable DMA */
787 TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN); 781 TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN);
@@ -852,12 +846,13 @@ void tx4938_report_pcic_status(void)
852 846
853#endif /* CONFIG_PCI */ 847#endif /* CONFIG_PCI */
854 848
855/* We use onchip r4k counter or TMR timer as our system wide timer
856 * interrupt running at 100HZ. */
857
858void __init plat_time_init(void) 849void __init plat_time_init(void)
859{ 850{
860 mips_hpt_frequency = txx9_cpu_clock / 2; 851 mips_hpt_frequency = txx9_cpu_clock / 2;
852 if (tx4938_ccfgptr->ccfg & TX4938_CCFG_TINTDIS)
853 txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL,
854 TXX9_IRQ_BASE + TX4938_IR_TMR(0),
855 txx9_gbus_clock / 2);
861} 856}
862 857
863void __init toshiba_rbtx4938_setup(void) 858void __init toshiba_rbtx4938_setup(void)
diff --git a/include/asm-mips/ip32/ip32_ints.h b/include/asm-mips/ip32/ip32_ints.h
index 042f821899a8..ab5612f90f6f 100644
--- a/include/asm-mips/ip32/ip32_ints.h
+++ b/include/asm-mips/ip32/ip32_ints.h
@@ -22,10 +22,12 @@ enum ip32_irq_no {
22 * CPU interrupts are 0 ... 7 22 * CPU interrupts are 0 ... 7
23 */ 23 */
24 24
25 CRIME_IRQ_BASE = MIPS_CPU_IRQ_BASE,
26
25 /* 27 /*
26 * MACE 28 * MACE
27 */ 29 */
28 MACE_VID_IN1_IRQ = MIPS_CPU_IRQ_BASE + 8, 30 MACE_VID_IN1_IRQ = CRIME_IRQ_BASE,
29 MACE_VID_IN2_IRQ, 31 MACE_VID_IN2_IRQ,
30 MACE_VID_OUT_IRQ, 32 MACE_VID_OUT_IRQ,
31 MACE_ETHERNET_IRQ, 33 MACE_ETHERNET_IRQ,
diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h
index b2dc35f56181..81602c8047eb 100644
--- a/include/asm-mips/jmr3927/jmr3927.h
+++ b/include/asm-mips/jmr3927/jmr3927.h
@@ -132,9 +132,7 @@
132#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA) 132#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA)
133#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO) 133#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO)
134#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI) 134#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI)
135#define JMR3927_IRQ_IRC_TMR0 (JMR3927_IRQ_IRC + TX3927_IR_TMR0) 135#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch))
136#define JMR3927_IRQ_IRC_TMR1 (JMR3927_IRQ_IRC + TX3927_IR_TMR1)
137#define JMR3927_IRQ_IRC_TMR2 (JMR3927_IRQ_IRC + TX3927_IR_TMR2)
138#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA) 136#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA)
139#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB) 137#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB)
140#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC) 138#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC)
@@ -148,17 +146,12 @@
148#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1 146#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1
149/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */ 147/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */
150#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3 148#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3
151/* Clock Tick (10ms) */
152#define JMR3927_IRQ_TICK JMR3927_IRQ_IRC_TMR0
153 149
154/* Clocks */ 150/* Clocks */
155#define JMR3927_CORECLK 132710400 /* 132.7MHz */ 151#define JMR3927_CORECLK 132710400 /* 132.7MHz */
156#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */ 152#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */
157#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */ 153#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */
158 154
159#define jmr3927_tmrptr tx3927_tmrptr(0) /* TMR0 */
160
161
162/* 155/*
163 * TX3927 Pin Configuration: 156 * TX3927 Pin Configuration:
164 * 157 *
diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h
index 211bcf47fffb..338f99882a39 100644
--- a/include/asm-mips/jmr3927/tx3927.h
+++ b/include/asm-mips/jmr3927/tx3927.h
@@ -222,9 +222,7 @@ struct tx3927_ccfg_reg {
222#define TX3927_IR_DMA 8 222#define TX3927_IR_DMA 8
223#define TX3927_IR_PIO 9 223#define TX3927_IR_PIO 9
224#define TX3927_IR_PCI 10 224#define TX3927_IR_PCI 10
225#define TX3927_IR_TMR0 13 225#define TX3927_IR_TMR(ch) (13 + (ch))
226#define TX3927_IR_TMR1 14
227#define TX3927_IR_TMR2 15
228#define TX3927_NUM_IR 16 226#define TX3927_NUM_IR 16
229 227
230/* 228/*
diff --git a/include/asm-mips/jmr3927/txx927.h b/include/asm-mips/jmr3927/txx927.h
index 58a8ff6be815..0474fe8dac3f 100644
--- a/include/asm-mips/jmr3927/txx927.h
+++ b/include/asm-mips/jmr3927/txx927.h
@@ -10,22 +10,6 @@
10#ifndef __ASM_TXX927_H 10#ifndef __ASM_TXX927_H
11#define __ASM_TXX927_H 11#define __ASM_TXX927_H
12 12
13struct txx927_tmr_reg {
14 volatile unsigned long tcr;
15 volatile unsigned long tisr;
16 volatile unsigned long cpra;
17 volatile unsigned long cprb;
18 volatile unsigned long itmr;
19 volatile unsigned long unused0[3];
20 volatile unsigned long ccdr;
21 volatile unsigned long unused1[3];
22 volatile unsigned long pgmr;
23 volatile unsigned long unused2[3];
24 volatile unsigned long wtmr;
25 volatile unsigned long unused3[43];
26 volatile unsigned long trr;
27};
28
29struct txx927_sio_reg { 13struct txx927_sio_reg {
30 volatile unsigned long lcr; 14 volatile unsigned long lcr;
31 volatile unsigned long dicr; 15 volatile unsigned long dicr;
@@ -51,27 +35,6 @@ struct txx927_pio_reg {
51}; 35};
52 36
53/* 37/*
54 * TMR
55 */
56/* TMTCR : Timer Control */
57#define TXx927_TMTCR_TCE 0x00000080
58#define TXx927_TMTCR_CCDE 0x00000040
59#define TXx927_TMTCR_CRE 0x00000020
60#define TXx927_TMTCR_ECES 0x00000008
61#define TXx927_TMTCR_CCS 0x00000004
62#define TXx927_TMTCR_TMODE_MASK 0x00000003
63#define TXx927_TMTCR_TMODE_ITVL 0x00000000
64
65/* TMTISR : Timer Int. Status */
66#define TXx927_TMTISR_TPIBS 0x00000004
67#define TXx927_TMTISR_TPIAS 0x00000002
68#define TXx927_TMTISR_TIIS 0x00000001
69
70/* TMTITMR : Interval Timer Mode */
71#define TXx927_TMTITMR_TIIE 0x00008000
72#define TXx927_TMTITMR_TZCE 0x00000001
73
74/*
75 * SIO 38 * SIO
76 */ 39 */
77/* SILCR : Line Control */ 40/* SILCR : Line Control */
diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h
index bc47af313bcd..0a6bc7dc158e 100644
--- a/include/asm-mips/time.h
+++ b/include/asm-mips/time.h
@@ -58,7 +58,6 @@ extern void local_timer_interrupt(int irq, void *dev_id);
58 */ 58 */
59struct irqaction; 59struct irqaction;
60extern void plat_time_init(void); 60extern void plat_time_init(void);
61extern void plat_timer_setup(struct irqaction *irq);
62 61
63/* 62/*
64 * mips_hpt_frequency - must be set if you intend to use an R4k-compatible 63 * mips_hpt_frequency - must be set if you intend to use an R4k-compatible
@@ -78,6 +77,7 @@ extern int (*perf_irq)(void);
78 */ 77 */
79#ifdef CONFIG_CEVT_R4K 78#ifdef CONFIG_CEVT_R4K
80extern void mips_clockevent_init(void); 79extern void mips_clockevent_init(void);
80extern unsigned int __weak get_c0_compare_int(void);
81#else 81#else
82static inline void mips_clockevent_init(void) 82static inline void mips_clockevent_init(void)
83{ 83{
diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h
index f98b2bb719d5..3f1e470192e3 100644
--- a/include/asm-mips/tx4927/tx4927_pci.h
+++ b/include/asm-mips/tx4927/tx4927_pci.h
@@ -9,6 +9,7 @@
9#define __ASM_TX4927_TX4927_PCI_H 9#define __ASM_TX4927_TX4927_PCI_H
10 10
11#define TX4927_CCFG_TOE 0x00004000 11#define TX4927_CCFG_TOE 0x00004000
12#define TX4927_CCFG_TINTDIS 0x01000000
12 13
13#define TX4927_PCIMEM 0x08000000 14#define TX4927_PCIMEM 0x08000000
14#define TX4927_PCIMEM_SIZE 0x08000000 15#define TX4927_PCIMEM_SIZE 0x08000000
@@ -20,6 +21,8 @@
20#define TX4927_PCIC_REG 0xff1fd000 21#define TX4927_PCIC_REG 0xff1fd000
21#define TX4927_CCFG_REG 0xff1fe000 22#define TX4927_CCFG_REG 0xff1fe000
22#define TX4927_IRC_REG 0xff1ff600 23#define TX4927_IRC_REG 0xff1ff600
24#define TX4927_NR_TMR 3
25#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100)
23#define TX4927_CE3 0x17f00000 /* 1M */ 26#define TX4927_CE3 0x17f00000 /* 1M */
24#define TX4927_PCIRESET_ADDR 0xbc00f006 27#define TX4927_PCIRESET_ADDR 0xbc00f006
25#define TX4927_PCI_CLK_ADDR (KSEG1 + TX4927_CE3 + 0x00040020) 28#define TX4927_PCI_CLK_ADDR (KSEG1 + TX4927_CE3 + 0x00040020)
diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h
index 650b010761f9..f7c448b90578 100644
--- a/include/asm-mips/tx4938/tx4938.h
+++ b/include/asm-mips/tx4938/tx4938.h
@@ -641,7 +641,6 @@ struct tx4938_ccfg_reg {
641#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG) 641#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG)
642#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG) 642#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG)
643#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG) 643#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG)
644#define tx4938_tmrptr(ch) ((struct tx4938_tmr_reg *)TX4938_TMR_REG(ch))
645#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch)) 644#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
646#define tx4938_pioptr ((struct tx4938_pio_reg *)TX4938_PIO_REG) 645#define tx4938_pioptr ((struct tx4938_pio_reg *)TX4938_PIO_REG)
647#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG) 646#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG)
diff --git a/include/asm-mips/txx9tmr.h b/include/asm-mips/txx9tmr.h
new file mode 100644
index 000000000000..67f70a8f09bd
--- /dev/null
+++ b/include/asm-mips/txx9tmr.h
@@ -0,0 +1,67 @@
1/*
2 * include/asm-mips/txx9tmr.h
3 * TX39/TX49 timer controller definitions.
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 */
9#ifndef __ASM_TXX9TMR_H
10#define __ASM_TXX9TMR_H
11
12#include <linux/types.h>
13
14struct txx9_tmr_reg {
15 u32 tcr;
16 u32 tisr;
17 u32 cpra;
18 u32 cprb;
19 u32 itmr;
20 u32 unused0[3];
21 u32 ccdr;
22 u32 unused1[3];
23 u32 pgmr;
24 u32 unused2[3];
25 u32 wtmr;
26 u32 unused3[43];
27 u32 trr;
28};
29
30/* TMTCR : Timer Control */
31#define TXx9_TMTCR_TCE 0x00000080
32#define TXx9_TMTCR_CCDE 0x00000040
33#define TXx9_TMTCR_CRE 0x00000020
34#define TXx9_TMTCR_ECES 0x00000008
35#define TXx9_TMTCR_CCS 0x00000004
36#define TXx9_TMTCR_TMODE_MASK 0x00000003
37#define TXx9_TMTCR_TMODE_ITVL 0x00000000
38#define TXx9_TMTCR_TMODE_PGEN 0x00000001
39#define TXx9_TMTCR_TMODE_WDOG 0x00000002
40
41/* TMTISR : Timer Int. Status */
42#define TXx9_TMTISR_TPIBS 0x00000004
43#define TXx9_TMTISR_TPIAS 0x00000002
44#define TXx9_TMTISR_TIIS 0x00000001
45
46/* TMITMR : Interval Timer Mode */
47#define TXx9_TMITMR_TIIE 0x00008000
48#define TXx9_TMITMR_TZCE 0x00000001
49
50/* TMWTMR : Watchdog Timer Mode */
51#define TXx9_TMWTMR_TWIE 0x00008000
52#define TXx9_TMWTMR_WDIS 0x00000080
53#define TXx9_TMWTMR_TWC 0x00000001
54
55void txx9_clocksource_init(unsigned long baseaddr,
56 unsigned int imbusclk);
57void txx9_clockevent_init(unsigned long baseaddr, int irq,
58 unsigned int imbusclk);
59void txx9_tmr_init(unsigned long baseaddr);
60
61#ifdef CONFIG_CPU_TX39XX
62#define TXX9_TIMER_BITS 24
63#else
64#define TXX9_TIMER_BITS 32
65#endif
66
67#endif /* __ASM_TXX9TMR_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-04 21:29:20 -0500