diff options
author | Vladimir Barinov <vbarinov@ru.mvista.com> | 2007-11-14 11:07:17 -0500 |
---|---|---|
committer | Jaroslav Kysela <perex@perex.cz> | 2008-01-31 11:29:23 -0500 |
commit | 44d0a879951a90a4eb463fb1d3b91942f97f36ca (patch) | |
tree | da8ee068c6233dfe69b88803288cc36b0bab565c | |
parent | 3a749730afc224ac11f4eff3df58a42494a0f035 (diff) |
[ALSA] ASoC TLV320AIC3X codec driver
This patch adds ALSA SoC support for TI TLV320AIC3X audio codecs.
The features that are supported:
o Capture/Playback/Bypass.
o 16/20/24/32 bit audio.
o 8k - 96k sample rates.
o codec master only mode
o DAPM.
Signed-off-by: Vladimir Barinov <vbarinov@ru.mvista.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Jaroslav Kysela <perex@perex.cz>
-rw-r--r-- | sound/soc/codecs/Kconfig | 3 | ||||
-rw-r--r-- | sound/soc/codecs/Makefile | 2 | ||||
-rw-r--r-- | sound/soc/codecs/tlv320aic3x.c | 1275 | ||||
-rw-r--r-- | sound/soc/codecs/tlv320aic3x.h | 181 |
4 files changed, 1461 insertions, 0 deletions
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 78248808a9d8..898a7d363284 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig | |||
@@ -37,3 +37,6 @@ config SND_SOC_CS4270_VD33_ERRATA | |||
37 | bool | 37 | bool |
38 | depends on SND_SOC_CS4270 | 38 | depends on SND_SOC_CS4270 |
39 | 39 | ||
40 | config SND_SOC_TLV320AIC3X | ||
41 | tristate | ||
42 | depends on SND_SOC && I2C | ||
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 7ad78e36d506..c6e5338c2666 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile | |||
@@ -4,6 +4,7 @@ snd-soc-wm8750-objs := wm8750.o | |||
4 | snd-soc-wm8753-objs := wm8753.o | 4 | snd-soc-wm8753-objs := wm8753.o |
5 | snd-soc-wm9712-objs := wm9712.o | 5 | snd-soc-wm9712-objs := wm9712.o |
6 | snd-soc-cs4270-objs := cs4270.o | 6 | snd-soc-cs4270-objs := cs4270.o |
7 | snd-soc-tlv320aic3x-objs := tlv320aic3x.o | ||
7 | 8 | ||
8 | obj-$(CONFIG_SND_SOC_AC97_CODEC) += snd-soc-ac97.o | 9 | obj-$(CONFIG_SND_SOC_AC97_CODEC) += snd-soc-ac97.o |
9 | obj-$(CONFIG_SND_SOC_WM8731) += snd-soc-wm8731.o | 10 | obj-$(CONFIG_SND_SOC_WM8731) += snd-soc-wm8731.o |
@@ -11,3 +12,4 @@ obj-$(CONFIG_SND_SOC_WM8750) += snd-soc-wm8750.o | |||
11 | obj-$(CONFIG_SND_SOC_WM8753) += snd-soc-wm8753.o | 12 | obj-$(CONFIG_SND_SOC_WM8753) += snd-soc-wm8753.o |
12 | obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o | 13 | obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o |
13 | obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o | 14 | obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o |
15 | obj-$(CONFIG_SND_SOC_TLV320AIC3X) += snd-soc-tlv320aic3x.o | ||
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c new file mode 100644 index 000000000000..c075a28949f6 --- /dev/null +++ b/sound/soc/codecs/tlv320aic3x.c | |||
@@ -0,0 +1,1275 @@ | |||
1 | /* | ||
2 | * ALSA SoC TLV320AIC3X codec driver | ||
3 | * | ||
4 | * Author: Vladimir Barinov, <vbarinov@ru.mvista.com> | ||
5 | * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> | ||
6 | * | ||
7 | * Based on sound/soc/codecs/wm8753.c by Liam Girdwood | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * Notes: | ||
14 | * The AIC3X is a driver for a low power stereo audio | ||
15 | * codecs aic31, aic32, aic33. | ||
16 | * | ||
17 | * It supports full aic33 codec functionality. | ||
18 | * The compatibility with aic32, aic31 is as follows: | ||
19 | * aic32 | aic31 | ||
20 | * --------------------------------------- | ||
21 | * MONO_LOUT -> N/A | MONO_LOUT -> N/A | ||
22 | * | IN1L -> LINE1L | ||
23 | * | IN1R -> LINE1R | ||
24 | * | IN2L -> LINE2L | ||
25 | * | IN2R -> LINE2R | ||
26 | * | MIC3L/R -> N/A | ||
27 | * truncated internal functionality in | ||
28 | * accordance with documentation | ||
29 | * --------------------------------------- | ||
30 | * | ||
31 | * Hence the machine layer should disable unsupported inputs/outputs by | ||
32 | * snd_soc_dapm_set_endpoint(codec, "MONO_LOUT", 0), etc. | ||
33 | */ | ||
34 | |||
35 | #include <linux/module.h> | ||
36 | #include <linux/moduleparam.h> | ||
37 | #include <linux/init.h> | ||
38 | #include <linux/delay.h> | ||
39 | #include <linux/pm.h> | ||
40 | #include <linux/i2c.h> | ||
41 | #include <linux/platform_device.h> | ||
42 | #include <sound/driver.h> | ||
43 | #include <sound/core.h> | ||
44 | #include <sound/pcm.h> | ||
45 | #include <sound/pcm_params.h> | ||
46 | #include <sound/soc.h> | ||
47 | #include <sound/soc-dapm.h> | ||
48 | #include <sound/initval.h> | ||
49 | |||
50 | #include "tlv320aic3x.h" | ||
51 | |||
52 | #define AUDIO_NAME "aic3x" | ||
53 | #define AIC3X_VERSION "0.1" | ||
54 | |||
55 | /* codec private data */ | ||
56 | struct aic3x_priv { | ||
57 | unsigned int sysclk; | ||
58 | int master; | ||
59 | }; | ||
60 | |||
61 | /* | ||
62 | * AIC3X register cache | ||
63 | * We can't read the AIC3X register space when we are | ||
64 | * using 2 wire for device control, so we cache them instead. | ||
65 | * There is no point in caching the reset register | ||
66 | */ | ||
67 | static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = { | ||
68 | 0x00, 0x00, 0x00, 0x10, /* 0 */ | ||
69 | 0x04, 0x00, 0x00, 0x00, /* 4 */ | ||
70 | 0x00, 0x00, 0x00, 0x01, /* 8 */ | ||
71 | 0x00, 0x00, 0x00, 0x80, /* 12 */ | ||
72 | 0x80, 0xff, 0xff, 0x78, /* 16 */ | ||
73 | 0x78, 0x78, 0x78, 0x78, /* 20 */ | ||
74 | 0x78, 0x00, 0x00, 0xfe, /* 24 */ | ||
75 | 0x00, 0x00, 0xfe, 0x00, /* 28 */ | ||
76 | 0x18, 0x18, 0x00, 0x00, /* 32 */ | ||
77 | 0x00, 0x00, 0x00, 0x00, /* 36 */ | ||
78 | 0x00, 0x00, 0x00, 0x80, /* 40 */ | ||
79 | 0x80, 0x00, 0x00, 0x00, /* 44 */ | ||
80 | 0x00, 0x00, 0x00, 0x04, /* 48 */ | ||
81 | 0x00, 0x00, 0x00, 0x00, /* 52 */ | ||
82 | 0x00, 0x00, 0x04, 0x00, /* 56 */ | ||
83 | 0x00, 0x00, 0x00, 0x00, /* 60 */ | ||
84 | 0x00, 0x04, 0x00, 0x00, /* 64 */ | ||
85 | 0x00, 0x00, 0x00, 0x00, /* 68 */ | ||
86 | 0x04, 0x00, 0x00, 0x00, /* 72 */ | ||
87 | 0x00, 0x00, 0x00, 0x00, /* 76 */ | ||
88 | 0x00, 0x00, 0x00, 0x00, /* 80 */ | ||
89 | 0x00, 0x00, 0x00, 0x00, /* 84 */ | ||
90 | 0x00, 0x00, 0x00, 0x00, /* 88 */ | ||
91 | 0x00, 0x00, 0x00, 0x00, /* 92 */ | ||
92 | 0x00, 0x00, 0x00, 0x00, /* 96 */ | ||
93 | 0x00, 0x00, 0x02, /* 100 */ | ||
94 | }; | ||
95 | |||
96 | /* | ||
97 | * read aic3x register cache | ||
98 | */ | ||
99 | static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec, | ||
100 | unsigned int reg) | ||
101 | { | ||
102 | u8 *cache = codec->reg_cache; | ||
103 | if (reg >= AIC3X_CACHEREGNUM) | ||
104 | return -1; | ||
105 | return cache[reg]; | ||
106 | } | ||
107 | |||
108 | /* | ||
109 | * write aic3x register cache | ||
110 | */ | ||
111 | static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec, | ||
112 | u8 reg, u8 value) | ||
113 | { | ||
114 | u8 *cache = codec->reg_cache; | ||
115 | if (reg >= AIC3X_CACHEREGNUM) | ||
116 | return; | ||
117 | cache[reg] = value; | ||
118 | } | ||
119 | |||
120 | /* | ||
121 | * write to the aic3x register space | ||
122 | */ | ||
123 | static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg, | ||
124 | unsigned int value) | ||
125 | { | ||
126 | u8 data[2]; | ||
127 | |||
128 | /* data is | ||
129 | * D15..D8 aic3x register offset | ||
130 | * D7...D0 register data | ||
131 | */ | ||
132 | data[0] = reg & 0xff; | ||
133 | data[1] = value & 0xff; | ||
134 | |||
135 | aic3x_write_reg_cache(codec, data[0], data[1]); | ||
136 | if (codec->hw_write(codec->control_data, data, 2) == 2) | ||
137 | return 0; | ||
138 | else | ||
139 | return -EIO; | ||
140 | } | ||
141 | |||
142 | #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \ | ||
143 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | ||
144 | .info = snd_soc_info_volsw, \ | ||
145 | .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \ | ||
146 | .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) } | ||
147 | |||
148 | /* | ||
149 | * All input lines are connected when !0xf and disconnected with 0xf bit field, | ||
150 | * so we have to use specific dapm_put call for input mixer | ||
151 | */ | ||
152 | static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol, | ||
153 | struct snd_ctl_elem_value *ucontrol) | ||
154 | { | ||
155 | struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); | ||
156 | int reg = kcontrol->private_value & 0xff; | ||
157 | int shift = (kcontrol->private_value >> 8) & 0x0f; | ||
158 | int mask = (kcontrol->private_value >> 16) & 0xff; | ||
159 | int invert = (kcontrol->private_value >> 24) & 0x01; | ||
160 | unsigned short val, val_mask; | ||
161 | int ret; | ||
162 | struct snd_soc_dapm_path *path; | ||
163 | int found = 0; | ||
164 | |||
165 | val = (ucontrol->value.integer.value[0] & mask); | ||
166 | |||
167 | mask = 0xf; | ||
168 | if (val) | ||
169 | val = mask; | ||
170 | |||
171 | if (invert) | ||
172 | val = mask - val; | ||
173 | val_mask = mask << shift; | ||
174 | val = val << shift; | ||
175 | |||
176 | mutex_lock(&widget->codec->mutex); | ||
177 | |||
178 | if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) { | ||
179 | /* find dapm widget path assoc with kcontrol */ | ||
180 | list_for_each_entry(path, &widget->codec->dapm_paths, list) { | ||
181 | if (path->kcontrol != kcontrol) | ||
182 | continue; | ||
183 | |||
184 | /* found, now check type */ | ||
185 | found = 1; | ||
186 | if (val) | ||
187 | /* new connection */ | ||
188 | path->connect = invert ? 0 : 1; | ||
189 | else | ||
190 | /* old connection must be powered down */ | ||
191 | path->connect = invert ? 1 : 0; | ||
192 | break; | ||
193 | } | ||
194 | |||
195 | if (found) | ||
196 | snd_soc_dapm_sync_endpoints(widget->codec); | ||
197 | } | ||
198 | |||
199 | ret = snd_soc_update_bits(widget->codec, reg, val_mask, val); | ||
200 | |||
201 | mutex_unlock(&widget->codec->mutex); | ||
202 | return ret; | ||
203 | } | ||
204 | |||
205 | static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" }; | ||
206 | static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" }; | ||
207 | static const char *aic3x_left_hpcom_mux[] = | ||
208 | { "differential of HPLOUT", "constant VCM", "single-ended" }; | ||
209 | static const char *aic3x_right_hpcom_mux[] = | ||
210 | { "differential of HPROUT", "constant VCM", "single-ended", | ||
211 | "differential of HPLCOM", "external feedback" }; | ||
212 | static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" }; | ||
213 | |||
214 | #define LDAC_ENUM 0 | ||
215 | #define RDAC_ENUM 1 | ||
216 | #define LHPCOM_ENUM 2 | ||
217 | #define RHPCOM_ENUM 3 | ||
218 | #define LINE1L_ENUM 4 | ||
219 | #define LINE1R_ENUM 5 | ||
220 | #define LINE2L_ENUM 6 | ||
221 | #define LINE2R_ENUM 7 | ||
222 | |||
223 | static const struct soc_enum aic3x_enum[] = { | ||
224 | SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux), | ||
225 | SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux), | ||
226 | SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux), | ||
227 | SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux), | ||
228 | SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), | ||
229 | SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), | ||
230 | SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), | ||
231 | SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), | ||
232 | }; | ||
233 | |||
234 | static const struct snd_kcontrol_new aic3x_snd_controls[] = { | ||
235 | /* Output */ | ||
236 | SOC_DOUBLE_R("PCM Playback Volume", LDAC_VOL, RDAC_VOL, 0, 0x7f, 1), | ||
237 | |||
238 | SOC_DOUBLE_R("Line DAC Playback Volume", DACL1_2_LLOPM_VOL, | ||
239 | DACR1_2_RLOPM_VOL, 0, 0x7f, 1), | ||
240 | SOC_DOUBLE_R("Line DAC Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3, | ||
241 | 0x01, 0), | ||
242 | SOC_DOUBLE_R("Line PGA Bypass Playback Volume", PGAL_2_LLOPM_VOL, | ||
243 | PGAR_2_RLOPM_VOL, 0, 0x7f, 1), | ||
244 | SOC_DOUBLE_R("Line Line2 Bypass Playback Volume", LINE2L_2_LLOPM_VOL, | ||
245 | LINE2R_2_RLOPM_VOL, 0, 0x7f, 1), | ||
246 | |||
247 | SOC_DOUBLE_R("Mono DAC Playback Volume", DACL1_2_MONOLOPM_VOL, | ||
248 | DACR1_2_MONOLOPM_VOL, 0, 0x7f, 1), | ||
249 | SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0), | ||
250 | SOC_DOUBLE_R("Mono PGA Bypass Playback Volume", PGAL_2_MONOLOPM_VOL, | ||
251 | PGAR_2_MONOLOPM_VOL, 0, 0x7f, 1), | ||
252 | SOC_DOUBLE_R("Mono Line2 Bypass Playback Volume", LINE2L_2_MONOLOPM_VOL, | ||
253 | LINE2R_2_MONOLOPM_VOL, 0, 0x7f, 1), | ||
254 | |||
255 | SOC_DOUBLE_R("HP DAC Playback Volume", DACL1_2_HPLOUT_VOL, | ||
256 | DACR1_2_HPROUT_VOL, 0, 0x7f, 1), | ||
257 | SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3, | ||
258 | 0x01, 0), | ||
259 | SOC_DOUBLE_R("HP PGA Bypass Playback Volume", PGAL_2_HPLOUT_VOL, | ||
260 | PGAR_2_HPROUT_VOL, 0, 0x7f, 1), | ||
261 | SOC_DOUBLE_R("HP Line2 Bypass Playback Volume", LINE2L_2_HPLOUT_VOL, | ||
262 | LINE2R_2_HPROUT_VOL, 0, 0x7f, 1), | ||
263 | |||
264 | SOC_DOUBLE_R("HPCOM DAC Playback Volume", DACL1_2_HPLCOM_VOL, | ||
265 | DACR1_2_HPRCOM_VOL, 0, 0x7f, 1), | ||
266 | SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3, | ||
267 | 0x01, 0), | ||
268 | SOC_DOUBLE_R("HPCOM PGA Bypass Playback Volume", PGAL_2_HPLCOM_VOL, | ||
269 | PGAR_2_HPRCOM_VOL, 0, 0x7f, 1), | ||
270 | SOC_DOUBLE_R("HPCOM Line2 Bypass Playback Volume", LINE2L_2_HPLCOM_VOL, | ||
271 | LINE2R_2_HPRCOM_VOL, 0, 0x7f, 1), | ||
272 | |||
273 | /* | ||
274 | * Note: enable Automatic input Gain Controller with care. It can | ||
275 | * adjust PGA to max value when ADC is on and will never go back. | ||
276 | */ | ||
277 | SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0), | ||
278 | |||
279 | /* Input */ | ||
280 | SOC_DOUBLE_R("PGA Capture Volume", LADC_VOL, RADC_VOL, 0, 0x7f, 0), | ||
281 | SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1), | ||
282 | }; | ||
283 | |||
284 | /* add non dapm controls */ | ||
285 | static int aic3x_add_controls(struct snd_soc_codec *codec) | ||
286 | { | ||
287 | int err, i; | ||
288 | |||
289 | for (i = 0; i < ARRAY_SIZE(aic3x_snd_controls); i++) { | ||
290 | err = snd_ctl_add(codec->card, | ||
291 | snd_soc_cnew(&aic3x_snd_controls[i], | ||
292 | codec, NULL)); | ||
293 | if (err < 0) | ||
294 | return err; | ||
295 | } | ||
296 | |||
297 | return 0; | ||
298 | } | ||
299 | |||
300 | /* Left DAC Mux */ | ||
301 | static const struct snd_kcontrol_new aic3x_left_dac_mux_controls = | ||
302 | SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]); | ||
303 | |||
304 | /* Right DAC Mux */ | ||
305 | static const struct snd_kcontrol_new aic3x_right_dac_mux_controls = | ||
306 | SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]); | ||
307 | |||
308 | /* Left HPCOM Mux */ | ||
309 | static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls = | ||
310 | SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]); | ||
311 | |||
312 | /* Right HPCOM Mux */ | ||
313 | static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls = | ||
314 | SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]); | ||
315 | |||
316 | /* Left DAC_L1 Mixer */ | ||
317 | static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = { | ||
318 | SOC_DAPM_SINGLE("Line Switch", DACL1_2_LLOPM_VOL, 7, 1, 0), | ||
319 | SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0), | ||
320 | SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0), | ||
321 | SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0), | ||
322 | }; | ||
323 | |||
324 | /* Right DAC_R1 Mixer */ | ||
325 | static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = { | ||
326 | SOC_DAPM_SINGLE("Line Switch", DACR1_2_RLOPM_VOL, 7, 1, 0), | ||
327 | SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0), | ||
328 | SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0), | ||
329 | SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0), | ||
330 | }; | ||
331 | |||
332 | /* Left PGA Mixer */ | ||
333 | static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = { | ||
334 | SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), | ||
335 | SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1), | ||
336 | SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), | ||
337 | }; | ||
338 | |||
339 | /* Right PGA Mixer */ | ||
340 | static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = { | ||
341 | SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), | ||
342 | SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1), | ||
343 | SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), | ||
344 | }; | ||
345 | |||
346 | /* Left Line1 Mux */ | ||
347 | static const struct snd_kcontrol_new aic3x_left_line1_mux_controls = | ||
348 | SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]); | ||
349 | |||
350 | /* Right Line1 Mux */ | ||
351 | static const struct snd_kcontrol_new aic3x_right_line1_mux_controls = | ||
352 | SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]); | ||
353 | |||
354 | /* Left Line2 Mux */ | ||
355 | static const struct snd_kcontrol_new aic3x_left_line2_mux_controls = | ||
356 | SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]); | ||
357 | |||
358 | /* Right Line2 Mux */ | ||
359 | static const struct snd_kcontrol_new aic3x_right_line2_mux_controls = | ||
360 | SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]); | ||
361 | |||
362 | /* Left PGA Bypass Mixer */ | ||
363 | static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = { | ||
364 | SOC_DAPM_SINGLE("Line Switch", PGAL_2_LLOPM_VOL, 7, 1, 0), | ||
365 | SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0), | ||
366 | SOC_DAPM_SINGLE("HP Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0), | ||
367 | SOC_DAPM_SINGLE("HPCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0), | ||
368 | }; | ||
369 | |||
370 | /* Right PGA Bypass Mixer */ | ||
371 | static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = { | ||
372 | SOC_DAPM_SINGLE("Line Switch", PGAR_2_RLOPM_VOL, 7, 1, 0), | ||
373 | SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0), | ||
374 | SOC_DAPM_SINGLE("HP Switch", PGAR_2_HPROUT_VOL, 7, 1, 0), | ||
375 | SOC_DAPM_SINGLE("HPCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0), | ||
376 | }; | ||
377 | |||
378 | /* Left Line2 Bypass Mixer */ | ||
379 | static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = { | ||
380 | SOC_DAPM_SINGLE("Line Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0), | ||
381 | SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0), | ||
382 | SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0), | ||
383 | SOC_DAPM_SINGLE("HPCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0), | ||
384 | }; | ||
385 | |||
386 | /* Right Line2 Bypass Mixer */ | ||
387 | static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = { | ||
388 | SOC_DAPM_SINGLE("Line Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0), | ||
389 | SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0), | ||
390 | SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0), | ||
391 | SOC_DAPM_SINGLE("HPCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0), | ||
392 | }; | ||
393 | |||
394 | static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { | ||
395 | /* Left DAC to Left Outputs */ | ||
396 | SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0), | ||
397 | SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0, | ||
398 | &aic3x_left_dac_mux_controls), | ||
399 | SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0, | ||
400 | &aic3x_left_dac_mixer_controls[0], | ||
401 | ARRAY_SIZE(aic3x_left_dac_mixer_controls)), | ||
402 | SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0, | ||
403 | &aic3x_left_hpcom_mux_controls), | ||
404 | SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0), | ||
405 | SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0), | ||
406 | SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0), | ||
407 | |||
408 | /* Right DAC to Right Outputs */ | ||
409 | SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0), | ||
410 | SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0, | ||
411 | &aic3x_right_dac_mux_controls), | ||
412 | SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0, | ||
413 | &aic3x_right_dac_mixer_controls[0], | ||
414 | ARRAY_SIZE(aic3x_right_dac_mixer_controls)), | ||
415 | SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0, | ||
416 | &aic3x_right_hpcom_mux_controls), | ||
417 | SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0), | ||
418 | SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0), | ||
419 | SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0), | ||
420 | |||
421 | /* Mono Output */ | ||
422 | SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0), | ||
423 | |||
424 | /* Left Inputs to Left ADC */ | ||
425 | SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0), | ||
426 | SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, | ||
427 | &aic3x_left_pga_mixer_controls[0], | ||
428 | ARRAY_SIZE(aic3x_left_pga_mixer_controls)), | ||
429 | SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0, | ||
430 | &aic3x_left_line1_mux_controls), | ||
431 | SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0, | ||
432 | &aic3x_left_line2_mux_controls), | ||
433 | |||
434 | /* Right Inputs to Right ADC */ | ||
435 | SND_SOC_DAPM_ADC("Right ADC", "Right Capture", | ||
436 | LINE1R_2_RADC_CTRL, 2, 0), | ||
437 | SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, | ||
438 | &aic3x_right_pga_mixer_controls[0], | ||
439 | ARRAY_SIZE(aic3x_right_pga_mixer_controls)), | ||
440 | SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0, | ||
441 | &aic3x_right_line1_mux_controls), | ||
442 | SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0, | ||
443 | &aic3x_right_line2_mux_controls), | ||
444 | |||
445 | /* Mic Bias */ | ||
446 | SND_SOC_DAPM_MICBIAS("Mic Bias 2V", MICBIAS_CTRL, 6, 0), | ||
447 | SND_SOC_DAPM_MICBIAS("Mic Bias 2.5V", MICBIAS_CTRL, 7, 0), | ||
448 | SND_SOC_DAPM_MICBIAS("Mic Bias AVDD", MICBIAS_CTRL, 6, 0), | ||
449 | SND_SOC_DAPM_MICBIAS("Mic Bias AVDD", MICBIAS_CTRL, 7, 0), | ||
450 | |||
451 | /* Left PGA to Left Output bypass */ | ||
452 | SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0, | ||
453 | &aic3x_left_pga_bp_mixer_controls[0], | ||
454 | ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)), | ||
455 | |||
456 | /* Right PGA to Right Output bypass */ | ||
457 | SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0, | ||
458 | &aic3x_right_pga_bp_mixer_controls[0], | ||
459 | ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)), | ||
460 | |||
461 | /* Left Line2 to Left Output bypass */ | ||
462 | SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0, | ||
463 | &aic3x_left_line2_bp_mixer_controls[0], | ||
464 | ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)), | ||
465 | |||
466 | /* Right Line2 to Right Output bypass */ | ||
467 | SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0, | ||
468 | &aic3x_right_line2_bp_mixer_controls[0], | ||
469 | ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)), | ||
470 | |||
471 | SND_SOC_DAPM_OUTPUT("LLOUT"), | ||
472 | SND_SOC_DAPM_OUTPUT("RLOUT"), | ||
473 | SND_SOC_DAPM_OUTPUT("MONO_LOUT"), | ||
474 | SND_SOC_DAPM_OUTPUT("HPLOUT"), | ||
475 | SND_SOC_DAPM_OUTPUT("HPROUT"), | ||
476 | SND_SOC_DAPM_OUTPUT("HPLCOM"), | ||
477 | SND_SOC_DAPM_OUTPUT("HPRCOM"), | ||
478 | |||
479 | SND_SOC_DAPM_INPUT("MIC3L"), | ||
480 | SND_SOC_DAPM_INPUT("MIC3R"), | ||
481 | SND_SOC_DAPM_INPUT("LINE1L"), | ||
482 | SND_SOC_DAPM_INPUT("LINE1R"), | ||
483 | SND_SOC_DAPM_INPUT("LINE2L"), | ||
484 | SND_SOC_DAPM_INPUT("LINE2R"), | ||
485 | }; | ||
486 | |||
487 | static const char *intercon[][3] = { | ||
488 | /* Left Output */ | ||
489 | {"Left DAC Mux", "DAC_L1", "Left DAC"}, | ||
490 | {"Left DAC Mux", "DAC_L2", "Left DAC"}, | ||
491 | {"Left DAC Mux", "DAC_L3", "Left DAC"}, | ||
492 | |||
493 | {"Left DAC_L1 Mixer", "Line Switch", "Left DAC Mux"}, | ||
494 | {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"}, | ||
495 | {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"}, | ||
496 | {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"}, | ||
497 | {"Left Line Out", NULL, "Left DAC Mux"}, | ||
498 | {"Left HP Out", NULL, "Left DAC Mux"}, | ||
499 | |||
500 | {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"}, | ||
501 | {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"}, | ||
502 | {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"}, | ||
503 | |||
504 | {"Left Line Out", NULL, "Left DAC_L1 Mixer"}, | ||
505 | {"Mono Out", NULL, "Left DAC_L1 Mixer"}, | ||
506 | {"Left HP Out", NULL, "Left DAC_L1 Mixer"}, | ||
507 | {"Left HP Com", NULL, "Left HPCOM Mux"}, | ||
508 | |||
509 | {"LLOUT", NULL, "Left Line Out"}, | ||
510 | {"LLOUT", NULL, "Left Line Out"}, | ||
511 | {"HPLOUT", NULL, "Left HP Out"}, | ||
512 | {"HPLCOM", NULL, "Left HP Com"}, | ||
513 | |||
514 | /* Right Output */ | ||
515 | {"Right DAC Mux", "DAC_R1", "Right DAC"}, | ||
516 | {"Right DAC Mux", "DAC_R2", "Right DAC"}, | ||
517 | {"Right DAC Mux", "DAC_R3", "Right DAC"}, | ||
518 | |||
519 | {"Right DAC_R1 Mixer", "Line Switch", "Right DAC Mux"}, | ||
520 | {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"}, | ||
521 | {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"}, | ||
522 | {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"}, | ||
523 | {"Right Line Out", NULL, "Right DAC Mux"}, | ||
524 | {"Right HP Out", NULL, "Right DAC Mux"}, | ||
525 | |||
526 | {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"}, | ||
527 | {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"}, | ||
528 | {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"}, | ||
529 | {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"}, | ||
530 | {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"}, | ||
531 | |||
532 | {"Right Line Out", NULL, "Right DAC_R1 Mixer"}, | ||
533 | {"Mono Out", NULL, "Right DAC_R1 Mixer"}, | ||
534 | {"Right HP Out", NULL, "Right DAC_R1 Mixer"}, | ||
535 | {"Right HP Com", NULL, "Right HPCOM Mux"}, | ||
536 | |||
537 | {"RLOUT", NULL, "Right Line Out"}, | ||
538 | {"RLOUT", NULL, "Right Line Out"}, | ||
539 | {"HPROUT", NULL, "Right HP Out"}, | ||
540 | {"HPRCOM", NULL, "Right HP Com"}, | ||
541 | |||
542 | /* Mono Output */ | ||
543 | {"MONOLOUT", NULL, "Mono Out"}, | ||
544 | {"MONOLOUT", NULL, "Mono Out"}, | ||
545 | |||
546 | /* Left Input */ | ||
547 | {"Left Line1L Mux", "single-ended", "LINE1L"}, | ||
548 | {"Left Line1L Mux", "differential", "LINE1L"}, | ||
549 | |||
550 | {"Left Line2L Mux", "single-ended", "LINE2L"}, | ||
551 | {"Left Line2L Mux", "differential", "LINE2L"}, | ||
552 | |||
553 | {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"}, | ||
554 | {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"}, | ||
555 | {"Left PGA Mixer", "Mic3L Switch", "MIC3L"}, | ||
556 | |||
557 | {"Left ADC", NULL, "Left PGA Mixer"}, | ||
558 | |||
559 | /* Right Input */ | ||
560 | {"Right Line1R Mux", "single-ended", "LINE1R"}, | ||
561 | {"Right Line1R Mux", "differential", "LINE1R"}, | ||
562 | |||
563 | {"Right Line2R Mux", "single-ended", "LINE2R"}, | ||
564 | {"Right Line2R Mux", "differential", "LINE2R"}, | ||
565 | |||
566 | {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"}, | ||
567 | {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"}, | ||
568 | {"Right PGA Mixer", "Mic3R Switch", "MIC3R"}, | ||
569 | |||
570 | {"Right ADC", NULL, "Right PGA Mixer"}, | ||
571 | |||
572 | /* Left PGA Bypass */ | ||
573 | {"Left PGA Bypass Mixer", "Line Switch", "Left PGA Mixer"}, | ||
574 | {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"}, | ||
575 | {"Left PGA Bypass Mixer", "HP Switch", "Left PGA Mixer"}, | ||
576 | {"Left PGA Bypass Mixer", "HPCOM Switch", "Left PGA Mixer"}, | ||
577 | |||
578 | {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"}, | ||
579 | {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"}, | ||
580 | {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"}, | ||
581 | |||
582 | {"Left Line Out", NULL, "Left PGA Bypass Mixer"}, | ||
583 | {"Mono Out", NULL, "Left PGA Bypass Mixer"}, | ||
584 | {"Left HP Out", NULL, "Left PGA Bypass Mixer"}, | ||
585 | |||
586 | /* Right PGA Bypass */ | ||
587 | {"Right PGA Bypass Mixer", "Line Switch", "Right PGA Mixer"}, | ||
588 | {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"}, | ||
589 | {"Right PGA Bypass Mixer", "HP Switch", "Right PGA Mixer"}, | ||
590 | {"Right PGA Bypass Mixer", "HPCOM Switch", "Right PGA Mixer"}, | ||
591 | |||
592 | {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"}, | ||
593 | {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"}, | ||
594 | {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"}, | ||
595 | {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"}, | ||
596 | {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"}, | ||
597 | |||
598 | {"Right Line Out", NULL, "Right PGA Bypass Mixer"}, | ||
599 | {"Mono Out", NULL, "Right PGA Bypass Mixer"}, | ||
600 | {"Right HP Out", NULL, "Right PGA Bypass Mixer"}, | ||
601 | |||
602 | /* Left Line2 Bypass */ | ||
603 | {"Left Line2 Bypass Mixer", "Line Switch", "Left Line2L Mux"}, | ||
604 | {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"}, | ||
605 | {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"}, | ||
606 | {"Left Line2 Bypass Mixer", "HPCOM Switch", "Left Line2L Mux"}, | ||
607 | |||
608 | {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"}, | ||
609 | {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"}, | ||
610 | {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"}, | ||
611 | |||
612 | {"Left Line Out", NULL, "Left Line2 Bypass Mixer"}, | ||
613 | {"Mono Out", NULL, "Left Line2 Bypass Mixer"}, | ||
614 | {"Left HP Out", NULL, "Left Line2 Bypass Mixer"}, | ||
615 | |||
616 | /* Right Line2 Bypass */ | ||
617 | {"Right Line2 Bypass Mixer", "Line Switch", "Right Line2R Mux"}, | ||
618 | {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"}, | ||
619 | {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"}, | ||
620 | {"Right Line2 Bypass Mixer", "HPCOM Switch", "Right Line2R Mux"}, | ||
621 | |||
622 | {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"}, | ||
623 | {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"}, | ||
624 | {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"}, | ||
625 | {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"}, | ||
626 | {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"}, | ||
627 | |||
628 | {"Right Line Out", NULL, "Right Line2 Bypass Mixer"}, | ||
629 | {"Mono Out", NULL, "Right Line2 Bypass Mixer"}, | ||
630 | {"Right HP Out", NULL, "Right Line2 Bypass Mixer"}, | ||
631 | |||
632 | /* terminator */ | ||
633 | {NULL, NULL, NULL}, | ||
634 | }; | ||
635 | |||
636 | static int aic3x_add_widgets(struct snd_soc_codec *codec) | ||
637 | { | ||
638 | int i; | ||
639 | |||
640 | for (i = 0; i < ARRAY_SIZE(aic3x_dapm_widgets); i++) | ||
641 | snd_soc_dapm_new_control(codec, &aic3x_dapm_widgets[i]); | ||
642 | |||
643 | /* set up audio path interconnects */ | ||
644 | for (i = 0; intercon[i][0] != NULL; i++) | ||
645 | snd_soc_dapm_connect_input(codec, intercon[i][0], | ||
646 | intercon[i][1], intercon[i][2]); | ||
647 | |||
648 | snd_soc_dapm_new_widgets(codec); | ||
649 | return 0; | ||
650 | } | ||
651 | |||
652 | struct aic3x_rate_divs { | ||
653 | u32 mclk; | ||
654 | u32 rate; | ||
655 | u32 fsref_reg; | ||
656 | u8 sr_reg:4; | ||
657 | u8 pllj_reg; | ||
658 | u16 plld_reg; | ||
659 | }; | ||
660 | |||
661 | /* AIC3X codec mclk clock divider coefficients */ | ||
662 | static const struct aic3x_rate_divs aic3x_divs[] = { | ||
663 | /* 8k */ | ||
664 | {22579200, 8000, 48000, 0xa, 8, 7075}, | ||
665 | {33868800, 8000, 48000, 0xa, 5, 8049}, | ||
666 | /* 11.025k */ | ||
667 | {22579200, 11025, 44100, 0x6, 8, 0}, | ||
668 | {33868800, 11025, 44100, 0x6, 5, 3333}, | ||
669 | /* 16k */ | ||
670 | {22579200, 16000, 48000, 0x4, 8, 7075}, | ||
671 | {33868800, 16000, 48000, 0x4, 5, 8049}, | ||
672 | /* 22.05k */ | ||
673 | {22579200, 22050, 44100, 0x2, 8, 0}, | ||
674 | {33868800, 22050, 44100, 0x2, 5, 3333}, | ||
675 | /* 32k */ | ||
676 | {22579200, 32000, 48000, 0x1, 8, 7075}, | ||
677 | {33868800, 32000, 48000, 0x1, 5, 8049}, | ||
678 | /* 44.1k */ | ||
679 | {22579200, 44100, 44100, 0x0, 8, 0}, | ||
680 | {33868800, 44100, 44100, 0x0, 5, 3333}, | ||
681 | /* 48k */ | ||
682 | {22579200, 48000, 48000, 0x0, 8, 7075}, | ||
683 | {33868800, 48000, 48000, 0x0, 5, 8049}, | ||
684 | /* 64k */ | ||
685 | {22579200, 96000, 96000, 0x1, 8, 7075}, | ||
686 | {33868800, 96000, 96000, 0x1, 5, 8049}, | ||
687 | /* 88.2k */ | ||
688 | {22579200, 88200, 88200, 0x0, 8, 0}, | ||
689 | {33868800, 88200, 88200, 0x0, 5, 3333}, | ||
690 | /* 96k */ | ||
691 | {22579200, 96000, 96000, 0x0, 8, 7075}, | ||
692 | {33868800, 96000, 96000, 0x0, 5, 8049}, | ||
693 | }; | ||
694 | |||
695 | static inline int aic3x_get_divs(int mclk, int rate) | ||
696 | { | ||
697 | int i; | ||
698 | |||
699 | for (i = 0; i < ARRAY_SIZE(aic3x_divs); i++) { | ||
700 | if (aic3x_divs[i].rate == rate && aic3x_divs[i].mclk == mclk) | ||
701 | return i; | ||
702 | } | ||
703 | |||
704 | return 0; | ||
705 | } | ||
706 | |||
707 | static int aic3x_hw_params(struct snd_pcm_substream *substream, | ||
708 | struct snd_pcm_hw_params *params) | ||
709 | { | ||
710 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | ||
711 | struct snd_soc_device *socdev = rtd->socdev; | ||
712 | struct snd_soc_codec *codec = socdev->codec; | ||
713 | struct aic3x_priv *aic3x = codec->private_data; | ||
714 | int i; | ||
715 | u8 data, pll_p, pll_r, pll_j; | ||
716 | u16 pll_d; | ||
717 | |||
718 | i = aic3x_get_divs(aic3x->sysclk, params_rate(params)); | ||
719 | |||
720 | /* Route Left DAC to left channel input and | ||
721 | * right DAC to right channel input */ | ||
722 | data = (LDAC2LCH | RDAC2RCH); | ||
723 | switch (aic3x_divs[i].fsref_reg) { | ||
724 | case 44100: | ||
725 | data |= FSREF_44100; | ||
726 | break; | ||
727 | case 48000: | ||
728 | data |= FSREF_48000; | ||
729 | break; | ||
730 | case 88200: | ||
731 | data |= FSREF_44100 | DUAL_RATE_MODE; | ||
732 | break; | ||
733 | case 96000: | ||
734 | data |= FSREF_48000 | DUAL_RATE_MODE; | ||
735 | break; | ||
736 | } | ||
737 | aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data); | ||
738 | |||
739 | /* codec sample rate select */ | ||
740 | data = aic3x_divs[i].sr_reg; | ||
741 | data |= (data << 4); | ||
742 | aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data); | ||
743 | |||
744 | /* Use PLL for generation Fsref by equation: | ||
745 | * Fsref = (MCLK * K * R)/(2048 * P); | ||
746 | * Fix P = 2 and R = 1 and calculate K, if | ||
747 | * K = J.D, i.e. J - an interger portion of K and D is the fractional | ||
748 | * one with 4 digits of precision; | ||
749 | * Example: | ||
750 | * For MCLK = 22.5792 MHz and Fsref = 48kHz: | ||
751 | * Select P = 2, R= 1, K = 8.7074, which results in J = 8, D = 7074 | ||
752 | */ | ||
753 | pll_p = 2; | ||
754 | pll_r = 1; | ||
755 | pll_j = aic3x_divs[i].pllj_reg; | ||
756 | pll_d = aic3x_divs[i].plld_reg; | ||
757 | |||
758 | data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); | ||
759 | aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT)); | ||
760 | aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT); | ||
761 | aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT); | ||
762 | aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT); | ||
763 | aic3x_write(codec, AIC3X_PLL_PROGD_REG, | ||
764 | (pll_d & 0x3F) << PLLD_LSB_SHIFT); | ||
765 | |||
766 | /* select data word length */ | ||
767 | data = | ||
768 | aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4)); | ||
769 | switch (params_format(params)) { | ||
770 | case SNDRV_PCM_FORMAT_S16_LE: | ||
771 | break; | ||
772 | case SNDRV_PCM_FORMAT_S20_3LE: | ||
773 | data |= (0x01 << 4); | ||
774 | break; | ||
775 | case SNDRV_PCM_FORMAT_S24_LE: | ||
776 | data |= (0x02 << 4); | ||
777 | break; | ||
778 | case SNDRV_PCM_FORMAT_S32_LE: | ||
779 | data |= (0x03 << 4); | ||
780 | break; | ||
781 | } | ||
782 | aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data); | ||
783 | |||
784 | return 0; | ||
785 | } | ||
786 | |||
787 | static int aic3x_mute(struct snd_soc_codec_dai *dai, int mute) | ||
788 | { | ||
789 | struct snd_soc_codec *codec = dai->codec; | ||
790 | u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON; | ||
791 | u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON; | ||
792 | |||
793 | if (mute) { | ||
794 | aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON); | ||
795 | aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON); | ||
796 | } else { | ||
797 | aic3x_write(codec, LDAC_VOL, ldac_reg); | ||
798 | aic3x_write(codec, RDAC_VOL, rdac_reg); | ||
799 | } | ||
800 | |||
801 | return 0; | ||
802 | } | ||
803 | |||
804 | static int aic3x_set_dai_sysclk(struct snd_soc_codec_dai *codec_dai, | ||
805 | int clk_id, unsigned int freq, int dir) | ||
806 | { | ||
807 | struct snd_soc_codec *codec = codec_dai->codec; | ||
808 | struct aic3x_priv *aic3x = codec->private_data; | ||
809 | |||
810 | switch (freq) { | ||
811 | case 22579200: | ||
812 | case 33868800: | ||
813 | aic3x->sysclk = freq; | ||
814 | return 0; | ||
815 | } | ||
816 | |||
817 | return -EINVAL; | ||
818 | } | ||
819 | |||
820 | static int aic3x_set_dai_fmt(struct snd_soc_codec_dai *codec_dai, | ||
821 | unsigned int fmt) | ||
822 | { | ||
823 | struct snd_soc_codec *codec = codec_dai->codec; | ||
824 | struct aic3x_priv *aic3x = codec->private_data; | ||
825 | u8 iface_areg = 0; | ||
826 | u8 iface_breg = 0; | ||
827 | |||
828 | /* set master/slave audio interface */ | ||
829 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | ||
830 | case SND_SOC_DAIFMT_CBM_CFM: | ||
831 | aic3x->master = 1; | ||
832 | iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER; | ||
833 | break; | ||
834 | case SND_SOC_DAIFMT_CBS_CFS: | ||
835 | aic3x->master = 0; | ||
836 | break; | ||
837 | default: | ||
838 | return -EINVAL; | ||
839 | } | ||
840 | |||
841 | /* interface format */ | ||
842 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | ||
843 | case SND_SOC_DAIFMT_I2S: | ||
844 | break; | ||
845 | case SND_SOC_DAIFMT_DSP_A: | ||
846 | iface_breg |= (0x01 << 6); | ||
847 | break; | ||
848 | case SND_SOC_DAIFMT_RIGHT_J: | ||
849 | iface_breg |= (0x02 << 6); | ||
850 | break; | ||
851 | case SND_SOC_DAIFMT_LEFT_J: | ||
852 | iface_breg |= (0x03 << 6); | ||
853 | break; | ||
854 | default: | ||
855 | return -EINVAL; | ||
856 | } | ||
857 | |||
858 | /* set iface */ | ||
859 | aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg); | ||
860 | aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg); | ||
861 | |||
862 | return 0; | ||
863 | } | ||
864 | |||
865 | static int aic3x_dapm_event(struct snd_soc_codec *codec, int event) | ||
866 | { | ||
867 | struct aic3x_priv *aic3x = codec->private_data; | ||
868 | u8 reg; | ||
869 | |||
870 | switch (event) { | ||
871 | case SNDRV_CTL_POWER_D0: | ||
872 | /* all power is driven by DAPM system */ | ||
873 | if (aic3x->master) { | ||
874 | /* enable pll */ | ||
875 | reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); | ||
876 | aic3x_write(codec, AIC3X_PLL_PROGA_REG, | ||
877 | reg | PLL_ENABLE); | ||
878 | } | ||
879 | break; | ||
880 | case SNDRV_CTL_POWER_D1: | ||
881 | case SNDRV_CTL_POWER_D2: | ||
882 | break; | ||
883 | case SNDRV_CTL_POWER_D3hot: | ||
884 | /* | ||
885 | * all power is driven by DAPM system, | ||
886 | * so output power is safe if bypass was set | ||
887 | */ | ||
888 | if (aic3x->master) { | ||
889 | /* disable pll */ | ||
890 | reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); | ||
891 | aic3x_write(codec, AIC3X_PLL_PROGA_REG, | ||
892 | reg & ~PLL_ENABLE); | ||
893 | } | ||
894 | break; | ||
895 | case SNDRV_CTL_POWER_D3cold: | ||
896 | /* force all power off */ | ||
897 | reg = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL); | ||
898 | aic3x_write(codec, LINE1L_2_LADC_CTRL, reg & ~LADC_PWR_ON); | ||
899 | reg = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL); | ||
900 | aic3x_write(codec, LINE1R_2_RADC_CTRL, reg & ~RADC_PWR_ON); | ||
901 | |||
902 | reg = aic3x_read_reg_cache(codec, DAC_PWR); | ||
903 | aic3x_write(codec, DAC_PWR, reg & ~(LDAC_PWR_ON | RDAC_PWR_ON)); | ||
904 | |||
905 | reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL); | ||
906 | aic3x_write(codec, HPLOUT_CTRL, reg & ~HPLOUT_PWR_ON); | ||
907 | reg = aic3x_read_reg_cache(codec, HPROUT_CTRL); | ||
908 | aic3x_write(codec, HPROUT_CTRL, reg & ~HPROUT_PWR_ON); | ||
909 | |||
910 | reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL); | ||
911 | aic3x_write(codec, HPLCOM_CTRL, reg & ~HPLCOM_PWR_ON); | ||
912 | reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL); | ||
913 | aic3x_write(codec, HPRCOM_CTRL, reg & ~HPRCOM_PWR_ON); | ||
914 | |||
915 | reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL); | ||
916 | aic3x_write(codec, MONOLOPM_CTRL, reg & ~MONOLOPM_PWR_ON); | ||
917 | |||
918 | reg = aic3x_read_reg_cache(codec, LLOPM_CTRL); | ||
919 | aic3x_write(codec, LLOPM_CTRL, reg & ~LLOPM_PWR_ON); | ||
920 | reg = aic3x_read_reg_cache(codec, RLOPM_CTRL); | ||
921 | aic3x_write(codec, RLOPM_CTRL, reg & ~RLOPM_PWR_ON); | ||
922 | |||
923 | if (aic3x->master) { | ||
924 | /* disable pll */ | ||
925 | reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); | ||
926 | aic3x_write(codec, AIC3X_PLL_PROGA_REG, | ||
927 | reg & ~PLL_ENABLE); | ||
928 | } | ||
929 | break; | ||
930 | } | ||
931 | codec->dapm_state = event; | ||
932 | |||
933 | return 0; | ||
934 | } | ||
935 | |||
936 | #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000 | ||
937 | #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | ||
938 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) | ||
939 | |||
940 | struct snd_soc_codec_dai aic3x_dai = { | ||
941 | .name = "aic3x", | ||
942 | .playback = { | ||
943 | .stream_name = "Playback", | ||
944 | .channels_min = 1, | ||
945 | .channels_max = 2, | ||
946 | .rates = AIC3X_RATES, | ||
947 | .formats = AIC3X_FORMATS,}, | ||
948 | .capture = { | ||
949 | .stream_name = "Capture", | ||
950 | .channels_min = 1, | ||
951 | .channels_max = 2, | ||
952 | .rates = AIC3X_RATES, | ||
953 | .formats = AIC3X_FORMATS,}, | ||
954 | .ops = { | ||
955 | .hw_params = aic3x_hw_params, | ||
956 | }, | ||
957 | .dai_ops = { | ||
958 | .digital_mute = aic3x_mute, | ||
959 | .set_sysclk = aic3x_set_dai_sysclk, | ||
960 | .set_fmt = aic3x_set_dai_fmt, | ||
961 | } | ||
962 | }; | ||
963 | EXPORT_SYMBOL_GPL(aic3x_dai); | ||
964 | |||
965 | static int aic3x_suspend(struct platform_device *pdev, pm_message_t state) | ||
966 | { | ||
967 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | ||
968 | struct snd_soc_codec *codec = socdev->codec; | ||
969 | |||
970 | aic3x_dapm_event(codec, SNDRV_CTL_POWER_D3cold); | ||
971 | |||
972 | return 0; | ||
973 | } | ||
974 | |||
975 | static int aic3x_resume(struct platform_device *pdev) | ||
976 | { | ||
977 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | ||
978 | struct snd_soc_codec *codec = socdev->codec; | ||
979 | int i; | ||
980 | u8 data[2]; | ||
981 | u8 *cache = codec->reg_cache; | ||
982 | |||
983 | /* Sync reg_cache with the hardware */ | ||
984 | for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) { | ||
985 | data[0] = i; | ||
986 | data[1] = cache[i]; | ||
987 | codec->hw_write(codec->control_data, data, 2); | ||
988 | } | ||
989 | |||
990 | aic3x_dapm_event(codec, codec->suspend_dapm_state); | ||
991 | |||
992 | return 0; | ||
993 | } | ||
994 | |||
995 | /* | ||
996 | * initialise the AIC3X driver | ||
997 | * register the mixer and dsp interfaces with the kernel | ||
998 | */ | ||
999 | static int aic3x_init(struct snd_soc_device *socdev) | ||
1000 | { | ||
1001 | struct snd_soc_codec *codec = socdev->codec; | ||
1002 | int reg, ret = 0; | ||
1003 | |||
1004 | codec->name = "aic3x"; | ||
1005 | codec->owner = THIS_MODULE; | ||
1006 | codec->read = aic3x_read_reg_cache; | ||
1007 | codec->write = aic3x_write; | ||
1008 | codec->dapm_event = aic3x_dapm_event; | ||
1009 | codec->dai = &aic3x_dai; | ||
1010 | codec->num_dai = 1; | ||
1011 | codec->reg_cache_size = sizeof(aic3x_reg); | ||
1012 | codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL); | ||
1013 | if (codec->reg_cache == NULL) | ||
1014 | return -ENOMEM; | ||
1015 | |||
1016 | aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT); | ||
1017 | aic3x_write(codec, AIC3X_RESET, SOFT_RESET); | ||
1018 | |||
1019 | /* register pcms */ | ||
1020 | ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); | ||
1021 | if (ret < 0) { | ||
1022 | printk(KERN_ERR "aic3x: failed to create pcms\n"); | ||
1023 | goto pcm_err; | ||
1024 | } | ||
1025 | |||
1026 | /* DAC default volume and mute */ | ||
1027 | aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON); | ||
1028 | aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON); | ||
1029 | |||
1030 | /* DAC to HP default volume and route to Output mixer */ | ||
1031 | aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON); | ||
1032 | aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON); | ||
1033 | aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON); | ||
1034 | aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON); | ||
1035 | /* DAC to Line Out default volume and route to Output mixer */ | ||
1036 | aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON); | ||
1037 | aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON); | ||
1038 | /* DAC to Mono Line Out default volume and route to Output mixer */ | ||
1039 | aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); | ||
1040 | aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); | ||
1041 | |||
1042 | /* unmute all outputs */ | ||
1043 | reg = aic3x_read_reg_cache(codec, LLOPM_CTRL); | ||
1044 | aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE); | ||
1045 | reg = aic3x_read_reg_cache(codec, RLOPM_CTRL); | ||
1046 | aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE); | ||
1047 | reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL); | ||
1048 | aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE); | ||
1049 | reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL); | ||
1050 | aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE); | ||
1051 | reg = aic3x_read_reg_cache(codec, HPROUT_CTRL); | ||
1052 | aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE); | ||
1053 | reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL); | ||
1054 | aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE); | ||
1055 | reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL); | ||
1056 | aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE); | ||
1057 | |||
1058 | /* ADC default volume and unmute */ | ||
1059 | aic3x_write(codec, LADC_VOL, DEFAULT_GAIN); | ||
1060 | aic3x_write(codec, RADC_VOL, DEFAULT_GAIN); | ||
1061 | /* By default route Line1 to ADC PGA mixer */ | ||
1062 | aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0); | ||
1063 | aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0); | ||
1064 | |||
1065 | /* PGA to HP Bypass default volume, disconnect from Output Mixer */ | ||
1066 | aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL); | ||
1067 | aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL); | ||
1068 | aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL); | ||
1069 | aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL); | ||
1070 | /* PGA to Line Out default volume, disconnect from Output Mixer */ | ||
1071 | aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL); | ||
1072 | aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL); | ||
1073 | /* PGA to Mono Line Out default volume, disconnect from Output Mixer */ | ||
1074 | aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL); | ||
1075 | aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL); | ||
1076 | |||
1077 | /* Line2 to HP Bypass default volume, disconnect from Output Mixer */ | ||
1078 | aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL); | ||
1079 | aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL); | ||
1080 | aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL); | ||
1081 | aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL); | ||
1082 | /* Line2 Line Out default volume, disconnect from Output Mixer */ | ||
1083 | aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL); | ||
1084 | aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL); | ||
1085 | /* Line2 to Mono Out default volume, disconnect from Output Mixer */ | ||
1086 | aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL); | ||
1087 | aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL); | ||
1088 | |||
1089 | /* off, with power on */ | ||
1090 | aic3x_dapm_event(codec, SNDRV_CTL_POWER_D3hot); | ||
1091 | |||
1092 | aic3x_add_controls(codec); | ||
1093 | aic3x_add_widgets(codec); | ||
1094 | ret = snd_soc_register_card(socdev); | ||
1095 | if (ret < 0) { | ||
1096 | printk(KERN_ERR "aic3x: failed to register card\n"); | ||
1097 | goto card_err; | ||
1098 | } | ||
1099 | |||
1100 | return ret; | ||
1101 | |||
1102 | card_err: | ||
1103 | snd_soc_free_pcms(socdev); | ||
1104 | snd_soc_dapm_free(socdev); | ||
1105 | pcm_err: | ||
1106 | kfree(codec->reg_cache); | ||
1107 | return ret; | ||
1108 | } | ||
1109 | |||
1110 | static struct snd_soc_device *aic3x_socdev; | ||
1111 | |||
1112 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | ||
1113 | /* | ||
1114 | * AIC3X 2 wire address can be up to 4 devices with device addresses | ||
1115 | * 0x18, 0x19, 0x1A, 0x1B | ||
1116 | */ | ||
1117 | static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END }; | ||
1118 | |||
1119 | /* Magic definition of all other variables and things */ | ||
1120 | I2C_CLIENT_INSMOD; | ||
1121 | |||
1122 | static struct i2c_driver aic3x_i2c_driver; | ||
1123 | static struct i2c_client client_template; | ||
1124 | |||
1125 | /* | ||
1126 | * If the i2c layer weren't so broken, we could pass this kind of data | ||
1127 | * around | ||
1128 | */ | ||
1129 | static int aic3x_codec_probe(struct i2c_adapter *adap, int addr, int kind) | ||
1130 | { | ||
1131 | struct snd_soc_device *socdev = aic3x_socdev; | ||
1132 | struct aic3x_setup_data *setup = socdev->codec_data; | ||
1133 | struct snd_soc_codec *codec = socdev->codec; | ||
1134 | struct i2c_client *i2c; | ||
1135 | int ret; | ||
1136 | |||
1137 | if (addr != setup->i2c_address) | ||
1138 | return -ENODEV; | ||
1139 | |||
1140 | client_template.adapter = adap; | ||
1141 | client_template.addr = addr; | ||
1142 | |||
1143 | i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL); | ||
1144 | if (i2c == NULL) { | ||
1145 | kfree(codec); | ||
1146 | return -ENOMEM; | ||
1147 | } | ||
1148 | i2c_set_clientdata(i2c, codec); | ||
1149 | codec->control_data = i2c; | ||
1150 | |||
1151 | ret = i2c_attach_client(i2c); | ||
1152 | if (ret < 0) { | ||
1153 | printk(KERN_ERR "aic3x: failed to attach codec at addr %x\n", | ||
1154 | addr); | ||
1155 | goto err; | ||
1156 | } | ||
1157 | |||
1158 | ret = aic3x_init(socdev); | ||
1159 | if (ret < 0) { | ||
1160 | printk(KERN_ERR "aic3x: failed to initialise AIC3X\n"); | ||
1161 | goto err; | ||
1162 | } | ||
1163 | return ret; | ||
1164 | |||
1165 | err: | ||
1166 | kfree(codec); | ||
1167 | kfree(i2c); | ||
1168 | return ret; | ||
1169 | } | ||
1170 | |||
1171 | static int aic3x_i2c_detach(struct i2c_client *client) | ||
1172 | { | ||
1173 | struct snd_soc_codec *codec = i2c_get_clientdata(client); | ||
1174 | i2c_detach_client(client); | ||
1175 | kfree(codec->reg_cache); | ||
1176 | kfree(client); | ||
1177 | return 0; | ||
1178 | } | ||
1179 | |||
1180 | static int aic3x_i2c_attach(struct i2c_adapter *adap) | ||
1181 | { | ||
1182 | return i2c_probe(adap, &addr_data, aic3x_codec_probe); | ||
1183 | } | ||
1184 | |||
1185 | /* machine i2c codec control layer */ | ||
1186 | static struct i2c_driver aic3x_i2c_driver = { | ||
1187 | .driver = { | ||
1188 | .name = "aic3x I2C Codec", | ||
1189 | .owner = THIS_MODULE, | ||
1190 | }, | ||
1191 | .id = I2C_DRIVERID_I2CDEV, | ||
1192 | .attach_adapter = aic3x_i2c_attach, | ||
1193 | .detach_client = aic3x_i2c_detach, | ||
1194 | .command = NULL, | ||
1195 | }; | ||
1196 | |||
1197 | static struct i2c_client client_template = { | ||
1198 | .name = "AIC3X", | ||
1199 | .driver = &aic3x_i2c_driver, | ||
1200 | }; | ||
1201 | #endif | ||
1202 | |||
1203 | static int aic3x_probe(struct platform_device *pdev) | ||
1204 | { | ||
1205 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | ||
1206 | struct aic3x_setup_data *setup; | ||
1207 | struct snd_soc_codec *codec; | ||
1208 | struct aic3x_priv *aic3x; | ||
1209 | int ret = 0; | ||
1210 | |||
1211 | printk(KERN_INFO "AIC3X Audio Codec %s\n", AIC3X_VERSION); | ||
1212 | |||
1213 | setup = socdev->codec_data; | ||
1214 | codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); | ||
1215 | if (codec == NULL) | ||
1216 | return -ENOMEM; | ||
1217 | |||
1218 | aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL); | ||
1219 | if (aic3x == NULL) { | ||
1220 | kfree(codec); | ||
1221 | return -ENOMEM; | ||
1222 | } | ||
1223 | |||
1224 | codec->private_data = aic3x; | ||
1225 | socdev->codec = codec; | ||
1226 | mutex_init(&codec->mutex); | ||
1227 | INIT_LIST_HEAD(&codec->dapm_widgets); | ||
1228 | INIT_LIST_HEAD(&codec->dapm_paths); | ||
1229 | |||
1230 | aic3x_socdev = socdev; | ||
1231 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | ||
1232 | if (setup->i2c_address) { | ||
1233 | normal_i2c[0] = setup->i2c_address; | ||
1234 | codec->hw_write = (hw_write_t) i2c_master_send; | ||
1235 | ret = i2c_add_driver(&aic3x_i2c_driver); | ||
1236 | if (ret != 0) | ||
1237 | printk(KERN_ERR "can't add i2c driver"); | ||
1238 | } | ||
1239 | #else | ||
1240 | /* Add other interfaces here */ | ||
1241 | #endif | ||
1242 | return ret; | ||
1243 | } | ||
1244 | |||
1245 | static int aic3x_remove(struct platform_device *pdev) | ||
1246 | { | ||
1247 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | ||
1248 | struct snd_soc_codec *codec = socdev->codec; | ||
1249 | |||
1250 | /* power down chip */ | ||
1251 | if (codec->control_data) | ||
1252 | aic3x_dapm_event(codec, SNDRV_CTL_POWER_D3); | ||
1253 | |||
1254 | snd_soc_free_pcms(socdev); | ||
1255 | snd_soc_dapm_free(socdev); | ||
1256 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | ||
1257 | i2c_del_driver(&aic3x_i2c_driver); | ||
1258 | #endif | ||
1259 | kfree(codec->private_data); | ||
1260 | kfree(codec); | ||
1261 | |||
1262 | return 0; | ||
1263 | } | ||
1264 | |||
1265 | struct snd_soc_codec_device soc_codec_dev_aic3x = { | ||
1266 | .probe = aic3x_probe, | ||
1267 | .remove = aic3x_remove, | ||
1268 | .suspend = aic3x_suspend, | ||
1269 | .resume = aic3x_resume, | ||
1270 | }; | ||
1271 | EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x); | ||
1272 | |||
1273 | MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver"); | ||
1274 | MODULE_AUTHOR("Vladimir Barinov"); | ||
1275 | MODULE_LICENSE("GPL"); | ||
diff --git a/sound/soc/codecs/tlv320aic3x.h b/sound/soc/codecs/tlv320aic3x.h new file mode 100644 index 000000000000..d0cdeeb629de --- /dev/null +++ b/sound/soc/codecs/tlv320aic3x.h | |||
@@ -0,0 +1,181 @@ | |||
1 | /* | ||
2 | * ALSA SoC TLV320AIC3X codec driver | ||
3 | * | ||
4 | * Author: Vladimir Barinov, <vbarinov@ru.mvista.com> | ||
5 | * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #ifndef _AIC3X_H | ||
13 | #define _AIC3X_H | ||
14 | |||
15 | /* AIC3X register space */ | ||
16 | #define AIC3X_CACHEREGNUM 103 | ||
17 | |||
18 | /* Page select register */ | ||
19 | #define AIC3X_PAGE_SELECT 0 | ||
20 | /* Software reset register */ | ||
21 | #define AIC3X_RESET 1 | ||
22 | /* Codec Sample rate select register */ | ||
23 | #define AIC3X_SAMPLE_RATE_SEL_REG 2 | ||
24 | /* PLL progrramming register A */ | ||
25 | #define AIC3X_PLL_PROGA_REG 3 | ||
26 | /* PLL progrramming register B */ | ||
27 | #define AIC3X_PLL_PROGB_REG 4 | ||
28 | /* PLL progrramming register C */ | ||
29 | #define AIC3X_PLL_PROGC_REG 5 | ||
30 | /* PLL progrramming register D */ | ||
31 | #define AIC3X_PLL_PROGD_REG 6 | ||
32 | /* Codec datapath setup register */ | ||
33 | #define AIC3X_CODEC_DATAPATH_REG 7 | ||
34 | /* Audio serial data interface control register A */ | ||
35 | #define AIC3X_ASD_INTF_CTRLA 8 | ||
36 | /* Audio serial data interface control register B */ | ||
37 | #define AIC3X_ASD_INTF_CTRLB 9 | ||
38 | /* Audio overflow status and PLL R value programming register */ | ||
39 | #define AIC3X_OVRF_STATUS_AND_PLLR_REG 11 | ||
40 | |||
41 | /* ADC PGA Gain control registers */ | ||
42 | #define LADC_VOL 15 | ||
43 | #define RADC_VOL 16 | ||
44 | /* MIC3 control registers */ | ||
45 | #define MIC3LR_2_LADC_CTRL 17 | ||
46 | #define MIC3LR_2_RADC_CTRL 18 | ||
47 | /* Line1 Input control registers */ | ||
48 | #define LINE1L_2_LADC_CTRL 19 | ||
49 | #define LINE1R_2_RADC_CTRL 22 | ||
50 | /* Line2 Input control registers */ | ||
51 | #define LINE2L_2_LADC_CTRL 20 | ||
52 | #define LINE2R_2_RADC_CTRL 23 | ||
53 | /* MICBIAS Control Register */ | ||
54 | #define MICBIAS_CTRL 25 | ||
55 | |||
56 | /* AGC Control Registers A, B, C */ | ||
57 | #define LAGC_CTRL_A 26 | ||
58 | #define LAGC_CTRL_B 27 | ||
59 | #define LAGC_CTRL_C 28 | ||
60 | #define RAGC_CTRL_A 29 | ||
61 | #define RAGC_CTRL_B 30 | ||
62 | #define RAGC_CTRL_C 31 | ||
63 | |||
64 | /* DAC Power and Left High Power Output control registers */ | ||
65 | #define DAC_PWR 37 | ||
66 | #define HPLCOM_CFG 37 | ||
67 | /* Right High Power Output control registers */ | ||
68 | #define HPRCOM_CFG 38 | ||
69 | /* DAC Output Switching control registers */ | ||
70 | #define DAC_LINE_MUX 41 | ||
71 | /* High Power Output Driver Pop Reduction registers */ | ||
72 | #define HPOUT_POP_REDUCTION 42 | ||
73 | /* DAC Digital control registers */ | ||
74 | #define LDAC_VOL 43 | ||
75 | #define RDAC_VOL 44 | ||
76 | /* High Power Output control registers */ | ||
77 | #define LINE2L_2_HPLOUT_VOL 45 | ||
78 | #define LINE2R_2_HPROUT_VOL 62 | ||
79 | #define PGAL_2_HPLOUT_VOL 46 | ||
80 | #define PGAR_2_HPROUT_VOL 63 | ||
81 | #define DACL1_2_HPLOUT_VOL 47 | ||
82 | #define DACR1_2_HPROUT_VOL 64 | ||
83 | #define HPLOUT_CTRL 51 | ||
84 | #define HPROUT_CTRL 65 | ||
85 | /* High Power COM control registers */ | ||
86 | #define LINE2L_2_HPLCOM_VOL 52 | ||
87 | #define LINE2R_2_HPRCOM_VOL 69 | ||
88 | #define PGAL_2_HPLCOM_VOL 53 | ||
89 | #define PGAR_2_HPRCOM_VOL 70 | ||
90 | #define DACL1_2_HPLCOM_VOL 54 | ||
91 | #define DACR1_2_HPRCOM_VOL 71 | ||
92 | #define HPLCOM_CTRL 58 | ||
93 | #define HPRCOM_CTRL 72 | ||
94 | /* Mono Line Output Plus/Minus control registers */ | ||
95 | #define LINE2L_2_MONOLOPM_VOL 73 | ||
96 | #define LINE2R_2_MONOLOPM_VOL 76 | ||
97 | #define PGAL_2_MONOLOPM_VOL 74 | ||
98 | #define PGAR_2_MONOLOPM_VOL 77 | ||
99 | #define DACL1_2_MONOLOPM_VOL 75 | ||
100 | #define DACR1_2_MONOLOPM_VOL 78 | ||
101 | #define MONOLOPM_CTRL 79 | ||
102 | /* Line Output Plus/Minus control registers */ | ||
103 | #define LINE2L_2_LLOPM_VOL 80 | ||
104 | #define LINE2R_2_RLOPM_VOL 90 | ||
105 | #define PGAL_2_LLOPM_VOL 81 | ||
106 | #define PGAR_2_RLOPM_VOL 91 | ||
107 | #define DACL1_2_LLOPM_VOL 82 | ||
108 | #define DACR1_2_RLOPM_VOL 92 | ||
109 | #define LLOPM_CTRL 86 | ||
110 | #define RLOPM_CTRL 93 | ||
111 | /* Clock generation control register */ | ||
112 | #define AIC3X_CLKGEN_CTRL_REG 102 | ||
113 | |||
114 | /* Page select register bits */ | ||
115 | #define PAGE0_SELECT 0 | ||
116 | #define PAGE1_SELECT 1 | ||
117 | |||
118 | /* Audio serial data interface control register A bits */ | ||
119 | #define BIT_CLK_MASTER 0x80 | ||
120 | #define WORD_CLK_MASTER 0x40 | ||
121 | |||
122 | /* Codec Datapath setup register 7 */ | ||
123 | #define FSREF_44100 (1 << 7) | ||
124 | #define FSREF_48000 (0 << 7) | ||
125 | #define DUAL_RATE_MODE ((1 << 5) | (1 << 6)) | ||
126 | #define LDAC2LCH (0x1 << 3) | ||
127 | #define RDAC2RCH (0x1 << 1) | ||
128 | |||
129 | /* PLL registers bitfields */ | ||
130 | #define PLLP_SHIFT 0 | ||
131 | #define PLLR_SHIFT 0 | ||
132 | #define PLLJ_SHIFT 2 | ||
133 | #define PLLD_MSB_SHIFT 0 | ||
134 | #define PLLD_LSB_SHIFT 2 | ||
135 | |||
136 | /* Clock generation register bits */ | ||
137 | #define PLL_CLKIN_SHIFT 4 | ||
138 | #define MCLK_SOURCE 0x0 | ||
139 | #define PLL_CLKDIV_SHIFT 0 | ||
140 | |||
141 | /* Software reset register bits */ | ||
142 | #define SOFT_RESET 0x80 | ||
143 | |||
144 | /* PLL progrramming register A bits */ | ||
145 | #define PLL_ENABLE 0x80 | ||
146 | |||
147 | /* Route bits */ | ||
148 | #define ROUTE_ON 0x80 | ||
149 | |||
150 | /* Mute bits */ | ||
151 | #define UNMUTE 0x08 | ||
152 | #define MUTE_ON 0x80 | ||
153 | |||
154 | /* Power bits */ | ||
155 | #define LADC_PWR_ON 0x04 | ||
156 | #define RADC_PWR_ON 0x04 | ||
157 | #define LDAC_PWR_ON 0x80 | ||
158 | #define RDAC_PWR_ON 0x40 | ||
159 | #define HPLOUT_PWR_ON 0x01 | ||
160 | #define HPROUT_PWR_ON 0x01 | ||
161 | #define HPLCOM_PWR_ON 0x01 | ||
162 | #define HPRCOM_PWR_ON 0x01 | ||
163 | #define MONOLOPM_PWR_ON 0x01 | ||
164 | #define LLOPM_PWR_ON 0x01 | ||
165 | #define RLOPM_PWR_ON 0x01 | ||
166 | |||
167 | #define INVERT_VOL(val) (0x7f - val) | ||
168 | |||
169 | /* Default output volume (inverted) */ | ||
170 | #define DEFAULT_VOL INVERT_VOL(0x50) | ||
171 | /* Default input volume */ | ||
172 | #define DEFAULT_GAIN 0x20 | ||
173 | |||
174 | struct aic3x_setup_data { | ||
175 | unsigned short i2c_address; | ||
176 | }; | ||
177 | |||
178 | extern struct snd_soc_codec_dai aic3x_dai; | ||
179 | extern struct snd_soc_codec_device soc_codec_dev_aic3x; | ||
180 | |||
181 | #endif /* _AIC3X_H */ | ||