[PATCH] kexec: x86: resture apic virtual wire mode on shutdown

When coming out of apic mode attempt to set the appropriate
apic back into virtual wire mode.  This improves on previous versions
of this patch by by never setting bot the local apic and the ioapic
into veritual wire mode.

This code looks at data from the mptable to see if an ioapic has
an ExtInt input to make this decision.  A future improvement
is to figure out which apic or ioapic was in virtual wire mode
at boot time and to remember it.  That is potentially a more accurate
method, of selecting which apic to place in virutal wire mode.

Signed-off-by: Eric Biederman <ebiederm@xmission.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

4 files changed, 71 insertions, 3 deletions

diff --git a/arch/i386/kernel/apic.c b/arch/i386/kernel/apic.c
index cf45bed96d08..93df90bbb87e 100644
--- a/arch/i386/kernel/apic.c
+++ b/arch/i386/kernel/apic.c
@@ -211,7 +211,7 @@ void __init connect_bsp_APIC(void)
         enable_apic_mode();
 }
 
-void disconnect_bsp_APIC(void)
+void disconnect_bsp_APIC(int virt_wire_setup)
 {
         if (pic_mode) {
                 /*
@@ -225,6 +225,42 @@ void disconnect_bsp_APIC(void)
                 outb(0x70, 0x22);
                 outb(0x00, 0x23);
         }
+        else {
+                /* Go back to Virtual Wire compatibility mode */
+                unsigned long value;
+
+                /* For the spurious interrupt use vector F, and enable it */
+                value = apic_read(APIC_SPIV);
+                value &= ~APIC_VECTOR_MASK;
+                value |= APIC_SPIV_APIC_ENABLED;
+                value |= 0xf;
+                apic_write_around(APIC_SPIV, value);
+
+                if (!virt_wire_setup) {
+                        /* For LVT0 make it edge triggered, active high, external and enabled */
+                        value = apic_read(APIC_LVT0);
+                        value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
+                                APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
+                                APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
+                        value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
+                        value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
+                        apic_write_around(APIC_LVT0, value);
+                }
+                else {
+                        /* Disable LVT0 */
+                        apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
+                }
+
+                /* For LVT1 make it edge triggered, active high, nmi and enabled */
+                value = apic_read(APIC_LVT1);
+                value &= ~(
+                        APIC_MODE_MASK | APIC_SEND_PENDING |
+                        APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
+                        APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
+                value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
+                value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
+                apic_write_around(APIC_LVT1, value);
+        }
 }
 
 void disable_local_APIC(void)
diff --git a/arch/i386/kernel/io_apic.c b/arch/i386/kernel/io_apic.c
index 3c2b3bdfc807..fc81c8cddd22 100644
--- a/arch/i386/kernel/io_apic.c
+++ b/arch/i386/kernel/io_apic.c
@@ -1636,12 +1636,43 @@ static void __init enable_IO_APIC(void)
  */
 void disable_IO_APIC(void)
 {
+        int pin;
         /*
          * Clear the IO-APIC before rebooting:
          */
         clear_IO_APIC();
 
-        disconnect_bsp_APIC();
+        /*
+         * If the i82559 is routed through an IOAPIC
+         * Put that IOAPIC in virtual wire mode
+         * so legacy interrups can be delivered.
+         */
+        pin = find_isa_irq_pin(0, mp_ExtINT);
+        if (pin != -1) {
+                struct IO_APIC_route_entry entry;
+                unsigned long flags;
+
+                memset(&entry, 0, sizeof(entry));
+                entry.mask            = 0; /* Enabled */
+                entry.trigger         = 0; /* Edge */
+                entry.irr             = 0;
+                entry.polarity        = 0; /* High */
+                entry.delivery_status = 0;
+                entry.dest_mode       = 0; /* Physical */
+                entry.delivery_mode   = 7; /* ExtInt */
+                entry.vector          = 0;
+                entry.dest.physical.physical_dest = 0;
+
+
+                /*
+                 * Add it to the IO-APIC irq-routing table:
+                 */
+                spin_lock_irqsave(&ioapic_lock, flags);
+                io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
+                io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
+                spin_unlock_irqrestore(&ioapic_lock, flags);
+        }
+        disconnect_bsp_APIC(pin != -1);
 }
 
 /*
diff --git a/include/asm-i386/apic.h b/include/asm-i386/apic.h
index 53268cd9306e..6a1b1882285c 100644
--- a/include/asm-i386/apic.h
+++ b/include/asm-i386/apic.h
@@ -100,7 +100,7 @@ extern void (*wait_timer_tick)(void);
 extern int get_maxlvt(void);
 extern void clear_local_APIC(void);
 extern void connect_bsp_APIC (void);
-extern void disconnect_bsp_APIC (void);
+extern void disconnect_bsp_APIC (int virt_wire_setup);
 extern void disable_local_APIC (void);
 extern void lapic_shutdown (void);
 extern int verify_local_APIC (void);
diff --git a/include/asm-i386/apicdef.h b/include/asm-i386/apicdef.h
index 41e8d2d918e0..0fed5e3c699c 100644
--- a/include/asm-i386/apicdef.h
+++ b/include/asm-i386/apicdef.h
@@ -86,6 +86,7 @@
 #define                 APIC_LVT_REMOTE_IRR             (1<<14)
 #define                 APIC_INPUT_POLARITY             (1<<13)
 #define                 APIC_SEND_PENDING               (1<<12)
+#define                 APIC_MODE_MASK                  0x700
 #define                 GET_APIC_DELIVERY_MODE(x)       (((x)>>8)&0x7)
 #define                 SET_APIC_DELIVERY_MODE(x,y)     (((x)&~0x700)|((y)<<8))
 #define                         APIC_MODE_FIXED         0x0