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authorKyle McMartin <kyle@parisc-linux.org>2006-08-13 20:37:26 -0400
committerMatthew Wilcox <willy@parisc-linux.org>2006-10-04 08:44:58 -0400
commit32104b29cdf93f78ac37e681bd4547413466d13c (patch)
tree4b058cad9227dd960da79daf94235517690f9197
parent4068d93cd17561bcbfc821c831cb048385320bd6 (diff)
[PARISC] PA7200 also supports prefetch for read
It seems PA7200 processors also suppress traps on loads to %r0. This means we can prefetch for read on these cpus. Of course, we can't support prefetch for write, since that requires LOAD DOUBLEWORD which was added with PA2.0 Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
-rw-r--r--arch/parisc/Kconfig2
-rw-r--r--include/asm-parisc/prefetch.h3
2 files changed, 4 insertions, 1 deletions
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index 6dd0ea8f88e0..d2101237442e 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -127,7 +127,7 @@ config PA11
127 127
128config PREFETCH 128config PREFETCH
129 def_bool y 129 def_bool y
130 depends on PA8X00 130 depends on PA8X00 || PA7200
131 131
132config 64BIT 132config 64BIT
133 bool "64-bit kernel" 133 bool "64-bit kernel"
diff --git a/include/asm-parisc/prefetch.h b/include/asm-parisc/prefetch.h
index f5a2e7ae2662..5d021726fa33 100644
--- a/include/asm-parisc/prefetch.h
+++ b/include/asm-parisc/prefetch.h
@@ -24,11 +24,14 @@ extern inline void prefetch(const void *addr)
24 __asm__("ldw 0(%0), %%r0" : : "r" (addr)); 24 __asm__("ldw 0(%0), %%r0" : : "r" (addr));
25} 25}
26 26
27/* LDD is a PA2.0 addition. */
28#ifdef CONFIG_PA20
27#define ARCH_HAS_PREFETCHW 29#define ARCH_HAS_PREFETCHW
28extern inline void prefetchw(const void *addr) 30extern inline void prefetchw(const void *addr)
29{ 31{
30 __asm__("ldd 0(%0), %%r0" : : "r" (addr)); 32 __asm__("ldd 0(%0), %%r0" : : "r" (addr));
31} 33}
34#endif /* CONFIG_PA20 */
32 35
33#endif /* CONFIG_PREFETCH */ 36#endif /* CONFIG_PREFETCH */
34#endif /* __ASSEMBLY__ */ 37#endif /* __ASSEMBLY__ */