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authorSebastian Siewior <bigeasy@linux.vnet.ibm.com>2007-06-28 20:57:50 -0400
committerPaul Mackerras <paulus@samba.org>2007-07-03 01:24:44 -0400
commitbe7031773eded128675de6da778234a935c8d8ea (patch)
tree7309341f39051d535731e79da6c2ff75242ee95f
parent7a896dc5f4a369193256653535aa7e2b521c611d (diff)
[POWERPC] spufs: Add bit definition
Add a bit define from book, and replace one hex number with a symbol, for clarity. Signed-off-by: Sebastian Siewior <bigeasy@linux.vnet.ibm.com> Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
-rw-r--r--arch/powerpc/platforms/cell/spufs/run.c3
-rw-r--r--include/asm-powerpc/spu.h1
2 files changed, 3 insertions, 1 deletions
diff --git a/arch/powerpc/platforms/cell/spufs/run.c b/arch/powerpc/platforms/cell/spufs/run.c
index 6625ed2a7fdd..3ba30cea764a 100644
--- a/arch/powerpc/platforms/cell/spufs/run.c
+++ b/arch/powerpc/platforms/cell/spufs/run.c
@@ -29,7 +29,8 @@ static inline int spu_stopped(struct spu_context *ctx, u32 * stat)
29 spu = ctx->spu; 29 spu = ctx->spu;
30 pte_fault = spu->dsisr & 30 pte_fault = spu->dsisr &
31 (MFC_DSISR_PTE_NOT_FOUND | MFC_DSISR_ACCESS_DENIED); 31 (MFC_DSISR_PTE_NOT_FOUND | MFC_DSISR_ACCESS_DENIED);
32 return (!(*stat & 0x1) || pte_fault || spu->class_0_pending) ? 1 : 0; 32 return (!(*stat & SPU_STATUS_RUNNING) || pte_fault || spu->class_0_pending) ?
33 1 : 0;
33} 34}
34 35
35static int spu_setup_isolated(struct spu_context *ctx) 36static int spu_setup_isolated(struct spu_context *ctx)
diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h
index 31d5054be20f..5f894b61e2d4 100644
--- a/include/asm-powerpc/spu.h
+++ b/include/asm-powerpc/spu.h
@@ -448,6 +448,7 @@ struct spu_priv1 {
448#define MFC_STATE1_PROBLEM_STATE_MASK 0x08ull 448#define MFC_STATE1_PROBLEM_STATE_MASK 0x08ull
449#define MFC_STATE1_RELOCATE_MASK 0x10ull 449#define MFC_STATE1_RELOCATE_MASK 0x10ull
450#define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull 450#define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull
451#define MFC_STATE1_TABLE_SEARCH_MASK 0x40ull
451 u64 mfc_lpid_RW; /* 0x008 */ 452 u64 mfc_lpid_RW; /* 0x008 */
452 u64 spu_idr_RW; /* 0x010 */ 453 u64 spu_idr_RW; /* 0x010 */
453 u64 mfc_vr_RO; /* 0x018 */ 454 u64 mfc_vr_RO; /* 0x018 */