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authorDavid Howells <dhowells@redhat.com>2006-01-08 04:01:17 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2006-01-08 23:13:36 -0500
commit2fa9e7e2dce6aafecc1890461bdc00d78897be8b (patch)
treeea17c2801b5f9b59027641cb1aebc87d83397363
parent2919b51075b3906c2f476e5a932244af1947bf80 (diff)
[PATCH] frv: drop 8/16-bit xchg and cmpxchg
Drop support for 8-bit and 16-bit xchg and cmpxchg emulation and implements 32-bit xchg with the SWAP/SWAPI instruction. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat
-rw-r--r--arch/frv/lib/atomic-ops.S92
-rw-r--r--include/asm-frv/atomic.h96
2 files changed, 5 insertions, 183 deletions
diff --git a/arch/frv/lib/atomic-ops.S b/arch/frv/lib/atomic-ops.S
index b03d510a89e4..545cd325ac57 100644
--- a/arch/frv/lib/atomic-ops.S
+++ b/arch/frv/lib/atomic-ops.S
@@ -129,48 +129,6 @@ atomic_sub_return:
129 129
130############################################################################### 130###############################################################################
131# 131#
132# uint8_t __xchg_8(uint8_t i, uint8_t *v)
133#
134###############################################################################
135 .globl __xchg_8
136 .type __xchg_8,@function
137__xchg_8:
138 or.p gr8,gr8,gr10
1390:
140 orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
141 ckeq icc3,cc7
142 ldub.p @(gr9,gr0),gr8 /* LD.P/ORCR must be atomic */
143 orcr cc7,cc7,cc3 /* set CC3 to true */
144 cstb.p gr10,@(gr9,gr0) ,cc3,#1
145 corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
146 beq icc3,#0,0b
147 bralr
148
149 .size __xchg_8, .-__xchg_8
150
151###############################################################################
152#
153# uint16_t __xchg_16(uint16_t i, uint16_t *v)
154#
155###############################################################################
156 .globl __xchg_16
157 .type __xchg_16,@function
158__xchg_16:
159 or.p gr8,gr8,gr10
1600:
161 orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
162 ckeq icc3,cc7
163 lduh.p @(gr9,gr0),gr8 /* LD.P/ORCR must be atomic */
164 orcr cc7,cc7,cc3 /* set CC3 to true */
165 csth.p gr10,@(gr9,gr0) ,cc3,#1
166 corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
167 beq icc3,#0,0b
168 bralr
169
170 .size __xchg_16, .-__xchg_16
171
172###############################################################################
173#
174# uint32_t __xchg_32(uint32_t i, uint32_t *v) 132# uint32_t __xchg_32(uint32_t i, uint32_t *v)
175# 133#
176############################################################################### 134###############################################################################
@@ -192,56 +150,6 @@ __xchg_32:
192 150
193############################################################################### 151###############################################################################
194# 152#
195# uint8_t __cmpxchg_8(uint8_t *v, uint8_t test, uint8_t new)
196#
197###############################################################################
198 .globl __cmpxchg_8
199 .type __cmpxchg_8,@function
200__cmpxchg_8:
201 or.p gr8,gr8,gr11
2020:
203 orcc gr0,gr0,gr0,icc3
204 ckeq icc3,cc7
205 ldub.p @(gr11,gr0),gr8
206 orcr cc7,cc7,cc3
207 sub gr8,gr9,gr7
208 sllicc gr7,#24,gr0,icc0
209 bne icc0,#0,1f
210 cstb.p gr10,@(gr11,gr0) ,cc3,#1
211 corcc gr29,gr29,gr0 ,cc3,#1
212 beq icc3,#0,0b
2131:
214 bralr
215
216 .size __cmpxchg_8, .-__cmpxchg_8
217
218###############################################################################
219#
220# uint16_t __cmpxchg_16(uint16_t *v, uint16_t test, uint16_t new)
221#
222###############################################################################
223 .globl __cmpxchg_16
224 .type __cmpxchg_16,@function
225__cmpxchg_16:
226 or.p gr8,gr8,gr11
2270:
228 orcc gr0,gr0,gr0,icc3
229 ckeq icc3,cc7
230 lduh.p @(gr11,gr0),gr8
231 orcr cc7,cc7,cc3
232 sub gr8,gr9,gr7
233 sllicc gr7,#16,gr0,icc0
234 bne icc0,#0,1f
235 csth.p gr10,@(gr11,gr0) ,cc3,#1
236 corcc gr29,gr29,gr0 ,cc3,#1
237 beq icc3,#0,0b
2381:
239 bralr
240
241 .size __cmpxchg_16, .-__cmpxchg_16
242
243###############################################################################
244#
245# uint32_t __cmpxchg_32(uint32_t *v, uint32_t test, uint32_t new) 153# uint32_t __cmpxchg_32(uint32_t *v, uint32_t test, uint32_t new)
246# 154#
247############################################################################### 155###############################################################################
diff --git a/include/asm-frv/atomic.h b/include/asm-frv/atomic.h
index 3f54fea2b051..9c9e9499cfd8 100644
--- a/include/asm-frv/atomic.h
+++ b/include/asm-frv/atomic.h
@@ -218,51 +218,12 @@ extern unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsig
218 __typeof__(*(ptr)) __xg_orig; \ 218 __typeof__(*(ptr)) __xg_orig; \
219 \ 219 \
220 switch (sizeof(__xg_orig)) { \ 220 switch (sizeof(__xg_orig)) { \
221 case 1: \
222 asm volatile( \
223 "0: \n" \
224 " orcc gr0,gr0,gr0,icc3 \n" \
225 " ckeq icc3,cc7 \n" \
226 " ldub.p %M0,%1 \n" \
227 " orcr cc7,cc7,cc3 \n" \
228 " cstb.p %2,%M0 ,cc3,#1 \n" \
229 " corcc gr29,gr29,gr0 ,cc3,#1 \n" \
230 " beq icc3,#0,0b \n" \
231 : "+U"(*__xg_ptr), "=&r"(__xg_orig) \
232 : "r"(x) \
233 : "memory", "cc7", "cc3", "icc3" \
234 ); \
235 break; \
236 \
237 case 2: \
238 asm volatile( \
239 "0: \n" \
240 " orcc gr0,gr0,gr0,icc3 \n" \
241 " ckeq icc3,cc7 \n" \
242 " lduh.p %M0,%1 \n" \
243 " orcr cc7,cc7,cc3 \n" \
244 " csth.p %2,%M0 ,cc3,#1 \n" \
245 " corcc gr29,gr29,gr0 ,cc3,#1 \n" \
246 " beq icc3,#0,0b \n" \
247 : "+U"(*__xg_ptr), "=&r"(__xg_orig) \
248 : "r"(x) \
249 : "memory", "cc7", "cc3", "icc3" \
250 ); \
251 break; \
252 \
253 case 4: \ 221 case 4: \
254 asm volatile( \ 222 asm volatile( \
255 "0: \n" \ 223 "swap%I0 %2,%M0" \
256 " orcc gr0,gr0,gr0,icc3 \n" \ 224 : "+m"(*__xg_ptr), "=&r"(__xg_orig) \
257 " ckeq icc3,cc7 \n" \
258 " ld.p %M0,%1 \n" \
259 " orcr cc7,cc7,cc3 \n" \
260 " cst.p %2,%M0 ,cc3,#1 \n" \
261 " corcc gr29,gr29,gr0 ,cc3,#1 \n" \
262 " beq icc3,#0,0b \n" \
263 : "+U"(*__xg_ptr), "=&r"(__xg_orig) \
264 : "r"(x) \ 225 : "r"(x) \
265 : "memory", "cc7", "cc3", "icc3" \ 226 : "memory" \
266 ); \ 227 ); \
267 break; \ 228 break; \
268 \ 229 \
@@ -277,8 +238,6 @@ extern unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsig
277 238
278#else 239#else
279 240
280extern uint8_t __xchg_8 (uint8_t i, volatile void *v);
281extern uint16_t __xchg_16(uint16_t i, volatile void *v);
282extern uint32_t __xchg_32(uint32_t i, volatile void *v); 241extern uint32_t __xchg_32(uint32_t i, volatile void *v);
283 242
284#define xchg(ptr, x) \ 243#define xchg(ptr, x) \
@@ -287,8 +246,6 @@ extern uint32_t __xchg_32(uint32_t i, volatile void *v);
287 __typeof__(*(ptr)) __xg_orig; \ 246 __typeof__(*(ptr)) __xg_orig; \
288 \ 247 \
289 switch (sizeof(__xg_orig)) { \ 248 switch (sizeof(__xg_orig)) { \
290 case 1: __xg_orig = (__typeof__(*(ptr))) __xchg_8 ((uint8_t) x, __xg_ptr); break; \
291 case 2: __xg_orig = (__typeof__(*(ptr))) __xchg_16((uint16_t) x, __xg_ptr); break; \
292 case 4: __xg_orig = (__typeof__(*(ptr))) __xchg_32((uint32_t) x, __xg_ptr); break; \ 249 case 4: __xg_orig = (__typeof__(*(ptr))) __xchg_32((uint32_t) x, __xg_ptr); break; \
293 default: \ 250 default: \
294 __xg_orig = 0; \ 251 __xg_orig = 0; \
@@ -318,46 +275,6 @@ extern uint32_t __xchg_32(uint32_t i, volatile void *v);
318 __typeof__(*(ptr)) __xg_new = (new); \ 275 __typeof__(*(ptr)) __xg_new = (new); \
319 \ 276 \
320 switch (sizeof(__xg_orig)) { \ 277 switch (sizeof(__xg_orig)) { \
321 case 1: \
322 asm volatile( \
323 "0: \n" \
324 " orcc gr0,gr0,gr0,icc3 \n" \
325 " ckeq icc3,cc7 \n" \
326 " ldub.p %M0,%1 \n" \
327 " orcr cc7,cc7,cc3 \n" \
328 " sub%I4 %1,%4,%2 \n" \
329 " sllcc %2,#24,gr0,icc0 \n" \
330 " bne icc0,#0,1f \n" \
331 " cstb.p %3,%M0 ,cc3,#1 \n" \
332 " corcc gr29,gr29,gr0 ,cc3,#1 \n" \
333 " beq icc3,#0,0b \n" \
334 "1: \n" \
335 : "+U"(*__xg_ptr), "=&r"(__xg_orig), "=&r"(__xg_tmp) \
336 : "r"(__xg_new), "NPr"(__xg_test) \
337 : "memory", "cc7", "cc3", "icc3", "icc0" \
338 ); \
339 break; \
340 \
341 case 2: \
342 asm volatile( \
343 "0: \n" \
344 " orcc gr0,gr0,gr0,icc3 \n" \
345 " ckeq icc3,cc7 \n" \
346 " lduh.p %M0,%1 \n" \
347 " orcr cc7,cc7,cc3 \n" \
348 " sub%I4 %1,%4,%2 \n" \
349 " sllcc %2,#16,gr0,icc0 \n" \
350 " bne icc0,#0,1f \n" \
351 " csth.p %3,%M0 ,cc3,#1 \n" \
352 " corcc gr29,gr29,gr0 ,cc3,#1 \n" \
353 " beq icc3,#0,0b \n" \
354 "1: \n" \
355 : "+U"(*__xg_ptr), "=&r"(__xg_orig), "=&r"(__xg_tmp) \
356 : "r"(__xg_new), "NPr"(__xg_test) \
357 : "memory", "cc7", "cc3", "icc3", "icc0" \
358 ); \
359 break; \
360 \
361 case 4: \ 278 case 4: \
362 asm volatile( \ 279 asm volatile( \
363 "0: \n" \ 280 "0: \n" \
@@ -388,8 +305,6 @@ extern uint32_t __xchg_32(uint32_t i, volatile void *v);
388 305
389#else 306#else
390 307
391extern uint8_t __cmpxchg_8 (uint8_t *v, uint8_t test, uint8_t new);
392extern uint16_t __cmpxchg_16(uint16_t *v, uint16_t test, uint16_t new);
393extern uint32_t __cmpxchg_32(uint32_t *v, uint32_t test, uint32_t new); 308extern uint32_t __cmpxchg_32(uint32_t *v, uint32_t test, uint32_t new);
394 309
395#define cmpxchg(ptr, test, new) \ 310#define cmpxchg(ptr, test, new) \
@@ -400,8 +315,6 @@ extern uint32_t __cmpxchg_32(uint32_t *v, uint32_t test, uint32_t new);
400 __typeof__(*(ptr)) __xg_new = (new); \ 315 __typeof__(*(ptr)) __xg_new = (new); \
401 \ 316 \
402 switch (sizeof(__xg_orig)) { \ 317 switch (sizeof(__xg_orig)) { \
403 case 1: __xg_orig = __cmpxchg_8 (__xg_ptr, __xg_test, __xg_new); break; \
404 case 2: __xg_orig = __cmpxchg_16(__xg_ptr, __xg_test, __xg_new); break; \
405 case 4: __xg_orig = __cmpxchg_32(__xg_ptr, __xg_test, __xg_new); break; \ 318 case 4: __xg_orig = __cmpxchg_32(__xg_ptr, __xg_test, __xg_new); break; \
406 default: \ 319 default: \
407 __xg_orig = 0; \ 320 __xg_orig = 0; \
@@ -414,7 +327,7 @@ extern uint32_t __cmpxchg_32(uint32_t *v, uint32_t test, uint32_t new);
414 327
415#endif 328#endif
416 329
417#define atomic_cmpxchg(v, old, new) ((int)cmpxchg(&((v)->counter), old, new)) 330#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
418 331
419#define atomic_add_unless(v, a, u) \ 332#define atomic_add_unless(v, a, u) \
420({ \ 333({ \
@@ -424,6 +337,7 @@ extern uint32_t __cmpxchg_32(uint32_t *v, uint32_t test, uint32_t new);
424 c = old; \ 337 c = old; \
425 c != (u); \ 338 c != (u); \
426}) 339})
340
427#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) 341#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
428 342
429#include <asm-generic/atomic.h> 343#include <asm-generic/atomic.h>
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