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authordmitry pervushin <dpervushin@ru.mvista.com>2006-05-21 06:53:06 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-06-19 12:39:26 -0400
commit355c471f2ff324c21f8a1fb8e2e242a0f2a4aa68 (patch)
tree8a491d03e865b9e16686004dea765a141e048219
parent4a0312fca6599299bbed944ce09278d90388a3e5 (diff)
[MIPS] Support for the R5500-based NEC EMMA2RH Mark-eins board
Signed-off-by: dmitry pervushin <dpervushin@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat
-rw-r--r--arch/mips/Kconfig19
-rw-r--r--arch/mips/Makefile9
-rw-r--r--arch/mips/configs/emma2rh_defconfig1198
-rw-r--r--arch/mips/emma2rh/common/Makefile13
-rw-r--r--arch/mips/emma2rh/common/irq.c108
-rw-r--r--arch/mips/emma2rh/common/irq_emma2rh.c134
-rw-r--r--arch/mips/emma2rh/common/prom.c77
-rw-r--r--arch/mips/emma2rh/markeins/Makefile13
-rw-r--r--arch/mips/emma2rh/markeins/irq.c134
-rw-r--r--arch/mips/emma2rh/markeins/irq_markeins.c197
-rw-r--r--arch/mips/emma2rh/markeins/led.c60
-rw-r--r--arch/mips/emma2rh/markeins/platform.c170
-rw-r--r--arch/mips/emma2rh/markeins/setup.c182
-rw-r--r--arch/mips/pci/Makefile1
-rw-r--r--arch/mips/pci/fixup-emma2rh.c102
-rw-r--r--arch/mips/pci/ops-emma2rh.c186
-rw-r--r--arch/mips/pci/pci-emma2rh.c90
-rw-r--r--include/asm-mips/bootinfo.h6
-rw-r--r--include/asm-mips/emma2rh/emma2rh.h330
-rw-r--r--include/asm-mips/emma2rh/markeins.h76
-rw-r--r--include/asm-mips/mach-emma2rh/irq.h13
21 files changed, 3118 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index ecf922e3dc62..db3d008732c6 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -530,6 +530,20 @@ config QEMU
530 simulate actual MIPS hardware platforms. More information on Qemu 530 simulate actual MIPS hardware platforms. More information on Qemu
531 can be found at http://www.linux-mips.org/wiki/Qemu. 531 can be found at http://www.linux-mips.org/wiki/Qemu.
532 532
533config MARKEINS
534 bool "Support for NEC EMMA2RH Mark-eins"
535 select DMA_NONCOHERENT
536 select HW_HAS_PCI
537 select IRQ_CPU
538 select SWAP_IO_SPACE
539 select SYS_SUPPORTS_32BIT_KERNEL
540 select SYS_SUPPORTS_BIG_ENDIAN
541 select SYS_SUPPORTS_LITTLE_ENDIAN
542 select SYS_HAS_CPU_R5000
543 help
544 This enables support for the R5432-based NEC Mark-eins
545 boards with R5500 CPU.
546
533config SGI_IP22 547config SGI_IP22
534 bool "SGI IP22 (Indy/Indigo2)" 548 bool "SGI IP22 (Indy/Indigo2)"
535 select ARC 549 select ARC
@@ -968,6 +982,11 @@ config SOC_PNX8550
968config SWAP_IO_SPACE 982config SWAP_IO_SPACE
969 bool 983 bool
970 984
985config EMMA2RH
986 bool
987 depends on MARKEINS
988 default y
989
971# 990#
972# Unfortunately not all GT64120 systems run the chip at the same clock. 991# Unfortunately not all GT64120 systems run the chip at the same clock.
973# As the user for the clock rate and try to minimize the available options. 992# As the user for the clock rate and try to minimize the available options.
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index e0cab2850a72..207197b91a53 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -465,6 +465,15 @@ libs-$(CONFIG_PNX8550_JBS) += arch/mips/philips/pnx8550/jbs/
465#cflags-$(CONFIG_PNX8550_JBS) += -Iinclude/asm-mips/mach-pnx8550 465#cflags-$(CONFIG_PNX8550_JBS) += -Iinclude/asm-mips/mach-pnx8550
466load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000 466load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000
467 467
468# NEC EMMA2RH boards
469#
470core-$(CONFIG_EMMA2RH) += arch/mips/emma2rh/common/
471cflags-$(CONFIG_EMMA2RH) += -Iinclude/asm-mips/mach-emma2rh
472
473# NEC EMMA2RH Mark-eins
474core-$(CONFIG_MARKEINS) += arch/mips/emma2rh/markeins/
475load-$(CONFIG_MARKEINS) += 0xffffffff88100000
476
468# 477#
469# SGI IP22 (Indy/Indigo2) 478# SGI IP22 (Indy/Indigo2)
470# 479#
diff --git a/arch/mips/configs/emma2rh_defconfig b/arch/mips/configs/emma2rh_defconfig
new file mode 100644
index 000000000000..da1bc03fa256
--- /dev/null
+++ b/arch/mips/configs/emma2rh_defconfig
@@ -0,0 +1,1198 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.17
4# Sun Jun 18 13:46:53 2006
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11# CONFIG_MIPS_MTX1 is not set
12# CONFIG_MIPS_BOSPORUS is not set
13# CONFIG_MIPS_PB1000 is not set
14# CONFIG_MIPS_PB1100 is not set
15# CONFIG_MIPS_PB1500 is not set
16# CONFIG_MIPS_PB1550 is not set
17# CONFIG_MIPS_PB1200 is not set
18# CONFIG_MIPS_DB1000 is not set
19# CONFIG_MIPS_DB1100 is not set
20# CONFIG_MIPS_DB1500 is not set
21# CONFIG_MIPS_DB1550 is not set
22# CONFIG_MIPS_DB1200 is not set
23# CONFIG_MIPS_MIRAGE is not set
24# CONFIG_MIPS_COBALT is not set
25# CONFIG_MACH_DECSTATION is not set
26# CONFIG_MIPS_EV64120 is not set
27# CONFIG_MIPS_EV96100 is not set
28# CONFIG_MIPS_IVR is not set
29# CONFIG_MIPS_ITE8172 is not set
30# CONFIG_MACH_JAZZ is not set
31# CONFIG_LASAT is not set
32# CONFIG_MIPS_ATLAS is not set
33# CONFIG_MIPS_MALTA is not set
34# CONFIG_MIPS_SEAD is not set
35# CONFIG_WR_PPMC is not set
36# CONFIG_MIPS_SIM is not set
37# CONFIG_MOMENCO_JAGUAR_ATX is not set
38# CONFIG_MOMENCO_OCELOT is not set
39# CONFIG_MOMENCO_OCELOT_3 is not set
40# CONFIG_MOMENCO_OCELOT_C is not set
41# CONFIG_MOMENCO_OCELOT_G is not set
42# CONFIG_MIPS_XXS1500 is not set
43# CONFIG_PNX8550_V2PCI is not set
44# CONFIG_PNX8550_JBS is not set
45# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set
48# CONFIG_QEMU is not set
49CONFIG_MARKEINS=y
50# CONFIG_SGI_IP22 is not set
51# CONFIG_SGI_IP27 is not set
52# CONFIG_SGI_IP32 is not set
53# CONFIG_SIBYTE_BIGSUR is not set
54# CONFIG_SIBYTE_SWARM is not set
55# CONFIG_SIBYTE_SENTOSA is not set
56# CONFIG_SIBYTE_RHONE is not set
57# CONFIG_SIBYTE_CARMEL is not set
58# CONFIG_SIBYTE_PTSWARM is not set
59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set
63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set
66CONFIG_RWSEM_GENERIC_SPINLOCK=y
67CONFIG_GENERIC_FIND_NEXT_BIT=y
68CONFIG_GENERIC_HWEIGHT=y
69CONFIG_GENERIC_CALIBRATE_DELAY=y
70CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
71CONFIG_DMA_NONCOHERENT=y
72CONFIG_DMA_NEED_PCI_MAP_STATE=y
73CONFIG_CPU_BIG_ENDIAN=y
74# CONFIG_CPU_LITTLE_ENDIAN is not set
75CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
76CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
77CONFIG_IRQ_CPU=y
78CONFIG_SWAP_IO_SPACE=y
79CONFIG_EMMA2RH=y
80CONFIG_MIPS_L1_CACHE_SHIFT=5
81
82#
83# CPU selection
84#
85# CONFIG_CPU_MIPS32_R1 is not set
86# CONFIG_CPU_MIPS32_R2 is not set
87# CONFIG_CPU_MIPS64_R1 is not set
88# CONFIG_CPU_MIPS64_R2 is not set
89# CONFIG_CPU_R3000 is not set
90# CONFIG_CPU_TX39XX is not set
91# CONFIG_CPU_VR41XX is not set
92# CONFIG_CPU_R4300 is not set
93# CONFIG_CPU_R4X00 is not set
94# CONFIG_CPU_TX49XX is not set
95CONFIG_CPU_R5000=y
96# CONFIG_CPU_R5432 is not set
97# CONFIG_CPU_R6000 is not set
98# CONFIG_CPU_NEVADA is not set
99# CONFIG_CPU_R8000 is not set
100# CONFIG_CPU_R10000 is not set
101# CONFIG_CPU_RM7000 is not set
102# CONFIG_CPU_RM9000 is not set
103# CONFIG_CPU_SB1 is not set
104CONFIG_SYS_HAS_CPU_R5000=y
105CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
106CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
107CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
108
109#
110# Kernel type
111#
112CONFIG_32BIT=y
113# CONFIG_64BIT is not set
114CONFIG_PAGE_SIZE_4KB=y
115# CONFIG_PAGE_SIZE_8KB is not set
116# CONFIG_PAGE_SIZE_16KB is not set
117# CONFIG_PAGE_SIZE_64KB is not set
118CONFIG_MIPS_MT_DISABLED=y
119# CONFIG_MIPS_MT_SMTC is not set
120# CONFIG_MIPS_MT_SMP is not set
121# CONFIG_MIPS_VPE_LOADER is not set
122# CONFIG_64BIT_PHYS_ADDR is not set
123CONFIG_CPU_HAS_LLSC=y
124CONFIG_CPU_HAS_SYNC=y
125CONFIG_GENERIC_HARDIRQS=y
126CONFIG_GENERIC_IRQ_PROBE=y
127CONFIG_ARCH_FLATMEM_ENABLE=y
128CONFIG_SELECT_MEMORY_MODEL=y
129CONFIG_FLATMEM_MANUAL=y
130# CONFIG_DISCONTIGMEM_MANUAL is not set
131# CONFIG_SPARSEMEM_MANUAL is not set
132CONFIG_FLATMEM=y
133CONFIG_FLAT_NODE_MEM_MAP=y
134# CONFIG_SPARSEMEM_STATIC is not set
135CONFIG_SPLIT_PTLOCK_CPUS=4
136# CONFIG_PREEMPT_NONE is not set
137# CONFIG_PREEMPT_VOLUNTARY is not set
138CONFIG_PREEMPT=y
139CONFIG_PREEMPT_BKL=y
140
141#
142# Code maturity level options
143#
144CONFIG_EXPERIMENTAL=y
145CONFIG_BROKEN_ON_SMP=y
146CONFIG_LOCK_KERNEL=y
147CONFIG_INIT_ENV_ARG_LIMIT=32
148
149#
150# General setup
151#
152CONFIG_LOCALVERSION=""
153CONFIG_LOCALVERSION_AUTO=y
154CONFIG_SWAP=y
155CONFIG_SYSVIPC=y
156CONFIG_POSIX_MQUEUE=y
157CONFIG_BSD_PROCESS_ACCT=y
158# CONFIG_BSD_PROCESS_ACCT_V3 is not set
159CONFIG_SYSCTL=y
160# CONFIG_AUDIT is not set
161CONFIG_IKCONFIG=y
162CONFIG_IKCONFIG_PROC=y
163# CONFIG_RELAY is not set
164CONFIG_INITRAMFS_SOURCE=""
165# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
166CONFIG_EMBEDDED=y
167CONFIG_KALLSYMS=y
168# CONFIG_KALLSYMS_EXTRA_PASS is not set
169CONFIG_HOTPLUG=y
170CONFIG_PRINTK=y
171CONFIG_BUG=y
172CONFIG_ELF_CORE=y
173CONFIG_BASE_FULL=y
174CONFIG_FUTEX=y
175CONFIG_EPOLL=y
176CONFIG_SHMEM=y
177CONFIG_SLAB=y
178# CONFIG_TINY_SHMEM is not set
179CONFIG_BASE_SMALL=0
180# CONFIG_SLOB is not set
181CONFIG_OBSOLETE_INTERMODULE=y
182
183#
184# Loadable module support
185#
186CONFIG_MODULES=y
187CONFIG_MODULE_UNLOAD=y
188CONFIG_MODULE_FORCE_UNLOAD=y
189CONFIG_MODVERSIONS=y
190# CONFIG_MODULE_SRCVERSION_ALL is not set
191CONFIG_KMOD=y
192
193#
194# Block layer
195#
196CONFIG_LBD=y
197# CONFIG_BLK_DEV_IO_TRACE is not set
198# CONFIG_LSF is not set
199
200#
201# IO Schedulers
202#
203CONFIG_IOSCHED_NOOP=y
204CONFIG_IOSCHED_AS=y
205CONFIG_IOSCHED_DEADLINE=y
206CONFIG_IOSCHED_CFQ=y
207CONFIG_DEFAULT_AS=y
208# CONFIG_DEFAULT_DEADLINE is not set
209# CONFIG_DEFAULT_CFQ is not set
210# CONFIG_DEFAULT_NOOP is not set
211CONFIG_DEFAULT_IOSCHED="anticipatory"
212
213#
214# Bus options (PCI, PCMCIA, EISA, ISA, TC)
215#
216CONFIG_HW_HAS_PCI=y
217CONFIG_PCI=y
218CONFIG_MMU=y
219
220#
221# PCCARD (PCMCIA/CardBus) support
222#
223# CONFIG_PCCARD is not set
224
225#
226# PCI Hotplug Support
227#
228# CONFIG_HOTPLUG_PCI is not set
229
230#
231# Executable file formats
232#
233CONFIG_BINFMT_ELF=y
234# CONFIG_BINFMT_MISC is not set
235CONFIG_TRAD_SIGNALS=y
236
237#
238# Networking
239#
240CONFIG_NET=y
241
242#
243# Networking options
244#
245# CONFIG_NETDEBUG is not set
246CONFIG_PACKET=y
247CONFIG_PACKET_MMAP=y
248CONFIG_UNIX=y
249CONFIG_XFRM=y
250# CONFIG_XFRM_USER is not set
251CONFIG_NET_KEY=y
252CONFIG_INET=y
253CONFIG_IP_MULTICAST=y
254CONFIG_IP_ADVANCED_ROUTER=y
255CONFIG_ASK_IP_FIB_HASH=y
256# CONFIG_IP_FIB_TRIE is not set
257CONFIG_IP_FIB_HASH=y
258CONFIG_IP_MULTIPLE_TABLES=y
259# CONFIG_IP_ROUTE_FWMARK is not set
260CONFIG_IP_ROUTE_MULTIPATH=y
261# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set
262CONFIG_IP_ROUTE_VERBOSE=y
263CONFIG_IP_PNP=y
264# CONFIG_IP_PNP_DHCP is not set
265CONFIG_IP_PNP_BOOTP=y
266# CONFIG_IP_PNP_RARP is not set
267# CONFIG_NET_IPIP is not set
268# CONFIG_NET_IPGRE is not set
269# CONFIG_IP_MROUTE is not set
270# CONFIG_ARPD is not set
271CONFIG_SYN_COOKIES=y
272# CONFIG_INET_AH is not set
273# CONFIG_INET_ESP is not set
274# CONFIG_INET_IPCOMP is not set
275# CONFIG_INET_XFRM_TUNNEL is not set
276# CONFIG_INET_TUNNEL is not set
277CONFIG_INET_DIAG=y
278CONFIG_INET_TCP_DIAG=y
279# CONFIG_TCP_CONG_ADVANCED is not set
280CONFIG_TCP_CONG_BIC=y
281
282#
283# IP: Virtual Server Configuration
284#
285# CONFIG_IP_VS is not set
286CONFIG_IPV6=m
287# CONFIG_IPV6_PRIVACY is not set
288# CONFIG_IPV6_ROUTER_PREF is not set
289# CONFIG_INET6_AH is not set
290# CONFIG_INET6_ESP is not set
291# CONFIG_INET6_IPCOMP is not set
292# CONFIG_INET6_XFRM_TUNNEL is not set
293# CONFIG_INET6_TUNNEL is not set
294# CONFIG_IPV6_TUNNEL is not set
295CONFIG_NETFILTER=y
296# CONFIG_NETFILTER_DEBUG is not set
297
298#
299# Core Netfilter Configuration
300#
301# CONFIG_NETFILTER_NETLINK is not set
302# CONFIG_NF_CONNTRACK is not set
303# CONFIG_NETFILTER_XTABLES is not set
304
305#
306# IP: Netfilter Configuration
307#
308# CONFIG_IP_NF_CONNTRACK is not set
309# CONFIG_IP_NF_QUEUE is not set
310
311#
312# IPv6: Netfilter Configuration (EXPERIMENTAL)
313#
314# CONFIG_IP6_NF_QUEUE is not set
315
316#
317# DCCP Configuration (EXPERIMENTAL)
318#
319# CONFIG_IP_DCCP is not set
320
321#
322# SCTP Configuration (EXPERIMENTAL)
323#
324CONFIG_IP_SCTP=m
325# CONFIG_SCTP_DBG_MSG is not set
326# CONFIG_SCTP_DBG_OBJCNT is not set
327# CONFIG_SCTP_HMAC_NONE is not set
328# CONFIG_SCTP_HMAC_SHA1 is not set
329CONFIG_SCTP_HMAC_MD5=y
330
331#
332# TIPC Configuration (EXPERIMENTAL)
333#
334# CONFIG_TIPC is not set
335# CONFIG_ATM is not set
336# CONFIG_BRIDGE is not set
337# CONFIG_VLAN_8021Q is not set
338# CONFIG_DECNET is not set
339# CONFIG_LLC2 is not set
340# CONFIG_IPX is not set
341# CONFIG_ATALK is not set
342# CONFIG_X25 is not set
343# CONFIG_LAPB is not set
344# CONFIG_NET_DIVERT is not set
345# CONFIG_ECONET is not set
346# CONFIG_WAN_ROUTER is not set
347
348#
349# QoS and/or fair queueing
350#
351# CONFIG_NET_SCHED is not set
352
353#
354# Network testing
355#
356# CONFIG_NET_PKTGEN is not set
357# CONFIG_HAMRADIO is not set
358# CONFIG_IRDA is not set
359# CONFIG_BT is not set
360# CONFIG_IEEE80211 is not set
361
362#
363# Device Drivers
364#
365
366#
367# Generic Driver Options
368#
369CONFIG_STANDALONE=y
370CONFIG_PREVENT_FIRMWARE_BUILD=y
371# CONFIG_FW_LOADER is not set
372
373#
374# Connector - unified userspace <-> kernelspace linker
375#
376# CONFIG_CONNECTOR is not set
377
378#
379# Memory Technology Devices (MTD)
380#
381CONFIG_MTD=y
382# CONFIG_MTD_DEBUG is not set
383# CONFIG_MTD_CONCAT is not set
384CONFIG_MTD_PARTITIONS=y
385# CONFIG_MTD_REDBOOT_PARTS is not set
386CONFIG_MTD_CMDLINE_PARTS=y
387
388#
389# User Modules And Translation Layers
390#
391CONFIG_MTD_CHAR=y
392CONFIG_MTD_BLOCK=y
393# CONFIG_FTL is not set
394# CONFIG_NFTL is not set
395# CONFIG_INFTL is not set
396# CONFIG_RFD_FTL is not set
397
398#
399# RAM/ROM/Flash chip drivers
400#
401CONFIG_MTD_CFI=y
402# CONFIG_MTD_JEDECPROBE is not set
403CONFIG_MTD_GEN_PROBE=y
404# CONFIG_MTD_CFI_ADV_OPTIONS is not set
405CONFIG_MTD_MAP_BANK_WIDTH_1=y
406CONFIG_MTD_MAP_BANK_WIDTH_2=y
407CONFIG_MTD_MAP_BANK_WIDTH_4=y
408# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
409# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
410# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
411CONFIG_MTD_CFI_I1=y
412CONFIG_MTD_CFI_I2=y
413# CONFIG_MTD_CFI_I4 is not set
414# CONFIG_MTD_CFI_I8 is not set
415# CONFIG_MTD_CFI_INTELEXT is not set
416CONFIG_MTD_CFI_AMDSTD=y
417# CONFIG_MTD_CFI_STAA is not set
418CONFIG_MTD_CFI_UTIL=y
419# CONFIG_MTD_RAM is not set
420# CONFIG_MTD_ROM is not set
421# CONFIG_MTD_ABSENT is not set
422# CONFIG_MTD_OBSOLETE_CHIPS is not set
423
424#
425# Mapping drivers for chip access
426#
427# CONFIG_MTD_COMPLEX_MAPPINGS is not set
428CONFIG_MTD_PHYSMAP=y
429CONFIG_MTD_PHYSMAP_START=0x1e000000
430CONFIG_MTD_PHYSMAP_LEN=0x02000000
431CONFIG_MTD_PHYSMAP_BANKWIDTH=2
432# CONFIG_MTD_PLATRAM is not set
433
434#
435# Self-contained MTD device drivers
436#
437# CONFIG_MTD_PMC551 is not set
438# CONFIG_MTD_SLRAM is not set
439# CONFIG_MTD_PHRAM is not set
440# CONFIG_MTD_MTDRAM is not set
441# CONFIG_MTD_BLOCK2MTD is not set
442
443#
444# Disk-On-Chip Device Drivers
445#
446# CONFIG_MTD_DOC2000 is not set
447# CONFIG_MTD_DOC2001 is not set
448# CONFIG_MTD_DOC2001PLUS is not set
449
450#
451# NAND Flash Device Drivers
452#
453# CONFIG_MTD_NAND is not set
454
455#
456# OneNAND Flash Device Drivers
457#
458# CONFIG_MTD_ONENAND is not set
459
460#
461# Parallel port support
462#
463# CONFIG_PARPORT is not set
464
465#
466# Plug and Play support
467#
468
469#
470# Block devices
471#
472# CONFIG_BLK_CPQ_DA is not set
473# CONFIG_BLK_CPQ_CISS_DA is not set
474# CONFIG_BLK_DEV_DAC960 is not set
475# CONFIG_BLK_DEV_UMEM is not set
476# CONFIG_BLK_DEV_COW_COMMON is not set
477CONFIG_BLK_DEV_LOOP=m
478CONFIG_BLK_DEV_CRYPTOLOOP=m
479# CONFIG_BLK_DEV_NBD is not set
480# CONFIG_BLK_DEV_SX8 is not set
481# CONFIG_BLK_DEV_RAM is not set
482# CONFIG_BLK_DEV_INITRD is not set
483# CONFIG_CDROM_PKTCDVD is not set
484# CONFIG_ATA_OVER_ETH is not set
485
486#
487# ATA/ATAPI/MFM/RLL support
488#
489# CONFIG_IDE is not set
490
491#
492# SCSI device support
493#
494# CONFIG_RAID_ATTRS is not set
495CONFIG_SCSI=m
496# CONFIG_SCSI_PROC_FS is not set
497
498#
499# SCSI support type (disk, tape, CD-ROM)
500#
501CONFIG_BLK_DEV_SD=m
502# CONFIG_CHR_DEV_ST is not set
503# CONFIG_CHR_DEV_OSST is not set
504# CONFIG_BLK_DEV_SR is not set
505CONFIG_CHR_DEV_SG=m
506# CONFIG_CHR_DEV_SCH is not set
507
508#
509# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
510#
511# CONFIG_SCSI_MULTI_LUN is not set
512# CONFIG_SCSI_CONSTANTS is not set
513# CONFIG_SCSI_LOGGING is not set
514
515#
516# SCSI Transport Attributes
517#
518# CONFIG_SCSI_SPI_ATTRS is not set
519# CONFIG_SCSI_FC_ATTRS is not set
520# CONFIG_SCSI_ISCSI_ATTRS is not set
521# CONFIG_SCSI_SAS_ATTRS is not set
522
523#
524# SCSI low-level drivers
525#
526# CONFIG_ISCSI_TCP is not set
527# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
528# CONFIG_SCSI_3W_9XXX is not set
529# CONFIG_SCSI_ACARD is not set
530# CONFIG_SCSI_AACRAID is not set
531# CONFIG_SCSI_AIC7XXX is not set
532# CONFIG_SCSI_AIC7XXX_OLD is not set
533# CONFIG_SCSI_AIC79XX is not set
534# CONFIG_SCSI_DPT_I2O is not set
535# CONFIG_MEGARAID_NEWGEN is not set
536# CONFIG_MEGARAID_LEGACY is not set
537# CONFIG_MEGARAID_SAS is not set
538# CONFIG_SCSI_SATA is not set
539# CONFIG_SCSI_DMX3191D is not set
540# CONFIG_SCSI_FUTURE_DOMAIN is not set
541# CONFIG_SCSI_IPS is not set
542# CONFIG_SCSI_INITIO is not set
543# CONFIG_SCSI_INIA100 is not set
544# CONFIG_SCSI_SYM53C8XX_2 is not set
545# CONFIG_SCSI_IPR is not set
546# CONFIG_SCSI_QLOGIC_1280 is not set
547# CONFIG_SCSI_QLA_FC is not set
548# CONFIG_SCSI_LPFC is not set
549# CONFIG_SCSI_DC395x is not set
550# CONFIG_SCSI_DC390T is not set
551# CONFIG_SCSI_NSP32 is not set
552# CONFIG_SCSI_DEBUG is not set
553
554#
555# Multi-device support (RAID and LVM)
556#
557# CONFIG_MD is not set
558
559#
560# Fusion MPT device support
561#
562# CONFIG_FUSION is not set
563# CONFIG_FUSION_SPI is not set
564# CONFIG_FUSION_FC is not set
565# CONFIG_FUSION_SAS is not set
566
567#
568# IEEE 1394 (FireWire) support
569#
570# CONFIG_IEEE1394 is not set
571
572#
573# I2O device support
574#
575# CONFIG_I2O is not set
576
577#
578# Network device support
579#
580CONFIG_NETDEVICES=y
581# CONFIG_DUMMY is not set
582# CONFIG_BONDING is not set
583# CONFIG_EQUALIZER is not set
584CONFIG_TUN=m
585
586#
587# ARCnet devices
588#
589# CONFIG_ARCNET is not set
590
591#
592# PHY device support
593#
594# CONFIG_PHYLIB is not set
595
596#
597# Ethernet (10 or 100Mbit)
598#
599CONFIG_NET_ETHERNET=y
600CONFIG_MII=y
601# CONFIG_HAPPYMEAL is not set
602# CONFIG_SUNGEM is not set
603# CONFIG_CASSINI is not set
604# CONFIG_NET_VENDOR_3COM is not set
605# CONFIG_DM9000 is not set
606
607#
608# Tulip family network device support
609#
610# CONFIG_NET_TULIP is not set
611# CONFIG_HP100 is not set
612CONFIG_NET_PCI=y
613# CONFIG_PCNET32 is not set
614# CONFIG_AMD8111_ETH is not set
615# CONFIG_ADAPTEC_STARFIRE is not set
616# CONFIG_B44 is not set
617# CONFIG_FORCEDETH is not set
618# CONFIG_DGRS is not set
619# CONFIG_EEPRO100 is not set
620# CONFIG_E100 is not set
621# CONFIG_FEALNX is not set
622CONFIG_NATSEMI=y
623# CONFIG_NE2K_PCI is not set
624# CONFIG_8139CP is not set
625# CONFIG_8139TOO is not set
626# CONFIG_SIS900 is not set
627# CONFIG_EPIC100 is not set
628# CONFIG_SUNDANCE is not set
629# CONFIG_TLAN is not set
630# CONFIG_VIA_RHINE is not set
631# CONFIG_LAN_SAA9730 is not set
632
633#
634# Ethernet (1000 Mbit)
635#
636# CONFIG_ACENIC is not set
637# CONFIG_DL2K is not set
638# CONFIG_E1000 is not set
639# CONFIG_NS83820 is not set
640# CONFIG_HAMACHI is not set
641# CONFIG_YELLOWFIN is not set
642# CONFIG_R8169 is not set
643# CONFIG_SIS190 is not set
644# CONFIG_SKGE is not set
645# CONFIG_SKY2 is not set
646# CONFIG_SK98LIN is not set
647# CONFIG_VIA_VELOCITY is not set
648# CONFIG_TIGON3 is not set
649# CONFIG_BNX2 is not set
650
651#
652# Ethernet (10000 Mbit)
653#
654# CONFIG_CHELSIO_T1 is not set
655# CONFIG_IXGB is not set
656# CONFIG_S2IO is not set
657
658#
659# Token Ring devices
660#
661# CONFIG_TR is not set
662
663#
664# Wireless LAN (non-hamradio)
665#
666# CONFIG_NET_RADIO is not set
667
668#
669# Wan interfaces
670#
671# CONFIG_WAN is not set
672# CONFIG_FDDI is not set
673# CONFIG_HIPPI is not set
674CONFIG_PPP=m
675# CONFIG_PPP_MULTILINK is not set
676# CONFIG_PPP_FILTER is not set
677CONFIG_PPP_ASYNC=m
678CONFIG_PPP_SYNC_TTY=m
679CONFIG_PPP_DEFLATE=m
680# CONFIG_PPP_BSDCOMP is not set
681# CONFIG_PPP_MPPE is not set
682# CONFIG_PPPOE is not set
683# CONFIG_SLIP is not set
684# CONFIG_NET_FC is not set
685# CONFIG_SHAPER is not set
686# CONFIG_NETCONSOLE is not set
687# CONFIG_NETPOLL is not set
688# CONFIG_NET_POLL_CONTROLLER is not set
689
690#
691# ISDN subsystem
692#
693# CONFIG_ISDN is not set
694
695#
696# Telephony Support
697#
698# CONFIG_PHONE is not set
699
700#
701# Input device support
702#
703CONFIG_INPUT=y
704
705#
706# Userland interfaces
707#
708# CONFIG_INPUT_MOUSEDEV is not set
709# CONFIG_INPUT_JOYDEV is not set
710# CONFIG_INPUT_TSDEV is not set
711CONFIG_INPUT_EVDEV=m
712# CONFIG_INPUT_EVBUG is not set
713
714#
715# Input Device Drivers
716#
717# CONFIG_INPUT_KEYBOARD is not set
718# CONFIG_INPUT_MOUSE is not set
719# CONFIG_INPUT_JOYSTICK is not set
720# CONFIG_INPUT_TOUCHSCREEN is not set
721# CONFIG_INPUT_MISC is not set
722
723#
724# Hardware I/O ports
725#
726# CONFIG_SERIO is not set
727# CONFIG_GAMEPORT is not set
728
729#
730# Character devices
731#
732# CONFIG_VT is not set
733# CONFIG_SERIAL_NONSTANDARD is not set
734
735#
736# Serial drivers
737#
738CONFIG_SERIAL_8250=y
739CONFIG_SERIAL_8250_CONSOLE=y
740CONFIG_SERIAL_8250_PCI=y
741CONFIG_SERIAL_8250_NR_UARTS=4
742CONFIG_SERIAL_8250_RUNTIME_UARTS=4
743# CONFIG_SERIAL_8250_EXTENDED is not set
744
745#
746# Non-8250 serial port support
747#
748CONFIG_SERIAL_CORE=y
749CONFIG_SERIAL_CORE_CONSOLE=y
750# CONFIG_SERIAL_JSM is not set
751CONFIG_UNIX98_PTYS=y
752CONFIG_LEGACY_PTYS=y
753CONFIG_LEGACY_PTY_COUNT=256
754
755#
756# IPMI
757#
758# CONFIG_IPMI_HANDLER is not set
759
760#
761# Watchdog Cards
762#
763# CONFIG_WATCHDOG is not set
764CONFIG_RTC=m
765CONFIG_GEN_RTC=m
766CONFIG_GEN_RTC_X=y
767# CONFIG_DTLK is not set
768# CONFIG_R3964 is not set
769# CONFIG_APPLICOM is not set
770
771#
772# Ftape, the floppy tape device driver
773#
774# CONFIG_DRM is not set
775# CONFIG_RAW_DRIVER is not set
776
777#
778# TPM devices
779#
780# CONFIG_TCG_TPM is not set
781# CONFIG_TELCLOCK is not set
782
783#
784# I2C support
785#
786CONFIG_I2C=y
787CONFIG_I2C_CHARDEV=y
788
789#
790# I2C Algorithms
791#
792# CONFIG_I2C_ALGOBIT is not set
793# CONFIG_I2C_ALGOPCF is not set
794# CONFIG_I2C_ALGOPCA is not set
795
796#
797# I2C Hardware Bus support
798#
799# CONFIG_I2C_ALI1535 is not set
800# CONFIG_I2C_ALI1563 is not set
801# CONFIG_I2C_ALI15X3 is not set
802# CONFIG_I2C_AMD756 is not set
803# CONFIG_I2C_AMD8111 is not set
804# CONFIG_I2C_I801 is not set
805# CONFIG_I2C_I810 is not set
806# CONFIG_I2C_PIIX4 is not set
807# CONFIG_I2C_NFORCE2 is not set
808# CONFIG_I2C_PARPORT_LIGHT is not set
809# CONFIG_I2C_PROSAVAGE is not set
810# CONFIG_I2C_SAVAGE4 is not set
811# CONFIG_I2C_SIS5595 is not set
812# CONFIG_I2C_SIS630 is not set
813# CONFIG_I2C_SIS96X is not set
814# CONFIG_I2C_STUB is not set
815# CONFIG_I2C_VIA is not set
816# CONFIG_I2C_VIAPRO is not set
817# CONFIG_I2C_VOODOO3 is not set
818# CONFIG_I2C_PCA_ISA is not set
819
820#
821# Miscellaneous I2C Chip support
822#
823# CONFIG_SENSORS_DS1337 is not set
824# CONFIG_SENSORS_DS1374 is not set
825# CONFIG_SENSORS_EEPROM is not set
826# CONFIG_SENSORS_PCF8574 is not set
827# CONFIG_SENSORS_PCA9539 is not set
828# CONFIG_SENSORS_PCF8591 is not set
829# CONFIG_SENSORS_MAX6875 is not set
830CONFIG_I2C_DEBUG_CORE=y
831# CONFIG_I2C_DEBUG_ALGO is not set
832CONFIG_I2C_DEBUG_BUS=y
833# CONFIG_I2C_DEBUG_CHIP is not set
834
835#
836# SPI support
837#
838# CONFIG_SPI is not set
839# CONFIG_SPI_MASTER is not set
840
841#
842# Dallas's 1-wire bus
843#
844# CONFIG_W1 is not set
845
846#
847# Hardware Monitoring support
848#
849CONFIG_HWMON=y
850# CONFIG_HWMON_VID is not set
851# CONFIG_SENSORS_ADM1021 is not set
852# CONFIG_SENSORS_ADM1025 is not set
853# CONFIG_SENSORS_ADM1026 is not set
854# CONFIG_SENSORS_ADM1031 is not set
855# CONFIG_SENSORS_ADM9240 is not set
856# CONFIG_SENSORS_ASB100 is not set
857# CONFIG_SENSORS_ATXP1 is not set
858# CONFIG_SENSORS_DS1621 is not set
859# CONFIG_SENSORS_F71805F is not set
860# CONFIG_SENSORS_FSCHER is not set
861# CONFIG_SENSORS_FSCPOS is not set
862# CONFIG_SENSORS_GL518SM is not set
863# CONFIG_SENSORS_GL520SM is not set
864# CONFIG_SENSORS_IT87 is not set
865# CONFIG_SENSORS_LM63 is not set
866# CONFIG_SENSORS_LM75 is not set
867# CONFIG_SENSORS_LM77 is not set
868# CONFIG_SENSORS_LM78 is not set
869# CONFIG_SENSORS_LM80 is not set
870# CONFIG_SENSORS_LM83 is not set
871# CONFIG_SENSORS_LM85 is not set
872# CONFIG_SENSORS_LM87 is not set
873# CONFIG_SENSORS_LM90 is not set
874# CONFIG_SENSORS_LM92 is not set
875# CONFIG_SENSORS_MAX1619 is not set
876# CONFIG_SENSORS_PC87360 is not set
877# CONFIG_SENSORS_SIS5595 is not set
878# CONFIG_SENSORS_SMSC47M1 is not set
879# CONFIG_SENSORS_SMSC47B397 is not set
880# CONFIG_SENSORS_VIA686A is not set
881# CONFIG_SENSORS_VT8231 is not set
882# CONFIG_SENSORS_W83781D is not set
883# CONFIG_SENSORS_W83792D is not set
884# CONFIG_SENSORS_W83L785TS is not set
885# CONFIG_SENSORS_W83627HF is not set
886# CONFIG_SENSORS_W83627EHF is not set
887# CONFIG_HWMON_DEBUG_CHIP is not set
888
889#
890# Misc devices
891#
892
893#
894# Multimedia devices
895#
896# CONFIG_VIDEO_DEV is not set
897CONFIG_VIDEO_V4L2=y
898
899#
900# Digital Video Broadcasting Devices
901#
902# CONFIG_DVB is not set
903
904#
905# Graphics support
906#
907# CONFIG_FB is not set
908
909#
910# Sound
911#
912# CONFIG_SOUND is not set
913
914#
915# USB support
916#
917CONFIG_USB_ARCH_HAS_HCD=y
918CONFIG_USB_ARCH_HAS_OHCI=y
919CONFIG_USB_ARCH_HAS_EHCI=y
920# CONFIG_USB is not set
921
922#
923# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
924#
925
926#
927# USB Gadget Support
928#
929# CONFIG_USB_GADGET is not set
930
931#
932# MMC/SD Card support
933#
934# CONFIG_MMC is not set
935
936#
937# LED devices
938#
939# CONFIG_NEW_LEDS is not set
940
941#
942# LED drivers
943#
944
945#
946# LED Triggers
947#
948
949#
950# InfiniBand support
951#
952# CONFIG_INFINIBAND is not set
953
954#
955# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
956#
957
958#
959# Real Time Clock
960#
961# CONFIG_RTC_CLASS is not set
962
963#
964# File systems
965#
966CONFIG_EXT2_FS=y
967CONFIG_EXT2_FS_XATTR=y
968CONFIG_EXT2_FS_POSIX_ACL=y
969CONFIG_EXT2_FS_SECURITY=y
970# CONFIG_EXT2_FS_XIP is not set
971CONFIG_EXT3_FS=m
972CONFIG_EXT3_FS_XATTR=y
973# CONFIG_EXT3_FS_POSIX_ACL is not set
974# CONFIG_EXT3_FS_SECURITY is not set
975CONFIG_JBD=m
976# CONFIG_JBD_DEBUG is not set
977CONFIG_FS_MBCACHE=y
978# CONFIG_REISERFS_FS is not set
979# CONFIG_JFS_FS is not set
980CONFIG_FS_POSIX_ACL=y
981CONFIG_XFS_FS=m
982CONFIG_XFS_EXPORT=y
983# CONFIG_XFS_QUOTA is not set
984# CONFIG_XFS_SECURITY is not set
985# CONFIG_XFS_POSIX_ACL is not set
986# CONFIG_XFS_RT is not set
987# CONFIG_OCFS2_FS is not set
988# CONFIG_MINIX_FS is not set
989# CONFIG_ROMFS_FS is not set
990CONFIG_INOTIFY=y
991# CONFIG_QUOTA is not set
992# CONFIG_DNOTIFY is not set
993# CONFIG_AUTOFS_FS is not set
994CONFIG_AUTOFS4_FS=m
995# CONFIG_FUSE_FS is not set
996
997#
998# CD-ROM/DVD Filesystems
999#
1000# CONFIG_ISO9660_FS is not set
1001# CONFIG_UDF_FS is not set
1002
1003#
1004# DOS/FAT/NT Filesystems
1005#
1006CONFIG_FAT_FS=y
1007CONFIG_MSDOS_FS=y
1008CONFIG_VFAT_FS=y
1009CONFIG_FAT_DEFAULT_CODEPAGE=437
1010CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1011CONFIG_NTFS_FS=m
1012# CONFIG_NTFS_DEBUG is not set
1013# CONFIG_NTFS_RW is not set
1014
1015#
1016# Pseudo filesystems
1017#
1018CONFIG_PROC_FS=y
1019CONFIG_PROC_KCORE=y
1020CONFIG_SYSFS=y
1021CONFIG_TMPFS=y
1022# CONFIG_HUGETLB_PAGE is not set
1023CONFIG_RAMFS=y
1024# CONFIG_CONFIGFS_FS is not set
1025
1026#
1027# Miscellaneous filesystems
1028#
1029# CONFIG_ADFS_FS is not set
1030# CONFIG_AFFS_FS is not set
1031# CONFIG_HFS_FS is not set
1032# CONFIG_HFSPLUS_FS is not set
1033# CONFIG_BEFS_FS is not set
1034# CONFIG_BFS_FS is not set
1035# CONFIG_EFS_FS is not set
1036# CONFIG_JFFS_FS is not set
1037CONFIG_JFFS2_FS=y
1038CONFIG_JFFS2_FS_DEBUG=0
1039CONFIG_JFFS2_FS_WRITEBUFFER=y
1040# CONFIG_JFFS2_SUMMARY is not set
1041CONFIG_JFFS2_COMPRESSION_OPTIONS=y
1042CONFIG_JFFS2_ZLIB=y
1043CONFIG_JFFS2_RTIME=y
1044# CONFIG_JFFS2_RUBIN is not set
1045# CONFIG_JFFS2_CMODE_NONE is not set
1046CONFIG_JFFS2_CMODE_PRIORITY=y
1047# CONFIG_JFFS2_CMODE_SIZE is not set
1048CONFIG_CRAMFS=y
1049# CONFIG_VXFS_FS is not set
1050# CONFIG_HPFS_FS is not set
1051# CONFIG_QNX4FS_FS is not set
1052# CONFIG_SYSV_FS is not set
1053# CONFIG_UFS_FS is not set
1054
1055#
1056# Network File Systems
1057#
1058CONFIG_NFS_FS=y
1059CONFIG_NFS_V3=y
1060# CONFIG_NFS_V3_ACL is not set
1061CONFIG_NFS_V4=y
1062CONFIG_NFS_DIRECTIO=y
1063CONFIG_NFSD=m
1064CONFIG_NFSD_V3=y
1065# CONFIG_NFSD_V3_ACL is not set
1066# CONFIG_NFSD_V4 is not set
1067CONFIG_NFSD_TCP=y
1068CONFIG_ROOT_NFS=y
1069CONFIG_LOCKD=y
1070CONFIG_LOCKD_V4=y
1071CONFIG_EXPORTFS=m
1072CONFIG_NFS_COMMON=y
1073CONFIG_SUNRPC=y
1074CONFIG_SUNRPC_GSS=y
1075CONFIG_RPCSEC_GSS_KRB5=y
1076# CONFIG_RPCSEC_GSS_SPKM3 is not set
1077CONFIG_SMB_FS=m
1078# CONFIG_SMB_NLS_DEFAULT is not set
1079# CONFIG_CIFS is not set
1080# CONFIG_NCP_FS is not set
1081# CONFIG_CODA_FS is not set
1082# CONFIG_AFS_FS is not set
1083# CONFIG_9P_FS is not set
1084
1085#
1086# Partition Types
1087#
1088# CONFIG_PARTITION_ADVANCED is not set
1089CONFIG_MSDOS_PARTITION=y
1090
1091#
1092# Native Language Support
1093#
1094CONFIG_NLS=y
1095CONFIG_NLS_DEFAULT=""
1096CONFIG_NLS_CODEPAGE_437=m
1097# CONFIG_NLS_CODEPAGE_737 is not set
1098# CONFIG_NLS_CODEPAGE_775 is not set
1099# CONFIG_NLS_CODEPAGE_850 is not set
1100# CONFIG_NLS_CODEPAGE_852 is not set
1101# CONFIG_NLS_CODEPAGE_855 is not set
1102# CONFIG_NLS_CODEPAGE_857 is not set
1103# CONFIG_NLS_CODEPAGE_860 is not set
1104# CONFIG_NLS_CODEPAGE_861 is not set
1105# CONFIG_NLS_CODEPAGE_862 is not set
1106# CONFIG_NLS_CODEPAGE_863 is not set
1107# CONFIG_NLS_CODEPAGE_864 is not set
1108# CONFIG_NLS_CODEPAGE_865 is not set
1109# CONFIG_NLS_CODEPAGE_866 is not set
1110# CONFIG_NLS_CODEPAGE_869 is not set
1111# CONFIG_NLS_CODEPAGE_936 is not set
1112# CONFIG_NLS_CODEPAGE_950 is not set
1113# CONFIG_NLS_CODEPAGE_932 is not set
1114# CONFIG_NLS_CODEPAGE_949 is not set
1115# CONFIG_NLS_CODEPAGE_874 is not set
1116# CONFIG_NLS_ISO8859_8 is not set
1117# CONFIG_NLS_CODEPAGE_1250 is not set
1118# CONFIG_NLS_CODEPAGE_1251 is not set
1119CONFIG_NLS_ASCII=m
1120CONFIG_NLS_ISO8859_1=m
1121# CONFIG_NLS_ISO8859_2 is not set
1122# CONFIG_NLS_ISO8859_3 is not set
1123# CONFIG_NLS_ISO8859_4 is not set
1124# CONFIG_NLS_ISO8859_5 is not set
1125# CONFIG_NLS_ISO8859_6 is not set
1126# CONFIG_NLS_ISO8859_7 is not set
1127# CONFIG_NLS_ISO8859_9 is not set
1128# CONFIG_NLS_ISO8859_13 is not set
1129# CONFIG_NLS_ISO8859_14 is not set
1130# CONFIG_NLS_ISO8859_15 is not set
1131# CONFIG_NLS_KOI8_R is not set
1132# CONFIG_NLS_KOI8_U is not set
1133CONFIG_NLS_UTF8=m
1134
1135#
1136# Profiling support
1137#
1138# CONFIG_PROFILING is not set
1139
1140#
1141# Kernel hacking
1142#
1143# CONFIG_PRINTK_TIME is not set
1144# CONFIG_MAGIC_SYSRQ is not set
1145# CONFIG_DEBUG_KERNEL is not set
1146CONFIG_LOG_BUF_SHIFT=14
1147# CONFIG_DEBUG_FS is not set
1148CONFIG_CROSSCOMPILE=y
1149CONFIG_CMDLINE="console=ttyS0,115200 mem=192m ip=bootp root=/dev/nfs rw"
1150
1151#
1152# Security options
1153#
1154# CONFIG_KEYS is not set
1155# CONFIG_SECURITY is not set
1156
1157#
1158# Cryptographic options
1159#
1160CONFIG_CRYPTO=y
1161CONFIG_CRYPTO_HMAC=y
1162# CONFIG_CRYPTO_NULL is not set
1163# CONFIG_CRYPTO_MD4 is not set
1164CONFIG_CRYPTO_MD5=y
1165# CONFIG_CRYPTO_SHA1 is not set
1166# CONFIG_CRYPTO_SHA256 is not set
1167# CONFIG_CRYPTO_SHA512 is not set
1168# CONFIG_CRYPTO_WP512 is not set
1169# CONFIG_CRYPTO_TGR192 is not set
1170CONFIG_CRYPTO_DES=y
1171# CONFIG_CRYPTO_BLOWFISH is not set
1172# CONFIG_CRYPTO_TWOFISH is not set
1173# CONFIG_CRYPTO_SERPENT is not set
1174# CONFIG_CRYPTO_AES is not set
1175# CONFIG_CRYPTO_CAST5 is not set
1176# CONFIG_CRYPTO_CAST6 is not set
1177# CONFIG_CRYPTO_TEA is not set
1178# CONFIG_CRYPTO_ARC4 is not set
1179# CONFIG_CRYPTO_KHAZAD is not set
1180# CONFIG_CRYPTO_ANUBIS is not set
1181# CONFIG_CRYPTO_DEFLATE is not set
1182# CONFIG_CRYPTO_MICHAEL_MIC is not set
1183# CONFIG_CRYPTO_CRC32C is not set
1184# CONFIG_CRYPTO_TEST is not set
1185
1186#
1187# Hardware crypto devices
1188#
1189
1190#
1191# Library routines
1192#
1193CONFIG_CRC_CCITT=m
1194# CONFIG_CRC16 is not set
1195CONFIG_CRC32=y
1196# CONFIG_LIBCRC32C is not set
1197CONFIG_ZLIB_INFLATE=y
1198CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/mips/emma2rh/common/Makefile b/arch/mips/emma2rh/common/Makefile
new file mode 100644
index 000000000000..859121b3867d
--- /dev/null
+++ b/arch/mips/emma2rh/common/Makefile
@@ -0,0 +1,13 @@
1#
2# arch/mips/emma2rh/common/Makefile
3# Makefile for the common code of NEC EMMA2RH based board.
4#
5# Copyright (C) NEC Electronics Corporation 2005-2006
6#
7# This program is free software; you can redistribute it and/or modify
8# it under the terms of the GNU General Public License as published by
9# the Free Software Foundation; either version 2 of the License, or
10# (at your option) any later version.
11#
12
13obj-$(CONFIG_MARKEINS) += irq.o irq_emma2rh.o prom.o
diff --git a/arch/mips/emma2rh/common/irq.c b/arch/mips/emma2rh/common/irq.c
new file mode 100644
index 000000000000..b075281e50e9
--- /dev/null
+++ b/arch/mips/emma2rh/common/irq.c
@@ -0,0 +1,108 @@
1/*
2 * arch/mips/emma2rh/common/irq.c
3 * This file is common irq dispatcher.
4 *
5 * Copyright (C) NEC Electronics Corporation 2005-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25#include <linux/config.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/types.h>
30
31#include <asm/i8259.h>
32#include <asm/system.h>
33#include <asm/mipsregs.h>
34#include <asm/debug.h>
35#include <asm/addrspace.h>
36#include <asm/bootinfo.h>
37
38#include <asm/emma2rh/emma2rh.h>
39
40/*
41 * the first level int-handler will jump here if it is a emma2rh irq
42 */
43asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs)
44{
45 u32 intStatus;
46 u32 bitmask;
47 u32 i;
48
49 intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0)
50 & emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);
51
52#ifdef EMMA2RH_SW_CASCADE
53 if (intStatus &
54 (1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
55 u32 swIntStatus;
56 swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT)
57 & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
58 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
59 if (swIntStatus & bitmask) {
60 do_IRQ(EMMA2RH_SW_IRQ_BASE + i, regs);
61 return;
62 }
63 }
64 }
65#endif
66
67 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
68 if (intStatus & bitmask) {
69 do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
70 return;
71 }
72 }
73
74 intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1)
75 & emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);
76
77#ifdef EMMA2RH_GPIO_CASCADE
78 if (intStatus &
79 (1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
80 u32 gpioIntStatus;
81 gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST)
82 & emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
83 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
84 if (gpioIntStatus & bitmask) {
85 do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i, regs);
86 return;
87 }
88 }
89 }
90#endif
91
92 for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
93 if (intStatus & bitmask) {
94 do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
95 return;
96 }
97 }
98
99 intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2)
100 & emma2rh_in32(EMMA2RH_BHIF_INT_EN_2);
101
102 for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) {
103 if (intStatus & bitmask) {
104 do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
105 return;
106 }
107 }
108}
diff --git a/arch/mips/emma2rh/common/irq_emma2rh.c b/arch/mips/emma2rh/common/irq_emma2rh.c
new file mode 100644
index 000000000000..b886aa94ca90
--- /dev/null
+++ b/arch/mips/emma2rh/common/irq_emma2rh.c
@@ -0,0 +1,134 @@
1/*
2 * arch/mips/emma2rh/common/irq_emma2rh.c
3 * This file defines the irq handler for EMMA2RH.
4 *
5 * Copyright (C) NEC Electronics Corporation 2005-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25
26/*
27 * EMMA2RH defines 64 IRQs.
28 *
29 * This file exports one function:
30 * emma2rh_irq_init(u32 irq_base);
31 */
32
33#include <linux/interrupt.h>
34#include <linux/types.h>
35#include <linux/ptrace.h>
36
37#include <asm/debug.h>
38
39#include <asm/emma2rh/emma2rh.h>
40
41/* number of total irqs supported by EMMA2RH */
42#define NUM_EMMA2RH_IRQ 96
43
44static int emma2rh_irq_base = -1;
45
46void ll_emma2rh_irq_enable(int);
47void ll_emma2rh_irq_disable(int);
48
49static void emma2rh_irq_enable(unsigned int irq)
50{
51 ll_emma2rh_irq_enable(irq - emma2rh_irq_base);
52}
53
54static void emma2rh_irq_disable(unsigned int irq)
55{
56 ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
57}
58
59static unsigned int emma2rh_irq_startup(unsigned int irq)
60{
61 emma2rh_irq_enable(irq);
62 return 0;
63}
64
65#define emma2rh_irq_shutdown emma2rh_irq_disable
66
67static void emma2rh_irq_ack(unsigned int irq)
68{
69 /* disable interrupt - some handler will re-enable the irq
70 * and if the interrupt is leveled, we will have infinite loop
71 */
72 ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
73}
74
75static void emma2rh_irq_end(unsigned int irq)
76{
77 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
78 ll_emma2rh_irq_enable(irq - emma2rh_irq_base);
79}
80
81hw_irq_controller emma2rh_irq_controller = {
82 .typename = "emma2rh_irq",
83 .startup = emma2rh_irq_startup,
84 .shutdown = emma2rh_irq_shutdown,
85 .enable = emma2rh_irq_enable,
86 .disable = emma2rh_irq_disable,
87 .ack = emma2rh_irq_ack,
88 .end = emma2rh_irq_end,
89 .set_affinity = NULL /* no affinity stuff for UP */
90};
91
92void emma2rh_irq_init(u32 irq_base)
93{
94 u32 i;
95
96 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++) {
97 irq_desc[i].status = IRQ_DISABLED;
98 irq_desc[i].action = NULL;
99 irq_desc[i].depth = 1;
100 irq_desc[i].handler = &emma2rh_irq_controller;
101 }
102
103 emma2rh_irq_base = irq_base;
104}
105
106void ll_emma2rh_irq_enable(int emma2rh_irq)
107{
108 u32 reg_value;
109 u32 reg_bitmask;
110 u32 reg_index;
111
112 reg_index = EMMA2RH_BHIF_INT_EN_0
113 + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0)
114 * (emma2rh_irq / 32);
115 reg_value = emma2rh_in32(reg_index);
116 reg_bitmask = 0x1 << (emma2rh_irq % 32);
117 db_assert((reg_value & reg_bitmask) == 0);
118 emma2rh_out32(reg_index, reg_value | reg_bitmask);
119}
120
121void ll_emma2rh_irq_disable(int emma2rh_irq)
122{
123 u32 reg_value;
124 u32 reg_bitmask;
125 u32 reg_index;
126
127 reg_index = EMMA2RH_BHIF_INT_EN_0
128 + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0)
129 * (emma2rh_irq / 32);
130 reg_value = emma2rh_in32(reg_index);
131 reg_bitmask = 0x1 << (emma2rh_irq % 32);
132 db_assert((reg_value & reg_bitmask) != 0);
133 emma2rh_out32(reg_index, reg_value & ~reg_bitmask);
134}
diff --git a/arch/mips/emma2rh/common/prom.c b/arch/mips/emma2rh/common/prom.c
new file mode 100644
index 000000000000..8bba0b02a204
--- /dev/null
+++ b/arch/mips/emma2rh/common/prom.c
@@ -0,0 +1,77 @@
1/*
2 * arch/mips/emma2rh/common/prom.c
3 * This file is prom file.
4 *
5 * Copyright (C) NEC Electronics Corporation 2004-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/common/prom.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25#include <linux/config.h>
26#include <linux/init.h>
27#include <linux/mm.h>
28#include <linux/sched.h>
29#include <linux/bootmem.h>
30
31#include <asm/addrspace.h>
32#include <asm/bootinfo.h>
33#include <asm/emma2rh/emma2rh.h>
34#include <asm/debug.h>
35
36const char *get_system_type(void)
37{
38 switch (mips_machtype) {
39 case MACH_NEC_MARKEINS:
40 return "NEC EMMA2RH Mark-eins";
41 default:
42 return "Unknown NEC board";
43 }
44}
45
46/* [jsun@junsun.net] PMON passes arguments in C main() style */
47void __init prom_init(void)
48{
49 int argc = fw_arg0;
50 char **arg = (char **)fw_arg1;
51 int i;
52
53 /* if user passes kernel args, ignore the default one */
54 if (argc > 1)
55 arcs_cmdline[0] = '\0';
56
57 /* arg[0] is "g", the rest is boot parameters */
58 for (i = 1; i < argc; i++) {
59 if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
60 >= sizeof(arcs_cmdline))
61 break;
62 strcat(arcs_cmdline, arg[i]);
63 strcat(arcs_cmdline, " ");
64 }
65
66 mips_machgroup = MACH_GROUP_NEC_EMMA2RH;
67
68#if defined(CONFIG_MARKEINS)
69 mips_machtype = MACH_NEC_MARKEINS;
70 add_memory_region(0, EMMA2RH_RAM_SIZE, BOOT_MEM_RAM);
71#endif
72
73}
74
75void __init prom_free_prom_memory(void)
76{
77}
diff --git a/arch/mips/emma2rh/markeins/Makefile b/arch/mips/emma2rh/markeins/Makefile
new file mode 100644
index 000000000000..14fc268b175c
--- /dev/null
+++ b/arch/mips/emma2rh/markeins/Makefile
@@ -0,0 +1,13 @@
1#
2# arch/mips/emma2rh/markeins/Makefile
3# Makefile for the common code of NEC EMMA2RH based board.
4#
5# Copyright (C) NEC Electronics Corporation 2005-2006
6#
7# This program is free software; you can redistribute it and/or modify
8# it under the terms of the GNU General Public License as published by
9# the Free Software Foundation; either version 2 of the License, or
10# (at your option) any later version.
11#
12
13obj-$(CONFIG_MARKEINS) += irq.o irq_markeins.o setup.o led.o platform.o
diff --git a/arch/mips/emma2rh/markeins/irq.c b/arch/mips/emma2rh/markeins/irq.c
new file mode 100644
index 000000000000..76dc3faeaf4e
--- /dev/null
+++ b/arch/mips/emma2rh/markeins/irq.c
@@ -0,0 +1,134 @@
1/*
2 * arch/mips/emma2rh/markeins/irq.c
3 * This file defines the irq handler for EMMA2RH.
4 *
5 * Copyright (C) NEC Electronics Corporation 2004-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25#include <linux/config.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/types.h>
30#include <linux/ptrace.h>
31#include <linux/delay.h>
32
33#include <asm/i8259.h>
34#include <asm/irq_cpu.h>
35#include <asm/system.h>
36#include <asm/mipsregs.h>
37#include <asm/debug.h>
38#include <asm/addrspace.h>
39#include <asm/bootinfo.h>
40
41#include <asm/emma2rh/emma2rh.h>
42
43/*
44 * IRQ mapping
45 *
46 * 0-7: 8 CPU interrupts
47 * 0 - software interrupt 0
48 * 1 - software interrupt 1
49 * 2 - most Vrc5477 interrupts are routed to this pin
50 * 3 - (optional) some other interrupts routed to this pin for debugg
51 * 4 - not used
52 * 5 - not used
53 * 6 - not used
54 * 7 - cpu timer (used by default)
55 *
56 */
57
58extern void emma2rh_sw_irq_init(u32 base);
59extern void emma2rh_gpio_irq_init(u32 base);
60extern void emma2rh_irq_init(u32 base);
61extern asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs);
62
63static struct irqaction irq_cascade = {
64 .handler = no_action,
65 .flags = 0,
66 .mask = CPU_MASK_NONE,
67 .name = "cascade",
68 .dev_id = NULL,
69 .next = NULL,
70};
71
72void __init arch_init_irq(void)
73{
74 u32 reg;
75
76 db_run(printk("markeins_irq_setup invoked.\n"));
77
78 /* by default, interrupts are disabled. */
79 emma2rh_out32(EMMA2RH_BHIF_INT_EN_0, 0);
80 emma2rh_out32(EMMA2RH_BHIF_INT_EN_1, 0);
81 emma2rh_out32(EMMA2RH_BHIF_INT_EN_2, 0);
82 emma2rh_out32(EMMA2RH_BHIF_INT1_EN_0, 0);
83 emma2rh_out32(EMMA2RH_BHIF_INT1_EN_1, 0);
84 emma2rh_out32(EMMA2RH_BHIF_INT1_EN_2, 0);
85 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, 0);
86
87 clear_c0_status(0xff00);
88 set_c0_status(0x0400);
89
90#define GPIO_PCI (0xf<<15)
91 /* setup GPIO interrupt for PCI interface */
92 /* direction input */
93 reg = emma2rh_in32(EMMA2RH_GPIO_DIR);
94 emma2rh_out32(EMMA2RH_GPIO_DIR, reg & ~GPIO_PCI);
95 /* disable interrupt */
96 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
97 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg & ~GPIO_PCI);
98 /* level triggerd */
99 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MODE);
100 emma2rh_out32(EMMA2RH_GPIO_INT_MODE, reg | GPIO_PCI);
101 reg = emma2rh_in32(EMMA2RH_GPIO_INT_CND_A);
102 emma2rh_out32(EMMA2RH_GPIO_INT_CND_A, reg & (~GPIO_PCI));
103 /* interrupt clear */
104 emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~GPIO_PCI);
105
106 /* init all controllers */
107 emma2rh_irq_init(EMMA2RH_IRQ_BASE);
108 emma2rh_sw_irq_init(EMMA2RH_SW_IRQ_BASE);
109 emma2rh_gpio_irq_init(EMMA2RH_GPIO_IRQ_BASE);
110 mips_cpu_irq_init(CPU_IRQ_BASE);
111
112 /* setup cascade interrupts */
113 setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
114 setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
115 setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
116}
117
118asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
119{
120 unsigned int pending = read_c0_status() & read_c0_cause();
121
122 if (pending & STATUSF_IP7)
123 do_IRQ(CPU_IRQ_BASE + 7, regs);
124 else if (pending & STATUSF_IP2)
125 emma2rh_irq_dispatch(regs);
126 else if (pending & STATUSF_IP1)
127 do_IRQ(CPU_IRQ_BASE + 1, regs);
128 else if (pending & STATUSF_IP0)
129 do_IRQ(CPU_IRQ_BASE + 0, regs);
130 else
131 spurious_interrupt(regs);
132}
133
134
diff --git a/arch/mips/emma2rh/markeins/irq_markeins.c b/arch/mips/emma2rh/markeins/irq_markeins.c
new file mode 100644
index 000000000000..1783fdab6459
--- /dev/null
+++ b/arch/mips/emma2rh/markeins/irq_markeins.c
@@ -0,0 +1,197 @@
1/*
2 * arch/mips/emma2rh/markeins/irq_markeins.c
3 * This file defines the irq handler for Mark-eins.
4 *
5 * Copyright (C) NEC Electronics Corporation 2004-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/types.h>
28#include <linux/ptrace.h>
29
30#include <asm/debug.h>
31#include <asm/emma2rh/emma2rh.h>
32
33static int emma2rh_sw_irq_base = -1;
34static int emma2rh_gpio_irq_base = -1;
35
36void ll_emma2rh_sw_irq_enable(int reg);
37void ll_emma2rh_sw_irq_disable(int reg);
38void ll_emma2rh_gpio_irq_enable(int reg);
39void ll_emma2rh_gpio_irq_disable(int reg);
40
41static void emma2rh_sw_irq_enable(unsigned int irq)
42{
43 ll_emma2rh_sw_irq_enable(irq - emma2rh_sw_irq_base);
44}
45
46static void emma2rh_sw_irq_disable(unsigned int irq)
47{
48 ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
49}
50
51static unsigned int emma2rh_sw_irq_startup(unsigned int irq)
52{
53 emma2rh_sw_irq_enable(irq);
54 return 0;
55}
56
57#define emma2rh_sw_irq_shutdown emma2rh_sw_irq_disable
58
59static void emma2rh_sw_irq_ack(unsigned int irq)
60{
61 ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
62}
63
64static void emma2rh_sw_irq_end(unsigned int irq)
65{
66 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
67 ll_emma2rh_sw_irq_enable(irq - emma2rh_sw_irq_base);
68}
69
70hw_irq_controller emma2rh_sw_irq_controller = {
71 .typename = "emma2rh_sw_irq",
72 .startup = emma2rh_sw_irq_startup,
73 .shutdown = emma2rh_sw_irq_shutdown,
74 .enable = emma2rh_sw_irq_enable,
75 .disable = emma2rh_sw_irq_disable,
76 .ack = emma2rh_sw_irq_ack,
77 .end = emma2rh_sw_irq_end,
78 .set_affinity = NULL,
79};
80
81void emma2rh_sw_irq_init(u32 irq_base)
82{
83 u32 i;
84
85 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++) {
86 irq_desc[i].status = IRQ_DISABLED;
87 irq_desc[i].action = NULL;
88 irq_desc[i].depth = 2;
89 irq_desc[i].handler = &emma2rh_sw_irq_controller;
90 }
91
92 emma2rh_sw_irq_base = irq_base;
93}
94
95void ll_emma2rh_sw_irq_enable(int irq)
96{
97 u32 reg;
98
99 db_assert(irq >= 0);
100 db_assert(irq < NUM_EMMA2RH_IRQ_SW);
101
102 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
103 reg |= 1 << irq;
104 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
105}
106
107void ll_emma2rh_sw_irq_disable(int irq)
108{
109 u32 reg;
110
111 db_assert(irq >= 0);
112 db_assert(irq < 32);
113
114 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
115 reg &= ~(1 << irq);
116 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
117}
118
119static void emma2rh_gpio_irq_enable(unsigned int irq)
120{
121 ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base);
122}
123
124static void emma2rh_gpio_irq_disable(unsigned int irq)
125{
126 ll_emma2rh_gpio_irq_disable(irq - emma2rh_gpio_irq_base);
127}
128
129static unsigned int emma2rh_gpio_irq_startup(unsigned int irq)
130{
131 emma2rh_gpio_irq_enable(irq);
132 return 0;
133}
134
135#define emma2rh_gpio_irq_shutdown emma2rh_gpio_irq_disable
136
137static void emma2rh_gpio_irq_ack(unsigned int irq)
138{
139 irq -= emma2rh_gpio_irq_base;
140 emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
141 ll_emma2rh_gpio_irq_disable(irq);
142}
143
144static void emma2rh_gpio_irq_end(unsigned int irq)
145{
146 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
147 ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base);
148}
149
150hw_irq_controller emma2rh_gpio_irq_controller = {
151 .typename = "emma2rh_gpio_irq",
152 .startup = emma2rh_gpio_irq_startup,
153 .shutdown = emma2rh_gpio_irq_shutdown,
154 .enable = emma2rh_gpio_irq_enable,
155 .disable = emma2rh_gpio_irq_disable,
156 .ack = emma2rh_gpio_irq_ack,
157 .end = emma2rh_gpio_irq_end,
158 .set_affinity = NULL,
159};
160
161void emma2rh_gpio_irq_init(u32 irq_base)
162{
163 u32 i;
164
165 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_GPIO; i++) {
166 irq_desc[i].status = IRQ_DISABLED;
167 irq_desc[i].action = NULL;
168 irq_desc[i].depth = 2;
169 irq_desc[i].handler = &emma2rh_gpio_irq_controller;
170 }
171
172 emma2rh_gpio_irq_base = irq_base;
173}
174
175void ll_emma2rh_gpio_irq_enable(int irq)
176{
177 u32 reg;
178
179 db_assert(irq >= 0);
180 db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
181
182 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
183 reg |= 1 << irq;
184 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
185}
186
187void ll_emma2rh_gpio_irq_disable(int irq)
188{
189 u32 reg;
190
191 db_assert(irq >= 0);
192 db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
193
194 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
195 reg &= ~(1 << irq);
196 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
197}
diff --git a/arch/mips/emma2rh/markeins/led.c b/arch/mips/emma2rh/markeins/led.c
new file mode 100644
index 000000000000..b65254c1bfe9
--- /dev/null
+++ b/arch/mips/emma2rh/markeins/led.c
@@ -0,0 +1,60 @@
1/*
2 * arch/mips/emma2rh/markeins/led.c
3 * This file defines the led display for Mark-eins.
4 *
5 * Copyright (C) NEC Electronics Corporation 2004-2006
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/string.h>
24#include <asm/emma2rh/emma2rh.h>
25
26const unsigned long clear = 0x20202020;
27
28#define LED_BASE 0xb1400038
29
30void markeins_led_clear(void)
31{
32 emma2rh_out32(LED_BASE, clear);
33 emma2rh_out32(LED_BASE + 4, clear);
34}
35
36void markeins_led(const char *str)
37{
38 int i;
39 int len = strlen(str);
40
41 markeins_led_clear();
42 if (len > 8)
43 len = 8;
44
45 if (emma2rh_in32(0xb0000800) & (0x1 << 18))
46 for (i = 0; i < len; i++)
47 emma2rh_out8(LED_BASE + i, str[i]);
48 else
49 for (i = 0; i < len; i++)
50 emma2rh_out8(LED_BASE + (i & 4) + (3 - (i & 3)),
51 str[i]);
52}
53
54void markeins_led_hex(u32 val)
55{
56 char str[10];
57
58 sprintf(str, "%08x", val);
59 markeins_led(str);
60}
diff --git a/arch/mips/emma2rh/markeins/platform.c b/arch/mips/emma2rh/markeins/platform.c
new file mode 100644
index 000000000000..6c1eeae1a898
--- /dev/null
+++ b/arch/mips/emma2rh/markeins/platform.c
@@ -0,0 +1,170 @@
1/*
2 * arch/mips/emma2rh/markeins/platofrm.c
3 * This file sets up platform devices for EMMA2RH Mark-eins.
4 *
5 * Copyright(C) MontaVista Software Inc, 2006
6 *
7 * Author: dmitry pervushin <dpervushin@ru.mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23#include <linux/config.h>
24#include <linux/init.h>
25#include <linux/kernel.h>
26#include <linux/types.h>
27#include <linux/ioport.h>
28#include <linux/serial_8250.h>
29#include <linux/mtd/physmap.h>
30
31#include <asm/cpu.h>
32#include <asm/bootinfo.h>
33#include <asm/addrspace.h>
34#include <asm/time.h>
35#include <asm/bcache.h>
36#include <asm/irq.h>
37#include <asm/reboot.h>
38#include <asm/gdb-stub.h>
39#include <asm/traps.h>
40#include <asm/debug.h>
41
42#include <asm/emma2rh/emma2rh.h>
43
44
45#define I2C_EMMA2RH "emma2rh-iic" /* must be in sync with IIC driver */
46
47static struct resource i2c_emma_resources_0[] = {
48 { NULL, EMMA2RH_IRQ_PIIC0, EMMA2RH_IRQ_PIIC0, IORESOURCE_IRQ },
49 { NULL, KSEG1ADDR(EMMA2RH_PIIC0_BASE), KSEG1ADDR(EMMA2RH_PIIC0_BASE + 0x1000), 0 },
50};
51
52struct resource i2c_emma_resources_1[] = {
53 { NULL, EMMA2RH_IRQ_PIIC1, EMMA2RH_IRQ_PIIC1, IORESOURCE_IRQ },
54 { NULL, KSEG1ADDR(EMMA2RH_PIIC1_BASE), KSEG1ADDR(EMMA2RH_PIIC1_BASE + 0x1000), 0 },
55};
56
57struct resource i2c_emma_resources_2[] = {
58 { NULL, EMMA2RH_IRQ_PIIC2, EMMA2RH_IRQ_PIIC2, IORESOURCE_IRQ },
59 { NULL, KSEG1ADDR(EMMA2RH_PIIC2_BASE), KSEG1ADDR(EMMA2RH_PIIC2_BASE + 0x1000), 0 },
60};
61
62struct platform_device i2c_emma_devices[] = {
63 [0] = {
64 .name = I2C_EMMA2RH,
65 .id = 0,
66 .resource = i2c_emma_resources_0,
67 .num_resources = ARRAY_SIZE(i2c_emma_resources_0),
68 },
69 [1] = {
70 .name = I2C_EMMA2RH,
71 .id = 1,
72 .resource = i2c_emma_resources_1,
73 .num_resources = ARRAY_SIZE(i2c_emma_resources_1),
74 },
75 [2] = {
76 .name = I2C_EMMA2RH,
77 .id = 2,
78 .resource = i2c_emma_resources_2,
79 .num_resources = ARRAY_SIZE(i2c_emma_resources_2),
80 },
81};
82
83#define EMMA2RH_SERIAL_CLOCK 18544000
84#define EMMA2RH_SERIAL_FLAGS UPF_BOOT_AUTOCONF | UPF_SKIP_TEST
85
86static struct plat_serial8250_port platform_serial_ports[] = {
87 [0] = {
88 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3),
89 .irq = EMMA2RH_IRQ_PFUR0,
90 .uartclk = EMMA2RH_SERIAL_CLOCK,
91 .regshift = 4,
92 .iotype = UPIO_MEM,
93 .flags = EMMA2RH_SERIAL_FLAGS,
94 },
95 [1] = {
96 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3),
97 .irq = EMMA2RH_IRQ_PFUR1,
98 .uartclk = EMMA2RH_SERIAL_CLOCK,
99 .regshift = 4,
100 .iotype = UPIO_MEM,
101 .flags = EMMA2RH_SERIAL_FLAGS,
102 },
103 [2] = {
104 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR2_BASE + 3),
105 .irq = EMMA2RH_IRQ_PFUR2,
106 .uartclk = EMMA2RH_SERIAL_CLOCK,
107 .regshift = 4,
108 .iotype = UPIO_MEM,
109 .flags = EMMA2RH_SERIAL_FLAGS,
110 },
111 [3] = {
112 .flags = 0,
113 },
114};
115
116static struct platform_device serial_emma = {
117 .name = "serial8250",
118 .dev = {
119 .platform_data = &platform_serial_ports,
120 },
121};
122
123static struct platform_device *devices[] = {
124 &i2c_emma_devices[0],
125 &i2c_emma_devices[1],
126 &i2c_emma_devices[2],
127 &serial_emma,
128};
129
130static struct mtd_partition markeins_parts[] = {
131 [0] = {
132 .name = "RootFS",
133 .offset = 0x00000000,
134 .size = 0x00c00000,
135 },
136 [1] = {
137 .name = "boot code area",
138 .offset = MTDPART_OFS_APPEND,
139 .size = 0x00100000,
140 },
141 [2] = {
142 .name = "kernel image",
143 .offset = MTDPART_OFS_APPEND,
144 .size = 0x00300000,
145 },
146 [3] = {
147 .name = "RootFS2",
148 .offset = MTDPART_OFS_APPEND,
149 .size = 0x00c00000,
150 },
151 [4] = {
152 .name = "boot code area2",
153 .offset = MTDPART_OFS_APPEND,
154 .size = 0x00100000,
155 },
156 [5] = {
157 .name = "kernel image2",
158 .offset = MTDPART_OFS_APPEND,
159 .size = MTDPART_SIZ_FULL,
160 },
161};
162
163static int __init platform_devices_setup(void)
164{
165 physmap_set_partitions(markeins_parts, ARRAY_SIZE(markeins_parts));
166 return platform_add_devices(devices, ARRAY_SIZE(devices));
167}
168
169arch_initcall(platform_devices_setup);
170
diff --git a/arch/mips/emma2rh/markeins/setup.c b/arch/mips/emma2rh/markeins/setup.c
new file mode 100644
index 000000000000..7d98fdbf8390
--- /dev/null
+++ b/arch/mips/emma2rh/markeins/setup.c
@@ -0,0 +1,182 @@
1/*
2 * arch/mips/emma2rh/markeins/setup.c
3 * This file is setup for EMMA2RH Mark-eins.
4 *
5 * Copyright (C) NEC Electronics Corporation 2004-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/setup.c.
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25#include <linux/config.h>
26#include <linux/init.h>
27#include <linux/kernel.h>
28#include <linux/types.h>
29#include <linux/initrd.h>
30#include <linux/irq.h>
31#include <linux/ide.h>
32#include <linux/ioport.h>
33#include <linux/param.h> /* for HZ */
34#include <linux/root_dev.h>
35#include <linux/serial.h>
36#include <linux/serial_core.h>
37
38#include <asm/cpu.h>
39#include <asm/bootinfo.h>
40#include <asm/addrspace.h>
41#include <asm/time.h>
42#include <asm/bcache.h>
43#include <asm/irq.h>
44#include <asm/reboot.h>
45#include <asm/gdb-stub.h>
46#include <asm/traps.h>
47#include <asm/debug.h>
48
49#include <asm/emma2rh/emma2rh.h>
50
51#define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
52
53extern void markeins_led(const char *);
54
55static int bus_frequency = 0;
56
57static void markeins_machine_restart(char *command)
58{
59 static void (*back_to_prom) (void) = (void (*)(void))0xbfc00000;
60
61 printk("cannot EMMA2RH Mark-eins restart.\n");
62 markeins_led("restart.");
63 back_to_prom();
64}
65
66static void markeins_machine_halt(void)
67{
68 printk("EMMA2RH Mark-eins halted.\n");
69 markeins_led("halted.");
70 while (1) ;
71}
72
73static void markeins_machine_power_off(void)
74{
75 printk("EMMA2RH Mark-eins halted. Please turn off the power.\n");
76 markeins_led("poweroff.");
77 while (1) ;
78}
79
80static unsigned long clock[4] = { 166500000, 187312500, 199800000, 210600000 };
81
82static unsigned int __init detect_bus_frequency(unsigned long rtc_base)
83{
84 u32 reg;
85
86 /* detect from boot strap */
87 reg = emma2rh_in32(EMMA2RH_BHIF_STRAP_0);
88 reg = (reg >> 4) & 0x3;
89 return clock[reg];
90}
91
92static void __init emma2rh_time_init(void)
93{
94 u32 reg;
95 if (bus_frequency == 0)
96 bus_frequency = detect_bus_frequency(0);
97
98 reg = emma2rh_in32(EMMA2RH_BHIF_STRAP_0);
99 if ((reg & 0x3) == 0)
100 reg = (reg >> 6) & 0x3;
101 else {
102 reg = emma2rh_in32(EMMA2RH_BHIF_MAIN_CTRL);
103 reg = (reg >> 4) & 0x3;
104 }
105 mips_hpt_frequency = (bus_frequency * (4 + reg)) / 4 / 2;
106}
107
108static void __init emma2rh_timer_setup(struct irqaction *irq)
109{
110 /* we are using the cpu counter for timer interrupts */
111 setup_irq(CPU_IRQ_BASE + 7, irq);
112}
113
114static void markeins_board_init(void);
115extern void markeins_irq_setup(void);
116
117static void inline __init markeins_sio_setup(void)
118{
119#ifdef CONFIG_KGDB_8250
120 struct uart_port emma_port;
121
122 memset(&emma_port, 0, sizeof(emma_port));
123
124 emma_port.flags =
125 UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
126 emma_port.iotype = UPIO_MEM;
127 emma_port.regshift = 4; /* I/O addresses are every 8 bytes */
128 emma_port.uartclk = 18544000; /* Clock rate of the chip */
129
130 emma_port.line = 0;
131 emma_port.mapbase = KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3);
132 emma_port.membase = (u8*)emma_port.mapbase;
133 early_serial_setup(&emma_port);
134
135 emma_port.line = 1;
136 emma_port.mapbase = KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3);
137 emma_port.membase = (u8*)emma_port.mapbase;
138 early_serial_setup(&emma_port);
139
140 emma_port.irq = EMMA2RH_IRQ_PFUR1;
141 kgdb8250_add_port(1, &emma_port);
142#endif
143}
144
145void __init plat_mem_setup(void)
146{
147 /* initialize board - we don't trust the loader */
148 markeins_board_init();
149
150 set_io_port_base(KSEG1ADDR(EMMA2RH_PCI_IO_BASE));
151
152 board_time_init = emma2rh_time_init;
153 board_timer_setup = emma2rh_timer_setup;
154
155 _machine_restart = markeins_machine_restart;
156 _machine_halt = markeins_machine_halt;
157 pm_power_off = markeins_machine_power_off;
158
159 /* setup resource limits */
160 ioport_resource.start = EMMA2RH_PCI_IO_BASE;
161 ioport_resource.end = EMMA2RH_PCI_IO_BASE + EMMA2RH_PCI_IO_SIZE - 1;
162 iomem_resource.start = EMMA2RH_IO_BASE;
163 iomem_resource.end = EMMA2RH_ROM_BASE - 1;
164
165 /* Reboot on panic */
166 panic_timeout = 180;
167
168 markeins_sio_setup();
169}
170
171static void __init markeins_board_init(void)
172{
173 u32 val;
174
175 val = emma2rh_in32(EMMA2RH_PBRD_INT_EN); /* open serial interrupts. */
176 emma2rh_out32(EMMA2RH_PBRD_INT_EN, val | 0xaa);
177 val = emma2rh_in32(EMMA2RH_PBRD_CLKSEL); /* set serial clocks. */
178 emma2rh_out32(EMMA2RH_PBRD_CLKSEL, val | 0x5); /* 18MHz */
179 emma2rh_out32(EMMA2RH_PCI_CONTROL, 0);
180
181 markeins_led("MVL E2RH");
182}
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index c5f5516f4695..56000a069604 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
18obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o 18obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o
19obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o 19obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
20obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o 20obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o
21obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
21 22
22# 23#
23# These are still pretty much in the old state, watch, go blind. 24# These are still pretty much in the old state, watch, go blind.
diff --git a/arch/mips/pci/fixup-emma2rh.c b/arch/mips/pci/fixup-emma2rh.c
new file mode 100644
index 000000000000..3a34cd0efd6b
--- /dev/null
+++ b/arch/mips/pci/fixup-emma2rh.c
@@ -0,0 +1,102 @@
1/*
2 * arch/mips/pci/fixup-emma2rh.c
3 * This file defines the PCI configration.
4 *
5 * Copyright (C) NEC Electronics Corporation 2004-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/pci.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25
26#include <linux/config.h>
27#include <linux/kernel.h>
28#include <linux/init.h>
29#include <linux/types.h>
30#include <linux/pci.h>
31
32#include <asm/bootinfo.h>
33#include <asm/debug.h>
34
35#include <asm/emma2rh/emma2rh.h>
36
37#define EMMA2RH_PCI_HOST_SLOT 0x09
38#define EMMA2RH_USB_SLOT 0x03
39#define PCI_DEVICE_ID_NEC_EMMA2RH 0x014b /* EMMA2RH PCI Host */
40
41/*
42 * we fix up irqs based on the slot number.
43 * The first entry is at AD:11.
44 * Fortunately this works because, although we have two pci buses,
45 * they all have different slot numbers (except for rockhopper slot 20
46 * which is handled below).
47 *
48 */
49
50#define MAX_SLOT_NUM 10
51static unsigned char irq_map[][5] __initdata = {
52 [3] = {0, MARKEINS_PCI_IRQ_INTB, MARKEINS_PCI_IRQ_INTC,
53 MARKEINS_PCI_IRQ_INTD, 0,},
54 [4] = {0, MARKEINS_PCI_IRQ_INTA, 0, 0, 0,},
55 [5] = {0, 0, 0, 0, 0,},
56 [6] = {0, MARKEINS_PCI_IRQ_INTC, MARKEINS_PCI_IRQ_INTD,
57 MARKEINS_PCI_IRQ_INTA, MARKEINS_PCI_IRQ_INTB,},
58};
59
60static void __devinit nec_usb_controller_fixup(struct pci_dev *dev)
61{
62 if (PCI_SLOT(dev->devfn) == EMMA2RH_USB_SLOT)
63 /* on board USB controller configuration */
64 pci_write_config_dword(dev, 0xe4, 1 << 5);
65}
66
67DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
68 nec_usb_controller_fixup);
69
70/*
71 * Prevent the PCI layer from seeing the resources allocated to this device
72 * if it is the host bridge by marking it as such. These resources are of
73 * no consequence to the PCI layer (they are handled elsewhere).
74 */
75static void __devinit emma2rh_pci_host_fixup(struct pci_dev *dev)
76{
77 int i;
78
79 if (PCI_SLOT(dev->devfn) == EMMA2RH_PCI_HOST_SLOT) {
80 dev->class &= 0xff;
81 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
82 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
83 dev->resource[i].start = 0;
84 dev->resource[i].end = 0;
85 dev->resource[i].flags = 0;
86 }
87 }
88}
89
90DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_EMMA2RH,
91 emma2rh_pci_host_fixup);
92
93int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
94{
95 return irq_map[slot][pin];
96}
97
98/* Do platform specific device initialization at pci_enable_device() time */
99int pcibios_plat_dev_init(struct pci_dev *dev)
100{
101 return 0;
102}
diff --git a/arch/mips/pci/ops-emma2rh.c b/arch/mips/pci/ops-emma2rh.c
new file mode 100644
index 000000000000..e21b11bf66bc
--- /dev/null
+++ b/arch/mips/pci/ops-emma2rh.c
@@ -0,0 +1,186 @@
1/*
2 * arch/mips/pci/ops-emma2rh.c
3 * This file defines the PCI operation for EMMA2RH.
4 *
5 * Copyright (C) NEC Electronics Corporation 2004-2006
6 *
7 * This file is based on the arch/mips/pci/ops-vr41xx.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25
26#include <linux/config.h>
27#include <linux/pci.h>
28#include <linux/kernel.h>
29#include <linux/types.h>
30
31#include <asm/addrspace.h>
32#include <asm/debug.h>
33
34#include <asm/emma2rh/emma2rh.h>
35
36#define RTABORT (0x1<<9)
37#define RMABORT (0x1<<10)
38#define EMMA2RH_PCI_SLOT_NUM 9 /* 0000:09.0 is final PCI device */
39
40/*
41 * access config space
42 */
43
44static int check_args(struct pci_bus *bus, u32 devfn, u32 * bus_num)
45{
46 /* check if the bus is top-level */
47 if (bus->parent != NULL) {
48 *bus_num = bus->number;
49 db_assert(bus_num != 0);
50 } else
51 *bus_num = 0;
52
53 if (*bus_num == 0) {
54 /* Type 0 */
55 if (PCI_SLOT(devfn) >= 10)
56 return PCIBIOS_DEVICE_NOT_FOUND;
57 } else {
58 /* Type 1 */
59 if ((*bus_num >= 64) || (PCI_SLOT(devfn) >= 16))
60 return PCIBIOS_DEVICE_NOT_FOUND;
61 }
62 return 0;
63}
64
65static inline int set_pci_configuration_address(unsigned char bus_num,
66 unsigned int devfn, int where)
67{
68 u32 config_win0;
69
70 emma2rh_out32(EMMA2RH_PCI_INT, ~RMABORT);
71 if (bus_num == 0)
72 /*
73 * Type 0 configuration
74 */
75 config_win0 = (1 << (22 + PCI_SLOT(devfn))) | (5 << 9);
76 else
77 /*
78 * Type 1 configuration
79 */
80 config_win0 = (bus_num << 26) | (PCI_SLOT(devfn) << 22) |
81 (1 << 15) | (5 << 9);
82
83 emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, config_win0);
84
85 return 0;
86}
87
88static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
89 int size, uint32_t * val)
90{
91 u32 bus_num;
92 u32 base = KSEG1ADDR(EMMA2RH_PCI_CONFIG_BASE);
93 u32 backup_win0;
94 u32 data;
95
96 *val = 0xffffffffU;
97
98 if (check_args(bus, devfn, &bus_num) == PCIBIOS_DEVICE_NOT_FOUND)
99 return PCIBIOS_DEVICE_NOT_FOUND;
100
101 backup_win0 = emma2rh_in32(EMMA2RH_PCI_IWIN0_CTR);
102
103 if (set_pci_configuration_address(bus_num, devfn, where) < 0)
104 return PCIBIOS_DEVICE_NOT_FOUND;
105
106 data =
107 *(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) +
108 (where & 0xfffffffc));
109
110 switch (size) {
111 case 1:
112 *val = (data >> ((where & 3) << 3)) & 0xffU;
113 break;
114 case 2:
115 *val = (data >> ((where & 2) << 3)) & 0xffffU;
116 break;
117 case 4:
118 *val = data;
119 break;
120 default:
121 emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
122 return PCIBIOS_FUNC_NOT_SUPPORTED;
123 }
124
125 emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
126
127 if (emma2rh_in32(EMMA2RH_PCI_INT) & RMABORT)
128 return PCIBIOS_DEVICE_NOT_FOUND;
129
130 return PCIBIOS_SUCCESSFUL;
131}
132
133static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
134 int size, u32 val)
135{
136 u32 bus_num;
137 u32 base = KSEG1ADDR(EMMA2RH_PCI_CONFIG_BASE);
138 u32 backup_win0;
139 u32 data;
140 int shift;
141
142 if (check_args(bus, devfn, &bus_num) == PCIBIOS_DEVICE_NOT_FOUND)
143 return PCIBIOS_DEVICE_NOT_FOUND;
144
145 backup_win0 = emma2rh_in32(EMMA2RH_PCI_IWIN0_CTR);
146
147 if (set_pci_configuration_address(bus_num, devfn, where) < 0)
148 return PCIBIOS_DEVICE_NOT_FOUND;
149
150 /* read modify write */
151 data =
152 *(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) +
153 (where & 0xfffffffc));
154
155 switch (size) {
156 case 1:
157 shift = (where & 3) << 3;
158 data &= ~(0xffU << shift);
159 data |= ((val & 0xffU) << shift);
160 break;
161 case 2:
162 shift = (where & 2) << 3;
163 data &= ~(0xffffU << shift);
164 data |= ((val & 0xffffU) << shift);
165 break;
166 case 4:
167 data = val;
168 break;
169 default:
170 emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
171 return PCIBIOS_FUNC_NOT_SUPPORTED;
172 }
173 *(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) +
174 (where & 0xfffffffc)) = data;
175
176 emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
177 if (emma2rh_in32(EMMA2RH_PCI_INT) & RMABORT)
178 return PCIBIOS_DEVICE_NOT_FOUND;
179
180 return PCIBIOS_SUCCESSFUL;
181}
182
183struct pci_ops emma2rh_pci_ops = {
184 .read = pci_config_read,
185 .write = pci_config_write,
186};
diff --git a/arch/mips/pci/pci-emma2rh.c b/arch/mips/pci/pci-emma2rh.c
new file mode 100644
index 000000000000..0f8b230057d3
--- /dev/null
+++ b/arch/mips/pci/pci-emma2rh.c
@@ -0,0 +1,90 @@
1/*
2 * arch/mips/pci/pci-emma2rh.c
3 * This file defines the PCI configration.
4 *
5 * Copyright (C) NEC Electronics Corporation 2004-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/pci.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25
26#include <linux/config.h>
27#include <linux/kernel.h>
28#include <linux/init.h>
29#include <linux/types.h>
30#include <linux/pci.h>
31
32#include <asm/bootinfo.h>
33#include <asm/debug.h>
34
35#include <asm/emma2rh/emma2rh.h>
36
37static struct resource pci_io_resource = {
38 .name = "pci IO space",
39 .start = EMMA2RH_PCI_IO_BASE,
40 .end = EMMA2RH_PCI_IO_BASE + EMMA2RH_PCI_IO_SIZE - 1,
41 .flags = IORESOURCE_IO,
42};
43
44static struct resource pci_mem_resource = {
45 .name = "pci memory space",
46 .start = EMMA2RH_PCI_MEM_BASE,
47 .end = EMMA2RH_PCI_MEM_BASE + EMMA2RH_PCI_MEM_SIZE - 1,
48 .flags = IORESOURCE_MEM,
49};
50
51extern struct pci_ops emma2rh_pci_ops;
52
53static struct pci_controller emma2rh_pci_controller = {
54 .pci_ops = &emma2rh_pci_ops,
55 .mem_resource = &pci_mem_resource,
56 .io_resource = &pci_io_resource,
57 .mem_offset = -0x04000000,
58 .io_offset = 0,
59};
60
61static void __init emma2rh_pci_init(void)
62{
63 /* setup PCI interface */
64 emma2rh_out32(EMMA2RH_PCI_ARBIT_CTR, 0x70f);
65
66 emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, 0x80000a18);
67 emma2rh_out32(EMMA2RH_PCI_CONFIG_BASE + PCI_COMMAND,
68 PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_CAP_LIST |
69 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
70 emma2rh_out32(EMMA2RH_PCI_CONFIG_BASE + PCI_BASE_ADDRESS_0, 0x10000000);
71 emma2rh_out32(EMMA2RH_PCI_CONFIG_BASE + PCI_BASE_ADDRESS_1, 0x00000000);
72
73 emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, 0x12000000 | 0x218);
74 emma2rh_out32(EMMA2RH_PCI_IWIN1_CTR, 0x18000000 | 0x600);
75 emma2rh_out32(EMMA2RH_PCI_INIT_ESWP, 0x00000200);
76
77 emma2rh_out32(EMMA2RH_PCI_TWIN_CTR, 0x00009200);
78 emma2rh_out32(EMMA2RH_PCI_TWIN_BADR, 0x00000000);
79 emma2rh_out32(EMMA2RH_PCI_TWIN0_DADR, 0x00000000);
80 emma2rh_out32(EMMA2RH_PCI_TWIN1_DADR, 0x00000000);
81}
82
83static int __init emma2rh_pci_setup(void)
84{
85 emma2rh_pci_init();
86 register_pci_controller(&emma2rh_pci_controller);
87 return 0;
88}
89
90arch_initcall(emma2rh_pci_setup);
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index edf2b9a71c82..72fa6dc45523 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -218,6 +218,12 @@
218#define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */ 218#define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
219#define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */ 219#define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
220 220
221/*
222 * Valid machtype for group NEC EMMA2RH
223 */
224#define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */
225#define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */
226
221#define CL_SIZE COMMAND_LINE_SIZE 227#define CL_SIZE COMMAND_LINE_SIZE
222 228
223const char *get_system_type(void); 229const char *get_system_type(void);
diff --git a/include/asm-mips/emma2rh/emma2rh.h b/include/asm-mips/emma2rh/emma2rh.h
new file mode 100644
index 000000000000..4fb8df71caa9
--- /dev/null
+++ b/include/asm-mips/emma2rh/emma2rh.h
@@ -0,0 +1,330 @@
1/*
2 * include/asm-mips/emma2rh/emma2rh.h
3 * This file is EMMA2RH common header.
4 *
5 * Copyright (C) NEC Electronics Corporation 2005-2006
6 *
7 * This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
8 * Copyright 2001 MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24#ifndef __ASM_EMMA2RH_EMMA2RH_H
25#define __ASM_EMMA2RH_EMMA2RH_H
26
27/*
28 * EMMA2RH registers
29 */
30#define REGBASE 0x10000000
31
32#define EMMA2RH_BHIF_STRAP_0 (0x000010+REGBASE)
33#define EMMA2RH_BHIF_INT_ST_0 (0x000030+REGBASE)
34#define EMMA2RH_BHIF_INT_ST_1 (0x000034+REGBASE)
35#define EMMA2RH_BHIF_INT_ST_2 (0x000038+REGBASE)
36#define EMMA2RH_BHIF_INT_EN_0 (0x000040+REGBASE)
37#define EMMA2RH_BHIF_INT_EN_1 (0x000044+REGBASE)
38#define EMMA2RH_BHIF_INT_EN_2 (0x000048+REGBASE)
39#define EMMA2RH_BHIF_INT1_EN_0 (0x000050+REGBASE)
40#define EMMA2RH_BHIF_INT1_EN_1 (0x000054+REGBASE)
41#define EMMA2RH_BHIF_INT1_EN_2 (0x000058+REGBASE)
42#define EMMA2RH_BHIF_SW_INT (0x000070+REGBASE)
43#define EMMA2RH_BHIF_SW_INT_EN (0x000080+REGBASE)
44#define EMMA2RH_BHIF_SW_INT_CLR (0x000090+REGBASE)
45#define EMMA2RH_BHIF_MAIN_CTRL (0x0000b4+REGBASE)
46#define EMMA2RH_BHIF_EXCEPT_VECT_BASE_ADDRESS (0x0000c0+REGBASE)
47#define EMMA2RH_GPIO_DIR (0x110d20+REGBASE)
48#define EMMA2RH_GPIO_INT_ST (0x110d30+REGBASE)
49#define EMMA2RH_GPIO_INT_MASK (0x110d3c+REGBASE)
50#define EMMA2RH_GPIO_INT_MODE (0x110d48+REGBASE)
51#define EMMA2RH_GPIO_INT_CND_A (0x110d54+REGBASE)
52#define EMMA2RH_GPIO_INT_CND_B (0x110d60+REGBASE)
53#define EMMA2RH_PBRD_INT_EN (0x100010+REGBASE)
54#define EMMA2RH_PBRD_CLKSEL (0x100028+REGBASE)
55#define EMMA2RH_PFUR0_BASE (0x101000+REGBASE)
56#define EMMA2RH_PFUR1_BASE (0x102000+REGBASE)
57#define EMMA2RH_PFUR2_BASE (0x103000+REGBASE)
58#define EMMA2RH_PIIC0_BASE (0x107000+REGBASE)
59#define EMMA2RH_PIIC1_BASE (0x108000+REGBASE)
60#define EMMA2RH_PIIC2_BASE (0x109000+REGBASE)
61#define EMMA2RH_PCI_CONTROL (0x200000+REGBASE)
62#define EMMA2RH_PCI_ARBIT_CTR (0x200004+REGBASE)
63#define EMMA2RH_PCI_IWIN0_CTR (0x200010+REGBASE)
64#define EMMA2RH_PCI_IWIN1_CTR (0x200014+REGBASE)
65#define EMMA2RH_PCI_INIT_ESWP (0x200018+REGBASE)
66#define EMMA2RH_PCI_INT (0x200020+REGBASE)
67#define EMMA2RH_PCI_INT_EN (0x200024+REGBASE)
68#define EMMA2RH_PCI_TWIN_CTR (0x200030+REGBASE)
69#define EMMA2RH_PCI_TWIN_BADR (0x200034+REGBASE)
70#define EMMA2RH_PCI_TWIN0_DADR (0x200038+REGBASE)
71#define EMMA2RH_PCI_TWIN1_DADR (0x20003c+REGBASE)
72
73/*
74 * Memory map (physical address)
75 *
76 * Note most of the following address must be properly aligned by the
77 * corresponding size. For example, if PCI_IO_SIZE is 16MB, then
78 * PCI_IO_BASE must be aligned along 16MB boundary.
79 */
80
81/* the actual ram size is detected at run-time */
82#define EMMA2RH_RAM_BASE 0x00000000
83#define EMMA2RH_RAM_SIZE 0x10000000 /* less than 256MB */
84
85#define EMMA2RH_IO_BASE 0x10000000
86#define EMMA2RH_IO_SIZE 0x01000000 /* 16 MB */
87
88#define EMMA2RH_GENERALIO_BASE 0x11000000
89#define EMMA2RH_GENERALIO_SIZE 0x01000000 /* 16 MB */
90
91#define EMMA2RH_PCI_IO_BASE 0x12000000
92#define EMMA2RH_PCI_IO_SIZE 0x02000000 /* 32 MB */
93
94#define EMMA2RH_PCI_MEM_BASE 0x14000000
95#define EMMA2RH_PCI_MEM_SIZE 0x08000000 /* 128 MB */
96
97#define EMMA2RH_ROM_BASE 0x1c000000
98#define EMMA2RH_ROM_SIZE 0x04000000 /* 64 MB */
99
100#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE
101#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE
102
103#define NUM_CPU_IRQ 8
104#define NUM_EMMA2RH_IRQ 96
105
106#define CPU_EMMA2RH_CASCADE 2
107#define EMMA2RH_IRQ_BASE 0
108
109/*
110 * emma2rh irq defs
111 */
112
113#define EMMA2RH_IRQ_INT0 (0 + EMMA2RH_IRQ_BASE)
114#define EMMA2RH_IRQ_INT1 (1 + EMMA2RH_IRQ_BASE)
115#define EMMA2RH_IRQ_INT2 (2 + EMMA2RH_IRQ_BASE)
116#define EMMA2RH_IRQ_INT3 (3 + EMMA2RH_IRQ_BASE)
117#define EMMA2RH_IRQ_INT4 (4 + EMMA2RH_IRQ_BASE)
118#define EMMA2RH_IRQ_INT5 (5 + EMMA2RH_IRQ_BASE)
119#define EMMA2RH_IRQ_INT6 (6 + EMMA2RH_IRQ_BASE)
120#define EMMA2RH_IRQ_INT7 (7 + EMMA2RH_IRQ_BASE)
121#define EMMA2RH_IRQ_INT8 (8 + EMMA2RH_IRQ_BASE)
122#define EMMA2RH_IRQ_INT9 (9 + EMMA2RH_IRQ_BASE)
123#define EMMA2RH_IRQ_INT10 (10 + EMMA2RH_IRQ_BASE)
124#define EMMA2RH_IRQ_INT11 (11 + EMMA2RH_IRQ_BASE)
125#define EMMA2RH_IRQ_INT12 (12 + EMMA2RH_IRQ_BASE)
126#define EMMA2RH_IRQ_INT13 (13 + EMMA2RH_IRQ_BASE)
127#define EMMA2RH_IRQ_INT14 (14 + EMMA2RH_IRQ_BASE)
128#define EMMA2RH_IRQ_INT15 (15 + EMMA2RH_IRQ_BASE)
129#define EMMA2RH_IRQ_INT16 (16 + EMMA2RH_IRQ_BASE)
130#define EMMA2RH_IRQ_INT17 (17 + EMMA2RH_IRQ_BASE)
131#define EMMA2RH_IRQ_INT18 (18 + EMMA2RH_IRQ_BASE)
132#define EMMA2RH_IRQ_INT19 (19 + EMMA2RH_IRQ_BASE)
133#define EMMA2RH_IRQ_INT20 (20 + EMMA2RH_IRQ_BASE)
134#define EMMA2RH_IRQ_INT21 (21 + EMMA2RH_IRQ_BASE)
135#define EMMA2RH_IRQ_INT22 (22 + EMMA2RH_IRQ_BASE)
136#define EMMA2RH_IRQ_INT23 (23 + EMMA2RH_IRQ_BASE)
137#define EMMA2RH_IRQ_INT24 (24 + EMMA2RH_IRQ_BASE)
138#define EMMA2RH_IRQ_INT25 (25 + EMMA2RH_IRQ_BASE)
139#define EMMA2RH_IRQ_INT26 (26 + EMMA2RH_IRQ_BASE)
140#define EMMA2RH_IRQ_INT27 (27 + EMMA2RH_IRQ_BASE)
141#define EMMA2RH_IRQ_INT28 (28 + EMMA2RH_IRQ_BASE)
142#define EMMA2RH_IRQ_INT29 (29 + EMMA2RH_IRQ_BASE)
143#define EMMA2RH_IRQ_INT30 (30 + EMMA2RH_IRQ_BASE)
144#define EMMA2RH_IRQ_INT31 (31 + EMMA2RH_IRQ_BASE)
145#define EMMA2RH_IRQ_INT32 (32 + EMMA2RH_IRQ_BASE)
146#define EMMA2RH_IRQ_INT33 (33 + EMMA2RH_IRQ_BASE)
147#define EMMA2RH_IRQ_INT34 (34 + EMMA2RH_IRQ_BASE)
148#define EMMA2RH_IRQ_INT35 (35 + EMMA2RH_IRQ_BASE)
149#define EMMA2RH_IRQ_INT36 (36 + EMMA2RH_IRQ_BASE)
150#define EMMA2RH_IRQ_INT37 (37 + EMMA2RH_IRQ_BASE)
151#define EMMA2RH_IRQ_INT38 (38 + EMMA2RH_IRQ_BASE)
152#define EMMA2RH_IRQ_INT39 (39 + EMMA2RH_IRQ_BASE)
153#define EMMA2RH_IRQ_INT40 (40 + EMMA2RH_IRQ_BASE)
154#define EMMA2RH_IRQ_INT41 (41 + EMMA2RH_IRQ_BASE)
155#define EMMA2RH_IRQ_INT42 (42 + EMMA2RH_IRQ_BASE)
156#define EMMA2RH_IRQ_INT43 (43 + EMMA2RH_IRQ_BASE)
157#define EMMA2RH_IRQ_INT44 (44 + EMMA2RH_IRQ_BASE)
158#define EMMA2RH_IRQ_INT45 (45 + EMMA2RH_IRQ_BASE)
159#define EMMA2RH_IRQ_INT46 (46 + EMMA2RH_IRQ_BASE)
160#define EMMA2RH_IRQ_INT47 (47 + EMMA2RH_IRQ_BASE)
161#define EMMA2RH_IRQ_INT48 (48 + EMMA2RH_IRQ_BASE)
162#define EMMA2RH_IRQ_INT49 (49 + EMMA2RH_IRQ_BASE)
163#define EMMA2RH_IRQ_INT50 (50 + EMMA2RH_IRQ_BASE)
164#define EMMA2RH_IRQ_INT51 (51 + EMMA2RH_IRQ_BASE)
165#define EMMA2RH_IRQ_INT52 (52 + EMMA2RH_IRQ_BASE)
166#define EMMA2RH_IRQ_INT53 (53 + EMMA2RH_IRQ_BASE)
167#define EMMA2RH_IRQ_INT54 (54 + EMMA2RH_IRQ_BASE)
168#define EMMA2RH_IRQ_INT55 (55 + EMMA2RH_IRQ_BASE)
169#define EMMA2RH_IRQ_INT56 (56 + EMMA2RH_IRQ_BASE)
170#define EMMA2RH_IRQ_INT57 (57 + EMMA2RH_IRQ_BASE)
171#define EMMA2RH_IRQ_INT58 (58 + EMMA2RH_IRQ_BASE)
172#define EMMA2RH_IRQ_INT59 (59 + EMMA2RH_IRQ_BASE)
173#define EMMA2RH_IRQ_INT60 (60 + EMMA2RH_IRQ_BASE)
174#define EMMA2RH_IRQ_INT61 (61 + EMMA2RH_IRQ_BASE)
175#define EMMA2RH_IRQ_INT62 (62 + EMMA2RH_IRQ_BASE)
176#define EMMA2RH_IRQ_INT63 (63 + EMMA2RH_IRQ_BASE)
177
178#define EMMA2RH_IRQ_PFUR0 EMMA2RH_IRQ_INT49
179#define EMMA2RH_IRQ_PFUR1 EMMA2RH_IRQ_INT50
180#define EMMA2RH_IRQ_PFUR2 EMMA2RH_IRQ_INT51
181#define EMMA2RH_IRQ_PIIC0 EMMA2RH_IRQ_INT56
182#define EMMA2RH_IRQ_PIIC1 EMMA2RH_IRQ_INT57
183#define EMMA2RH_IRQ_PIIC2 EMMA2RH_IRQ_INT58
184
185/*
186 * EMMA2RH Register Access
187 */
188
189#define EMMA2RH_BASE (0xa0000000)
190
191static inline void emma2rh_sync(void)
192{
193 volatile u32 *p = (volatile u32 *)0xbfc00000;
194 (void)(*p);
195}
196
197static inline void emma2rh_out32(u32 offset, u32 val)
198{
199 *(volatile u32 *)(EMMA2RH_BASE | offset) = val;
200 emma2rh_sync();
201}
202
203static inline u32 emma2rh_in32(u32 offset)
204{
205 u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset);
206 emma2rh_sync();
207 return val;
208}
209
210static inline void emma2rh_out16(u32 offset, u16 val)
211{
212 *(volatile u16 *)(EMMA2RH_BASE | offset) = val;
213 emma2rh_sync();
214}
215
216static inline u16 emma2rh_in16(u32 offset)
217{
218 u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset);
219 emma2rh_sync();
220 return val;
221}
222
223static inline void emma2rh_out8(u32 offset, u8 val)
224{
225 *(volatile u8 *)(EMMA2RH_BASE | offset) = val;
226 emma2rh_sync();
227}
228
229static inline u8 emma2rh_in8(u32 offset)
230{
231 u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset);
232 emma2rh_sync();
233 return val;
234}
235
236/**
237 * IIC registers map
238 **/
239
240/*---------------------------------------------------------------------------*/
241/* CNT - Control register (00H R/W) */
242/*---------------------------------------------------------------------------*/
243#define SPT 0x00000001
244#define STT 0x00000002
245#define ACKE 0x00000004
246#define WTIM 0x00000008
247#define SPIE 0x00000010
248#define WREL 0x00000020
249#define LREL 0x00000040
250#define IICE 0x00000080
251#define CNT_RESERVED 0x000000ff /* reserved bit 0 */
252
253#define I2C_EMMA_START (IICE | STT)
254#define I2C_EMMA_STOP (IICE | SPT)
255#define I2C_EMMA_REPSTART I2C_EMMA_START
256
257/*---------------------------------------------------------------------------*/
258/* STA - Status register (10H Read) */
259/*---------------------------------------------------------------------------*/
260#define MSTS 0x00000080
261#define ALD 0x00000040
262#define EXC 0x00000020
263#define COI 0x00000010
264#define TRC 0x00000008
265#define ACKD 0x00000004
266#define STD 0x00000002
267#define SPD 0x00000001
268
269/*---------------------------------------------------------------------------*/
270/* CSEL - Clock select register (20H R/W) */
271/*---------------------------------------------------------------------------*/
272#define FCL 0x00000080
273#define ND50 0x00000040
274#define CLD 0x00000020
275#define DAD 0x00000010
276#define SMC 0x00000008
277#define DFC 0x00000004
278#define CL 0x00000003
279#define CSEL_RESERVED 0x000000ff /* reserved bit 0 */
280
281#define FAST397 0x0000008b
282#define FAST297 0x0000008a
283#define FAST347 0x0000000b
284#define FAST260 0x0000000a
285#define FAST130 0x00000008
286#define STANDARD108 0x00000083
287#define STANDARD83 0x00000082
288#define STANDARD95 0x00000003
289#define STANDARD73 0x00000002
290#define STANDARD36 0x00000001
291#define STANDARD71 0x00000000
292
293/*---------------------------------------------------------------------------*/
294/* SVA - Slave address register (30H R/W) */
295/*---------------------------------------------------------------------------*/
296#define SVA 0x000000fe
297
298/*---------------------------------------------------------------------------*/
299/* SHR - Shift register (40H R/W) */
300/*---------------------------------------------------------------------------*/
301#define SR 0x000000ff
302
303/*---------------------------------------------------------------------------*/
304/* INT - Interrupt register (50H R/W) */
305/* INTM - Interrupt mask register (60H R/W) */
306/*---------------------------------------------------------------------------*/
307#define INTE0 0x00000001
308
309/***********************************************************************
310 * I2C registers
311 ***********************************************************************
312 */
313#define I2C_EMMA_CNT 0x00
314#define I2C_EMMA_STA 0x10
315#define I2C_EMMA_CSEL 0x20
316#define I2C_EMMA_SVA 0x30
317#define I2C_EMMA_SHR 0x40
318#define I2C_EMMA_INT 0x50
319#define I2C_EMMA_INTM 0x60
320
321/*
322 * include the board dependent part
323 */
324#if defined(CONFIG_MARKEINS)
325#include <asm/emma2rh/markeins.h>
326#else
327#error "Unknown EMMA2RH board!"
328#endif
329
330#endif /* __ASM_EMMA2RH_EMMA2RH_H */
diff --git a/include/asm-mips/emma2rh/markeins.h b/include/asm-mips/emma2rh/markeins.h
new file mode 100644
index 000000000000..8fa766795078
--- /dev/null
+++ b/include/asm-mips/emma2rh/markeins.h
@@ -0,0 +1,76 @@
1/*
2 * include/asm-mips/emma2rh/markeins.h
3 * This file is EMMA2RH board depended header.
4 *
5 * Copyright (C) NEC Electronics Corporation 2005-2006
6 *
7 * This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
8 * Copyright 2001 MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25#ifndef MARKEINS_H
26#define MARKEINS_H
27
28#define NUM_EMMA2RH_IRQ_SW 32
29#define NUM_EMMA2RH_IRQ_GPIO 32
30
31#define EMMA2RH_SW_CASCADE (EMMA2RH_IRQ_INT7 - EMMA2RH_IRQ_INT0)
32#define EMMA2RH_GPIO_CASCADE (EMMA2RH_IRQ_INT46 - EMMA2RH_IRQ_INT0)
33
34#define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ)
35#define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW)
36#define CPU_IRQ_BASE (EMMA2RH_GPIO_IRQ_BASE + NUM_EMMA2RH_IRQ_GPIO)
37
38#define EMMA2RH_SW_IRQ_INT0 (0+EMMA2RH_SW_IRQ_BASE)
39#define EMMA2RH_SW_IRQ_INT1 (1+EMMA2RH_SW_IRQ_BASE)
40#define EMMA2RH_SW_IRQ_INT2 (2+EMMA2RH_SW_IRQ_BASE)
41#define EMMA2RH_SW_IRQ_INT3 (3+EMMA2RH_SW_IRQ_BASE)
42#define EMMA2RH_SW_IRQ_INT4 (4+EMMA2RH_SW_IRQ_BASE)
43#define EMMA2RH_SW_IRQ_INT5 (5+EMMA2RH_SW_IRQ_BASE)
44#define EMMA2RH_SW_IRQ_INT6 (6+EMMA2RH_SW_IRQ_BASE)
45#define EMMA2RH_SW_IRQ_INT7 (7+EMMA2RH_SW_IRQ_BASE)
46#define EMMA2RH_SW_IRQ_INT8 (8+EMMA2RH_SW_IRQ_BASE)
47#define EMMA2RH_SW_IRQ_INT9 (9+EMMA2RH_SW_IRQ_BASE)
48#define EMMA2RH_SW_IRQ_INT10 (10+EMMA2RH_SW_IRQ_BASE)
49#define EMMA2RH_SW_IRQ_INT11 (11+EMMA2RH_SW_IRQ_BASE)
50#define EMMA2RH_SW_IRQ_INT12 (12+EMMA2RH_SW_IRQ_BASE)
51#define EMMA2RH_SW_IRQ_INT13 (13+EMMA2RH_SW_IRQ_BASE)
52#define EMMA2RH_SW_IRQ_INT14 (14+EMMA2RH_SW_IRQ_BASE)
53#define EMMA2RH_SW_IRQ_INT15 (15+EMMA2RH_SW_IRQ_BASE)
54#define EMMA2RH_SW_IRQ_INT16 (16+EMMA2RH_SW_IRQ_BASE)
55#define EMMA2RH_SW_IRQ_INT17 (17+EMMA2RH_SW_IRQ_BASE)
56#define EMMA2RH_SW_IRQ_INT18 (18+EMMA2RH_SW_IRQ_BASE)
57#define EMMA2RH_SW_IRQ_INT19 (19+EMMA2RH_SW_IRQ_BASE)
58#define EMMA2RH_SW_IRQ_INT20 (20+EMMA2RH_SW_IRQ_BASE)
59#define EMMA2RH_SW_IRQ_INT21 (21+EMMA2RH_SW_IRQ_BASE)
60#define EMMA2RH_SW_IRQ_INT22 (22+EMMA2RH_SW_IRQ_BASE)
61#define EMMA2RH_SW_IRQ_INT23 (23+EMMA2RH_SW_IRQ_BASE)
62#define EMMA2RH_SW_IRQ_INT24 (24+EMMA2RH_SW_IRQ_BASE)
63#define EMMA2RH_SW_IRQ_INT25 (25+EMMA2RH_SW_IRQ_BASE)
64#define EMMA2RH_SW_IRQ_INT26 (26+EMMA2RH_SW_IRQ_BASE)
65#define EMMA2RH_SW_IRQ_INT27 (27+EMMA2RH_SW_IRQ_BASE)
66#define EMMA2RH_SW_IRQ_INT28 (28+EMMA2RH_SW_IRQ_BASE)
67#define EMMA2RH_SW_IRQ_INT29 (29+EMMA2RH_SW_IRQ_BASE)
68#define EMMA2RH_SW_IRQ_INT30 (30+EMMA2RH_SW_IRQ_BASE)
69#define EMMA2RH_SW_IRQ_INT31 (31+EMMA2RH_SW_IRQ_BASE)
70
71#define MARKEINS_PCI_IRQ_INTA EMMA2RH_GPIO_IRQ_BASE+15
72#define MARKEINS_PCI_IRQ_INTB EMMA2RH_GPIO_IRQ_BASE+16
73#define MARKEINS_PCI_IRQ_INTC EMMA2RH_GPIO_IRQ_BASE+17
74#define MARKEINS_PCI_IRQ_INTD EMMA2RH_GPIO_IRQ_BASE+18
75
76#endif /* CONFIG_MARKEINS */
diff --git a/include/asm-mips/mach-emma2rh/irq.h b/include/asm-mips/mach-emma2rh/irq.h
new file mode 100644
index 000000000000..bce64244b800
--- /dev/null
+++ b/include/asm-mips/mach-emma2rh/irq.h
@@ -0,0 +1,13 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 by Ralf Baechle
7 */
8#ifndef __ASM_MACH_EMMA2RH_IRQ_H
9#define __ASM_MACH_EMMA2RH_IRQ_H
10
11#define NR_IRQS 256
12
13#endif /* __ASM_MACH_EMMA2RH_IRQ_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 22:47:00 -0500