[PATCH] pciehp: Fix programming hotplug parameters

Current PCHEHP driver doesn't have any code to program hotplug
parameters from firmware. So hotplug parameters are never programed at
hot-add time. This patch add support for programming hotplug
parameters to PCIEHP driver.

Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Cc: Kristen Accardi <kristen.c.accardi@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

1 files changed, 139 insertions, 2 deletions

diff --git a/drivers/pci/hotplug/pciehp_pci.c b/drivers/pci/hotplug/pciehp_pci.c
index 4017fb03a0b8..6aa6a1be4555 100644
--- a/drivers/pci/hotplug/pciehp_pci.c
+++ b/drivers/pci/hotplug/pciehp_pci.c
@@ -34,6 +34,144 @@
 #include "../pci.h"
 #include "pciehp.h"
 
+static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
+{
+        u16 pci_cmd, pci_bctl;
+
+        if (hpp->revision > 1) {
+                printk(KERN_WARNING "%s: Rev.%d type0 record not supported\n",
+                       __FUNCTION__, hpp->revision);
+                return;
+        }
+
+        pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
+        pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
+        pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
+        if (hpp->enable_serr)
+                pci_cmd |= PCI_COMMAND_SERR;
+        else
+                pci_cmd &= ~PCI_COMMAND_SERR;
+        if (hpp->enable_perr)
+                pci_cmd |= PCI_COMMAND_PARITY;
+        else
+                pci_cmd &= ~PCI_COMMAND_PARITY;
+        pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
+
+        /* Program bridge control value */
+        if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
+                pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
+                                      hpp->latency_timer);
+                pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
+                if (hpp->enable_serr)
+                        pci_bctl |= PCI_BRIDGE_CTL_SERR;
+                else
+                        pci_bctl &= ~PCI_BRIDGE_CTL_SERR;
+                if (hpp->enable_perr)
+                        pci_bctl |= PCI_BRIDGE_CTL_PARITY;
+                else
+                        pci_bctl &= ~PCI_BRIDGE_CTL_PARITY;
+                pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
+        }
+}
+
+static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
+{
+        int pos;
+        u16 reg16;
+        u32 reg32;
+
+        if (hpp->revision > 1) {
+                printk(KERN_WARNING "%s: Rev.%d type2 record not supported\n",
+                       __FUNCTION__, hpp->revision);
+                return;
+        }
+
+        /* Find PCI Express capability */
+        pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
+        if (!pos)
+                return;
+
+        /* Initialize Device Control Register */
+        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &reg16);
+        reg16 = (reg16 & hpp->pci_exp_devctl_and) | hpp->pci_exp_devctl_or;
+        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, reg16);
+
+        /* Initialize Link Control Register */
+        if (dev->subordinate) {
+                pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &reg16);
+                reg16 = (reg16 & hpp->pci_exp_lnkctl_and)
+                        | hpp->pci_exp_lnkctl_or;
+                pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, reg16);
+        }
+
+        /* Find Advanced Error Reporting Enhanced Capability */
+        pos = 256;
+        do {
+                pci_read_config_dword(dev, pos, &reg32);
+                if (PCI_EXT_CAP_ID(reg32) == PCI_EXT_CAP_ID_ERR)
+                        break;
+        } while ((pos = PCI_EXT_CAP_NEXT(reg32)));
+        if (!pos)
+                return;
+
+        /* Initialize Uncorrectable Error Mask Register */
+        pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32);
+        reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
+        pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
+
+        /* Initialize Uncorrectable Error Severity Register */
+        pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32);
+        reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
+        pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
+
+        /* Initialize Correctable Error Mask Register */
+        pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32);
+        reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
+        pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
+
+        /* Initialize Advanced Error Capabilities and Control Register */
+        pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
+        reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
+        pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
+
+        /*
+         * FIXME: The following two registers are not supported yet.
+         *
+         *   o Secondary Uncorrectable Error Severity Register
+         *   o Secondary Uncorrectable Error Mask Register
+         */
+}
+
+static void program_fw_provided_values(struct pci_dev *dev)
+{
+        struct pci_dev *cdev;
+        struct hotplug_params hpp;
+
+        /* Program hpp values for this device */
+        if (!(dev->hdr_type == PCI_HEADER_TYPE_NORMAL ||
+                        (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
+                        (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)))
+                return;
+
+        if (pciehp_get_hp_params_from_firmware(dev, &hpp)) {
+                printk(KERN_WARNING "%s: Could not get hotplug parameters\n",
+                       __FUNCTION__);
+                return;
+        }
+
+        if (hpp.t2)
+                program_hpp_type2(dev, hpp.t2);
+        if (hpp.t0)
+                program_hpp_type0(dev, hpp.t0);
+
+        /* Program child devices */
+        if (dev->subordinate) {
+                list_for_each_entry(cdev, &dev->subordinate->devices,
+                                    bus_list)
+                        program_fw_provided_values(cdev);
+        }
+}
+
 static int pciehp_add_bridge(struct pci_dev *dev)
 {
         struct pci_bus *parent = dev->bus;
@@ -92,8 +230,7 @@ int pciehp_configure_device(struct slot *p_slot)
                                 (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)) {
                         pciehp_add_bridge(dev);
                 }
-                /* TBD: program firmware provided _HPP values */
-                /* program_fw_provided_values(dev); */
+                program_fw_provided_values(dev);
         }
 
         pci_bus_assign_resources(parent);