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authorMatt Carlson <mcarlson@broadcom.com>2009-08-28 08:29:16 -0400
committerDavid S. Miller <davem@davemloft.net>2009-08-29 18:42:33 -0400
commit8590a603e5e20ccf49d6cf0ea71ecf5388d1f9da (patch)
treefe9c1f335c96afa70da75ee64bd33ffe4f210c07
parent2befdcea96fcd9a13e94373c66ea1dd7365d2a74 (diff)
tg3: Reformat NVRAM case statements
This patch fixes up the NVRAM detection switch statements to conform to the kernel coding style. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/tg3.c369
1 files changed, 183 insertions, 186 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index d43b30b80f1e..4c4d164a4b44 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -10302,8 +10302,7 @@ static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10302 nvcfg1 = tr32(NVRAM_CFG1); 10302 nvcfg1 = tr32(NVRAM_CFG1);
10303 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) { 10303 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10304 tp->tg3_flags2 |= TG3_FLG2_FLASH; 10304 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10305 } 10305 } else {
10306 else {
10307 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; 10306 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10308 tw32(NVRAM_CFG1, nvcfg1); 10307 tw32(NVRAM_CFG1, nvcfg1);
10309 } 10308 }
@@ -10311,37 +10310,36 @@ static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10311 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) || 10310 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10312 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { 10311 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10313 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { 10312 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10314 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: 10313 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10315 tp->nvram_jedecnum = JEDEC_ATMEL; 10314 tp->nvram_jedecnum = JEDEC_ATMEL;
10316 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; 10315 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10317 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 10316 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10318 break; 10317 break;
10319 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED: 10318 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10320 tp->nvram_jedecnum = JEDEC_ATMEL; 10319 tp->nvram_jedecnum = JEDEC_ATMEL;
10321 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; 10320 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10322 break; 10321 break;
10323 case FLASH_VENDOR_ATMEL_EEPROM: 10322 case FLASH_VENDOR_ATMEL_EEPROM:
10324 tp->nvram_jedecnum = JEDEC_ATMEL; 10323 tp->nvram_jedecnum = JEDEC_ATMEL;
10325 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; 10324 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10326 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 10325 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10327 break; 10326 break;
10328 case FLASH_VENDOR_ST: 10327 case FLASH_VENDOR_ST:
10329 tp->nvram_jedecnum = JEDEC_ST; 10328 tp->nvram_jedecnum = JEDEC_ST;
10330 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; 10329 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10331 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 10330 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10332 break; 10331 break;
10333 case FLASH_VENDOR_SAIFUN: 10332 case FLASH_VENDOR_SAIFUN:
10334 tp->nvram_jedecnum = JEDEC_SAIFUN; 10333 tp->nvram_jedecnum = JEDEC_SAIFUN;
10335 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; 10334 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10336 break; 10335 break;
10337 case FLASH_VENDOR_SST_SMALL: 10336 case FLASH_VENDOR_SST_SMALL:
10338 case FLASH_VENDOR_SST_LARGE: 10337 case FLASH_VENDOR_SST_LARGE:
10339 tp->nvram_jedecnum = JEDEC_SST; 10338 tp->nvram_jedecnum = JEDEC_SST;
10340 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; 10339 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10341 break; 10340 break;
10342 } 10341 }
10343 } 10342 } else {
10344 else {
10345 tp->nvram_jedecnum = JEDEC_ATMEL; 10343 tp->nvram_jedecnum = JEDEC_ATMEL;
10346 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; 10344 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10347 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 10345 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
@@ -10359,48 +10357,47 @@ static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10359 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM; 10357 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10360 10358
10361 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { 10359 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10362 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: 10360 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10363 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ: 10361 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10364 tp->nvram_jedecnum = JEDEC_ATMEL; 10362 tp->nvram_jedecnum = JEDEC_ATMEL;
10365 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 10363 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10366 break; 10364 break;
10367 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: 10365 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10368 tp->nvram_jedecnum = JEDEC_ATMEL; 10366 tp->nvram_jedecnum = JEDEC_ATMEL;
10369 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 10367 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10370 tp->tg3_flags2 |= TG3_FLG2_FLASH; 10368 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10371 break; 10369 break;
10372 case FLASH_5752VENDOR_ST_M45PE10: 10370 case FLASH_5752VENDOR_ST_M45PE10:
10373 case FLASH_5752VENDOR_ST_M45PE20: 10371 case FLASH_5752VENDOR_ST_M45PE20:
10374 case FLASH_5752VENDOR_ST_M45PE40: 10372 case FLASH_5752VENDOR_ST_M45PE40:
10375 tp->nvram_jedecnum = JEDEC_ST; 10373 tp->nvram_jedecnum = JEDEC_ST;
10376 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 10374 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10377 tp->tg3_flags2 |= TG3_FLG2_FLASH; 10375 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10378 break; 10376 break;
10379 } 10377 }
10380 10378
10381 if (tp->tg3_flags2 & TG3_FLG2_FLASH) { 10379 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10382 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) { 10380 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10383 case FLASH_5752PAGE_SIZE_256: 10381 case FLASH_5752PAGE_SIZE_256:
10384 tp->nvram_pagesize = 256; 10382 tp->nvram_pagesize = 256;
10385 break; 10383 break;
10386 case FLASH_5752PAGE_SIZE_512: 10384 case FLASH_5752PAGE_SIZE_512:
10387 tp->nvram_pagesize = 512; 10385 tp->nvram_pagesize = 512;
10388 break; 10386 break;
10389 case FLASH_5752PAGE_SIZE_1K: 10387 case FLASH_5752PAGE_SIZE_1K:
10390 tp->nvram_pagesize = 1024; 10388 tp->nvram_pagesize = 1024;
10391 break; 10389 break;
10392 case FLASH_5752PAGE_SIZE_2K: 10390 case FLASH_5752PAGE_SIZE_2K:
10393 tp->nvram_pagesize = 2048; 10391 tp->nvram_pagesize = 2048;
10394 break; 10392 break;
10395 case FLASH_5752PAGE_SIZE_4K: 10393 case FLASH_5752PAGE_SIZE_4K:
10396 tp->nvram_pagesize = 4096; 10394 tp->nvram_pagesize = 4096;
10397 break; 10395 break;
10398 case FLASH_5752PAGE_SIZE_264: 10396 case FLASH_5752PAGE_SIZE_264:
10399 tp->nvram_pagesize = 264; 10397 tp->nvram_pagesize = 264;
10400 break; 10398 break;
10401 } 10399 }
10402 } 10400 } else {
10403 else {
10404 /* For eeprom, set pagesize to maximum eeprom size */ 10401 /* For eeprom, set pagesize to maximum eeprom size */
10405 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; 10402 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10406 10403
@@ -10423,45 +10420,45 @@ static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10423 10420
10424 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; 10421 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10425 switch (nvcfg1) { 10422 switch (nvcfg1) {
10426 case FLASH_5755VENDOR_ATMEL_FLASH_1: 10423 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10427 case FLASH_5755VENDOR_ATMEL_FLASH_2: 10424 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10428 case FLASH_5755VENDOR_ATMEL_FLASH_3: 10425 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10429 case FLASH_5755VENDOR_ATMEL_FLASH_5: 10426 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10430 tp->nvram_jedecnum = JEDEC_ATMEL; 10427 tp->nvram_jedecnum = JEDEC_ATMEL;
10431 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 10428 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10432 tp->tg3_flags2 |= TG3_FLG2_FLASH; 10429 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10433 tp->nvram_pagesize = 264; 10430 tp->nvram_pagesize = 264;
10434 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 || 10431 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10435 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5) 10432 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10436 tp->nvram_size = (protect ? 0x3e200 : 10433 tp->nvram_size = (protect ? 0x3e200 :
10437 TG3_NVRAM_SIZE_512KB); 10434 TG3_NVRAM_SIZE_512KB);
10438 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2) 10435 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10439 tp->nvram_size = (protect ? 0x1f200 : 10436 tp->nvram_size = (protect ? 0x1f200 :
10440 TG3_NVRAM_SIZE_256KB); 10437 TG3_NVRAM_SIZE_256KB);
10441 else 10438 else
10442 tp->nvram_size = (protect ? 0x1f200 : 10439 tp->nvram_size = (protect ? 0x1f200 :
10443 TG3_NVRAM_SIZE_128KB); 10440 TG3_NVRAM_SIZE_128KB);
10444 break; 10441 break;
10445 case FLASH_5752VENDOR_ST_M45PE10: 10442 case FLASH_5752VENDOR_ST_M45PE10:
10446 case FLASH_5752VENDOR_ST_M45PE20: 10443 case FLASH_5752VENDOR_ST_M45PE20:
10447 case FLASH_5752VENDOR_ST_M45PE40: 10444 case FLASH_5752VENDOR_ST_M45PE40:
10448 tp->nvram_jedecnum = JEDEC_ST; 10445 tp->nvram_jedecnum = JEDEC_ST;
10449 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 10446 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10450 tp->tg3_flags2 |= TG3_FLG2_FLASH; 10447 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10451 tp->nvram_pagesize = 256; 10448 tp->nvram_pagesize = 256;
10452 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10) 10449 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10453 tp->nvram_size = (protect ? 10450 tp->nvram_size = (protect ?
10454 TG3_NVRAM_SIZE_64KB : 10451 TG3_NVRAM_SIZE_64KB :
10455 TG3_NVRAM_SIZE_128KB); 10452 TG3_NVRAM_SIZE_128KB);
10456 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20) 10453 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10457 tp->nvram_size = (protect ? 10454 tp->nvram_size = (protect ?
10458 TG3_NVRAM_SIZE_64KB : 10455 TG3_NVRAM_SIZE_64KB :
10459 TG3_NVRAM_SIZE_256KB); 10456 TG3_NVRAM_SIZE_256KB);
10460 else 10457 else
10461 tp->nvram_size = (protect ? 10458 tp->nvram_size = (protect ?
10462 TG3_NVRAM_SIZE_128KB : 10459 TG3_NVRAM_SIZE_128KB :
10463 TG3_NVRAM_SIZE_512KB); 10460 TG3_NVRAM_SIZE_512KB);
10464 break; 10461 break;
10465 } 10462 }
10466} 10463}
10467 10464
@@ -10472,34 +10469,34 @@ static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10472 nvcfg1 = tr32(NVRAM_CFG1); 10469 nvcfg1 = tr32(NVRAM_CFG1);
10473 10470
10474 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { 10471 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10475 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ: 10472 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10476 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: 10473 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10477 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ: 10474 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10478 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: 10475 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10479 tp->nvram_jedecnum = JEDEC_ATMEL; 10476 tp->nvram_jedecnum = JEDEC_ATMEL;
10480 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 10477 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10481 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; 10478 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10482 10479
10483 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; 10480 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10484 tw32(NVRAM_CFG1, nvcfg1); 10481 tw32(NVRAM_CFG1, nvcfg1);
10485 break; 10482 break;
10486 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: 10483 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10487 case FLASH_5755VENDOR_ATMEL_FLASH_1: 10484 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10488 case FLASH_5755VENDOR_ATMEL_FLASH_2: 10485 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10489 case FLASH_5755VENDOR_ATMEL_FLASH_3: 10486 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10490 tp->nvram_jedecnum = JEDEC_ATMEL; 10487 tp->nvram_jedecnum = JEDEC_ATMEL;
10491 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 10488 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10492 tp->tg3_flags2 |= TG3_FLG2_FLASH; 10489 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10493 tp->nvram_pagesize = 264; 10490 tp->nvram_pagesize = 264;
10494 break; 10491 break;
10495 case FLASH_5752VENDOR_ST_M45PE10: 10492 case FLASH_5752VENDOR_ST_M45PE10:
10496 case FLASH_5752VENDOR_ST_M45PE20: 10493 case FLASH_5752VENDOR_ST_M45PE20:
10497 case FLASH_5752VENDOR_ST_M45PE40: 10494 case FLASH_5752VENDOR_ST_M45PE40:
10498 tp->nvram_jedecnum = JEDEC_ST; 10495 tp->nvram_jedecnum = JEDEC_ST;
10499 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 10496 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10500 tp->tg3_flags2 |= TG3_FLG2_FLASH; 10497 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10501 tp->nvram_pagesize = 256; 10498 tp->nvram_pagesize = 256;
10502 break; 10499 break;
10503 } 10500 }
10504} 10501}
10505 10502
@@ -10517,63 +10514,63 @@ static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10517 10514
10518 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; 10515 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10519 switch (nvcfg1) { 10516 switch (nvcfg1) {
10520 case FLASH_5761VENDOR_ATMEL_ADB021D: 10517 case FLASH_5761VENDOR_ATMEL_ADB021D:
10521 case FLASH_5761VENDOR_ATMEL_ADB041D: 10518 case FLASH_5761VENDOR_ATMEL_ADB041D:
10522 case FLASH_5761VENDOR_ATMEL_ADB081D: 10519 case FLASH_5761VENDOR_ATMEL_ADB081D:
10523 case FLASH_5761VENDOR_ATMEL_ADB161D: 10520 case FLASH_5761VENDOR_ATMEL_ADB161D:
10524 case FLASH_5761VENDOR_ATMEL_MDB021D: 10521 case FLASH_5761VENDOR_ATMEL_MDB021D:
10525 case FLASH_5761VENDOR_ATMEL_MDB041D: 10522 case FLASH_5761VENDOR_ATMEL_MDB041D:
10526 case FLASH_5761VENDOR_ATMEL_MDB081D: 10523 case FLASH_5761VENDOR_ATMEL_MDB081D:
10527 case FLASH_5761VENDOR_ATMEL_MDB161D: 10524 case FLASH_5761VENDOR_ATMEL_MDB161D:
10528 tp->nvram_jedecnum = JEDEC_ATMEL; 10525 tp->nvram_jedecnum = JEDEC_ATMEL;
10529 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 10526 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10530 tp->tg3_flags2 |= TG3_FLG2_FLASH; 10527 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10531 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; 10528 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10532 tp->nvram_pagesize = 256; 10529 tp->nvram_pagesize = 256;
10533 break; 10530 break;
10534 case FLASH_5761VENDOR_ST_A_M45PE20: 10531 case FLASH_5761VENDOR_ST_A_M45PE20:
10535 case FLASH_5761VENDOR_ST_A_M45PE40: 10532 case FLASH_5761VENDOR_ST_A_M45PE40:
10536 case FLASH_5761VENDOR_ST_A_M45PE80: 10533 case FLASH_5761VENDOR_ST_A_M45PE80:
10537 case FLASH_5761VENDOR_ST_A_M45PE16: 10534 case FLASH_5761VENDOR_ST_A_M45PE16:
10538 case FLASH_5761VENDOR_ST_M_M45PE20: 10535 case FLASH_5761VENDOR_ST_M_M45PE20:
10539 case FLASH_5761VENDOR_ST_M_M45PE40: 10536 case FLASH_5761VENDOR_ST_M_M45PE40:
10540 case FLASH_5761VENDOR_ST_M_M45PE80: 10537 case FLASH_5761VENDOR_ST_M_M45PE80:
10541 case FLASH_5761VENDOR_ST_M_M45PE16: 10538 case FLASH_5761VENDOR_ST_M_M45PE16:
10542 tp->nvram_jedecnum = JEDEC_ST; 10539 tp->nvram_jedecnum = JEDEC_ST;
10543 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 10540 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10544 tp->tg3_flags2 |= TG3_FLG2_FLASH; 10541 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10545 tp->nvram_pagesize = 256; 10542 tp->nvram_pagesize = 256;
10546 break; 10543 break;
10547 } 10544 }
10548 10545
10549 if (protect) { 10546 if (protect) {
10550 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); 10547 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10551 } else { 10548 } else {
10552 switch (nvcfg1) { 10549 switch (nvcfg1) {
10553 case FLASH_5761VENDOR_ATMEL_ADB161D: 10550 case FLASH_5761VENDOR_ATMEL_ADB161D:
10554 case FLASH_5761VENDOR_ATMEL_MDB161D: 10551 case FLASH_5761VENDOR_ATMEL_MDB161D:
10555 case FLASH_5761VENDOR_ST_A_M45PE16: 10552 case FLASH_5761VENDOR_ST_A_M45PE16:
10556 case FLASH_5761VENDOR_ST_M_M45PE16: 10553 case FLASH_5761VENDOR_ST_M_M45PE16:
10557 tp->nvram_size = TG3_NVRAM_SIZE_2MB; 10554 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10558 break; 10555 break;
10559 case FLASH_5761VENDOR_ATMEL_ADB081D: 10556 case FLASH_5761VENDOR_ATMEL_ADB081D:
10560 case FLASH_5761VENDOR_ATMEL_MDB081D: 10557 case FLASH_5761VENDOR_ATMEL_MDB081D:
10561 case FLASH_5761VENDOR_ST_A_M45PE80: 10558 case FLASH_5761VENDOR_ST_A_M45PE80:
10562 case FLASH_5761VENDOR_ST_M_M45PE80: 10559 case FLASH_5761VENDOR_ST_M_M45PE80:
10563 tp->nvram_size = TG3_NVRAM_SIZE_1MB; 10560 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10564 break; 10561 break;
10565 case FLASH_5761VENDOR_ATMEL_ADB041D: 10562 case FLASH_5761VENDOR_ATMEL_ADB041D:
10566 case FLASH_5761VENDOR_ATMEL_MDB041D: 10563 case FLASH_5761VENDOR_ATMEL_MDB041D:
10567 case FLASH_5761VENDOR_ST_A_M45PE40: 10564 case FLASH_5761VENDOR_ST_A_M45PE40:
10568 case FLASH_5761VENDOR_ST_M_M45PE40: 10565 case FLASH_5761VENDOR_ST_M_M45PE40:
10569 tp->nvram_size = TG3_NVRAM_SIZE_512KB; 10566 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10570 break; 10567 break;
10571 case FLASH_5761VENDOR_ATMEL_ADB021D: 10568 case FLASH_5761VENDOR_ATMEL_ADB021D:
10572 case FLASH_5761VENDOR_ATMEL_MDB021D: 10569 case FLASH_5761VENDOR_ATMEL_MDB021D:
10573 case FLASH_5761VENDOR_ST_A_M45PE20: 10570 case FLASH_5761VENDOR_ST_A_M45PE20:
10574 case FLASH_5761VENDOR_ST_M_M45PE20: 10571 case FLASH_5761VENDOR_ST_M_M45PE20:
10575 tp->nvram_size = TG3_NVRAM_SIZE_256KB; 10572 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10576 break; 10573 break;
10577 } 10574 }
10578 } 10575 }
10579} 10576}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 01:59:49 -0500