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authorshemminger@osdl.org <shemminger@osdl.org>2005-11-30 14:45:21 -0500
committerJeff Garzik <jgarzik@pobox.com>2005-12-01 02:20:21 -0500
commitaf4ed7e6ba0cba388cf691f3a330089bd46e4d9e (patch)
treeec4da6f110bf391d6a3796629661c7e2a38c99e1
parent65497dacd8104004f5115dcb2dfe1bf697154ce9 (diff)
[PATCH] sky2: remove pci-express hacks
Eliminate special case tuning for PCI-Express. This code causes receive hangs and doesn't help performance much anyway. Signed-off-by: Stephen Hemminger <shemmnger@osdl.org> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
-rw-r--r--drivers/net/sky2.c22
-rw-r--r--drivers/net/sky2.h2
2 files changed, 6 insertions, 18 deletions
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index 52c7b1886314..c6c3275fc5ed 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -651,12 +651,12 @@ static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
651} 651}
652 652
653/* Setup Bus Memory Interface */ 653/* Setup Bus Memory Interface */
654static void sky2_qset(struct sky2_hw *hw, u16 q, u32 wm) 654static void sky2_qset(struct sky2_hw *hw, u16 q)
655{ 655{
656 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); 656 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
657 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); 657 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
658 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); 658 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
659 sky2_write32(hw, Q_ADDR(q, Q_WM), wm); 659 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
660} 660}
661 661
662/* Setup prefetch unit registers. This is the interface between 662/* Setup prefetch unit registers. This is the interface between
@@ -921,7 +921,7 @@ static int sky2_rx_start(struct sky2_port *sky2)
921 int i; 921 int i;
922 922
923 sky2->rx_put = sky2->rx_next = 0; 923 sky2->rx_put = sky2->rx_next = 0;
924 sky2_qset(hw, rxq, is_pciex(hw) ? 0x80 : 0x600); 924 sky2_qset(hw, rxq);
925 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); 925 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
926 926
927 rx_set_checksum(sky2); 927 rx_set_checksum(sky2);
@@ -1004,7 +1004,7 @@ static int sky2_up(struct net_device *dev)
1004 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), 1004 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1005 RB_RST_SET); 1005 RB_RST_SET);
1006 1006
1007 sky2_qset(hw, txqaddr[port], 0x600); 1007 sky2_qset(hw, txqaddr[port]);
1008 if (hw->chip_id == CHIP_ID_YUKON_EC_U) 1008 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
1009 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0); 1009 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1010 1010
@@ -2148,20 +2148,6 @@ static int sky2_reset(struct sky2_hw *hw)
2148 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); 2148 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2149 } 2149 }
2150 2150
2151 if (is_pciex(hw)) {
2152 u16 pctrl;
2153
2154 /* change Max. Read Request Size to 2048 bytes */
2155 pci_read_config_word(hw->pdev, PEX_DEV_CTRL, &pctrl);
2156 pctrl &= ~PEX_DC_MAX_RRS_MSK;
2157 pctrl |= PEX_DC_MAX_RD_RQ_SIZE(4);
2158
2159
2160 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2161 pci_write_config_word(hw->pdev, PEX_DEV_CTRL, pctrl);
2162 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2163 }
2164
2165 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK); 2151 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2166 2152
2167 spin_lock_bh(&hw->phy_lock); 2153 spin_lock_bh(&hw->phy_lock);
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index 420454a44724..930680f50fca 100644
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -631,6 +631,8 @@ enum {
631 BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR, 631 BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR,
632 BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START | 632 BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START |
633 BMU_FIFO_ENA | BMU_OP_ON, 633 BMU_FIFO_ENA | BMU_OP_ON,
634
635 BMU_WM_DEFAULT = 0x600,
634}; 636};
635 637
636/* Tx BMU Control / Status Registers (Yukon-2) */ 638/* Tx BMU Control / Status Registers (Yukon-2) */