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authorAndy Walls <awalls@radix.net>2008-10-25 22:27:06 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2008-11-11 05:11:24 -0500
commitf3a3e881b81ae33b786759c7042de974c1e0bbf7 (patch)
tree95550ab8f4a12e0562084801da1d6e6a761079d3
parent8182ff69f8675fc1847a399be4eea5e8118a8dd3 (diff)
V4L/DVB (9475): cx18: Disable write retries for registers that always change - part 1.
cx18: Disable write retries for registers that always change - part 1. Interrupt related registers will likely not read back the value we just wrote. Disable retries for these registers for now to avoid accidently discarding interrupts. More intelligent read back verification criteria are needed for these and other registers (e.g. GPIO line registers), which will be addressed in subsequent changes. Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
-rw-r--r--drivers/media/video/cx18/cx18-io.c4
-rw-r--r--drivers/media/video/cx18/cx18-irq.c6
-rw-r--r--drivers/media/video/cx18/cx18-mailbox.c4
3 files changed, 7 insertions, 7 deletions
diff --git a/drivers/media/video/cx18/cx18-io.c b/drivers/media/video/cx18/cx18-io.c
index 700ab9439c16..31be5e8684dc 100644
--- a/drivers/media/video/cx18/cx18-io.c
+++ b/drivers/media/video/cx18/cx18-io.c
@@ -218,7 +218,7 @@ void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count)
218void cx18_sw1_irq_enable(struct cx18 *cx, u32 val) 218void cx18_sw1_irq_enable(struct cx18 *cx, u32 val)
219{ 219{
220 u32 r; 220 u32 r;
221 cx18_write_reg(cx, val, SW1_INT_STATUS); 221 cx18_write_reg_noretry(cx, val, SW1_INT_STATUS);
222 r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI); 222 r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI);
223 cx18_write_reg(cx, r | val, SW1_INT_ENABLE_PCI); 223 cx18_write_reg(cx, r | val, SW1_INT_ENABLE_PCI);
224} 224}
@@ -233,7 +233,7 @@ void cx18_sw1_irq_disable(struct cx18 *cx, u32 val)
233void cx18_sw2_irq_enable(struct cx18 *cx, u32 val) 233void cx18_sw2_irq_enable(struct cx18 *cx, u32 val)
234{ 234{
235 u32 r; 235 u32 r;
236 cx18_write_reg(cx, val, SW2_INT_STATUS); 236 cx18_write_reg_noretry(cx, val, SW2_INT_STATUS);
237 r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI); 237 r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI);
238 cx18_write_reg(cx, r | val, SW2_INT_ENABLE_PCI); 238 cx18_write_reg(cx, r | val, SW2_INT_ENABLE_PCI);
239} 239}
diff --git a/drivers/media/video/cx18/cx18-irq.c b/drivers/media/video/cx18/cx18-irq.c
index 360330f5463f..447fc9c391ac 100644
--- a/drivers/media/video/cx18/cx18-irq.c
+++ b/drivers/media/video/cx18/cx18-irq.c
@@ -149,9 +149,9 @@ irqreturn_t cx18_irq_handler(int irq, void *dev_id)
149 sw1_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU; 149 sw1_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU;
150 sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & sw1_mask; 150 sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & sw1_mask;
151 151
152 cx18_write_reg(cx, sw2&sw2_mask, SW2_INT_STATUS); 152 cx18_write_reg_noretry(cx, sw2&sw2_mask, SW2_INT_STATUS);
153 cx18_write_reg(cx, sw1&sw1_mask, SW1_INT_STATUS); 153 cx18_write_reg_noretry(cx, sw1&sw1_mask, SW1_INT_STATUS);
154 cx18_write_reg(cx, hw2&hw2_mask, HW2_INT_CLR_STATUS); 154 cx18_write_reg_noretry(cx, hw2&hw2_mask, HW2_INT_CLR_STATUS);
155 155
156 if (sw1 || sw2 || hw2) 156 if (sw1 || sw2 || hw2)
157 CX18_DEBUG_HI_IRQ("SW1: %x SW2: %x HW2: %x\n", sw1, sw2, hw2); 157 CX18_DEBUG_HI_IRQ("SW1: %x SW2: %x HW2: %x\n", sw1, sw2, hw2);
diff --git a/drivers/media/video/cx18/cx18-mailbox.c b/drivers/media/video/cx18/cx18-mailbox.c
index 9d18dd22de76..87f7c8e2c181 100644
--- a/drivers/media/video/cx18/cx18-mailbox.c
+++ b/drivers/media/video/cx18/cx18-mailbox.c
@@ -176,7 +176,7 @@ long cx18_mb_ack(struct cx18 *cx, const struct cx18_mailbox *mb)
176 176
177 cx18_setup_page(cx, SCB_OFFSET); 177 cx18_setup_page(cx, SCB_OFFSET);
178 cx18_write_sync(cx, mb->request, &ack_mb->ack); 178 cx18_write_sync(cx, mb->request, &ack_mb->ack);
179 cx18_write_reg(cx, ack_irq, SW2_INT_SET); 179 cx18_write_reg_noretry(cx, ack_irq, SW2_INT_SET);
180 return 0; 180 return 0;
181} 181}
182 182
@@ -225,7 +225,7 @@ static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
225 } 225 }
226 if (info->flags & API_FAST) 226 if (info->flags & API_FAST)
227 timeout /= 2; 227 timeout /= 2;
228 cx18_write_reg(cx, irq, SW1_INT_SET); 228 cx18_write_reg_noretry(cx, irq, SW1_INT_SET);
229 229
230 while (!sig && cx18_readl(cx, &mb->ack) != cx18_readl(cx, &mb->request) 230 while (!sig && cx18_readl(cx, &mb->ack) != cx18_readl(cx, &mb->request)
231 && cnt < 660) { 231 && cnt < 660) {