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authorRalf Baechle <ralf@linux-mips.org>2005-10-29 14:32:40 -0400
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:32:40 -0400
commitbeb3ca82fc0c2ec938b7446b006c8f34abb301b2 (patch)
treeea89c648dbeae35bdbe9734b2138ecdebdb55fe1
parent4ee1303a787434d4994ae68d028ca025e339b434 (diff)
More configcheck fixes.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_psc.h2
-rw-r--r--include/asm-mips/mmzone.h1
-rw-r--r--include/asm-mips/spinlock.h5
3 files changed, 5 insertions, 3 deletions
diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/include/asm-mips/mach-au1x00/au1xxx_psc.h
index 283519dfdec4..8e5fb3c7da4d 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_psc.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_psc.h
@@ -33,6 +33,8 @@
33#ifndef _AU1000_PSC_H_ 33#ifndef _AU1000_PSC_H_
34#define _AU1000_PSC_H_ 34#define _AU1000_PSC_H_
35 35
36#include <linux/config.h>
37
36/* The PSC base addresses. */ 38/* The PSC base addresses. */
37#ifdef CONFIG_SOC_AU1550 39#ifdef CONFIG_SOC_AU1550
38#define PSC0_BASE_ADDR 0xb1a00000 40#define PSC0_BASE_ADDR 0xb1a00000
diff --git a/include/asm-mips/mmzone.h b/include/asm-mips/mmzone.h
index d721143dbd47..011caebac369 100644
--- a/include/asm-mips/mmzone.h
+++ b/include/asm-mips/mmzone.h
@@ -5,6 +5,7 @@
5#ifndef _ASM_MMZONE_H_ 5#ifndef _ASM_MMZONE_H_
6#define _ASM_MMZONE_H_ 6#define _ASM_MMZONE_H_
7 7
8#include <linux/config.h>
8#include <asm/page.h> 9#include <asm/page.h>
9#include <mmzone.h> 10#include <mmzone.h>
10 11
diff --git a/include/asm-mips/spinlock.h b/include/asm-mips/spinlock.h
index 7d1cc75a1cbb..669b8e349ff2 100644
--- a/include/asm-mips/spinlock.h
+++ b/include/asm-mips/spinlock.h
@@ -9,17 +9,16 @@
9#ifndef _ASM_SPINLOCK_H 9#ifndef _ASM_SPINLOCK_H
10#define _ASM_SPINLOCK_H 10#define _ASM_SPINLOCK_H
11 11
12#include <linux/config.h>
13#include <asm/war.h> 12#include <asm/war.h>
14 13
15/* 14/*
16 * Your basic SMP spinlocks, allowing only a single CPU anywhere 15 * Your basic SMP spinlocks, allowing only a single CPU anywhere
17 */ 16 */
18 17
19#define __raw_spin_is_locked(x) ((x)->lock != 0) 18#define __raw_spin_is_locked(x) ((x)->lock != 0)
20#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock) 19#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
21#define __raw_spin_unlock_wait(x) \ 20#define __raw_spin_unlock_wait(x) \
22 do { cpu_relax(); } while ((x)->lock) 21 do { cpu_relax(); } while ((x)->lock)
23 22
24/* 23/*
25 * Simple spin lock operations. There are two variants, one clears IRQ's 24 * Simple spin lock operations. There are two variants, one clears IRQ's