diff options
| author | Rafał Miłecki <zajec5@gmail.com> | 2010-03-31 16:54:19 -0400 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2010-04-26 13:51:09 -0400 |
| commit | 5af55428858a45d94893fd6124d60988e89c0d59 (patch) | |
| tree | 91345a57d6470f75e129391abd887c8eda9ea868 | |
| parent | 0a182fd88f8180b342f753f04c7d5507b5891c96 (diff) | |
ssb: Fix order of definitions and some text space indents
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
| -rw-r--r-- | include/linux/ssb/ssb_regs.h | 58 |
1 files changed, 29 insertions, 29 deletions
diff --git a/include/linux/ssb/ssb_regs.h b/include/linux/ssb/ssb_regs.h index 8990e30c657a..a6d5225b9275 100644 --- a/include/linux/ssb/ssb_regs.h +++ b/include/linux/ssb/ssb_regs.h | |||
| @@ -245,7 +245,6 @@ | |||
| 245 | #define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */ | 245 | #define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */ |
| 246 | 246 | ||
| 247 | /* SPROM Revision 3 (inherits most data from rev 2) */ | 247 | /* SPROM Revision 3 (inherits most data from rev 2) */ |
| 248 | #define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */ | ||
| 249 | #define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */ | 248 | #define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */ |
| 250 | #define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */ | 249 | #define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */ |
| 251 | #define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */ | 250 | #define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */ |
| @@ -254,6 +253,7 @@ | |||
| 254 | #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8 | 253 | #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8 |
| 255 | #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */ | 254 | #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */ |
| 256 | #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16 | 255 | #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16 |
| 256 | #define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */ | ||
| 257 | #define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */ | 257 | #define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */ |
| 258 | #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */ | 258 | #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */ |
| 259 | #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */ | 259 | #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */ |
| @@ -265,20 +265,29 @@ | |||
| 265 | #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */ | 265 | #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */ |
| 266 | 266 | ||
| 267 | /* SPROM Revision 4 */ | 267 | /* SPROM Revision 4 */ |
| 268 | #define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */ | ||
| 269 | #define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */ | ||
| 268 | #define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */ | 270 | #define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */ |
| 271 | #define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */ | ||
| 272 | #define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */ | ||
| 273 | #define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */ | ||
| 274 | #define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */ | ||
| 275 | #define SSB_SPROM4_GPIOA_P1_SHIFT 8 | ||
| 276 | #define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */ | ||
| 277 | #define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */ | ||
| 278 | #define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */ | ||
| 279 | #define SSB_SPROM4_GPIOB_P3_SHIFT 8 | ||
| 269 | #define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */ | 280 | #define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */ |
| 270 | #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */ | 281 | #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */ |
| 271 | #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */ | 282 | #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */ |
| 272 | #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5 | 283 | #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5 |
| 273 | #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */ | 284 | #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */ |
| 274 | #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */ | 285 | #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */ |
| 275 | #define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */ | ||
| 276 | #define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */ | 286 | #define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */ |
| 277 | #define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */ | 287 | #define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */ |
| 278 | #define SSB_SPROM4_ANTAVAIL_A_SHIFT 0 | 288 | #define SSB_SPROM4_ANTAVAIL_A_SHIFT 0 |
| 279 | #define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */ | 289 | #define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */ |
| 280 | #define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8 | 290 | #define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8 |
| 281 | #define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */ | ||
| 282 | #define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */ | 291 | #define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */ |
| 283 | #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */ | 292 | #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */ |
| 284 | #define SSB_SPROM4_AGAIN0_SHIFT 0 | 293 | #define SSB_SPROM4_AGAIN0_SHIFT 0 |
| @@ -289,7 +298,6 @@ | |||
| 289 | #define SSB_SPROM4_AGAIN2_SHIFT 0 | 298 | #define SSB_SPROM4_AGAIN2_SHIFT 0 |
| 290 | #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */ | 299 | #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */ |
| 291 | #define SSB_SPROM4_AGAIN3_SHIFT 8 | 300 | #define SSB_SPROM4_AGAIN3_SHIFT 8 |
| 292 | #define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */ | ||
| 293 | #define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */ | 301 | #define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */ |
| 294 | #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */ | 302 | #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */ |
| 295 | #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ | 303 | #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ |
| @@ -298,14 +306,6 @@ | |||
| 298 | #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */ | 306 | #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */ |
| 299 | #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */ | 307 | #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */ |
| 300 | #define SSB_SPROM4_ITSSI_A_SHIFT 8 | 308 | #define SSB_SPROM4_ITSSI_A_SHIFT 8 |
| 301 | #define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */ | ||
| 302 | #define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */ | ||
| 303 | #define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */ | ||
| 304 | #define SSB_SPROM4_GPIOA_P1_SHIFT 8 | ||
| 305 | #define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */ | ||
| 306 | #define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */ | ||
| 307 | #define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */ | ||
| 308 | #define SSB_SPROM4_GPIOB_P3_SHIFT 8 | ||
| 309 | #define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */ | 309 | #define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */ |
| 310 | #define SSB_SPROM4_PA0B1 0x0084 /* only guesses */ | 310 | #define SSB_SPROM4_PA0B1 0x0084 /* only guesses */ |
| 311 | #define SSB_SPROM4_PA0B2 0x0086 | 311 | #define SSB_SPROM4_PA0B2 0x0086 |
| @@ -314,10 +314,10 @@ | |||
| 314 | #define SSB_SPROM4_PA1B2 0x0092 | 314 | #define SSB_SPROM4_PA1B2 0x0092 |
| 315 | 315 | ||
| 316 | /* SPROM Revision 5 (inherits most data from rev 4) */ | 316 | /* SPROM Revision 5 (inherits most data from rev 4) */ |
| 317 | #define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */ | ||
| 317 | #define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */ | 318 | #define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */ |
| 318 | #define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */ | 319 | #define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */ |
| 319 | #define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */ | 320 | #define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */ |
| 320 | #define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */ | ||
| 321 | #define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */ | 321 | #define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */ |
| 322 | #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */ | 322 | #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */ |
| 323 | #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */ | 323 | #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */ |
| @@ -335,11 +335,19 @@ | |||
| 335 | #define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */ | 335 | #define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */ |
| 336 | #define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */ | 336 | #define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */ |
| 337 | #define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */ | 337 | #define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */ |
| 338 | #define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */ | ||
| 339 | #define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */ | ||
| 340 | #define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */ | ||
| 341 | #define SSB_SPROM8_GPIOA_P1_SHIFT 8 | ||
| 342 | #define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */ | ||
| 343 | #define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */ | ||
| 344 | #define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */ | ||
| 345 | #define SSB_SPROM8_GPIOB_P3_SHIFT 8 | ||
| 338 | #define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/ | 346 | #define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/ |
| 339 | #define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */ | 347 | #define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */ |
| 340 | #define SSB_SPROM8_ANTAVAIL_A_SHIFT 8 | 348 | #define SSB_SPROM8_ANTAVAIL_A_SHIFT 8 |
| 341 | #define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */ | 349 | #define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */ |
| 342 | #define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0 | 350 | #define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0 |
| 343 | #define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */ | 351 | #define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */ |
| 344 | #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */ | 352 | #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */ |
| 345 | #define SSB_SPROM8_AGAIN0_SHIFT 0 | 353 | #define SSB_SPROM8_AGAIN0_SHIFT 0 |
| @@ -350,14 +358,6 @@ | |||
| 350 | #define SSB_SPROM8_AGAIN2_SHIFT 0 | 358 | #define SSB_SPROM8_AGAIN2_SHIFT 0 |
| 351 | #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */ | 359 | #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */ |
| 352 | #define SSB_SPROM8_AGAIN3_SHIFT 8 | 360 | #define SSB_SPROM8_AGAIN3_SHIFT 8 |
| 353 | #define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */ | ||
| 354 | #define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */ | ||
| 355 | #define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */ | ||
| 356 | #define SSB_SPROM8_GPIOA_P1_SHIFT 8 | ||
| 357 | #define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */ | ||
| 358 | #define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */ | ||
| 359 | #define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */ | ||
| 360 | #define SSB_SPROM8_GPIOB_P3_SHIFT 8 | ||
| 361 | #define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */ | 361 | #define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */ |
| 362 | #define SSB_SPROM8_RSSISMF2G 0x000F | 362 | #define SSB_SPROM8_RSSISMF2G 0x000F |
| 363 | #define SSB_SPROM8_RSSISMC2G 0x00F0 | 363 | #define SSB_SPROM8_RSSISMC2G 0x00F0 |