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authorGuennadi Liakhovetski <g.liakhovetski@gmx.de>2007-05-04 16:59:40 -0400
committerJames Bottomley <jejb@mulgrave.il.steeleye.com>2007-05-06 10:33:21 -0400
commit46e5ba2b644d1c7be1253ec32e7cd6ab1dcdf790 (patch)
tree2004e75a362b31fd710c57153337995484a5a1c4
parent860bfecf71495fc2b82c878958c97b0b6b601626 (diff)
[SCSI] tmscsim: remove bogus endianness conversions
cpu_to_le32 endianness conversions in tmscsim.c, followed by arithmetic operations don't look correct. Besides, {in,out}[wl] already perform the necessary conversions. Further, bus addresses of request buffers are guaranteed to be (mapped) under 4G by current scsi- and block-layer defaults. This could be explicitly enforced by using blk_queue_bounce_limit(), which, however, doesn't seem to be the common practice among SCSI drivers. Signed-off-by: G. Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
-rw-r--r--drivers/scsi/tmscsim.c27
-rw-r--r--drivers/scsi/tmscsim.h12
2 files changed, 17 insertions, 22 deletions
diff --git a/drivers/scsi/tmscsim.c b/drivers/scsi/tmscsim.c
index bc0a007eb893..12d8fea3de93 100644
--- a/drivers/scsi/tmscsim.c
+++ b/drivers/scsi/tmscsim.c
@@ -778,8 +778,8 @@ dc390_DataOut_0( struct dc390_acb* pACB, struct dc390_srb* pSRB, u8 *psstatus)
778 pSRB->pSegmentList++; 778 pSRB->pSegmentList++;
779 psgl = pSRB->pSegmentList; 779 psgl = pSRB->pSegmentList;
780 780
781 pSRB->SGBusAddr = cpu_to_le32(pci_dma_lo32(sg_dma_address(psgl))); 781 pSRB->SGBusAddr = sg_dma_address(psgl);
782 pSRB->SGToBeXferLen = cpu_to_le32(sg_dma_len(psgl)); 782 pSRB->SGToBeXferLen = sg_dma_len(psgl);
783 } 783 }
784 else 784 else
785 pSRB->SGToBeXferLen = 0; 785 pSRB->SGToBeXferLen = 0;
@@ -842,7 +842,7 @@ dc390_DataIn_0( struct dc390_acb* pACB, struct dc390_srb* pSRB, u8 *psstatus)
842 DEBUG1(ResidCnt = ((unsigned long) DC390_read8 (CtcReg_High) << 16) \ 842 DEBUG1(ResidCnt = ((unsigned long) DC390_read8 (CtcReg_High) << 16) \
843 + ((unsigned long) DC390_read8 (CtcReg_Mid) << 8) \ 843 + ((unsigned long) DC390_read8 (CtcReg_Mid) << 8) \
844 + ((unsigned long) DC390_read8 (CtcReg_Low))); 844 + ((unsigned long) DC390_read8 (CtcReg_Low)));
845 DEBUG1(printk (KERN_DEBUG "Count_2_Zero (ResidCnt=%i,ToBeXfer=%li),", ResidCnt, pSRB->SGToBeXferLen)); 845 DEBUG1(printk (KERN_DEBUG "Count_2_Zero (ResidCnt=%u,ToBeXfer=%lu),", ResidCnt, pSRB->SGToBeXferLen));
846 846
847 DC390_write8 (DMA_Cmd, READ_DIRECTION+DMA_IDLE_CMD); 847 DC390_write8 (DMA_Cmd, READ_DIRECTION+DMA_IDLE_CMD);
848 848
@@ -853,8 +853,8 @@ dc390_DataIn_0( struct dc390_acb* pACB, struct dc390_srb* pSRB, u8 *psstatus)
853 pSRB->pSegmentList++; 853 pSRB->pSegmentList++;
854 psgl = pSRB->pSegmentList; 854 psgl = pSRB->pSegmentList;
855 855
856 pSRB->SGBusAddr = cpu_to_le32(pci_dma_lo32(sg_dma_address(psgl))); 856 pSRB->SGBusAddr = sg_dma_address(psgl);
857 pSRB->SGToBeXferLen = cpu_to_le32(sg_dma_len(psgl)); 857 pSRB->SGToBeXferLen = sg_dma_len(psgl);
858 } 858 }
859 else 859 else
860 pSRB->SGToBeXferLen = 0; 860 pSRB->SGToBeXferLen = 0;
@@ -921,11 +921,12 @@ din_1:
921 921
922 ptr = (u8 *) bus_to_virt( pSRB->SGBusAddr ); 922 ptr = (u8 *) bus_to_virt( pSRB->SGBusAddr );
923 *ptr = bval; 923 *ptr = bval;
924 pSRB->SGBusAddr++; xferCnt++; 924 pSRB->SGBusAddr++;
925 xferCnt++;
925 pSRB->TotalXferredLen++; 926 pSRB->TotalXferredLen++;
926 pSRB->SGToBeXferLen--; 927 pSRB->SGToBeXferLen--;
927 } 928 }
928 DEBUG1(printk (KERN_DEBUG "Xfered: %li, Total: %li, Remaining: %li\n", xferCnt,\ 929 DEBUG1(printk (KERN_DEBUG "Xfered: %lu, Total: %lu, Remaining: %lu\n", xferCnt,\
929 pSRB->TotalXferredLen, pSRB->SGToBeXferLen)); 930 pSRB->TotalXferredLen, pSRB->SGToBeXferLen));
930 931
931 } 932 }
@@ -1157,14 +1158,14 @@ dc390_restore_ptr (struct dc390_acb* pACB, struct dc390_srb* pSRB)
1157 { 1158 {
1158 pSRB->pSegmentList++; 1159 pSRB->pSegmentList++;
1159 psgl = pSRB->pSegmentList; 1160 psgl = pSRB->pSegmentList;
1160 pSRB->SGBusAddr = cpu_to_le32(pci_dma_lo32(sg_dma_address(psgl))); 1161 pSRB->SGBusAddr = sg_dma_address(psgl);
1161 pSRB->SGToBeXferLen = cpu_to_le32(sg_dma_len(psgl)); 1162 pSRB->SGToBeXferLen = sg_dma_len(psgl);
1162 } 1163 }
1163 else 1164 else
1164 pSRB->SGToBeXferLen = 0; 1165 pSRB->SGToBeXferLen = 0;
1165 } 1166 }
1166 pSRB->SGToBeXferLen -= (pSRB->Saved_Ptr - pSRB->TotalXferredLen); 1167 pSRB->SGToBeXferLen -= pSRB->Saved_Ptr - pSRB->TotalXferredLen;
1167 pSRB->SGBusAddr += (pSRB->Saved_Ptr - pSRB->TotalXferredLen); 1168 pSRB->SGBusAddr += pSRB->Saved_Ptr - pSRB->TotalXferredLen;
1168 printk (KERN_INFO "DC390: Pointer restored. Segment %i, Total %li, Bus %08lx\n", 1169 printk (KERN_INFO "DC390: Pointer restored. Segment %i, Total %li, Bus %08lx\n",
1169 pSRB->SGIndex, pSRB->Saved_Ptr, pSRB->SGBusAddr); 1170 pSRB->SGIndex, pSRB->Saved_Ptr, pSRB->SGBusAddr);
1170 1171
@@ -1315,8 +1316,8 @@ dc390_DataIO_Comm( struct dc390_acb* pACB, struct dc390_srb* pSRB, u8 ioDir)
1315 if( !pSRB->SGToBeXferLen ) 1316 if( !pSRB->SGToBeXferLen )
1316 { 1317 {
1317 psgl = pSRB->pSegmentList; 1318 psgl = pSRB->pSegmentList;
1318 pSRB->SGBusAddr = cpu_to_le32(pci_dma_lo32(sg_dma_address(psgl))); 1319 pSRB->SGBusAddr = sg_dma_address(psgl);
1319 pSRB->SGToBeXferLen = cpu_to_le32(sg_dma_len(psgl)); 1320 pSRB->SGToBeXferLen = sg_dma_len(psgl);
1320 DEBUG1(printk (KERN_DEBUG " DC390: Next SG segment.")); 1321 DEBUG1(printk (KERN_DEBUG " DC390: Next SG segment."));
1321 } 1322 }
1322 lval = pSRB->SGToBeXferLen; 1323 lval = pSRB->SGToBeXferLen;
diff --git a/drivers/scsi/tmscsim.h b/drivers/scsi/tmscsim.h
index 9b66fa8d38d9..c3d8c80cfb38 100644
--- a/drivers/scsi/tmscsim.h
+++ b/drivers/scsi/tmscsim.h
@@ -19,14 +19,6 @@
19 19
20#define SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40 MHz) */ 20#define SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40 MHz) */
21 21
22#define pci_dma_lo32(a) (a & 0xffffffff)
23
24typedef u8 UCHAR; /* 8 bits */
25typedef u16 USHORT; /* 16 bits */
26typedef u32 UINT; /* 32 bits */
27typedef unsigned long ULONG; /* 32/64 bits */
28
29
30/* 22/*
31;----------------------------------------------------------------------- 23;-----------------------------------------------------------------------
32; SCSI Request Block 24; SCSI Request Block
@@ -43,7 +35,9 @@ struct scatterlist *pSegmentList;
43 35
44struct scatterlist Segmentx; /* make a one entry of S/G list table */ 36struct scatterlist Segmentx; /* make a one entry of S/G list table */
45 37
46unsigned long SGBusAddr; /*;a segment starting address as seen by AM53C974A*/ 38unsigned long SGBusAddr; /*;a segment starting address as seen by AM53C974A
39 in CPU endianness. We're only getting 32-bit bus
40 addresses by default */
47unsigned long SGToBeXferLen; /*; to be xfer length */ 41unsigned long SGToBeXferLen; /*; to be xfer length */
48unsigned long TotalXferredLen; 42unsigned long TotalXferredLen;
49unsigned long SavedTotXLen; 43unsigned long SavedTotXLen;