Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] Export except_vec_vi_{mori,lui,ori} as text symbols.
  [MIPS] mips-boards: More liberal check for mips-board console
  [MIPS] Misc fixes for plat_irq_dispatch functions
  [MIPS] Qemu: Fix Symmetric Uniprocessor support.
  [MIPS] VI: TRACE_IRQS_OFF clobbers $v0, so save & restore around call.

17 files changed, 49 insertions, 24 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 5f29018a6533..656f0ca52782 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -542,6 +542,8 @@ config QEMU
         select SYS_SUPPORTS_LITTLE_ENDIAN
         select ARCH_SPARSEMEM_ENABLE
         select GENERIC_HARDIRQS_NO__DO_IRQ
+        select NR_CPUS_DEFAULT_1
+        select SYS_SUPPORTS_SMP
         help
           Qemu is a software emulator which among other architectures also
           can simulate a MIPS32 4Kc system.  This patch adds support for the
@@ -1805,6 +1807,9 @@ config SMP
 config SYS_SUPPORTS_SMP
         bool
 
+config NR_CPUS_DEFAULT_1
+        bool
+
 config NR_CPUS_DEFAULT_2
         bool
 
@@ -1825,8 +1830,9 @@ config NR_CPUS_DEFAULT_64
 
 config NR_CPUS
         int "Maximum number of CPUs (2-64)"
-        range 2 64
+        range 1 64 if NR_CPUS_DEFAULT_1
         depends on SMP
+        default "1" if NR_CPUS_DEFAULT_1
         default "2" if NR_CPUS_DEFAULT_2
         default "4" if NR_CPUS_DEFAULT_4
         default "8" if NR_CPUS_DEFAULT_8
@@ -1837,10 +1843,13 @@ config NR_CPUS
           This allows you to specify the maximum number of CPUs which this
           kernel will support.  The maximum supported value is 32 for 32-bit
           kernel and 64 for 64-bit kernels; the minimum value which makes
-          sense is 2.
+          sense is 1 for Qemu (useful only for kernel debugging purposes)
+          and 2 for all others.
 
           This is purely to save memory - each supported CPU adds
-          approximately eight kilobytes to the kernel image.
+          approximately eight kilobytes to the kernel image.  For best
+          performance should round up your number of processors to the next
+          power of two.
 
 #
 # Timer Interrupt Frequency Configuration
diff --git a/arch/mips/ddb5xxx/ddb5477/irq.c b/arch/mips/ddb5xxx/ddb5477/irq.c
index 2b23234a5b95..faa4a506bf82 100644
--- a/arch/mips/ddb5xxx/ddb5477/irq.c
+++ b/arch/mips/ddb5xxx/ddb5477/irq.c
@@ -194,7 +194,7 @@ static void vrc5477_irq_dispatch(void)
 
 asmlinkage void plat_irq_dispatch(void)
 {
-        unsigned int pending = read_c0_cause() & read_c0_status();
+        unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
 
         if (pending & STATUSF_IP7)
                 do_IRQ(CPU_IRQ_BASE + 7);
diff --git a/arch/mips/emma2rh/markeins/irq.c b/arch/mips/emma2rh/markeins/irq.c
index e26630026375..6bcf6a06367a 100644
--- a/arch/mips/emma2rh/markeins/irq.c
+++ b/arch/mips/emma2rh/markeins/irq.c
@@ -115,7 +115,7 @@ void __init arch_init_irq(void)
 
 asmlinkage void plat_irq_dispatch(void)
 {
-        unsigned int pending = read_c0_status() & read_c0_cause();
+        unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 
         if (pending & STATUSF_IP7)
                 do_IRQ(CPU_IRQ_BASE + 7);
diff --git a/arch/mips/gt64120/ev64120/irq.c b/arch/mips/gt64120/ev64120/irq.c
index 04572b9c9642..64e4c80b6139 100644
--- a/arch/mips/gt64120/ev64120/irq.c
+++ b/arch/mips/gt64120/ev64120/irq.c
@@ -48,7 +48,7 @@
 
 asmlinkage void plat_irq_dispatch(void)
 {
-        unsigned int pending = read_c0_status() & read_c0_cause();
+        unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 
         if (pending & STATUSF_IP4)              /* int2 hardware line (timer) */
                 do_IRQ(4);
diff --git a/arch/mips/gt64120/wrppmc/irq.c b/arch/mips/gt64120/wrppmc/irq.c
index d3d96591780e..06177bf5b1d6 100644
--- a/arch/mips/gt64120/wrppmc/irq.c
+++ b/arch/mips/gt64120/wrppmc/irq.c
@@ -32,7 +32,7 @@
 
 asmlinkage void plat_irq_dispatch(void)
 {
-        unsigned int pending = read_c0_status() & read_c0_cause();
+        unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 
         if (pending & STATUSF_IP7)
                 do_IRQ(WRPPMC_MIPS_TIMER_IRQ);  /* CPU Compare/Count internal timer */
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index 295892e4ce53..015cf4bb51dd 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -122,7 +122,7 @@ static void ll_local_dev(void)
 
 asmlinkage void plat_irq_dispatch(void)
 {
-        unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
+        unsigned int pending = read_c0_cause() & read_c0_status();
 
         if (pending & IE_IRQ5)
                 write_c0_compare(0);
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index aacd4a005c5f..83843a229be7 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -181,13 +181,13 @@ NESTED(except_vec_vi, 0, sp)
          * during service by SMTC kernel, we also want to
          * pass the IM value to be cleared.
          */
-EXPORT(except_vec_vi_mori)
+FEXPORT(except_vec_vi_mori)
         ori     a0, $0, 0
 #endif /* CONFIG_MIPS_MT_SMTC */
-EXPORT(except_vec_vi_lui)
+FEXPORT(except_vec_vi_lui)
         lui     v0, 0           /* Patched */
         j       except_vec_vi_handler
-EXPORT(except_vec_vi_ori)
+FEXPORT(except_vec_vi_ori)
          ori    v0, 0           /* Patched */
         .set    pop
         END(except_vec_vi)
@@ -220,7 +220,17 @@ NESTED(except_vec_vi_handler, 0, sp)
         _ehb
 #endif /* CONFIG_MIPS_MT_SMTC */
         CLI
+#ifdef CONFIG_TRACE_IRQFLAGS
+        move    s0, v0
+#ifdef CONFIG_MIPS_MT_SMTC
+        move    s1, a0
+#endif
         TRACE_IRQS_OFF
+#ifdef CONFIG_MIPS_MT_SMTC
+        move    a0, s1
+#endif
+        move    v0, s0
+#endif
 
         LONG_L  s0, TI_REGS($28)
         LONG_S  sp, TI_REGS($28)
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c
index 1acdf091c258..88e9c2a7a2f9 100644
--- a/arch/mips/mips-boards/generic/init.c
+++ b/arch/mips/mips-boards/generic/init.c
@@ -145,7 +145,7 @@ static void __init console_config(void)
         char parity = '\0', bits = '\0', flow = '\0';
         char *s;
 
-        if ((strstr(prom_getcmdline(), "console=ttyS")) == NULL) {
+        if ((strstr(prom_getcmdline(), "console=")) == NULL) {
                 s = prom_getenv("modetty0");
                 if (s) {
                         while (*s >= '0' && *s <= '9')
diff --git a/arch/mips/momentum/ocelot_c/irq.c b/arch/mips/momentum/ocelot_c/irq.c
index 40472f7944d7..844d566c9de3 100644
--- a/arch/mips/momentum/ocelot_c/irq.c
+++ b/arch/mips/momentum/ocelot_c/irq.c
@@ -64,7 +64,7 @@ extern void ll_cpci_irq(void);
 
 asmlinkage void plat_irq_dispatch(void)
 {
-        unsigned int pending = read_c0_cause() & read_c0_status();
+        unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
 
         if (pending & STATUSF_IP0)
                 do_IRQ(0);
diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c
index b1c4805a0b92..aad03429a5e3 100644
--- a/arch/mips/philips/pnx8550/common/int.c
+++ b/arch/mips/philips/pnx8550/common/int.c
@@ -83,16 +83,15 @@ static void timer_irqdispatch(int irq)
 
 asmlinkage void plat_irq_dispatch(void)
 {
-        unsigned int pending = read_c0_status() & read_c0_cause();
+        unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 
         if (pending & STATUSF_IP2)
                 hw0_irqdispatch(2);
         else if (pending & STATUSF_IP7) {
                 if (read_c0_config7() & 0x01c0)
                         timer_irqdispatch(7);
-        }
-
-        spurious_interrupt();
+        } else
+                spurious_interrupt();
 }
 
 static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask)
diff --git a/arch/mips/qemu/q-smp.c b/arch/mips/qemu/q-smp.c
index 5a12354cd576..786bbfa214d1 100644
--- a/arch/mips/qemu/q-smp.c
+++ b/arch/mips/qemu/q-smp.c
@@ -46,3 +46,10 @@ void __init prom_prepare_cpus(unsigned int max_cpus)
 void prom_boot_secondary(int cpu, struct task_struct *idle)
 {
 }
+
+void __init plat_smp_setup(void)
+{
+}
+void __init plat_prepare_cpus(unsigned int max_cpus)
+{
+}
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index b454924aeb56..18348321795d 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -237,7 +237,7 @@ extern void indy_8254timer_irq(void);
 
 asmlinkage void plat_irq_dispatch(void)
 {
-        unsigned int pending = read_c0_cause();
+        unsigned int pending = read_c0_status() & read_c0_cause();
 
         /*
          * First we check for r4k counter/timer IRQ.
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index 8c450d9e8696..fb9da9acf53f 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -454,7 +454,7 @@ static void ip32_irq5(void)
 
 asmlinkage void plat_irq_dispatch(void)
 {
-        unsigned int pending = read_c0_cause();
+        unsigned int pending = read_c0_status() & read_c0_cause();
 
         if (likely(pending & IE_IRQ0))
                 ip32_irq0();
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 148239446e6e..0e6a13c0bd0e 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -421,7 +421,7 @@ asmlinkage void plat_irq_dispatch(void)
          * blasting the high 32 bits.
          */
 
-        pending = read_c0_cause() & read_c0_status();
+        pending = read_c0_cause() & read_c0_status() & ST0_IM;
 
 #ifdef CONFIG_SIBYTE_SB1250_PROF
         if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */
diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c
index 39e5b4abc555..8e8593b64f6a 100644
--- a/arch/mips/sni/pcimt.c
+++ b/arch/mips/sni/pcimt.c
@@ -333,7 +333,7 @@ static void pcimt_hwint3(void)
 
 static void sni_pcimt_hwint(void)
 {
-        u32 pending = (read_c0_cause() & read_c0_status());
+        u32 pending = read_c0_cause() & read_c0_status();
 
         if (pending & C_IRQ5)
                 do_IRQ (MIPS_CPU_IRQ_BASE + 7);
diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c
index 8d6b3d5b13a1..1dfc3f00bbd3 100644
--- a/arch/mips/sni/pcit.c
+++ b/arch/mips/sni/pcit.c
@@ -271,7 +271,7 @@ static void pcit_hwint0(void)
 
 static void sni_pcit_hwint(void)
 {
-        u32 pending = (read_c0_cause() & read_c0_status());
+        u32 pending = read_c0_cause() & read_c0_status();
 
         if (pending & C_IRQ1)
                 pcit_hwint1();
@@ -285,7 +285,7 @@ static void sni_pcit_hwint(void)
 
 static void sni_pcit_hwint_cplus(void)
 {
-        u32 pending = (read_c0_cause() & read_c0_status());
+        u32 pending = read_c0_cause() & read_c0_status();
 
         if (pending & C_IRQ0)
                 pcit_hwint0();
diff --git a/arch/mips/tx4927/common/tx4927_irq.c b/arch/mips/tx4927/common/tx4927_irq.c
index e7f3e5b84dcf..3d25d010f3d5 100644
--- a/arch/mips/tx4927/common/tx4927_irq.c
+++ b/arch/mips/tx4927/common/tx4927_irq.c
@@ -416,7 +416,7 @@ static int tx4927_irq_nested(void)
 
 asmlinkage void plat_irq_dispatch(void)
 {
-        unsigned int pending = read_c0_status() & read_c0_cause();
+        unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 
         if (pending & STATUSF_IP7)                      /* cpu timer */
                 do_IRQ(TX4927_IRQ_CPU_TIMER);