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authorRichard Purdie <rpurdie@rpsys.net>2006-10-06 12:36:39 -0400
committerJaroslav Kysela <perex@suse.cz>2007-02-09 03:00:22 -0500
commitabadfc928a27e1cf27c834e8e29e6b1f64ca2d55 (patch)
tree3d98573969684978fd783a260bbb084057ed0603
parent40e0aa64660b4e28a9348e57bfbda6c114617969 (diff)
[ALSA] ASoC codecs: WM8750 support
This patch adds ASoC support for the WM8750 codec. Supported features:- o Capture/Playback/Sidetone/Bypass. o 16 & 24 bit audio. o 8k - 96k sample rates. o DAPM. Signed-off-by: Richard Purdie <rpurdie@rpsys.net> Signed-off-by: Liam Girdwood <liam.girdwood@wolfsonmicro.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@suse.cz>
Diffstat
-rw-r--r--include/linux/i2c-id.h1
-rw-r--r--sound/soc/codecs/wm8750.c1131
-rw-r--r--sound/soc/codecs/wm8750.h66
3 files changed, 1198 insertions, 0 deletions
diff --git a/include/linux/i2c-id.h b/include/linux/i2c-id.h
index 01e98c2a9618..6e7ec4c76178 100644
--- a/include/linux/i2c-id.h
+++ b/include/linux/i2c-id.h
@@ -116,6 +116,7 @@
116#define I2C_DRIVERID_TLV320AIC23B 87 /* TI TLV320AIC23B audio codec */ 116#define I2C_DRIVERID_TLV320AIC23B 87 /* TI TLV320AIC23B audio codec */
117#define I2C_DRIVERID_ISL1208 88 /* Intersil ISL1208 RTC */ 117#define I2C_DRIVERID_ISL1208 88 /* Intersil ISL1208 RTC */
118#define I2C_DRIVERID_WM8731 89 /* Wolfson WM8731 audio codec */ 118#define I2C_DRIVERID_WM8731 89 /* Wolfson WM8731 audio codec */
119#define I2C_DRIVERID_WM8750 90 /* Wolfson WM8750 audio codec */
119 120
120#define I2C_DRIVERID_I2CDEV 900 121#define I2C_DRIVERID_I2CDEV 900
121#define I2C_DRIVERID_ARP 902 /* SMBus ARP Client */ 122#define I2C_DRIVERID_ARP 902 /* SMBus ARP Client */
diff --git a/sound/soc/codecs/wm8750.c b/sound/soc/codecs/wm8750.c
new file mode 100644
index 000000000000..6a8b2799b3b1
--- /dev/null
+++ b/sound/soc/codecs/wm8750.c
@@ -0,0 +1,1131 @@
1/*
2 * wm8750.c -- WM8750 ALSA SoC audio driver
3 *
4 * Copyright 2005 Openedhand Ltd.
5 *
6 * Author: Richard Purdie <richard@openedhand.com>
7 *
8 * Based on WM8753.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/pm.h>
20#include <linux/i2c.h>
21#include <linux/platform_device.h>
22#include <sound/driver.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h>
29
30#include "wm8750.h"
31
32#define AUDIO_NAME "WM8750"
33#define WM8750_VERSION "0.11"
34
35/*
36 * Debug
37 */
38
39#define WM8750_DEBUG 0
40
41#ifdef WM8750_DEBUG
42#define dbg(format, arg...) \
43 printk(KERN_DEBUG AUDIO_NAME ": " format "\n" , ## arg)
44#else
45#define dbg(format, arg...) do {} while (0)
46#endif
47#define err(format, arg...) \
48 printk(KERN_ERR AUDIO_NAME ": " format "\n" , ## arg)
49#define info(format, arg...) \
50 printk(KERN_INFO AUDIO_NAME ": " format "\n" , ## arg)
51#define warn(format, arg...) \
52 printk(KERN_WARNING AUDIO_NAME ": " format "\n" , ## arg)
53
54static struct workqueue_struct *wm8750_workq = NULL;
55static struct work_struct wm8750_dapm_work;
56
57/*
58 * wm8750 register cache
59 * We can't read the WM8750 register space when we
60 * are using 2 wire for device control, so we cache them instead.
61 */
62static const u16 wm8750_reg[] = {
63 0x0097, 0x0097, 0x0079, 0x0079, /* 0 */
64 0x0000, 0x0008, 0x0000, 0x000a, /* 4 */
65 0x0000, 0x0000, 0x00ff, 0x00ff, /* 8 */
66 0x000f, 0x000f, 0x0000, 0x0000, /* 12 */
67 0x0000, 0x007b, 0x0000, 0x0032, /* 16 */
68 0x0000, 0x00c3, 0x00c3, 0x00c0, /* 20 */
69 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
70 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
71 0x0000, 0x0000, 0x0050, 0x0050, /* 32 */
72 0x0050, 0x0050, 0x0050, 0x0050, /* 36 */
73 0x0079, 0x0079, 0x0079, /* 40 */
74};
75
76#define WM8750_HIFI_DAIFMT \
77 (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_RIGHT_J | \
78 SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_NB_IF | SND_SOC_DAIFMT_IB_NF | \
79 SND_SOC_DAIFMT_IB_IF)
80
81#define WM8750_DIR \
82 (SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE)
83
84#define WM8750_HIFI_FSB \
85 (SND_SOC_FSBD(1) | SND_SOC_FSBD(2) | SND_SOC_FSBD(4) | \
86 SND_SOC_FSBD(8) | SND_SOC_FSBD(16))
87
88#define WM8750_HIFI_RATES \
89 (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
90 SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
91 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
92
93#define WM8750_HIFI_BITS \
94 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
95 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
96
97static struct snd_soc_dai_mode wm8750_modes[] = {
98 /* common codec frame and clock master modes */
99 /* 8k */
100 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
101 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_8000,
102 WM8750_DIR, SND_SOC_DAI_BFS_DIV, 1536, WM8750_HIFI_FSB},
103 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
104 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_8000,
105 WM8750_DIR, SND_SOC_DAI_BFS_DIV, 1408, WM8750_HIFI_FSB},
106 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
107 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_8000,
108 WM8750_DIR, SND_SOC_DAI_BFS_DIV, 2304, WM8750_HIFI_FSB},
109 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
110 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_8000,
111 WM8750_DIR, SND_SOC_DAI_BFS_DIV, 2112, WM8750_HIFI_FSB},
112 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
113 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_8000,
114 WM8750_DIR, SND_SOC_DAI_BFS_DIV, 1500, WM8750_HIFI_FSB},
115
116 /* 11.025k */
117 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
118 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_11025,
119 WM8750_DIR, SND_SOC_DAI_BFS_DIV, 1024, WM8750_HIFI_FSB},
120 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
121 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_11025,
122 WM8750_DIR, SND_SOC_DAI_BFS_DIV, 1536, WM8750_HIFI_FSB},
123 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
124 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_11025,
125 WM8750_DIR, SND_SOC_DAI_BFS_DIV, 1088, WM8750_HIFI_FSB},
126
127 /* 16k */
128 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
129 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_16000,
130 WM8750_DIR, SND_SOC_DAI_BFS_DIV, 768, WM8750_HIFI_FSB},
131 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
132 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_16000,
133 WM8750_DIR, SND_SOC_DAI_BFS_DIV, 1152, WM8750_HIFI_FSB},
134 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
135 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_16000,
136 WM8750_DIR, SND_SOC_DAI_BFS_DIV, 750, WM8750_HIFI_FSB},
137
138 /* 22.05k */
139 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
140 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_22050,
141 WM8750_DIR, SND_SOC_DAI_BFS_DIV, 512, WM8750_HIFI_FSB},
142 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
143 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_22050,
144 WM8750_DIR, SND_SOC_DAI_BFS_DIV, 768, WM8750_HIFI_FSB},
145 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
146 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_22050,
147 WM8750_DIR, SND_SOC_DAI_BFS_DIV, 544, WM8750_HIFI_FSB},
148
149 /* 32k */
150 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
151 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_16000,
152 WM8750_DIR, SND_SOC_DAI_BFS_DIV, 384, WM8750_HIFI_FSB},
153 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
154 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_16000,
155 WM8750_DIR, SND_SOC_DAI_BFS_DIV, 576, WM8750_HIFI_FSB},
156 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
157 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_16000,
158 WM8750_DIR, SND_SOC_DAI_BFS_DIV, 375, WM8750_HIFI_FSB},
159
160 /* 44.1k & 48k */
161 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
162 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_44100 |
163 SNDRV_PCM_RATE_48000, WM8750_DIR, SND_SOC_DAI_BFS_DIV, 256,
164 WM8750_HIFI_FSB},
165 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
166 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_44100 |
167 SNDRV_PCM_RATE_48000, WM8750_DIR, SND_SOC_DAI_BFS_DIV, 384,
168 WM8750_HIFI_FSB},
169 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
170 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_44100,
171 WM8750_DIR, SND_SOC_DAI_BFS_DIV, 272, WM8750_HIFI_FSB},
172 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
173 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_48000,
174 WM8750_DIR, SND_SOC_DAI_BFS_DIV, 250, WM8750_HIFI_FSB},
175
176 /* 88.2k & 96k */
177 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
178 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_88200 |
179 SNDRV_PCM_RATE_96000, WM8750_DIR, SND_SOC_DAI_BFS_DIV, 128,
180 WM8750_HIFI_FSB},
181 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
182 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_88200 |
183 SNDRV_PCM_RATE_96000, WM8750_DIR, SND_SOC_DAI_BFS_DIV, 192,
184 WM8750_HIFI_FSB},
185 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
186 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_88200,
187 WM8750_DIR, SND_SOC_DAI_BFS_DIV, 136, WM8750_HIFI_FSB},
188 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBM_CFM,
189 SND_SOC_DAITDM_LRDW(0,0), WM8750_HIFI_BITS, SNDRV_PCM_RATE_96000,
190 WM8750_DIR, SND_SOC_DAI_BFS_DIV, 125, WM8750_HIFI_FSB},
191
192 /* codec frame and clock slave modes */
193 {WM8750_HIFI_DAIFMT | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0),
194 WM8750_HIFI_BITS, WM8750_HIFI_RATES, WM8750_DIR,
195 SND_SOC_DAI_BFS_DIV, SND_SOC_FS_ALL, SND_SOC_FSBD_ALL},
196};
197
198/*
199 * read wm8750 register cache
200 */
201static inline unsigned int wm8750_read_reg_cache(struct snd_soc_codec *codec,
202 unsigned int reg)
203{
204 u16 *cache = codec->reg_cache;
205 if (reg > WM8750_CACHE_REGNUM)
206 return -1;
207 return cache[reg];
208}
209
210/*
211 * write wm8750 register cache
212 */
213static inline void wm8750_write_reg_cache(struct snd_soc_codec *codec,
214 unsigned int reg, unsigned int value)
215{
216 u16 *cache = codec->reg_cache;
217 if (reg > WM8750_CACHE_REGNUM)
218 return;
219 cache[reg] = value;
220}
221
222static int wm8750_write(struct snd_soc_codec *codec, unsigned int reg,
223 unsigned int value)
224{
225 u8 data[2];
226
227 /* data is
228 * D15..D9 WM8753 register offset
229 * D8...D0 register data
230 */
231 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
232 data[1] = value & 0x00ff;
233
234 wm8750_write_reg_cache (codec, reg, value);
235 if (codec->hw_write(codec->control_data, data, 2) == 2)
236 return 0;
237 else
238 return -EIO;
239}
240
241#define wm8750_reset(c) wm8750_write(c, WM8750_RESET, 0)
242
243/*
244 * WM8750 Controls
245 */
246static const char *wm8750_bass[] = {"Linear Control", "Adaptive Boost"};
247static const char *wm8750_bass_filter[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
248static const char *wm8750_treble[] = {"8kHz", "4kHz"};
249static const char *wm8750_3d_lc[] = {"200Hz", "500Hz"};
250static const char *wm8750_3d_uc[] = {"2.2kHz", "1.5kHz"};
251static const char *wm8750_3d_func[] = {"Capture", "Playback"};
252static const char *wm8750_alc_func[] = {"Off", "Right", "Left", "Stereo"};
253static const char *wm8750_ng_type[] = {"Constant PGA Gain",
254 "Mute ADC Output"};
255static const char *wm8750_line_mux[] = {"Line 1", "Line 2", "Line 3", "PGA",
256 "Differential"};
257static const char *wm8750_pga_sel[] = {"Line 1", "Line 2", "Line 3",
258 "Differential"};
259static const char *wm8750_out3[] = {"VREF", "ROUT1 + Vol", "MonoOut",
260 "ROUT1"};
261static const char *wm8750_diff_sel[] = {"Line 1", "Line 2"};
262static const char *wm8750_adcpol[] = {"Normal", "L Invert", "R Invert",
263 "L + R Invert"};
264static const char *wm8750_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
265static const char *wm8750_mono_mux[] = {"Stereo", "Mono (Left)",
266 "Mono (Right)", "Digital Mono"};
267
268static const struct soc_enum wm8750_enum[] = {
269SOC_ENUM_SINGLE(WM8750_BASS, 7, 2, wm8750_bass),
270SOC_ENUM_SINGLE(WM8750_BASS, 6, 2, wm8750_bass_filter),
271SOC_ENUM_SINGLE(WM8750_TREBLE, 6, 2, wm8750_treble),
272SOC_ENUM_SINGLE(WM8750_3D, 5, 2, wm8750_3d_lc),
273SOC_ENUM_SINGLE(WM8750_3D, 6, 2, wm8750_3d_uc),
274SOC_ENUM_SINGLE(WM8750_3D, 7, 2, wm8750_3d_func),
275SOC_ENUM_SINGLE(WM8750_ALC1, 7, 4, wm8750_alc_func),
276SOC_ENUM_SINGLE(WM8750_NGATE, 1, 2, wm8750_ng_type),
277SOC_ENUM_SINGLE(WM8750_LOUTM1, 0, 5, wm8750_line_mux),
278SOC_ENUM_SINGLE(WM8750_ROUTM1, 0, 5, wm8750_line_mux),
279SOC_ENUM_SINGLE(WM8750_LADCIN, 6, 4, wm8750_pga_sel), /* 10 */
280SOC_ENUM_SINGLE(WM8750_RADCIN, 6, 4, wm8750_pga_sel),
281SOC_ENUM_SINGLE(WM8750_ADCTL2, 7, 4, wm8750_out3),
282SOC_ENUM_SINGLE(WM8750_ADCIN, 8, 2, wm8750_diff_sel),
283SOC_ENUM_SINGLE(WM8750_ADCDAC, 5, 4, wm8750_adcpol),
284SOC_ENUM_SINGLE(WM8750_ADCDAC, 1, 4, wm8750_deemph),
285SOC_ENUM_SINGLE(WM8750_ADCIN, 6, 4, wm8750_mono_mux), /* 16 */
286
287};
288
289static const struct snd_kcontrol_new wm8750_snd_controls[] = {
290
291SOC_DOUBLE_R("Capture Volume", WM8750_LINVOL, WM8750_RINVOL, 0, 63, 0),
292SOC_DOUBLE_R("Capture ZC Switch", WM8750_LINVOL, WM8750_RINVOL, 6, 1, 0),
293SOC_DOUBLE_R("Capture Switch", WM8750_LINVOL, WM8750_RINVOL, 7, 1, 1),
294
295SOC_DOUBLE_R("Out1 Playback ZC Switch", WM8750_LOUT1V,
296 WM8750_ROUT1V, 7, 1, 0),
297SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8750_LOUT2V,
298 WM8750_ROUT2V, 7, 1, 0),
299
300SOC_ENUM("Playback De-emphasis", wm8750_enum[15]),
301
302SOC_ENUM("Capture Polarity", wm8750_enum[14]),
303SOC_SINGLE("Playback 6dB Attenuate", WM8750_ADCDAC, 7, 1, 0),
304SOC_SINGLE("Capture 6dB Attenuate", WM8750_ADCDAC, 8, 1, 0),
305
306SOC_DOUBLE_R("PCM Volume", WM8750_LDAC, WM8750_RDAC, 0, 255, 0),
307
308SOC_ENUM("Bass Boost", wm8750_enum[0]),
309SOC_ENUM("Bass Filter", wm8750_enum[1]),
310SOC_SINGLE("Bass Volume", WM8750_BASS, 0, 15, 1),
311
312SOC_SINGLE("Treble Volume", WM8750_TREBLE, 0, 15, 0),
313SOC_ENUM("Treble Cut-off", wm8750_enum[2]),
314
315SOC_SINGLE("3D Switch", WM8750_3D, 0, 1, 0),
316SOC_SINGLE("3D Volume", WM8750_3D, 1, 15, 0),
317SOC_ENUM("3D Lower Cut-off", wm8750_enum[3]),
318SOC_ENUM("3D Upper Cut-off", wm8750_enum[4]),
319SOC_ENUM("3D Mode", wm8750_enum[5]),
320
321SOC_SINGLE("ALC Capture Target Volume", WM8750_ALC1, 0, 7, 0),
322SOC_SINGLE("ALC Capture Max Volume", WM8750_ALC1, 4, 7, 0),
323SOC_ENUM("ALC Capture Function", wm8750_enum[6]),
324SOC_SINGLE("ALC Capture ZC Switch", WM8750_ALC2, 7, 1, 0),
325SOC_SINGLE("ALC Capture Hold Time", WM8750_ALC2, 0, 15, 0),
326SOC_SINGLE("ALC Capture Decay Time", WM8750_ALC3, 4, 15, 0),
327SOC_SINGLE("ALC Capture Attack Time", WM8750_ALC3, 0, 15, 0),
328SOC_SINGLE("ALC Capture NG Threshold", WM8750_NGATE, 3, 31, 0),
329SOC_ENUM("ALC Capture NG Type", wm8750_enum[4]),
330SOC_SINGLE("ALC Capture NG Switch", WM8750_NGATE, 0, 1, 0),
331
332SOC_SINGLE("Left ADC Capture Volume", WM8750_LADC, 0, 255, 0),
333SOC_SINGLE("Right ADC Capture Volume", WM8750_RADC, 0, 255, 0),
334
335SOC_SINGLE("ZC Timeout Switch", WM8750_ADCTL1, 0, 1, 0),
336SOC_SINGLE("Playback Invert Switch", WM8750_ADCTL1, 1, 1, 0),
337
338SOC_SINGLE("Right Out2 Playback Invert Switch", WM8750_ADCTL2, 4, 1, 0),
339
340/* Unimplemented */
341/* ADCDAC Bit 0 - ADCHPD */
342/* ADCDAC Bit 4 - HPOR */
343/* ADCTL1 Bit 2,3 - DATSEL */
344/* ADCTL1 Bit 4,5 - DMONOMIX */
345/* ADCTL1 Bit 6,7 - VSEL */
346/* ADCTL2 Bit 2 - LRCM */
347/* ADCTL2 Bit 3 - TRI */
348/* ADCTL3 Bit 5 - HPFLREN */
349/* ADCTL3 Bit 6 - VROI */
350/* ADCTL3 Bit 7,8 - ADCLRM */
351/* ADCIN Bit 4 - LDCM */
352/* ADCIN Bit 5 - RDCM */
353
354SOC_DOUBLE_R("Mic Boost", WM8750_LADCIN, WM8750_RADCIN, 4, 3, 0),
355
356SOC_DOUBLE_R("Bypass Left Playback Volume", WM8750_LOUTM1,
357 WM8750_LOUTM2, 4, 7, 1),
358SOC_DOUBLE_R("Bypass Right Playback Volume", WM8750_ROUTM1,
359 WM8750_ROUTM2, 4, 7, 1),
360SOC_DOUBLE_R("Bypass Mono Playback Volume", WM8750_MOUTM1,
361 WM8750_MOUTM2, 4, 7, 1),
362
363SOC_SINGLE("Mono Playback ZC Switch", WM8750_MOUTV, 7, 1, 0),
364
365SOC_DOUBLE_R("Out1 Playback Volume", WM8750_LOUT1V, WM8750_ROUT1V, 0, 127, 0),
366SOC_DOUBLE_R("Out2 Playback Volume", WM8750_LOUT2V, WM8750_ROUT2V, 0, 127, 0),
367
368SOC_SINGLE("Mono Playback Volume", WM8750_MOUTV, 0, 127, 0),
369
370};
371
372/* add non dapm controls */
373static int wm8750_add_controls(struct snd_soc_codec *codec)
374{
375 int err, i;
376
377 for (i = 0; i < ARRAY_SIZE(wm8750_snd_controls); i++) {
378 err = snd_ctl_add(codec->card,
379 snd_soc_cnew(&wm8750_snd_controls[i],codec, NULL));
380 if (err < 0)
381 return err;
382 }
383 return 0;
384}
385
386/*
387 * DAPM Controls
388 */
389
390/* Left Mixer */
391static const struct snd_kcontrol_new wm8750_left_mixer_controls[] = {
392SOC_DAPM_SINGLE("Playback Switch", WM8750_LOUTM1, 8, 1, 0),
393SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_LOUTM1, 7, 1, 0),
394SOC_DAPM_SINGLE("Right Playback Switch", WM8750_LOUTM2, 8, 1, 0),
395SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_LOUTM2, 7, 1, 0),
396};
397
398/* Right Mixer */
399static const struct snd_kcontrol_new wm8750_right_mixer_controls[] = {
400SOC_DAPM_SINGLE("Left Playback Switch", WM8750_ROUTM1, 8, 1, 0),
401SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_ROUTM1, 7, 1, 0),
402SOC_DAPM_SINGLE("Playback Switch", WM8750_ROUTM2, 8, 1, 0),
403SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_ROUTM2, 7, 1, 0),
404};
405
406/* Mono Mixer */
407static const struct snd_kcontrol_new wm8750_mono_mixer_controls[] = {
408SOC_DAPM_SINGLE("Left Playback Switch", WM8750_MOUTM1, 8, 1, 0),
409SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_MOUTM1, 7, 1, 0),
410SOC_DAPM_SINGLE("Right Playback Switch", WM8750_MOUTM2, 8, 1, 0),
411SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_MOUTM2, 7, 1, 0),
412};
413
414/* Left Line Mux */
415static const struct snd_kcontrol_new wm8750_left_line_controls =
416SOC_DAPM_ENUM("Route", wm8750_enum[8]);
417
418/* Right Line Mux */
419static const struct snd_kcontrol_new wm8750_right_line_controls =
420SOC_DAPM_ENUM("Route", wm8750_enum[9]);
421
422/* Left PGA Mux */
423static const struct snd_kcontrol_new wm8750_left_pga_controls =
424SOC_DAPM_ENUM("Route", wm8750_enum[10]);
425
426/* Right PGA Mux */
427static const struct snd_kcontrol_new wm8750_right_pga_controls =
428SOC_DAPM_ENUM("Route", wm8750_enum[11]);
429
430/* Out 3 Mux */
431static const struct snd_kcontrol_new wm8750_out3_controls =
432SOC_DAPM_ENUM("Route", wm8750_enum[12]);
433
434/* Differential Mux */
435static const struct snd_kcontrol_new wm8750_diffmux_controls =
436SOC_DAPM_ENUM("Route", wm8750_enum[13]);
437
438/* Mono ADC Mux */
439static const struct snd_kcontrol_new wm8750_monomux_controls =
440SOC_DAPM_ENUM("Route", wm8750_enum[16]);
441
442static const struct snd_soc_dapm_widget wm8750_dapm_widgets[] = {
443 SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
444 &wm8750_left_mixer_controls[0],
445 ARRAY_SIZE(wm8750_left_mixer_controls)),
446 SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
447 &wm8750_right_mixer_controls[0],
448 ARRAY_SIZE(wm8750_right_mixer_controls)),
449 SND_SOC_DAPM_MIXER("Mono Mixer", WM8750_PWR2, 2, 0,
450 &wm8750_mono_mixer_controls[0],
451 ARRAY_SIZE(wm8750_mono_mixer_controls)),
452
453 SND_SOC_DAPM_PGA("Right Out 2", WM8750_PWR2, 3, 0, NULL, 0),
454 SND_SOC_DAPM_PGA("Left Out 2", WM8750_PWR2, 4, 0, NULL, 0),
455 SND_SOC_DAPM_PGA("Right Out 1", WM8750_PWR2, 5, 0, NULL, 0),
456 SND_SOC_DAPM_PGA("Left Out 1", WM8750_PWR2, 6, 0, NULL, 0),
457 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8750_PWR2, 7, 0),
458 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8750_PWR2, 8, 0),
459
460 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8750_PWR1, 1, 0),
461 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8750_PWR1, 2, 0),
462 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8750_PWR1, 3, 0),
463
464 SND_SOC_DAPM_MUX("Left PGA Mux", WM8750_PWR1, 5, 0,
465 &wm8750_left_pga_controls),
466 SND_SOC_DAPM_MUX("Right PGA Mux", WM8750_PWR1, 4, 0,
467 &wm8750_right_pga_controls),
468 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
469 &wm8750_left_line_controls),
470 SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
471 &wm8750_right_line_controls),
472
473 SND_SOC_DAPM_MUX("Out3 Mux", SND_SOC_NOPM, 0, 0, &wm8750_out3_controls),
474 SND_SOC_DAPM_PGA("Out 3", WM8750_PWR2, 1, 0, NULL, 0),
475 SND_SOC_DAPM_PGA("Mono Out 1", WM8750_PWR2, 2, 0, NULL, 0),
476
477 SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
478 &wm8750_diffmux_controls),
479 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
480 &wm8750_monomux_controls),
481 SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
482 &wm8750_monomux_controls),
483
484 SND_SOC_DAPM_OUTPUT("LOUT1"),
485 SND_SOC_DAPM_OUTPUT("ROUT1"),
486 SND_SOC_DAPM_OUTPUT("LOUT2"),
487 SND_SOC_DAPM_OUTPUT("ROUT2"),
488 SND_SOC_DAPM_OUTPUT("MONO"),
489 SND_SOC_DAPM_OUTPUT("OUT3"),
490
491 SND_SOC_DAPM_INPUT("LINPUT1"),
492 SND_SOC_DAPM_INPUT("LINPUT2"),
493 SND_SOC_DAPM_INPUT("LINPUT3"),
494 SND_SOC_DAPM_INPUT("RINPUT1"),
495 SND_SOC_DAPM_INPUT("RINPUT2"),
496 SND_SOC_DAPM_INPUT("RINPUT3"),
497};
498
499static const char *audio_map[][3] = {
500 /* left mixer */
501 {"Left Mixer", "Playback Switch", "Left DAC"},
502 {"Left Mixer", "Left Bypass Switch", "Left Line Mux"},
503 {"Left Mixer", "Right Playback Switch", "Right DAC"},
504 {"Left Mixer", "Right Bypass Switch", "Right Line Mux"},
505
506 /* right mixer */
507 {"Right Mixer", "Left Playback Switch", "Left DAC"},
508 {"Right Mixer", "Left Bypass Switch", "Left Line Mux"},
509 {"Right Mixer", "Playback Switch", "Right DAC"},
510 {"Right Mixer", "Right Bypass Switch", "Right Line Mux"},
511
512 /* left out 1 */
513 {"Left Out 1", NULL, "Left Mixer"},
514 {"LOUT1", NULL, "Left Out 1"},
515
516 /* left out 2 */
517 {"Left Out 2", NULL, "Left Mixer"},
518 {"LOUT2", NULL, "Left Out 2"},
519
520 /* right out 1 */
521 {"Right Out 1", NULL, "Right Mixer"},
522 {"ROUT1", NULL, "Right Out 1"},
523
524 /* right out 2 */
525 {"Right Out 2", NULL, "Right Mixer"},
526 {"ROUT2", NULL, "Right Out 2"},
527
528 /* mono mixer */
529 {"Mono Mixer", "Left Playback Switch", "Left DAC"},
530 {"Mono Mixer", "Left Bypass Switch", "Left Line Mux"},
531 {"Mono Mixer", "Right Playback Switch", "Right DAC"},
532 {"Mono Mixer", "Right Bypass Switch", "Right Line Mux"},
533
534 /* mono out */
535 {"Mono Out 1", NULL, "Mono Mixer"},
536 {"MONO1", NULL, "Mono Out 1"},
537
538 /* out 3 */
539 {"Out3 Mux", "VREF", "VREF"},
540 {"Out3 Mux", "ROUT1 + Vol", "ROUT1"},
541 {"Out3 Mux", "ROUT1", "Right Mixer"},
542 {"Out3 Mux", "MonoOut", "MONO1"},
543 {"Out 3", NULL, "Out3 Mux"},
544 {"OUT3", NULL, "Out 3"},
545
546 /* Left Line Mux */
547 {"Left Line Mux", "Line 1", "LINPUT1"},
548 {"Left Line Mux", "Line 2", "LINPUT2"},
549 {"Left Line Mux", "Line 3", "LINPUT3"},
550 {"Left Line Mux", "PGA", "Left PGA Mux"},
551 {"Left Line Mux", "Differential", "Differential Mux"},
552
553 /* Right Line Mux */
554 {"Right Line Mux", "Line 1", "RINPUT1"},
555 {"Right Line Mux", "Line 2", "RINPUT2"},
556 {"Right Line Mux", "Line 3", "RINPUT3"},
557 {"Right Line Mux", "PGA", "Right PGA Mux"},
558 {"Right Line Mux", "Differential", "Differential Mux"},
559
560 /* Left PGA Mux */
561 {"Left PGA Mux", "Line 1", "LINPUT1"},
562 {"Left PGA Mux", "Line 2", "LINPUT2"},
563 {"Left PGA Mux", "Line 3", "LINPUT3"},
564 {"Left PGA Mux", "Differential", "Differential Mux"},
565
566 /* Right PGA Mux */
567 {"Right PGA Mux", "Line 1", "RINPUT1"},
568 {"Right PGA Mux", "Line 2", "RINPUT2"},
569 {"Right PGA Mux", "Line 3", "RINPUT3"},
570 {"Right PGA Mux", "Differential", "Differential Mux"},
571
572 /* Differential Mux */
573 {"Differential Mux", "Line 1", "LINPUT1"},
574 {"Differential Mux", "Line 1", "RINPUT1"},
575 {"Differential Mux", "Line 2", "LINPUT2"},
576 {"Differential Mux", "Line 2", "RINPUT2"},
577
578 /* Left ADC Mux */
579 {"Left ADC Mux", "Stereo", "Left PGA Mux"},
580 {"Left ADC Mux", "Mono (Left)", "Left PGA Mux"},
581 {"Left ADC Mux", "Digital Mono", "Left PGA Mux"},
582
583 /* Right ADC Mux */
584 {"Right ADC Mux", "Stereo", "Right PGA Mux"},
585 {"Right ADC Mux", "Mono (Right)", "Right PGA Mux"},
586 {"Right ADC Mux", "Digital Mono", "Right PGA Mux"},
587
588 /* ADC */
589 {"Left ADC", NULL, "Left ADC Mux"},
590 {"Right ADC", NULL, "Right ADC Mux"},
591
592 /* terminator */
593 {NULL, NULL, NULL},
594};
595
596static int wm8750_add_widgets(struct snd_soc_codec *codec)
597{
598 int i;
599
600 for(i = 0; i < ARRAY_SIZE(wm8750_dapm_widgets); i++) {
601 snd_soc_dapm_new_control(codec, &wm8750_dapm_widgets[i]);
602 }
603
604 /* set up audio path audio_mapnects */
605 for(i = 0; audio_map[i][0] != NULL; i++) {
606 snd_soc_dapm_connect_input(codec, audio_map[i][0],
607 audio_map[i][1], audio_map[i][2]);
608 }
609
610 snd_soc_dapm_new_widgets(codec);
611 return 0;
612}
613
614struct _coeff_div {
615 u32 mclk;
616 u32 rate;
617 u16 fs;
618 u8 sr:5;
619 u8 usb:1;
620};
621
622/* codec hifi mclk clock divider coefficients */
623static const struct _coeff_div coeff_div[] = {
624 /* 8k */
625 {12288000, 8000, 1536, 0x6, 0x0},
626 {11289600, 8000, 1408, 0x16, 0x0},
627 {18432000, 8000, 2304, 0x7, 0x0},
628 {16934400, 8000, 2112, 0x17, 0x0},
629 {12000000, 8000, 1500, 0x6, 0x1},
630
631 /* 11.025k */
632 {11289600, 11025, 1024, 0x18, 0x0},
633 {16934400, 11025, 1536, 0x19, 0x0},
634 {12000000, 11025, 1088, 0x19, 0x1},
635
636 /* 16k */
637 {12288000, 16000, 768, 0xa, 0x0},
638 {18432000, 16000, 1152, 0xb, 0x0},
639 {12000000, 16000, 750, 0xa, 0x1},
640
641 /* 22.05k */
642 {11289600, 22050, 512, 0x1a, 0x0},
643 {16934400, 22050, 768, 0x1b, 0x0},
644 {12000000, 22050, 544, 0x1b, 0x1},
645
646 /* 32k */
647 {12288000, 32000, 384, 0xc, 0x0},
648 {18432000, 32000, 576, 0xd, 0x0},
649 {12000000, 32000, 375, 0xa, 0x1},
650
651 /* 44.1k */
652 {11289600, 44100, 256, 0x10, 0x0},
653 {16934400, 44100, 384, 0x11, 0x0},
654 {12000000, 44100, 272, 0x11, 0x1},
655
656 /* 48k */
657 {12288000, 48000, 256, 0x0, 0x0},
658 {18432000, 48000, 384, 0x1, 0x0},
659 {12000000, 48000, 250, 0x0, 0x1},
660
661 /* 88.2k */
662 {11289600, 88200, 128, 0x1e, 0x0},
663 {16934400, 88200, 192, 0x1f, 0x0},
664 {12000000, 88200, 136, 0x1f, 0x1},
665
666 /* 96k */
667 {12288000, 96000, 128, 0xe, 0x0},
668 {18432000, 96000, 192, 0xf, 0x0},
669 {12000000, 96000, 125, 0xe, 0x1},
670};
671
672static inline int get_coeff(int mclk, int rate)
673{
674 int i;
675
676 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
677 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
678 return i;
679 }
680 return -EINVAL;
681}
682
683/* WM8750 supports numerous input clocks per sample rate */
684static unsigned int wm8750_config_sysclk(struct snd_soc_codec_dai *dai,
685 struct snd_soc_clock_info *info, unsigned int clk)
686{
687 dai->mclk = 0;
688
689 /* check that the calculated FS and rate actually match a clock from
690 * the machine driver */
691 if (info->fs * info->rate == clk)
692 dai->mclk = clk;
693
694 return dai->mclk;
695}
696
697static int wm8750_pcm_prepare(struct snd_pcm_substream *substream)
698{
699 struct snd_soc_pcm_runtime *rtd = substream->private_data;
700 struct snd_soc_device *socdev = rtd->socdev;
701 struct snd_soc_codec *codec = socdev->codec;
702 u16 iface = 0, bfs, srate = 0;
703 int i = get_coeff(rtd->codec_dai->mclk,
704 snd_soc_get_rate(rtd->codec_dai->dai_runtime.pcmrate));
705
706 /* is coefficient valid ? */
707 if (i < 0)
708 return i;
709
710 bfs = SND_SOC_FSB_REAL(rtd->codec_dai->dai_runtime.bfs);
711
712 /* set master/slave audio interface */
713 switch (rtd->codec_dai->dai_runtime.fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
714 case SND_SOC_DAIFMT_CBM_CFM:
715 iface = 0x0040;
716 break;
717 case SND_SOC_DAIFMT_CBS_CFS:
718 break;
719 }
720
721 /* interface format */
722 switch (rtd->codec_dai->dai_runtime.fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
723 case SND_SOC_DAIFMT_I2S:
724 iface |= 0x0002;
725 break;
726 case SND_SOC_DAIFMT_RIGHT_J:
727 break;
728 case SND_SOC_DAIFMT_LEFT_J:
729 iface |= 0x0001;
730 break;
731 case SND_SOC_DAIFMT_DSP_A:
732 iface |= 0x0003;
733 break;
734 case SND_SOC_DAIFMT_DSP_B:
735 iface |= 0x0013;
736 break;
737 }
738
739 /* bit size */
740 switch (rtd->codec_dai->dai_runtime.pcmfmt) {
741 case SNDRV_PCM_FMTBIT_S16_LE:
742 break;
743 case SNDRV_PCM_FMTBIT_S20_3LE:
744 iface |= 0x0004;
745 break;
746 case SNDRV_PCM_FMTBIT_S24_LE:
747 iface |= 0x0008;
748 break;
749 case SNDRV_PCM_FMTBIT_S32_LE:
750 iface |= 0x000c;
751 break;
752 }
753
754 /* clock inversion */
755 switch (rtd->codec_dai->dai_runtime.fmt & SND_SOC_DAIFMT_INV_MASK) {
756 case SND_SOC_DAIFMT_NB_NF:
757 break;
758 case SND_SOC_DAIFMT_IB_IF:
759 iface |= 0x0090;
760 break;
761 case SND_SOC_DAIFMT_IB_NF:
762 iface |= 0x0080;
763 break;
764 case SND_SOC_DAIFMT_NB_IF:
765 iface |= 0x0010;
766 break;
767 }
768
769 /* set bclk divisor rate */
770 switch (bfs) {
771 case 1:
772 break;
773 case 4:
774 srate |= (0x1 << 7);
775 break;
776 case 8:
777 srate |= (0x2 << 7);
778 break;
779 case 16:
780 srate |= (0x3 << 7);
781 break;
782 }
783
784 /* set iface & srate */
785 wm8750_write(codec, WM8750_IFACE, iface);
786 wm8750_write(codec, WM8750_SRATE, srate |
787 (coeff_div[i].sr << 1) | coeff_div[i].usb);
788
789 return 0;
790}
791
792static int wm8750_mute(struct snd_soc_codec *codec,
793 struct snd_soc_codec_dai *dai, int mute)
794{
795 u16 mute_reg = wm8750_read_reg_cache(codec, WM8750_ADCDAC) & 0xfff7;
796 if (mute)
797 wm8750_write(codec, WM8750_ADCDAC, mute_reg | 0x8);
798 else
799 wm8750_write(codec, WM8750_ADCDAC, mute_reg);
800 return 0;
801}
802
803static int wm8750_dapm_event(struct snd_soc_codec *codec, int event)
804{
805 u16 pwr_reg = wm8750_read_reg_cache(codec, WM8750_PWR1) & 0xfe3e;
806
807 switch (event) {
808 case SNDRV_CTL_POWER_D0: /* full On */
809 /* set vmid to 50k and unmute dac */
810 wm8750_write(codec, WM8750_PWR1, pwr_reg | 0x00c0);
811 break;
812 case SNDRV_CTL_POWER_D1: /* partial On */
813 case SNDRV_CTL_POWER_D2: /* partial On */
814 /* set vmid to 5k for quick power up */
815 wm8750_write(codec, WM8750_PWR1, pwr_reg | 0x01c1);
816 break;
817 case SNDRV_CTL_POWER_D3hot: /* Off, with power */
818 /* mute dac and set vmid to 500k, enable VREF */
819 wm8750_write(codec, WM8750_PWR1, pwr_reg | 0x0141);
820 break;
821 case SNDRV_CTL_POWER_D3cold: /* Off, without power */
822 wm8750_write(codec, WM8750_PWR1, 0x0001);
823 break;
824 }
825 codec->dapm_state = event;
826 return 0;
827}
828
829struct snd_soc_codec_dai wm8750_dai = {
830 .name = "WM8750",
831 .playback = {
832 .stream_name = "Playback",
833 .channels_min = 1,
834 .channels_max = 2,
835 },
836 .capture = {
837 .stream_name = "Capture",
838 .channels_min = 1,
839 .channels_max = 2,
840 },
841 .config_sysclk = wm8750_config_sysclk,
842 .digital_mute = wm8750_mute,
843 .ops = {
844 .prepare = wm8750_pcm_prepare,
845 },
846 .caps = {
847 .num_modes = ARRAY_SIZE(wm8750_modes),
848 .mode = wm8750_modes,
849 },
850};
851EXPORT_SYMBOL_GPL(wm8750_dai);
852
853static void wm8750_work(void *data)
854{
855 struct snd_soc_codec *codec = (struct snd_soc_codec *)data;
856 wm8750_dapm_event(codec, codec->dapm_state);
857}
858
859static int wm8750_suspend(struct platform_device *pdev, pm_message_t state)
860{
861 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
862 struct snd_soc_codec *codec = socdev->codec;
863
864 wm8750_dapm_event(codec, SNDRV_CTL_POWER_D3cold);
865 return 0;
866}
867
868static int wm8750_resume(struct platform_device *pdev)
869{
870 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
871 struct snd_soc_codec *codec = socdev->codec;
872 int i;
873 u8 data[2];
874 u16 *cache = codec->reg_cache;
875
876 /* Sync reg_cache with the hardware */
877 for (i = 0; i < ARRAY_SIZE(wm8750_reg); i++) {
878 if (i == WM8750_RESET)
879 continue;
880 data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
881 data[1] = cache[i] & 0x00ff;
882 codec->hw_write(codec->control_data, data, 2);
883 }
884
885 wm8750_dapm_event(codec, SNDRV_CTL_POWER_D3hot);
886
887 /* charge wm8750 caps */
888 if (codec->suspend_dapm_state == SNDRV_CTL_POWER_D0) {
889 wm8750_dapm_event(codec, SNDRV_CTL_POWER_D2);
890 codec->dapm_state = SNDRV_CTL_POWER_D0;
891 queue_delayed_work(wm8750_workq, &wm8750_dapm_work,
892 msecs_to_jiffies(1000));
893 }
894
895 return 0;
896}
897
898/*
899 * initialise the WM8750 driver
900 * register the mixer and dsp interfaces with the kernel
901 */
902static int wm8750_init(struct snd_soc_device *socdev)
903{
904 struct snd_soc_codec *codec = socdev->codec;
905 int reg, ret = 0;
906
907 codec->name = "WM8750";
908 codec->owner = THIS_MODULE;
909 codec->read = wm8750_read_reg_cache;
910 codec->write = wm8750_write;
911 codec->dapm_event = wm8750_dapm_event;
912 codec->dai = &wm8750_dai;
913 codec->num_dai = 1;
914 codec->reg_cache_size = ARRAY_SIZE(wm8750_reg);
915
916 codec->reg_cache =
917 kzalloc(sizeof(u16) * ARRAY_SIZE(wm8750_reg), GFP_KERNEL);
918 if (codec->reg_cache == NULL)
919 return -ENOMEM;
920 memcpy(codec->reg_cache, wm8750_reg,
921 sizeof(u16) * ARRAY_SIZE(wm8750_reg));
922 codec->reg_cache_size = sizeof(u16) * ARRAY_SIZE(wm8750_reg);
923
924 wm8750_reset(codec);
925
926 /* register pcms */
927 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
928 if (ret < 0) {
929 kfree(codec->reg_cache);
930 return ret;
931 }
932
933 /* charge output caps */
934 wm8750_dapm_event(codec, SNDRV_CTL_POWER_D2);
935 codec->dapm_state = SNDRV_CTL_POWER_D3hot;
936 queue_delayed_work(wm8750_workq, &wm8750_dapm_work,
937 msecs_to_jiffies(1000));
938
939 /* set the update bits */
940 reg = wm8750_read_reg_cache(codec, WM8750_LDAC);
941 wm8750_write(codec, WM8750_LDAC, reg | 0x0100);
942 reg = wm8750_read_reg_cache(codec, WM8750_RDAC);
943 wm8750_write(codec, WM8750_RDAC, reg | 0x0100);
944 reg = wm8750_read_reg_cache(codec, WM8750_LOUT1V);
945 wm8750_write(codec, WM8750_LOUT1V, reg | 0x0100);
946 reg = wm8750_read_reg_cache(codec, WM8750_ROUT1V);
947 wm8750_write(codec, WM8750_ROUT1V, reg | 0x0100);
948 reg = wm8750_read_reg_cache(codec, WM8750_LOUT2V);
949 wm8750_write(codec, WM8750_LOUT2V, reg | 0x0100);
950 reg = wm8750_read_reg_cache(codec, WM8750_ROUT2V);
951 wm8750_write(codec, WM8750_ROUT2V, reg | 0x0100);
952 reg = wm8750_read_reg_cache(codec, WM8750_LINVOL);
953 wm8750_write(codec, WM8750_LINVOL, reg | 0x0100);
954 reg = wm8750_read_reg_cache(codec, WM8750_RINVOL);
955 wm8750_write(codec, WM8750_RINVOL, reg | 0x0100);
956
957 wm8750_add_controls(codec);
958 wm8750_add_widgets(codec);
959 ret = snd_soc_register_card(socdev);
960 if (ret < 0) {
961 snd_soc_free_pcms(socdev);
962 snd_soc_dapm_free(socdev);
963 }
964
965 return ret;
966}
967
968/* If the i2c layer weren't so broken, we could pass this kind of data
969 around */
970static struct snd_soc_device *wm8750_socdev;
971
972#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE)
973
974/*
975 * WM8731 2 wire address is determined by GPIO5
976 * state during powerup.
977 * low = 0x1a
978 * high = 0x1b
979 */
980static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END };
981
982/* Magic definition of all other variables and things */
983I2C_CLIENT_INSMOD;
984
985static struct i2c_driver wm8750_i2c_driver;
986static struct i2c_client client_template;
987
988static int wm8750_codec_probe(struct i2c_adapter *adap, int addr, int kind)
989{
990 struct snd_soc_device *socdev = wm8750_socdev;
991 struct wm8750_setup_data *setup = socdev->codec_data;
992 struct snd_soc_codec *codec = socdev->codec;
993 struct i2c_client *i2c;
994 int ret;
995
996 if (addr != setup->i2c_address)
997 return -ENODEV;
998
999 client_template.adapter = adap;
1000 client_template.addr = addr;
1001
1002 i2c = kzalloc(sizeof(struct i2c_client), GFP_KERNEL);
1003 if (i2c == NULL) {
1004 kfree(codec);
1005 return -ENOMEM;
1006 }
1007 memcpy(i2c, &client_template, sizeof(struct i2c_client));
1008 i2c_set_clientdata(i2c, codec);
1009 codec->control_data = i2c;
1010
1011 ret = i2c_attach_client(i2c);
1012 if (ret < 0) {
1013 err("failed to attach codec at addr %x\n", addr);
1014 goto err;
1015 }
1016
1017 ret = wm8750_init(socdev);
1018 if (ret < 0) {
1019 err("failed to initialise WM8750\n");
1020 goto err;
1021 }
1022 return ret;
1023
1024err:
1025 kfree(codec);
1026 kfree(i2c);
1027 return ret;
1028}
1029
1030static int wm8750_i2c_detach(struct i2c_client *client)
1031{
1032 struct snd_soc_codec *codec = i2c_get_clientdata(client);
1033 i2c_detach_client(client);
1034 kfree(codec->reg_cache);
1035 kfree(client);
1036 return 0;
1037}
1038
1039static int wm8750_i2c_attach(struct i2c_adapter *adap)
1040{
1041 return i2c_probe(adap, &addr_data, wm8750_codec_probe);
1042}
1043
1044/* corgi i2c codec control layer */
1045static struct i2c_driver wm8750_i2c_driver = {
1046 .driver = {
1047 .name = "WM8750 I2C Codec",
1048 .owner = THIS_MODULE,
1049 },
1050 .id = I2C_DRIVERID_WM8750,
1051 .attach_adapter = wm8750_i2c_attach,
1052 .detach_client = wm8750_i2c_detach,
1053 .command = NULL,
1054};
1055
1056static struct i2c_client client_template = {
1057 .name = "WM8750",
1058 .driver = &wm8750_i2c_driver,
1059};
1060#endif
1061
1062static int wm8750_probe(struct platform_device *pdev)
1063{
1064 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1065 struct wm8750_setup_data *setup = socdev->codec_data;
1066 struct snd_soc_codec *codec;
1067 int ret = 0;
1068
1069 info("WM8750 Audio Codec %s", WM8750_VERSION);
1070 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1071 if (codec == NULL)
1072 return -ENOMEM;
1073
1074 socdev->codec = codec;
1075 mutex_init(&codec->mutex);
1076 INIT_LIST_HEAD(&codec->dapm_widgets);
1077 INIT_LIST_HEAD(&codec->dapm_paths);
1078 wm8750_socdev = socdev;
1079 INIT_WORK(&wm8750_dapm_work, wm8750_work, codec);
1080 wm8750_workq = create_workqueue("wm8750");
1081 if (wm8750_workq == NULL) {
1082 kfree(codec);
1083 return -ENOMEM;
1084 }
1085#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE)
1086 if (setup->i2c_address) {
1087 normal_i2c[0] = setup->i2c_address;
1088 codec->hw_write = (hw_write_t)i2c_master_send;
1089 ret = i2c_add_driver(&wm8750_i2c_driver);
1090 if (ret != 0)
1091 printk(KERN_ERR "can't add i2c driver");
1092 }
1093#else
1094 /* Add other interfaces here */
1095#endif
1096
1097 return ret;
1098}
1099
1100/* power down chip */
1101static int wm8750_remove(struct platform_device *pdev)
1102{
1103 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1104 struct snd_soc_codec *codec = socdev->codec;
1105
1106 if (codec->control_data)
1107 wm8750_dapm_event(codec, SNDRV_CTL_POWER_D3cold);
1108 if (wm8750_workq)
1109 destroy_workqueue(wm8750_workq);
1110 snd_soc_free_pcms(socdev);
1111 snd_soc_dapm_free(socdev);
1112#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE)
1113 i2c_del_driver(&wm8750_i2c_driver);
1114#endif
1115 kfree(codec);
1116
1117 return 0;
1118}
1119
1120struct snd_soc_codec_device soc_codec_dev_wm8750 = {
1121 .probe = wm8750_probe,
1122 .remove = wm8750_remove,
1123 .suspend = wm8750_suspend,
1124 .resume = wm8750_resume,
1125};
1126
1127EXPORT_SYMBOL_GPL(soc_codec_dev_wm8750);
1128
1129MODULE_DESCRIPTION("ASoC WM8750 driver");
1130MODULE_AUTHOR("Liam Girdwood");
1131MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8750.h b/sound/soc/codecs/wm8750.h
new file mode 100644
index 000000000000..ee5eea4a2d34
--- /dev/null
+++ b/sound/soc/codecs/wm8750.h
@@ -0,0 +1,66 @@
1/*
2 * Copyright 2005 Openedhand Ltd.
3 *
4 * Author: Richard Purdie <richard@openedhand.com>
5 *
6 * Based on WM8753.h
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#ifndef _WM8750_H
15#define _WM8750_H
16
17/* WM8750 register space */
18
19#define WM8750_LINVOL 0x00
20#define WM8750_RINVOL 0x01
21#define WM8750_LOUT1V 0x02
22#define WM8750_ROUT1V 0x03
23#define WM8750_ADCDAC 0x05
24#define WM8750_IFACE 0x07
25#define WM8750_SRATE 0x08
26#define WM8750_LDAC 0x0a
27#define WM8750_RDAC 0x0b
28#define WM8750_BASS 0x0c
29#define WM8750_TREBLE 0x0d
30#define WM8750_RESET 0x0f
31#define WM8750_3D 0x10
32#define WM8750_ALC1 0x11
33#define WM8750_ALC2 0x12
34#define WM8750_ALC3 0x13
35#define WM8750_NGATE 0x14
36#define WM8750_LADC 0x15
37#define WM8750_RADC 0x16
38#define WM8750_ADCTL1 0x17
39#define WM8750_ADCTL2 0x18
40#define WM8750_PWR1 0x19
41#define WM8750_PWR2 0x1a
42#define WM8750_ADCTL3 0x1b
43#define WM8750_ADCIN 0x1f
44#define WM8750_LADCIN 0x20
45#define WM8750_RADCIN 0x21
46#define WM8750_LOUTM1 0x22
47#define WM8750_LOUTM2 0x23
48#define WM8750_ROUTM1 0x24
49#define WM8750_ROUTM2 0x25
50#define WM8750_MOUTM1 0x26
51#define WM8750_MOUTM2 0x27
52#define WM8750_LOUT2V 0x28
53#define WM8750_ROUT2V 0x29
54#define WM8750_MOUTV 0x2a
55
56#define WM8750_CACHE_REGNUM 0x2a
57
58struct wm8750_setup_data {
59 unsigned short i2c_address;
60 unsigned int mclk;
61};
62
63extern struct snd_soc_codec_dai wm8750_dai;
64extern struct snd_soc_codec_device soc_codec_dev_wm8750;
65
66#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 00:29:15 -0500