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authorHaavard Skinnemoen <hskinnemoen@atmel.com>2007-02-14 03:33:09 -0500
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-02-14 11:09:53 -0500
commit754ce4f29937ba11f16afa41a648a30b0fc1f075 (patch)
tree65586a969cb51be1069406fd12bb441a10999b60
parentde8211b96b8491911bcb222d153c0986cb522bd6 (diff)
[PATCH] SPI: atmel_spi driver
Driver for the Atmel on-chip SPI master controller. Tested primarily on AVR32/AT32AP7000/ATSTK1000 using mtd_dataflash and the jffs2 filesystem. Should also work fine on various AT91 ARM-based chips like AT91SAM926x and AT91RM9200. Hardware documentation can be found in the AT32AP7000 data sheet, or its AT91 siblings, which can be downloaded from http://www.atmel.com/dyn/products/datasheets.asp?family_id=682 Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat
-rw-r--r--MAINTAINERS5
-rw-r--r--drivers/spi/Kconfig7
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/atmel_spi.c678
-rw-r--r--drivers/spi/atmel_spi.h167
5 files changed, 858 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 93a338daedd8..9e6c9ff0f543 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -620,6 +620,11 @@ P: Haavard Skinnemoen
620M: hskinnemoen@atmel.com 620M: hskinnemoen@atmel.com
621S: Supported 621S: Supported
622 622
623ATMEL SPI DRIVER
624P: Haavard Skinnemoen
625M: hskinnemoen@atmel.com
626S: Supported
627
623ATMEL WIRELESS DRIVER 628ATMEL WIRELESS DRIVER
624P: Simon Kelley 629P: Simon Kelley
625M: simon@thekelleys.org.uk 630M: simon@thekelleys.org.uk
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 9052f4c3493b..7e54e48efd5c 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -51,6 +51,13 @@ config SPI_MASTER
51comment "SPI Master Controller Drivers" 51comment "SPI Master Controller Drivers"
52 depends on SPI_MASTER 52 depends on SPI_MASTER
53 53
54config SPI_ATMEL
55 tristate "Atmel SPI Controller"
56 depends on (ARCH_AT91 || AVR32) && SPI_MASTER
57 help
58 This selects a driver for the Atmel SPI Controller, present on
59 many AT32 (AVR32) and AT91 (ARM) chips.
60
54config SPI_BITBANG 61config SPI_BITBANG
55 tristate "Bitbanging SPI master" 62 tristate "Bitbanging SPI master"
56 depends on SPI_MASTER && EXPERIMENTAL 63 depends on SPI_MASTER && EXPERIMENTAL
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index bf271fe4e536..3c280ad89202 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_SPI_MASTER) += spi.o
12 12
13# SPI master controller drivers (bus) 13# SPI master controller drivers (bus)
14obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o 14obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o
15obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o
15obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o 16obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o
16obj-$(CONFIG_SPI_IMX) += spi_imx.o 17obj-$(CONFIG_SPI_IMX) += spi_imx.o
17obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o 18obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o
diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
new file mode 100644
index 000000000000..c2a9fef58edc
--- /dev/null
+++ b/drivers/spi/atmel_spi.c
@@ -0,0 +1,678 @@
1/*
2 * Driver for Atmel AT32 and AT91 SPI Controllers
3 *
4 * Copyright (C) 2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/clk.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17#include <linux/dma-mapping.h>
18#include <linux/err.h>
19#include <linux/interrupt.h>
20#include <linux/spi/spi.h>
21
22#include <asm/io.h>
23#include <asm/arch/board.h>
24#include <asm/arch/gpio.h>
25
26#include "atmel_spi.h"
27
28/*
29 * The core SPI transfer engine just talks to a register bank to set up
30 * DMA transfers; transfer queue progress is driven by IRQs. The clock
31 * framework provides the base clock, subdivided for each spi_device.
32 *
33 * Newer controllers, marked with "new_1" flag, have:
34 * - CR.LASTXFER
35 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
36 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
37 * - SPI_CSRx.CSAAT
38 * - SPI_CSRx.SBCR allows faster clocking
39 */
40struct atmel_spi {
41 spinlock_t lock;
42
43 void __iomem *regs;
44 int irq;
45 struct clk *clk;
46 struct platform_device *pdev;
47 unsigned new_1:1;
48
49 u8 stopping;
50 struct list_head queue;
51 struct spi_transfer *current_transfer;
52 unsigned long remaining_bytes;
53
54 void *buffer;
55 dma_addr_t buffer_dma;
56};
57
58#define BUFFER_SIZE PAGE_SIZE
59#define INVALID_DMA_ADDRESS 0xffffffff
60
61/*
62 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
63 * they assume that spi slave device state will not change on deselect, so
64 * that automagic deselection is OK. Not so! Workaround uses nCSx pins
65 * as GPIOs; or newer controllers have CSAAT and friends.
66 *
67 * Since the CSAAT functionality is a bit weird on newer controllers
68 * as well, we use GPIO to control nCSx pins on all controllers.
69 */
70
71static inline void cs_activate(struct spi_device *spi)
72{
73 unsigned gpio = (unsigned) spi->controller_data;
74 unsigned active = spi->mode & SPI_CS_HIGH;
75
76 dev_dbg(&spi->dev, "activate %u%s\n", gpio, active ? " (high)" : "");
77 gpio_set_value(gpio, active);
78}
79
80static inline void cs_deactivate(struct spi_device *spi)
81{
82 unsigned gpio = (unsigned) spi->controller_data;
83 unsigned active = spi->mode & SPI_CS_HIGH;
84
85 dev_dbg(&spi->dev, "DEactivate %u%s\n", gpio, active ? " (low)" : "");
86 gpio_set_value(gpio, !active);
87}
88
89/*
90 * Submit next transfer for DMA.
91 * lock is held, spi irq is blocked
92 */
93static void atmel_spi_next_xfer(struct spi_master *master,
94 struct spi_message *msg)
95{
96 struct atmel_spi *as = spi_master_get_devdata(master);
97 struct spi_transfer *xfer;
98 u32 len;
99 dma_addr_t tx_dma, rx_dma;
100
101 xfer = as->current_transfer;
102 if (!xfer || as->remaining_bytes == 0) {
103 if (xfer)
104 xfer = list_entry(xfer->transfer_list.next,
105 struct spi_transfer, transfer_list);
106 else
107 xfer = list_entry(msg->transfers.next,
108 struct spi_transfer, transfer_list);
109 as->remaining_bytes = xfer->len;
110 as->current_transfer = xfer;
111 }
112
113 len = as->remaining_bytes;
114
115 tx_dma = xfer->tx_dma;
116 rx_dma = xfer->rx_dma;
117
118 /* use scratch buffer only when rx or tx data is unspecified */
119 if (rx_dma == INVALID_DMA_ADDRESS) {
120 rx_dma = as->buffer_dma;
121 if (len > BUFFER_SIZE)
122 len = BUFFER_SIZE;
123 }
124 if (tx_dma == INVALID_DMA_ADDRESS) {
125 tx_dma = as->buffer_dma;
126 if (len > BUFFER_SIZE)
127 len = BUFFER_SIZE;
128 memset(as->buffer, 0, len);
129 dma_sync_single_for_device(&as->pdev->dev,
130 as->buffer_dma, len, DMA_TO_DEVICE);
131 }
132
133 spi_writel(as, RPR, rx_dma);
134 spi_writel(as, TPR, tx_dma);
135
136 as->remaining_bytes -= len;
137 if (msg->spi->bits_per_word > 8)
138 len >>= 1;
139
140 /* REVISIT: when xfer->delay_usecs == 0, the PDC "next transfer"
141 * mechanism might help avoid the IRQ latency between transfers
142 *
143 * We're also waiting for ENDRX before we start the next
144 * transfer because we need to handle some difficult timing
145 * issues otherwise. If we wait for ENDTX in one transfer and
146 * then starts waiting for ENDRX in the next, it's difficult
147 * to tell the difference between the ENDRX interrupt we're
148 * actually waiting for and the ENDRX interrupt of the
149 * previous transfer.
150 *
151 * It should be doable, though. Just not now...
152 */
153 spi_writel(as, TNCR, 0);
154 spi_writel(as, RNCR, 0);
155 spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES));
156
157 dev_dbg(&msg->spi->dev,
158 " start xfer %p: len %u tx %p/%08x rx %p/%08x imr %03x\n",
159 xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
160 xfer->rx_buf, xfer->rx_dma, spi_readl(as, IMR));
161
162 spi_writel(as, TCR, len);
163 spi_writel(as, RCR, len);
164 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
165}
166
167static void atmel_spi_next_message(struct spi_master *master)
168{
169 struct atmel_spi *as = spi_master_get_devdata(master);
170 struct spi_message *msg;
171 u32 mr;
172
173 BUG_ON(as->current_transfer);
174
175 msg = list_entry(as->queue.next, struct spi_message, queue);
176
177 /* Select the chip */
178 mr = spi_readl(as, MR);
179 mr = SPI_BFINS(PCS, ~(1 << msg->spi->chip_select), mr);
180 spi_writel(as, MR, mr);
181 cs_activate(msg->spi);
182
183 atmel_spi_next_xfer(master, msg);
184}
185
186static void
187atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
188{
189 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
190 if (xfer->tx_buf)
191 xfer->tx_dma = dma_map_single(&as->pdev->dev,
192 (void *) xfer->tx_buf, xfer->len,
193 DMA_TO_DEVICE);
194 if (xfer->rx_buf)
195 xfer->rx_dma = dma_map_single(&as->pdev->dev,
196 xfer->rx_buf, xfer->len,
197 DMA_FROM_DEVICE);
198}
199
200static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
201 struct spi_transfer *xfer)
202{
203 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
204 dma_unmap_single(master->cdev.dev, xfer->tx_dma,
205 xfer->len, DMA_TO_DEVICE);
206 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
207 dma_unmap_single(master->cdev.dev, xfer->rx_dma,
208 xfer->len, DMA_FROM_DEVICE);
209}
210
211static void
212atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
213 struct spi_message *msg, int status)
214{
215 cs_deactivate(msg->spi);
216 list_del(&msg->queue);
217 msg->status = status;
218
219 dev_dbg(master->cdev.dev,
220 "xfer complete: %u bytes transferred\n",
221 msg->actual_length);
222
223 spin_unlock(&as->lock);
224 msg->complete(msg->context);
225 spin_lock(&as->lock);
226
227 as->current_transfer = NULL;
228
229 /* continue if needed */
230 if (list_empty(&as->queue) || as->stopping)
231 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
232 else
233 atmel_spi_next_message(master);
234}
235
236static irqreturn_t
237atmel_spi_interrupt(int irq, void *dev_id)
238{
239 struct spi_master *master = dev_id;
240 struct atmel_spi *as = spi_master_get_devdata(master);
241 struct spi_message *msg;
242 struct spi_transfer *xfer;
243 u32 status, pending, imr;
244 int ret = IRQ_NONE;
245
246 spin_lock(&as->lock);
247
248 xfer = as->current_transfer;
249 msg = list_entry(as->queue.next, struct spi_message, queue);
250
251 imr = spi_readl(as, IMR);
252 status = spi_readl(as, SR);
253 pending = status & imr;
254
255 if (pending & SPI_BIT(OVRES)) {
256 int timeout;
257
258 ret = IRQ_HANDLED;
259
260 spi_writel(as, IDR, (SPI_BIT(ENDTX) | SPI_BIT(ENDRX)
261 | SPI_BIT(OVRES)));
262
263 /*
264 * When we get an overrun, we disregard the current
265 * transfer. Data will not be copied back from any
266 * bounce buffer and msg->actual_len will not be
267 * updated with the last xfer.
268 *
269 * We will also not process any remaning transfers in
270 * the message.
271 *
272 * First, stop the transfer and unmap the DMA buffers.
273 */
274 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
275 if (!msg->is_dma_mapped)
276 atmel_spi_dma_unmap_xfer(master, xfer);
277
278 /* REVISIT: udelay in irq is unfriendly */
279 if (xfer->delay_usecs)
280 udelay(xfer->delay_usecs);
281
282 dev_warn(master->cdev.dev, "fifo overrun (%u/%u remaining)\n",
283 spi_readl(as, TCR), spi_readl(as, RCR));
284
285 /*
286 * Clean up DMA registers and make sure the data
287 * registers are empty.
288 */
289 spi_writel(as, RNCR, 0);
290 spi_writel(as, TNCR, 0);
291 spi_writel(as, RCR, 0);
292 spi_writel(as, TCR, 0);
293 for (timeout = 1000; timeout; timeout--)
294 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
295 break;
296 if (!timeout)
297 dev_warn(master->cdev.dev,
298 "timeout waiting for TXEMPTY");
299 while (spi_readl(as, SR) & SPI_BIT(RDRF))
300 spi_readl(as, RDR);
301
302 /* Clear any overrun happening while cleaning up */
303 spi_readl(as, SR);
304
305 atmel_spi_msg_done(master, as, msg, -EIO);
306 } else if (pending & SPI_BIT(ENDRX)) {
307 ret = IRQ_HANDLED;
308
309 spi_writel(as, IDR, pending);
310
311 if (as->remaining_bytes == 0) {
312 msg->actual_length += xfer->len;
313
314 if (!msg->is_dma_mapped)
315 atmel_spi_dma_unmap_xfer(master, xfer);
316
317 /* REVISIT: udelay in irq is unfriendly */
318 if (xfer->delay_usecs)
319 udelay(xfer->delay_usecs);
320
321 if (msg->transfers.prev == &xfer->transfer_list) {
322 /* report completed message */
323 atmel_spi_msg_done(master, as, msg, 0);
324 } else {
325 if (xfer->cs_change) {
326 cs_deactivate(msg->spi);
327 udelay(1);
328 cs_activate(msg->spi);
329 }
330
331 /*
332 * Not done yet. Submit the next transfer.
333 *
334 * FIXME handle protocol options for xfer
335 */
336 atmel_spi_next_xfer(master, msg);
337 }
338 } else {
339 /*
340 * Keep going, we still have data to send in
341 * the current transfer.
342 */
343 atmel_spi_next_xfer(master, msg);
344 }
345 }
346
347 spin_unlock(&as->lock);
348
349 return ret;
350}
351
352#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
353
354static int atmel_spi_setup(struct spi_device *spi)
355{
356 struct atmel_spi *as;
357 u32 scbr, csr;
358 unsigned int bits = spi->bits_per_word;
359 unsigned long bus_hz, sck_hz;
360 unsigned int npcs_pin;
361 int ret;
362
363 as = spi_master_get_devdata(spi->master);
364
365 if (as->stopping)
366 return -ESHUTDOWN;
367
368 if (spi->chip_select > spi->master->num_chipselect) {
369 dev_dbg(&spi->dev,
370 "setup: invalid chipselect %u (%u defined)\n",
371 spi->chip_select, spi->master->num_chipselect);
372 return -EINVAL;
373 }
374
375 if (bits == 0)
376 bits = 8;
377 if (bits < 8 || bits > 16) {
378 dev_dbg(&spi->dev,
379 "setup: invalid bits_per_word %u (8 to 16)\n",
380 bits);
381 return -EINVAL;
382 }
383
384 if (spi->mode & ~MODEBITS) {
385 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
386 spi->mode & ~MODEBITS);
387 return -EINVAL;
388 }
389
390 /* speed zero convention is used by some upper layers */
391 bus_hz = clk_get_rate(as->clk);
392 if (spi->max_speed_hz) {
393 /* assume div32/fdiv/mbz == 0 */
394 if (!as->new_1)
395 bus_hz /= 2;
396 scbr = ((bus_hz + spi->max_speed_hz - 1)
397 / spi->max_speed_hz);
398 if (scbr >= (1 << SPI_SCBR_SIZE)) {
399 dev_dbg(&spi->dev, "setup: %d Hz too slow, scbr %u\n",
400 spi->max_speed_hz, scbr);
401 return -EINVAL;
402 }
403 } else
404 scbr = 0xff;
405 sck_hz = bus_hz / scbr;
406
407 csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
408 if (spi->mode & SPI_CPOL)
409 csr |= SPI_BIT(CPOL);
410 if (!(spi->mode & SPI_CPHA))
411 csr |= SPI_BIT(NCPHA);
412
413 /* TODO: DLYBS and DLYBCT */
414 csr |= SPI_BF(DLYBS, 10);
415 csr |= SPI_BF(DLYBCT, 10);
416
417 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
418 npcs_pin = (unsigned int)spi->controller_data;
419 if (!spi->controller_state) {
420 ret = gpio_request(npcs_pin, "spi_npcs");
421 if (ret)
422 return ret;
423 spi->controller_state = (void *)npcs_pin;
424 gpio_direction_output(npcs_pin);
425 }
426
427 dev_dbg(&spi->dev,
428 "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
429 sck_hz, bits, spi->mode, spi->chip_select, csr);
430
431 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
432
433 return 0;
434}
435
436static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
437{
438 struct atmel_spi *as;
439 struct spi_transfer *xfer;
440 unsigned long flags;
441 struct device *controller = spi->master->cdev.dev;
442
443 as = spi_master_get_devdata(spi->master);
444
445 dev_dbg(controller, "new message %p submitted for %s\n",
446 msg, spi->dev.bus_id);
447
448 if (unlikely(list_empty(&msg->transfers)
449 || !spi->max_speed_hz))
450 return -EINVAL;
451
452 if (as->stopping)
453 return -ESHUTDOWN;
454
455 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
456 if (!(xfer->tx_buf || xfer->rx_buf)) {
457 dev_dbg(&spi->dev, "missing rx or tx buf\n");
458 return -EINVAL;
459 }
460
461 /* FIXME implement these protocol options!! */
462 if (xfer->bits_per_word || xfer->speed_hz) {
463 dev_dbg(&spi->dev, "no protocol options yet\n");
464 return -ENOPROTOOPT;
465 }
466 }
467
468 /* scrub dcache "early" */
469 if (!msg->is_dma_mapped) {
470 list_for_each_entry(xfer, &msg->transfers, transfer_list)
471 atmel_spi_dma_map_xfer(as, xfer);
472 }
473
474 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
475 dev_dbg(controller,
476 " xfer %p: len %u tx %p/%08x rx %p/%08x\n",
477 xfer, xfer->len,
478 xfer->tx_buf, xfer->tx_dma,
479 xfer->rx_buf, xfer->rx_dma);
480 }
481
482 msg->status = -EINPROGRESS;
483 msg->actual_length = 0;
484
485 spin_lock_irqsave(&as->lock, flags);
486 list_add_tail(&msg->queue, &as->queue);
487 if (!as->current_transfer)
488 atmel_spi_next_message(spi->master);
489 spin_unlock_irqrestore(&as->lock, flags);
490
491 return 0;
492}
493
494static void atmel_spi_cleanup(const struct spi_device *spi)
495{
496 if (spi->controller_state)
497 gpio_free((unsigned int)spi->controller_data);
498}
499
500/*-------------------------------------------------------------------------*/
501
502static int __init atmel_spi_probe(struct platform_device *pdev)
503{
504 struct resource *regs;
505 int irq;
506 struct clk *clk;
507 int ret;
508 struct spi_master *master;
509 struct atmel_spi *as;
510
511 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
512 if (!regs)
513 return -ENXIO;
514
515 irq = platform_get_irq(pdev, 0);
516 if (irq < 0)
517 return irq;
518
519 clk = clk_get(&pdev->dev, "spi_clk");
520 if (IS_ERR(clk))
521 return PTR_ERR(clk);
522
523 /* setup spi core then atmel-specific driver state */
524 ret = -ENOMEM;
525 master = spi_alloc_master(&pdev->dev, sizeof *as);
526 if (!master)
527 goto out_free;
528
529 master->bus_num = pdev->id;
530 master->num_chipselect = 4;
531 master->setup = atmel_spi_setup;
532 master->transfer = atmel_spi_transfer;
533 master->cleanup = atmel_spi_cleanup;
534 platform_set_drvdata(pdev, master);
535
536 as = spi_master_get_devdata(master);
537
538 as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
539 &as->buffer_dma, GFP_KERNEL);
540 if (!as->buffer)
541 goto out_free;
542
543 spin_lock_init(&as->lock);
544 INIT_LIST_HEAD(&as->queue);
545 as->pdev = pdev;
546 as->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
547 if (!as->regs)
548 goto out_free_buffer;
549 as->irq = irq;
550 as->clk = clk;
551#ifdef CONFIG_ARCH_AT91
552 if (!cpu_is_at91rm9200())
553 as->new_1 = 1;
554#endif
555
556 ret = request_irq(irq, atmel_spi_interrupt, 0,
557 pdev->dev.bus_id, master);
558 if (ret)
559 goto out_unmap_regs;
560
561 /* Initialize the hardware */
562 clk_enable(clk);
563 spi_writel(as, CR, SPI_BIT(SWRST));
564 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
565 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
566 spi_writel(as, CR, SPI_BIT(SPIEN));
567
568 /* go! */
569 dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
570 (unsigned long)regs->start, irq);
571
572 ret = spi_register_master(master);
573 if (ret)
574 goto out_reset_hw;
575
576 return 0;
577
578out_reset_hw:
579 spi_writel(as, CR, SPI_BIT(SWRST));
580 clk_disable(clk);
581 free_irq(irq, master);
582out_unmap_regs:
583 iounmap(as->regs);
584out_free_buffer:
585 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
586 as->buffer_dma);
587out_free:
588 clk_put(clk);
589 spi_master_put(master);
590 return ret;
591}
592
593static int __exit atmel_spi_remove(struct platform_device *pdev)
594{
595 struct spi_master *master = platform_get_drvdata(pdev);
596 struct atmel_spi *as = spi_master_get_devdata(master);
597 struct spi_message *msg;
598
599 /* reset the hardware and block queue progress */
600 spin_lock_irq(&as->lock);
601 as->stopping = 1;
602 spi_writel(as, CR, SPI_BIT(SWRST));
603 spi_readl(as, SR);
604 spin_unlock_irq(&as->lock);
605
606 /* Terminate remaining queued transfers */
607 list_for_each_entry(msg, &as->queue, queue) {
608 /* REVISIT unmapping the dma is a NOP on ARM and AVR32
609 * but we shouldn't depend on that...
610 */
611 msg->status = -ESHUTDOWN;
612 msg->complete(msg->context);
613 }
614
615 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
616 as->buffer_dma);
617
618 clk_disable(as->clk);
619 clk_put(as->clk);
620 free_irq(as->irq, master);
621 iounmap(as->regs);
622
623 spi_unregister_master(master);
624
625 return 0;
626}
627
628#ifdef CONFIG_PM
629
630static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
631{
632 struct spi_master *master = platform_get_drvdata(pdev);
633 struct atmel_spi *as = spi_master_get_devdata(master);
634
635 clk_disable(as->clk);
636 return 0;
637}
638
639static int atmel_spi_resume(struct platform_device *pdev)
640{
641 struct spi_master *master = platform_get_drvdata(pdev);
642 struct atmel_spi *as = spi_master_get_devdata(master);
643
644 clk_enable(as->clk);
645 return 0;
646}
647
648#else
649#define atmel_spi_suspend NULL
650#define atmel_spi_resume NULL
651#endif
652
653
654static struct platform_driver atmel_spi_driver = {
655 .driver = {
656 .name = "atmel_spi",
657 .owner = THIS_MODULE,
658 },
659 .suspend = atmel_spi_suspend,
660 .resume = atmel_spi_resume,
661 .remove = __exit_p(atmel_spi_remove),
662};
663
664static int __init atmel_spi_init(void)
665{
666 return platform_driver_probe(&atmel_spi_driver, atmel_spi_probe);
667}
668module_init(atmel_spi_init);
669
670static void __exit atmel_spi_exit(void)
671{
672 platform_driver_unregister(&atmel_spi_driver);
673}
674module_exit(atmel_spi_exit);
675
676MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
677MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
678MODULE_LICENSE("GPL");
diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h
new file mode 100644
index 000000000000..6e06b6ad3a45
--- /dev/null
+++ b/drivers/spi/atmel_spi.h
@@ -0,0 +1,167 @@
1/*
2 * Register definitions for Atmel Serial Peripheral Interface (SPI)
3 *
4 * Copyright (C) 2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __ATMEL_SPI_H__
11#define __ATMEL_SPI_H__
12
13/* SPI register offsets */
14#define SPI_CR 0x0000
15#define SPI_MR 0x0004
16#define SPI_RDR 0x0008
17#define SPI_TDR 0x000c
18#define SPI_SR 0x0010
19#define SPI_IER 0x0014
20#define SPI_IDR 0x0018
21#define SPI_IMR 0x001c
22#define SPI_CSR0 0x0030
23#define SPI_CSR1 0x0034
24#define SPI_CSR2 0x0038
25#define SPI_CSR3 0x003c
26#define SPI_RPR 0x0100
27#define SPI_RCR 0x0104
28#define SPI_TPR 0x0108
29#define SPI_TCR 0x010c
30#define SPI_RNPR 0x0110
31#define SPI_RNCR 0x0114
32#define SPI_TNPR 0x0118
33#define SPI_TNCR 0x011c
34#define SPI_PTCR 0x0120
35#define SPI_PTSR 0x0124
36
37/* Bitfields in CR */
38#define SPI_SPIEN_OFFSET 0
39#define SPI_SPIEN_SIZE 1
40#define SPI_SPIDIS_OFFSET 1
41#define SPI_SPIDIS_SIZE 1
42#define SPI_SWRST_OFFSET 7
43#define SPI_SWRST_SIZE 1
44#define SPI_LASTXFER_OFFSET 24
45#define SPI_LASTXFER_SIZE 1
46
47/* Bitfields in MR */
48#define SPI_MSTR_OFFSET 0
49#define SPI_MSTR_SIZE 1
50#define SPI_PS_OFFSET 1
51#define SPI_PS_SIZE 1
52#define SPI_PCSDEC_OFFSET 2
53#define SPI_PCSDEC_SIZE 1
54#define SPI_FDIV_OFFSET 3
55#define SPI_FDIV_SIZE 1
56#define SPI_MODFDIS_OFFSET 4
57#define SPI_MODFDIS_SIZE 1
58#define SPI_LLB_OFFSET 7
59#define SPI_LLB_SIZE 1
60#define SPI_PCS_OFFSET 16
61#define SPI_PCS_SIZE 4
62#define SPI_DLYBCS_OFFSET 24
63#define SPI_DLYBCS_SIZE 8
64
65/* Bitfields in RDR */
66#define SPI_RD_OFFSET 0
67#define SPI_RD_SIZE 16
68
69/* Bitfields in TDR */
70#define SPI_TD_OFFSET 0
71#define SPI_TD_SIZE 16
72
73/* Bitfields in SR */
74#define SPI_RDRF_OFFSET 0
75#define SPI_RDRF_SIZE 1
76#define SPI_TDRE_OFFSET 1
77#define SPI_TDRE_SIZE 1
78#define SPI_MODF_OFFSET 2
79#define SPI_MODF_SIZE 1
80#define SPI_OVRES_OFFSET 3
81#define SPI_OVRES_SIZE 1
82#define SPI_ENDRX_OFFSET 4
83#define SPI_ENDRX_SIZE 1
84#define SPI_ENDTX_OFFSET 5
85#define SPI_ENDTX_SIZE 1
86#define SPI_RXBUFF_OFFSET 6
87#define SPI_RXBUFF_SIZE 1
88#define SPI_TXBUFE_OFFSET 7
89#define SPI_TXBUFE_SIZE 1
90#define SPI_NSSR_OFFSET 8
91#define SPI_NSSR_SIZE 1
92#define SPI_TXEMPTY_OFFSET 9
93#define SPI_TXEMPTY_SIZE 1
94#define SPI_SPIENS_OFFSET 16
95#define SPI_SPIENS_SIZE 1
96
97/* Bitfields in CSR0 */
98#define SPI_CPOL_OFFSET 0
99#define SPI_CPOL_SIZE 1
100#define SPI_NCPHA_OFFSET 1
101#define SPI_NCPHA_SIZE 1
102#define SPI_CSAAT_OFFSET 3
103#define SPI_CSAAT_SIZE 1
104#define SPI_BITS_OFFSET 4
105#define SPI_BITS_SIZE 4
106#define SPI_SCBR_OFFSET 8
107#define SPI_SCBR_SIZE 8
108#define SPI_DLYBS_OFFSET 16
109#define SPI_DLYBS_SIZE 8
110#define SPI_DLYBCT_OFFSET 24
111#define SPI_DLYBCT_SIZE 8
112
113/* Bitfields in RCR */
114#define SPI_RXCTR_OFFSET 0
115#define SPI_RXCTR_SIZE 16
116
117/* Bitfields in TCR */
118#define SPI_TXCTR_OFFSET 0
119#define SPI_TXCTR_SIZE 16
120
121/* Bitfields in RNCR */
122#define SPI_RXNCR_OFFSET 0
123#define SPI_RXNCR_SIZE 16
124
125/* Bitfields in TNCR */
126#define SPI_TXNCR_OFFSET 0
127#define SPI_TXNCR_SIZE 16
128
129/* Bitfields in PTCR */
130#define SPI_RXTEN_OFFSET 0
131#define SPI_RXTEN_SIZE 1
132#define SPI_RXTDIS_OFFSET 1
133#define SPI_RXTDIS_SIZE 1
134#define SPI_TXTEN_OFFSET 8
135#define SPI_TXTEN_SIZE 1
136#define SPI_TXTDIS_OFFSET 9
137#define SPI_TXTDIS_SIZE 1
138
139/* Constants for BITS */
140#define SPI_BITS_8_BPT 0
141#define SPI_BITS_9_BPT 1
142#define SPI_BITS_10_BPT 2
143#define SPI_BITS_11_BPT 3
144#define SPI_BITS_12_BPT 4
145#define SPI_BITS_13_BPT 5
146#define SPI_BITS_14_BPT 6
147#define SPI_BITS_15_BPT 7
148#define SPI_BITS_16_BPT 8
149
150/* Bit manipulation macros */
151#define SPI_BIT(name) \
152 (1 << SPI_##name##_OFFSET)
153#define SPI_BF(name,value) \
154 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
155#define SPI_BFEXT(name,value) \
156 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
157#define SPI_BFINS(name,value,old) \
158 ( ((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
159 | SPI_BF(name,value))
160
161/* Register access macros */
162#define spi_readl(port,reg) \
163 __raw_readl((port)->regs + SPI_##reg)
164#define spi_writel(port,reg,value) \
165 __raw_writel((value), (port)->regs + SPI_##reg)
166
167#endif /* __ATMEL_SPI_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 10:02:49 -0400