aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorJeff Garzik <jeff@garzik.org>2006-08-31 17:39:21 -0400
committerJeff Garzik <jeff@garzik.org>2006-08-31 17:39:21 -0400
commit7c440e7990ea22c0c374c59a5fbd79b0579d1517 (patch)
tree4fa6513ee2740479bf9c2796a3911eefa485572b
parenta422142cfdf90d889d8d3e2affb8311a381530b7 (diff)
parent9ee093f653bae98cb56b0669819d4bccb8c05fa4 (diff)
Merge branch 'upstream' of git://lost.foo-projects.org/~ahkok/git/netdev-2.6 into upstream
Diffstat
-rw-r--r--drivers/net/e100.c8
-rw-r--r--drivers/net/e1000/e1000.h6
-rw-r--r--drivers/net/e1000/e1000_ethtool.c217
-rw-r--r--drivers/net/e1000/e1000_hw.c1055
-rw-r--r--drivers/net/e1000/e1000_hw.h26
-rw-r--r--drivers/net/e1000/e1000_main.c145
-rw-r--r--drivers/net/e1000/e1000_param.c161
-rw-r--r--drivers/net/ixgb/ixgb.h5
-rw-r--r--drivers/net/ixgb/ixgb_ethtool.c6
-rw-r--r--drivers/net/ixgb/ixgb_main.c138
10 files changed, 975 insertions, 792 deletions
diff --git a/drivers/net/e100.c b/drivers/net/e100.c
index b42ad76b1116..3b0b95892d5f 100644
--- a/drivers/net/e100.c
+++ b/drivers/net/e100.c
@@ -159,7 +159,7 @@
159 159
160#define DRV_NAME "e100" 160#define DRV_NAME "e100"
161#define DRV_EXT "-NAPI" 161#define DRV_EXT "-NAPI"
162#define DRV_VERSION "3.5.10-k4"DRV_EXT 162#define DRV_VERSION "3.5.16-k2"DRV_EXT
163#define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver" 163#define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
164#define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation" 164#define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation"
165#define PFX DRV_NAME ": " 165#define PFX DRV_NAME ": "
@@ -1759,11 +1759,10 @@ static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1759#define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN) 1759#define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
1760static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx) 1760static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1761{ 1761{
1762 if(!(rx->skb = dev_alloc_skb(RFD_BUF_LEN + NET_IP_ALIGN))) 1762 if(!(rx->skb = netdev_alloc_skb(nic->netdev, RFD_BUF_LEN + NET_IP_ALIGN)))
1763 return -ENOMEM; 1763 return -ENOMEM;
1764 1764
1765 /* Align, init, and map the RFD. */ 1765 /* Align, init, and map the RFD. */
1766 rx->skb->dev = nic->netdev;
1767 skb_reserve(rx->skb, NET_IP_ALIGN); 1766 skb_reserve(rx->skb, NET_IP_ALIGN);
1768 memcpy(rx->skb->data, &nic->blank_rfd, sizeof(struct rfd)); 1767 memcpy(rx->skb->data, &nic->blank_rfd, sizeof(struct rfd));
1769 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data, 1768 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
@@ -2139,7 +2138,7 @@ static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2139 2138
2140 e100_start_receiver(nic, NULL); 2139 e100_start_receiver(nic, NULL);
2141 2140
2142 if(!(skb = dev_alloc_skb(ETH_DATA_LEN))) { 2141 if(!(skb = netdev_alloc_skb(nic->netdev, ETH_DATA_LEN))) {
2143 err = -ENOMEM; 2142 err = -ENOMEM;
2144 goto err_loopback_none; 2143 goto err_loopback_none;
2145 } 2144 }
@@ -2791,6 +2790,7 @@ static pci_ers_result_t e100_io_error_detected(struct pci_dev *pdev, pci_channel
2791 /* Detach; put netif into state similar to hotplug unplug. */ 2790 /* Detach; put netif into state similar to hotplug unplug. */
2792 netif_poll_enable(netdev); 2791 netif_poll_enable(netdev);
2793 netif_device_detach(netdev); 2792 netif_device_detach(netdev);
2793 pci_disable_device(pdev);
2794 2794
2795 /* Request a slot reset. */ 2795 /* Request a slot reset. */
2796 return PCI_ERS_RESULT_NEED_RESET; 2796 return PCI_ERS_RESULT_NEED_RESET;
diff --git a/drivers/net/e1000/e1000.h b/drivers/net/e1000/e1000.h
index d304297c496c..98afa9c2057e 100644
--- a/drivers/net/e1000/e1000.h
+++ b/drivers/net/e1000/e1000.h
@@ -242,12 +242,10 @@ struct e1000_adapter {
242 struct timer_list watchdog_timer; 242 struct timer_list watchdog_timer;
243 struct timer_list phy_info_timer; 243 struct timer_list phy_info_timer;
244 struct vlan_group *vlgrp; 244 struct vlan_group *vlgrp;
245 uint16_t mng_vlan_id; 245 uint16_t mng_vlan_id;
246 uint32_t bd_number; 246 uint32_t bd_number;
247 uint32_t rx_buffer_len; 247 uint32_t rx_buffer_len;
248 uint32_t part_num;
249 uint32_t wol; 248 uint32_t wol;
250 uint32_t ksp3_port_a;
251 uint32_t smartspeed; 249 uint32_t smartspeed;
252 uint32_t en_mng_pt; 250 uint32_t en_mng_pt;
253 uint16_t link_speed; 251 uint16_t link_speed;
@@ -342,7 +340,9 @@ struct e1000_adapter {
342 boolean_t tso_force; 340 boolean_t tso_force;
343#endif 341#endif
344 boolean_t smart_power_down; /* phy smart power down */ 342 boolean_t smart_power_down; /* phy smart power down */
343 boolean_t quad_port_a;
345 unsigned long flags; 344 unsigned long flags;
345 uint32_t eeprom_wol;
346}; 346};
347 347
348enum e1000_state_t { 348enum e1000_state_t {
diff --git a/drivers/net/e1000/e1000_ethtool.c b/drivers/net/e1000/e1000_ethtool.c
index 2baccf864328..3fccffdb27b5 100644
--- a/drivers/net/e1000/e1000_ethtool.c
+++ b/drivers/net/e1000/e1000_ethtool.c
@@ -428,12 +428,12 @@ e1000_get_regs(struct net_device *netdev,
428 regs_buff[23] = regs_buff[18]; /* mdix mode */ 428 regs_buff[23] = regs_buff[18]; /* mdix mode */
429 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0); 429 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0);
430 } else { 430 } else {
431 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 431 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
432 regs_buff[13] = (uint32_t)phy_data; /* cable length */ 432 regs_buff[13] = (uint32_t)phy_data; /* cable length */
433 regs_buff[14] = 0; /* Dummy (to align w/ IGP phy reg dump) */ 433 regs_buff[14] = 0; /* Dummy (to align w/ IGP phy reg dump) */
434 regs_buff[15] = 0; /* Dummy (to align w/ IGP phy reg dump) */ 434 regs_buff[15] = 0; /* Dummy (to align w/ IGP phy reg dump) */
435 regs_buff[16] = 0; /* Dummy (to align w/ IGP phy reg dump) */ 435 regs_buff[16] = 0; /* Dummy (to align w/ IGP phy reg dump) */
436 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 436 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
437 regs_buff[17] = (uint32_t)phy_data; /* extended 10bt distance */ 437 regs_buff[17] = (uint32_t)phy_data; /* extended 10bt distance */
438 regs_buff[18] = regs_buff[13]; /* cable polarity */ 438 regs_buff[18] = regs_buff[13]; /* cable polarity */
439 regs_buff[19] = 0; /* Dummy (to align w/ IGP phy reg dump) */ 439 regs_buff[19] = 0; /* Dummy (to align w/ IGP phy reg dump) */
@@ -709,7 +709,6 @@ e1000_set_ringparam(struct net_device *netdev,
709 } 709 }
710 710
711 clear_bit(__E1000_RESETTING, &adapter->flags); 711 clear_bit(__E1000_RESETTING, &adapter->flags);
712
713 return 0; 712 return 0;
714err_setup_tx: 713err_setup_tx:
715 e1000_free_all_rx_resources(adapter); 714 e1000_free_all_rx_resources(adapter);
@@ -894,16 +893,17 @@ e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data)
894 893
895 *data = 0; 894 *data = 0;
896 895
896 /* NOTE: we don't test MSI interrupts here, yet */
897 /* Hook up test interrupt handler just for this test */ 897 /* Hook up test interrupt handler just for this test */
898 if (!request_irq(irq, &e1000_test_intr, IRQF_PROBE_SHARED, 898 if (!request_irq(irq, &e1000_test_intr, IRQF_PROBE_SHARED,
899 netdev->name, netdev)) { 899 netdev->name, netdev))
900 shared_int = FALSE; 900 shared_int = FALSE;
901 } else if (request_irq(irq, &e1000_test_intr, IRQF_SHARED, 901 else if (request_irq(irq, &e1000_test_intr, IRQF_SHARED,
902 netdev->name, netdev)){ 902 netdev->name, netdev)) {
903 *data = 1; 903 *data = 1;
904 return -1; 904 return -1;
905 } 905 }
906 DPRINTK(PROBE,INFO, "testing %s interrupt\n", 906 DPRINTK(HW, INFO, "testing %s interrupt\n",
907 (shared_int ? "shared" : "unshared")); 907 (shared_int ? "shared" : "unshared"));
908 908
909 /* Disable all the interrupts */ 909 /* Disable all the interrupts */
@@ -1269,11 +1269,10 @@ e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
1269 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x9140); 1269 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x9140);
1270 /* autoneg off */ 1270 /* autoneg off */
1271 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x8140); 1271 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x8140);
1272 } else if (adapter->hw.phy_type == e1000_phy_gg82563) { 1272 } else if (adapter->hw.phy_type == e1000_phy_gg82563)
1273 e1000_write_phy_reg(&adapter->hw, 1273 e1000_write_phy_reg(&adapter->hw,
1274 GG82563_PHY_KMRN_MODE_CTRL, 1274 GG82563_PHY_KMRN_MODE_CTRL,
1275 0x1CC); 1275 0x1CC);
1276 }
1277 1276
1278 ctrl_reg = E1000_READ_REG(&adapter->hw, CTRL); 1277 ctrl_reg = E1000_READ_REG(&adapter->hw, CTRL);
1279 1278
@@ -1301,9 +1300,9 @@ e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
1301 } 1300 }
1302 1301
1303 if (adapter->hw.media_type == e1000_media_type_copper && 1302 if (adapter->hw.media_type == e1000_media_type_copper &&
1304 adapter->hw.phy_type == e1000_phy_m88) { 1303 adapter->hw.phy_type == e1000_phy_m88)
1305 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */ 1304 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1306 } else { 1305 else {
1307 /* Set the ILOS bit on the fiber Nic is half 1306 /* Set the ILOS bit on the fiber Nic is half
1308 * duplex link is detected. */ 1307 * duplex link is detected. */
1309 stat_reg = E1000_READ_REG(&adapter->hw, STATUS); 1308 stat_reg = E1000_READ_REG(&adapter->hw, STATUS);
@@ -1439,11 +1438,10 @@ e1000_loopback_cleanup(struct e1000_adapter *adapter)
1439 case e1000_82546_rev_3: 1438 case e1000_82546_rev_3:
1440 default: 1439 default:
1441 hw->autoneg = TRUE; 1440 hw->autoneg = TRUE;
1442 if (hw->phy_type == e1000_phy_gg82563) { 1441 if (hw->phy_type == e1000_phy_gg82563)
1443 e1000_write_phy_reg(hw, 1442 e1000_write_phy_reg(hw,
1444 GG82563_PHY_KMRN_MODE_CTRL, 1443 GG82563_PHY_KMRN_MODE_CTRL,
1445 0x180); 1444 0x180);
1446 }
1447 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); 1445 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg);
1448 if (phy_reg & MII_CR_LOOPBACK) { 1446 if (phy_reg & MII_CR_LOOPBACK) {
1449 phy_reg &= ~MII_CR_LOOPBACK; 1447 phy_reg &= ~MII_CR_LOOPBACK;
@@ -1677,14 +1675,12 @@ e1000_diag_test(struct net_device *netdev,
1677 msleep_interruptible(4 * 1000); 1675 msleep_interruptible(4 * 1000);
1678} 1676}
1679 1677
1680static void 1678static int e1000_wol_exclusion(struct e1000_adapter *adapter, struct ethtool_wolinfo *wol)
1681e1000_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1682{ 1679{
1683 struct e1000_adapter *adapter = netdev_priv(netdev);
1684 struct e1000_hw *hw = &adapter->hw; 1680 struct e1000_hw *hw = &adapter->hw;
1681 int retval = 1; /* fail by default */
1685 1682
1686 switch (adapter->hw.device_id) { 1683 switch (hw->device_id) {
1687 case E1000_DEV_ID_82542:
1688 case E1000_DEV_ID_82543GC_FIBER: 1684 case E1000_DEV_ID_82543GC_FIBER:
1689 case E1000_DEV_ID_82543GC_COPPER: 1685 case E1000_DEV_ID_82543GC_COPPER:
1690 case E1000_DEV_ID_82544EI_FIBER: 1686 case E1000_DEV_ID_82544EI_FIBER:
@@ -1692,52 +1688,87 @@ e1000_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1692 case E1000_DEV_ID_82545EM_FIBER: 1688 case E1000_DEV_ID_82545EM_FIBER:
1693 case E1000_DEV_ID_82545EM_COPPER: 1689 case E1000_DEV_ID_82545EM_COPPER:
1694 case E1000_DEV_ID_82546GB_QUAD_COPPER: 1690 case E1000_DEV_ID_82546GB_QUAD_COPPER:
1691 case E1000_DEV_ID_82546GB_PCIE:
1692 /* these don't support WoL at all */
1695 wol->supported = 0; 1693 wol->supported = 0;
1696 wol->wolopts = 0; 1694 break;
1697 return;
1698
1699 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1700 /* device id 10B5 port-A supports wol */
1701 if (!adapter->ksp3_port_a) {
1702 wol->supported = 0;
1703 return;
1704 }
1705 /* KSP3 does not suppport UCAST wake-ups for any interface */
1706 wol->supported = WAKE_MCAST | WAKE_BCAST | WAKE_MAGIC;
1707
1708 if (adapter->wol & E1000_WUFC_EX)
1709 DPRINTK(DRV, ERR, "Interface does not support "
1710 "directed (unicast) frame wake-up packets\n");
1711 wol->wolopts = 0;
1712 goto do_defaults;
1713
1714 case E1000_DEV_ID_82546EB_FIBER: 1695 case E1000_DEV_ID_82546EB_FIBER:
1715 case E1000_DEV_ID_82546GB_FIBER: 1696 case E1000_DEV_ID_82546GB_FIBER:
1716 case E1000_DEV_ID_82571EB_FIBER: 1697 case E1000_DEV_ID_82571EB_FIBER:
1717 /* Wake events only supported on port A for dual fiber */ 1698 case E1000_DEV_ID_82571EB_SERDES:
1699 case E1000_DEV_ID_82571EB_COPPER:
1700 /* Wake events not supported on port B */
1718 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) { 1701 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) {
1719 wol->supported = 0; 1702 wol->supported = 0;
1720 wol->wolopts = 0; 1703 break;
1721 return;
1722 } 1704 }
1723 /* Fall Through */ 1705 /* return success for non excluded adapter ports */
1724 1706 retval = 0;
1707 break;
1708 case E1000_DEV_ID_82571EB_QUAD_COPPER:
1709 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1710 /* quad port adapters only support WoL on port A */
1711 if (!adapter->quad_port_a) {
1712 wol->supported = 0;
1713 break;
1714 }
1715 /* return success for non excluded adapter ports */
1716 retval = 0;
1717 break;
1725 default: 1718 default:
1726 wol->supported = WAKE_UCAST | WAKE_MCAST | 1719 /* dual port cards only support WoL on port A from now on
1727 WAKE_BCAST | WAKE_MAGIC; 1720 * unless it was enabled in the eeprom for port B
1728 wol->wolopts = 0; 1721 * so exclude FUNC_1 ports from having WoL enabled */
1722 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1 &&
1723 !adapter->eeprom_wol) {
1724 wol->supported = 0;
1725 break;
1726 }
1729 1727
1730do_defaults: 1728 retval = 0;
1731 if (adapter->wol & E1000_WUFC_EX) 1729 }
1732 wol->wolopts |= WAKE_UCAST; 1730
1733 if (adapter->wol & E1000_WUFC_MC) 1731 return retval;
1734 wol->wolopts |= WAKE_MCAST; 1732}
1735 if (adapter->wol & E1000_WUFC_BC) 1733
1736 wol->wolopts |= WAKE_BCAST; 1734static void
1737 if (adapter->wol & E1000_WUFC_MAG) 1735e1000_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1738 wol->wolopts |= WAKE_MAGIC; 1736{
1737 struct e1000_adapter *adapter = netdev_priv(netdev);
1738
1739 wol->supported = WAKE_UCAST | WAKE_MCAST |
1740 WAKE_BCAST | WAKE_MAGIC;
1741 wol->wolopts = 0;
1742
1743 /* this function will set ->supported = 0 and return 1 if wol is not
1744 * supported by this hardware */
1745 if (e1000_wol_exclusion(adapter, wol))
1739 return; 1746 return;
1747
1748 /* apply any specific unsupported masks here */
1749 switch (adapter->hw.device_id) {
1750 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1751 /* KSP3 does not suppport UCAST wake-ups */
1752 wol->supported &= ~WAKE_UCAST;
1753
1754 if (adapter->wol & E1000_WUFC_EX)
1755 DPRINTK(DRV, ERR, "Interface does not support "
1756 "directed (unicast) frame wake-up packets\n");
1757 break;
1758 default:
1759 break;
1740 } 1760 }
1761
1762 if (adapter->wol & E1000_WUFC_EX)
1763 wol->wolopts |= WAKE_UCAST;
1764 if (adapter->wol & E1000_WUFC_MC)
1765 wol->wolopts |= WAKE_MCAST;
1766 if (adapter->wol & E1000_WUFC_BC)
1767 wol->wolopts |= WAKE_BCAST;
1768 if (adapter->wol & E1000_WUFC_MAG)
1769 wol->wolopts |= WAKE_MAGIC;
1770
1771 return;
1741} 1772}
1742 1773
1743static int 1774static int
@@ -1746,51 +1777,35 @@ e1000_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1746 struct e1000_adapter *adapter = netdev_priv(netdev); 1777 struct e1000_adapter *adapter = netdev_priv(netdev);
1747 struct e1000_hw *hw = &adapter->hw; 1778 struct e1000_hw *hw = &adapter->hw;
1748 1779
1749 switch (adapter->hw.device_id) { 1780 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1750 case E1000_DEV_ID_82542: 1781 return -EOPNOTSUPP;
1751 case E1000_DEV_ID_82543GC_FIBER: 1782
1752 case E1000_DEV_ID_82543GC_COPPER: 1783 if (e1000_wol_exclusion(adapter, wol))
1753 case E1000_DEV_ID_82544EI_FIBER:
1754 case E1000_DEV_ID_82546EB_QUAD_COPPER:
1755 case E1000_DEV_ID_82546GB_QUAD_COPPER:
1756 case E1000_DEV_ID_82545EM_FIBER:
1757 case E1000_DEV_ID_82545EM_COPPER:
1758 return wol->wolopts ? -EOPNOTSUPP : 0; 1784 return wol->wolopts ? -EOPNOTSUPP : 0;
1759 1785
1786 switch (hw->device_id) {
1760 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 1787 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1761 /* device id 10B5 port-A supports wol */
1762 if (!adapter->ksp3_port_a)
1763 return wol->wolopts ? -EOPNOTSUPP : 0;
1764
1765 if (wol->wolopts & WAKE_UCAST) { 1788 if (wol->wolopts & WAKE_UCAST) {
1766 DPRINTK(DRV, ERR, "Interface does not support " 1789 DPRINTK(DRV, ERR, "Interface does not support "
1767 "directed (unicast) frame wake-up packets\n"); 1790 "directed (unicast) frame wake-up packets\n");
1768 return -EOPNOTSUPP; 1791 return -EOPNOTSUPP;
1769 } 1792 }
1770 1793 break;
1771 case E1000_DEV_ID_82546EB_FIBER:
1772 case E1000_DEV_ID_82546GB_FIBER:
1773 case E1000_DEV_ID_82571EB_FIBER:
1774 /* Wake events only supported on port A for dual fiber */
1775 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1776 return wol->wolopts ? -EOPNOTSUPP : 0;
1777 /* Fall Through */
1778
1779 default: 1794 default:
1780 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE)) 1795 break;
1781 return -EOPNOTSUPP; 1796 }
1782 1797
1783 adapter->wol = 0; 1798 /* these settings will always override what we currently have */
1799 adapter->wol = 0;
1784 1800
1785 if (wol->wolopts & WAKE_UCAST) 1801 if (wol->wolopts & WAKE_UCAST)
1786 adapter->wol |= E1000_WUFC_EX; 1802 adapter->wol |= E1000_WUFC_EX;
1787 if (wol->wolopts & WAKE_MCAST) 1803 if (wol->wolopts & WAKE_MCAST)
1788 adapter->wol |= E1000_WUFC_MC; 1804 adapter->wol |= E1000_WUFC_MC;
1789 if (wol->wolopts & WAKE_BCAST) 1805 if (wol->wolopts & WAKE_BCAST)
1790 adapter->wol |= E1000_WUFC_BC; 1806 adapter->wol |= E1000_WUFC_BC;
1791 if (wol->wolopts & WAKE_MAGIC) 1807 if (wol->wolopts & WAKE_MAGIC)
1792 adapter->wol |= E1000_WUFC_MAG; 1808 adapter->wol |= E1000_WUFC_MAG;
1793 }
1794 1809
1795 return 0; 1810 return 0;
1796} 1811}
@@ -1915,8 +1930,8 @@ static struct ethtool_ops e1000_ethtool_ops = {
1915 .get_regs = e1000_get_regs, 1930 .get_regs = e1000_get_regs,
1916 .get_wol = e1000_get_wol, 1931 .get_wol = e1000_get_wol,
1917 .set_wol = e1000_set_wol, 1932 .set_wol = e1000_set_wol,
1918 .get_msglevel = e1000_get_msglevel, 1933 .get_msglevel = e1000_get_msglevel,
1919 .set_msglevel = e1000_set_msglevel, 1934 .set_msglevel = e1000_set_msglevel,
1920 .nway_reset = e1000_nway_reset, 1935 .nway_reset = e1000_nway_reset,
1921 .get_link = ethtool_op_get_link, 1936 .get_link = ethtool_op_get_link,
1922 .get_eeprom_len = e1000_get_eeprom_len, 1937 .get_eeprom_len = e1000_get_eeprom_len,
@@ -1924,17 +1939,17 @@ static struct ethtool_ops e1000_ethtool_ops = {
1924 .set_eeprom = e1000_set_eeprom, 1939 .set_eeprom = e1000_set_eeprom,
1925 .get_ringparam = e1000_get_ringparam, 1940 .get_ringparam = e1000_get_ringparam,
1926 .set_ringparam = e1000_set_ringparam, 1941 .set_ringparam = e1000_set_ringparam,
1927 .get_pauseparam = e1000_get_pauseparam, 1942 .get_pauseparam = e1000_get_pauseparam,
1928 .set_pauseparam = e1000_set_pauseparam, 1943 .set_pauseparam = e1000_set_pauseparam,
1929 .get_rx_csum = e1000_get_rx_csum, 1944 .get_rx_csum = e1000_get_rx_csum,
1930 .set_rx_csum = e1000_set_rx_csum, 1945 .set_rx_csum = e1000_set_rx_csum,
1931 .get_tx_csum = e1000_get_tx_csum, 1946 .get_tx_csum = e1000_get_tx_csum,
1932 .set_tx_csum = e1000_set_tx_csum, 1947 .set_tx_csum = e1000_set_tx_csum,
1933 .get_sg = ethtool_op_get_sg, 1948 .get_sg = ethtool_op_get_sg,
1934 .set_sg = ethtool_op_set_sg, 1949 .set_sg = ethtool_op_set_sg,
1935#ifdef NETIF_F_TSO 1950#ifdef NETIF_F_TSO
1936 .get_tso = ethtool_op_get_tso, 1951 .get_tso = ethtool_op_get_tso,
1937 .set_tso = e1000_set_tso, 1952 .set_tso = e1000_set_tso,
1938#endif 1953#endif
1939 .self_test_count = e1000_diag_test_count, 1954 .self_test_count = e1000_diag_test_count,
1940 .self_test = e1000_diag_test, 1955 .self_test = e1000_diag_test,
@@ -1942,7 +1957,7 @@ static struct ethtool_ops e1000_ethtool_ops = {
1942 .phys_id = e1000_phys_id, 1957 .phys_id = e1000_phys_id,
1943 .get_stats_count = e1000_get_stats_count, 1958 .get_stats_count = e1000_get_stats_count,
1944 .get_ethtool_stats = e1000_get_ethtool_stats, 1959 .get_ethtool_stats = e1000_get_ethtool_stats,
1945 .get_perm_addr = ethtool_op_get_perm_addr, 1960 .get_perm_addr = ethtool_op_get_perm_addr,
1946}; 1961};
1947 1962
1948void e1000_set_ethtool_ops(struct net_device *netdev) 1963void e1000_set_ethtool_ops(struct net_device *netdev)
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index f62d17848332..4b54c489f819 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -31,6 +31,7 @@
31 * Shared functions for accessing and configuring the MAC 31 * Shared functions for accessing and configuring the MAC
32 */ 32 */
33 33
34
34#include "e1000_hw.h" 35#include "e1000_hw.h"
35 36
36static int32_t e1000_set_phy_type(struct e1000_hw *hw); 37static int32_t e1000_set_phy_type(struct e1000_hw *hw);
@@ -166,10 +167,10 @@ e1000_set_phy_type(struct e1000_hw *hw)
166{ 167{
167 DEBUGFUNC("e1000_set_phy_type"); 168 DEBUGFUNC("e1000_set_phy_type");
168 169
169 if(hw->mac_type == e1000_undefined) 170 if (hw->mac_type == e1000_undefined)
170 return -E1000_ERR_PHY_TYPE; 171 return -E1000_ERR_PHY_TYPE;
171 172
172 switch(hw->phy_id) { 173 switch (hw->phy_id) {
173 case M88E1000_E_PHY_ID: 174 case M88E1000_E_PHY_ID:
174 case M88E1000_I_PHY_ID: 175 case M88E1000_I_PHY_ID:
175 case M88E1011_I_PHY_ID: 176 case M88E1011_I_PHY_ID:
@@ -177,10 +178,10 @@ e1000_set_phy_type(struct e1000_hw *hw)
177 hw->phy_type = e1000_phy_m88; 178 hw->phy_type = e1000_phy_m88;
178 break; 179 break;
179 case IGP01E1000_I_PHY_ID: 180 case IGP01E1000_I_PHY_ID:
180 if(hw->mac_type == e1000_82541 || 181 if (hw->mac_type == e1000_82541 ||
181 hw->mac_type == e1000_82541_rev_2 || 182 hw->mac_type == e1000_82541_rev_2 ||
182 hw->mac_type == e1000_82547 || 183 hw->mac_type == e1000_82547 ||
183 hw->mac_type == e1000_82547_rev_2) { 184 hw->mac_type == e1000_82547_rev_2) {
184 hw->phy_type = e1000_phy_igp; 185 hw->phy_type = e1000_phy_igp;
185 break; 186 break;
186 } 187 }
@@ -207,6 +208,7 @@ e1000_set_phy_type(struct e1000_hw *hw)
207 return E1000_SUCCESS; 208 return E1000_SUCCESS;
208} 209}
209 210
211
210/****************************************************************************** 212/******************************************************************************
211 * IGP phy init script - initializes the GbE PHY 213 * IGP phy init script - initializes the GbE PHY
212 * 214 *
@@ -220,7 +222,7 @@ e1000_phy_init_script(struct e1000_hw *hw)
220 222
221 DEBUGFUNC("e1000_phy_init_script"); 223 DEBUGFUNC("e1000_phy_init_script");
222 224
223 if(hw->phy_init_script) { 225 if (hw->phy_init_script) {
224 msec_delay(20); 226 msec_delay(20);
225 227
226 /* Save off the current value of register 0x2F5B to be restored at 228 /* Save off the current value of register 0x2F5B to be restored at
@@ -236,7 +238,7 @@ e1000_phy_init_script(struct e1000_hw *hw)
236 238
237 msec_delay(5); 239 msec_delay(5);
238 240
239 switch(hw->mac_type) { 241 switch (hw->mac_type) {
240 case e1000_82541: 242 case e1000_82541:
241 case e1000_82547: 243 case e1000_82547:
242 e1000_write_phy_reg(hw, 0x1F95, 0x0001); 244 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
@@ -273,22 +275,22 @@ e1000_phy_init_script(struct e1000_hw *hw)
273 /* Now enable the transmitter */ 275 /* Now enable the transmitter */
274 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 276 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
275 277
276 if(hw->mac_type == e1000_82547) { 278 if (hw->mac_type == e1000_82547) {
277 uint16_t fused, fine, coarse; 279 uint16_t fused, fine, coarse;
278 280
279 /* Move to analog registers page */ 281 /* Move to analog registers page */
280 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 282 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
281 283
282 if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 284 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
283 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused); 285 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
284 286
285 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 287 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
286 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 288 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
287 289
288 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 290 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
289 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; 291 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
290 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 292 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
291 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 293 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
292 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 294 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
293 295
294 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 296 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
@@ -387,6 +389,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
387 case E1000_DEV_ID_82571EB_COPPER: 389 case E1000_DEV_ID_82571EB_COPPER:
388 case E1000_DEV_ID_82571EB_FIBER: 390 case E1000_DEV_ID_82571EB_FIBER:
389 case E1000_DEV_ID_82571EB_SERDES: 391 case E1000_DEV_ID_82571EB_SERDES:
392 case E1000_DEV_ID_82571EB_QUAD_COPPER:
390 hw->mac_type = e1000_82571; 393 hw->mac_type = e1000_82571;
391 break; 394 break;
392 case E1000_DEV_ID_82572EI_COPPER: 395 case E1000_DEV_ID_82572EI_COPPER:
@@ -418,7 +421,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
418 return -E1000_ERR_MAC_TYPE; 421 return -E1000_ERR_MAC_TYPE;
419 } 422 }
420 423
421 switch(hw->mac_type) { 424 switch (hw->mac_type) {
422 case e1000_ich8lan: 425 case e1000_ich8lan:
423 hw->swfwhw_semaphore_present = TRUE; 426 hw->swfwhw_semaphore_present = TRUE;
424 hw->asf_firmware_present = TRUE; 427 hw->asf_firmware_present = TRUE;
@@ -456,7 +459,7 @@ e1000_set_media_type(struct e1000_hw *hw)
456 459
457 DEBUGFUNC("e1000_set_media_type"); 460 DEBUGFUNC("e1000_set_media_type");
458 461
459 if(hw->mac_type != e1000_82543) { 462 if (hw->mac_type != e1000_82543) {
460 /* tbi_compatibility is only valid on 82543 */ 463 /* tbi_compatibility is only valid on 82543 */
461 hw->tbi_compatibility_en = FALSE; 464 hw->tbi_compatibility_en = FALSE;
462 } 465 }
@@ -516,16 +519,16 @@ e1000_reset_hw(struct e1000_hw *hw)
516 DEBUGFUNC("e1000_reset_hw"); 519 DEBUGFUNC("e1000_reset_hw");
517 520
518 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 521 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
519 if(hw->mac_type == e1000_82542_rev2_0) { 522 if (hw->mac_type == e1000_82542_rev2_0) {
520 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 523 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
521 e1000_pci_clear_mwi(hw); 524 e1000_pci_clear_mwi(hw);
522 } 525 }
523 526
524 if(hw->bus_type == e1000_bus_type_pci_express) { 527 if (hw->bus_type == e1000_bus_type_pci_express) {
525 /* Prevent the PCI-E bus from sticking if there is no TLP connection 528 /* Prevent the PCI-E bus from sticking if there is no TLP connection
526 * on the last TLP read/write transaction when MAC is reset. 529 * on the last TLP read/write transaction when MAC is reset.
527 */ 530 */
528 if(e1000_disable_pciex_master(hw) != E1000_SUCCESS) { 531 if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
529 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 532 DEBUGOUT("PCI-E Master disable polling has failed.\n");
530 } 533 }
531 } 534 }
@@ -553,14 +556,14 @@ e1000_reset_hw(struct e1000_hw *hw)
553 ctrl = E1000_READ_REG(hw, CTRL); 556 ctrl = E1000_READ_REG(hw, CTRL);
554 557
555 /* Must reset the PHY before resetting the MAC */ 558 /* Must reset the PHY before resetting the MAC */
556 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 559 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
557 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 560 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
558 msec_delay(5); 561 msec_delay(5);
559 } 562 }
560 563
561 /* Must acquire the MDIO ownership before MAC reset. 564 /* Must acquire the MDIO ownership before MAC reset.
562 * Ownership defaults to firmware after a reset. */ 565 * Ownership defaults to firmware after a reset. */
563 if(hw->mac_type == e1000_82573) { 566 if (hw->mac_type == e1000_82573) {
564 timeout = 10; 567 timeout = 10;
565 568
566 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 569 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
@@ -570,14 +573,14 @@ e1000_reset_hw(struct e1000_hw *hw)
570 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 573 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
571 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 574 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
572 575
573 if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 576 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
574 break; 577 break;
575 else 578 else
576 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 579 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
577 580
578 msec_delay(2); 581 msec_delay(2);
579 timeout--; 582 timeout--;
580 } while(timeout); 583 } while (timeout);
581 } 584 }
582 585
583 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 586 /* Workaround for ICH8 bit corruption issue in FIFO memory */
@@ -595,7 +598,7 @@ e1000_reset_hw(struct e1000_hw *hw)
595 */ 598 */
596 DEBUGOUT("Issuing a global reset to MAC\n"); 599 DEBUGOUT("Issuing a global reset to MAC\n");
597 600
598 switch(hw->mac_type) { 601 switch (hw->mac_type) {
599 case e1000_82544: 602 case e1000_82544:
600 case e1000_82540: 603 case e1000_82540:
601 case e1000_82545: 604 case e1000_82545:
@@ -634,7 +637,7 @@ e1000_reset_hw(struct e1000_hw *hw)
634 * device. Later controllers reload the EEPROM automatically, so just wait 637 * device. Later controllers reload the EEPROM automatically, so just wait
635 * for reload to complete. 638 * for reload to complete.
636 */ 639 */
637 switch(hw->mac_type) { 640 switch (hw->mac_type) {
638 case e1000_82542_rev2_0: 641 case e1000_82542_rev2_0:
639 case e1000_82542_rev2_1: 642 case e1000_82542_rev2_1:
640 case e1000_82543: 643 case e1000_82543:
@@ -669,7 +672,7 @@ e1000_reset_hw(struct e1000_hw *hw)
669 case e1000_ich8lan: 672 case e1000_ich8lan:
670 case e1000_80003es2lan: 673 case e1000_80003es2lan:
671 ret_val = e1000_get_auto_rd_done(hw); 674 ret_val = e1000_get_auto_rd_done(hw);
672 if(ret_val) 675 if (ret_val)
673 /* We don't want to continue accessing MAC registers. */ 676 /* We don't want to continue accessing MAC registers. */
674 return ret_val; 677 return ret_val;
675 break; 678 break;
@@ -680,13 +683,13 @@ e1000_reset_hw(struct e1000_hw *hw)
680 } 683 }
681 684
682 /* Disable HW ARPs on ASF enabled adapters */ 685 /* Disable HW ARPs on ASF enabled adapters */
683 if(hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) { 686 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
684 manc = E1000_READ_REG(hw, MANC); 687 manc = E1000_READ_REG(hw, MANC);
685 manc &= ~(E1000_MANC_ARP_EN); 688 manc &= ~(E1000_MANC_ARP_EN);
686 E1000_WRITE_REG(hw, MANC, manc); 689 E1000_WRITE_REG(hw, MANC, manc);
687 } 690 }
688 691
689 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 692 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
690 e1000_phy_init_script(hw); 693 e1000_phy_init_script(hw);
691 694
692 /* Configure activity LED after PHY reset */ 695 /* Configure activity LED after PHY reset */
@@ -704,8 +707,8 @@ e1000_reset_hw(struct e1000_hw *hw)
704 icr = E1000_READ_REG(hw, ICR); 707 icr = E1000_READ_REG(hw, ICR);
705 708
706 /* If MWI was previously enabled, reenable it. */ 709 /* If MWI was previously enabled, reenable it. */
707 if(hw->mac_type == e1000_82542_rev2_0) { 710 if (hw->mac_type == e1000_82542_rev2_0) {
708 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 711 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
709 e1000_pci_set_mwi(hw); 712 e1000_pci_set_mwi(hw);
710 } 713 }
711 714
@@ -758,7 +761,7 @@ e1000_init_hw(struct e1000_hw *hw)
758 761
759 /* Initialize Identification LED */ 762 /* Initialize Identification LED */
760 ret_val = e1000_id_led_init(hw); 763 ret_val = e1000_id_led_init(hw);
761 if(ret_val) { 764 if (ret_val) {
762 DEBUGOUT("Error Initializing Identification LED\n"); 765 DEBUGOUT("Error Initializing Identification LED\n");
763 return ret_val; 766 return ret_val;
764 } 767 }
@@ -776,7 +779,7 @@ e1000_init_hw(struct e1000_hw *hw)
776 } 779 }
777 780
778 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 781 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
779 if(hw->mac_type == e1000_82542_rev2_0) { 782 if (hw->mac_type == e1000_82542_rev2_0) {
780 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 783 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
781 e1000_pci_clear_mwi(hw); 784 e1000_pci_clear_mwi(hw);
782 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 785 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
@@ -790,11 +793,11 @@ e1000_init_hw(struct e1000_hw *hw)
790 e1000_init_rx_addrs(hw); 793 e1000_init_rx_addrs(hw);
791 794
792 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 795 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
793 if(hw->mac_type == e1000_82542_rev2_0) { 796 if (hw->mac_type == e1000_82542_rev2_0) {
794 E1000_WRITE_REG(hw, RCTL, 0); 797 E1000_WRITE_REG(hw, RCTL, 0);
795 E1000_WRITE_FLUSH(hw); 798 E1000_WRITE_FLUSH(hw);
796 msec_delay(1); 799 msec_delay(1);
797 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 800 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
798 e1000_pci_set_mwi(hw); 801 e1000_pci_set_mwi(hw);
799 } 802 }
800 803
@@ -803,7 +806,7 @@ e1000_init_hw(struct e1000_hw *hw)
803 mta_size = E1000_MC_TBL_SIZE; 806 mta_size = E1000_MC_TBL_SIZE;
804 if (hw->mac_type == e1000_ich8lan) 807 if (hw->mac_type == e1000_ich8lan)
805 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 808 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
806 for(i = 0; i < mta_size; i++) { 809 for (i = 0; i < mta_size; i++) {
807 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 810 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
808 /* use write flush to prevent Memory Write Block (MWB) from 811 /* use write flush to prevent Memory Write Block (MWB) from
809 * occuring when accessing our register space */ 812 * occuring when accessing our register space */
@@ -815,18 +818,18 @@ e1000_init_hw(struct e1000_hw *hw)
815 * gives equal priority to transmits and receives. Valid only on 818 * gives equal priority to transmits and receives. Valid only on
816 * 82542 and 82543 silicon. 819 * 82542 and 82543 silicon.
817 */ 820 */
818 if(hw->dma_fairness && hw->mac_type <= e1000_82543) { 821 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
819 ctrl = E1000_READ_REG(hw, CTRL); 822 ctrl = E1000_READ_REG(hw, CTRL);
820 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 823 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
821 } 824 }
822 825
823 switch(hw->mac_type) { 826 switch (hw->mac_type) {
824 case e1000_82545_rev_3: 827 case e1000_82545_rev_3:
825 case e1000_82546_rev_3: 828 case e1000_82546_rev_3:
826 break; 829 break;
827 default: 830 default:
828 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 831 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
829 if(hw->bus_type == e1000_bus_type_pcix) { 832 if (hw->bus_type == e1000_bus_type_pcix) {
830 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word); 833 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
831 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, 834 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
832 &pcix_stat_hi_word); 835 &pcix_stat_hi_word);
@@ -834,9 +837,9 @@ e1000_init_hw(struct e1000_hw *hw)
834 PCIX_COMMAND_MMRBC_SHIFT; 837 PCIX_COMMAND_MMRBC_SHIFT;
835 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 838 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
836 PCIX_STATUS_HI_MMRBC_SHIFT; 839 PCIX_STATUS_HI_MMRBC_SHIFT;
837 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 840 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
838 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 841 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
839 if(cmd_mmrbc > stat_mmrbc) { 842 if (cmd_mmrbc > stat_mmrbc) {
840 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 843 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
841 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 844 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
842 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, 845 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
@@ -854,7 +857,7 @@ e1000_init_hw(struct e1000_hw *hw)
854 ret_val = e1000_setup_link(hw); 857 ret_val = e1000_setup_link(hw);
855 858
856 /* Set the transmit descriptor write-back policy */ 859 /* Set the transmit descriptor write-back policy */
857 if(hw->mac_type > e1000_82544) { 860 if (hw->mac_type > e1000_82544) {
858 ctrl = E1000_READ_REG(hw, TXDCTL); 861 ctrl = E1000_READ_REG(hw, TXDCTL);
859 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 862 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
860 switch (hw->mac_type) { 863 switch (hw->mac_type) {
@@ -905,14 +908,13 @@ e1000_init_hw(struct e1000_hw *hw)
905 case e1000_ich8lan: 908 case e1000_ich8lan:
906 ctrl = E1000_READ_REG(hw, TXDCTL1); 909 ctrl = E1000_READ_REG(hw, TXDCTL1);
907 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 910 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
908 if(hw->mac_type >= e1000_82571) 911 if (hw->mac_type >= e1000_82571)
909 ctrl |= E1000_TXDCTL_COUNT_DESC; 912 ctrl |= E1000_TXDCTL_COUNT_DESC;
910 E1000_WRITE_REG(hw, TXDCTL1, ctrl); 913 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
911 break; 914 break;
912 } 915 }
913 916
914 917
915
916 if (hw->mac_type == e1000_82573) { 918 if (hw->mac_type == e1000_82573) {
917 uint32_t gcr = E1000_READ_REG(hw, GCR); 919 uint32_t gcr = E1000_READ_REG(hw, GCR);
918 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 920 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
@@ -956,10 +958,10 @@ e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
956 958
957 DEBUGFUNC("e1000_adjust_serdes_amplitude"); 959 DEBUGFUNC("e1000_adjust_serdes_amplitude");
958 960
959 if(hw->media_type != e1000_media_type_internal_serdes) 961 if (hw->media_type != e1000_media_type_internal_serdes)
960 return E1000_SUCCESS; 962 return E1000_SUCCESS;
961 963
962 switch(hw->mac_type) { 964 switch (hw->mac_type) {
963 case e1000_82545_rev_3: 965 case e1000_82545_rev_3:
964 case e1000_82546_rev_3: 966 case e1000_82546_rev_3:
965 break; 967 break;
@@ -972,11 +974,11 @@ e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
972 return ret_val; 974 return ret_val;
973 } 975 }
974 976
975 if(eeprom_data != EEPROM_RESERVED_WORD) { 977 if (eeprom_data != EEPROM_RESERVED_WORD) {
976 /* Adjust SERDES output amplitude only. */ 978 /* Adjust SERDES output amplitude only. */
977 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 979 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
978 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); 980 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
979 if(ret_val) 981 if (ret_val)
980 return ret_val; 982 return ret_val;
981 } 983 }
982 984
@@ -1044,10 +1046,10 @@ e1000_setup_link(struct e1000_hw *hw)
1044 * in case we get disconnected and then reconnected into a different 1046 * in case we get disconnected and then reconnected into a different
1045 * hub or switch with different Flow Control capabilities. 1047 * hub or switch with different Flow Control capabilities.
1046 */ 1048 */
1047 if(hw->mac_type == e1000_82542_rev2_0) 1049 if (hw->mac_type == e1000_82542_rev2_0)
1048 hw->fc &= (~e1000_fc_tx_pause); 1050 hw->fc &= (~e1000_fc_tx_pause);
1049 1051
1050 if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 1052 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1051 hw->fc &= (~e1000_fc_rx_pause); 1053 hw->fc &= (~e1000_fc_rx_pause);
1052 1054
1053 hw->original_fc = hw->fc; 1055 hw->original_fc = hw->fc;
@@ -1062,12 +1064,12 @@ e1000_setup_link(struct e1000_hw *hw)
1062 * or e1000_phy_setup() is called. 1064 * or e1000_phy_setup() is called.
1063 */ 1065 */
1064 if (hw->mac_type == e1000_82543) { 1066 if (hw->mac_type == e1000_82543) {
1065 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1067 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1066 1, &eeprom_data); 1068 1, &eeprom_data);
1067 if (ret_val) { 1069 if (ret_val) {
1068 DEBUGOUT("EEPROM Read Error\n"); 1070 DEBUGOUT("EEPROM Read Error\n");
1069 return -E1000_ERR_EEPROM; 1071 return -E1000_ERR_EEPROM;
1070 } 1072 }
1071 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1073 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1072 SWDPIO__EXT_SHIFT); 1074 SWDPIO__EXT_SHIFT);
1073 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1075 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
@@ -1100,14 +1102,14 @@ e1000_setup_link(struct e1000_hw *hw)
1100 * ability to transmit pause frames in not enabled, then these 1102 * ability to transmit pause frames in not enabled, then these
1101 * registers will be set to 0. 1103 * registers will be set to 0.
1102 */ 1104 */
1103 if(!(hw->fc & e1000_fc_tx_pause)) { 1105 if (!(hw->fc & e1000_fc_tx_pause)) {
1104 E1000_WRITE_REG(hw, FCRTL, 0); 1106 E1000_WRITE_REG(hw, FCRTL, 0);
1105 E1000_WRITE_REG(hw, FCRTH, 0); 1107 E1000_WRITE_REG(hw, FCRTH, 0);
1106 } else { 1108 } else {
1107 /* We need to set up the Receive Threshold high and low water marks 1109 /* We need to set up the Receive Threshold high and low water marks
1108 * as well as (optionally) enabling the transmission of XON frames. 1110 * as well as (optionally) enabling the transmission of XON frames.
1109 */ 1111 */
1110 if(hw->fc_send_xon) { 1112 if (hw->fc_send_xon) {
1111 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); 1113 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1112 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1114 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1113 } else { 1115 } else {
@@ -1154,11 +1156,11 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1154 * the EEPROM. 1156 * the EEPROM.
1155 */ 1157 */
1156 ctrl = E1000_READ_REG(hw, CTRL); 1158 ctrl = E1000_READ_REG(hw, CTRL);
1157 if(hw->media_type == e1000_media_type_fiber) 1159 if (hw->media_type == e1000_media_type_fiber)
1158 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 1160 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1159 1161
1160 ret_val = e1000_adjust_serdes_amplitude(hw); 1162 ret_val = e1000_adjust_serdes_amplitude(hw);
1161 if(ret_val) 1163 if (ret_val)
1162 return ret_val; 1164 return ret_val;
1163 1165
1164 /* Take the link out of reset */ 1166 /* Take the link out of reset */
@@ -1166,7 +1168,7 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1166 1168
1167 /* Adjust VCO speed to improve BER performance */ 1169 /* Adjust VCO speed to improve BER performance */
1168 ret_val = e1000_set_vco_speed(hw); 1170 ret_val = e1000_set_vco_speed(hw);
1169 if(ret_val) 1171 if (ret_val)
1170 return ret_val; 1172 return ret_val;
1171 1173
1172 e1000_config_collision_dist(hw); 1174 e1000_config_collision_dist(hw);
@@ -1237,15 +1239,15 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1237 * less than 500 milliseconds even if the other end is doing it in SW). 1239 * less than 500 milliseconds even if the other end is doing it in SW).
1238 * For internal serdes, we just assume a signal is present, then poll. 1240 * For internal serdes, we just assume a signal is present, then poll.
1239 */ 1241 */
1240 if(hw->media_type == e1000_media_type_internal_serdes || 1242 if (hw->media_type == e1000_media_type_internal_serdes ||
1241 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 1243 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1242 DEBUGOUT("Looking for Link\n"); 1244 DEBUGOUT("Looking for Link\n");
1243 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 1245 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1244 msec_delay(10); 1246 msec_delay(10);
1245 status = E1000_READ_REG(hw, STATUS); 1247 status = E1000_READ_REG(hw, STATUS);
1246 if(status & E1000_STATUS_LU) break; 1248 if (status & E1000_STATUS_LU) break;
1247 } 1249 }
1248 if(i == (LINK_UP_TIMEOUT / 10)) { 1250 if (i == (LINK_UP_TIMEOUT / 10)) {
1249 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1251 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1250 hw->autoneg_failed = 1; 1252 hw->autoneg_failed = 1;
1251 /* AutoNeg failed to achieve a link, so we'll call 1253 /* AutoNeg failed to achieve a link, so we'll call
@@ -1254,7 +1256,7 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1254 * non-autonegotiating link partners. 1256 * non-autonegotiating link partners.
1255 */ 1257 */
1256 ret_val = e1000_check_for_link(hw); 1258 ret_val = e1000_check_for_link(hw);
1257 if(ret_val) { 1259 if (ret_val) {
1258 DEBUGOUT("Error while checking for link\n"); 1260 DEBUGOUT("Error while checking for link\n");
1259 return ret_val; 1261 return ret_val;
1260 } 1262 }
@@ -1288,7 +1290,7 @@ e1000_copper_link_preconfig(struct e1000_hw *hw)
1288 * the PHY speed and duplex configuration is. In addition, we need to 1290 * the PHY speed and duplex configuration is. In addition, we need to
1289 * perform a hardware reset on the PHY to take it out of reset. 1291 * perform a hardware reset on the PHY to take it out of reset.
1290 */ 1292 */
1291 if(hw->mac_type > e1000_82543) { 1293 if (hw->mac_type > e1000_82543) {
1292 ctrl |= E1000_CTRL_SLU; 1294 ctrl |= E1000_CTRL_SLU;
1293 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1295 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1294 E1000_WRITE_REG(hw, CTRL, ctrl); 1296 E1000_WRITE_REG(hw, CTRL, ctrl);
@@ -1296,13 +1298,13 @@ e1000_copper_link_preconfig(struct e1000_hw *hw)
1296 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 1298 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1297 E1000_WRITE_REG(hw, CTRL, ctrl); 1299 E1000_WRITE_REG(hw, CTRL, ctrl);
1298 ret_val = e1000_phy_hw_reset(hw); 1300 ret_val = e1000_phy_hw_reset(hw);
1299 if(ret_val) 1301 if (ret_val)
1300 return ret_val; 1302 return ret_val;
1301 } 1303 }
1302 1304
1303 /* Make sure we have a valid PHY */ 1305 /* Make sure we have a valid PHY */
1304 ret_val = e1000_detect_gig_phy(hw); 1306 ret_val = e1000_detect_gig_phy(hw);
1305 if(ret_val) { 1307 if (ret_val) {
1306 DEBUGOUT("Error, did not detect valid phy.\n"); 1308 DEBUGOUT("Error, did not detect valid phy.\n");
1307 return ret_val; 1309 return ret_val;
1308 } 1310 }
@@ -1310,19 +1312,19 @@ e1000_copper_link_preconfig(struct e1000_hw *hw)
1310 1312
1311 /* Set PHY to class A mode (if necessary) */ 1313 /* Set PHY to class A mode (if necessary) */
1312 ret_val = e1000_set_phy_mode(hw); 1314 ret_val = e1000_set_phy_mode(hw);
1313 if(ret_val) 1315 if (ret_val)
1314 return ret_val; 1316 return ret_val;
1315 1317
1316 if((hw->mac_type == e1000_82545_rev_3) || 1318 if ((hw->mac_type == e1000_82545_rev_3) ||
1317 (hw->mac_type == e1000_82546_rev_3)) { 1319 (hw->mac_type == e1000_82546_rev_3)) {
1318 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1320 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1319 phy_data |= 0x00000008; 1321 phy_data |= 0x00000008;
1320 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1322 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1321 } 1323 }
1322 1324
1323 if(hw->mac_type <= e1000_82543 || 1325 if (hw->mac_type <= e1000_82543 ||
1324 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || 1326 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1325 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) 1327 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1326 hw->phy_reset_disable = FALSE; 1328 hw->phy_reset_disable = FALSE;
1327 1329
1328 return E1000_SUCCESS; 1330 return E1000_SUCCESS;
@@ -1352,7 +1354,7 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
1352 return ret_val; 1354 return ret_val;
1353 } 1355 }
1354 1356
1355 /* Wait 10ms for MAC to configure PHY from eeprom settings */ 1357 /* Wait 15ms for MAC to configure PHY from eeprom settings */
1356 msec_delay(15); 1358 msec_delay(15);
1357 if (hw->mac_type != e1000_ich8lan) { 1359 if (hw->mac_type != e1000_ich8lan) {
1358 /* Configure activity LED after PHY reset */ 1360 /* Configure activity LED after PHY reset */
@@ -1407,45 +1409,45 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
1407 } 1409 }
1408 } 1410 }
1409 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1411 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1410 if(ret_val) 1412 if (ret_val)
1411 return ret_val; 1413 return ret_val;
1412 1414
1413 /* set auto-master slave resolution settings */ 1415 /* set auto-master slave resolution settings */
1414 if(hw->autoneg) { 1416 if (hw->autoneg) {
1415 e1000_ms_type phy_ms_setting = hw->master_slave; 1417 e1000_ms_type phy_ms_setting = hw->master_slave;
1416 1418
1417 if(hw->ffe_config_state == e1000_ffe_config_active) 1419 if (hw->ffe_config_state == e1000_ffe_config_active)
1418 hw->ffe_config_state = e1000_ffe_config_enabled; 1420 hw->ffe_config_state = e1000_ffe_config_enabled;
1419 1421
1420 if(hw->dsp_config_state == e1000_dsp_config_activated) 1422 if (hw->dsp_config_state == e1000_dsp_config_activated)
1421 hw->dsp_config_state = e1000_dsp_config_enabled; 1423 hw->dsp_config_state = e1000_dsp_config_enabled;
1422 1424
1423 /* when autonegotiation advertisment is only 1000Mbps then we 1425 /* when autonegotiation advertisment is only 1000Mbps then we
1424 * should disable SmartSpeed and enable Auto MasterSlave 1426 * should disable SmartSpeed and enable Auto MasterSlave
1425 * resolution as hardware default. */ 1427 * resolution as hardware default. */
1426 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) { 1428 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1427 /* Disable SmartSpeed */ 1429 /* Disable SmartSpeed */
1428 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); 1430 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1429 if(ret_val) 1431 &phy_data);
1432 if (ret_val)
1430 return ret_val; 1433 return ret_val;
1431 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1434 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1432 ret_val = e1000_write_phy_reg(hw, 1435 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1433 IGP01E1000_PHY_PORT_CONFIG, 1436 phy_data);
1434 phy_data); 1437 if (ret_val)
1435 if(ret_val)
1436 return ret_val; 1438 return ret_val;
1437 /* Set auto Master/Slave resolution process */ 1439 /* Set auto Master/Slave resolution process */
1438 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1440 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1439 if(ret_val) 1441 if (ret_val)
1440 return ret_val; 1442 return ret_val;
1441 phy_data &= ~CR_1000T_MS_ENABLE; 1443 phy_data &= ~CR_1000T_MS_ENABLE;
1442 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1444 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1443 if(ret_val) 1445 if (ret_val)
1444 return ret_val; 1446 return ret_val;
1445 } 1447 }
1446 1448
1447 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1449 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1448 if(ret_val) 1450 if (ret_val)
1449 return ret_val; 1451 return ret_val;
1450 1452
1451 /* load defaults for future use */ 1453 /* load defaults for future use */
@@ -1469,7 +1471,7 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
1469 break; 1471 break;
1470 } 1472 }
1471 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1473 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1472 if(ret_val) 1474 if (ret_val)
1473 return ret_val; 1475 return ret_val;
1474 } 1476 }
1475 1477
@@ -1490,12 +1492,12 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1490 1492
1491 DEBUGFUNC("e1000_copper_link_ggp_setup"); 1493 DEBUGFUNC("e1000_copper_link_ggp_setup");
1492 1494
1493 if(!hw->phy_reset_disable) { 1495 if (!hw->phy_reset_disable) {
1494 1496
1495 /* Enable CRS on TX for half-duplex operation. */ 1497 /* Enable CRS on TX for half-duplex operation. */
1496 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 1498 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1497 &phy_data); 1499 &phy_data);
1498 if(ret_val) 1500 if (ret_val)
1499 return ret_val; 1501 return ret_val;
1500 1502
1501 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 1503 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
@@ -1504,7 +1506,7 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1504 1506
1505 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 1507 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1506 phy_data); 1508 phy_data);
1507 if(ret_val) 1509 if (ret_val)
1508 return ret_val; 1510 return ret_val;
1509 1511
1510 /* Options: 1512 /* Options:
@@ -1515,7 +1517,7 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1515 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1517 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1516 */ 1518 */
1517 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data); 1519 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
1518 if(ret_val) 1520 if (ret_val)
1519 return ret_val; 1521 return ret_val;
1520 1522
1521 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 1523 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
@@ -1540,11 +1542,11 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1540 * 1 - Enabled 1542 * 1 - Enabled
1541 */ 1543 */
1542 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1544 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1543 if(hw->disable_polarity_correction == 1) 1545 if (hw->disable_polarity_correction == 1)
1544 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1546 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1545 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); 1547 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1546 1548
1547 if(ret_val) 1549 if (ret_val)
1548 return ret_val; 1550 return ret_val;
1549 1551
1550 /* SW Reset the PHY so all changes take effect */ 1552 /* SW Reset the PHY so all changes take effect */
@@ -1600,9 +1602,9 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1600 return ret_val; 1602 return ret_val;
1601 1603
1602 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1604 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1603
1604 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1605 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1605 phy_data); 1606 phy_data);
1607
1606 if (ret_val) 1608 if (ret_val)
1607 return ret_val; 1609 return ret_val;
1608 } 1610 }
@@ -1637,12 +1639,12 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1637 1639
1638 DEBUGFUNC("e1000_copper_link_mgp_setup"); 1640 DEBUGFUNC("e1000_copper_link_mgp_setup");
1639 1641
1640 if(hw->phy_reset_disable) 1642 if (hw->phy_reset_disable)
1641 return E1000_SUCCESS; 1643 return E1000_SUCCESS;
1642 1644
1643 /* Enable CRS on TX. This must be set for half-duplex operation. */ 1645 /* Enable CRS on TX. This must be set for half-duplex operation. */
1644 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1646 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1645 if(ret_val) 1647 if (ret_val)
1646 return ret_val; 1648 return ret_val;
1647 1649
1648 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1650 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
@@ -1679,7 +1681,7 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1679 * 1 - Enabled 1681 * 1 - Enabled
1680 */ 1682 */
1681 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1683 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1682 if(hw->disable_polarity_correction == 1) 1684 if (hw->disable_polarity_correction == 1)
1683 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1685 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1684 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1686 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1685 if (ret_val) 1687 if (ret_val)
@@ -1719,7 +1721,7 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1719 1721
1720 /* SW Reset the PHY so all changes take effect */ 1722 /* SW Reset the PHY so all changes take effect */
1721 ret_val = e1000_phy_reset(hw); 1723 ret_val = e1000_phy_reset(hw);
1722 if(ret_val) { 1724 if (ret_val) {
1723 DEBUGOUT("Error Resetting the PHY\n"); 1725 DEBUGOUT("Error Resetting the PHY\n");
1724 return ret_val; 1726 return ret_val;
1725 } 1727 }
@@ -1749,7 +1751,7 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
1749 /* If autoneg_advertised is zero, we assume it was not defaulted 1751 /* If autoneg_advertised is zero, we assume it was not defaulted
1750 * by the calling code so we set to advertise full capability. 1752 * by the calling code so we set to advertise full capability.
1751 */ 1753 */
1752 if(hw->autoneg_advertised == 0) 1754 if (hw->autoneg_advertised == 0)
1753 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1755 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1754 1756
1755 /* IFE phy only supports 10/100 */ 1757 /* IFE phy only supports 10/100 */
@@ -1758,7 +1760,7 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
1758 1760
1759 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1761 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1760 ret_val = e1000_phy_setup_autoneg(hw); 1762 ret_val = e1000_phy_setup_autoneg(hw);
1761 if(ret_val) { 1763 if (ret_val) {
1762 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1764 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1763 return ret_val; 1765 return ret_val;
1764 } 1766 }
@@ -1768,20 +1770,20 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
1768 * the Auto Neg Restart bit in the PHY control register. 1770 * the Auto Neg Restart bit in the PHY control register.
1769 */ 1771 */
1770 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 1772 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1771 if(ret_val) 1773 if (ret_val)
1772 return ret_val; 1774 return ret_val;
1773 1775
1774 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1776 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1775 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 1777 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1776 if(ret_val) 1778 if (ret_val)
1777 return ret_val; 1779 return ret_val;
1778 1780
1779 /* Does the user want to wait for Auto-Neg to complete here, or 1781 /* Does the user want to wait for Auto-Neg to complete here, or
1780 * check at a later time (for example, callback routine). 1782 * check at a later time (for example, callback routine).
1781 */ 1783 */
1782 if(hw->wait_autoneg_complete) { 1784 if (hw->wait_autoneg_complete) {
1783 ret_val = e1000_wait_autoneg(hw); 1785 ret_val = e1000_wait_autoneg(hw);
1784 if(ret_val) { 1786 if (ret_val) {
1785 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1787 DEBUGOUT("Error while waiting for autoneg to complete\n");
1786 return ret_val; 1788 return ret_val;
1787 } 1789 }
@@ -1792,7 +1794,6 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
1792 return E1000_SUCCESS; 1794 return E1000_SUCCESS;
1793} 1795}
1794 1796
1795
1796/****************************************************************************** 1797/******************************************************************************
1797* Config the MAC and the PHY after link is up. 1798* Config the MAC and the PHY after link is up.
1798* 1) Set up the MAC to the current PHY speed/duplex 1799* 1) Set up the MAC to the current PHY speed/duplex
@@ -1811,25 +1812,25 @@ e1000_copper_link_postconfig(struct e1000_hw *hw)
1811 int32_t ret_val; 1812 int32_t ret_val;
1812 DEBUGFUNC("e1000_copper_link_postconfig"); 1813 DEBUGFUNC("e1000_copper_link_postconfig");
1813 1814
1814 if(hw->mac_type >= e1000_82544) { 1815 if (hw->mac_type >= e1000_82544) {
1815 e1000_config_collision_dist(hw); 1816 e1000_config_collision_dist(hw);
1816 } else { 1817 } else {
1817 ret_val = e1000_config_mac_to_phy(hw); 1818 ret_val = e1000_config_mac_to_phy(hw);
1818 if(ret_val) { 1819 if (ret_val) {
1819 DEBUGOUT("Error configuring MAC to PHY settings\n"); 1820 DEBUGOUT("Error configuring MAC to PHY settings\n");
1820 return ret_val; 1821 return ret_val;
1821 } 1822 }
1822 } 1823 }
1823 ret_val = e1000_config_fc_after_link_up(hw); 1824 ret_val = e1000_config_fc_after_link_up(hw);
1824 if(ret_val) { 1825 if (ret_val) {
1825 DEBUGOUT("Error Configuring Flow Control\n"); 1826 DEBUGOUT("Error Configuring Flow Control\n");
1826 return ret_val; 1827 return ret_val;
1827 } 1828 }
1828 1829
1829 /* Config DSP to improve Giga link quality */ 1830 /* Config DSP to improve Giga link quality */
1830 if(hw->phy_type == e1000_phy_igp) { 1831 if (hw->phy_type == e1000_phy_igp) {
1831 ret_val = e1000_config_dsp_after_link_change(hw, TRUE); 1832 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1832 if(ret_val) { 1833 if (ret_val) {
1833 DEBUGOUT("Error Configuring DSP after link up\n"); 1834 DEBUGOUT("Error Configuring DSP after link up\n");
1834 return ret_val; 1835 return ret_val;
1835 } 1836 }
@@ -1875,7 +1876,7 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1875 1876
1876 /* Check if it is a valid PHY and set PHY mode if necessary. */ 1877 /* Check if it is a valid PHY and set PHY mode if necessary. */
1877 ret_val = e1000_copper_link_preconfig(hw); 1878 ret_val = e1000_copper_link_preconfig(hw);
1878 if(ret_val) 1879 if (ret_val)
1879 return ret_val; 1880 return ret_val;
1880 1881
1881 switch (hw->mac_type) { 1882 switch (hw->mac_type) {
@@ -1896,30 +1897,30 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1896 hw->phy_type == e1000_phy_igp_3 || 1897 hw->phy_type == e1000_phy_igp_3 ||
1897 hw->phy_type == e1000_phy_igp_2) { 1898 hw->phy_type == e1000_phy_igp_2) {
1898 ret_val = e1000_copper_link_igp_setup(hw); 1899 ret_val = e1000_copper_link_igp_setup(hw);
1899 if(ret_val) 1900 if (ret_val)
1900 return ret_val; 1901 return ret_val;
1901 } else if (hw->phy_type == e1000_phy_m88) { 1902 } else if (hw->phy_type == e1000_phy_m88) {
1902 ret_val = e1000_copper_link_mgp_setup(hw); 1903 ret_val = e1000_copper_link_mgp_setup(hw);
1903 if(ret_val) 1904 if (ret_val)
1904 return ret_val; 1905 return ret_val;
1905 } else if (hw->phy_type == e1000_phy_gg82563) { 1906 } else if (hw->phy_type == e1000_phy_gg82563) {
1906 ret_val = e1000_copper_link_ggp_setup(hw); 1907 ret_val = e1000_copper_link_ggp_setup(hw);
1907 if(ret_val) 1908 if (ret_val)
1908 return ret_val; 1909 return ret_val;
1909 } 1910 }
1910 1911
1911 if(hw->autoneg) { 1912 if (hw->autoneg) {
1912 /* Setup autoneg and flow control advertisement 1913 /* Setup autoneg and flow control advertisement
1913 * and perform autonegotiation */ 1914 * and perform autonegotiation */
1914 ret_val = e1000_copper_link_autoneg(hw); 1915 ret_val = e1000_copper_link_autoneg(hw);
1915 if(ret_val) 1916 if (ret_val)
1916 return ret_val; 1917 return ret_val;
1917 } else { 1918 } else {
1918 /* PHY will be set to 10H, 10F, 100H,or 100F 1919 /* PHY will be set to 10H, 10F, 100H,or 100F
1919 * depending on value from forced_speed_duplex. */ 1920 * depending on value from forced_speed_duplex. */
1920 DEBUGOUT("Forcing speed and duplex\n"); 1921 DEBUGOUT("Forcing speed and duplex\n");
1921 ret_val = e1000_phy_force_speed_duplex(hw); 1922 ret_val = e1000_phy_force_speed_duplex(hw);
1922 if(ret_val) { 1923 if (ret_val) {
1923 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1924 DEBUGOUT("Error Forcing Speed and Duplex\n");
1924 return ret_val; 1925 return ret_val;
1925 } 1926 }
@@ -1928,18 +1929,18 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1928 /* Check link status. Wait up to 100 microseconds for link to become 1929 /* Check link status. Wait up to 100 microseconds for link to become
1929 * valid. 1930 * valid.
1930 */ 1931 */
1931 for(i = 0; i < 10; i++) { 1932 for (i = 0; i < 10; i++) {
1932 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 1933 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1933 if(ret_val) 1934 if (ret_val)
1934 return ret_val; 1935 return ret_val;
1935 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 1936 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1936 if(ret_val) 1937 if (ret_val)
1937 return ret_val; 1938 return ret_val;
1938 1939
1939 if(phy_data & MII_SR_LINK_STATUS) { 1940 if (phy_data & MII_SR_LINK_STATUS) {
1940 /* Config the MAC and PHY after link is up */ 1941 /* Config the MAC and PHY after link is up */
1941 ret_val = e1000_copper_link_postconfig(hw); 1942 ret_val = e1000_copper_link_postconfig(hw);
1942 if(ret_val) 1943 if (ret_val)
1943 return ret_val; 1944 return ret_val;
1944 1945
1945 DEBUGOUT("Valid link established!!!\n"); 1946 DEBUGOUT("Valid link established!!!\n");
@@ -2041,7 +2042,7 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
2041 2042
2042 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 2043 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2043 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 2044 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
2044 if(ret_val) 2045 if (ret_val)
2045 return ret_val; 2046 return ret_val;
2046 2047
2047 if (hw->phy_type != e1000_phy_ife) { 2048 if (hw->phy_type != e1000_phy_ife) {
@@ -2069,36 +2070,36 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
2069 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); 2070 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2070 2071
2071 /* Do we want to advertise 10 Mb Half Duplex? */ 2072 /* Do we want to advertise 10 Mb Half Duplex? */
2072 if(hw->autoneg_advertised & ADVERTISE_10_HALF) { 2073 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
2073 DEBUGOUT("Advertise 10mb Half duplex\n"); 2074 DEBUGOUT("Advertise 10mb Half duplex\n");
2074 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 2075 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
2075 } 2076 }
2076 2077
2077 /* Do we want to advertise 10 Mb Full Duplex? */ 2078 /* Do we want to advertise 10 Mb Full Duplex? */
2078 if(hw->autoneg_advertised & ADVERTISE_10_FULL) { 2079 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
2079 DEBUGOUT("Advertise 10mb Full duplex\n"); 2080 DEBUGOUT("Advertise 10mb Full duplex\n");
2080 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 2081 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
2081 } 2082 }
2082 2083
2083 /* Do we want to advertise 100 Mb Half Duplex? */ 2084 /* Do we want to advertise 100 Mb Half Duplex? */
2084 if(hw->autoneg_advertised & ADVERTISE_100_HALF) { 2085 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
2085 DEBUGOUT("Advertise 100mb Half duplex\n"); 2086 DEBUGOUT("Advertise 100mb Half duplex\n");
2086 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 2087 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
2087 } 2088 }
2088 2089
2089 /* Do we want to advertise 100 Mb Full Duplex? */ 2090 /* Do we want to advertise 100 Mb Full Duplex? */
2090 if(hw->autoneg_advertised & ADVERTISE_100_FULL) { 2091 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
2091 DEBUGOUT("Advertise 100mb Full duplex\n"); 2092 DEBUGOUT("Advertise 100mb Full duplex\n");
2092 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 2093 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
2093 } 2094 }
2094 2095
2095 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 2096 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
2096 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) { 2097 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
2097 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); 2098 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
2098 } 2099 }
2099 2100
2100 /* Do we want to advertise 1000 Mb Full Duplex? */ 2101 /* Do we want to advertise 1000 Mb Full Duplex? */
2101 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) { 2102 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
2102 DEBUGOUT("Advertise 1000mb Full duplex\n"); 2103 DEBUGOUT("Advertise 1000mb Full duplex\n");
2103 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 2104 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2104 if (hw->phy_type == e1000_phy_ife) { 2105 if (hw->phy_type == e1000_phy_ife) {
@@ -2160,7 +2161,7 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
2160 } 2161 }
2161 2162
2162 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 2163 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
2163 if(ret_val) 2164 if (ret_val)
2164 return ret_val; 2165 return ret_val;
2165 2166
2166 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 2167 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
@@ -2208,7 +2209,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2208 2209
2209 /* Read the MII Control Register. */ 2210 /* Read the MII Control Register. */
2210 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 2211 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
2211 if(ret_val) 2212 if (ret_val)
2212 return ret_val; 2213 return ret_val;
2213 2214
2214 /* We need to disable autoneg in order to force link and duplex. */ 2215 /* We need to disable autoneg in order to force link and duplex. */
@@ -2216,8 +2217,8 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2216 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 2217 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2217 2218
2218 /* Are we forcing Full or Half Duplex? */ 2219 /* Are we forcing Full or Half Duplex? */
2219 if(hw->forced_speed_duplex == e1000_100_full || 2220 if (hw->forced_speed_duplex == e1000_100_full ||
2220 hw->forced_speed_duplex == e1000_10_full) { 2221 hw->forced_speed_duplex == e1000_10_full) {
2221 /* We want to force full duplex so we SET the full duplex bits in the 2222 /* We want to force full duplex so we SET the full duplex bits in the
2222 * Device and MII Control Registers. 2223 * Device and MII Control Registers.
2223 */ 2224 */
@@ -2234,7 +2235,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2234 } 2235 }
2235 2236
2236 /* Are we forcing 100Mbps??? */ 2237 /* Are we forcing 100Mbps??? */
2237 if(hw->forced_speed_duplex == e1000_100_full || 2238 if (hw->forced_speed_duplex == e1000_100_full ||
2238 hw->forced_speed_duplex == e1000_100_half) { 2239 hw->forced_speed_duplex == e1000_100_half) {
2239 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 2240 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
2240 ctrl |= E1000_CTRL_SPD_100; 2241 ctrl |= E1000_CTRL_SPD_100;
@@ -2257,7 +2258,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2257 if ((hw->phy_type == e1000_phy_m88) || 2258 if ((hw->phy_type == e1000_phy_m88) ||
2258 (hw->phy_type == e1000_phy_gg82563)) { 2259 (hw->phy_type == e1000_phy_gg82563)) {
2259 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2260 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2260 if(ret_val) 2261 if (ret_val)
2261 return ret_val; 2262 return ret_val;
2262 2263
2263 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 2264 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
@@ -2265,7 +2266,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2265 */ 2266 */
2266 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2267 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2267 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2268 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2268 if(ret_val) 2269 if (ret_val)
2269 return ret_val; 2270 return ret_val;
2270 2271
2271 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); 2272 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
@@ -2289,20 +2290,20 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2289 * forced whenever speed or duplex are forced. 2290 * forced whenever speed or duplex are forced.
2290 */ 2291 */
2291 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2292 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2292 if(ret_val) 2293 if (ret_val)
2293 return ret_val; 2294 return ret_val;
2294 2295
2295 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2296 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2296 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2297 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2297 2298
2298 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2299 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2299 if(ret_val) 2300 if (ret_val)
2300 return ret_val; 2301 return ret_val;
2301 } 2302 }
2302 2303
2303 /* Write back the modified PHY MII control register. */ 2304 /* Write back the modified PHY MII control register. */
2304 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 2305 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
2305 if(ret_val) 2306 if (ret_val)
2306 return ret_val; 2307 return ret_val;
2307 2308
2308 udelay(1); 2309 udelay(1);
@@ -2314,50 +2315,50 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2314 * only if the user has set wait_autoneg_complete to 1, which is 2315 * only if the user has set wait_autoneg_complete to 1, which is
2315 * the default. 2316 * the default.
2316 */ 2317 */
2317 if(hw->wait_autoneg_complete) { 2318 if (hw->wait_autoneg_complete) {
2318 /* We will wait for autoneg to complete. */ 2319 /* We will wait for autoneg to complete. */
2319 DEBUGOUT("Waiting for forced speed/duplex link.\n"); 2320 DEBUGOUT("Waiting for forced speed/duplex link.\n");
2320 mii_status_reg = 0; 2321 mii_status_reg = 0;
2321 2322
2322 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 2323 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2323 for(i = PHY_FORCE_TIME; i > 0; i--) { 2324 for (i = PHY_FORCE_TIME; i > 0; i--) {
2324 /* Read the MII Status Register and wait for Auto-Neg Complete bit 2325 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2325 * to be set. 2326 * to be set.
2326 */ 2327 */
2327 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2328 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2328 if(ret_val) 2329 if (ret_val)
2329 return ret_val; 2330 return ret_val;
2330 2331
2331 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2332 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2332 if(ret_val) 2333 if (ret_val)
2333 return ret_val; 2334 return ret_val;
2334 2335
2335 if(mii_status_reg & MII_SR_LINK_STATUS) break; 2336 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2336 msec_delay(100); 2337 msec_delay(100);
2337 } 2338 }
2338 if((i == 0) && 2339 if ((i == 0) &&
2339 ((hw->phy_type == e1000_phy_m88) || 2340 ((hw->phy_type == e1000_phy_m88) ||
2340 (hw->phy_type == e1000_phy_gg82563))) { 2341 (hw->phy_type == e1000_phy_gg82563))) {
2341 /* We didn't get link. Reset the DSP and wait again for link. */ 2342 /* We didn't get link. Reset the DSP and wait again for link. */
2342 ret_val = e1000_phy_reset_dsp(hw); 2343 ret_val = e1000_phy_reset_dsp(hw);
2343 if(ret_val) { 2344 if (ret_val) {
2344 DEBUGOUT("Error Resetting PHY DSP\n"); 2345 DEBUGOUT("Error Resetting PHY DSP\n");
2345 return ret_val; 2346 return ret_val;
2346 } 2347 }
2347 } 2348 }
2348 /* This loop will early-out if the link condition has been met. */ 2349 /* This loop will early-out if the link condition has been met. */
2349 for(i = PHY_FORCE_TIME; i > 0; i--) { 2350 for (i = PHY_FORCE_TIME; i > 0; i--) {
2350 if(mii_status_reg & MII_SR_LINK_STATUS) break; 2351 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2351 msec_delay(100); 2352 msec_delay(100);
2352 /* Read the MII Status Register and wait for Auto-Neg Complete bit 2353 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2353 * to be set. 2354 * to be set.
2354 */ 2355 */
2355 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2356 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2356 if(ret_val) 2357 if (ret_val)
2357 return ret_val; 2358 return ret_val;
2358 2359
2359 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2360 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2360 if(ret_val) 2361 if (ret_val)
2361 return ret_val; 2362 return ret_val;
2362 } 2363 }
2363 } 2364 }
@@ -2368,32 +2369,31 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2368 * defaults back to a 2.5MHz clock when the PHY is reset. 2369 * defaults back to a 2.5MHz clock when the PHY is reset.
2369 */ 2370 */
2370 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 2371 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2371 if(ret_val) 2372 if (ret_val)
2372 return ret_val; 2373 return ret_val;
2373 2374
2374 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2375 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2375 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2376 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2376 if(ret_val) 2377 if (ret_val)
2377 return ret_val; 2378 return ret_val;
2378 2379
2379 /* In addition, because of the s/w reset above, we need to enable CRS on 2380 /* In addition, because of the s/w reset above, we need to enable CRS on
2380 * TX. This must be set for both full and half duplex operation. 2381 * TX. This must be set for both full and half duplex operation.
2381 */ 2382 */
2382 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2383 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2383 if(ret_val) 2384 if (ret_val)
2384 return ret_val; 2385 return ret_val;
2385 2386
2386 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2387 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2387 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2388 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2388 if(ret_val) 2389 if (ret_val)
2389 return ret_val; 2390 return ret_val;
2390 2391
2391 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && 2392 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2392 (!hw->autoneg) && 2393 (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
2393 (hw->forced_speed_duplex == e1000_10_full || 2394 hw->forced_speed_duplex == e1000_10_half)) {
2394 hw->forced_speed_duplex == e1000_10_half)) {
2395 ret_val = e1000_polarity_reversal_workaround(hw); 2395 ret_val = e1000_polarity_reversal_workaround(hw);
2396 if(ret_val) 2396 if (ret_val)
2397 return ret_val; 2397 return ret_val;
2398 } 2398 }
2399 } else if (hw->phy_type == e1000_phy_gg82563) { 2399 } else if (hw->phy_type == e1000_phy_gg82563) {
@@ -2484,10 +2484,10 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
2484 * registers depending on negotiated values. 2484 * registers depending on negotiated values.
2485 */ 2485 */
2486 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2486 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2487 if(ret_val) 2487 if (ret_val)
2488 return ret_val; 2488 return ret_val;
2489 2489
2490 if(phy_data & M88E1000_PSSR_DPLX) 2490 if (phy_data & M88E1000_PSSR_DPLX)
2491 ctrl |= E1000_CTRL_FD; 2491 ctrl |= E1000_CTRL_FD;
2492 else 2492 else
2493 ctrl &= ~E1000_CTRL_FD; 2493 ctrl &= ~E1000_CTRL_FD;
@@ -2497,9 +2497,9 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
2497 /* Set up speed in the Device Control register depending on 2497 /* Set up speed in the Device Control register depending on
2498 * negotiated values. 2498 * negotiated values.
2499 */ 2499 */
2500 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 2500 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2501 ctrl |= E1000_CTRL_SPD_1000; 2501 ctrl |= E1000_CTRL_SPD_1000;
2502 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 2502 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2503 ctrl |= E1000_CTRL_SPD_100; 2503 ctrl |= E1000_CTRL_SPD_100;
2504 2504
2505 /* Write the configured values back to the Device Control Reg. */ 2505 /* Write the configured values back to the Device Control Reg. */
@@ -2567,7 +2567,7 @@ e1000_force_mac_fc(struct e1000_hw *hw)
2567 } 2567 }
2568 2568
2569 /* Disable TX Flow Control for 82542 (rev 2.0) */ 2569 /* Disable TX Flow Control for 82542 (rev 2.0) */
2570 if(hw->mac_type == e1000_82542_rev2_0) 2570 if (hw->mac_type == e1000_82542_rev2_0)
2571 ctrl &= (~E1000_CTRL_TFCE); 2571 ctrl &= (~E1000_CTRL_TFCE);
2572 2572
2573 E1000_WRITE_REG(hw, CTRL, ctrl); 2573 E1000_WRITE_REG(hw, CTRL, ctrl);
@@ -2601,11 +2601,12 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2601 * so we had to force link. In this case, we need to force the 2601 * so we had to force link. In this case, we need to force the
2602 * configuration of the MAC to match the "fc" parameter. 2602 * configuration of the MAC to match the "fc" parameter.
2603 */ 2603 */
2604 if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) || 2604 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2605 ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) || 2605 ((hw->media_type == e1000_media_type_internal_serdes) &&
2606 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) { 2606 (hw->autoneg_failed)) ||
2607 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
2607 ret_val = e1000_force_mac_fc(hw); 2608 ret_val = e1000_force_mac_fc(hw);
2608 if(ret_val) { 2609 if (ret_val) {
2609 DEBUGOUT("Error forcing flow control settings\n"); 2610 DEBUGOUT("Error forcing flow control settings\n");
2610 return ret_val; 2611 return ret_val;
2611 } 2612 }
@@ -2616,19 +2617,19 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2616 * has completed, and if so, how the PHY and link partner has 2617 * has completed, and if so, how the PHY and link partner has
2617 * flow control configured. 2618 * flow control configured.
2618 */ 2619 */
2619 if((hw->media_type == e1000_media_type_copper) && hw->autoneg) { 2620 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2620 /* Read the MII Status Register and check to see if AutoNeg 2621 /* Read the MII Status Register and check to see if AutoNeg
2621 * has completed. We read this twice because this reg has 2622 * has completed. We read this twice because this reg has
2622 * some "sticky" (latched) bits. 2623 * some "sticky" (latched) bits.
2623 */ 2624 */
2624 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2625 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2625 if(ret_val) 2626 if (ret_val)
2626 return ret_val; 2627 return ret_val;
2627 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2628 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2628 if(ret_val) 2629 if (ret_val)
2629 return ret_val; 2630 return ret_val;
2630 2631
2631 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 2632 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2632 /* The AutoNeg process has completed, so we now need to 2633 /* The AutoNeg process has completed, so we now need to
2633 * read both the Auto Negotiation Advertisement Register 2634 * read both the Auto Negotiation Advertisement Register
2634 * (Address 4) and the Auto_Negotiation Base Page Ability 2635 * (Address 4) and the Auto_Negotiation Base Page Ability
@@ -2637,11 +2638,11 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2637 */ 2638 */
2638 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 2639 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2639 &mii_nway_adv_reg); 2640 &mii_nway_adv_reg);
2640 if(ret_val) 2641 if (ret_val)
2641 return ret_val; 2642 return ret_val;
2642 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, 2643 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2643 &mii_nway_lp_ability_reg); 2644 &mii_nway_lp_ability_reg);
2644 if(ret_val) 2645 if (ret_val)
2645 return ret_val; 2646 return ret_val;
2646 2647
2647 /* Two bits in the Auto Negotiation Advertisement Register 2648 /* Two bits in the Auto Negotiation Advertisement Register
@@ -2678,15 +2679,15 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2678 * 1 | DC | 1 | DC | e1000_fc_full 2679 * 1 | DC | 1 | DC | e1000_fc_full
2679 * 2680 *
2680 */ 2681 */
2681 if((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2682 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2682 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 2683 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2683 /* Now we need to check if the user selected RX ONLY 2684 /* Now we need to check if the user selected RX ONLY
2684 * of pause frames. In this case, we had to advertise 2685 * of pause frames. In this case, we had to advertise
2685 * FULL flow control because we could not advertise RX 2686 * FULL flow control because we could not advertise RX
2686 * ONLY. Hence, we must now check to see if we need to 2687 * ONLY. Hence, we must now check to see if we need to
2687 * turn OFF the TRANSMISSION of PAUSE frames. 2688 * turn OFF the TRANSMISSION of PAUSE frames.
2688 */ 2689 */
2689 if(hw->original_fc == e1000_fc_full) { 2690 if (hw->original_fc == e1000_fc_full) {
2690 hw->fc = e1000_fc_full; 2691 hw->fc = e1000_fc_full;
2691 DEBUGOUT("Flow Control = FULL.\n"); 2692 DEBUGOUT("Flow Control = FULL.\n");
2692 } else { 2693 } else {
@@ -2702,10 +2703,10 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2702 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 2703 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2703 * 2704 *
2704 */ 2705 */
2705 else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 2706 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2706 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2707 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2707 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2708 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2708 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 2709 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2709 hw->fc = e1000_fc_tx_pause; 2710 hw->fc = e1000_fc_tx_pause;
2710 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 2711 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2711 } 2712 }
@@ -2717,10 +2718,10 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2717 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 2718 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2718 * 2719 *
2719 */ 2720 */
2720 else if((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2721 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2721 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2722 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2722 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2723 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2723 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 2724 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2724 hw->fc = e1000_fc_rx_pause; 2725 hw->fc = e1000_fc_rx_pause;
2725 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2726 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2726 } 2727 }
@@ -2744,9 +2745,9 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2744 * be asked to delay transmission of packets than asking 2745 * be asked to delay transmission of packets than asking
2745 * our link partner to pause transmission of frames. 2746 * our link partner to pause transmission of frames.
2746 */ 2747 */
2747 else if((hw->original_fc == e1000_fc_none || 2748 else if ((hw->original_fc == e1000_fc_none ||
2748 hw->original_fc == e1000_fc_tx_pause) || 2749 hw->original_fc == e1000_fc_tx_pause) ||
2749 hw->fc_strict_ieee) { 2750 hw->fc_strict_ieee) {
2750 hw->fc = e1000_fc_none; 2751 hw->fc = e1000_fc_none;
2751 DEBUGOUT("Flow Control = NONE.\n"); 2752 DEBUGOUT("Flow Control = NONE.\n");
2752 } else { 2753 } else {
@@ -2759,19 +2760,19 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2759 * enabled per IEEE 802.3 spec. 2760 * enabled per IEEE 802.3 spec.
2760 */ 2761 */
2761 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 2762 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2762 if(ret_val) { 2763 if (ret_val) {
2763 DEBUGOUT("Error getting link speed and duplex\n"); 2764 DEBUGOUT("Error getting link speed and duplex\n");
2764 return ret_val; 2765 return ret_val;
2765 } 2766 }
2766 2767
2767 if(duplex == HALF_DUPLEX) 2768 if (duplex == HALF_DUPLEX)
2768 hw->fc = e1000_fc_none; 2769 hw->fc = e1000_fc_none;
2769 2770
2770 /* Now we call a subroutine to actually force the MAC 2771 /* Now we call a subroutine to actually force the MAC
2771 * controller to use the correct flow control settings. 2772 * controller to use the correct flow control settings.
2772 */ 2773 */
2773 ret_val = e1000_force_mac_fc(hw); 2774 ret_val = e1000_force_mac_fc(hw);
2774 if(ret_val) { 2775 if (ret_val) {
2775 DEBUGOUT("Error forcing flow control settings\n"); 2776 DEBUGOUT("Error forcing flow control settings\n");
2776 return ret_val; 2777 return ret_val;
2777 } 2778 }
@@ -2810,13 +2811,13 @@ e1000_check_for_link(struct e1000_hw *hw)
2810 * set when the optics detect a signal. On older adapters, it will be 2811 * set when the optics detect a signal. On older adapters, it will be
2811 * cleared when there is a signal. This applies to fiber media only. 2812 * cleared when there is a signal. This applies to fiber media only.
2812 */ 2813 */
2813 if((hw->media_type == e1000_media_type_fiber) || 2814 if ((hw->media_type == e1000_media_type_fiber) ||
2814 (hw->media_type == e1000_media_type_internal_serdes)) { 2815 (hw->media_type == e1000_media_type_internal_serdes)) {
2815 rxcw = E1000_READ_REG(hw, RXCW); 2816 rxcw = E1000_READ_REG(hw, RXCW);
2816 2817
2817 if(hw->media_type == e1000_media_type_fiber) { 2818 if (hw->media_type == e1000_media_type_fiber) {
2818 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 2819 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2819 if(status & E1000_STATUS_LU) 2820 if (status & E1000_STATUS_LU)
2820 hw->get_link_status = FALSE; 2821 hw->get_link_status = FALSE;
2821 } 2822 }
2822 } 2823 }
@@ -2827,20 +2828,20 @@ e1000_check_for_link(struct e1000_hw *hw)
2827 * receive a Link Status Change interrupt or we have Rx Sequence 2828 * receive a Link Status Change interrupt or we have Rx Sequence
2828 * Errors. 2829 * Errors.
2829 */ 2830 */
2830 if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 2831 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2831 /* First we want to see if the MII Status Register reports 2832 /* First we want to see if the MII Status Register reports
2832 * link. If so, then we want to get the current speed/duplex 2833 * link. If so, then we want to get the current speed/duplex
2833 * of the PHY. 2834 * of the PHY.
2834 * Read the register twice since the link bit is sticky. 2835 * Read the register twice since the link bit is sticky.
2835 */ 2836 */
2836 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2837 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2837 if(ret_val) 2838 if (ret_val)
2838 return ret_val; 2839 return ret_val;
2839 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2840 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2840 if(ret_val) 2841 if (ret_val)
2841 return ret_val; 2842 return ret_val;
2842 2843
2843 if(phy_data & MII_SR_LINK_STATUS) { 2844 if (phy_data & MII_SR_LINK_STATUS) {
2844 hw->get_link_status = FALSE; 2845 hw->get_link_status = FALSE;
2845 /* Check if there was DownShift, must be checked immediately after 2846 /* Check if there was DownShift, must be checked immediately after
2846 * link-up */ 2847 * link-up */
@@ -2854,10 +2855,10 @@ e1000_check_for_link(struct e1000_hw *hw)
2854 * happen due to the execution of this workaround. 2855 * happen due to the execution of this workaround.
2855 */ 2856 */
2856 2857
2857 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && 2858 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2858 (!hw->autoneg) && 2859 (!hw->autoneg) &&
2859 (hw->forced_speed_duplex == e1000_10_full || 2860 (hw->forced_speed_duplex == e1000_10_full ||
2860 hw->forced_speed_duplex == e1000_10_half)) { 2861 hw->forced_speed_duplex == e1000_10_half)) {
2861 E1000_WRITE_REG(hw, IMC, 0xffffffff); 2862 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2862 ret_val = e1000_polarity_reversal_workaround(hw); 2863 ret_val = e1000_polarity_reversal_workaround(hw);
2863 icr = E1000_READ_REG(hw, ICR); 2864 icr = E1000_READ_REG(hw, ICR);
@@ -2874,7 +2875,7 @@ e1000_check_for_link(struct e1000_hw *hw)
2874 /* If we are forcing speed/duplex, then we simply return since 2875 /* If we are forcing speed/duplex, then we simply return since
2875 * we have already determined whether we have link or not. 2876 * we have already determined whether we have link or not.
2876 */ 2877 */
2877 if(!hw->autoneg) return -E1000_ERR_CONFIG; 2878 if (!hw->autoneg) return -E1000_ERR_CONFIG;
2878 2879
2879 /* optimize the dsp settings for the igp phy */ 2880 /* optimize the dsp settings for the igp phy */
2880 e1000_config_dsp_after_link_change(hw, TRUE); 2881 e1000_config_dsp_after_link_change(hw, TRUE);
@@ -2887,11 +2888,11 @@ e1000_check_for_link(struct e1000_hw *hw)
2887 * speed/duplex on the MAC to the current PHY speed/duplex 2888 * speed/duplex on the MAC to the current PHY speed/duplex
2888 * settings. 2889 * settings.
2889 */ 2890 */
2890 if(hw->mac_type >= e1000_82544) 2891 if (hw->mac_type >= e1000_82544)
2891 e1000_config_collision_dist(hw); 2892 e1000_config_collision_dist(hw);
2892 else { 2893 else {
2893 ret_val = e1000_config_mac_to_phy(hw); 2894 ret_val = e1000_config_mac_to_phy(hw);
2894 if(ret_val) { 2895 if (ret_val) {
2895 DEBUGOUT("Error configuring MAC to PHY settings\n"); 2896 DEBUGOUT("Error configuring MAC to PHY settings\n");
2896 return ret_val; 2897 return ret_val;
2897 } 2898 }
@@ -2902,7 +2903,7 @@ e1000_check_for_link(struct e1000_hw *hw)
2902 * have had to re-autoneg with a different link partner. 2903 * have had to re-autoneg with a different link partner.
2903 */ 2904 */
2904 ret_val = e1000_config_fc_after_link_up(hw); 2905 ret_val = e1000_config_fc_after_link_up(hw);
2905 if(ret_val) { 2906 if (ret_val) {
2906 DEBUGOUT("Error configuring flow control\n"); 2907 DEBUGOUT("Error configuring flow control\n");
2907 return ret_val; 2908 return ret_val;
2908 } 2909 }
@@ -2914,7 +2915,7 @@ e1000_check_for_link(struct e1000_hw *hw)
2914 * at gigabit speed, then TBI compatibility is not needed. If we are 2915 * at gigabit speed, then TBI compatibility is not needed. If we are
2915 * at gigabit speed, we turn on TBI compatibility. 2916 * at gigabit speed, we turn on TBI compatibility.
2916 */ 2917 */
2917 if(hw->tbi_compatibility_en) { 2918 if (hw->tbi_compatibility_en) {
2918 uint16_t speed, duplex; 2919 uint16_t speed, duplex;
2919 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 2920 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2920 if (ret_val) { 2921 if (ret_val) {
@@ -2925,7 +2926,7 @@ e1000_check_for_link(struct e1000_hw *hw)
2925 /* If link speed is not set to gigabit speed, we do not need 2926 /* If link speed is not set to gigabit speed, we do not need
2926 * to enable TBI compatibility. 2927 * to enable TBI compatibility.
2927 */ 2928 */
2928 if(hw->tbi_compatibility_on) { 2929 if (hw->tbi_compatibility_on) {
2929 /* If we previously were in the mode, turn it off. */ 2930 /* If we previously were in the mode, turn it off. */
2930 rctl = E1000_READ_REG(hw, RCTL); 2931 rctl = E1000_READ_REG(hw, RCTL);
2931 rctl &= ~E1000_RCTL_SBP; 2932 rctl &= ~E1000_RCTL_SBP;
@@ -2938,7 +2939,7 @@ e1000_check_for_link(struct e1000_hw *hw)
2938 * packets. Some frames have an additional byte on the end and 2939 * packets. Some frames have an additional byte on the end and
2939 * will look like CRC errors to to the hardware. 2940 * will look like CRC errors to to the hardware.
2940 */ 2941 */
2941 if(!hw->tbi_compatibility_on) { 2942 if (!hw->tbi_compatibility_on) {
2942 hw->tbi_compatibility_on = TRUE; 2943 hw->tbi_compatibility_on = TRUE;
2943 rctl = E1000_READ_REG(hw, RCTL); 2944 rctl = E1000_READ_REG(hw, RCTL);
2944 rctl |= E1000_RCTL_SBP; 2945 rctl |= E1000_RCTL_SBP;
@@ -2954,12 +2955,12 @@ e1000_check_for_link(struct e1000_hw *hw)
2954 * auto-negotiation time to complete, in case the cable was just plugged 2955 * auto-negotiation time to complete, in case the cable was just plugged
2955 * in. The autoneg_failed flag does this. 2956 * in. The autoneg_failed flag does this.
2956 */ 2957 */
2957 else if((((hw->media_type == e1000_media_type_fiber) && 2958 else if ((((hw->media_type == e1000_media_type_fiber) &&
2958 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || 2959 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2959 (hw->media_type == e1000_media_type_internal_serdes)) && 2960 (hw->media_type == e1000_media_type_internal_serdes)) &&
2960 (!(status & E1000_STATUS_LU)) && 2961 (!(status & E1000_STATUS_LU)) &&
2961 (!(rxcw & E1000_RXCW_C))) { 2962 (!(rxcw & E1000_RXCW_C))) {
2962 if(hw->autoneg_failed == 0) { 2963 if (hw->autoneg_failed == 0) {
2963 hw->autoneg_failed = 1; 2964 hw->autoneg_failed = 1;
2964 return 0; 2965 return 0;
2965 } 2966 }
@@ -2975,7 +2976,7 @@ e1000_check_for_link(struct e1000_hw *hw)
2975 2976
2976 /* Configure Flow Control after forcing link up. */ 2977 /* Configure Flow Control after forcing link up. */
2977 ret_val = e1000_config_fc_after_link_up(hw); 2978 ret_val = e1000_config_fc_after_link_up(hw);
2978 if(ret_val) { 2979 if (ret_val) {
2979 DEBUGOUT("Error configuring flow control\n"); 2980 DEBUGOUT("Error configuring flow control\n");
2980 return ret_val; 2981 return ret_val;
2981 } 2982 }
@@ -2985,9 +2986,9 @@ e1000_check_for_link(struct e1000_hw *hw)
2985 * Device Control register in an attempt to auto-negotiate with our link 2986 * Device Control register in an attempt to auto-negotiate with our link
2986 * partner. 2987 * partner.
2987 */ 2988 */
2988 else if(((hw->media_type == e1000_media_type_fiber) || 2989 else if (((hw->media_type == e1000_media_type_fiber) ||
2989 (hw->media_type == e1000_media_type_internal_serdes)) && 2990 (hw->media_type == e1000_media_type_internal_serdes)) &&
2990 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 2991 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2991 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 2992 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
2992 E1000_WRITE_REG(hw, TXCW, hw->txcw); 2993 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2993 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 2994 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
@@ -2997,12 +2998,12 @@ e1000_check_for_link(struct e1000_hw *hw)
2997 /* If we force link for non-auto-negotiation switch, check link status 2998 /* If we force link for non-auto-negotiation switch, check link status
2998 * based on MAC synchronization for internal serdes media type. 2999 * based on MAC synchronization for internal serdes media type.
2999 */ 3000 */
3000 else if((hw->media_type == e1000_media_type_internal_serdes) && 3001 else if ((hw->media_type == e1000_media_type_internal_serdes) &&
3001 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 3002 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3002 /* SYNCH bit and IV bit are sticky. */ 3003 /* SYNCH bit and IV bit are sticky. */
3003 udelay(10); 3004 udelay(10);
3004 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { 3005 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
3005 if(!(rxcw & E1000_RXCW_IV)) { 3006 if (!(rxcw & E1000_RXCW_IV)) {
3006 hw->serdes_link_down = FALSE; 3007 hw->serdes_link_down = FALSE;
3007 DEBUGOUT("SERDES: Link is up.\n"); 3008 DEBUGOUT("SERDES: Link is up.\n");
3008 } 3009 }
@@ -3011,8 +3012,8 @@ e1000_check_for_link(struct e1000_hw *hw)
3011 DEBUGOUT("SERDES: Link is down.\n"); 3012 DEBUGOUT("SERDES: Link is down.\n");
3012 } 3013 }
3013 } 3014 }
3014 if((hw->media_type == e1000_media_type_internal_serdes) && 3015 if ((hw->media_type == e1000_media_type_internal_serdes) &&
3015 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 3016 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3016 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS)); 3017 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
3017 } 3018 }
3018 return E1000_SUCCESS; 3019 return E1000_SUCCESS;
@@ -3036,12 +3037,12 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
3036 3037
3037 DEBUGFUNC("e1000_get_speed_and_duplex"); 3038 DEBUGFUNC("e1000_get_speed_and_duplex");
3038 3039
3039 if(hw->mac_type >= e1000_82543) { 3040 if (hw->mac_type >= e1000_82543) {
3040 status = E1000_READ_REG(hw, STATUS); 3041 status = E1000_READ_REG(hw, STATUS);
3041 if(status & E1000_STATUS_SPEED_1000) { 3042 if (status & E1000_STATUS_SPEED_1000) {
3042 *speed = SPEED_1000; 3043 *speed = SPEED_1000;
3043 DEBUGOUT("1000 Mbs, "); 3044 DEBUGOUT("1000 Mbs, ");
3044 } else if(status & E1000_STATUS_SPEED_100) { 3045 } else if (status & E1000_STATUS_SPEED_100) {
3045 *speed = SPEED_100; 3046 *speed = SPEED_100;
3046 DEBUGOUT("100 Mbs, "); 3047 DEBUGOUT("100 Mbs, ");
3047 } else { 3048 } else {
@@ -3049,7 +3050,7 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
3049 DEBUGOUT("10 Mbs, "); 3050 DEBUGOUT("10 Mbs, ");
3050 } 3051 }
3051 3052
3052 if(status & E1000_STATUS_FD) { 3053 if (status & E1000_STATUS_FD) {
3053 *duplex = FULL_DUPLEX; 3054 *duplex = FULL_DUPLEX;
3054 DEBUGOUT("Full Duplex\n"); 3055 DEBUGOUT("Full Duplex\n");
3055 } else { 3056 } else {
@@ -3066,18 +3067,18 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
3066 * if it is operating at half duplex. Here we set the duplex settings to 3067 * if it is operating at half duplex. Here we set the duplex settings to
3067 * match the duplex in the link partner's capabilities. 3068 * match the duplex in the link partner's capabilities.
3068 */ 3069 */
3069 if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { 3070 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3070 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 3071 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3071 if(ret_val) 3072 if (ret_val)
3072 return ret_val; 3073 return ret_val;
3073 3074
3074 if(!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 3075 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3075 *duplex = HALF_DUPLEX; 3076 *duplex = HALF_DUPLEX;
3076 else { 3077 else {
3077 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); 3078 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
3078 if(ret_val) 3079 if (ret_val)
3079 return ret_val; 3080 return ret_val;
3080 if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || 3081 if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
3081 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 3082 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3082 *duplex = HALF_DUPLEX; 3083 *duplex = HALF_DUPLEX;
3083 } 3084 }
@@ -3118,17 +3119,17 @@ e1000_wait_autoneg(struct e1000_hw *hw)
3118 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 3119 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3119 3120
3120 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 3121 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3121 for(i = PHY_AUTO_NEG_TIME; i > 0; i--) { 3122 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3122 /* Read the MII Status Register and wait for Auto-Neg 3123 /* Read the MII Status Register and wait for Auto-Neg
3123 * Complete bit to be set. 3124 * Complete bit to be set.
3124 */ 3125 */
3125 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3126 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3126 if(ret_val) 3127 if (ret_val)
3127 return ret_val; 3128 return ret_val;
3128 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3129 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3129 if(ret_val) 3130 if (ret_val)
3130 return ret_val; 3131 return ret_val;
3131 if(phy_data & MII_SR_AUTONEG_COMPLETE) { 3132 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3132 return E1000_SUCCESS; 3133 return E1000_SUCCESS;
3133 } 3134 }
3134 msec_delay(100); 3135 msec_delay(100);
@@ -3201,14 +3202,16 @@ e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3201 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 3202 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3202 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 3203 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3203 3204
3204 while(mask) { 3205 while (mask) {
3205 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 3206 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3206 * then raising and lowering the Management Data Clock. A "0" is 3207 * then raising and lowering the Management Data Clock. A "0" is
3207 * shifted out to the PHY by setting the MDIO bit to "0" and then 3208 * shifted out to the PHY by setting the MDIO bit to "0" and then
3208 * raising and lowering the clock. 3209 * raising and lowering the clock.
3209 */ 3210 */
3210 if(data & mask) ctrl |= E1000_CTRL_MDIO; 3211 if (data & mask)
3211 else ctrl &= ~E1000_CTRL_MDIO; 3212 ctrl |= E1000_CTRL_MDIO;
3213 else
3214 ctrl &= ~E1000_CTRL_MDIO;
3212 3215
3213 E1000_WRITE_REG(hw, CTRL, ctrl); 3216 E1000_WRITE_REG(hw, CTRL, ctrl);
3214 E1000_WRITE_FLUSH(hw); 3217 E1000_WRITE_FLUSH(hw);
@@ -3259,12 +3262,13 @@ e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3259 e1000_raise_mdi_clk(hw, &ctrl); 3262 e1000_raise_mdi_clk(hw, &ctrl);
3260 e1000_lower_mdi_clk(hw, &ctrl); 3263 e1000_lower_mdi_clk(hw, &ctrl);
3261 3264
3262 for(data = 0, i = 0; i < 16; i++) { 3265 for (data = 0, i = 0; i < 16; i++) {
3263 data = data << 1; 3266 data = data << 1;
3264 e1000_raise_mdi_clk(hw, &ctrl); 3267 e1000_raise_mdi_clk(hw, &ctrl);
3265 ctrl = E1000_READ_REG(hw, CTRL); 3268 ctrl = E1000_READ_REG(hw, CTRL);
3266 /* Check to see if we shifted in a "1". */ 3269 /* Check to see if we shifted in a "1". */
3267 if(ctrl & E1000_CTRL_MDIO) data |= 1; 3270 if (ctrl & E1000_CTRL_MDIO)
3271 data |= 1;
3268 e1000_lower_mdi_clk(hw, &ctrl); 3272 e1000_lower_mdi_clk(hw, &ctrl);
3269 } 3273 }
3270 3274
@@ -3290,7 +3294,7 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3290 if (!hw->swfw_sync_present) 3294 if (!hw->swfw_sync_present)
3291 return e1000_get_hw_eeprom_semaphore(hw); 3295 return e1000_get_hw_eeprom_semaphore(hw);
3292 3296
3293 while(timeout) { 3297 while (timeout) {
3294 if (e1000_get_hw_eeprom_semaphore(hw)) 3298 if (e1000_get_hw_eeprom_semaphore(hw))
3295 return -E1000_ERR_SWFW_SYNC; 3299 return -E1000_ERR_SWFW_SYNC;
3296 3300
@@ -3379,7 +3383,7 @@ e1000_read_phy_reg(struct e1000_hw *hw,
3379 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3383 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3380 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3384 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3381 (uint16_t)reg_addr); 3385 (uint16_t)reg_addr);
3382 if(ret_val) { 3386 if (ret_val) {
3383 e1000_swfw_sync_release(hw, swfw); 3387 e1000_swfw_sync_release(hw, swfw);
3384 return ret_val; 3388 return ret_val;
3385 } 3389 }
@@ -3424,12 +3428,12 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw,
3424 3428
3425 DEBUGFUNC("e1000_read_phy_reg_ex"); 3429 DEBUGFUNC("e1000_read_phy_reg_ex");
3426 3430
3427 if(reg_addr > MAX_PHY_REG_ADDRESS) { 3431 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3428 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 3432 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3429 return -E1000_ERR_PARAM; 3433 return -E1000_ERR_PARAM;
3430 } 3434 }
3431 3435
3432 if(hw->mac_type > e1000_82543) { 3436 if (hw->mac_type > e1000_82543) {
3433 /* Set up Op-code, Phy Address, and register address in the MDI 3437 /* Set up Op-code, Phy Address, and register address in the MDI
3434 * Control register. The MAC will take care of interfacing with the 3438 * Control register. The MAC will take care of interfacing with the
3435 * PHY to retrieve the desired data. 3439 * PHY to retrieve the desired data.
@@ -3441,16 +3445,16 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw,
3441 E1000_WRITE_REG(hw, MDIC, mdic); 3445 E1000_WRITE_REG(hw, MDIC, mdic);
3442 3446
3443 /* Poll the ready bit to see if the MDI read completed */ 3447 /* Poll the ready bit to see if the MDI read completed */
3444 for(i = 0; i < 64; i++) { 3448 for (i = 0; i < 64; i++) {
3445 udelay(50); 3449 udelay(50);
3446 mdic = E1000_READ_REG(hw, MDIC); 3450 mdic = E1000_READ_REG(hw, MDIC);
3447 if(mdic & E1000_MDIC_READY) break; 3451 if (mdic & E1000_MDIC_READY) break;
3448 } 3452 }
3449 if(!(mdic & E1000_MDIC_READY)) { 3453 if (!(mdic & E1000_MDIC_READY)) {
3450 DEBUGOUT("MDI Read did not complete\n"); 3454 DEBUGOUT("MDI Read did not complete\n");
3451 return -E1000_ERR_PHY; 3455 return -E1000_ERR_PHY;
3452 } 3456 }
3453 if(mdic & E1000_MDIC_ERROR) { 3457 if (mdic & E1000_MDIC_ERROR) {
3454 DEBUGOUT("MDI Error\n"); 3458 DEBUGOUT("MDI Error\n");
3455 return -E1000_ERR_PHY; 3459 return -E1000_ERR_PHY;
3456 } 3460 }
@@ -3519,7 +3523,7 @@ e1000_write_phy_reg(struct e1000_hw *hw,
3519 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3523 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3520 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3524 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3521 (uint16_t)reg_addr); 3525 (uint16_t)reg_addr);
3522 if(ret_val) { 3526 if (ret_val) {
3523 e1000_swfw_sync_release(hw, swfw); 3527 e1000_swfw_sync_release(hw, swfw);
3524 return ret_val; 3528 return ret_val;
3525 } 3529 }
@@ -3564,12 +3568,12 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw,
3564 3568
3565 DEBUGFUNC("e1000_write_phy_reg_ex"); 3569 DEBUGFUNC("e1000_write_phy_reg_ex");
3566 3570
3567 if(reg_addr > MAX_PHY_REG_ADDRESS) { 3571 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3568 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 3572 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3569 return -E1000_ERR_PARAM; 3573 return -E1000_ERR_PARAM;
3570 } 3574 }
3571 3575
3572 if(hw->mac_type > e1000_82543) { 3576 if (hw->mac_type > e1000_82543) {
3573 /* Set up Op-code, Phy Address, register address, and data intended 3577 /* Set up Op-code, Phy Address, register address, and data intended
3574 * for the PHY register in the MDI Control register. The MAC will take 3578 * for the PHY register in the MDI Control register. The MAC will take
3575 * care of interfacing with the PHY to send the desired data. 3579 * care of interfacing with the PHY to send the desired data.
@@ -3582,12 +3586,12 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw,
3582 E1000_WRITE_REG(hw, MDIC, mdic); 3586 E1000_WRITE_REG(hw, MDIC, mdic);
3583 3587
3584 /* Poll the ready bit to see if the MDI read completed */ 3588 /* Poll the ready bit to see if the MDI read completed */
3585 for(i = 0; i < 640; i++) { 3589 for (i = 0; i < 641; i++) {
3586 udelay(5); 3590 udelay(5);
3587 mdic = E1000_READ_REG(hw, MDIC); 3591 mdic = E1000_READ_REG(hw, MDIC);
3588 if(mdic & E1000_MDIC_READY) break; 3592 if (mdic & E1000_MDIC_READY) break;
3589 } 3593 }
3590 if(!(mdic & E1000_MDIC_READY)) { 3594 if (!(mdic & E1000_MDIC_READY)) {
3591 DEBUGOUT("MDI Write did not complete\n"); 3595 DEBUGOUT("MDI Write did not complete\n");
3592 return -E1000_ERR_PHY; 3596 return -E1000_ERR_PHY;
3593 } 3597 }
@@ -3699,7 +3703,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3699 3703
3700 DEBUGOUT("Resetting Phy...\n"); 3704 DEBUGOUT("Resetting Phy...\n");
3701 3705
3702 if(hw->mac_type > e1000_82543) { 3706 if (hw->mac_type > e1000_82543) {
3703 if ((hw->mac_type == e1000_80003es2lan) && 3707 if ((hw->mac_type == e1000_80003es2lan) &&
3704 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3708 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3705 swfw = E1000_SWFW_PHY1_SM; 3709 swfw = E1000_SWFW_PHY1_SM;
@@ -3747,7 +3751,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3747 } 3751 }
3748 udelay(150); 3752 udelay(150);
3749 3753
3750 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 3754 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3751 /* Configure activity LED after PHY reset */ 3755 /* Configure activity LED after PHY reset */
3752 led_ctrl = E1000_READ_REG(hw, LEDCTL); 3756 led_ctrl = E1000_READ_REG(hw, LEDCTL);
3753 led_ctrl &= IGP_ACTIVITY_LED_MASK; 3757 led_ctrl &= IGP_ACTIVITY_LED_MASK;
@@ -3757,14 +3761,13 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3757 3761
3758 /* Wait for FW to finish PHY configuration. */ 3762 /* Wait for FW to finish PHY configuration. */
3759 ret_val = e1000_get_phy_cfg_done(hw); 3763 ret_val = e1000_get_phy_cfg_done(hw);
3764 if (ret_val != E1000_SUCCESS)
3765 return ret_val;
3760 e1000_release_software_semaphore(hw); 3766 e1000_release_software_semaphore(hw);
3761 3767
3762 if ((hw->mac_type == e1000_ich8lan) && 3768 if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
3763 (hw->phy_type == e1000_phy_igp_3)) { 3769 ret_val = e1000_init_lcd_from_nvm(hw);
3764 ret_val = e1000_init_lcd_from_nvm(hw); 3770
3765 if (ret_val)
3766 return ret_val;
3767 }
3768 return ret_val; 3771 return ret_val;
3769} 3772}
3770 3773
@@ -3795,25 +3798,25 @@ e1000_phy_reset(struct e1000_hw *hw)
3795 case e1000_82572: 3798 case e1000_82572:
3796 case e1000_ich8lan: 3799 case e1000_ich8lan:
3797 ret_val = e1000_phy_hw_reset(hw); 3800 ret_val = e1000_phy_hw_reset(hw);
3798 if(ret_val) 3801 if (ret_val)
3799 return ret_val; 3802 return ret_val;
3800 3803
3801 break; 3804 break;
3802 default: 3805 default:
3803 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 3806 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3804 if(ret_val) 3807 if (ret_val)
3805 return ret_val; 3808 return ret_val;
3806 3809
3807 phy_data |= MII_CR_RESET; 3810 phy_data |= MII_CR_RESET;
3808 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 3811 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3809 if(ret_val) 3812 if (ret_val)
3810 return ret_val; 3813 return ret_val;
3811 3814
3812 udelay(1); 3815 udelay(1);
3813 break; 3816 break;
3814 } 3817 }
3815 3818
3816 if(hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) 3819 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
3817 e1000_phy_init_script(hw); 3820 e1000_phy_init_script(hw);
3818 3821
3819 return E1000_SUCCESS; 3822 return E1000_SUCCESS;
@@ -3891,8 +3894,8 @@ e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3891 if (hw->kmrn_lock_loss_workaround_disabled) 3894 if (hw->kmrn_lock_loss_workaround_disabled)
3892 return E1000_SUCCESS; 3895 return E1000_SUCCESS;
3893 3896
3894 /* Make sure link is up before proceeding. If not just return. 3897 /* Make sure link is up before proceeding. If not just return.
3895 * Attempting this while link is negotiating fouls up link 3898 * Attempting this while link is negotiating fouled up link
3896 * stability */ 3899 * stability */
3897 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3900 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3898 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3901 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
@@ -3969,34 +3972,34 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
3969 hw->phy_id = (uint32_t) (phy_id_high << 16); 3972 hw->phy_id = (uint32_t) (phy_id_high << 16);
3970 udelay(20); 3973 udelay(20);
3971 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 3974 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
3972 if(ret_val) 3975 if (ret_val)
3973 return ret_val; 3976 return ret_val;
3974 3977
3975 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 3978 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
3976 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 3979 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
3977 3980
3978 switch(hw->mac_type) { 3981 switch (hw->mac_type) {
3979 case e1000_82543: 3982 case e1000_82543:
3980 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE; 3983 if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
3981 break; 3984 break;
3982 case e1000_82544: 3985 case e1000_82544:
3983 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE; 3986 if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
3984 break; 3987 break;
3985 case e1000_82540: 3988 case e1000_82540:
3986 case e1000_82545: 3989 case e1000_82545:
3987 case e1000_82545_rev_3: 3990 case e1000_82545_rev_3:
3988 case e1000_82546: 3991 case e1000_82546:
3989 case e1000_82546_rev_3: 3992 case e1000_82546_rev_3:
3990 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE; 3993 if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
3991 break; 3994 break;
3992 case e1000_82541: 3995 case e1000_82541:
3993 case e1000_82541_rev_2: 3996 case e1000_82541_rev_2:
3994 case e1000_82547: 3997 case e1000_82547:
3995 case e1000_82547_rev_2: 3998 case e1000_82547_rev_2:
3996 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; 3999 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
3997 break; 4000 break;
3998 case e1000_82573: 4001 case e1000_82573:
3999 if(hw->phy_id == M88E1111_I_PHY_ID) match = TRUE; 4002 if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
4000 break; 4003 break;
4001 case e1000_80003es2lan: 4004 case e1000_80003es2lan:
4002 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE; 4005 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
@@ -4035,14 +4038,14 @@ e1000_phy_reset_dsp(struct e1000_hw *hw)
4035 do { 4038 do {
4036 if (hw->phy_type != e1000_phy_gg82563) { 4039 if (hw->phy_type != e1000_phy_gg82563) {
4037 ret_val = e1000_write_phy_reg(hw, 29, 0x001d); 4040 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
4038 if(ret_val) break; 4041 if (ret_val) break;
4039 } 4042 }
4040 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); 4043 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
4041 if(ret_val) break; 4044 if (ret_val) break;
4042 ret_val = e1000_write_phy_reg(hw, 30, 0x0000); 4045 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
4043 if(ret_val) break; 4046 if (ret_val) break;
4044 ret_val = E1000_SUCCESS; 4047 ret_val = E1000_SUCCESS;
4045 } while(0); 4048 } while (0);
4046 4049
4047 return ret_val; 4050 return ret_val;
4048} 4051}
@@ -4053,7 +4056,7 @@ e1000_phy_reset_dsp(struct e1000_hw *hw)
4053* hw - Struct containing variables accessed by shared code 4056* hw - Struct containing variables accessed by shared code
4054* phy_info - PHY information structure 4057* phy_info - PHY information structure
4055******************************************************************************/ 4058******************************************************************************/
4056static int32_t 4059int32_t
4057e1000_phy_igp_get_info(struct e1000_hw *hw, 4060e1000_phy_igp_get_info(struct e1000_hw *hw,
4058 struct e1000_phy_info *phy_info) 4061 struct e1000_phy_info *phy_info)
4059{ 4062{
@@ -4074,23 +4077,23 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
4074 4077
4075 /* Check polarity status */ 4078 /* Check polarity status */
4076 ret_val = e1000_check_polarity(hw, &polarity); 4079 ret_val = e1000_check_polarity(hw, &polarity);
4077 if(ret_val) 4080 if (ret_val)
4078 return ret_val; 4081 return ret_val;
4079 4082
4080 phy_info->cable_polarity = polarity; 4083 phy_info->cable_polarity = polarity;
4081 4084
4082 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); 4085 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
4083 if(ret_val) 4086 if (ret_val)
4084 return ret_val; 4087 return ret_val;
4085 4088
4086 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >> 4089 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
4087 IGP01E1000_PSSR_MDIX_SHIFT; 4090 IGP01E1000_PSSR_MDIX_SHIFT;
4088 4091
4089 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 4092 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4090 IGP01E1000_PSSR_SPEED_1000MBPS) { 4093 IGP01E1000_PSSR_SPEED_1000MBPS) {
4091 /* Local/Remote Receiver Information are only valid at 1000 Mbps */ 4094 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
4092 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 4095 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4093 if(ret_val) 4096 if (ret_val)
4094 return ret_val; 4097 return ret_val;
4095 4098
4096 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> 4099 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
@@ -4100,19 +4103,19 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
4100 4103
4101 /* Get cable length */ 4104 /* Get cable length */
4102 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); 4105 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
4103 if(ret_val) 4106 if (ret_val)
4104 return ret_val; 4107 return ret_val;
4105 4108
4106 /* Translate to old method */ 4109 /* Translate to old method */
4107 average = (max_length + min_length) / 2; 4110 average = (max_length + min_length) / 2;
4108 4111
4109 if(average <= e1000_igp_cable_length_50) 4112 if (average <= e1000_igp_cable_length_50)
4110 phy_info->cable_length = e1000_cable_length_50; 4113 phy_info->cable_length = e1000_cable_length_50;
4111 else if(average <= e1000_igp_cable_length_80) 4114 else if (average <= e1000_igp_cable_length_80)
4112 phy_info->cable_length = e1000_cable_length_50_80; 4115 phy_info->cable_length = e1000_cable_length_50_80;
4113 else if(average <= e1000_igp_cable_length_110) 4116 else if (average <= e1000_igp_cable_length_110)
4114 phy_info->cable_length = e1000_cable_length_80_110; 4117 phy_info->cable_length = e1000_cable_length_80_110;
4115 else if(average <= e1000_igp_cable_length_140) 4118 else if (average <= e1000_igp_cable_length_140)
4116 phy_info->cable_length = e1000_cable_length_110_140; 4119 phy_info->cable_length = e1000_cable_length_110_140;
4117 else 4120 else
4118 phy_info->cable_length = e1000_cable_length_140; 4121 phy_info->cable_length = e1000_cable_length_140;
@@ -4188,7 +4191,7 @@ e1000_phy_m88_get_info(struct e1000_hw *hw,
4188 phy_info->downshift = (e1000_downshift)hw->speed_downgraded; 4191 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4189 4192
4190 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 4193 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
4191 if(ret_val) 4194 if (ret_val)
4192 return ret_val; 4195 return ret_val;
4193 4196
4194 phy_info->extended_10bt_distance = 4197 phy_info->extended_10bt_distance =
@@ -4200,12 +4203,12 @@ e1000_phy_m88_get_info(struct e1000_hw *hw,
4200 4203
4201 /* Check polarity status */ 4204 /* Check polarity status */
4202 ret_val = e1000_check_polarity(hw, &polarity); 4205 ret_val = e1000_check_polarity(hw, &polarity);
4203 if(ret_val) 4206 if (ret_val)
4204 return ret_val; 4207 return ret_val;
4205 phy_info->cable_polarity = polarity; 4208 phy_info->cable_polarity = polarity;
4206 4209
4207 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 4210 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
4208 if(ret_val) 4211 if (ret_val)
4209 return ret_val; 4212 return ret_val;
4210 4213
4211 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >> 4214 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
@@ -4228,7 +4231,7 @@ e1000_phy_m88_get_info(struct e1000_hw *hw,
4228 } 4231 }
4229 4232
4230 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 4233 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4231 if(ret_val) 4234 if (ret_val)
4232 return ret_val; 4235 return ret_val;
4233 4236
4234 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> 4237 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
@@ -4265,20 +4268,20 @@ e1000_phy_get_info(struct e1000_hw *hw,
4265 phy_info->local_rx = e1000_1000t_rx_status_undefined; 4268 phy_info->local_rx = e1000_1000t_rx_status_undefined;
4266 phy_info->remote_rx = e1000_1000t_rx_status_undefined; 4269 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
4267 4270
4268 if(hw->media_type != e1000_media_type_copper) { 4271 if (hw->media_type != e1000_media_type_copper) {
4269 DEBUGOUT("PHY info is only valid for copper media\n"); 4272 DEBUGOUT("PHY info is only valid for copper media\n");
4270 return -E1000_ERR_CONFIG; 4273 return -E1000_ERR_CONFIG;
4271 } 4274 }
4272 4275
4273 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 4276 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4274 if(ret_val) 4277 if (ret_val)
4275 return ret_val; 4278 return ret_val;
4276 4279
4277 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 4280 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4278 if(ret_val) 4281 if (ret_val)
4279 return ret_val; 4282 return ret_val;
4280 4283
4281 if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { 4284 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
4282 DEBUGOUT("PHY info is only valid if link is up\n"); 4285 DEBUGOUT("PHY info is only valid if link is up\n");
4283 return -E1000_ERR_CONFIG; 4286 return -E1000_ERR_CONFIG;
4284 } 4287 }
@@ -4298,7 +4301,7 @@ e1000_validate_mdi_setting(struct e1000_hw *hw)
4298{ 4301{
4299 DEBUGFUNC("e1000_validate_mdi_settings"); 4302 DEBUGFUNC("e1000_validate_mdi_settings");
4300 4303
4301 if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { 4304 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
4302 DEBUGOUT("Invalid MDI setting detected\n"); 4305 DEBUGOUT("Invalid MDI setting detected\n");
4303 hw->mdix = 1; 4306 hw->mdix = 1;
4304 return -E1000_ERR_CONFIG; 4307 return -E1000_ERR_CONFIG;
@@ -4345,7 +4348,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4345 eeprom->type = e1000_eeprom_microwire; 4348 eeprom->type = e1000_eeprom_microwire;
4346 eeprom->opcode_bits = 3; 4349 eeprom->opcode_bits = 3;
4347 eeprom->delay_usec = 50; 4350 eeprom->delay_usec = 50;
4348 if(eecd & E1000_EECD_SIZE) { 4351 if (eecd & E1000_EECD_SIZE) {
4349 eeprom->word_size = 256; 4352 eeprom->word_size = 256;
4350 eeprom->address_bits = 8; 4353 eeprom->address_bits = 8;
4351 } else { 4354 } else {
@@ -4413,7 +4416,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4413 } 4416 }
4414 eeprom->use_eerd = TRUE; 4417 eeprom->use_eerd = TRUE;
4415 eeprom->use_eewr = TRUE; 4418 eeprom->use_eewr = TRUE;
4416 if(e1000_is_onboard_nvm_eeprom(hw) == FALSE) { 4419 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
4417 eeprom->type = e1000_eeprom_flash; 4420 eeprom->type = e1000_eeprom_flash;
4418 eeprom->word_size = 2048; 4421 eeprom->word_size = 2048;
4419 4422
@@ -4474,17 +4477,17 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4474 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to 4477 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4475 * 32KB (incremented by powers of 2). 4478 * 32KB (incremented by powers of 2).
4476 */ 4479 */
4477 if(hw->mac_type <= e1000_82547_rev_2) { 4480 if (hw->mac_type <= e1000_82547_rev_2) {
4478 /* Set to default value for initial eeprom read. */ 4481 /* Set to default value for initial eeprom read. */
4479 eeprom->word_size = 64; 4482 eeprom->word_size = 64;
4480 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); 4483 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
4481 if(ret_val) 4484 if (ret_val)
4482 return ret_val; 4485 return ret_val;
4483 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; 4486 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4484 /* 256B eeprom size was not supported in earlier hardware, so we 4487 /* 256B eeprom size was not supported in earlier hardware, so we
4485 * bump eeprom_size up one to ensure that "1" (which maps to 256B) 4488 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4486 * is never the result used in the shifting logic below. */ 4489 * is never the result used in the shifting logic below. */
4487 if(eeprom_size) 4490 if (eeprom_size)
4488 eeprom_size++; 4491 eeprom_size++;
4489 } else { 4492 } else {
4490 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >> 4493 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
@@ -4569,7 +4572,7 @@ e1000_shift_out_ee_bits(struct e1000_hw *hw,
4569 */ 4572 */
4570 eecd &= ~E1000_EECD_DI; 4573 eecd &= ~E1000_EECD_DI;
4571 4574
4572 if(data & mask) 4575 if (data & mask)
4573 eecd |= E1000_EECD_DI; 4576 eecd |= E1000_EECD_DI;
4574 4577
4575 E1000_WRITE_REG(hw, EECD, eecd); 4578 E1000_WRITE_REG(hw, EECD, eecd);
@@ -4582,7 +4585,7 @@ e1000_shift_out_ee_bits(struct e1000_hw *hw,
4582 4585
4583 mask = mask >> 1; 4586 mask = mask >> 1;
4584 4587
4585 } while(mask); 4588 } while (mask);
4586 4589
4587 /* We leave the "DI" bit set to "0" when we leave this routine. */ 4590 /* We leave the "DI" bit set to "0" when we leave this routine. */
4588 eecd &= ~E1000_EECD_DI; 4591 eecd &= ~E1000_EECD_DI;
@@ -4614,14 +4617,14 @@ e1000_shift_in_ee_bits(struct e1000_hw *hw,
4614 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 4617 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4615 data = 0; 4618 data = 0;
4616 4619
4617 for(i = 0; i < count; i++) { 4620 for (i = 0; i < count; i++) {
4618 data = data << 1; 4621 data = data << 1;
4619 e1000_raise_ee_clk(hw, &eecd); 4622 e1000_raise_ee_clk(hw, &eecd);
4620 4623
4621 eecd = E1000_READ_REG(hw, EECD); 4624 eecd = E1000_READ_REG(hw, EECD);
4622 4625
4623 eecd &= ~(E1000_EECD_DI); 4626 eecd &= ~(E1000_EECD_DI);
4624 if(eecd & E1000_EECD_DO) 4627 if (eecd & E1000_EECD_DO)
4625 data |= 1; 4628 data |= 1;
4626 4629
4627 e1000_lower_ee_clk(hw, &eecd); 4630 e1000_lower_ee_clk(hw, &eecd);
@@ -4652,17 +4655,17 @@ e1000_acquire_eeprom(struct e1000_hw *hw)
4652 4655
4653 if (hw->mac_type != e1000_82573) { 4656 if (hw->mac_type != e1000_82573) {
4654 /* Request EEPROM Access */ 4657 /* Request EEPROM Access */
4655 if(hw->mac_type > e1000_82544) { 4658 if (hw->mac_type > e1000_82544) {
4656 eecd |= E1000_EECD_REQ; 4659 eecd |= E1000_EECD_REQ;
4657 E1000_WRITE_REG(hw, EECD, eecd); 4660 E1000_WRITE_REG(hw, EECD, eecd);
4658 eecd = E1000_READ_REG(hw, EECD); 4661 eecd = E1000_READ_REG(hw, EECD);
4659 while((!(eecd & E1000_EECD_GNT)) && 4662 while ((!(eecd & E1000_EECD_GNT)) &&
4660 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 4663 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4661 i++; 4664 i++;
4662 udelay(5); 4665 udelay(5);
4663 eecd = E1000_READ_REG(hw, EECD); 4666 eecd = E1000_READ_REG(hw, EECD);
4664 } 4667 }
4665 if(!(eecd & E1000_EECD_GNT)) { 4668 if (!(eecd & E1000_EECD_GNT)) {
4666 eecd &= ~E1000_EECD_REQ; 4669 eecd &= ~E1000_EECD_REQ;
4667 E1000_WRITE_REG(hw, EECD, eecd); 4670 E1000_WRITE_REG(hw, EECD, eecd);
4668 DEBUGOUT("Could not acquire EEPROM grant\n"); 4671 DEBUGOUT("Could not acquire EEPROM grant\n");
@@ -4705,7 +4708,7 @@ e1000_standby_eeprom(struct e1000_hw *hw)
4705 4708
4706 eecd = E1000_READ_REG(hw, EECD); 4709 eecd = E1000_READ_REG(hw, EECD);
4707 4710
4708 if(eeprom->type == e1000_eeprom_microwire) { 4711 if (eeprom->type == e1000_eeprom_microwire) {
4709 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 4712 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4710 E1000_WRITE_REG(hw, EECD, eecd); 4713 E1000_WRITE_REG(hw, EECD, eecd);
4711 E1000_WRITE_FLUSH(hw); 4714 E1000_WRITE_FLUSH(hw);
@@ -4728,7 +4731,7 @@ e1000_standby_eeprom(struct e1000_hw *hw)
4728 E1000_WRITE_REG(hw, EECD, eecd); 4731 E1000_WRITE_REG(hw, EECD, eecd);
4729 E1000_WRITE_FLUSH(hw); 4732 E1000_WRITE_FLUSH(hw);
4730 udelay(eeprom->delay_usec); 4733 udelay(eeprom->delay_usec);
4731 } else if(eeprom->type == e1000_eeprom_spi) { 4734 } else if (eeprom->type == e1000_eeprom_spi) {
4732 /* Toggle CS to flush commands */ 4735 /* Toggle CS to flush commands */
4733 eecd |= E1000_EECD_CS; 4736 eecd |= E1000_EECD_CS;
4734 E1000_WRITE_REG(hw, EECD, eecd); 4737 E1000_WRITE_REG(hw, EECD, eecd);
@@ -4762,7 +4765,7 @@ e1000_release_eeprom(struct e1000_hw *hw)
4762 E1000_WRITE_REG(hw, EECD, eecd); 4765 E1000_WRITE_REG(hw, EECD, eecd);
4763 4766
4764 udelay(hw->eeprom.delay_usec); 4767 udelay(hw->eeprom.delay_usec);
4765 } else if(hw->eeprom.type == e1000_eeprom_microwire) { 4768 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
4766 /* cleanup eeprom */ 4769 /* cleanup eeprom */
4767 4770
4768 /* CS on Microwire is active-high */ 4771 /* CS on Microwire is active-high */
@@ -4784,7 +4787,7 @@ e1000_release_eeprom(struct e1000_hw *hw)
4784 } 4787 }
4785 4788
4786 /* Stop requesting EEPROM access */ 4789 /* Stop requesting EEPROM access */
4787 if(hw->mac_type > e1000_82544) { 4790 if (hw->mac_type > e1000_82544) {
4788 eecd &= ~E1000_EECD_REQ; 4791 eecd &= ~E1000_EECD_REQ;
4789 E1000_WRITE_REG(hw, EECD, eecd); 4792 E1000_WRITE_REG(hw, EECD, eecd);
4790 } 4793 }
@@ -4822,12 +4825,12 @@ e1000_spi_eeprom_ready(struct e1000_hw *hw)
4822 retry_count += 5; 4825 retry_count += 5;
4823 4826
4824 e1000_standby_eeprom(hw); 4827 e1000_standby_eeprom(hw);
4825 } while(retry_count < EEPROM_MAX_RETRY_SPI); 4828 } while (retry_count < EEPROM_MAX_RETRY_SPI);
4826 4829
4827 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 4830 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
4828 * only 0-5mSec on 5V devices) 4831 * only 0-5mSec on 5V devices)
4829 */ 4832 */
4830 if(retry_count >= EEPROM_MAX_RETRY_SPI) { 4833 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
4831 DEBUGOUT("SPI EEPROM Status error\n"); 4834 DEBUGOUT("SPI EEPROM Status error\n");
4832 return -E1000_ERR_EEPROM; 4835 return -E1000_ERR_EEPROM;
4833 } 4836 }
@@ -4858,7 +4861,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
4858 /* A check for invalid values: offset too large, too many words, and not 4861 /* A check for invalid values: offset too large, too many words, and not
4859 * enough words. 4862 * enough words.
4860 */ 4863 */
4861 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || 4864 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4862 (words == 0)) { 4865 (words == 0)) {
4863 DEBUGOUT("\"words\" parameter out of bounds\n"); 4866 DEBUGOUT("\"words\" parameter out of bounds\n");
4864 return -E1000_ERR_EEPROM; 4867 return -E1000_ERR_EEPROM;
@@ -4866,7 +4869,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
4866 4869
4867 /* FLASH reads without acquiring the semaphore are safe */ 4870 /* FLASH reads without acquiring the semaphore are safe */
4868 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE && 4871 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
4869 hw->eeprom.use_eerd == FALSE) { 4872 hw->eeprom.use_eerd == FALSE) {
4870 switch (hw->mac_type) { 4873 switch (hw->mac_type) {
4871 case e1000_80003es2lan: 4874 case e1000_80003es2lan:
4872 break; 4875 break;
@@ -4893,7 +4896,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
4893 uint16_t word_in; 4896 uint16_t word_in;
4894 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 4897 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
4895 4898
4896 if(e1000_spi_eeprom_ready(hw)) { 4899 if (e1000_spi_eeprom_ready(hw)) {
4897 e1000_release_eeprom(hw); 4900 e1000_release_eeprom(hw);
4898 return -E1000_ERR_EEPROM; 4901 return -E1000_ERR_EEPROM;
4899 } 4902 }
@@ -4901,7 +4904,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
4901 e1000_standby_eeprom(hw); 4904 e1000_standby_eeprom(hw);
4902 4905
4903 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ 4906 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4904 if((eeprom->address_bits == 8) && (offset >= 128)) 4907 if ((eeprom->address_bits == 8) && (offset >= 128))
4905 read_opcode |= EEPROM_A8_OPCODE_SPI; 4908 read_opcode |= EEPROM_A8_OPCODE_SPI;
4906 4909
4907 /* Send the READ command (opcode + addr) */ 4910 /* Send the READ command (opcode + addr) */
@@ -4917,7 +4920,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
4917 word_in = e1000_shift_in_ee_bits(hw, 16); 4920 word_in = e1000_shift_in_ee_bits(hw, 16);
4918 data[i] = (word_in >> 8) | (word_in << 8); 4921 data[i] = (word_in >> 8) | (word_in << 8);
4919 } 4922 }
4920 } else if(eeprom->type == e1000_eeprom_microwire) { 4923 } else if (eeprom->type == e1000_eeprom_microwire) {
4921 for (i = 0; i < words; i++) { 4924 for (i = 0; i < words; i++) {
4922 /* Send the READ command (opcode + addr) */ 4925 /* Send the READ command (opcode + addr) */
4923 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, 4926 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
@@ -4962,7 +4965,7 @@ e1000_read_eeprom_eerd(struct e1000_hw *hw,
4962 E1000_WRITE_REG(hw, EERD, eerd); 4965 E1000_WRITE_REG(hw, EERD, eerd);
4963 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 4966 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
4964 4967
4965 if(error) { 4968 if (error) {
4966 break; 4969 break;
4967 } 4970 }
4968 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA); 4971 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
@@ -4999,7 +5002,7 @@ e1000_write_eeprom_eewr(struct e1000_hw *hw,
4999 E1000_EEPROM_RW_REG_START; 5002 E1000_EEPROM_RW_REG_START;
5000 5003
5001 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 5004 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5002 if(error) { 5005 if (error) {
5003 break; 5006 break;
5004 } 5007 }
5005 5008
@@ -5007,7 +5010,7 @@ e1000_write_eeprom_eewr(struct e1000_hw *hw,
5007 5010
5008 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 5011 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5009 5012
5010 if(error) { 5013 if (error) {
5011 break; 5014 break;
5012 } 5015 }
5013 } 5016 }
@@ -5028,13 +5031,13 @@ e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5028 uint32_t i, reg = 0; 5031 uint32_t i, reg = 0;
5029 int32_t done = E1000_ERR_EEPROM; 5032 int32_t done = E1000_ERR_EEPROM;
5030 5033
5031 for(i = 0; i < attempts; i++) { 5034 for (i = 0; i < attempts; i++) {
5032 if(eerd == E1000_EEPROM_POLL_READ) 5035 if (eerd == E1000_EEPROM_POLL_READ)
5033 reg = E1000_READ_REG(hw, EERD); 5036 reg = E1000_READ_REG(hw, EERD);
5034 else 5037 else
5035 reg = E1000_READ_REG(hw, EEWR); 5038 reg = E1000_READ_REG(hw, EEWR);
5036 5039
5037 if(reg & E1000_EEPROM_RW_REG_DONE) { 5040 if (reg & E1000_EEPROM_RW_REG_DONE) {
5038 done = E1000_SUCCESS; 5041 done = E1000_SUCCESS;
5039 break; 5042 break;
5040 } 5043 }
@@ -5066,7 +5069,7 @@ e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5066 eecd = ((eecd >> 15) & 0x03); 5069 eecd = ((eecd >> 15) & 0x03);
5067 5070
5068 /* If both bits are set, device is Flash type */ 5071 /* If both bits are set, device is Flash type */
5069 if(eecd == 0x03) { 5072 if (eecd == 0x03) {
5070 return FALSE; 5073 return FALSE;
5071 } 5074 }
5072 } 5075 }
@@ -5131,7 +5134,7 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5131 checksum += eeprom_data; 5134 checksum += eeprom_data;
5132 } 5135 }
5133 5136
5134 if(checksum == (uint16_t) EEPROM_SUM) 5137 if (checksum == (uint16_t) EEPROM_SUM)
5135 return E1000_SUCCESS; 5138 return E1000_SUCCESS;
5136 else { 5139 else {
5137 DEBUGOUT("EEPROM Checksum Invalid\n"); 5140 DEBUGOUT("EEPROM Checksum Invalid\n");
@@ -5156,15 +5159,15 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw)
5156 5159
5157 DEBUGFUNC("e1000_update_eeprom_checksum"); 5160 DEBUGFUNC("e1000_update_eeprom_checksum");
5158 5161
5159 for(i = 0; i < EEPROM_CHECKSUM_REG; i++) { 5162 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
5160 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 5163 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5161 DEBUGOUT("EEPROM Read Error\n"); 5164 DEBUGOUT("EEPROM Read Error\n");
5162 return -E1000_ERR_EEPROM; 5165 return -E1000_ERR_EEPROM;
5163 } 5166 }
5164 checksum += eeprom_data; 5167 checksum += eeprom_data;
5165 } 5168 }
5166 checksum = (uint16_t) EEPROM_SUM - checksum; 5169 checksum = (uint16_t) EEPROM_SUM - checksum;
5167 if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 5170 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
5168 DEBUGOUT("EEPROM Write Error\n"); 5171 DEBUGOUT("EEPROM Write Error\n");
5169 return -E1000_ERR_EEPROM; 5172 return -E1000_ERR_EEPROM;
5170 } else if (hw->eeprom.type == e1000_eeprom_flash) { 5173 } else if (hw->eeprom.type == e1000_eeprom_flash) {
@@ -5206,14 +5209,14 @@ e1000_write_eeprom(struct e1000_hw *hw,
5206 /* A check for invalid values: offset too large, too many words, and not 5209 /* A check for invalid values: offset too large, too many words, and not
5207 * enough words. 5210 * enough words.
5208 */ 5211 */
5209 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || 5212 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
5210 (words == 0)) { 5213 (words == 0)) {
5211 DEBUGOUT("\"words\" parameter out of bounds\n"); 5214 DEBUGOUT("\"words\" parameter out of bounds\n");
5212 return -E1000_ERR_EEPROM; 5215 return -E1000_ERR_EEPROM;
5213 } 5216 }
5214 5217
5215 /* 82573 writes only through eewr */ 5218 /* 82573 writes only through eewr */
5216 if(eeprom->use_eewr == TRUE) 5219 if (eeprom->use_eewr == TRUE)
5217 return e1000_write_eeprom_eewr(hw, offset, words, data); 5220 return e1000_write_eeprom_eewr(hw, offset, words, data);
5218 5221
5219 if (eeprom->type == e1000_eeprom_ich8) 5222 if (eeprom->type == e1000_eeprom_ich8)
@@ -5223,7 +5226,7 @@ e1000_write_eeprom(struct e1000_hw *hw,
5223 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 5226 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5224 return -E1000_ERR_EEPROM; 5227 return -E1000_ERR_EEPROM;
5225 5228
5226 if(eeprom->type == e1000_eeprom_microwire) { 5229 if (eeprom->type == e1000_eeprom_microwire) {
5227 status = e1000_write_eeprom_microwire(hw, offset, words, data); 5230 status = e1000_write_eeprom_microwire(hw, offset, words, data);
5228 } else { 5231 } else {
5229 status = e1000_write_eeprom_spi(hw, offset, words, data); 5232 status = e1000_write_eeprom_spi(hw, offset, words, data);
@@ -5259,7 +5262,7 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
5259 while (widx < words) { 5262 while (widx < words) {
5260 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; 5263 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
5261 5264
5262 if(e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; 5265 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
5263 5266
5264 e1000_standby_eeprom(hw); 5267 e1000_standby_eeprom(hw);
5265 5268
@@ -5270,7 +5273,7 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
5270 e1000_standby_eeprom(hw); 5273 e1000_standby_eeprom(hw);
5271 5274
5272 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ 5275 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
5273 if((eeprom->address_bits == 8) && (offset >= 128)) 5276 if ((eeprom->address_bits == 8) && (offset >= 128))
5274 write_opcode |= EEPROM_A8_OPCODE_SPI; 5277 write_opcode |= EEPROM_A8_OPCODE_SPI;
5275 5278
5276 /* Send the Write command (8-bit opcode + addr) */ 5279 /* Send the Write command (8-bit opcode + addr) */
@@ -5292,7 +5295,7 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
5292 * operation, while the smaller eeproms are capable of an 8-byte 5295 * operation, while the smaller eeproms are capable of an 8-byte
5293 * PAGE WRITE operation. Break the inner loop to pass new address 5296 * PAGE WRITE operation. Break the inner loop to pass new address
5294 */ 5297 */
5295 if((((offset + widx)*2) % eeprom->page_size) == 0) { 5298 if ((((offset + widx)*2) % eeprom->page_size) == 0) {
5296 e1000_standby_eeprom(hw); 5299 e1000_standby_eeprom(hw);
5297 break; 5300 break;
5298 } 5301 }
@@ -5358,12 +5361,12 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw,
5358 * signal that the command has been completed by raising the DO signal. 5361 * signal that the command has been completed by raising the DO signal.
5359 * If DO does not go high in 10 milliseconds, then error out. 5362 * If DO does not go high in 10 milliseconds, then error out.
5360 */ 5363 */
5361 for(i = 0; i < 200; i++) { 5364 for (i = 0; i < 200; i++) {
5362 eecd = E1000_READ_REG(hw, EECD); 5365 eecd = E1000_READ_REG(hw, EECD);
5363 if(eecd & E1000_EECD_DO) break; 5366 if (eecd & E1000_EECD_DO) break;
5364 udelay(50); 5367 udelay(50);
5365 } 5368 }
5366 if(i == 200) { 5369 if (i == 200) {
5367 DEBUGOUT("EEPROM Write did not complete\n"); 5370 DEBUGOUT("EEPROM Write did not complete\n");
5368 return -E1000_ERR_EEPROM; 5371 return -E1000_ERR_EEPROM;
5369 } 5372 }
@@ -5554,40 +5557,6 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5554} 5557}
5555 5558
5556/****************************************************************************** 5559/******************************************************************************
5557 * Reads the adapter's part number from the EEPROM
5558 *
5559 * hw - Struct containing variables accessed by shared code
5560 * part_num - Adapter's part number
5561 *****************************************************************************/
5562int32_t
5563e1000_read_part_num(struct e1000_hw *hw,
5564 uint32_t *part_num)
5565{
5566 uint16_t offset = EEPROM_PBA_BYTE_1;
5567 uint16_t eeprom_data;
5568
5569 DEBUGFUNC("e1000_read_part_num");
5570
5571 /* Get word 0 from EEPROM */
5572 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5573 DEBUGOUT("EEPROM Read Error\n");
5574 return -E1000_ERR_EEPROM;
5575 }
5576 /* Save word 0 in upper half of part_num */
5577 *part_num = (uint32_t) (eeprom_data << 16);
5578
5579 /* Get word 1 from EEPROM */
5580 if(e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
5581 DEBUGOUT("EEPROM Read Error\n");
5582 return -E1000_ERR_EEPROM;
5583 }
5584 /* Save word 1 in lower half of part_num */
5585 *part_num |= eeprom_data;
5586
5587 return E1000_SUCCESS;
5588}
5589
5590/******************************************************************************
5591 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 5560 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5592 * second function of dual function devices 5561 * second function of dual function devices
5593 * 5562 *
@@ -5601,9 +5570,9 @@ e1000_read_mac_addr(struct e1000_hw * hw)
5601 5570
5602 DEBUGFUNC("e1000_read_mac_addr"); 5571 DEBUGFUNC("e1000_read_mac_addr");
5603 5572
5604 for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 5573 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
5605 offset = i >> 1; 5574 offset = i >> 1;
5606 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 5575 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5607 DEBUGOUT("EEPROM Read Error\n"); 5576 DEBUGOUT("EEPROM Read Error\n");
5608 return -E1000_ERR_EEPROM; 5577 return -E1000_ERR_EEPROM;
5609 } 5578 }
@@ -5618,12 +5587,12 @@ e1000_read_mac_addr(struct e1000_hw * hw)
5618 case e1000_82546_rev_3: 5587 case e1000_82546_rev_3:
5619 case e1000_82571: 5588 case e1000_82571:
5620 case e1000_80003es2lan: 5589 case e1000_80003es2lan:
5621 if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 5590 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
5622 hw->perm_mac_addr[5] ^= 0x01; 5591 hw->perm_mac_addr[5] ^= 0x01;
5623 break; 5592 break;
5624 } 5593 }
5625 5594
5626 for(i = 0; i < NODE_ADDRESS_SIZE; i++) 5595 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
5627 hw->mac_addr[i] = hw->perm_mac_addr[i]; 5596 hw->mac_addr[i] = hw->perm_mac_addr[i];
5628 return E1000_SUCCESS; 5597 return E1000_SUCCESS;
5629} 5598}
@@ -5662,7 +5631,7 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
5662 5631
5663 /* Zero out the other 15 receive addresses. */ 5632 /* Zero out the other 15 receive addresses. */
5664 DEBUGOUT("Clearing RAR[1-15]\n"); 5633 DEBUGOUT("Clearing RAR[1-15]\n");
5665 for(i = 1; i < rar_num; i++) { 5634 for (i = 1; i < rar_num; i++) {
5666 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 5635 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5667 E1000_WRITE_FLUSH(hw); 5636 E1000_WRITE_FLUSH(hw);
5668 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 5637 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
@@ -5713,7 +5682,7 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
5713 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) 5682 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5714 num_rar_entry -= 1; 5683 num_rar_entry -= 1;
5715 5684
5716 for(i = rar_used_count; i < num_rar_entry; i++) { 5685 for (i = rar_used_count; i < num_rar_entry; i++) {
5717 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 5686 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5718 E1000_WRITE_FLUSH(hw); 5687 E1000_WRITE_FLUSH(hw);
5719 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 5688 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
@@ -5725,13 +5694,13 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
5725 num_mta_entry = E1000_NUM_MTA_REGISTERS; 5694 num_mta_entry = E1000_NUM_MTA_REGISTERS;
5726 if (hw->mac_type == e1000_ich8lan) 5695 if (hw->mac_type == e1000_ich8lan)
5727 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN; 5696 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN;
5728 for(i = 0; i < num_mta_entry; i++) { 5697 for (i = 0; i < num_mta_entry; i++) {
5729 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 5698 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
5730 E1000_WRITE_FLUSH(hw); 5699 E1000_WRITE_FLUSH(hw);
5731 } 5700 }
5732 5701
5733 /* Add the new addresses */ 5702 /* Add the new addresses */
5734 for(i = 0; i < mc_addr_count; i++) { 5703 for (i = 0; i < mc_addr_count; i++) {
5735 DEBUGOUT(" Adding the multicast addresses:\n"); 5704 DEBUGOUT(" Adding the multicast addresses:\n");
5736 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, 5705 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
5737 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], 5706 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
@@ -5863,7 +5832,7 @@ e1000_mta_set(struct e1000_hw *hw,
5863 * in the MTA, save off the previous entry before writing and 5832 * in the MTA, save off the previous entry before writing and
5864 * restore the old value after writing. 5833 * restore the old value after writing.
5865 */ 5834 */
5866 if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) { 5835 if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
5867 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); 5836 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5868 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 5837 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5869 E1000_WRITE_FLUSH(hw); 5838 E1000_WRITE_FLUSH(hw);
@@ -6013,7 +5982,7 @@ e1000_id_led_init(struct e1000_hw * hw)
6013 5982
6014 DEBUGFUNC("e1000_id_led_init"); 5983 DEBUGFUNC("e1000_id_led_init");
6015 5984
6016 if(hw->mac_type < e1000_82540) { 5985 if (hw->mac_type < e1000_82540) {
6017 /* Nothing to do */ 5986 /* Nothing to do */
6018 return E1000_SUCCESS; 5987 return E1000_SUCCESS;
6019 } 5988 }
@@ -6023,7 +5992,7 @@ e1000_id_led_init(struct e1000_hw * hw)
6023 hw->ledctl_mode1 = hw->ledctl_default; 5992 hw->ledctl_mode1 = hw->ledctl_default;
6024 hw->ledctl_mode2 = hw->ledctl_default; 5993 hw->ledctl_mode2 = hw->ledctl_default;
6025 5994
6026 if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 5995 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
6027 DEBUGOUT("EEPROM Read Error\n"); 5996 DEBUGOUT("EEPROM Read Error\n");
6028 return -E1000_ERR_EEPROM; 5997 return -E1000_ERR_EEPROM;
6029 } 5998 }
@@ -6040,7 +6009,7 @@ e1000_id_led_init(struct e1000_hw * hw)
6040 } 6009 }
6041 for (i = 0; i < 4; i++) { 6010 for (i = 0; i < 4; i++) {
6042 temp = (eeprom_data >> (i << 2)) & led_mask; 6011 temp = (eeprom_data >> (i << 2)) & led_mask;
6043 switch(temp) { 6012 switch (temp) {
6044 case ID_LED_ON1_DEF2: 6013 case ID_LED_ON1_DEF2:
6045 case ID_LED_ON1_ON2: 6014 case ID_LED_ON1_ON2:
6046 case ID_LED_ON1_OFF2: 6015 case ID_LED_ON1_OFF2:
@@ -6057,7 +6026,7 @@ e1000_id_led_init(struct e1000_hw * hw)
6057 /* Do nothing */ 6026 /* Do nothing */
6058 break; 6027 break;
6059 } 6028 }
6060 switch(temp) { 6029 switch (temp) {
6061 case ID_LED_DEF1_ON2: 6030 case ID_LED_DEF1_ON2:
6062 case ID_LED_ON1_ON2: 6031 case ID_LED_ON1_ON2:
6063 case ID_LED_OFF1_ON2: 6032 case ID_LED_OFF1_ON2:
@@ -6091,7 +6060,7 @@ e1000_setup_led(struct e1000_hw *hw)
6091 6060
6092 DEBUGFUNC("e1000_setup_led"); 6061 DEBUGFUNC("e1000_setup_led");
6093 6062
6094 switch(hw->mac_type) { 6063 switch (hw->mac_type) {
6095 case e1000_82542_rev2_0: 6064 case e1000_82542_rev2_0:
6096 case e1000_82542_rev2_1: 6065 case e1000_82542_rev2_1:
6097 case e1000_82543: 6066 case e1000_82543:
@@ -6105,16 +6074,16 @@ e1000_setup_led(struct e1000_hw *hw)
6105 /* Turn off PHY Smart Power Down (if enabled) */ 6074 /* Turn off PHY Smart Power Down (if enabled) */
6106 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, 6075 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
6107 &hw->phy_spd_default); 6076 &hw->phy_spd_default);
6108 if(ret_val) 6077 if (ret_val)
6109 return ret_val; 6078 return ret_val;
6110 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 6079 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6111 (uint16_t)(hw->phy_spd_default & 6080 (uint16_t)(hw->phy_spd_default &
6112 ~IGP01E1000_GMII_SPD)); 6081 ~IGP01E1000_GMII_SPD));
6113 if(ret_val) 6082 if (ret_val)
6114 return ret_val; 6083 return ret_val;
6115 /* Fall Through */ 6084 /* Fall Through */
6116 default: 6085 default:
6117 if(hw->media_type == e1000_media_type_fiber) { 6086 if (hw->media_type == e1000_media_type_fiber) {
6118 ledctl = E1000_READ_REG(hw, LEDCTL); 6087 ledctl = E1000_READ_REG(hw, LEDCTL);
6119 /* Save current LEDCTL settings */ 6088 /* Save current LEDCTL settings */
6120 hw->ledctl_default = ledctl; 6089 hw->ledctl_default = ledctl;
@@ -6125,7 +6094,7 @@ e1000_setup_led(struct e1000_hw *hw)
6125 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 6094 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6126 E1000_LEDCTL_LED0_MODE_SHIFT); 6095 E1000_LEDCTL_LED0_MODE_SHIFT);
6127 E1000_WRITE_REG(hw, LEDCTL, ledctl); 6096 E1000_WRITE_REG(hw, LEDCTL, ledctl);
6128 } else if(hw->media_type == e1000_media_type_copper) 6097 } else if (hw->media_type == e1000_media_type_copper)
6129 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); 6098 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6130 break; 6099 break;
6131 } 6100 }
@@ -6133,6 +6102,7 @@ e1000_setup_led(struct e1000_hw *hw)
6133 return E1000_SUCCESS; 6102 return E1000_SUCCESS;
6134} 6103}
6135 6104
6105
6136/****************************************************************************** 6106/******************************************************************************
6137 * Used on 82571 and later Si that has LED blink bits. 6107 * Used on 82571 and later Si that has LED blink bits.
6138 * Callers must use their own timer and should have already called 6108 * Callers must use their own timer and should have already called
@@ -6183,7 +6153,7 @@ e1000_cleanup_led(struct e1000_hw *hw)
6183 6153
6184 DEBUGFUNC("e1000_cleanup_led"); 6154 DEBUGFUNC("e1000_cleanup_led");
6185 6155
6186 switch(hw->mac_type) { 6156 switch (hw->mac_type) {
6187 case e1000_82542_rev2_0: 6157 case e1000_82542_rev2_0:
6188 case e1000_82542_rev2_1: 6158 case e1000_82542_rev2_1:
6189 case e1000_82543: 6159 case e1000_82543:
@@ -6197,7 +6167,7 @@ e1000_cleanup_led(struct e1000_hw *hw)
6197 /* Turn on PHY Smart Power Down (if previously enabled) */ 6167 /* Turn on PHY Smart Power Down (if previously enabled) */
6198 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 6168 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6199 hw->phy_spd_default); 6169 hw->phy_spd_default);
6200 if(ret_val) 6170 if (ret_val)
6201 return ret_val; 6171 return ret_val;
6202 /* Fall Through */ 6172 /* Fall Through */
6203 default: 6173 default:
@@ -6225,7 +6195,7 @@ e1000_led_on(struct e1000_hw *hw)
6225 6195
6226 DEBUGFUNC("e1000_led_on"); 6196 DEBUGFUNC("e1000_led_on");
6227 6197
6228 switch(hw->mac_type) { 6198 switch (hw->mac_type) {
6229 case e1000_82542_rev2_0: 6199 case e1000_82542_rev2_0:
6230 case e1000_82542_rev2_1: 6200 case e1000_82542_rev2_1:
6231 case e1000_82543: 6201 case e1000_82543:
@@ -6234,7 +6204,7 @@ e1000_led_on(struct e1000_hw *hw)
6234 ctrl |= E1000_CTRL_SWDPIO0; 6204 ctrl |= E1000_CTRL_SWDPIO0;
6235 break; 6205 break;
6236 case e1000_82544: 6206 case e1000_82544:
6237 if(hw->media_type == e1000_media_type_fiber) { 6207 if (hw->media_type == e1000_media_type_fiber) {
6238 /* Set SW Defineable Pin 0 to turn on the LED */ 6208 /* Set SW Defineable Pin 0 to turn on the LED */
6239 ctrl |= E1000_CTRL_SWDPIN0; 6209 ctrl |= E1000_CTRL_SWDPIN0;
6240 ctrl |= E1000_CTRL_SWDPIO0; 6210 ctrl |= E1000_CTRL_SWDPIO0;
@@ -6245,7 +6215,7 @@ e1000_led_on(struct e1000_hw *hw)
6245 } 6215 }
6246 break; 6216 break;
6247 default: 6217 default:
6248 if(hw->media_type == e1000_media_type_fiber) { 6218 if (hw->media_type == e1000_media_type_fiber) {
6249 /* Clear SW Defineable Pin 0 to turn on the LED */ 6219 /* Clear SW Defineable Pin 0 to turn on the LED */
6250 ctrl &= ~E1000_CTRL_SWDPIN0; 6220 ctrl &= ~E1000_CTRL_SWDPIN0;
6251 ctrl |= E1000_CTRL_SWDPIO0; 6221 ctrl |= E1000_CTRL_SWDPIO0;
@@ -6276,7 +6246,7 @@ e1000_led_off(struct e1000_hw *hw)
6276 6246
6277 DEBUGFUNC("e1000_led_off"); 6247 DEBUGFUNC("e1000_led_off");
6278 6248
6279 switch(hw->mac_type) { 6249 switch (hw->mac_type) {
6280 case e1000_82542_rev2_0: 6250 case e1000_82542_rev2_0:
6281 case e1000_82542_rev2_1: 6251 case e1000_82542_rev2_1:
6282 case e1000_82543: 6252 case e1000_82543:
@@ -6285,7 +6255,7 @@ e1000_led_off(struct e1000_hw *hw)
6285 ctrl |= E1000_CTRL_SWDPIO0; 6255 ctrl |= E1000_CTRL_SWDPIO0;
6286 break; 6256 break;
6287 case e1000_82544: 6257 case e1000_82544:
6288 if(hw->media_type == e1000_media_type_fiber) { 6258 if (hw->media_type == e1000_media_type_fiber) {
6289 /* Clear SW Defineable Pin 0 to turn off the LED */ 6259 /* Clear SW Defineable Pin 0 to turn off the LED */
6290 ctrl &= ~E1000_CTRL_SWDPIN0; 6260 ctrl &= ~E1000_CTRL_SWDPIN0;
6291 ctrl |= E1000_CTRL_SWDPIO0; 6261 ctrl |= E1000_CTRL_SWDPIO0;
@@ -6296,7 +6266,7 @@ e1000_led_off(struct e1000_hw *hw)
6296 } 6266 }
6297 break; 6267 break;
6298 default: 6268 default:
6299 if(hw->media_type == e1000_media_type_fiber) { 6269 if (hw->media_type == e1000_media_type_fiber) {
6300 /* Set SW Defineable Pin 0 to turn off the LED */ 6270 /* Set SW Defineable Pin 0 to turn off the LED */
6301 ctrl |= E1000_CTRL_SWDPIN0; 6271 ctrl |= E1000_CTRL_SWDPIN0;
6302 ctrl |= E1000_CTRL_SWDPIO0; 6272 ctrl |= E1000_CTRL_SWDPIO0;
@@ -6320,7 +6290,7 @@ e1000_led_off(struct e1000_hw *hw)
6320 * 6290 *
6321 * hw - Struct containing variables accessed by shared code 6291 * hw - Struct containing variables accessed by shared code
6322 *****************************************************************************/ 6292 *****************************************************************************/
6323static void 6293void
6324e1000_clear_hw_cntrs(struct e1000_hw *hw) 6294e1000_clear_hw_cntrs(struct e1000_hw *hw)
6325{ 6295{
6326 volatile uint32_t temp; 6296 volatile uint32_t temp;
@@ -6383,7 +6353,7 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
6383 temp = E1000_READ_REG(hw, MPTC); 6353 temp = E1000_READ_REG(hw, MPTC);
6384 temp = E1000_READ_REG(hw, BPTC); 6354 temp = E1000_READ_REG(hw, BPTC);
6385 6355
6386 if(hw->mac_type < e1000_82543) return; 6356 if (hw->mac_type < e1000_82543) return;
6387 6357
6388 temp = E1000_READ_REG(hw, ALGNERRC); 6358 temp = E1000_READ_REG(hw, ALGNERRC);
6389 temp = E1000_READ_REG(hw, RXERRC); 6359 temp = E1000_READ_REG(hw, RXERRC);
@@ -6392,13 +6362,13 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
6392 temp = E1000_READ_REG(hw, TSCTC); 6362 temp = E1000_READ_REG(hw, TSCTC);
6393 temp = E1000_READ_REG(hw, TSCTFC); 6363 temp = E1000_READ_REG(hw, TSCTFC);
6394 6364
6395 if(hw->mac_type <= e1000_82544) return; 6365 if (hw->mac_type <= e1000_82544) return;
6396 6366
6397 temp = E1000_READ_REG(hw, MGTPRC); 6367 temp = E1000_READ_REG(hw, MGTPRC);
6398 temp = E1000_READ_REG(hw, MGTPDC); 6368 temp = E1000_READ_REG(hw, MGTPDC);
6399 temp = E1000_READ_REG(hw, MGTPTC); 6369 temp = E1000_READ_REG(hw, MGTPTC);
6400 6370
6401 if(hw->mac_type <= e1000_82547_rev_2) return; 6371 if (hw->mac_type <= e1000_82547_rev_2) return;
6402 6372
6403 temp = E1000_READ_REG(hw, IAC); 6373 temp = E1000_READ_REG(hw, IAC);
6404 temp = E1000_READ_REG(hw, ICRXOC); 6374 temp = E1000_READ_REG(hw, ICRXOC);
@@ -6429,8 +6399,8 @@ e1000_reset_adaptive(struct e1000_hw *hw)
6429{ 6399{
6430 DEBUGFUNC("e1000_reset_adaptive"); 6400 DEBUGFUNC("e1000_reset_adaptive");
6431 6401
6432 if(hw->adaptive_ifs) { 6402 if (hw->adaptive_ifs) {
6433 if(!hw->ifs_params_forced) { 6403 if (!hw->ifs_params_forced) {
6434 hw->current_ifs_val = 0; 6404 hw->current_ifs_val = 0;
6435 hw->ifs_min_val = IFS_MIN; 6405 hw->ifs_min_val = IFS_MIN;
6436 hw->ifs_max_val = IFS_MAX; 6406 hw->ifs_max_val = IFS_MAX;
@@ -6457,12 +6427,12 @@ e1000_update_adaptive(struct e1000_hw *hw)
6457{ 6427{
6458 DEBUGFUNC("e1000_update_adaptive"); 6428 DEBUGFUNC("e1000_update_adaptive");
6459 6429
6460 if(hw->adaptive_ifs) { 6430 if (hw->adaptive_ifs) {
6461 if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) { 6431 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
6462 if(hw->tx_packet_delta > MIN_NUM_XMITS) { 6432 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
6463 hw->in_ifs_mode = TRUE; 6433 hw->in_ifs_mode = TRUE;
6464 if(hw->current_ifs_val < hw->ifs_max_val) { 6434 if (hw->current_ifs_val < hw->ifs_max_val) {
6465 if(hw->current_ifs_val == 0) 6435 if (hw->current_ifs_val == 0)
6466 hw->current_ifs_val = hw->ifs_min_val; 6436 hw->current_ifs_val = hw->ifs_min_val;
6467 else 6437 else
6468 hw->current_ifs_val += hw->ifs_step_size; 6438 hw->current_ifs_val += hw->ifs_step_size;
@@ -6470,7 +6440,7 @@ e1000_update_adaptive(struct e1000_hw *hw)
6470 } 6440 }
6471 } 6441 }
6472 } else { 6442 } else {
6473 if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { 6443 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
6474 hw->current_ifs_val = 0; 6444 hw->current_ifs_val = 0;
6475 hw->in_ifs_mode = FALSE; 6445 hw->in_ifs_mode = FALSE;
6476 E1000_WRITE_REG(hw, AIT, 0); 6446 E1000_WRITE_REG(hw, AIT, 0);
@@ -6517,46 +6487,46 @@ e1000_tbi_adjust_stats(struct e1000_hw *hw,
6517 * This could be simplified if all environments supported 6487 * This could be simplified if all environments supported
6518 * 64-bit integers. 6488 * 64-bit integers.
6519 */ 6489 */
6520 if(carry_bit && ((stats->gorcl & 0x80000000) == 0)) 6490 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
6521 stats->gorch++; 6491 stats->gorch++;
6522 /* Is this a broadcast or multicast? Check broadcast first, 6492 /* Is this a broadcast or multicast? Check broadcast first,
6523 * since the test for a multicast frame will test positive on 6493 * since the test for a multicast frame will test positive on
6524 * a broadcast frame. 6494 * a broadcast frame.
6525 */ 6495 */
6526 if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) 6496 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
6527 /* Broadcast packet */ 6497 /* Broadcast packet */
6528 stats->bprc++; 6498 stats->bprc++;
6529 else if(*mac_addr & 0x01) 6499 else if (*mac_addr & 0x01)
6530 /* Multicast packet */ 6500 /* Multicast packet */
6531 stats->mprc++; 6501 stats->mprc++;
6532 6502
6533 if(frame_len == hw->max_frame_size) { 6503 if (frame_len == hw->max_frame_size) {
6534 /* In this case, the hardware has overcounted the number of 6504 /* In this case, the hardware has overcounted the number of
6535 * oversize frames. 6505 * oversize frames.
6536 */ 6506 */
6537 if(stats->roc > 0) 6507 if (stats->roc > 0)
6538 stats->roc--; 6508 stats->roc--;
6539 } 6509 }
6540 6510
6541 /* Adjust the bin counters when the extra byte put the frame in the 6511 /* Adjust the bin counters when the extra byte put the frame in the
6542 * wrong bin. Remember that the frame_len was adjusted above. 6512 * wrong bin. Remember that the frame_len was adjusted above.
6543 */ 6513 */
6544 if(frame_len == 64) { 6514 if (frame_len == 64) {
6545 stats->prc64++; 6515 stats->prc64++;
6546 stats->prc127--; 6516 stats->prc127--;
6547 } else if(frame_len == 127) { 6517 } else if (frame_len == 127) {
6548 stats->prc127++; 6518 stats->prc127++;
6549 stats->prc255--; 6519 stats->prc255--;
6550 } else if(frame_len == 255) { 6520 } else if (frame_len == 255) {
6551 stats->prc255++; 6521 stats->prc255++;
6552 stats->prc511--; 6522 stats->prc511--;
6553 } else if(frame_len == 511) { 6523 } else if (frame_len == 511) {
6554 stats->prc511++; 6524 stats->prc511++;
6555 stats->prc1023--; 6525 stats->prc1023--;
6556 } else if(frame_len == 1023) { 6526 } else if (frame_len == 1023) {
6557 stats->prc1023++; 6527 stats->prc1023++;
6558 stats->prc1522--; 6528 stats->prc1522--;
6559 } else if(frame_len == 1522) { 6529 } else if (frame_len == 1522) {
6560 stats->prc1522++; 6530 stats->prc1522++;
6561 } 6531 }
6562} 6532}
@@ -6596,10 +6566,10 @@ e1000_get_bus_info(struct e1000_hw *hw)
6596 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 6566 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6597 e1000_bus_type_pcix : e1000_bus_type_pci; 6567 e1000_bus_type_pcix : e1000_bus_type_pci;
6598 6568
6599 if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 6569 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
6600 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? 6570 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
6601 e1000_bus_speed_66 : e1000_bus_speed_120; 6571 e1000_bus_speed_66 : e1000_bus_speed_120;
6602 } else if(hw->bus_type == e1000_bus_type_pci) { 6572 } else if (hw->bus_type == e1000_bus_type_pci) {
6603 hw->bus_speed = (status & E1000_STATUS_PCI66) ? 6573 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6604 e1000_bus_speed_66 : e1000_bus_speed_33; 6574 e1000_bus_speed_66 : e1000_bus_speed_33;
6605 } else { 6575 } else {
@@ -6694,11 +6664,11 @@ e1000_get_cable_length(struct e1000_hw *hw,
6694 *min_length = *max_length = 0; 6664 *min_length = *max_length = 0;
6695 6665
6696 /* Use old method for Phy older than IGP */ 6666 /* Use old method for Phy older than IGP */
6697 if(hw->phy_type == e1000_phy_m88) { 6667 if (hw->phy_type == e1000_phy_m88) {
6698 6668
6699 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 6669 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6700 &phy_data); 6670 &phy_data);
6701 if(ret_val) 6671 if (ret_val)
6702 return ret_val; 6672 return ret_val;
6703 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 6673 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6704 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 6674 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
@@ -6757,7 +6727,7 @@ e1000_get_cable_length(struct e1000_hw *hw,
6757 return -E1000_ERR_PHY; 6727 return -E1000_ERR_PHY;
6758 break; 6728 break;
6759 } 6729 }
6760 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ 6730 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6761 uint16_t cur_agc_value; 6731 uint16_t cur_agc_value;
6762 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 6732 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6763 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 6733 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
@@ -6766,10 +6736,10 @@ e1000_get_cable_length(struct e1000_hw *hw,
6766 IGP01E1000_PHY_AGC_C, 6736 IGP01E1000_PHY_AGC_C,
6767 IGP01E1000_PHY_AGC_D}; 6737 IGP01E1000_PHY_AGC_D};
6768 /* Read the AGC registers for all channels */ 6738 /* Read the AGC registers for all channels */
6769 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 6739 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6770 6740
6771 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); 6741 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6772 if(ret_val) 6742 if (ret_val)
6773 return ret_val; 6743 return ret_val;
6774 6744
6775 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; 6745 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
@@ -6819,7 +6789,7 @@ e1000_get_cable_length(struct e1000_hw *hw,
6819 if (ret_val) 6789 if (ret_val)
6820 return ret_val; 6790 return ret_val;
6821 6791
6822 /* Getting bits 15:9, which represent the combination of course and 6792 /* Getting bits 15:9, which represent the combination of course and
6823 * fine gain values. The result is a number that can be put into 6793 * fine gain values. The result is a number that can be put into
6824 * the lookup table to obtain the approximate cable length. */ 6794 * the lookup table to obtain the approximate cable length. */
6825 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 6795 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
@@ -6884,7 +6854,7 @@ e1000_check_polarity(struct e1000_hw *hw,
6884 /* return the Polarity bit in the Status register. */ 6854 /* return the Polarity bit in the Status register. */
6885 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 6855 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6886 &phy_data); 6856 &phy_data);
6887 if(ret_val) 6857 if (ret_val)
6888 return ret_val; 6858 return ret_val;
6889 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >> 6859 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
6890 M88E1000_PSSR_REV_POLARITY_SHIFT; 6860 M88E1000_PSSR_REV_POLARITY_SHIFT;
@@ -6894,18 +6864,18 @@ e1000_check_polarity(struct e1000_hw *hw,
6894 /* Read the Status register to check the speed */ 6864 /* Read the Status register to check the speed */
6895 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 6865 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
6896 &phy_data); 6866 &phy_data);
6897 if(ret_val) 6867 if (ret_val)
6898 return ret_val; 6868 return ret_val;
6899 6869
6900 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to 6870 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
6901 * find the polarity status */ 6871 * find the polarity status */
6902 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 6872 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
6903 IGP01E1000_PSSR_SPEED_1000MBPS) { 6873 IGP01E1000_PSSR_SPEED_1000MBPS) {
6904 6874
6905 /* Read the GIG initialization PCS register (0x00B4) */ 6875 /* Read the GIG initialization PCS register (0x00B4) */
6906 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, 6876 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
6907 &phy_data); 6877 &phy_data);
6908 if(ret_val) 6878 if (ret_val)
6909 return ret_val; 6879 return ret_val;
6910 6880
6911 /* Check the polarity bits */ 6881 /* Check the polarity bits */
@@ -6954,7 +6924,7 @@ e1000_check_downshift(struct e1000_hw *hw)
6954 hw->phy_type == e1000_phy_igp_2) { 6924 hw->phy_type == e1000_phy_igp_2) {
6955 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 6925 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6956 &phy_data); 6926 &phy_data);
6957 if(ret_val) 6927 if (ret_val)
6958 return ret_val; 6928 return ret_val;
6959 6929
6960 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 6930 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
@@ -6962,7 +6932,7 @@ e1000_check_downshift(struct e1000_hw *hw)
6962 (hw->phy_type == e1000_phy_gg82563)) { 6932 (hw->phy_type == e1000_phy_gg82563)) {
6963 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 6933 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6964 &phy_data); 6934 &phy_data);
6965 if(ret_val) 6935 if (ret_val)
6966 return ret_val; 6936 return ret_val;
6967 6937
6968 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 6938 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
@@ -7002,42 +6972,42 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
7002 6972
7003 DEBUGFUNC("e1000_config_dsp_after_link_change"); 6973 DEBUGFUNC("e1000_config_dsp_after_link_change");
7004 6974
7005 if(hw->phy_type != e1000_phy_igp) 6975 if (hw->phy_type != e1000_phy_igp)
7006 return E1000_SUCCESS; 6976 return E1000_SUCCESS;
7007 6977
7008 if(link_up) { 6978 if (link_up) {
7009 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 6979 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
7010 if(ret_val) { 6980 if (ret_val) {
7011 DEBUGOUT("Error getting link speed and duplex\n"); 6981 DEBUGOUT("Error getting link speed and duplex\n");
7012 return ret_val; 6982 return ret_val;
7013 } 6983 }
7014 6984
7015 if(speed == SPEED_1000) { 6985 if (speed == SPEED_1000) {
7016 6986
7017 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); 6987 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
7018 if (ret_val) 6988 if (ret_val)
7019 return ret_val; 6989 return ret_val;
7020 6990
7021 if((hw->dsp_config_state == e1000_dsp_config_enabled) && 6991 if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
7022 min_length >= e1000_igp_cable_length_50) { 6992 min_length >= e1000_igp_cable_length_50) {
7023 6993
7024 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 6994 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7025 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], 6995 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
7026 &phy_data); 6996 &phy_data);
7027 if(ret_val) 6997 if (ret_val)
7028 return ret_val; 6998 return ret_val;
7029 6999
7030 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 7000 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7031 7001
7032 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], 7002 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
7033 phy_data); 7003 phy_data);
7034 if(ret_val) 7004 if (ret_val)
7035 return ret_val; 7005 return ret_val;
7036 } 7006 }
7037 hw->dsp_config_state = e1000_dsp_config_activated; 7007 hw->dsp_config_state = e1000_dsp_config_activated;
7038 } 7008 }
7039 7009
7040 if((hw->ffe_config_state == e1000_ffe_config_enabled) && 7010 if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
7041 (min_length < e1000_igp_cable_length_50)) { 7011 (min_length < e1000_igp_cable_length_50)) {
7042 7012
7043 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 7013 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
@@ -7046,70 +7016,70 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
7046 /* clear previous idle error counts */ 7016 /* clear previous idle error counts */
7047 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, 7017 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7048 &phy_data); 7018 &phy_data);
7049 if(ret_val) 7019 if (ret_val)
7050 return ret_val; 7020 return ret_val;
7051 7021
7052 for(i = 0; i < ffe_idle_err_timeout; i++) { 7022 for (i = 0; i < ffe_idle_err_timeout; i++) {
7053 udelay(1000); 7023 udelay(1000);
7054 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, 7024 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7055 &phy_data); 7025 &phy_data);
7056 if(ret_val) 7026 if (ret_val)
7057 return ret_val; 7027 return ret_val;
7058 7028
7059 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); 7029 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
7060 if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 7030 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
7061 hw->ffe_config_state = e1000_ffe_config_active; 7031 hw->ffe_config_state = e1000_ffe_config_active;
7062 7032
7063 ret_val = e1000_write_phy_reg(hw, 7033 ret_val = e1000_write_phy_reg(hw,
7064 IGP01E1000_PHY_DSP_FFE, 7034 IGP01E1000_PHY_DSP_FFE,
7065 IGP01E1000_PHY_DSP_FFE_CM_CP); 7035 IGP01E1000_PHY_DSP_FFE_CM_CP);
7066 if(ret_val) 7036 if (ret_val)
7067 return ret_val; 7037 return ret_val;
7068 break; 7038 break;
7069 } 7039 }
7070 7040
7071 if(idle_errs) 7041 if (idle_errs)
7072 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100; 7042 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
7073 } 7043 }
7074 } 7044 }
7075 } 7045 }
7076 } else { 7046 } else {
7077 if(hw->dsp_config_state == e1000_dsp_config_activated) { 7047 if (hw->dsp_config_state == e1000_dsp_config_activated) {
7078 /* Save off the current value of register 0x2F5B to be restored at 7048 /* Save off the current value of register 0x2F5B to be restored at
7079 * the end of the routines. */ 7049 * the end of the routines. */
7080 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 7050 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7081 7051
7082 if(ret_val) 7052 if (ret_val)
7083 return ret_val; 7053 return ret_val;
7084 7054
7085 /* Disable the PHY transmitter */ 7055 /* Disable the PHY transmitter */
7086 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 7056 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7087 7057
7088 if(ret_val) 7058 if (ret_val)
7089 return ret_val; 7059 return ret_val;
7090 7060
7091 msec_delay_irq(20); 7061 msec_delay_irq(20);
7092 7062
7093 ret_val = e1000_write_phy_reg(hw, 0x0000, 7063 ret_val = e1000_write_phy_reg(hw, 0x0000,
7094 IGP01E1000_IEEE_FORCE_GIGA); 7064 IGP01E1000_IEEE_FORCE_GIGA);
7095 if(ret_val) 7065 if (ret_val)
7096 return ret_val; 7066 return ret_val;
7097 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 7067 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7098 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data); 7068 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
7099 if(ret_val) 7069 if (ret_val)
7100 return ret_val; 7070 return ret_val;
7101 7071
7102 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 7072 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7103 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 7073 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
7104 7074
7105 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data); 7075 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
7106 if(ret_val) 7076 if (ret_val)
7107 return ret_val; 7077 return ret_val;
7108 } 7078 }
7109 7079
7110 ret_val = e1000_write_phy_reg(hw, 0x0000, 7080 ret_val = e1000_write_phy_reg(hw, 0x0000,
7111 IGP01E1000_IEEE_RESTART_AUTONEG); 7081 IGP01E1000_IEEE_RESTART_AUTONEG);
7112 if(ret_val) 7082 if (ret_val)
7113 return ret_val; 7083 return ret_val;
7114 7084
7115 msec_delay_irq(20); 7085 msec_delay_irq(20);
@@ -7117,40 +7087,40 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
7117 /* Now enable the transmitter */ 7087 /* Now enable the transmitter */
7118 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 7088 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7119 7089
7120 if(ret_val) 7090 if (ret_val)
7121 return ret_val; 7091 return ret_val;
7122 7092
7123 hw->dsp_config_state = e1000_dsp_config_enabled; 7093 hw->dsp_config_state = e1000_dsp_config_enabled;
7124 } 7094 }
7125 7095
7126 if(hw->ffe_config_state == e1000_ffe_config_active) { 7096 if (hw->ffe_config_state == e1000_ffe_config_active) {
7127 /* Save off the current value of register 0x2F5B to be restored at 7097 /* Save off the current value of register 0x2F5B to be restored at
7128 * the end of the routines. */ 7098 * the end of the routines. */
7129 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 7099 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7130 7100
7131 if(ret_val) 7101 if (ret_val)
7132 return ret_val; 7102 return ret_val;
7133 7103
7134 /* Disable the PHY transmitter */ 7104 /* Disable the PHY transmitter */
7135 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 7105 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7136 7106
7137 if(ret_val) 7107 if (ret_val)
7138 return ret_val; 7108 return ret_val;
7139 7109
7140 msec_delay_irq(20); 7110 msec_delay_irq(20);
7141 7111
7142 ret_val = e1000_write_phy_reg(hw, 0x0000, 7112 ret_val = e1000_write_phy_reg(hw, 0x0000,
7143 IGP01E1000_IEEE_FORCE_GIGA); 7113 IGP01E1000_IEEE_FORCE_GIGA);
7144 if(ret_val) 7114 if (ret_val)
7145 return ret_val; 7115 return ret_val;
7146 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, 7116 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
7147 IGP01E1000_PHY_DSP_FFE_DEFAULT); 7117 IGP01E1000_PHY_DSP_FFE_DEFAULT);
7148 if(ret_val) 7118 if (ret_val)
7149 return ret_val; 7119 return ret_val;
7150 7120
7151 ret_val = e1000_write_phy_reg(hw, 0x0000, 7121 ret_val = e1000_write_phy_reg(hw, 0x0000,
7152 IGP01E1000_IEEE_RESTART_AUTONEG); 7122 IGP01E1000_IEEE_RESTART_AUTONEG);
7153 if(ret_val) 7123 if (ret_val)
7154 return ret_val; 7124 return ret_val;
7155 7125
7156 msec_delay_irq(20); 7126 msec_delay_irq(20);
@@ -7158,7 +7128,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
7158 /* Now enable the transmitter */ 7128 /* Now enable the transmitter */
7159 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 7129 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7160 7130
7161 if(ret_val) 7131 if (ret_val)
7162 return ret_val; 7132 return ret_val;
7163 7133
7164 hw->ffe_config_state = e1000_ffe_config_enabled; 7134 hw->ffe_config_state = e1000_ffe_config_enabled;
@@ -7183,20 +7153,20 @@ e1000_set_phy_mode(struct e1000_hw *hw)
7183 7153
7184 DEBUGFUNC("e1000_set_phy_mode"); 7154 DEBUGFUNC("e1000_set_phy_mode");
7185 7155
7186 if((hw->mac_type == e1000_82545_rev_3) && 7156 if ((hw->mac_type == e1000_82545_rev_3) &&
7187 (hw->media_type == e1000_media_type_copper)) { 7157 (hw->media_type == e1000_media_type_copper)) {
7188 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data); 7158 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
7189 if(ret_val) { 7159 if (ret_val) {
7190 return ret_val; 7160 return ret_val;
7191 } 7161 }
7192 7162
7193 if((eeprom_data != EEPROM_RESERVED_WORD) && 7163 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
7194 (eeprom_data & EEPROM_PHY_CLASS_A)) { 7164 (eeprom_data & EEPROM_PHY_CLASS_A)) {
7195 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B); 7165 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
7196 if(ret_val) 7166 if (ret_val)
7197 return ret_val; 7167 return ret_val;
7198 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104); 7168 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
7199 if(ret_val) 7169 if (ret_val)
7200 return ret_val; 7170 return ret_val;
7201 7171
7202 hw->phy_reset_disable = FALSE; 7172 hw->phy_reset_disable = FALSE;
@@ -7247,16 +7217,16 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
7247 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 7217 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7248 } else { 7218 } else {
7249 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 7219 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7250 if(ret_val) 7220 if (ret_val)
7251 return ret_val; 7221 return ret_val;
7252 } 7222 }
7253 7223
7254 if(!active) { 7224 if (!active) {
7255 if(hw->mac_type == e1000_82541_rev_2 || 7225 if (hw->mac_type == e1000_82541_rev_2 ||
7256 hw->mac_type == e1000_82547_rev_2) { 7226 hw->mac_type == e1000_82547_rev_2) {
7257 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 7227 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
7258 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); 7228 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7259 if(ret_val) 7229 if (ret_val)
7260 return ret_val; 7230 return ret_val;
7261 } else { 7231 } else {
7262 if (hw->mac_type == e1000_ich8lan) { 7232 if (hw->mac_type == e1000_ich8lan) {
@@ -7278,13 +7248,13 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
7278 if (hw->smart_speed == e1000_smart_speed_on) { 7248 if (hw->smart_speed == e1000_smart_speed_on) {
7279 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7249 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7280 &phy_data); 7250 &phy_data);
7281 if(ret_val) 7251 if (ret_val)
7282 return ret_val; 7252 return ret_val;
7283 7253
7284 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 7254 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7285 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7255 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7286 phy_data); 7256 phy_data);
7287 if(ret_val) 7257 if (ret_val)
7288 return ret_val; 7258 return ret_val;
7289 } else if (hw->smart_speed == e1000_smart_speed_off) { 7259 } else if (hw->smart_speed == e1000_smart_speed_off) {
7290 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7260 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
@@ -7295,19 +7265,19 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
7295 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 7265 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7296 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7266 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7297 phy_data); 7267 phy_data);
7298 if(ret_val) 7268 if (ret_val)
7299 return ret_val; 7269 return ret_val;
7300 } 7270 }
7301 7271
7302 } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) || 7272 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
7303 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || 7273 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
7304 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 7274 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
7305 7275
7306 if(hw->mac_type == e1000_82541_rev_2 || 7276 if (hw->mac_type == e1000_82541_rev_2 ||
7307 hw->mac_type == e1000_82547_rev_2) { 7277 hw->mac_type == e1000_82547_rev_2) {
7308 phy_data |= IGP01E1000_GMII_FLEX_SPD; 7278 phy_data |= IGP01E1000_GMII_FLEX_SPD;
7309 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); 7279 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7310 if(ret_val) 7280 if (ret_val)
7311 return ret_val; 7281 return ret_val;
7312 } else { 7282 } else {
7313 if (hw->mac_type == e1000_ich8lan) { 7283 if (hw->mac_type == e1000_ich8lan) {
@@ -7324,12 +7294,12 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
7324 7294
7325 /* When LPLU is enabled we should disable SmartSpeed */ 7295 /* When LPLU is enabled we should disable SmartSpeed */
7326 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); 7296 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7327 if(ret_val) 7297 if (ret_val)
7328 return ret_val; 7298 return ret_val;
7329 7299
7330 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 7300 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7331 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); 7301 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7332 if(ret_val) 7302 if (ret_val)
7333 return ret_val; 7303 return ret_val;
7334 7304
7335 } 7305 }
@@ -7359,14 +7329,14 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
7359 uint16_t phy_data; 7329 uint16_t phy_data;
7360 DEBUGFUNC("e1000_set_d0_lplu_state"); 7330 DEBUGFUNC("e1000_set_d0_lplu_state");
7361 7331
7362 if(hw->mac_type <= e1000_82547_rev_2) 7332 if (hw->mac_type <= e1000_82547_rev_2)
7363 return E1000_SUCCESS; 7333 return E1000_SUCCESS;
7364 7334
7365 if (hw->mac_type == e1000_ich8lan) { 7335 if (hw->mac_type == e1000_ich8lan) {
7366 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 7336 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7367 } else { 7337 } else {
7368 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 7338 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7369 if(ret_val) 7339 if (ret_val)
7370 return ret_val; 7340 return ret_val;
7371 } 7341 }
7372 7342
@@ -7388,13 +7358,13 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
7388 if (hw->smart_speed == e1000_smart_speed_on) { 7358 if (hw->smart_speed == e1000_smart_speed_on) {
7389 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7359 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7390 &phy_data); 7360 &phy_data);
7391 if(ret_val) 7361 if (ret_val)
7392 return ret_val; 7362 return ret_val;
7393 7363
7394 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 7364 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7395 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7365 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7396 phy_data); 7366 phy_data);
7397 if(ret_val) 7367 if (ret_val)
7398 return ret_val; 7368 return ret_val;
7399 } else if (hw->smart_speed == e1000_smart_speed_off) { 7369 } else if (hw->smart_speed == e1000_smart_speed_off) {
7400 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7370 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
@@ -7405,7 +7375,7 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
7405 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 7375 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7406 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7376 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7407 phy_data); 7377 phy_data);
7408 if(ret_val) 7378 if (ret_val)
7409 return ret_val; 7379 return ret_val;
7410 } 7380 }
7411 7381
@@ -7424,12 +7394,12 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
7424 7394
7425 /* When LPLU is enabled we should disable SmartSpeed */ 7395 /* When LPLU is enabled we should disable SmartSpeed */
7426 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); 7396 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7427 if(ret_val) 7397 if (ret_val)
7428 return ret_val; 7398 return ret_val;
7429 7399
7430 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 7400 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7431 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); 7401 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7432 if(ret_val) 7402 if (ret_val)
7433 return ret_val; 7403 return ret_val;
7434 7404
7435 } 7405 }
@@ -7450,7 +7420,7 @@ e1000_set_vco_speed(struct e1000_hw *hw)
7450 7420
7451 DEBUGFUNC("e1000_set_vco_speed"); 7421 DEBUGFUNC("e1000_set_vco_speed");
7452 7422
7453 switch(hw->mac_type) { 7423 switch (hw->mac_type) {
7454 case e1000_82545_rev_3: 7424 case e1000_82545_rev_3:
7455 case e1000_82546_rev_3: 7425 case e1000_82546_rev_3:
7456 break; 7426 break;
@@ -7461,39 +7431,39 @@ e1000_set_vco_speed(struct e1000_hw *hw)
7461 /* Set PHY register 30, page 5, bit 8 to 0 */ 7431 /* Set PHY register 30, page 5, bit 8 to 0 */
7462 7432
7463 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); 7433 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
7464 if(ret_val) 7434 if (ret_val)
7465 return ret_val; 7435 return ret_val;
7466 7436
7467 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 7437 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
7468 if(ret_val) 7438 if (ret_val)
7469 return ret_val; 7439 return ret_val;
7470 7440
7471 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 7441 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7472 if(ret_val) 7442 if (ret_val)
7473 return ret_val; 7443 return ret_val;
7474 7444
7475 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 7445 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
7476 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 7446 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7477 if(ret_val) 7447 if (ret_val)
7478 return ret_val; 7448 return ret_val;
7479 7449
7480 /* Set PHY register 30, page 4, bit 11 to 1 */ 7450 /* Set PHY register 30, page 4, bit 11 to 1 */
7481 7451
7482 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 7452 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
7483 if(ret_val) 7453 if (ret_val)
7484 return ret_val; 7454 return ret_val;
7485 7455
7486 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 7456 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7487 if(ret_val) 7457 if (ret_val)
7488 return ret_val; 7458 return ret_val;
7489 7459
7490 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 7460 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
7491 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 7461 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7492 if(ret_val) 7462 if (ret_val)
7493 return ret_val; 7463 return ret_val;
7494 7464
7495 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); 7465 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
7496 if(ret_val) 7466 if (ret_val)
7497 return ret_val; 7467 return ret_val;
7498 7468
7499 return E1000_SUCCESS; 7469 return E1000_SUCCESS;
@@ -7572,7 +7542,7 @@ e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7572{ 7542{
7573 uint8_t *tmp; 7543 uint8_t *tmp;
7574 uint8_t *bufptr = buffer; 7544 uint8_t *bufptr = buffer;
7575 uint32_t data; 7545 uint32_t data = 0;
7576 uint16_t remaining, i, j, prev_bytes; 7546 uint16_t remaining, i, j, prev_bytes;
7577 7547
7578 /* sum = only sum of the data and it is not checksum */ 7548 /* sum = only sum of the data and it is not checksum */
@@ -7652,7 +7622,7 @@ e1000_mng_write_cmd_header(struct e1000_hw * hw,
7652 7622
7653 buffer = (uint8_t *) hdr; 7623 buffer = (uint8_t *) hdr;
7654 i = length; 7624 i = length;
7655 while(i--) 7625 while (i--)
7656 sum += buffer[i]; 7626 sum += buffer[i];
7657 7627
7658 hdr->checksum = 0 - sum; 7628 hdr->checksum = 0 - sum;
@@ -7675,8 +7645,7 @@ e1000_mng_write_cmd_header(struct e1000_hw * hw,
7675 * returns - E1000_SUCCESS for success. 7645 * returns - E1000_SUCCESS for success.
7676 ****************************************************************************/ 7646 ****************************************************************************/
7677static int32_t 7647static int32_t
7678e1000_mng_write_commit( 7648e1000_mng_write_commit(struct e1000_hw * hw)
7679 struct e1000_hw * hw)
7680{ 7649{
7681 uint32_t hicr; 7650 uint32_t hicr;
7682 7651
@@ -7848,31 +7817,31 @@ e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7848 /* Disable the transmitter on the PHY */ 7817 /* Disable the transmitter on the PHY */
7849 7818
7850 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 7819 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7851 if(ret_val) 7820 if (ret_val)
7852 return ret_val; 7821 return ret_val;
7853 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 7822 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
7854 if(ret_val) 7823 if (ret_val)
7855 return ret_val; 7824 return ret_val;
7856 7825
7857 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 7826 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7858 if(ret_val) 7827 if (ret_val)
7859 return ret_val; 7828 return ret_val;
7860 7829
7861 /* This loop will early-out if the NO link condition has been met. */ 7830 /* This loop will early-out if the NO link condition has been met. */
7862 for(i = PHY_FORCE_TIME; i > 0; i--) { 7831 for (i = PHY_FORCE_TIME; i > 0; i--) {
7863 /* Read the MII Status Register and wait for Link Status bit 7832 /* Read the MII Status Register and wait for Link Status bit
7864 * to be clear. 7833 * to be clear.
7865 */ 7834 */
7866 7835
7867 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 7836 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7868 if(ret_val) 7837 if (ret_val)
7869 return ret_val; 7838 return ret_val;
7870 7839
7871 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 7840 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7872 if(ret_val) 7841 if (ret_val)
7873 return ret_val; 7842 return ret_val;
7874 7843
7875 if((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break; 7844 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
7876 msec_delay_irq(100); 7845 msec_delay_irq(100);
7877 } 7846 }
7878 7847
@@ -7882,40 +7851,40 @@ e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7882 /* Now we will re-enable th transmitter on the PHY */ 7851 /* Now we will re-enable th transmitter on the PHY */
7883 7852
7884 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 7853 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7885 if(ret_val) 7854 if (ret_val)
7886 return ret_val; 7855 return ret_val;
7887 msec_delay_irq(50); 7856 msec_delay_irq(50);
7888 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 7857 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
7889 if(ret_val) 7858 if (ret_val)
7890 return ret_val; 7859 return ret_val;
7891 msec_delay_irq(50); 7860 msec_delay_irq(50);
7892 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 7861 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
7893 if(ret_val) 7862 if (ret_val)
7894 return ret_val; 7863 return ret_val;
7895 msec_delay_irq(50); 7864 msec_delay_irq(50);
7896 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 7865 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
7897 if(ret_val) 7866 if (ret_val)
7898 return ret_val; 7867 return ret_val;
7899 7868
7900 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 7869 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7901 if(ret_val) 7870 if (ret_val)
7902 return ret_val; 7871 return ret_val;
7903 7872
7904 /* This loop will early-out if the link condition has been met. */ 7873 /* This loop will early-out if the link condition has been met. */
7905 for(i = PHY_FORCE_TIME; i > 0; i--) { 7874 for (i = PHY_FORCE_TIME; i > 0; i--) {
7906 /* Read the MII Status Register and wait for Link Status bit 7875 /* Read the MII Status Register and wait for Link Status bit
7907 * to be set. 7876 * to be set.
7908 */ 7877 */
7909 7878
7910 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 7879 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7911 if(ret_val) 7880 if (ret_val)
7912 return ret_val; 7881 return ret_val;
7913 7882
7914 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 7883 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7915 if(ret_val) 7884 if (ret_val)
7916 return ret_val; 7885 return ret_val;
7917 7886
7918 if(mii_status_reg & MII_SR_LINK_STATUS) break; 7887 if (mii_status_reg & MII_SR_LINK_STATUS) break;
7919 msec_delay_irq(100); 7888 msec_delay_irq(100);
7920 } 7889 }
7921 return E1000_SUCCESS; 7890 return E1000_SUCCESS;
@@ -7994,15 +7963,15 @@ e1000_disable_pciex_master(struct e1000_hw *hw)
7994 7963
7995 e1000_set_pci_express_master_disable(hw); 7964 e1000_set_pci_express_master_disable(hw);
7996 7965
7997 while(timeout) { 7966 while (timeout) {
7998 if(!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) 7967 if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
7999 break; 7968 break;
8000 else 7969 else
8001 udelay(100); 7970 udelay(100);
8002 timeout--; 7971 timeout--;
8003 } 7972 }
8004 7973
8005 if(!timeout) { 7974 if (!timeout) {
8006 DEBUGOUT("Master requests are pending.\n"); 7975 DEBUGOUT("Master requests are pending.\n");
8007 return -E1000_ERR_MASTER_REQUESTS_PENDING; 7976 return -E1000_ERR_MASTER_REQUESTS_PENDING;
8008 } 7977 }
@@ -8043,7 +8012,7 @@ e1000_get_auto_rd_done(struct e1000_hw *hw)
8043 timeout--; 8012 timeout--;
8044 } 8013 }
8045 8014
8046 if(!timeout) { 8015 if (!timeout) {
8047 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n"); 8016 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
8048 return -E1000_ERR_RESET; 8017 return -E1000_ERR_RESET;
8049 } 8018 }
@@ -8124,7 +8093,7 @@ e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8124 8093
8125 DEBUGFUNC("e1000_get_hw_eeprom_semaphore"); 8094 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
8126 8095
8127 if(!hw->eeprom_semaphore_present) 8096 if (!hw->eeprom_semaphore_present)
8128 return E1000_SUCCESS; 8097 return E1000_SUCCESS;
8129 8098
8130 if (hw->mac_type == e1000_80003es2lan) { 8099 if (hw->mac_type == e1000_80003es2lan) {
@@ -8135,20 +8104,20 @@ e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8135 8104
8136 /* Get the FW semaphore. */ 8105 /* Get the FW semaphore. */
8137 timeout = hw->eeprom.word_size + 1; 8106 timeout = hw->eeprom.word_size + 1;
8138 while(timeout) { 8107 while (timeout) {
8139 swsm = E1000_READ_REG(hw, SWSM); 8108 swsm = E1000_READ_REG(hw, SWSM);
8140 swsm |= E1000_SWSM_SWESMBI; 8109 swsm |= E1000_SWSM_SWESMBI;
8141 E1000_WRITE_REG(hw, SWSM, swsm); 8110 E1000_WRITE_REG(hw, SWSM, swsm);
8142 /* if we managed to set the bit we got the semaphore. */ 8111 /* if we managed to set the bit we got the semaphore. */
8143 swsm = E1000_READ_REG(hw, SWSM); 8112 swsm = E1000_READ_REG(hw, SWSM);
8144 if(swsm & E1000_SWSM_SWESMBI) 8113 if (swsm & E1000_SWSM_SWESMBI)
8145 break; 8114 break;
8146 8115
8147 udelay(50); 8116 udelay(50);
8148 timeout--; 8117 timeout--;
8149 } 8118 }
8150 8119
8151 if(!timeout) { 8120 if (!timeout) {
8152 /* Release semaphores */ 8121 /* Release semaphores */
8153 e1000_put_hw_eeprom_semaphore(hw); 8122 e1000_put_hw_eeprom_semaphore(hw);
8154 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n"); 8123 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
@@ -8173,7 +8142,7 @@ e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8173 8142
8174 DEBUGFUNC("e1000_put_hw_eeprom_semaphore"); 8143 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
8175 8144
8176 if(!hw->eeprom_semaphore_present) 8145 if (!hw->eeprom_semaphore_present)
8177 return; 8146 return;
8178 8147
8179 swsm = E1000_READ_REG(hw, SWSM); 8148 swsm = E1000_READ_REG(hw, SWSM);
@@ -8206,16 +8175,16 @@ e1000_get_software_semaphore(struct e1000_hw *hw)
8206 if (hw->mac_type != e1000_80003es2lan) 8175 if (hw->mac_type != e1000_80003es2lan)
8207 return E1000_SUCCESS; 8176 return E1000_SUCCESS;
8208 8177
8209 while(timeout) { 8178 while (timeout) {
8210 swsm = E1000_READ_REG(hw, SWSM); 8179 swsm = E1000_READ_REG(hw, SWSM);
8211 /* If SMBI bit cleared, it is now set and we hold the semaphore */ 8180 /* If SMBI bit cleared, it is now set and we hold the semaphore */
8212 if(!(swsm & E1000_SWSM_SMBI)) 8181 if (!(swsm & E1000_SWSM_SMBI))
8213 break; 8182 break;
8214 msec_delay_irq(1); 8183 msec_delay_irq(1);
8215 timeout--; 8184 timeout--;
8216 } 8185 }
8217 8186
8218 if(!timeout) { 8187 if (!timeout) {
8219 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 8188 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
8220 return -E1000_ERR_RESET; 8189 return -E1000_ERR_RESET;
8221 } 8190 }
@@ -8291,7 +8260,7 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw)
8291 case e1000_82573: 8260 case e1000_82573:
8292 case e1000_80003es2lan: 8261 case e1000_80003es2lan:
8293 fwsm = E1000_READ_REG(hw, FWSM); 8262 fwsm = E1000_READ_REG(hw, FWSM);
8294 if((fwsm & E1000_FWSM_MODE_MASK) != 0) 8263 if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
8295 return TRUE; 8264 return TRUE;
8296 break; 8265 break;
8297 case e1000_ich8lan: 8266 case e1000_ich8lan:
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
index 375b95518c31..a170e96251f6 100644
--- a/drivers/net/e1000/e1000_hw.h
+++ b/drivers/net/e1000/e1000_hw.h
@@ -336,9 +336,9 @@ uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw);
336#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */ 336#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */
337 337
338#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */ 338#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */
339#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */ 339#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */
340#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */ 340#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */
341#define E1000_MNG_IAMT_MODE 0x3 341#define E1000_MNG_IAMT_MODE 0x3
342#define E1000_MNG_ICH_IAMT_MODE 0x2 342#define E1000_MNG_ICH_IAMT_MODE 0x2
343#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */ 343#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */
344 344
@@ -385,7 +385,7 @@ struct e1000_host_mng_dhcp_cookie{
385#endif 385#endif
386 386
387int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer, 387int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer,
388 uint16_t length); 388 uint16_t length);
389boolean_t e1000_check_mng_mode(struct e1000_hw *hw); 389boolean_t e1000_check_mng_mode(struct e1000_hw *hw);
390boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); 390boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);
391 391
@@ -470,6 +470,7 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
470#define E1000_DEV_ID_82571EB_COPPER 0x105E 470#define E1000_DEV_ID_82571EB_COPPER 0x105E
471#define E1000_DEV_ID_82571EB_FIBER 0x105F 471#define E1000_DEV_ID_82571EB_FIBER 0x105F
472#define E1000_DEV_ID_82571EB_SERDES 0x1060 472#define E1000_DEV_ID_82571EB_SERDES 0x1060
473#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
473#define E1000_DEV_ID_82572EI_COPPER 0x107D 474#define E1000_DEV_ID_82572EI_COPPER 0x107D
474#define E1000_DEV_ID_82572EI_FIBER 0x107E 475#define E1000_DEV_ID_82572EI_FIBER 0x107E
475#define E1000_DEV_ID_82572EI_SERDES 0x107F 476#define E1000_DEV_ID_82572EI_SERDES 0x107F
@@ -523,7 +524,7 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
523 524
524 525
525/* 802.1q VLAN Packet Sizes */ 526/* 802.1q VLAN Packet Sizes */
526#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ 527#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
527 528
528/* Ethertype field values */ 529/* Ethertype field values */
529#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 530#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
@@ -697,6 +698,7 @@ union e1000_rx_desc_packet_split {
697 E1000_RXDEXT_STATERR_CXE | \ 698 E1000_RXDEXT_STATERR_CXE | \
698 E1000_RXDEXT_STATERR_RXE) 699 E1000_RXDEXT_STATERR_RXE)
699 700
701
700/* Transmit Descriptor */ 702/* Transmit Descriptor */
701struct e1000_tx_desc { 703struct e1000_tx_desc {
702 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 704 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
@@ -2086,7 +2088,7 @@ struct e1000_hw {
2086#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address 2088#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address
2087 * filtering */ 2089 * filtering */
2088#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ 2090#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
2089#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ 2091#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
2090#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ 2092#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
2091#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ 2093#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
2092#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ 2094#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
@@ -2172,7 +2174,7 @@ struct e1000_host_command_info {
2172 2174
2173#define E1000_MDALIGN 4096 2175#define E1000_MDALIGN 4096
2174 2176
2175/* PCI-Ex registers */ 2177/* PCI-Ex registers*/
2176 2178
2177/* PCI-Ex Control Register */ 2179/* PCI-Ex Control Register */
2178#define E1000_GCR_RXD_NO_SNOOP 0x00000001 2180#define E1000_GCR_RXD_NO_SNOOP 0x00000001
@@ -2224,7 +2226,7 @@ struct e1000_host_command_info {
2224#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */ 2226#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */
2225 2227
2226/* EEPROM Commands - SPI */ 2228/* EEPROM Commands - SPI */
2227#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 2229#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
2228#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 2230#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
2229#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 2231#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
2230#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 2232#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
@@ -3082,10 +3084,10 @@ struct e1000_host_command_info {
3082 3084
3083/* DSP Distance Register (Page 5, Register 26) */ 3085/* DSP Distance Register (Page 5, Register 26) */
3084#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M; 3086#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M;
3085 1 = 50-80M; 3087 1 = 50-80M;
3086 2 = 80-110M; 3088 2 = 80-110M;
3087 3 = 110-140M; 3089 3 = 110-140M;
3088 4 = >140M */ 3090 4 = >140M */
3089 3091
3090/* Kumeran Mode Control Register (Page 193, Register 16) */ 3092/* Kumeran Mode Control Register (Page 193, Register 16) */
3091#define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */ 3093#define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index 0cf9ff2462ba..1d7c99947e92 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -36,7 +36,7 @@ static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
36#else 36#else
37#define DRIVERNAPI "-NAPI" 37#define DRIVERNAPI "-NAPI"
38#endif 38#endif
39#define DRV_VERSION "7.1.9-k6"DRIVERNAPI 39#define DRV_VERSION "7.2.7-k2"DRIVERNAPI
40char e1000_driver_version[] = DRV_VERSION; 40char e1000_driver_version[] = DRV_VERSION;
41static char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation."; 41static char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
42 42
@@ -98,6 +98,7 @@ static struct pci_device_id e1000_pci_tbl[] = {
98 INTEL_E1000_ETHERNET_DEVICE(0x1098), 98 INTEL_E1000_ETHERNET_DEVICE(0x1098),
99 INTEL_E1000_ETHERNET_DEVICE(0x1099), 99 INTEL_E1000_ETHERNET_DEVICE(0x1099),
100 INTEL_E1000_ETHERNET_DEVICE(0x109A), 100 INTEL_E1000_ETHERNET_DEVICE(0x109A),
101 INTEL_E1000_ETHERNET_DEVICE(0x10A4),
101 INTEL_E1000_ETHERNET_DEVICE(0x10B5), 102 INTEL_E1000_ETHERNET_DEVICE(0x10B5),
102 INTEL_E1000_ETHERNET_DEVICE(0x10B9), 103 INTEL_E1000_ETHERNET_DEVICE(0x10B9),
103 INTEL_E1000_ETHERNET_DEVICE(0x10BA), 104 INTEL_E1000_ETHERNET_DEVICE(0x10BA),
@@ -681,9 +682,9 @@ e1000_probe(struct pci_dev *pdev,
681 unsigned long flash_start, flash_len; 682 unsigned long flash_start, flash_len;
682 683
683 static int cards_found = 0; 684 static int cards_found = 0;
684 static int e1000_ksp3_port_a = 0; /* global ksp3 port a indication */ 685 static int global_quad_port_a = 0; /* global ksp3 port a indication */
685 int i, err, pci_using_dac; 686 int i, err, pci_using_dac;
686 uint16_t eeprom_data; 687 uint16_t eeprom_data = 0;
687 uint16_t eeprom_apme_mask = E1000_EEPROM_APME; 688 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
688 if ((err = pci_enable_device(pdev))) 689 if ((err = pci_enable_device(pdev)))
689 return err; 690 return err;
@@ -695,21 +696,20 @@ e1000_probe(struct pci_dev *pdev,
695 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) && 696 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) &&
696 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) { 697 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) {
697 E1000_ERR("No usable DMA configuration, aborting\n"); 698 E1000_ERR("No usable DMA configuration, aborting\n");
698 return err; 699 goto err_dma;
699 } 700 }
700 pci_using_dac = 0; 701 pci_using_dac = 0;
701 } 702 }
702 703
703 if ((err = pci_request_regions(pdev, e1000_driver_name))) 704 if ((err = pci_request_regions(pdev, e1000_driver_name)))
704 return err; 705 goto err_pci_reg;
705 706
706 pci_set_master(pdev); 707 pci_set_master(pdev);
707 708
709 err = -ENOMEM;
708 netdev = alloc_etherdev(sizeof(struct e1000_adapter)); 710 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
709 if (!netdev) { 711 if (!netdev)
710 err = -ENOMEM;
711 goto err_alloc_etherdev; 712 goto err_alloc_etherdev;
712 }
713 713
714 SET_MODULE_OWNER(netdev); 714 SET_MODULE_OWNER(netdev);
715 SET_NETDEV_DEV(netdev, &pdev->dev); 715 SET_NETDEV_DEV(netdev, &pdev->dev);
@@ -724,11 +724,10 @@ e1000_probe(struct pci_dev *pdev,
724 mmio_start = pci_resource_start(pdev, BAR_0); 724 mmio_start = pci_resource_start(pdev, BAR_0);
725 mmio_len = pci_resource_len(pdev, BAR_0); 725 mmio_len = pci_resource_len(pdev, BAR_0);
726 726
727 err = -EIO;
727 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 728 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
728 if (!adapter->hw.hw_addr) { 729 if (!adapter->hw.hw_addr)
729 err = -EIO;
730 goto err_ioremap; 730 goto err_ioremap;
731 }
732 731
733 for (i = BAR_1; i <= BAR_5; i++) { 732 for (i = BAR_1; i <= BAR_5; i++) {
734 if (pci_resource_len(pdev, i) == 0) 733 if (pci_resource_len(pdev, i) == 0)
@@ -773,6 +772,7 @@ e1000_probe(struct pci_dev *pdev,
773 if ((err = e1000_sw_init(adapter))) 772 if ((err = e1000_sw_init(adapter)))
774 goto err_sw_init; 773 goto err_sw_init;
775 774
775 err = -EIO;
776 /* Flash BAR mapping must happen after e1000_sw_init 776 /* Flash BAR mapping must happen after e1000_sw_init
777 * because it depends on mac_type */ 777 * because it depends on mac_type */
778 if ((adapter->hw.mac_type == e1000_ich8lan) && 778 if ((adapter->hw.mac_type == e1000_ich8lan) &&
@@ -780,24 +780,13 @@ e1000_probe(struct pci_dev *pdev,
780 flash_start = pci_resource_start(pdev, 1); 780 flash_start = pci_resource_start(pdev, 1);
781 flash_len = pci_resource_len(pdev, 1); 781 flash_len = pci_resource_len(pdev, 1);
782 adapter->hw.flash_address = ioremap(flash_start, flash_len); 782 adapter->hw.flash_address = ioremap(flash_start, flash_len);
783 if (!adapter->hw.flash_address) { 783 if (!adapter->hw.flash_address)
784 err = -EIO;
785 goto err_flashmap; 784 goto err_flashmap;
786 }
787 } 785 }
788 786
789 if ((err = e1000_check_phy_reset_block(&adapter->hw))) 787 if (e1000_check_phy_reset_block(&adapter->hw))
790 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n"); 788 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
791 789
792 /* if ksp3, indicate if it's port a being setup */
793 if (pdev->device == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 &&
794 e1000_ksp3_port_a == 0)
795 adapter->ksp3_port_a = 1;
796 e1000_ksp3_port_a++;
797 /* Reset for multiple KP3 adapters */
798 if (e1000_ksp3_port_a == 4)
799 e1000_ksp3_port_a = 0;
800
801 if (adapter->hw.mac_type >= e1000_82543) { 790 if (adapter->hw.mac_type >= e1000_82543) {
802 netdev->features = NETIF_F_SG | 791 netdev->features = NETIF_F_SG |
803 NETIF_F_HW_CSUM | 792 NETIF_F_HW_CSUM |
@@ -829,7 +818,7 @@ e1000_probe(struct pci_dev *pdev,
829 818
830 if (e1000_init_eeprom_params(&adapter->hw)) { 819 if (e1000_init_eeprom_params(&adapter->hw)) {
831 E1000_ERR("EEPROM initialization failed\n"); 820 E1000_ERR("EEPROM initialization failed\n");
832 return -EIO; 821 goto err_eeprom;
833 } 822 }
834 823
835 /* before reading the EEPROM, reset the controller to 824 /* before reading the EEPROM, reset the controller to
@@ -841,7 +830,6 @@ e1000_probe(struct pci_dev *pdev,
841 830
842 if (e1000_validate_eeprom_checksum(&adapter->hw) < 0) { 831 if (e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
843 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n"); 832 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
844 err = -EIO;
845 goto err_eeprom; 833 goto err_eeprom;
846 } 834 }
847 835
@@ -854,12 +842,9 @@ e1000_probe(struct pci_dev *pdev,
854 842
855 if (!is_valid_ether_addr(netdev->perm_addr)) { 843 if (!is_valid_ether_addr(netdev->perm_addr)) {
856 DPRINTK(PROBE, ERR, "Invalid MAC Address\n"); 844 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
857 err = -EIO;
858 goto err_eeprom; 845 goto err_eeprom;
859 } 846 }
860 847
861 e1000_read_part_num(&adapter->hw, &(adapter->part_num));
862
863 e1000_get_bus_info(&adapter->hw); 848 e1000_get_bus_info(&adapter->hw);
864 849
865 init_timer(&adapter->tx_fifo_stall_timer); 850 init_timer(&adapter->tx_fifo_stall_timer);
@@ -920,7 +905,38 @@ e1000_probe(struct pci_dev *pdev,
920 break; 905 break;
921 } 906 }
922 if (eeprom_data & eeprom_apme_mask) 907 if (eeprom_data & eeprom_apme_mask)
923 adapter->wol |= E1000_WUFC_MAG; 908 adapter->eeprom_wol |= E1000_WUFC_MAG;
909
910 /* now that we have the eeprom settings, apply the special cases
911 * where the eeprom may be wrong or the board simply won't support
912 * wake on lan on a particular port */
913 switch (pdev->device) {
914 case E1000_DEV_ID_82546GB_PCIE:
915 adapter->eeprom_wol = 0;
916 break;
917 case E1000_DEV_ID_82546EB_FIBER:
918 case E1000_DEV_ID_82546GB_FIBER:
919 case E1000_DEV_ID_82571EB_FIBER:
920 /* Wake events only supported on port A for dual fiber
921 * regardless of eeprom setting */
922 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1)
923 adapter->eeprom_wol = 0;
924 break;
925 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
926 case E1000_DEV_ID_82571EB_QUAD_COPPER:
927 /* if quad port adapter, disable WoL on all but port A */
928 if (global_quad_port_a != 0)
929 adapter->eeprom_wol = 0;
930 else
931 adapter->quad_port_a = 1;
932 /* Reset for multiple quad port adapters */
933 if (++global_quad_port_a == 4)
934 global_quad_port_a = 0;
935 break;
936 }
937
938 /* initialize the wol settings based on the eeprom settings */
939 adapter->wol = adapter->eeprom_wol;
924 940
925 /* print bus type/speed/width info */ 941 /* print bus type/speed/width info */
926 { 942 {
@@ -963,16 +979,33 @@ e1000_probe(struct pci_dev *pdev,
963 return 0; 979 return 0;
964 980
965err_register: 981err_register:
982 e1000_release_hw_control(adapter);
983err_eeprom:
984 if (!e1000_check_phy_reset_block(&adapter->hw))
985 e1000_phy_hw_reset(&adapter->hw);
986
966 if (adapter->hw.flash_address) 987 if (adapter->hw.flash_address)
967 iounmap(adapter->hw.flash_address); 988 iounmap(adapter->hw.flash_address);
968err_flashmap: 989err_flashmap:
990#ifdef CONFIG_E1000_NAPI
991 for (i = 0; i < adapter->num_rx_queues; i++)
992 dev_put(&adapter->polling_netdev[i]);
993#endif
994
995 kfree(adapter->tx_ring);
996 kfree(adapter->rx_ring);
997#ifdef CONFIG_E1000_NAPI
998 kfree(adapter->polling_netdev);
999#endif
969err_sw_init: 1000err_sw_init:
970err_eeprom:
971 iounmap(adapter->hw.hw_addr); 1001 iounmap(adapter->hw.hw_addr);
972err_ioremap: 1002err_ioremap:
973 free_netdev(netdev); 1003 free_netdev(netdev);
974err_alloc_etherdev: 1004err_alloc_etherdev:
975 pci_release_regions(pdev); 1005 pci_release_regions(pdev);
1006err_pci_reg:
1007err_dma:
1008 pci_disable_device(pdev);
976 return err; 1009 return err;
977} 1010}
978 1011
@@ -1207,7 +1240,7 @@ e1000_open(struct net_device *netdev)
1207 1240
1208 err = e1000_request_irq(adapter); 1241 err = e1000_request_irq(adapter);
1209 if (err) 1242 if (err)
1210 goto err_up; 1243 goto err_req_irq;
1211 1244
1212 e1000_power_up_phy(adapter); 1245 e1000_power_up_phy(adapter);
1213 1246
@@ -1228,6 +1261,9 @@ e1000_open(struct net_device *netdev)
1228 return E1000_SUCCESS; 1261 return E1000_SUCCESS;
1229 1262
1230err_up: 1263err_up:
1264 e1000_power_down_phy(adapter);
1265 e1000_free_irq(adapter);
1266err_req_irq:
1231 e1000_free_all_rx_resources(adapter); 1267 e1000_free_all_rx_resources(adapter);
1232err_setup_rx: 1268err_setup_rx:
1233 e1000_free_all_tx_resources(adapter); 1269 e1000_free_all_tx_resources(adapter);
@@ -1380,10 +1416,6 @@ setup_tx_desc_die:
1380 * (Descriptors) for all queues 1416 * (Descriptors) for all queues
1381 * @adapter: board private structure 1417 * @adapter: board private structure
1382 * 1418 *
1383 * If this function returns with an error, then it's possible one or
1384 * more of the rings is populated (while the rest are not). It is the
1385 * callers duty to clean those orphaned rings.
1386 *
1387 * Return 0 on success, negative on failure 1419 * Return 0 on success, negative on failure
1388 **/ 1420 **/
1389 1421
@@ -1397,6 +1429,9 @@ e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1397 if (err) { 1429 if (err) {
1398 DPRINTK(PROBE, ERR, 1430 DPRINTK(PROBE, ERR,
1399 "Allocation for Tx Queue %u failed\n", i); 1431 "Allocation for Tx Queue %u failed\n", i);
1432 for (i-- ; i >= 0; i--)
1433 e1000_free_tx_resources(adapter,
1434 &adapter->tx_ring[i]);
1400 break; 1435 break;
1401 } 1436 }
1402 } 1437 }
@@ -1636,10 +1671,6 @@ setup_rx_desc_die:
1636 * (Descriptors) for all queues 1671 * (Descriptors) for all queues
1637 * @adapter: board private structure 1672 * @adapter: board private structure
1638 * 1673 *
1639 * If this function returns with an error, then it's possible one or
1640 * more of the rings is populated (while the rest are not). It is the
1641 * callers duty to clean those orphaned rings.
1642 *
1643 * Return 0 on success, negative on failure 1674 * Return 0 on success, negative on failure
1644 **/ 1675 **/
1645 1676
@@ -1653,6 +1684,9 @@ e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1653 if (err) { 1684 if (err) {
1654 DPRINTK(PROBE, ERR, 1685 DPRINTK(PROBE, ERR,
1655 "Allocation for Rx Queue %u failed\n", i); 1686 "Allocation for Rx Queue %u failed\n", i);
1687 for (i-- ; i >= 0; i--)
1688 e1000_free_rx_resources(adapter,
1689 &adapter->rx_ring[i]);
1656 break; 1690 break;
1657 } 1691 }
1658 } 1692 }
@@ -2439,10 +2473,9 @@ e1000_watchdog(unsigned long data)
2439 * disable receives in the ISR and 2473 * disable receives in the ISR and
2440 * reset device here in the watchdog 2474 * reset device here in the watchdog
2441 */ 2475 */
2442 if (adapter->hw.mac_type == e1000_80003es2lan) { 2476 if (adapter->hw.mac_type == e1000_80003es2lan)
2443 /* reset device */ 2477 /* reset device */
2444 schedule_work(&adapter->reset_task); 2478 schedule_work(&adapter->reset_task);
2445 }
2446 } 2479 }
2447 2480
2448 e1000_smartspeed(adapter); 2481 e1000_smartspeed(adapter);
@@ -3677,7 +3710,7 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter,
3677 E1000_DBG("%s: Receive packet consumed multiple" 3710 E1000_DBG("%s: Receive packet consumed multiple"
3678 " buffers\n", netdev->name); 3711 " buffers\n", netdev->name);
3679 /* recycle */ 3712 /* recycle */
3680 buffer_info-> skb = skb; 3713 buffer_info->skb = skb;
3681 goto next_desc; 3714 goto next_desc;
3682 } 3715 }
3683 3716
@@ -3708,7 +3741,6 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter,
3708 netdev_alloc_skb(netdev, length + NET_IP_ALIGN); 3741 netdev_alloc_skb(netdev, length + NET_IP_ALIGN);
3709 if (new_skb) { 3742 if (new_skb) {
3710 skb_reserve(new_skb, NET_IP_ALIGN); 3743 skb_reserve(new_skb, NET_IP_ALIGN);
3711 new_skb->dev = netdev;
3712 memcpy(new_skb->data - NET_IP_ALIGN, 3744 memcpy(new_skb->data - NET_IP_ALIGN,
3713 skb->data - NET_IP_ALIGN, 3745 skb->data - NET_IP_ALIGN,
3714 length + NET_IP_ALIGN); 3746 length + NET_IP_ALIGN);
@@ -3975,13 +4007,13 @@ e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
3975 buffer_info = &rx_ring->buffer_info[i]; 4007 buffer_info = &rx_ring->buffer_info[i];
3976 4008
3977 while (cleaned_count--) { 4009 while (cleaned_count--) {
3978 if (!(skb = buffer_info->skb)) 4010 skb = buffer_info->skb;
3979 skb = netdev_alloc_skb(netdev, bufsz); 4011 if (skb) {
3980 else {
3981 skb_trim(skb, 0); 4012 skb_trim(skb, 0);
3982 goto map_skb; 4013 goto map_skb;
3983 } 4014 }
3984 4015
4016 skb = netdev_alloc_skb(netdev, bufsz);
3985 if (unlikely(!skb)) { 4017 if (unlikely(!skb)) {
3986 /* Better luck next round */ 4018 /* Better luck next round */
3987 adapter->alloc_rx_buff_failed++; 4019 adapter->alloc_rx_buff_failed++;
@@ -4006,10 +4038,10 @@ e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
4006 dev_kfree_skb(skb); 4038 dev_kfree_skb(skb);
4007 dev_kfree_skb(oldskb); 4039 dev_kfree_skb(oldskb);
4008 break; /* while !buffer_info->skb */ 4040 break; /* while !buffer_info->skb */
4009 } else {
4010 /* Use new allocation */
4011 dev_kfree_skb(oldskb);
4012 } 4041 }
4042
4043 /* Use new allocation */
4044 dev_kfree_skb(oldskb);
4013 } 4045 }
4014 /* Make buffer alignment 2 beyond a 16 byte boundary 4046 /* Make buffer alignment 2 beyond a 16 byte boundary
4015 * this will result in a 16 byte aligned IP header after 4047 * this will result in a 16 byte aligned IP header after
@@ -4017,8 +4049,6 @@ e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
4017 */ 4049 */
4018 skb_reserve(skb, NET_IP_ALIGN); 4050 skb_reserve(skb, NET_IP_ALIGN);
4019 4051
4020 skb->dev = netdev;
4021
4022 buffer_info->skb = skb; 4052 buffer_info->skb = skb;
4023 buffer_info->length = adapter->rx_buffer_len; 4053 buffer_info->length = adapter->rx_buffer_len;
4024map_skb: 4054map_skb:
@@ -4132,8 +4162,6 @@ e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
4132 */ 4162 */
4133 skb_reserve(skb, NET_IP_ALIGN); 4163 skb_reserve(skb, NET_IP_ALIGN);
4134 4164
4135 skb->dev = netdev;
4136
4137 buffer_info->skb = skb; 4165 buffer_info->skb = skb;
4138 buffer_info->length = adapter->rx_ps_bsize0; 4166 buffer_info->length = adapter->rx_ps_bsize0;
4139 buffer_info->dma = pci_map_single(pdev, skb->data, 4167 buffer_info->dma = pci_map_single(pdev, skb->data,
@@ -4625,7 +4653,7 @@ e1000_suspend(struct pci_dev *pdev, pm_message_t state)
4625 e1000_set_multi(netdev); 4653 e1000_set_multi(netdev);
4626 4654
4627 /* turn on all-multi mode if wake on multicast is enabled */ 4655 /* turn on all-multi mode if wake on multicast is enabled */
4628 if (adapter->wol & E1000_WUFC_MC) { 4656 if (wufc & E1000_WUFC_MC) {
4629 rctl = E1000_READ_REG(&adapter->hw, RCTL); 4657 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4630 rctl |= E1000_RCTL_MPE; 4658 rctl |= E1000_RCTL_MPE;
4631 E1000_WRITE_REG(&adapter->hw, RCTL, rctl); 4659 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
@@ -4697,11 +4725,14 @@ e1000_resume(struct pci_dev *pdev)
4697{ 4725{
4698 struct net_device *netdev = pci_get_drvdata(pdev); 4726 struct net_device *netdev = pci_get_drvdata(pdev);
4699 struct e1000_adapter *adapter = netdev_priv(netdev); 4727 struct e1000_adapter *adapter = netdev_priv(netdev);
4700 uint32_t manc, ret_val; 4728 uint32_t manc, err;
4701 4729
4702 pci_set_power_state(pdev, PCI_D0); 4730 pci_set_power_state(pdev, PCI_D0);
4703 e1000_pci_restore_state(adapter); 4731 e1000_pci_restore_state(adapter);
4704 ret_val = pci_enable_device(pdev); 4732 if ((err = pci_enable_device(pdev))) {
4733 printk(KERN_ERR "e1000: Cannot enable PCI device from suspend\n");
4734 return err;
4735 }
4705 pci_set_master(pdev); 4736 pci_set_master(pdev);
4706 4737
4707 pci_enable_wake(pdev, PCI_D3hot, 0); 4738 pci_enable_wake(pdev, PCI_D3hot, 0);
diff --git a/drivers/net/e1000/e1000_param.c b/drivers/net/e1000/e1000_param.c
index 0ef413172c68..212842738972 100644
--- a/drivers/net/e1000/e1000_param.c
+++ b/drivers/net/e1000/e1000_param.c
@@ -324,7 +324,6 @@ e1000_check_options(struct e1000_adapter *adapter)
324 DPRINTK(PROBE, NOTICE, 324 DPRINTK(PROBE, NOTICE,
325 "Warning: no configuration for board #%i\n", bd); 325 "Warning: no configuration for board #%i\n", bd);
326 DPRINTK(PROBE, NOTICE, "Using defaults for all values\n"); 326 DPRINTK(PROBE, NOTICE, "Using defaults for all values\n");
327 bd = E1000_MAX_NIC;
328 } 327 }
329 328
330 { /* Transmit Descriptor Count */ 329 { /* Transmit Descriptor Count */
@@ -342,9 +341,14 @@ e1000_check_options(struct e1000_adapter *adapter)
342 opt.arg.r.max = mac_type < e1000_82544 ? 341 opt.arg.r.max = mac_type < e1000_82544 ?
343 E1000_MAX_TXD : E1000_MAX_82544_TXD; 342 E1000_MAX_TXD : E1000_MAX_82544_TXD;
344 343
345 tx_ring->count = TxDescriptors[bd]; 344 if (num_TxDescriptors > bd) {
346 e1000_validate_option(&tx_ring->count, &opt, adapter); 345 tx_ring->count = TxDescriptors[bd];
347 E1000_ROUNDUP(tx_ring->count, REQ_TX_DESCRIPTOR_MULTIPLE); 346 e1000_validate_option(&tx_ring->count, &opt, adapter);
347 E1000_ROUNDUP(tx_ring->count,
348 REQ_TX_DESCRIPTOR_MULTIPLE);
349 } else {
350 tx_ring->count = opt.def;
351 }
348 for (i = 0; i < adapter->num_tx_queues; i++) 352 for (i = 0; i < adapter->num_tx_queues; i++)
349 tx_ring[i].count = tx_ring->count; 353 tx_ring[i].count = tx_ring->count;
350 } 354 }
@@ -363,9 +367,14 @@ e1000_check_options(struct e1000_adapter *adapter)
363 opt.arg.r.max = mac_type < e1000_82544 ? E1000_MAX_RXD : 367 opt.arg.r.max = mac_type < e1000_82544 ? E1000_MAX_RXD :
364 E1000_MAX_82544_RXD; 368 E1000_MAX_82544_RXD;
365 369
366 rx_ring->count = RxDescriptors[bd]; 370 if (num_RxDescriptors > bd) {
367 e1000_validate_option(&rx_ring->count, &opt, adapter); 371 rx_ring->count = RxDescriptors[bd];
368 E1000_ROUNDUP(rx_ring->count, REQ_RX_DESCRIPTOR_MULTIPLE); 372 e1000_validate_option(&rx_ring->count, &opt, adapter);
373 E1000_ROUNDUP(rx_ring->count,
374 REQ_RX_DESCRIPTOR_MULTIPLE);
375 } else {
376 rx_ring->count = opt.def;
377 }
369 for (i = 0; i < adapter->num_rx_queues; i++) 378 for (i = 0; i < adapter->num_rx_queues; i++)
370 rx_ring[i].count = rx_ring->count; 379 rx_ring[i].count = rx_ring->count;
371 } 380 }
@@ -377,9 +386,13 @@ e1000_check_options(struct e1000_adapter *adapter)
377 .def = OPTION_ENABLED 386 .def = OPTION_ENABLED
378 }; 387 };
379 388
380 int rx_csum = XsumRX[bd]; 389 if (num_XsumRX > bd) {
381 e1000_validate_option(&rx_csum, &opt, adapter); 390 int rx_csum = XsumRX[bd];
382 adapter->rx_csum = rx_csum; 391 e1000_validate_option(&rx_csum, &opt, adapter);
392 adapter->rx_csum = rx_csum;
393 } else {
394 adapter->rx_csum = opt.def;
395 }
383 } 396 }
384 { /* Flow Control */ 397 { /* Flow Control */
385 398
@@ -399,9 +412,13 @@ e1000_check_options(struct e1000_adapter *adapter)
399 .p = fc_list }} 412 .p = fc_list }}
400 }; 413 };
401 414
402 int fc = FlowControl[bd]; 415 if (num_FlowControl > bd) {
403 e1000_validate_option(&fc, &opt, adapter); 416 int fc = FlowControl[bd];
404 adapter->hw.fc = adapter->hw.original_fc = fc; 417 e1000_validate_option(&fc, &opt, adapter);
418 adapter->hw.fc = adapter->hw.original_fc = fc;
419 } else {
420 adapter->hw.fc = adapter->hw.original_fc = opt.def;
421 }
405 } 422 }
406 { /* Transmit Interrupt Delay */ 423 { /* Transmit Interrupt Delay */
407 struct e1000_option opt = { 424 struct e1000_option opt = {
@@ -413,8 +430,13 @@ e1000_check_options(struct e1000_adapter *adapter)
413 .max = MAX_TXDELAY }} 430 .max = MAX_TXDELAY }}
414 }; 431 };
415 432
416 adapter->tx_int_delay = TxIntDelay[bd]; 433 if (num_TxIntDelay > bd) {
417 e1000_validate_option(&adapter->tx_int_delay, &opt, adapter); 434 adapter->tx_int_delay = TxIntDelay[bd];
435 e1000_validate_option(&adapter->tx_int_delay, &opt,
436 adapter);
437 } else {
438 adapter->tx_int_delay = opt.def;
439 }
418 } 440 }
419 { /* Transmit Absolute Interrupt Delay */ 441 { /* Transmit Absolute Interrupt Delay */
420 struct e1000_option opt = { 442 struct e1000_option opt = {
@@ -426,9 +448,13 @@ e1000_check_options(struct e1000_adapter *adapter)
426 .max = MAX_TXABSDELAY }} 448 .max = MAX_TXABSDELAY }}
427 }; 449 };
428 450
429 adapter->tx_abs_int_delay = TxAbsIntDelay[bd]; 451 if (num_TxAbsIntDelay > bd) {
430 e1000_validate_option(&adapter->tx_abs_int_delay, &opt, 452 adapter->tx_abs_int_delay = TxAbsIntDelay[bd];
431 adapter); 453 e1000_validate_option(&adapter->tx_abs_int_delay, &opt,
454 adapter);
455 } else {
456 adapter->tx_abs_int_delay = opt.def;
457 }
432 } 458 }
433 { /* Receive Interrupt Delay */ 459 { /* Receive Interrupt Delay */
434 struct e1000_option opt = { 460 struct e1000_option opt = {
@@ -440,8 +466,13 @@ e1000_check_options(struct e1000_adapter *adapter)
440 .max = MAX_RXDELAY }} 466 .max = MAX_RXDELAY }}
441 }; 467 };
442 468
443 adapter->rx_int_delay = RxIntDelay[bd]; 469 if (num_RxIntDelay > bd) {
444 e1000_validate_option(&adapter->rx_int_delay, &opt, adapter); 470 adapter->rx_int_delay = RxIntDelay[bd];
471 e1000_validate_option(&adapter->rx_int_delay, &opt,
472 adapter);
473 } else {
474 adapter->rx_int_delay = opt.def;
475 }
445 } 476 }
446 { /* Receive Absolute Interrupt Delay */ 477 { /* Receive Absolute Interrupt Delay */
447 struct e1000_option opt = { 478 struct e1000_option opt = {
@@ -453,9 +484,13 @@ e1000_check_options(struct e1000_adapter *adapter)
453 .max = MAX_RXABSDELAY }} 484 .max = MAX_RXABSDELAY }}
454 }; 485 };
455 486
456 adapter->rx_abs_int_delay = RxAbsIntDelay[bd]; 487 if (num_RxAbsIntDelay > bd) {
457 e1000_validate_option(&adapter->rx_abs_int_delay, &opt, 488 adapter->rx_abs_int_delay = RxAbsIntDelay[bd];
458 adapter); 489 e1000_validate_option(&adapter->rx_abs_int_delay, &opt,
490 adapter);
491 } else {
492 adapter->rx_abs_int_delay = opt.def;
493 }
459 } 494 }
460 { /* Interrupt Throttling Rate */ 495 { /* Interrupt Throttling Rate */
461 struct e1000_option opt = { 496 struct e1000_option opt = {
@@ -467,18 +502,24 @@ e1000_check_options(struct e1000_adapter *adapter)
467 .max = MAX_ITR }} 502 .max = MAX_ITR }}
468 }; 503 };
469 504
470 adapter->itr = InterruptThrottleRate[bd]; 505 if (num_InterruptThrottleRate > bd) {
471 switch (adapter->itr) { 506 adapter->itr = InterruptThrottleRate[bd];
472 case 0: 507 switch (adapter->itr) {
473 DPRINTK(PROBE, INFO, "%s turned off\n", opt.name); 508 case 0:
474 break; 509 DPRINTK(PROBE, INFO, "%s turned off\n",
475 case 1: 510 opt.name);
476 DPRINTK(PROBE, INFO, "%s set to dynamic mode\n", 511 break;
477 opt.name); 512 case 1:
478 break; 513 DPRINTK(PROBE, INFO, "%s set to dynamic mode\n",
479 default: 514 opt.name);
480 e1000_validate_option(&adapter->itr, &opt, adapter); 515 break;
481 break; 516 default:
517 e1000_validate_option(&adapter->itr, &opt,
518 adapter);
519 break;
520 }
521 } else {
522 adapter->itr = opt.def;
482 } 523 }
483 } 524 }
484 { /* Smart Power Down */ 525 { /* Smart Power Down */
@@ -489,9 +530,13 @@ e1000_check_options(struct e1000_adapter *adapter)
489 .def = OPTION_DISABLED 530 .def = OPTION_DISABLED
490 }; 531 };
491 532
492 int spd = SmartPowerDownEnable[bd]; 533 if (num_SmartPowerDownEnable > bd) {
493 e1000_validate_option(&spd, &opt, adapter); 534 int spd = SmartPowerDownEnable[bd];
494 adapter->smart_power_down = spd; 535 e1000_validate_option(&spd, &opt, adapter);
536 adapter->smart_power_down = spd;
537 } else {
538 adapter->smart_power_down = opt.def;
539 }
495 } 540 }
496 { /* Kumeran Lock Loss Workaround */ 541 { /* Kumeran Lock Loss Workaround */
497 struct e1000_option opt = { 542 struct e1000_option opt = {
@@ -501,9 +546,13 @@ e1000_check_options(struct e1000_adapter *adapter)
501 .def = OPTION_ENABLED 546 .def = OPTION_ENABLED
502 }; 547 };
503 548
549 if (num_KumeranLockLoss > bd) {
504 int kmrn_lock_loss = KumeranLockLoss[bd]; 550 int kmrn_lock_loss = KumeranLockLoss[bd];
505 e1000_validate_option(&kmrn_lock_loss, &opt, adapter); 551 e1000_validate_option(&kmrn_lock_loss, &opt, adapter);
506 adapter->hw.kmrn_lock_loss_workaround_disabled = !kmrn_lock_loss; 552 adapter->hw.kmrn_lock_loss_workaround_disabled = !kmrn_lock_loss;
553 } else {
554 adapter->hw.kmrn_lock_loss_workaround_disabled = !opt.def;
555 }
507 } 556 }
508 557
509 switch (adapter->hw.media_type) { 558 switch (adapter->hw.media_type) {
@@ -530,18 +579,17 @@ static void __devinit
530e1000_check_fiber_options(struct e1000_adapter *adapter) 579e1000_check_fiber_options(struct e1000_adapter *adapter)
531{ 580{
532 int bd = adapter->bd_number; 581 int bd = adapter->bd_number;
533 bd = bd > E1000_MAX_NIC ? E1000_MAX_NIC : bd; 582 if (num_Speed > bd) {
534 if ((Speed[bd] != OPTION_UNSET)) {
535 DPRINTK(PROBE, INFO, "Speed not valid for fiber adapters, " 583 DPRINTK(PROBE, INFO, "Speed not valid for fiber adapters, "
536 "parameter ignored\n"); 584 "parameter ignored\n");
537 } 585 }
538 586
539 if ((Duplex[bd] != OPTION_UNSET)) { 587 if (num_Duplex > bd) {
540 DPRINTK(PROBE, INFO, "Duplex not valid for fiber adapters, " 588 DPRINTK(PROBE, INFO, "Duplex not valid for fiber adapters, "
541 "parameter ignored\n"); 589 "parameter ignored\n");
542 } 590 }
543 591
544 if ((AutoNeg[bd] != OPTION_UNSET) && (AutoNeg[bd] != 0x20)) { 592 if ((num_AutoNeg > bd) && (AutoNeg[bd] != 0x20)) {
545 DPRINTK(PROBE, INFO, "AutoNeg other than 1000/Full is " 593 DPRINTK(PROBE, INFO, "AutoNeg other than 1000/Full is "
546 "not valid for fiber adapters, " 594 "not valid for fiber adapters, "
547 "parameter ignored\n"); 595 "parameter ignored\n");
@@ -560,7 +608,6 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
560{ 608{
561 int speed, dplx, an; 609 int speed, dplx, an;
562 int bd = adapter->bd_number; 610 int bd = adapter->bd_number;
563 bd = bd > E1000_MAX_NIC ? E1000_MAX_NIC : bd;
564 611
565 { /* Speed */ 612 { /* Speed */
566 struct e1000_opt_list speed_list[] = {{ 0, "" }, 613 struct e1000_opt_list speed_list[] = {{ 0, "" },
@@ -577,8 +624,12 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
577 .p = speed_list }} 624 .p = speed_list }}
578 }; 625 };
579 626
580 speed = Speed[bd]; 627 if (num_Speed > bd) {
581 e1000_validate_option(&speed, &opt, adapter); 628 speed = Speed[bd];
629 e1000_validate_option(&speed, &opt, adapter);
630 } else {
631 speed = opt.def;
632 }
582 } 633 }
583 { /* Duplex */ 634 { /* Duplex */
584 struct e1000_opt_list dplx_list[] = {{ 0, "" }, 635 struct e1000_opt_list dplx_list[] = {{ 0, "" },
@@ -600,11 +651,15 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
600 "Speed/Duplex/AutoNeg parameter ignored.\n"); 651 "Speed/Duplex/AutoNeg parameter ignored.\n");
601 return; 652 return;
602 } 653 }
603 dplx = Duplex[bd]; 654 if (num_Duplex > bd) {
604 e1000_validate_option(&dplx, &opt, adapter); 655 dplx = Duplex[bd];
656 e1000_validate_option(&dplx, &opt, adapter);
657 } else {
658 dplx = opt.def;
659 }
605 } 660 }
606 661
607 if (AutoNeg[bd] != OPTION_UNSET && (speed != 0 || dplx != 0)) { 662 if ((num_AutoNeg > bd) && (speed != 0 || dplx != 0)) {
608 DPRINTK(PROBE, INFO, 663 DPRINTK(PROBE, INFO,
609 "AutoNeg specified along with Speed or Duplex, " 664 "AutoNeg specified along with Speed or Duplex, "
610 "parameter ignored\n"); 665 "parameter ignored\n");
@@ -653,15 +708,19 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
653 .p = an_list }} 708 .p = an_list }}
654 }; 709 };
655 710
656 an = AutoNeg[bd]; 711 if (num_AutoNeg > bd) {
657 e1000_validate_option(&an, &opt, adapter); 712 an = AutoNeg[bd];
713 e1000_validate_option(&an, &opt, adapter);
714 } else {
715 an = opt.def;
716 }
658 adapter->hw.autoneg_advertised = an; 717 adapter->hw.autoneg_advertised = an;
659 } 718 }
660 719
661 switch (speed + dplx) { 720 switch (speed + dplx) {
662 case 0: 721 case 0:
663 adapter->hw.autoneg = adapter->fc_autoneg = 1; 722 adapter->hw.autoneg = adapter->fc_autoneg = 1;
664 if (Speed[bd] != OPTION_UNSET || Duplex[bd] != OPTION_UNSET) 723 if ((num_Speed > bd) && (speed != 0 || dplx != 0))
665 DPRINTK(PROBE, INFO, 724 DPRINTK(PROBE, INFO,
666 "Speed and duplex autonegotiation enabled\n"); 725 "Speed and duplex autonegotiation enabled\n");
667 break; 726 break;
diff --git a/drivers/net/ixgb/ixgb.h b/drivers/net/ixgb/ixgb.h
index 82b67af54c94..a51604b3651f 100644
--- a/drivers/net/ixgb/ixgb.h
+++ b/drivers/net/ixgb/ixgb.h
@@ -110,9 +110,6 @@ struct ixgb_adapter;
110#define IXGB_RXBUFFER_8192 8192 110#define IXGB_RXBUFFER_8192 8192
111#define IXGB_RXBUFFER_16384 16384 111#define IXGB_RXBUFFER_16384 16384
112 112
113/* How many Tx Descriptors do we need to call netif_wake_queue? */
114#define IXGB_TX_QUEUE_WAKE 16
115
116/* How many Rx Buffers do we bundle into one write to the hardware ? */ 113/* How many Rx Buffers do we bundle into one write to the hardware ? */
117#define IXGB_RX_BUFFER_WRITE 4 /* Must be power of 2 */ 114#define IXGB_RX_BUFFER_WRITE 4 /* Must be power of 2 */
118 115
@@ -173,7 +170,7 @@ struct ixgb_adapter {
173 unsigned long led_status; 170 unsigned long led_status;
174 171
175 /* TX */ 172 /* TX */
176 struct ixgb_desc_ring tx_ring; 173 struct ixgb_desc_ring tx_ring ____cacheline_aligned_in_smp;
177 unsigned long timeo_start; 174 unsigned long timeo_start;
178 uint32_t tx_cmd_type; 175 uint32_t tx_cmd_type;
179 uint64_t hw_csum_tx_good; 176 uint64_t hw_csum_tx_good;
diff --git a/drivers/net/ixgb/ixgb_ethtool.c b/drivers/net/ixgb/ixgb_ethtool.c
index cf19b898ba9b..ba621083830a 100644
--- a/drivers/net/ixgb/ixgb_ethtool.c
+++ b/drivers/net/ixgb/ixgb_ethtool.c
@@ -654,11 +654,7 @@ ixgb_phys_id(struct net_device *netdev, uint32_t data)
654 654
655 mod_timer(&adapter->blink_timer, jiffies); 655 mod_timer(&adapter->blink_timer, jiffies);
656 656
657 if (data) 657 msleep_interruptible(data * 1000);
658 schedule_timeout_interruptible(data * HZ);
659 else
660 schedule_timeout_interruptible(MAX_SCHEDULE_TIMEOUT);
661
662 del_timer_sync(&adapter->blink_timer); 658 del_timer_sync(&adapter->blink_timer);
663 ixgb_led_off(&adapter->hw); 659 ixgb_led_off(&adapter->hw);
664 clear_bit(IXGB_LED_ON, &adapter->led_status); 660 clear_bit(IXGB_LED_ON, &adapter->led_status);
diff --git a/drivers/net/ixgb/ixgb_main.c b/drivers/net/ixgb/ixgb_main.c
index 346273d42f97..e36dee1dd333 100644
--- a/drivers/net/ixgb/ixgb_main.c
+++ b/drivers/net/ixgb/ixgb_main.c
@@ -36,7 +36,7 @@ static char ixgb_driver_string[] = "Intel(R) PRO/10GbE Network Driver";
36#else 36#else
37#define DRIVERNAPI "-NAPI" 37#define DRIVERNAPI "-NAPI"
38#endif 38#endif
39#define DRV_VERSION "1.0.109-k4"DRIVERNAPI 39#define DRV_VERSION "1.0.112-k2"DRIVERNAPI
40char ixgb_driver_version[] = DRV_VERSION; 40char ixgb_driver_version[] = DRV_VERSION;
41static char ixgb_copyright[] = "Copyright (c) 1999-2006 Intel Corporation."; 41static char ixgb_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
42 42
@@ -118,15 +118,26 @@ static void ixgb_restore_vlan(struct ixgb_adapter *adapter);
118static void ixgb_netpoll(struct net_device *dev); 118static void ixgb_netpoll(struct net_device *dev);
119#endif 119#endif
120 120
121/* Exported from other modules */ 121static pci_ers_result_t ixgb_io_error_detected (struct pci_dev *pdev,
122 enum pci_channel_state state);
123static pci_ers_result_t ixgb_io_slot_reset (struct pci_dev *pdev);
124static void ixgb_io_resume (struct pci_dev *pdev);
122 125
126/* Exported from other modules */
123extern void ixgb_check_options(struct ixgb_adapter *adapter); 127extern void ixgb_check_options(struct ixgb_adapter *adapter);
124 128
129static struct pci_error_handlers ixgb_err_handler = {
130 .error_detected = ixgb_io_error_detected,
131 .slot_reset = ixgb_io_slot_reset,
132 .resume = ixgb_io_resume,
133};
134
125static struct pci_driver ixgb_driver = { 135static struct pci_driver ixgb_driver = {
126 .name = ixgb_driver_name, 136 .name = ixgb_driver_name,
127 .id_table = ixgb_pci_tbl, 137 .id_table = ixgb_pci_tbl,
128 .probe = ixgb_probe, 138 .probe = ixgb_probe,
129 .remove = __devexit_p(ixgb_remove), 139 .remove = __devexit_p(ixgb_remove),
140 .err_handler = &ixgb_err_handler
130}; 141};
131 142
132MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 143MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
@@ -1174,6 +1185,7 @@ ixgb_tso(struct ixgb_adapter *adapter, struct sk_buff *skb)
1174 int err; 1185 int err;
1175 1186
1176 if (likely(skb_is_gso(skb))) { 1187 if (likely(skb_is_gso(skb))) {
1188 struct ixgb_buffer *buffer_info;
1177 if (skb_header_cloned(skb)) { 1189 if (skb_header_cloned(skb)) {
1178 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); 1190 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1179 if (err) 1191 if (err)
@@ -1196,6 +1208,8 @@ ixgb_tso(struct ixgb_adapter *adapter, struct sk_buff *skb)
1196 1208
1197 i = adapter->tx_ring.next_to_use; 1209 i = adapter->tx_ring.next_to_use;
1198 context_desc = IXGB_CONTEXT_DESC(adapter->tx_ring, i); 1210 context_desc = IXGB_CONTEXT_DESC(adapter->tx_ring, i);
1211 buffer_info = &adapter->tx_ring.buffer_info[i];
1212 WARN_ON(buffer_info->dma != 0);
1199 1213
1200 context_desc->ipcss = ipcss; 1214 context_desc->ipcss = ipcss;
1201 context_desc->ipcso = ipcso; 1215 context_desc->ipcso = ipcso;
@@ -1233,11 +1247,14 @@ ixgb_tx_csum(struct ixgb_adapter *adapter, struct sk_buff *skb)
1233 uint8_t css, cso; 1247 uint8_t css, cso;
1234 1248
1235 if(likely(skb->ip_summed == CHECKSUM_HW)) { 1249 if(likely(skb->ip_summed == CHECKSUM_HW)) {
1250 struct ixgb_buffer *buffer_info;
1236 css = skb->h.raw - skb->data; 1251 css = skb->h.raw - skb->data;
1237 cso = (skb->h.raw + skb->csum) - skb->data; 1252 cso = (skb->h.raw + skb->csum) - skb->data;
1238 1253
1239 i = adapter->tx_ring.next_to_use; 1254 i = adapter->tx_ring.next_to_use;
1240 context_desc = IXGB_CONTEXT_DESC(adapter->tx_ring, i); 1255 context_desc = IXGB_CONTEXT_DESC(adapter->tx_ring, i);
1256 buffer_info = &adapter->tx_ring.buffer_info[i];
1257 WARN_ON(buffer_info->dma != 0);
1241 1258
1242 context_desc->tucss = css; 1259 context_desc->tucss = css;
1243 context_desc->tucso = cso; 1260 context_desc->tucso = cso;
@@ -1283,6 +1300,7 @@ ixgb_tx_map(struct ixgb_adapter *adapter, struct sk_buff *skb,
1283 buffer_info = &tx_ring->buffer_info[i]; 1300 buffer_info = &tx_ring->buffer_info[i];
1284 size = min(len, IXGB_MAX_DATA_PER_TXD); 1301 size = min(len, IXGB_MAX_DATA_PER_TXD);
1285 buffer_info->length = size; 1302 buffer_info->length = size;
1303 WARN_ON(buffer_info->dma != 0);
1286 buffer_info->dma = 1304 buffer_info->dma =
1287 pci_map_single(adapter->pdev, 1305 pci_map_single(adapter->pdev,
1288 skb->data + offset, 1306 skb->data + offset,
@@ -1543,6 +1561,11 @@ void
1543ixgb_update_stats(struct ixgb_adapter *adapter) 1561ixgb_update_stats(struct ixgb_adapter *adapter)
1544{ 1562{
1545 struct net_device *netdev = adapter->netdev; 1563 struct net_device *netdev = adapter->netdev;
1564 struct pci_dev *pdev = adapter->pdev;
1565
1566 /* Prevent stats update while adapter is being reset */
1567 if (pdev->error_state && pdev->error_state != pci_channel_io_normal)
1568 return;
1546 1569
1547 if((netdev->flags & IFF_PROMISC) || (netdev->flags & IFF_ALLMULTI) || 1570 if((netdev->flags & IFF_PROMISC) || (netdev->flags & IFF_ALLMULTI) ||
1548 (netdev->mc_count > IXGB_MAX_NUM_MULTICAST_ADDRESSES)) { 1571 (netdev->mc_count > IXGB_MAX_NUM_MULTICAST_ADDRESSES)) {
@@ -1787,7 +1810,7 @@ ixgb_clean_tx_irq(struct ixgb_adapter *adapter)
1787 if (unlikely(netif_queue_stopped(netdev))) { 1810 if (unlikely(netif_queue_stopped(netdev))) {
1788 spin_lock(&adapter->tx_lock); 1811 spin_lock(&adapter->tx_lock);
1789 if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev) && 1812 if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev) &&
1790 (IXGB_DESC_UNUSED(tx_ring) > IXGB_TX_QUEUE_WAKE)) 1813 (IXGB_DESC_UNUSED(tx_ring) >= DESC_NEEDED))
1791 netif_wake_queue(netdev); 1814 netif_wake_queue(netdev);
1792 spin_unlock(&adapter->tx_lock); 1815 spin_unlock(&adapter->tx_lock);
1793 } 1816 }
@@ -1948,10 +1971,9 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
1948#define IXGB_CB_LENGTH 256 1971#define IXGB_CB_LENGTH 256
1949 if (length < IXGB_CB_LENGTH) { 1972 if (length < IXGB_CB_LENGTH) {
1950 struct sk_buff *new_skb = 1973 struct sk_buff *new_skb =
1951 dev_alloc_skb(length + NET_IP_ALIGN); 1974 netdev_alloc_skb(netdev, length + NET_IP_ALIGN);
1952 if (new_skb) { 1975 if (new_skb) {
1953 skb_reserve(new_skb, NET_IP_ALIGN); 1976 skb_reserve(new_skb, NET_IP_ALIGN);
1954 new_skb->dev = netdev;
1955 memcpy(new_skb->data - NET_IP_ALIGN, 1977 memcpy(new_skb->data - NET_IP_ALIGN,
1956 skb->data - NET_IP_ALIGN, 1978 skb->data - NET_IP_ALIGN,
1957 length + NET_IP_ALIGN); 1979 length + NET_IP_ALIGN);
@@ -2031,14 +2053,14 @@ ixgb_alloc_rx_buffers(struct ixgb_adapter *adapter)
2031 /* leave three descriptors unused */ 2053 /* leave three descriptors unused */
2032 while(--cleancount > 2) { 2054 while(--cleancount > 2) {
2033 /* recycle! its good for you */ 2055 /* recycle! its good for you */
2034 if (!(skb = buffer_info->skb)) 2056 skb = buffer_info->skb;
2035 skb = dev_alloc_skb(adapter->rx_buffer_len 2057 if (skb) {
2036 + NET_IP_ALIGN);
2037 else {
2038 skb_trim(skb, 0); 2058 skb_trim(skb, 0);
2039 goto map_skb; 2059 goto map_skb;
2040 } 2060 }
2041 2061
2062 skb = netdev_alloc_skb(netdev, adapter->rx_buffer_len
2063 + NET_IP_ALIGN);
2042 if (unlikely(!skb)) { 2064 if (unlikely(!skb)) {
2043 /* Better luck next round */ 2065 /* Better luck next round */
2044 adapter->alloc_rx_buff_failed++; 2066 adapter->alloc_rx_buff_failed++;
@@ -2051,8 +2073,6 @@ ixgb_alloc_rx_buffers(struct ixgb_adapter *adapter)
2051 */ 2073 */
2052 skb_reserve(skb, NET_IP_ALIGN); 2074 skb_reserve(skb, NET_IP_ALIGN);
2053 2075
2054 skb->dev = netdev;
2055
2056 buffer_info->skb = skb; 2076 buffer_info->skb = skb;
2057 buffer_info->length = adapter->rx_buffer_len; 2077 buffer_info->length = adapter->rx_buffer_len;
2058map_skb: 2078map_skb:
@@ -2190,7 +2210,7 @@ ixgb_restore_vlan(struct ixgb_adapter *adapter)
2190 2210
2191static void ixgb_netpoll(struct net_device *dev) 2211static void ixgb_netpoll(struct net_device *dev)
2192{ 2212{
2193 struct ixgb_adapter *adapter = dev->priv; 2213 struct ixgb_adapter *adapter = netdev_priv(dev);
2194 2214
2195 disable_irq(adapter->pdev->irq); 2215 disable_irq(adapter->pdev->irq);
2196 ixgb_intr(adapter->pdev->irq, dev, NULL); 2216 ixgb_intr(adapter->pdev->irq, dev, NULL);
@@ -2198,4 +2218,98 @@ static void ixgb_netpoll(struct net_device *dev)
2198} 2218}
2199#endif 2219#endif
2200 2220
2221/**
2222 * ixgb_io_error_detected() - called when PCI error is detected
2223 * @pdev pointer to pci device with error
2224 * @state pci channel state after error
2225 *
2226 * This callback is called by the PCI subsystem whenever
2227 * a PCI bus error is detected.
2228 */
2229static pci_ers_result_t ixgb_io_error_detected (struct pci_dev *pdev,
2230 enum pci_channel_state state)
2231{
2232 struct net_device *netdev = pci_get_drvdata(pdev);
2233 struct ixgb_adapter *adapter = netdev->priv;
2234
2235 if(netif_running(netdev))
2236 ixgb_down(adapter, TRUE);
2237
2238 pci_disable_device(pdev);
2239
2240 /* Request a slot reset. */
2241 return PCI_ERS_RESULT_NEED_RESET;
2242}
2243
2244/**
2245 * ixgb_io_slot_reset - called after the pci bus has been reset.
2246 * @pdev pointer to pci device with error
2247 *
2248 * This callback is called after the PCI buss has been reset.
2249 * Basically, this tries to restart the card from scratch.
2250 * This is a shortened version of the device probe/discovery code,
2251 * it resembles the first-half of the ixgb_probe() routine.
2252 */
2253static pci_ers_result_t ixgb_io_slot_reset (struct pci_dev *pdev)
2254{
2255 struct net_device *netdev = pci_get_drvdata(pdev);
2256 struct ixgb_adapter *adapter = netdev->priv;
2257
2258 if(pci_enable_device(pdev)) {
2259 DPRINTK(PROBE, ERR, "Cannot re-enable PCI device after reset.\n");
2260 return PCI_ERS_RESULT_DISCONNECT;
2261 }
2262
2263 /* Perform card reset only on one instance of the card */
2264 if (0 != PCI_FUNC (pdev->devfn))
2265 return PCI_ERS_RESULT_RECOVERED;
2266
2267 pci_set_master(pdev);
2268
2269 netif_carrier_off(netdev);
2270 netif_stop_queue(netdev);
2271 ixgb_reset(adapter);
2272
2273 /* Make sure the EEPROM is good */
2274 if(!ixgb_validate_eeprom_checksum(&adapter->hw)) {
2275 DPRINTK(PROBE, ERR, "After reset, the EEPROM checksum is not valid.\n");
2276 return PCI_ERS_RESULT_DISCONNECT;
2277 }
2278 ixgb_get_ee_mac_addr(&adapter->hw, netdev->dev_addr);
2279 memcpy(netdev->perm_addr, netdev->dev_addr, netdev->addr_len);
2280
2281 if(!is_valid_ether_addr(netdev->perm_addr)) {
2282 DPRINTK(PROBE, ERR, "After reset, invalid MAC address.\n");
2283 return PCI_ERS_RESULT_DISCONNECT;
2284 }
2285
2286 return PCI_ERS_RESULT_RECOVERED;
2287}
2288
2289/**
2290 * ixgb_io_resume - called when its OK to resume normal operations
2291 * @pdev pointer to pci device with error
2292 *
2293 * The error recovery driver tells us that its OK to resume
2294 * normal operation. Implementation resembles the second-half
2295 * of the ixgb_probe() routine.
2296 */
2297static void ixgb_io_resume (struct pci_dev *pdev)
2298{
2299 struct net_device *netdev = pci_get_drvdata(pdev);
2300 struct ixgb_adapter *adapter = netdev->priv;
2301
2302 pci_set_master(pdev);
2303
2304 if(netif_running(netdev)) {
2305 if(ixgb_up(adapter)) {
2306 printk ("ixgb: can't bring device back up after reset\n");
2307 return;
2308 }
2309 }
2310
2311 netif_device_attach(netdev);
2312 mod_timer(&adapter->watchdog_timer, jiffies);
2313}
2314
2201/* ixgb_main.c */ 2315/* ixgb_main.c */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-11 18:23:34 -0500