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authorBill Gatliff <bgat@billgatliff.com>2007-07-20 22:39:36 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-07-22 10:44:01 -0400
commit7bbb18c9f4783b6fb3bf27af71625b590cf4f00b (patch)
tree0f52553d0543e1b38a31bd152278956174bd13ca
parent3d50527bbf1b68e5206263ade414f0d966b00f74 (diff)
[ARM] 4507/1: pxa2xx clock_event_device
Reimplements arch/arm/mach-pxa/time.c using a clock_event_device based on OSMR0. Tested on PXA270, linux-2.6.22+arm:pxa patches. Signed-off-by: Bill Gatliff <bgat@billgatliff.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--arch/arm/mach-pxa/time.c258
1 files changed, 128 insertions, 130 deletions
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 6f91fd2d061a..98d27e646b09 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -1,9 +1,11 @@
1/* 1/*
2 * arch/arm/mach-pxa/time.c 2 * arch/arm/mach-pxa/time.c
3 * 3 *
4 * Author: Nicolas Pitre 4 * PXA clocksource, clockevents, and OST interrupt handlers.
5 * Created: Jun 15, 2001 5 * Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
6 * Copyright: MontaVista Software Inc. 6 *
7 * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
8 * by MontaVista Software, Inc. (Nico, your code rocks!)
7 * 9 *
8 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
@@ -12,164 +14,160 @@
12 14
13#include <linux/kernel.h> 15#include <linux/kernel.h>
14#include <linux/init.h> 16#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/interrupt.h> 17#include <linux/interrupt.h>
17#include <linux/time.h> 18#include <linux/clockchips.h>
18#include <linux/signal.h> 19
19#include <linux/errno.h>
20#include <linux/sched.h>
21#include <linux/clocksource.h>
22
23#include <asm/system.h>
24#include <asm/hardware.h>
25#include <asm/io.h>
26#include <asm/leds.h>
27#include <asm/irq.h>
28#include <asm/mach/irq.h> 20#include <asm/mach/irq.h>
29#include <asm/mach/time.h> 21#include <asm/mach/time.h>
30#include <asm/arch/pxa-regs.h> 22#include <asm/arch/pxa-regs.h>
31 23
32
33static int pxa_set_rtc(void)
34{
35 unsigned long current_time = xtime.tv_sec;
36
37 if (RTSR & RTSR_ALE) {
38 /* make sure not to forward the clock over an alarm */
39 unsigned long alarm = RTAR;
40 if (current_time >= alarm && alarm >= RCNR)
41 return -ERESTARTSYS;
42 }
43 RCNR = current_time;
44 return 0;
45}
46
47#ifdef CONFIG_NO_IDLE_HZ
48static unsigned long initial_match;
49static int match_posponed;
50#endif
51
52static irqreturn_t 24static irqreturn_t
53pxa_timer_interrupt(int irq, void *dev_id) 25pxa_ost0_interrupt(int irq, void *dev_id)
54{ 26{
55 int next_match; 27 int next_match;
56 28 struct clock_event_device *c = dev_id;
57 write_seqlock(&xtime_lock); 29
58 30 if (c->mode == CLOCK_EVT_MODE_ONESHOT) {
59#ifdef CONFIG_NO_IDLE_HZ 31 /* Disarm the compare/match, signal the event. */
60 if (match_posponed) { 32 OIER &= ~OIER_E0;
61 match_posponed = 0; 33 c->event_handler(c);
62 OSMR0 = initial_match; 34 } else if (c->mode == CLOCK_EVT_MODE_PERIODIC) {
63 } 35 /* Call the event handler as many times as necessary
64#endif 36 * to recover missed events, if any (if we update
65 37 * OSMR0 and OSCR0 is still ahead of us, we've missed
66 /* Loop until we get ahead of the free running timer. 38 * the event). As we're dealing with that, re-arm the
67 * This ensures an exact clock tick count and time accuracy. 39 * compare/match for the next event.
68 * Since IRQs are disabled at this point, coherence between 40 *
69 * lost_ticks(updated in do_timer()) and the match reg value is 41 * HACK ALERT:
70 * ensured, hence we can use do_gettimeofday() from interrupt 42 *
71 * handlers. 43 * There's a latency between the instruction that
72 * 44 * writes to OSMR0 and the actual commit to the
73 * HACK ALERT: it seems that the PXA timer regs aren't updated right 45 * physical hardware, because the CPU doesn't (have
74 * away in all cases when a write occurs. We therefore compare with 46 * to) run at bus speed, there's a write buffer
75 * 8 instead of 0 in the while() condition below to avoid missing a 47 * between the CPU and the bus, etc. etc. So if the
76 * match if OSCR has already reached the next OSMR value. 48 * target OSCR0 is "very close", to the OSMR0 load
77 * Experience has shown that up to 6 ticks are needed to work around 49 * value, the update to OSMR0 might not get to the
78 * this problem, but let's use 8 to be conservative. Note that this 50 * hardware in time and we'll miss that interrupt.
79 * affect things only when the timer IRQ has been delayed by nearly 51 *
80 * exactly one tick period which should be a pretty rare event. 52 * To be safe, if the new OSMR0 is "very close" to the
53 * target OSCR0 value, we call the event_handler as
54 * though the event actually happened. According to
55 * Nico's comment in the previous version of this
56 * code, experience has shown that 6 OSCR ticks is
57 * "very close" but he went with 8. We will use 16,
58 * based on the results of testing on PXA270.
59 *
60 * To be doubly sure, we also tell clkevt via
61 * clockevents_register_device() not to ask for
62 * anything that might put us "very close".
81 */ 63 */
64#define MIN_OSCR_DELTA 16
82 do { 65 do {
83 timer_tick(); 66 OSSR = OSSR_M0;
84 OSSR = OSSR_M0; /* Clear match on timer 0 */
85 next_match = (OSMR0 += LATCH); 67 next_match = (OSMR0 += LATCH);
86 } while( (signed long)(next_match - OSCR) <= 8 ); 68 c->event_handler(c);
87 69 } while (((signed long)(next_match - OSCR) <= MIN_OSCR_DELTA)
88 write_sequnlock(&xtime_lock); 70 && (c->mode == CLOCK_EVT_MODE_PERIODIC));
71 }
89 72
90 return IRQ_HANDLED; 73 return IRQ_HANDLED;
91} 74}
92 75
93static struct irqaction pxa_timer_irq = { 76static int
94 .name = "PXA Timer Tick", 77pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
95 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 78{
96 .handler = pxa_timer_interrupt, 79 unsigned long irqflags;
80
81 raw_local_irq_save(irqflags);
82 OSMR0 = OSCR + delta;
83 OSSR = OSSR_M0;
84 OIER |= OIER_E0;
85 raw_local_irq_restore(irqflags);
86 return 0;
87}
88
89static void
90pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
91{
92 unsigned long irqflags;
93
94 switch (mode) {
95 case CLOCK_EVT_MODE_PERIODIC:
96 raw_local_irq_save(irqflags);
97 OSMR0 = OSCR + LATCH;
98 OSSR = OSSR_M0;
99 OIER |= OIER_E0;
100 raw_local_irq_restore(irqflags);
101 break;
102
103 case CLOCK_EVT_MODE_ONESHOT:
104 raw_local_irq_save(irqflags);
105 OIER &= ~OIER_E0;
106 raw_local_irq_restore(irqflags);
107 break;
108
109 case CLOCK_EVT_MODE_UNUSED:
110 case CLOCK_EVT_MODE_SHUTDOWN:
111 /* initializing, released, or preparing for suspend */
112 raw_local_irq_save(irqflags);
113 OIER &= ~OIER_E0;
114 raw_local_irq_restore(irqflags);
115 break;
116 }
117}
118
119static struct clock_event_device ckevt_pxa_osmr0 = {
120 .name = "osmr0",
121 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
122 .shift = 32,
123 .rating = 200,
124 .cpumask = CPU_MASK_CPU0,
125 .set_next_event = pxa_osmr0_set_next_event,
126 .set_mode = pxa_osmr0_set_mode,
97}; 127};
98 128
99static cycle_t pxa_get_cycles(void) 129static cycle_t pxa_read_oscr(void)
100{ 130{
101 return OSCR; 131 return OSCR;
102} 132}
103 133
104static struct clocksource clocksource_pxa = { 134static struct clocksource cksrc_pxa_oscr0 = {
105 .name = "pxa_timer", 135 .name = "oscr0",
106 .rating = 200, 136 .rating = 200,
107 .read = pxa_get_cycles, 137 .read = pxa_read_oscr,
108 .mask = CLOCKSOURCE_MASK(32), 138 .mask = CLOCKSOURCE_MASK(32),
109 .shift = 20, 139 .shift = 20,
110 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 140 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
111}; 141};
112 142
143static struct irqaction pxa_ost0_irq = {
144 .name = "ost0",
145 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
146 .handler = pxa_ost0_interrupt,
147 .dev_id = &ckevt_pxa_osmr0,
148};
149
113static void __init pxa_timer_init(void) 150static void __init pxa_timer_init(void)
114{ 151{
115 struct timespec tv; 152 OIER = 0;
116 unsigned long flags; 153 OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
117 154
118 set_rtc = pxa_set_rtc; 155 ckevt_pxa_osmr0.mult =
156 div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
157 ckevt_pxa_osmr0.max_delta_ns =
158 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
159 ckevt_pxa_osmr0.min_delta_ns =
160 clockevent_delta2ns(MIN_OSCR_DELTA, &ckevt_pxa_osmr0) + 1;
119 161
120 OIER = 0; /* disable any timer interrupts */ 162 cksrc_pxa_oscr0.mult =
121 OSSR = 0xf; /* clear status on all timers */ 163 clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_pxa_oscr0.shift);
122 setup_irq(IRQ_OST0, &pxa_timer_irq);
123 local_irq_save(flags);
124 OIER = OIER_E0; /* enable match on timer 0 to cause interrupts */
125 OSMR0 = OSCR + LATCH; /* set initial match */
126 local_irq_restore(flags);
127
128 /*
129 * OSCR runs continuously on PXA and is not written to,
130 * so we can use it as clock source directly.
131 */
132 clocksource_pxa.mult =
133 clocksource_hz2mult(CLOCK_TICK_RATE, clocksource_pxa.shift);
134 clocksource_register(&clocksource_pxa);
135}
136
137#ifdef CONFIG_NO_IDLE_HZ
138static int pxa_dyn_tick_enable_disable(void)
139{
140 /* nothing to do */
141 return 0;
142}
143 164
144static void pxa_dyn_tick_reprogram(unsigned long ticks) 165 setup_irq(IRQ_OST0, &pxa_ost0_irq);
145{
146 if (ticks > 1) {
147 initial_match = OSMR0;
148 OSMR0 = initial_match + ticks * LATCH;
149 match_posponed = 1;
150 }
151}
152 166
153static irqreturn_t 167 clocksource_register(&cksrc_pxa_oscr0);
154pxa_dyn_tick_handler(int irq, void *dev_id) 168 clockevents_register_device(&ckevt_pxa_osmr0);
155{
156 if (match_posponed) {
157 match_posponed = 0;
158 OSMR0 = initial_match;
159 if ( (signed long)(initial_match - OSCR) <= 8 )
160 return pxa_timer_interrupt(irq, dev_id);
161 }
162 return IRQ_NONE;
163} 169}
164 170
165static struct dyn_tick_timer pxa_dyn_tick = {
166 .enable = pxa_dyn_tick_enable_disable,
167 .disable = pxa_dyn_tick_enable_disable,
168 .reprogram = pxa_dyn_tick_reprogram,
169 .handler = pxa_dyn_tick_handler,
170};
171#endif
172
173#ifdef CONFIG_PM 171#ifdef CONFIG_PM
174static unsigned long osmr[4], oier; 172static unsigned long osmr[4], oier;
175 173
@@ -191,7 +189,10 @@ static void pxa_timer_resume(void)
191 OIER = oier; 189 OIER = oier;
192 190
193 /* 191 /*
194 * OSMR0 is the system timer: make sure OSCR is sufficiently behind 192 * OSCR0 is the system timer, which has to increase
193 * monotonically until it rolls over in hardware. The value
194 * (OSMR0 - LATCH) is OSCR0 at the most recent system tick,
195 * which is a handy value to restore to OSCR0.
195 */ 196 */
196 OSCR = OSMR0 - LATCH; 197 OSCR = OSMR0 - LATCH;
197} 198}
@@ -204,7 +205,4 @@ struct sys_timer pxa_timer = {
204 .init = pxa_timer_init, 205 .init = pxa_timer_init,
205 .suspend = pxa_timer_suspend, 206 .suspend = pxa_timer_suspend,
206 .resume = pxa_timer_resume, 207 .resume = pxa_timer_resume,
207#ifdef CONFIG_NO_IDLE_HZ
208 .dyn_tick = &pxa_dyn_tick,
209#endif
210}; 208};