[PATCH] ppc32: Added support for new MPC8548 family of PowerQUICC III processors

Added descriptions of the new MPC8548 family processors, e500 core and peripherals. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
author: Kumar Gala <galak@freescale.com> 2005-06-21 20:15:18 -0400
committer: Linus Torvalds <torvalds@ppc970.osdl.org> 2005-06-21 21:46:23 -0400
commit: 5b37b700f7c491a9320f4e29472bbaf23dded8fd (patch)
tree: e8a77c322bec5e75f0524c99f3be61645560b3c3
parent: da3caa204ca40c32dcb751ebead2a6835b83e8d1 (diff)
6 files changed, 323 insertions, 2 deletions
diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c
index d44b7dc5390a..01c226008dbf 100644
--- a/arch/ppc/kernel/cputable.c
+++ b/arch/ppc/kernel/cputable.c
@@ -918,6 +918,20 @@ struct cpu_spec	cpu_specs[] = {
                .dcache_bsize           = 32,
                .num_pmcs               = 4,
        },
+        {       /* e500v2 */
+                .pvr_mask               = 0xffff0000,
+                .pvr_value              = 0x80210000,
+                .cpu_name               = "e500v2",
+                /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
+                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                        CPU_FTR_USE_TB | CPU_FTR_BIG_PHYS,
+                .cpu_user_features      = PPC_FEATURE_32 |
+                        PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
+                        PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .num_pmcs               = 4,
+        },
 #endif
 #if !CLASSIC_PPC
        {       /* default match */
diff --git a/arch/ppc/syslib/mpc85xx_devices.c b/arch/ppc/syslib/mpc85xx_devices.c
index 1e658ef57e75..b30c57d4518f 100644
--- a/arch/ppc/syslib/mpc85xx_devices.c
+++ b/arch/ppc/syslib/mpc85xx_devices.c
@@ -40,6 +40,42 @@ static struct gianfar_platform_data mpc85xx_tsec2_pdata = {
        .phy_reg_addr = MPC85xx_ENET1_OFFSET,
 };
+static struct gianfar_platform_data mpc85xx_etsec1_pdata = {
+        .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
+            FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
+            FSL_GIANFAR_DEV_HAS_MULTI_INTR |
+            FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
+            FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
+        .phy_reg_addr = MPC85xx_ENET1_OFFSET,
+};
+static struct gianfar_platform_data mpc85xx_etsec2_pdata = {
+        .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
+            FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
+            FSL_GIANFAR_DEV_HAS_MULTI_INTR |
+            FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
+            FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
+        .phy_reg_addr = MPC85xx_ENET1_OFFSET,
+};
+static struct gianfar_platform_data mpc85xx_etsec3_pdata = {
+        .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
+            FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
+            FSL_GIANFAR_DEV_HAS_MULTI_INTR |
+            FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
+            FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
+        .phy_reg_addr = MPC85xx_ENET1_OFFSET,
+};
+static struct gianfar_platform_data mpc85xx_etsec4_pdata = {
+        .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
+            FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
+            FSL_GIANFAR_DEV_HAS_MULTI_INTR |
+            FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
+            FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
+        .phy_reg_addr = MPC85xx_ENET1_OFFSET,
+};
 static struct gianfar_platform_data mpc85xx_fec_pdata = {
        .phy_reg_addr = MPC85xx_ENET1_OFFSET,
 };
@@ -48,6 +84,10 @@ static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata = {
        .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
 };
+static struct fsl_i2c_platform_data mpc85xx_fsl_i2c2_pdata = {
+        .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
+};
 static struct plat_serial8250_port serial_platform_data[] = {
        [0] = {
                .mapbase        = 0x4500,
@@ -536,6 +576,151 @@ struct platform_device ppc_sys_platform_devices[] = {
                },
        },
 #endif /* CONFIG_CPM2 */
+        [MPC85xx_eTSEC1] = {
+                .name = "fsl-gianfar",
+                .id     = 1,
+                .dev.platform_data = &mpc85xx_etsec1_pdata,
+                .num_resources   = 4,
+                .resource = (struct resource[]) {
+                        {
+                                .start  = MPC85xx_ENET1_OFFSET,
+                                .end    = MPC85xx_ENET1_OFFSET +
+                                                MPC85xx_ENET1_SIZE - 1,
+                                .flags  = IORESOURCE_MEM,
+                        },
+                        {
+                                .name   = "tx",
+                                .start  = MPC85xx_IRQ_TSEC1_TX,
+                                .end    = MPC85xx_IRQ_TSEC1_TX,
+                                .flags  = IORESOURCE_IRQ,
+                        },
+                        {
+                                .name   = "rx",
+                                .start  = MPC85xx_IRQ_TSEC1_RX,
+                                .end    = MPC85xx_IRQ_TSEC1_RX,
+                                .flags  = IORESOURCE_IRQ,
+                        },
+                        {
+                                .name   = "error",
+                                .start  = MPC85xx_IRQ_TSEC1_ERROR,
+                                .end    = MPC85xx_IRQ_TSEC1_ERROR,
+                                .flags  = IORESOURCE_IRQ,
+                        },
+                },
+        },
+        [MPC85xx_eTSEC2] = {
+                .name = "fsl-gianfar",
+                .id     = 2,
+                .dev.platform_data = &mpc85xx_etsec2_pdata,
+                .num_resources   = 4,
+                .resource = (struct resource[]) {
+                        {
+                                .start  = MPC85xx_ENET2_OFFSET,
+                                .end    = MPC85xx_ENET2_OFFSET +
+                                                MPC85xx_ENET2_SIZE - 1,
+                                .flags  = IORESOURCE_MEM,
+                        },
+                        {
+                                .name   = "tx",
+                                .start  = MPC85xx_IRQ_TSEC2_TX,
+                                .end    = MPC85xx_IRQ_TSEC2_TX,
+                                .flags  = IORESOURCE_IRQ,
+                        },
+                        {
+                                .name   = "rx",
+                                .start  = MPC85xx_IRQ_TSEC2_RX,
+                                .end    = MPC85xx_IRQ_TSEC2_RX,
+                                .flags  = IORESOURCE_IRQ,
+                        },
+                        {
+                                .name   = "error",
+                                .start  = MPC85xx_IRQ_TSEC2_ERROR,
+                                .end    = MPC85xx_IRQ_TSEC2_ERROR,
+                                .flags  = IORESOURCE_IRQ,
+                        },
+                },
+        },
+        [MPC85xx_eTSEC3] = {
+                .name = "fsl-gianfar",
+                .id     = 3,
+                .dev.platform_data = &mpc85xx_etsec3_pdata,
+                .num_resources   = 4,
+                .resource = (struct resource[]) {
+                        {
+                                .start  = MPC85xx_ENET3_OFFSET,
+                                .end    = MPC85xx_ENET3_OFFSET +
+                                                MPC85xx_ENET3_SIZE - 1,
+                                .flags  = IORESOURCE_MEM,
+                        },
+                        {
+                                .name   = "tx",
+                                .start  = MPC85xx_IRQ_TSEC3_TX,
+                                .end    = MPC85xx_IRQ_TSEC3_TX,
+                                .flags  = IORESOURCE_IRQ,
+                        },
+                        {
+                                .name   = "rx",
+                                .start  = MPC85xx_IRQ_TSEC3_RX,
+                                .end    = MPC85xx_IRQ_TSEC3_RX,
+                                .flags  = IORESOURCE_IRQ,
+                        },
+                        {
+                                .name   = "error",
+                                .start  = MPC85xx_IRQ_TSEC3_ERROR,
+                                .end    = MPC85xx_IRQ_TSEC3_ERROR,
+                                .flags  = IORESOURCE_IRQ,
+                        },
+                },
+        },
+        [MPC85xx_eTSEC4] = {
+                .name = "fsl-gianfar",
+                .id     = 4,
+                .dev.platform_data = &mpc85xx_etsec4_pdata,
+                .num_resources   = 4,
+                .resource = (struct resource[]) {
+                        {
+                                .start  = 0x27000,
+                                .end    = 0x27fff,
+                                .flags  = IORESOURCE_MEM,
+                        },
+                        {
+                                .name   = "tx",
+                                .start  = MPC85xx_IRQ_TSEC4_TX,
+                                .end    = MPC85xx_IRQ_TSEC4_TX,
+                                .flags  = IORESOURCE_IRQ,
+                        },
+                        {
+                                .name   = "rx",
+                                .start  = MPC85xx_IRQ_TSEC4_RX,
+                                .end    = MPC85xx_IRQ_TSEC4_RX,
+                                .flags  = IORESOURCE_IRQ,
+                        },
+                        {
+                                .name   = "error",
+                                .start  = MPC85xx_IRQ_TSEC4_ERROR,
+                                .end    = MPC85xx_IRQ_TSEC4_ERROR,
+                                .flags  = IORESOURCE_IRQ,
+                        },
+                },
+        },
+        [MPC85xx_IIC2] = {
+                .name = "fsl-i2c",
+                .id     = 2,
+                .dev.platform_data = &mpc85xx_fsl_i2c2_pdata,
+                .num_resources   = 2,
+                .resource = (struct resource[]) {
+                        {
+                                .start  = 0x03100,
+                                .end    = 0x031ff,
+                                .flags  = IORESOURCE_MEM,
+                        },
+                        {
+                                .start  = MPC85xx_IRQ_IIC1,
+                                .end    = MPC85xx_IRQ_IIC1,
+                                .flags  = IORESOURCE_IRQ,
+                        },
+                },
+        },
 };
 static int __init mach_mpc85xx_fixup(struct platform_device *pdev)
diff --git a/arch/ppc/syslib/mpc85xx_sys.c b/arch/ppc/syslib/mpc85xx_sys.c
index d806a92a9401..6e3184ab354f 100644
--- a/arch/ppc/syslib/mpc85xx_sys.c
+++ b/arch/ppc/syslib/mpc85xx_sys.c
@@ -110,6 +110,111 @@ struct ppc_sys_spec ppc_sys_specs[] = {
                        MPC85xx_CPM_USB,
                },
        },
+        /* SVRs on 8548 rev1.0 matches for 8548/8547/8545 */
+        {
+                .ppc_sys_name   = "8548E",
+                .mask           = 0xFFFF00F0,
+                .value          = 0x80390010,
+                .num_devices    = 13,
+                .device_list    = (enum ppc_sys_devices[])
+                {
+                        MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
+                        MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
+                        MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
+                        MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
+                },
+        },
+        {
+                .ppc_sys_name   = "8548",
+                .mask           = 0xFFFF00F0,
+                .value          = 0x80310010,
+                .num_devices    = 12,
+                .device_list    = (enum ppc_sys_devices[])
+                {
+                        MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
+                        MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
+                        MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
+                        MPC85xx_PERFMON, MPC85xx_DUART,
+                },
+        },
+        {
+                .ppc_sys_name   = "8547E",
+                .mask           = 0xFFFF00F0,
+                .value          = 0x80390010,
+                .num_devices    = 13,
+                .device_list    = (enum ppc_sys_devices[])
+                {
+                        MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
+                        MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
+                        MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
+                        MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
+                },
+        },
+        {
+                .ppc_sys_name   = "8547",
+                .mask           = 0xFFFF00F0,
+                .value          = 0x80310010,
+                .num_devices    = 12,
+                .device_list    = (enum ppc_sys_devices[])
+                {
+                        MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
+                        MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
+                        MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
+                        MPC85xx_PERFMON, MPC85xx_DUART,
+                },
+        },
+        {
+                .ppc_sys_name   = "8545E",
+                .mask           = 0xFFFF00F0,
+                .value          = 0x80390010,
+                .num_devices    = 11,
+                .device_list    = (enum ppc_sys_devices[])
+                {
+                        MPC85xx_eTSEC1, MPC85xx_eTSEC2,
+                        MPC85xx_IIC1, MPC85xx_IIC2,
+                        MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
+                        MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
+                },
+        },
+        {
+                .ppc_sys_name   = "8545",
+                .mask           = 0xFFFF00F0,
+                .value          = 0x80310010,
+                .num_devices    = 10,
+                .device_list    = (enum ppc_sys_devices[])
+                {
+                        MPC85xx_eTSEC1, MPC85xx_eTSEC2,
+                        MPC85xx_IIC1, MPC85xx_IIC2,
+                        MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
+                        MPC85xx_PERFMON, MPC85xx_DUART,
+                },
+        },
+        {
+                .ppc_sys_name   = "8543E",
+                .mask           = 0xFFFF00F0,
+                .value          = 0x803A0010,
+                .num_devices    = 11,
+                .device_list    = (enum ppc_sys_devices[])
+                {
+                        MPC85xx_eTSEC1, MPC85xx_eTSEC2,
+                        MPC85xx_IIC1, MPC85xx_IIC2,
+                        MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
+                        MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
+                },
+        },
+        {
+                .ppc_sys_name   = "8543",
+                .mask           = 0xFFFF00F0,
+                .value          = 0x80320010,
+                .num_devices    = 10,
+                .device_list    = (enum ppc_sys_devices[])
+                {
+                        MPC85xx_eTSEC1, MPC85xx_eTSEC2,
+                        MPC85xx_IIC1, MPC85xx_IIC2,
+                        MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
+                        MPC85xx_PERFMON, MPC85xx_DUART,
+                },
+        },
        {       /* default match */
                .ppc_sys_name   = "",
                .mask           = 0x00000000,
diff --git a/include/asm-ppc/irq.h b/include/asm-ppc/irq.h
index 06b86be61ed1..434fc515ba64 100644
--- a/include/asm-ppc/irq.h
+++ b/include/asm-ppc/irq.h
@@ -223,9 +223,15 @@ static __inline__ int irq_canonicalize(int irq)
 #define MPC85xx_IRQ_RIO_RX      (12 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_TSEC1_TX    (13 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_TSEC1_RX    (14 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC3_TX    (15 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC3_RX    (16 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC3_ERROR (17 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_TSEC2_TX    (19 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_TSEC2_RX    (20 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC4_TX    (21 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC4_RX    (22 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC4_ERROR (23 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_FEC         (25 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_DUART       (26 + MPC85xx_OPENPIC_IRQ_OFFSET)
diff --git a/include/asm-ppc/mpc85xx.h b/include/asm-ppc/mpc85xx.h
index 22713e331585..51b61d3305f7 100644
--- a/include/asm-ppc/mpc85xx.h
+++ b/include/asm-ppc/mpc85xx.h
@@ -74,7 +74,7 @@ extern unsigned char __res[];
 #define MPC85xx_GUTS_OFFSET     (0xe0000)
 #define MPC85xx_GUTS_SIZE       (0x01000)
 #define MPC85xx_IIC1_OFFSET     (0x03000)
-#define MPC85xx_IIC1_SIZE       (0x01000)
+#define MPC85xx_IIC1_SIZE       (0x00100)
 #define MPC85xx_OPENPIC_OFFSET  (0x40000)
 #define MPC85xx_OPENPIC_SIZE    (0x40000)
 #define MPC85xx_PCI1_OFFSET     (0x08000)
@@ -127,6 +127,11 @@ enum ppc_sys_devices {
        MPC85xx_CPM_MCC2,
        MPC85xx_CPM_SMC1,
        MPC85xx_CPM_SMC2,
+        MPC85xx_eTSEC1,
+        MPC85xx_eTSEC2,
+        MPC85xx_eTSEC3,
+        MPC85xx_eTSEC4,
+        MPC85xx_IIC2,
 };
 #endif /* CONFIG_85xx */
diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index faaff4c64559..70f54af87b9f 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -51,6 +51,7 @@ struct gianfar_platform_data {
        /* board specific information */
        u32 board_flags;
+        u32 phy_flags;
        u32 phyid;
        u32 interruptPHY;
        u8 mac_addr[6];
@@ -61,9 +62,14 @@ struct gianfar_platform_data {
 #define FSL_GIANFAR_DEV_HAS_COALESCE            0x00000002
 #define FSL_GIANFAR_DEV_HAS_RMON                0x00000004
 #define FSL_GIANFAR_DEV_HAS_MULTI_INTR          0x00000008
+#define FSL_GIANFAR_DEV_HAS_CSUM                0x00000010
+#define FSL_GIANFAR_DEV_HAS_VLAN                0x00000020
+#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH       0x00000040
+#define FSL_GIANFAR_DEV_HAS_PADDING             0x00000080
 /* Flags in gianfar_platform_data */
-#define FSL_GIANFAR_BRD_HAS_PHY_INTR    0x00000001      /* if not set use a timer */
+#define FSL_GIANFAR_BRD_HAS_PHY_INTR    0x00000001 /* set or use a timer */
+#define FSL_GIANFAR_BRD_IS_REDUCED      0x00000002 /* Set if RGMII, RMII */
 struct fsl_i2c_platform_data {
        /* device specific information */
author	Kumar Gala <galak@freescale.com>	2005-06-21 20:15:18 -0400
committer	Linus Torvalds <torvalds@ppc970.osdl.org>	2005-06-21 21:46:23 -0400
commit	5b37b700f7c491a9320f4e29472bbaf23dded8fd (patch)
tree	e8a77c322bec5e75f0524c99f3be61645560b3c3
parent	da3caa204ca40c32dcb751ebead2a6835b83e8d1 (diff)

diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c index d44b7dc5390a..01c226008dbf 100644 --- a/arch/ppc/kernel/cputable.c +++ b/arch/ppc/kernel/cputable.c
@@ -918,6 +918,20 @@ struct cpu_spec cpu_specs[] = {
918	.dcache_bsize = 32,	918	.dcache_bsize = 32,
919	.num_pmcs = 4,	919	.num_pmcs = 4,
920	},	920	},
		921	{ /* e500v2 */
		922	.pvr_mask = 0xffff0000,
		923	.pvr_value = 0x80210000,
		924	.cpu_name = "e500v2",
		925	/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
		926	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
		927	CPU_FTR_USE_TB \| CPU_FTR_BIG_PHYS,
		928	.cpu_user_features = PPC_FEATURE_32 \|
		929	PPC_FEATURE_HAS_MMU \| PPC_FEATURE_SPE_COMP \|
		930	PPC_FEATURE_HAS_EFP_SINGLE \| PPC_FEATURE_HAS_EFP_DOUBLE,
		931	.icache_bsize = 32,
		932	.dcache_bsize = 32,
		933	.num_pmcs = 4,
		934	},
921	#endif	935	#endif
922	#if !CLASSIC_PPC	936	#if !CLASSIC_PPC
923	{ /* default match */	937	{ /* default match */


diff --git a/arch/ppc/syslib/mpc85xx_devices.c b/arch/ppc/syslib/mpc85xx_devices.c index 1e658ef57e75..b30c57d4518f 100644 --- a/arch/ppc/syslib/mpc85xx_devices.c +++ b/arch/ppc/syslib/mpc85xx_devices.c
@@ -40,6 +40,42 @@ static struct gianfar_platform_data mpc85xx_tsec2_pdata = {
40	.phy_reg_addr = MPC85xx_ENET1_OFFSET,	40	.phy_reg_addr = MPC85xx_ENET1_OFFSET,
41	};	41	};
42		42
		43	static struct gianfar_platform_data mpc85xx_etsec1_pdata = {
		44	.device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT \|
		45	FSL_GIANFAR_DEV_HAS_COALESCE \| FSL_GIANFAR_DEV_HAS_RMON \|
		46	FSL_GIANFAR_DEV_HAS_MULTI_INTR \|
		47	FSL_GIANFAR_DEV_HAS_CSUM \| FSL_GIANFAR_DEV_HAS_VLAN \|
		48	FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
		49	.phy_reg_addr = MPC85xx_ENET1_OFFSET,
		50	};
		51
		52	static struct gianfar_platform_data mpc85xx_etsec2_pdata = {
		53	.device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT \|
		54	FSL_GIANFAR_DEV_HAS_COALESCE \| FSL_GIANFAR_DEV_HAS_RMON \|
		55	FSL_GIANFAR_DEV_HAS_MULTI_INTR \|
		56	FSL_GIANFAR_DEV_HAS_CSUM \| FSL_GIANFAR_DEV_HAS_VLAN \|
		57	FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
		58	.phy_reg_addr = MPC85xx_ENET1_OFFSET,
		59	};
		60
		61	static struct gianfar_platform_data mpc85xx_etsec3_pdata = {
		62	.device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT \|
		63	FSL_GIANFAR_DEV_HAS_COALESCE \| FSL_GIANFAR_DEV_HAS_RMON \|
		64	FSL_GIANFAR_DEV_HAS_MULTI_INTR \|
		65	FSL_GIANFAR_DEV_HAS_CSUM \| FSL_GIANFAR_DEV_HAS_VLAN \|
		66	FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
		67	.phy_reg_addr = MPC85xx_ENET1_OFFSET,
		68	};
		69
		70	static struct gianfar_platform_data mpc85xx_etsec4_pdata = {
		71	.device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT \|
		72	FSL_GIANFAR_DEV_HAS_COALESCE \| FSL_GIANFAR_DEV_HAS_RMON \|
		73	FSL_GIANFAR_DEV_HAS_MULTI_INTR \|
		74	FSL_GIANFAR_DEV_HAS_CSUM \| FSL_GIANFAR_DEV_HAS_VLAN \|
		75	FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
		76	.phy_reg_addr = MPC85xx_ENET1_OFFSET,
		77	};
		78
43	static struct gianfar_platform_data mpc85xx_fec_pdata = {	79	static struct gianfar_platform_data mpc85xx_fec_pdata = {
44	.phy_reg_addr = MPC85xx_ENET1_OFFSET,	80	.phy_reg_addr = MPC85xx_ENET1_OFFSET,
45	};	81	};
@@ -48,6 +84,10 @@ static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata = {
48	.device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,	84	.device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
49	};	85	};
50		86
		87	static struct fsl_i2c_platform_data mpc85xx_fsl_i2c2_pdata = {
		88	.device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
		89	};
		90
51	static struct plat_serial8250_port serial_platform_data[] = {	91	static struct plat_serial8250_port serial_platform_data[] = {
52	[0] = {	92	[0] = {
53	.mapbase = 0x4500,	93	.mapbase = 0x4500,
@@ -536,6 +576,151 @@ struct platform_device ppc_sys_platform_devices[] = {
536	},	576	},
537	},	577	},
538	#endif /* CONFIG_CPM2 */	578	#endif /* CONFIG_CPM2 */
		579	[MPC85xx_eTSEC1] = {
		580	.name = "fsl-gianfar",
		581	.id = 1,
		582	.dev.platform_data = &mpc85xx_etsec1_pdata,
		583	.num_resources = 4,
		584	.resource = (struct resource[]) {
		585	{
		586	.start = MPC85xx_ENET1_OFFSET,
		587	.end = MPC85xx_ENET1_OFFSET +
		588	MPC85xx_ENET1_SIZE - 1,
		589	.flags = IORESOURCE_MEM,
		590	},
		591	{
		592	.name = "tx",
		593	.start = MPC85xx_IRQ_TSEC1_TX,
		594	.end = MPC85xx_IRQ_TSEC1_TX,
		595	.flags = IORESOURCE_IRQ,
		596	},
		597	{
		598	.name = "rx",
		599	.start = MPC85xx_IRQ_TSEC1_RX,
		600	.end = MPC85xx_IRQ_TSEC1_RX,
		601	.flags = IORESOURCE_IRQ,
		602	},
		603	{
		604	.name = "error",
		605	.start = MPC85xx_IRQ_TSEC1_ERROR,
		606	.end = MPC85xx_IRQ_TSEC1_ERROR,
		607	.flags = IORESOURCE_IRQ,
		608	},
		609	},
		610	},
		611	[MPC85xx_eTSEC2] = {
		612	.name = "fsl-gianfar",
		613	.id = 2,
		614	.dev.platform_data = &mpc85xx_etsec2_pdata,
		615	.num_resources = 4,
		616	.resource = (struct resource[]) {
		617	{
		618	.start = MPC85xx_ENET2_OFFSET,
		619	.end = MPC85xx_ENET2_OFFSET +
		620	MPC85xx_ENET2_SIZE - 1,
		621	.flags = IORESOURCE_MEM,
		622	},
		623	{
		624	.name = "tx",
		625	.start = MPC85xx_IRQ_TSEC2_TX,
		626	.end = MPC85xx_IRQ_TSEC2_TX,
		627	.flags = IORESOURCE_IRQ,
		628	},
		629	{
		630	.name = "rx",
		631	.start = MPC85xx_IRQ_TSEC2_RX,
		632	.end = MPC85xx_IRQ_TSEC2_RX,
		633	.flags = IORESOURCE_IRQ,
		634	},
		635	{
		636	.name = "error",
		637	.start = MPC85xx_IRQ_TSEC2_ERROR,
		638	.end = MPC85xx_IRQ_TSEC2_ERROR,
		639	.flags = IORESOURCE_IRQ,
		640	},
		641	},
		642	},
		643	[MPC85xx_eTSEC3] = {
		644	.name = "fsl-gianfar",
		645	.id = 3,
		646	.dev.platform_data = &mpc85xx_etsec3_pdata,
		647	.num_resources = 4,
		648	.resource = (struct resource[]) {
		649	{
		650	.start = MPC85xx_ENET3_OFFSET,
		651	.end = MPC85xx_ENET3_OFFSET +
		652	MPC85xx_ENET3_SIZE - 1,
		653	.flags = IORESOURCE_MEM,
		654	},
		655	{
		656	.name = "tx",
		657	.start = MPC85xx_IRQ_TSEC3_TX,
		658	.end = MPC85xx_IRQ_TSEC3_TX,
		659	.flags = IORESOURCE_IRQ,
		660	},
		661	{
		662	.name = "rx",
		663	.start = MPC85xx_IRQ_TSEC3_RX,
		664	.end = MPC85xx_IRQ_TSEC3_RX,
		665	.flags = IORESOURCE_IRQ,
		666	},
		667	{
		668	.name = "error",
		669	.start = MPC85xx_IRQ_TSEC3_ERROR,
		670	.end = MPC85xx_IRQ_TSEC3_ERROR,
		671	.flags = IORESOURCE_IRQ,
		672	},
		673	},
		674	},
		675	[MPC85xx_eTSEC4] = {
		676	.name = "fsl-gianfar",
		677	.id = 4,
		678	.dev.platform_data = &mpc85xx_etsec4_pdata,
		679	.num_resources = 4,
		680	.resource = (struct resource[]) {
		681	{
		682	.start = 0x27000,
		683	.end = 0x27fff,
		684	.flags = IORESOURCE_MEM,
		685	},
		686	{
		687	.name = "tx",
		688	.start = MPC85xx_IRQ_TSEC4_TX,
		689	.end = MPC85xx_IRQ_TSEC4_TX,
		690	.flags = IORESOURCE_IRQ,
		691	},
		692	{
		693	.name = "rx",
		694	.start = MPC85xx_IRQ_TSEC4_RX,
		695	.end = MPC85xx_IRQ_TSEC4_RX,
		696	.flags = IORESOURCE_IRQ,
		697	},
		698	{
		699	.name = "error",
		700	.start = MPC85xx_IRQ_TSEC4_ERROR,
		701	.end = MPC85xx_IRQ_TSEC4_ERROR,
		702	.flags = IORESOURCE_IRQ,
		703	},
		704	},
		705	},
		706	[MPC85xx_IIC2] = {
		707	.name = "fsl-i2c",
		708	.id = 2,
		709	.dev.platform_data = &mpc85xx_fsl_i2c2_pdata,
		710	.num_resources = 2,
		711	.resource = (struct resource[]) {
		712	{
		713	.start = 0x03100,
		714	.end = 0x031ff,
		715	.flags = IORESOURCE_MEM,
		716	},
		717	{
		718	.start = MPC85xx_IRQ_IIC1,
		719	.end = MPC85xx_IRQ_IIC1,
		720	.flags = IORESOURCE_IRQ,
		721	},
		722	},
		723	},
539	};	724	};
540		725
541	static int __init mach_mpc85xx_fixup(struct platform_device *pdev)	726	static int __init mach_mpc85xx_fixup(struct platform_device *pdev)


diff --git a/arch/ppc/syslib/mpc85xx_sys.c b/arch/ppc/syslib/mpc85xx_sys.c index d806a92a9401..6e3184ab354f 100644 --- a/arch/ppc/syslib/mpc85xx_sys.c +++ b/arch/ppc/syslib/mpc85xx_sys.c
@@ -110,6 +110,111 @@ struct ppc_sys_spec ppc_sys_specs[] = {
110	MPC85xx_CPM_USB,	110	MPC85xx_CPM_USB,
111	},	111	},
112	},	112	},
		113	/* SVRs on 8548 rev1.0 matches for 8548/8547/8545 */
		114	{
		115	.ppc_sys_name = "8548E",
		116	.mask = 0xFFFF00F0,
		117	.value = 0x80390010,
		118	.num_devices = 13,
		119	.device_list = (enum ppc_sys_devices[])
		120	{
		121	MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
		122	MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
		123	MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
		124	MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
		125	},
		126	},
		127	{
		128	.ppc_sys_name = "8548",
		129	.mask = 0xFFFF00F0,
		130	.value = 0x80310010,
		131	.num_devices = 12,
		132	.device_list = (enum ppc_sys_devices[])
		133	{
		134	MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
		135	MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
		136	MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
		137	MPC85xx_PERFMON, MPC85xx_DUART,
		138	},
		139	},
		140	{
		141	.ppc_sys_name = "8547E",
		142	.mask = 0xFFFF00F0,
		143	.value = 0x80390010,
		144	.num_devices = 13,
		145	.device_list = (enum ppc_sys_devices[])
		146	{
		147	MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
		148	MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
		149	MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
		150	MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
		151	},
		152	},
		153	{
		154	.ppc_sys_name = "8547",
		155	.mask = 0xFFFF00F0,
		156	.value = 0x80310010,
		157	.num_devices = 12,
		158	.device_list = (enum ppc_sys_devices[])
		159	{
		160	MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
		161	MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
		162	MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
		163	MPC85xx_PERFMON, MPC85xx_DUART,
		164	},
		165	},
		166	{
		167	.ppc_sys_name = "8545E",
		168	.mask = 0xFFFF00F0,
		169	.value = 0x80390010,
		170	.num_devices = 11,
		171	.device_list = (enum ppc_sys_devices[])
		172	{
		173	MPC85xx_eTSEC1, MPC85xx_eTSEC2,
		174	MPC85xx_IIC1, MPC85xx_IIC2,
		175	MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
		176	MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
		177	},
		178	},
		179	{
		180	.ppc_sys_name = "8545",
		181	.mask = 0xFFFF00F0,
		182	.value = 0x80310010,
		183	.num_devices = 10,
		184	.device_list = (enum ppc_sys_devices[])
		185	{
		186	MPC85xx_eTSEC1, MPC85xx_eTSEC2,
		187	MPC85xx_IIC1, MPC85xx_IIC2,
		188	MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
		189	MPC85xx_PERFMON, MPC85xx_DUART,
		190	},
		191	},
		192	{
		193	.ppc_sys_name = "8543E",
		194	.mask = 0xFFFF00F0,
		195	.value = 0x803A0010,
		196	.num_devices = 11,
		197	.device_list = (enum ppc_sys_devices[])
		198	{
		199	MPC85xx_eTSEC1, MPC85xx_eTSEC2,
		200	MPC85xx_IIC1, MPC85xx_IIC2,
		201	MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
		202	MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
		203	},
		204	},
		205	{
		206	.ppc_sys_name = "8543",
		207	.mask = 0xFFFF00F0,
		208	.value = 0x80320010,
		209	.num_devices = 10,
		210	.device_list = (enum ppc_sys_devices[])
		211	{
		212	MPC85xx_eTSEC1, MPC85xx_eTSEC2,
		213	MPC85xx_IIC1, MPC85xx_IIC2,
		214	MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
		215	MPC85xx_PERFMON, MPC85xx_DUART,
		216	},
		217	},
113	{ /* default match */	218	{ /* default match */
114	.ppc_sys_name = "",	219	.ppc_sys_name = "",
115	.mask = 0x00000000,	220	.mask = 0x00000000,


diff --git a/include/asm-ppc/irq.h b/include/asm-ppc/irq.h index 06b86be61ed1..434fc515ba64 100644 --- a/include/asm-ppc/irq.h +++ b/include/asm-ppc/irq.h
@@ -223,9 +223,15 @@ static __inline__ int irq_canonicalize(int irq)
223	#define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET)	223	#define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET)
224	#define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET)	224	#define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET)
225	#define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET)	225	#define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET)
		226	#define MPC85xx_IRQ_TSEC3_TX (15 + MPC85xx_OPENPIC_IRQ_OFFSET)
		227	#define MPC85xx_IRQ_TSEC3_RX (16 + MPC85xx_OPENPIC_IRQ_OFFSET)
		228	#define MPC85xx_IRQ_TSEC3_ERROR (17 + MPC85xx_OPENPIC_IRQ_OFFSET)
226	#define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET)	229	#define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET)
227	#define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET)	230	#define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET)
228	#define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET)	231	#define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET)
		232	#define MPC85xx_IRQ_TSEC4_TX (21 + MPC85xx_OPENPIC_IRQ_OFFSET)
		233	#define MPC85xx_IRQ_TSEC4_RX (22 + MPC85xx_OPENPIC_IRQ_OFFSET)
		234	#define MPC85xx_IRQ_TSEC4_ERROR (23 + MPC85xx_OPENPIC_IRQ_OFFSET)
229	#define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET)	235	#define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET)
230	#define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET)	236	#define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET)
231	#define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET)	237	#define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET)


diff --git a/include/asm-ppc/mpc85xx.h b/include/asm-ppc/mpc85xx.h index 22713e331585..51b61d3305f7 100644 --- a/include/asm-ppc/mpc85xx.h +++ b/include/asm-ppc/mpc85xx.h
@@ -74,7 +74,7 @@ extern unsigned char __res[];
74	#define MPC85xx_GUTS_OFFSET (0xe0000)	74	#define MPC85xx_GUTS_OFFSET (0xe0000)
75	#define MPC85xx_GUTS_SIZE (0x01000)	75	#define MPC85xx_GUTS_SIZE (0x01000)
76	#define MPC85xx_IIC1_OFFSET (0x03000)	76	#define MPC85xx_IIC1_OFFSET (0x03000)
77	#define MPC85xx_IIC1_SIZE (0x01000)	77	#define MPC85xx_IIC1_SIZE (0x00100)
78	#define MPC85xx_OPENPIC_OFFSET (0x40000)	78	#define MPC85xx_OPENPIC_OFFSET (0x40000)
79	#define MPC85xx_OPENPIC_SIZE (0x40000)	79	#define MPC85xx_OPENPIC_SIZE (0x40000)
80	#define MPC85xx_PCI1_OFFSET (0x08000)	80	#define MPC85xx_PCI1_OFFSET (0x08000)
@@ -127,6 +127,11 @@ enum ppc_sys_devices {
127	MPC85xx_CPM_MCC2,	127	MPC85xx_CPM_MCC2,
128	MPC85xx_CPM_SMC1,	128	MPC85xx_CPM_SMC1,
129	MPC85xx_CPM_SMC2,	129	MPC85xx_CPM_SMC2,
		130	MPC85xx_eTSEC1,
		131	MPC85xx_eTSEC2,
		132	MPC85xx_eTSEC3,
		133	MPC85xx_eTSEC4,
		134	MPC85xx_IIC2,
130	};	135	};
131		136
132	#endif /* CONFIG_85xx */	137	#endif /* CONFIG_85xx */


diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index faaff4c64559..70f54af87b9f 100644 --- a/include/linux/fsl_devices.h +++ b/include/linux/fsl_devices.h
@@ -51,6 +51,7 @@ struct gianfar_platform_data {
51		51
52	/* board specific information */	52	/* board specific information */
53	u32 board_flags;	53	u32 board_flags;
		54	u32 phy_flags;
54	u32 phyid;	55	u32 phyid;
55	u32 interruptPHY;	56	u32 interruptPHY;
56	u8 mac_addr[6];	57	u8 mac_addr[6];
@@ -61,9 +62,14 @@ struct gianfar_platform_data {
61	#define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002	62	#define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002
62	#define FSL_GIANFAR_DEV_HAS_RMON 0x00000004	63	#define FSL_GIANFAR_DEV_HAS_RMON 0x00000004
63	#define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008	64	#define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008
		65	#define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010
		66	#define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020
		67	#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040
		68	#define FSL_GIANFAR_DEV_HAS_PADDING 0x00000080
64		69
65	/* Flags in gianfar_platform_data */	70	/* Flags in gianfar_platform_data */
66	#define FSL_GIANFAR_BRD_HAS_PHY_INTR 0x00000001 /* if not set use a timer */	71	#define FSL_GIANFAR_BRD_HAS_PHY_INTR 0x00000001 /* set or use a timer */
		72	#define FSL_GIANFAR_BRD_IS_REDUCED 0x00000002 /* Set if RGMII, RMII */
67		73
68	struct fsl_i2c_platform_data {	74	struct fsl_i2c_platform_data {
69	/* device specific information */	75	/* device specific information */