aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorTrond Myklebust <Trond.Myklebust@netapp.com>2007-06-16 14:17:01 -0400
committerTrond Myklebust <Trond.Myklebust@netapp.com>2007-07-10 23:40:28 -0400
commit4bef61ff7514396419563ca54fd42ef846485b06 (patch)
tree5ea7eca032557a8ae307661b8c2b887fac257476
parent6529eba08fe7297852391a468d95322913de73fa (diff)
SUNRPC: Add a per-rpc_clnt spinlock
Use that to protect the rpc_clnt->cl_tasks list instead of using a global lock. Signed-off-by: Trond Myklebust <Trond.Myklebust@netapp.com>
-rw-r--r--include/linux/sunrpc/clnt.h1
-rw-r--r--net/sunrpc/clnt.c2
-rw-r--r--net/sunrpc/sched.c47
3 files changed, 30 insertions, 20 deletions
diff --git a/include/linux/sunrpc/clnt.h b/include/linux/sunrpc/clnt.h
index 0801ab5407ce..2f4b520a7419 100644
--- a/include/linux/sunrpc/clnt.h
+++ b/include/linux/sunrpc/clnt.h
@@ -28,6 +28,7 @@ struct rpc_clnt {
28 atomic_t cl_users; /* number of references */ 28 atomic_t cl_users; /* number of references */
29 struct list_head cl_clients; /* Global list of clients */ 29 struct list_head cl_clients; /* Global list of clients */
30 struct list_head cl_tasks; /* List of tasks */ 30 struct list_head cl_tasks; /* List of tasks */
31 spinlock_t cl_lock; /* spinlock */
31 struct rpc_xprt * cl_xprt; /* transport */ 32 struct rpc_xprt * cl_xprt; /* transport */
32 struct rpc_procinfo * cl_procinfo; /* procedure info */ 33 struct rpc_procinfo * cl_procinfo; /* procedure info */
33 u32 cl_prog, /* RPC program number */ 34 u32 cl_prog, /* RPC program number */
diff --git a/net/sunrpc/clnt.c b/net/sunrpc/clnt.c
index 6631ece14983..424dfdc6862c 100644
--- a/net/sunrpc/clnt.c
+++ b/net/sunrpc/clnt.c
@@ -149,6 +149,7 @@ static struct rpc_clnt * rpc_new_client(struct rpc_xprt *xprt, char *servname, s
149 goto out_no_stats; 149 goto out_no_stats;
150 clnt->cl_program = program; 150 clnt->cl_program = program;
151 INIT_LIST_HEAD(&clnt->cl_tasks); 151 INIT_LIST_HEAD(&clnt->cl_tasks);
152 spin_lock_init(&clnt->cl_lock);
152 153
153 if (!xprt_bound(clnt->cl_xprt)) 154 if (!xprt_bound(clnt->cl_xprt))
154 clnt->cl_autobind = 1; 155 clnt->cl_autobind = 1;
@@ -286,6 +287,7 @@ rpc_clone_client(struct rpc_clnt *clnt)
286 new->cl_oneshot = 0; 287 new->cl_oneshot = 0;
287 new->cl_dead = 0; 288 new->cl_dead = 0;
288 INIT_LIST_HEAD(&new->cl_tasks); 289 INIT_LIST_HEAD(&new->cl_tasks);
290 spin_lock_init(&new->cl_lock);
289 rpc_init_rtt(&new->cl_rtt_default, clnt->cl_xprt->timeout.to_initval); 291 rpc_init_rtt(&new->cl_rtt_default, clnt->cl_xprt->timeout.to_initval);
290 if (new->cl_auth) 292 if (new->cl_auth)
291 atomic_inc(&new->cl_auth->au_count); 293 atomic_inc(&new->cl_auth->au_count);
diff --git a/net/sunrpc/sched.c b/net/sunrpc/sched.c
index 6309f3b52c53..f56ebc5a08f7 100644
--- a/net/sunrpc/sched.c
+++ b/net/sunrpc/sched.c
@@ -270,17 +270,22 @@ static int rpc_wait_bit_interruptible(void *word)
270 270
271static void rpc_set_active(struct rpc_task *task) 271static void rpc_set_active(struct rpc_task *task)
272{ 272{
273 struct rpc_clnt *clnt;
273 if (test_and_set_bit(RPC_TASK_ACTIVE, &task->tk_runstate) != 0) 274 if (test_and_set_bit(RPC_TASK_ACTIVE, &task->tk_runstate) != 0)
274 return; 275 return;
275 spin_lock(&rpc_sched_lock);
276#ifdef RPC_DEBUG 276#ifdef RPC_DEBUG
277 task->tk_magic = RPC_TASK_MAGIC_ID; 277 task->tk_magic = RPC_TASK_MAGIC_ID;
278 spin_lock(&rpc_sched_lock);
278 task->tk_pid = rpc_task_id++; 279 task->tk_pid = rpc_task_id++;
280 spin_unlock(&rpc_sched_lock);
279#endif 281#endif
280 /* Add to global list of all tasks */ 282 /* Add to global list of all tasks */
281 if (task->tk_client) 283 clnt = task->tk_client;
282 list_add_tail(&task->tk_task, &task->tk_client->cl_tasks); 284 if (clnt != NULL) {
283 spin_unlock(&rpc_sched_lock); 285 spin_lock(&clnt->cl_lock);
286 list_add_tail(&task->tk_task, &clnt->cl_tasks);
287 spin_unlock(&clnt->cl_lock);
288 }
284} 289}
285 290
286/* 291/*
@@ -924,10 +929,11 @@ static void rpc_release_task(struct rpc_task *task)
924 dprintk("RPC: %5u release task\n", task->tk_pid); 929 dprintk("RPC: %5u release task\n", task->tk_pid);
925 930
926 if (!list_empty(&task->tk_task)) { 931 if (!list_empty(&task->tk_task)) {
932 struct rpc_clnt *clnt = task->tk_client;
927 /* Remove from client task list */ 933 /* Remove from client task list */
928 spin_lock(&rpc_sched_lock); 934 spin_lock(&clnt->cl_lock);
929 list_del(&task->tk_task); 935 list_del(&task->tk_task);
930 spin_unlock(&rpc_sched_lock); 936 spin_unlock(&clnt->cl_lock);
931 } 937 }
932 BUG_ON (RPC_IS_QUEUED(task)); 938 BUG_ON (RPC_IS_QUEUED(task));
933 939
@@ -970,12 +976,19 @@ EXPORT_SYMBOL(rpc_run_task);
970 * Kill all tasks for the given client. 976 * Kill all tasks for the given client.
971 * XXX: kill their descendants as well? 977 * XXX: kill their descendants as well?
972 */ 978 */
973static void rpc_killall_tasks_locked(struct list_head *head) 979void rpc_killall_tasks(struct rpc_clnt *clnt)
974{ 980{
975 struct rpc_task *rovr; 981 struct rpc_task *rovr;
976 982
977 983
978 list_for_each_entry(rovr, head, tk_task) { 984 if (list_empty(&clnt->cl_tasks))
985 return;
986 dprintk("RPC: killing all tasks for client %p\n", clnt);
987 /*
988 * Spin lock all_tasks to prevent changes...
989 */
990 spin_lock(&clnt->cl_lock);
991 list_for_each_entry(rovr, &clnt->cl_tasks, tk_task) {
979 if (! RPC_IS_ACTIVATED(rovr)) 992 if (! RPC_IS_ACTIVATED(rovr))
980 continue; 993 continue;
981 if (!(rovr->tk_flags & RPC_TASK_KILLED)) { 994 if (!(rovr->tk_flags & RPC_TASK_KILLED)) {
@@ -984,17 +997,7 @@ static void rpc_killall_tasks_locked(struct list_head *head)
984 rpc_wake_up_task(rovr); 997 rpc_wake_up_task(rovr);
985 } 998 }
986 } 999 }
987} 1000 spin_unlock(&clnt->cl_lock);
988
989void rpc_killall_tasks(struct rpc_clnt *clnt)
990{
991 dprintk("RPC: killing all tasks for client %p\n", clnt);
992 /*
993 * Spin lock all_tasks to prevent changes...
994 */
995 spin_lock(&rpc_sched_lock);
996 rpc_killall_tasks_locked(&clnt->cl_tasks);
997 spin_unlock(&rpc_sched_lock);
998} 1001}
999 1002
1000static void rpciod_killall(void) 1003static void rpciod_killall(void)
@@ -1007,7 +1010,7 @@ static void rpciod_killall(void)
1007 1010
1008 spin_lock(&rpc_sched_lock); 1011 spin_lock(&rpc_sched_lock);
1009 list_for_each_entry(clnt, &all_clients, cl_clients) 1012 list_for_each_entry(clnt, &all_clients, cl_clients)
1010 rpc_killall_tasks_locked(&clnt->cl_tasks); 1013 rpc_killall_tasks(clnt);
1011 spin_unlock(&rpc_sched_lock); 1014 spin_unlock(&rpc_sched_lock);
1012 flush_workqueue(rpciod_workqueue); 1015 flush_workqueue(rpciod_workqueue);
1013 if (!list_empty(&all_clients)) 1016 if (!list_empty(&all_clients))
@@ -1110,6 +1113,9 @@ void rpc_show_tasks(void)
1110 printk("-pid- proc flgs status -client- -prog- --rqstp- -timeout " 1113 printk("-pid- proc flgs status -client- -prog- --rqstp- -timeout "
1111 "-rpcwait -action- ---ops--\n"); 1114 "-rpcwait -action- ---ops--\n");
1112 list_for_each_entry(clnt, &all_clients, cl_clients) { 1115 list_for_each_entry(clnt, &all_clients, cl_clients) {
1116 if (list_empty(&clnt->cl_tasks))
1117 continue;
1118 spin_lock(&clnt->cl_lock);
1113 list_for_each_entry(t, &clnt->cl_tasks, tk_task) { 1119 list_for_each_entry(t, &clnt->cl_tasks, tk_task) {
1114 const char *rpc_waitq = "none"; 1120 const char *rpc_waitq = "none";
1115 1121
@@ -1126,6 +1132,7 @@ void rpc_show_tasks(void)
1126 rpc_waitq, 1132 rpc_waitq,
1127 t->tk_action, t->tk_ops); 1133 t->tk_action, t->tk_ops);
1128 } 1134 }
1135 spin_unlock(&clnt->cl_lock);
1129 } 1136 }
1130out: 1137out:
1131 spin_unlock(&rpc_sched_lock); 1138 spin_unlock(&rpc_sched_lock);
pt">; nvm->address_bits = 16; break; case e1000_nvm_override_spi_small: nvm->page_size = 8; nvm->address_bits = 8; break; default: nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; break; } nvm->type = e1000_nvm_eeprom_spi; size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> E1000_EECD_SIZE_EX_SHIFT); /* Added to a constant, "size" becomes the left-shift value * for setting word_size. */ size += NVM_WORD_SIZE_BASE_SHIFT; nvm->word_size = 1 << size; return 0; } /** * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. * @hw: pointer to the HW structure * * This is a function pointer entry point called by the api module. **/ static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter) { struct e1000_hw *hw = &adapter->hw; struct e1000_mac_info *mac = &hw->mac; struct e1000_mac_operations *func = &mac->ops; /* Set media type */ switch (adapter->pdev->device) { case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: hw->media_type = e1000_media_type_internal_serdes; break; default: hw->media_type = e1000_media_type_copper; break; } /* Set mta register count */ mac->mta_reg_count = 128; /* Set rar entry count */ mac->rar_entry_count = E1000_RAR_ENTRIES; /* Set if manageability features are enabled. */ mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0; /* check for link */ switch (hw->media_type) { case e1000_media_type_copper: func->setup_physical_interface = e1000_setup_copper_link_80003es2lan; func->check_for_link = e1000e_check_for_copper_link; break; case e1000_media_type_fiber: func->setup_physical_interface = e1000e_setup_fiber_serdes_link; func->check_for_link = e1000e_check_for_fiber_link; break; case e1000_media_type_internal_serdes: func->setup_physical_interface = e1000e_setup_fiber_serdes_link; func->check_for_link = e1000e_check_for_serdes_link; break; default: return -E1000_ERR_CONFIG; break; } return 0; } static s32 e1000_get_invariants_80003es2lan(struct e1000_adapter *adapter) { struct e1000_hw *hw = &adapter->hw; s32 rc; rc = e1000_init_mac_params_80003es2lan(adapter); if (rc) return rc; rc = e1000_init_nvm_params_80003es2lan(hw); if (rc) return rc; rc = e1000_init_phy_params_80003es2lan(hw); if (rc) return rc; return 0; } /** * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY * @hw: pointer to the HW structure * * A wrapper to acquire access rights to the correct PHY. This is a * function pointer entry point called by the api module. **/ static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) { u16 mask; mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; return e1000_acquire_swfw_sync_80003es2lan(hw, mask); } /** * e1000_release_phy_80003es2lan - Release rights to access PHY * @hw: pointer to the HW structure * * A wrapper to release access rights to the correct PHY. This is a * function pointer entry point called by the api module. **/ static void e1000_release_phy_80003es2lan(struct e1000_hw *hw) { u16 mask; mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; e1000_release_swfw_sync_80003es2lan(hw, mask); } /** * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM * @hw: pointer to the HW structure * * Acquire the semaphore to access the EEPROM. This is a function * pointer entry point called by the api module. **/ static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) { s32 ret_val; ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); if (ret_val) return ret_val; ret_val = e1000e_acquire_nvm(hw); if (ret_val) e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); return ret_val; } /** * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM * @hw: pointer to the HW structure * * Release the semaphore used to access the EEPROM. This is a * function pointer entry point called by the api module. **/ static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) { e1000e_release_nvm(hw); e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); } /** * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore * @hw: pointer to the HW structure * @mask: specifies which semaphore to acquire * * Acquire the SW/FW semaphore to access the PHY or NVM. The mask * will also specify which port we're acquiring the lock for. **/ static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) { u32 swfw_sync; u32 swmask = mask; u32 fwmask = mask << 16; s32 i = 0; s32 timeout = 200; while (i < timeout) { if (e1000e_get_hw_semaphore(hw)) return -E1000_ERR_SWFW_SYNC; swfw_sync = er32(SW_FW_SYNC); if (!(swfw_sync & (fwmask | swmask))) break; /* Firmware currently using resource (fwmask) * or other software thread using resource (swmask) */ e1000e_put_hw_semaphore(hw); mdelay(5); i++; } if (i == timeout) { hw_dbg(hw, "Driver can't access resource, SW_FW_SYNC timeout.\n"); return -E1000_ERR_SWFW_SYNC; } swfw_sync |= swmask; ew32(SW_FW_SYNC, swfw_sync); e1000e_put_hw_semaphore(hw); return 0; } /** * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore * @hw: pointer to the HW structure * @mask: specifies which semaphore to acquire * * Release the SW/FW semaphore used to access the PHY or NVM. The mask * will also specify which port we're releasing the lock for. **/ static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) { u32 swfw_sync; while (e1000e_get_hw_semaphore(hw) != 0); /* Empty */ swfw_sync = er32(SW_FW_SYNC); swfw_sync &= ~mask; ew32(SW_FW_SYNC, swfw_sync); e1000e_put_hw_semaphore(hw); } /** * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register * @hw: pointer to the HW structure * @offset: offset of the register to read * @data: pointer to the data returned from the operation * * Read the GG82563 PHY register. This is a function pointer entry * point called by the api module. **/ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, u32 offset, u16 *data) { s32 ret_val; u32 page_select; u16 temp; /* Select Configuration Page */ if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) page_select = GG82563_PHY_PAGE_SELECT; else /* Use Alternative Page Select register to access * registers 30 and 31 */ page_select = GG82563_PHY_PAGE_SELECT_ALT; temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); ret_val = e1000e_write_phy_reg_m88(hw, page_select, temp); if (ret_val) return ret_val; /* The "ready" bit in the MDIC register may be incorrectly set * before the device has completed the "Page Select" MDI * transaction. So we wait 200us after each MDI command... */ udelay(200); /* ...and verify the command was successful. */ ret_val = e1000e_read_phy_reg_m88(hw, page_select, &temp); if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { ret_val = -E1000_ERR_PHY; return ret_val; } udelay(200); ret_val = e1000e_read_phy_reg_m88(hw, MAX_PHY_REG_ADDRESS & offset, data); udelay(200); return ret_val; } /** * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register * @hw: pointer to the HW structure * @offset: offset of the register to read * @data: value to write to the register * * Write to the GG82563 PHY register. This is a function pointer entry * point called by the api module. **/ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, u32 offset, u16 data) { s32 ret_val; u32 page_select; u16 temp; /* Select Configuration Page */ if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) page_select = GG82563_PHY_PAGE_SELECT; else /* Use Alternative Page Select register to access * registers 30 and 31 */ page_select = GG82563_PHY_PAGE_SELECT_ALT; temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); ret_val = e1000e_write_phy_reg_m88(hw, page_select, temp); if (ret_val) return ret_val; /* The "ready" bit in the MDIC register may be incorrectly set * before the device has completed the "Page Select" MDI * transaction. So we wait 200us after each MDI command... */ udelay(200); /* ...and verify the command was successful. */ ret_val = e1000e_read_phy_reg_m88(hw, page_select, &temp); if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) return -E1000_ERR_PHY; udelay(200); ret_val = e1000e_write_phy_reg_m88(hw, MAX_PHY_REG_ADDRESS & offset, data); udelay(200); return ret_val; } /** * e1000_write_nvm_80003es2lan - Write to ESB2 NVM * @hw: pointer to the HW structure * @offset: offset of the register to read * @words: number of words to write * @data: buffer of data to write to the NVM * * Write "words" of data to the ESB2 NVM. This is a function * pointer entry point called by the api module. **/ static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) { return e1000e_write_nvm_spi(hw, offset, words, data); } /** * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete * @hw: pointer to the HW structure * * Wait a specific amount of time for manageability processes to complete. * This is a function pointer entry point called by the phy module. **/ static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) { s32 timeout = PHY_CFG_TIMEOUT; u32 mask = E1000_NVM_CFG_DONE_PORT_0; if (hw->bus.func == 1) mask = E1000_NVM_CFG_DONE_PORT_1; while (timeout) { if (er32(EEMNGCTL) & mask) break; msleep(1); timeout--; } if (!timeout) { hw_dbg(hw, "MNG configuration cycle has not completed.\n"); return -E1000_ERR_RESET; } return 0; } /** * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex * @hw: pointer to the HW structure * * Force the speed and duplex settings onto the PHY. This is a * function pointer entry point called by the phy module. **/ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) { s32 ret_val; u16 phy_data; bool link; /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI * forced whenever speed and duplex are forced. */ ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); if (ret_val) return ret_val; phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data); if (ret_val) return ret_val; hw_dbg(hw, "GG82563 PSCR: %X\n", phy_data); ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); if (ret_val) return ret_val; e1000e_phy_force_speed_duplex_setup(hw, &phy_data); /* Reset the phy to commit changes. */ phy_data |= MII_CR_RESET; ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); if (ret_val) return ret_val; udelay(1); if (hw->phy.wait_for_link) { hw_dbg(hw, "Waiting for forced speed/duplex link " "on GG82563 phy.\n"); ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 100000, &link); if (ret_val) return ret_val; if (!link) { /* We didn't get link. * Reset the DSP and cross our fingers. */ ret_val = e1000e_phy_reset_dsp(hw); if (ret_val) return ret_val; } /* Try once more */ ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 100000, &link); if (ret_val) return ret_val; } ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); if (ret_val) return ret_val; /* Resetting the phy means we need to verify the TX_CLK corresponds * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. */ phy_data &= ~GG82563_MSCR_TX_CLK_MASK; if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; else phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; /* In addition, we must re-enable CRS on Tx for both half and full * duplex. */ phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); return ret_val; } /** * e1000_get_cable_length_80003es2lan - Set approximate cable length * @hw: pointer to the HW structure * * Find the approximate cable length as measured by the GG82563 PHY. * This is a function pointer entry point called by the phy module. **/ static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) { struct e1000_phy_info *phy = &hw->phy; s32 ret_val; u16 phy_data; u16 index; ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); if (ret_val) return ret_val; index = phy_data & GG82563_DSPD_CABLE_LENGTH; phy->min_cable_length = e1000_gg82563_cable_length_table[index]; phy->max_cable_length = e1000_gg82563_cable_length_table[index+5]; phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; return 0; } /** * e1000_get_link_up_info_80003es2lan - Report speed and duplex * @hw: pointer to the HW structure * @speed: pointer to speed buffer * @duplex: pointer to duplex buffer * * Retrieve the current speed and duplex configuration. * This is a function pointer entry point called by the api module. **/ static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, u16 *duplex) { s32 ret_val; if (hw->media_type == e1000_media_type_copper) { ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); if (ret_val) return ret_val; if (*speed == SPEED_1000) ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); else ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, *duplex); } else { ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw, speed, duplex); } return ret_val; } /** * e1000_reset_hw_80003es2lan - Reset the ESB2 controller * @hw: pointer to the HW structure * * Perform a global reset to the ESB2 controller. * This is a function pointer entry point called by the api module. **/ static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) { u32 ctrl; u32 icr; s32 ret_val; /* Prevent the PCI-E bus from sticking if there is no TLP connection * on the last TLP read/write transaction when MAC is reset. */ ret_val = e1000e_disable_pcie_master(hw); if (ret_val) hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); hw_dbg(hw, "Masking off all interrupts\n"); ew32(IMC, 0xffffffff); ew32(RCTL, 0); ew32(TCTL, E1000_TCTL_PSP); e1e_flush(); msleep(10); ctrl = er32(CTRL); hw_dbg(hw, "Issuing a global reset to MAC\n"); ew32(CTRL, ctrl | E1000_CTRL_RST); ret_val = e1000e_get_auto_rd_done(hw); if (ret_val) /* We don't want to continue accessing MAC registers. */ return ret_val; /* Clear any pending interrupt events. */ ew32(IMC, 0xffffffff); icr = er32(ICR); return 0; } /** * e1000_init_hw_80003es2lan - Initialize the ESB2 controller * @hw: pointer to the HW structure * * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. * This is a function pointer entry point called by the api module. **/ static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) { struct e1000_mac_info *mac = &hw->mac; u32 reg_data; s32 ret_val; u16 i; e1000_initialize_hw_bits_80003es2lan(hw); /* Initialize identification LED */ ret_val = e1000e_id_led_init(hw); if (ret_val) { hw_dbg(hw, "Error initializing identification LED\n"); return ret_val; } /* Disabling VLAN filtering */ hw_dbg(hw, "Initializing the IEEE VLAN\n"); e1000e_clear_vfta(hw); /* Setup the receive address. */ e1000e_init_rx_addrs(hw, mac->rar_entry_count); /* Zero out the Multicast HASH table */ hw_dbg(hw, "Zeroing the MTA\n"); for (i = 0; i < mac->mta_reg_count; i++) E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); /* Setup link and flow control */ ret_val = e1000e_setup_link(hw); /* Set the transmit descriptor write-back policy */ reg_data = er32(TXDCTL); reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; ew32(TXDCTL, reg_data); /* ...for both queues. */ reg_data = er32(TXDCTL1); reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; ew32(TXDCTL1, reg_data); /* Enable retransmit on late collisions */ reg_data = er32(TCTL); reg_data |= E1000_TCTL_RTLC; ew32(TCTL, reg_data); /* Configure Gigabit Carry Extend Padding */ reg_data = er32(TCTL_EXT); reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; ew32(TCTL_EXT, reg_data); /* Configure Transmit Inter-Packet Gap */ reg_data = er32(TIPG); reg_data &= ~E1000_TIPG_IPGT_MASK; reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; ew32(TIPG, reg_data); reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); reg_data &= ~0x00100000; E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); /* Clear all of the statistics registers (clear on read). It is * important that we do this after we have tried to establish link * because the symbol error count will increment wildly if there * is no link. */ e1000_clear_hw_cntrs_80003es2lan(hw); return ret_val; } /** * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 * @hw: pointer to the HW structure * * Initializes required hardware-dependent bits needed for normal operation. **/ static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) { u32 reg; /* Transmit Descriptor Control 0 */ reg = er32(TXDCTL); reg |= (1 << 22); ew32(TXDCTL, reg); /* Transmit Descriptor Control 1 */ reg = er32(TXDCTL1); reg |= (1 << 22); ew32(TXDCTL1, reg); /* Transmit Arbitration Control 0 */ reg = er32(TARC0); reg &= ~(0xF << 27); /* 30:27 */ if (hw->media_type != e1000_media_type_copper) reg &= ~(1 << 20); ew32(TARC0, reg); /* Transmit Arbitration Control 1 */ reg = er32(TARC1); if (er32(TCTL) & E1000_TCTL_MULR) reg &= ~(1 << 28); else reg |= (1 << 28); ew32(TARC1, reg); } /** * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link * @hw: pointer to the HW structure * * Setup some GG82563 PHY registers for obtaining link **/ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) { struct e1000_phy_info *phy = &hw->phy; s32 ret_val; u32 ctrl_ext; u16 data; ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data); if (ret_val) return ret_val; data |= GG82563_MSCR_ASSERT_CRS_ON_TX; /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ data |= GG82563_MSCR_TX_CLK_1000MBPS_25; ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data); if (ret_val) return ret_val; /* Options: * MDI/MDI-X = 0 (default) * 0 - Auto for all speeds * 1 - MDI mode * 2 - MDI-X mode * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) */ ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data); if (ret_val) return ret_val; data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; switch (phy->mdix) { case 1: data |= GG82563_PSCR_CROSSOVER_MODE_MDI; break; case 2: data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; break; case 0: default: data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; break; } /* Options: * disable_polarity_correction = 0 (default) * Automatic Correction for Reversed Cable Polarity * 0 - Disabled * 1 - Enabled */ data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; if (phy->disable_polarity_correction) data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data); if (ret_val) return ret_val; /* SW Reset the PHY so all changes take effect */ ret_val = e1000e_commit_phy(hw); if (ret_val) { hw_dbg(hw, "Error Resetting the PHY\n"); return ret_val; } /* Bypass RX and TX FIFO's */ ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); if (ret_val) return ret_val; ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data); if (ret_val) return ret_val; data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data); if (ret_val) return ret_val; ctrl_ext = er32(CTRL_EXT); ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); ew32(CTRL_EXT, ctrl_ext); ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); if (ret_val) return ret_val; /* Do not init these registers when the HW is in IAMT mode, since the * firmware will have already initialized them. We only initialize * them if the HW is not in IAMT mode. */ if (!e1000e_check_mng_mode(hw)) { /* Enable Electrical Idle on the PHY */ data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data); if (ret_val) return ret_val; ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data); if (ret_val) return ret_val; data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data); if (ret_val) return ret_val; } /* Workaround: Disable padding in Kumeran interface in the MAC * and in the PHY to avoid CRC errors. */ ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data); if (ret_val) return ret_val; data |= GG82563_ICR_DIS_PADDING; ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data); if (ret_val) return ret_val; return 0; } /** * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 * @hw: pointer to the HW structure * * Essentially a wrapper for setting up all things "copper" related. * This is a function pointer entry point called by the mac module. **/ static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) { u32 ctrl; s32 ret_val; u16 reg_data; ctrl = er32(CTRL); ctrl |= E1000_CTRL_SLU; ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); ew32(CTRL, ctrl); /* Set the mac to wait the maximum time between each * iteration and increase the max iterations when * polling the phy; this fixes erroneous timeouts at 10Mbps. */ ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); if (ret_val) return ret_val; ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data); if (ret_val) return ret_val; reg_data |= 0x3F; ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); if (ret_val) return ret_val; ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, &reg_data); if (ret_val) return ret_val; reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, reg_data); if (ret_val) return ret_val; ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); if (ret_val) return ret_val; ret_val = e1000e_setup_copper_link(hw); return 0; } /** * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation * @hw: pointer to the HW structure * @duplex: current duplex setting * * Configure the KMRN interface by applying last minute quirks for * 10/100 operation. **/ static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) { s32 ret_val; u32 tipg; u16 reg_data; reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, reg_data); if (ret_val) return ret_val; /* Configure Transmit Inter-Packet Gap */ tipg = er32(TIPG); tipg &= ~E1000_TIPG_IPGT_MASK; tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; ew32(TIPG, tipg); ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data); if (ret_val) return ret_val; if (duplex == HALF_DUPLEX) reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; else reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); return 0; } /** * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation * @hw: pointer to the HW structure * * Configure the KMRN interface by applying last minute quirks for * gigabit operation. **/ static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) { s32 ret_val; u16 reg_data; u32 tipg; reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, reg_data); if (ret_val) return ret_val; /* Configure Transmit Inter-Packet Gap */ tipg = er32(TIPG); tipg &= ~E1000_TIPG_IPGT_MASK; tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; ew32(TIPG, tipg); ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data); if (ret_val) return ret_val; reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); return ret_val; } /** * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters * @hw: pointer to the HW structure * * Clears the hardware counters by reading the counter registers. **/ static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) { u32 temp; e1000e_clear_hw_cntrs_base(hw); temp = er32(PRC64); temp = er32(PRC127); temp = er32(PRC255); temp = er32(PRC511); temp = er32(PRC1023); temp = er32(PRC1522); temp = er32(PTC64); temp = er32(PTC127); temp = er32(PTC255); temp = er32(PTC511); temp = er32(PTC1023); temp = er32(PTC1522); temp = er32(ALGNERRC); temp = er32(RXERRC); temp = er32(TNCRS); temp = er32(CEXTERR); temp = er32(TSCTC); temp = er32(TSCTFC); temp = er32(MGTPRC); temp = er32(MGTPDC); temp = er32(MGTPTC); temp = er32(IAC); temp = er32(ICRXOC); temp = er32(ICRXPTC); temp = er32(ICRXATC); temp = er32(ICTXPTC); temp = er32(ICTXATC); temp = er32(ICTXQEC); temp = er32(ICTXQMTC); temp = er32(ICRXDMTC); } static struct e1000_mac_operations es2_mac_ops = { .mng_mode_enab = E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT, /* check_for_link dependent on media type */ .cleanup_led = e1000e_cleanup_led_generic, .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan, .get_bus_info = e1000e_get_bus_info_pcie, .get_link_up_info = e1000_get_link_up_info_80003es2lan, .led_on = e1000e_led_on_generic, .led_off = e1000e_led_off_generic, .mc_addr_list_update = e1000e_mc_addr_list_update_generic, .reset_hw = e1000_reset_hw_80003es2lan, .init_hw = e1000_init_hw_80003es2lan, .setup_link = e1000e_setup_link, /* setup_physical_interface dependent on media type */ }; static struct e1000_phy_operations es2_phy_ops = { .acquire_phy = e1000_acquire_phy_80003es2lan, .check_reset_block = e1000e_check_reset_block_generic, .commit_phy = e1000e_phy_sw_reset, .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan, .get_cfg_done = e1000_get_cfg_done_80003es2lan, .get_cable_length = e1000_get_cable_length_80003es2lan, .get_phy_info = e1000e_get_phy_info_m88, .read_phy_reg = e1000_read_phy_reg_gg82563_80003es2lan, .release_phy = e1000_release_phy_80003es2lan, .reset_phy = e1000e_phy_hw_reset_generic, .set_d0_lplu_state = NULL, .set_d3_lplu_state = e1000e_set_d3_lplu_state, .write_phy_reg = e1000_write_phy_reg_gg82563_80003es2lan, }; static struct e1000_nvm_operations es2_nvm_ops = { .acquire_nvm = e1000_acquire_nvm_80003es2lan, .read_nvm = e1000e_read_nvm_eerd, .release_nvm = e1000_release_nvm_80003es2lan, .update_nvm = e1000e_update_nvm_checksum_generic, .valid_led_default = e1000e_valid_led_default, .validate_nvm = e1000e_validate_nvm_checksum_generic, .write_nvm = e1000_write_nvm_80003es2lan, }; struct e1000_info e1000_es2_info = { .mac = e1000_80003es2lan, .flags = FLAG_HAS_HW_VLAN_FILTER | FLAG_HAS_JUMBO_FRAMES | FLAG_HAS_STATS_PTC_PRC | FLAG_HAS_WOL | FLAG_APME_IN_CTRL3 | FLAG_RX_CSUM_ENABLED | FLAG_HAS_CTRLEXT_ON_LOAD | FLAG_HAS_STATS_ICR_ICT | FLAG_RX_NEEDS_RESTART /* errata */ | FLAG_TARC_SET_BIT_ZERO /* errata */ | FLAG_APME_CHECK_PORT_B | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ | FLAG_TIPG_MEDIUM_FOR_80003ESLAN, .pba = 38, .get_invariants = e1000_get_invariants_80003es2lan, .mac_ops = &es2_mac_ops, .phy_ops = &es2_phy_ops, .nvm_ops = &es2_nvm_ops, };