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authorMatthew Wilcox <matthew@wil.cx>2006-08-28 13:53:30 -0400
committerMatthew Wilcox <willy@parisc-linux.org>2006-10-04 08:47:03 -0400
commit136ce40e9f1f24ca1dbf7714c669a7bca56440ea (patch)
treec628ca029dc7f3829ebb52c403fba467b6faa804
parent75a4958154f5d0028d5464f2479b4297d55cf4a3 (diff)
[PARISC] Clean up asm-parisc/serial.h
Russell King pointed out that asm/serial.h is anachronistic and we were misusing BASE_BAUD. So fix BASE_BAUD for PCI 16550 UARTs, move LASI_BASE_BAUD into 8250_gsc, and fix the obsolete comment about reserving serial port slots. Signed-off-by: Matthew Wilcox <matthew@wil.cx> Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
-rw-r--r--drivers/serial/8250_gsc.c4
-rw-r--r--include/asm-parisc/serial.h16
2 files changed, 4 insertions, 16 deletions
diff --git a/drivers/serial/8250_gsc.c b/drivers/serial/8250_gsc.c
index 1ebe6b585d2d..c5d0addfda4f 100644
--- a/drivers/serial/8250_gsc.c
+++ b/drivers/serial/8250_gsc.c
@@ -22,7 +22,6 @@
22#include <asm/hardware.h> 22#include <asm/hardware.h>
23#include <asm/parisc-device.h> 23#include <asm/parisc-device.h>
24#include <asm/io.h> 24#include <asm/io.h>
25#include <asm/serial.h> /* for LASI_BASE_BAUD */
26 25
27#include "8250.h" 26#include "8250.h"
28 27
@@ -54,7 +53,8 @@ serial_init_chip(struct parisc_device *dev)
54 53
55 memset(&port, 0, sizeof(port)); 54 memset(&port, 0, sizeof(port));
56 port.iotype = UPIO_MEM; 55 port.iotype = UPIO_MEM;
57 port.uartclk = LASI_BASE_BAUD * 16; 56 /* 7.272727MHz on Lasi. Assumed the same for Dino, Wax and Timi. */
57 port.uartclk = 7272727;
58 port.mapbase = address; 58 port.mapbase = address;
59 port.membase = ioremap_nocache(address, 16); 59 port.membase = ioremap_nocache(address, 16);
60 port.irq = dev->irq; 60 port.irq = dev->irq;
diff --git a/include/asm-parisc/serial.h b/include/asm-parisc/serial.h
index 82fd820d684f..d7e3cc60dbc3 100644
--- a/include/asm-parisc/serial.h
+++ b/include/asm-parisc/serial.h
@@ -3,20 +3,8 @@
3 */ 3 */
4 4
5/* 5/*
6 * This assumes you have a 7.272727 MHz clock for your UART. 6 * This is used for 16550-compatible UARTs
7 * The documentation implies a 40Mhz clock, and elsewhere a 7Mhz clock
8 * Clarified: 7.2727MHz on LASI. Not yet clarified for DINO
9 */ 7 */
8#define BASE_BAUD ( 1843200 / 16 )
10 9
11#define LASI_BASE_BAUD ( 7272727 / 16 )
12#define BASE_BAUD LASI_BASE_BAUD
13
14/*
15 * We don't use the ISA probing code, so these entries are just to reserve
16 * space. Some example (maximal) configurations:
17 * - 712 w/ additional Lasi & RJ16 ports: 4
18 * - J5k w/ PCI serial cards: 2 + 4 * card ~= 34
19 * A500 w/ PCI serial cards: 5 + 4 * card ~= 17
20 */
21
22#define SERIAL_PORT_DFNS 10#define SERIAL_PORT_DFNS