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authorAshok Raj <ashok.raj@intel.com>2006-01-06 03:12:08 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2006-01-06 11:33:37 -0500
commit1855a2c4ce708b823b8b824f8b12937b45f5462a (patch)
tree2aeed2e32d792652e43ae086d2522210715c9992
parentc898ec16e83331abde39118e22e9e38335bbb950 (diff)
[PATCH] x86: convert bigsmp to use flat physical mode
When we bring up a new CPU via INIT/startup IPI messages, the CPU that's coming up sends a xTPR message to the chipset. Intel chipsets (at least) don't provide any architectural guarantee on what the chipset will do with this message. For example, the E850x chipsets uses this xTPR message to interpret the interrupt operating mode of the platform. When the CPU coming online sends this message, it always indicates that it is in logical flat mode. For the CPU hotplug case, the platform may already be functioning in cluster APIC mode at this time, the chipset can get confused and mishandle I/O device and IPI interrupt routing. The situation eventually gets corrected when the new CPU sends another xTPR update when we switch it to cluster mode, but there's a window during which the chipset may be in an inconsistent state. This patch avoids this problem by using the flat physical interrupt delivery mode instead of cluster mode for bigsmp (>8 cpu) support. Signed-off-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Cc: Andi Kleen <ak@muc.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
-rw-r--r--include/asm-i386/mach-bigsmp/mach_apic.h79
-rw-r--r--include/asm-i386/mach-bigsmp/mach_apicdef.h4
2 files changed, 38 insertions, 45 deletions
diff --git a/include/asm-i386/mach-bigsmp/mach_apic.h b/include/asm-i386/mach-bigsmp/mach_apic.h
index ba936d4daedb..18b19a773440 100644
--- a/include/asm-i386/mach-bigsmp/mach_apic.h
+++ b/include/asm-i386/mach-bigsmp/mach_apic.h
@@ -1,17 +1,10 @@
1#ifndef __ASM_MACH_APIC_H 1#ifndef __ASM_MACH_APIC_H
2#define __ASM_MACH_APIC_H 2#define __ASM_MACH_APIC_H
3#include <asm/smp.h> 3
4 4
5#define SEQUENTIAL_APICID 5extern u8 bios_cpu_apicid[];
6#ifdef SEQUENTIAL_APICID 6
7#define xapic_phys_to_log_apicid(phys_apic) ( (1ul << ((phys_apic) & 0x3)) |\ 7#define xapic_phys_to_log_apicid(cpu) (bios_cpu_apicid[cpu])
8 ((phys_apic<<2) & (~0xf)) )
9#elif CLUSTERED_APICID
10#define xapic_phys_to_log_apicid(phys_apic) ( (1ul << ((phys_apic) & 0x3)) |\
11 ((phys_apic) & (~0xf)) )
12#endif
13
14#define NO_BALANCE_IRQ (1)
15#define esr_disable (1) 8#define esr_disable (1)
16 9
17static inline int apic_id_registered(void) 10static inline int apic_id_registered(void)
@@ -19,7 +12,6 @@ static inline int apic_id_registered(void)
19 return (1); 12 return (1);
20} 13}
21 14
22#define APIC_DFR_VALUE (APIC_DFR_CLUSTER)
23/* Round robin the irqs amoung the online cpus */ 15/* Round robin the irqs amoung the online cpus */
24static inline cpumask_t target_cpus(void) 16static inline cpumask_t target_cpus(void)
25{ 17{
@@ -32,29 +24,34 @@ static inline cpumask_t target_cpus(void)
32 } while (cpu >= NR_CPUS); 24 } while (cpu >= NR_CPUS);
33 return cpumask_of_cpu(cpu); 25 return cpumask_of_cpu(cpu);
34} 26}
35#define TARGET_CPUS (target_cpus())
36 27
37#define INT_DELIVERY_MODE dest_Fixed 28#undef APIC_DEST_LOGICAL
38#define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */ 29#define APIC_DEST_LOGICAL 0
30#define TARGET_CPUS (target_cpus())
31#define APIC_DFR_VALUE (APIC_DFR_FLAT)
32#define INT_DELIVERY_MODE (dest_Fixed)
33#define INT_DEST_MODE (0) /* phys delivery to target proc */
34#define NO_BALANCE_IRQ (0)
35#define WAKE_SECONDARY_VIA_INIT
36
39 37
40static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid) 38static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
41{ 39{
42 return 0; 40 return (0);
43} 41}
44 42
45/* we don't use the phys_cpu_present_map to indicate apicid presence */ 43static inline unsigned long check_apicid_present(int bit)
46static inline unsigned long check_apicid_present(int bit)
47{ 44{
48 return 1; 45 return (1);
49} 46}
50 47
51#define apicid_cluster(apicid) (apicid & 0xF0) 48static inline unsigned long calculate_ldr(int cpu)
52
53static inline unsigned long calculate_ldr(unsigned long old)
54{ 49{
55 unsigned long id; 50 unsigned long val, id;
56 id = xapic_phys_to_log_apicid(hard_smp_processor_id()); 51 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
57 return ((old & ~APIC_LDR_MASK) | SET_APIC_LOGICAL_ID(id)); 52 id = xapic_phys_to_log_apicid(cpu);
53 val |= SET_APIC_LOGICAL_ID(id);
54 return val;
58} 55}
59 56
60/* 57/*
@@ -67,37 +64,35 @@ static inline unsigned long calculate_ldr(unsigned long old)
67static inline void init_apic_ldr(void) 64static inline void init_apic_ldr(void)
68{ 65{
69 unsigned long val; 66 unsigned long val;
67 int cpu = smp_processor_id();
70 68
71 apic_write_around(APIC_DFR, APIC_DFR_VALUE); 69 apic_write_around(APIC_DFR, APIC_DFR_VALUE);
72 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 70 val = calculate_ldr(cpu);
73 val = calculate_ldr(val);
74 apic_write_around(APIC_LDR, val); 71 apic_write_around(APIC_LDR, val);
75} 72}
76 73
77static inline void clustered_apic_check(void) 74static inline void clustered_apic_check(void)
78{ 75{
79 printk("Enabling APIC mode: %s. Using %d I/O APICs\n", 76 printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
80 "Cluster", nr_ioapics); 77 "Physflat", nr_ioapics);
81} 78}
82 79
83static inline int multi_timer_check(int apic, int irq) 80static inline int multi_timer_check(int apic, int irq)
84{ 81{
85 return 0; 82 return (0);
86} 83}
87 84
88static inline int apicid_to_node(int logical_apicid) 85static inline int apicid_to_node(int logical_apicid)
89{ 86{
90 return 0; 87 return (0);
91} 88}
92 89
93extern u8 bios_cpu_apicid[];
94
95static inline int cpu_present_to_apicid(int mps_cpu) 90static inline int cpu_present_to_apicid(int mps_cpu)
96{ 91{
97 if (mps_cpu < NR_CPUS) 92 if (mps_cpu < NR_CPUS)
98 return (int)bios_cpu_apicid[mps_cpu]; 93 return (int) bios_cpu_apicid[mps_cpu];
99 else 94
100 return BAD_APICID; 95 return BAD_APICID;
101} 96}
102 97
103static inline physid_mask_t apicid_to_cpu_present(int phys_apicid) 98static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
@@ -109,10 +104,10 @@ extern u8 cpu_2_logical_apicid[];
109/* Mapping from cpu number to logical apicid */ 104/* Mapping from cpu number to logical apicid */
110static inline int cpu_to_logical_apicid(int cpu) 105static inline int cpu_to_logical_apicid(int cpu)
111{ 106{
112 if (cpu >= NR_CPUS) 107 if (cpu >= NR_CPUS)
113 return BAD_APICID; 108 return BAD_APICID;
114 return (int)cpu_2_logical_apicid[cpu]; 109 return cpu_physical_id(cpu);
115 } 110}
116 111
117static inline int mpc_apic_id(struct mpc_config_processor *m, 112static inline int mpc_apic_id(struct mpc_config_processor *m,
118 struct mpc_config_translation *translation_record) 113 struct mpc_config_translation *translation_record)
@@ -128,11 +123,9 @@ static inline int mpc_apic_id(struct mpc_config_processor *m,
128static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map) 123static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
129{ 124{
130 /* For clustered we don't have a good way to do this yet - hack */ 125 /* For clustered we don't have a good way to do this yet - hack */
131 return physids_promote(0xFUL); 126 return physids_promote(0xFFL);
132} 127}
133 128
134#define WAKE_SECONDARY_VIA_INIT
135
136static inline void setup_portio_remap(void) 129static inline void setup_portio_remap(void)
137{ 130{
138} 131}
diff --git a/include/asm-i386/mach-bigsmp/mach_apicdef.h b/include/asm-i386/mach-bigsmp/mach_apicdef.h
index 23e58b317c79..a58ab5a75c8c 100644
--- a/include/asm-i386/mach-bigsmp/mach_apicdef.h
+++ b/include/asm-i386/mach-bigsmp/mach_apicdef.h
@@ -1,11 +1,11 @@
1#ifndef __ASM_MACH_APICDEF_H 1#ifndef __ASM_MACH_APICDEF_H
2#define __ASM_MACH_APICDEF_H 2#define __ASM_MACH_APICDEF_H
3 3
4#define APIC_ID_MASK (0x0F<<24) 4#define APIC_ID_MASK (0xFF<<24)
5 5
6static inline unsigned get_apic_id(unsigned long x) 6static inline unsigned get_apic_id(unsigned long x)
7{ 7{
8 return (((x)>>24)&0x0F); 8 return (((x)>>24)&0xFF);
9} 9}
10 10
11#define GET_APIC_ID(x) get_apic_id(x) 11#define GET_APIC_ID(x) get_apic_id(x)