diff options
author | David S. Miller <davem@sunset.davemloft.net> | 2006-01-31 20:09:20 -0500 |
---|---|---|
committer | David S. Miller <davem@sunset.davemloft.net> | 2006-01-31 20:12:55 -0500 |
commit | 7fb76aa07facce5cb9c8d26a0de09001a31eed0c (patch) | |
tree | 0f5077e2da5cfe608b5394c1ba973b04879e5ce4 | |
parent | 3fa97c9db4f6f93f41f7a40d08872dbfd8dc907e (diff) |
[SUNGEM]: Unbreak Sun GEM chips.
Revert: 40727198bfb2ce5842a6e8c7f89cf8a40ff7bf14
These PHY changes hang the sungem driver on startup with Sun chips on
sparc64. Hopefully we can redo these changes in a way that doesn't
break non-Apple systems.
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r-- | arch/powerpc/platforms/powermac/feature.c | 6 | ||||
-rw-r--r-- | drivers/net/sungem.c | 55 |
2 files changed, 27 insertions, 34 deletions
diff --git a/arch/powerpc/platforms/powermac/feature.c b/arch/powerpc/platforms/powermac/feature.c index 2296f3d46ca8..558dd0692092 100644 --- a/arch/powerpc/platforms/powermac/feature.c +++ b/arch/powerpc/platforms/powermac/feature.c | |||
@@ -910,18 +910,16 @@ core99_gmac_phy_reset(struct device_node *node, long param, long value) | |||
910 | macio->type != macio_intrepid) | 910 | macio->type != macio_intrepid) |
911 | return -ENODEV; | 911 | return -ENODEV; |
912 | 912 | ||
913 | printk(KERN_DEBUG "Hard reset of PHY chip ...\n"); | ||
914 | |||
915 | LOCK(flags); | 913 | LOCK(flags); |
916 | MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, KEYLARGO_GPIO_OUTPUT_ENABLE); | 914 | MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, KEYLARGO_GPIO_OUTPUT_ENABLE); |
917 | (void)MACIO_IN8(KL_GPIO_ETH_PHY_RESET); | 915 | (void)MACIO_IN8(KL_GPIO_ETH_PHY_RESET); |
918 | UNLOCK(flags); | 916 | UNLOCK(flags); |
919 | msleep(10); | 917 | mdelay(10); |
920 | LOCK(flags); | 918 | LOCK(flags); |
921 | MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, /*KEYLARGO_GPIO_OUTPUT_ENABLE | */ | 919 | MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, /*KEYLARGO_GPIO_OUTPUT_ENABLE | */ |
922 | KEYLARGO_GPIO_OUTOUT_DATA); | 920 | KEYLARGO_GPIO_OUTOUT_DATA); |
923 | UNLOCK(flags); | 921 | UNLOCK(flags); |
924 | msleep(10); | 922 | mdelay(10); |
925 | 923 | ||
926 | return 0; | 924 | return 0; |
927 | } | 925 | } |
diff --git a/drivers/net/sungem.c b/drivers/net/sungem.c index 55f3b856236e..28ce47a02408 100644 --- a/drivers/net/sungem.c +++ b/drivers/net/sungem.c | |||
@@ -1653,40 +1653,36 @@ static void gem_init_rings(struct gem *gp) | |||
1653 | /* Init PHY interface and start link poll state machine */ | 1653 | /* Init PHY interface and start link poll state machine */ |
1654 | static void gem_init_phy(struct gem *gp) | 1654 | static void gem_init_phy(struct gem *gp) |
1655 | { | 1655 | { |
1656 | u32 mif_cfg; | 1656 | u32 mifcfg; |
1657 | 1657 | ||
1658 | /* Revert MIF CFG setting done on stop_phy */ | 1658 | /* Revert MIF CFG setting done on stop_phy */ |
1659 | mif_cfg = readl(gp->regs + MIF_CFG); | 1659 | mifcfg = readl(gp->regs + MIF_CFG); |
1660 | mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1); | 1660 | mifcfg &= ~MIF_CFG_BBMODE; |
1661 | mif_cfg |= MIF_CFG_MDI0; | 1661 | writel(mifcfg, gp->regs + MIF_CFG); |
1662 | writel(mif_cfg, gp->regs + MIF_CFG); | ||
1663 | writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE); | ||
1664 | writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG); | ||
1665 | 1662 | ||
1666 | if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) { | 1663 | if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) { |
1667 | int i; | 1664 | int i; |
1668 | u16 ctrl; | ||
1669 | 1665 | ||
1666 | /* Those delay sucks, the HW seem to love them though, I'll | ||
1667 | * serisouly consider breaking some locks here to be able | ||
1668 | * to schedule instead | ||
1669 | */ | ||
1670 | for (i = 0; i < 3; i++) { | ||
1670 | #ifdef CONFIG_PPC_PMAC | 1671 | #ifdef CONFIG_PPC_PMAC |
1671 | pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0); | 1672 | pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0); |
1673 | msleep(20); | ||
1672 | #endif | 1674 | #endif |
1673 | 1675 | /* Some PHYs used by apple have problem getting back to us, | |
1674 | /* Some PHYs used by apple have problem getting back | 1676 | * we do an additional reset here |
1675 | * to us, we do an additional reset here | 1677 | */ |
1676 | */ | 1678 | phy_write(gp, MII_BMCR, BMCR_RESET); |
1677 | phy_write(gp, MII_BMCR, BMCR_RESET); | 1679 | msleep(20); |
1678 | for (i = 0; i < 50; i++) { | 1680 | if (phy_read(gp, MII_BMCR) != 0xffff) |
1679 | if ((phy_read(gp, MII_BMCR) & BMCR_RESET) == 0) | ||
1680 | break; | 1681 | break; |
1681 | msleep(10); | 1682 | if (i == 2) |
1683 | printk(KERN_WARNING "%s: GMAC PHY not responding !\n", | ||
1684 | gp->dev->name); | ||
1682 | } | 1685 | } |
1683 | if (i == 50) | ||
1684 | printk(KERN_WARNING "%s: GMAC PHY not responding !\n", | ||
1685 | gp->dev->name); | ||
1686 | /* Make sure isolate is off */ | ||
1687 | ctrl = phy_read(gp, MII_BMCR); | ||
1688 | if (ctrl & BMCR_ISOLATE) | ||
1689 | phy_write(gp, MII_BMCR, ctrl & ~BMCR_ISOLATE); | ||
1690 | } | 1686 | } |
1691 | 1687 | ||
1692 | if (gp->pdev->vendor == PCI_VENDOR_ID_SUN && | 1688 | if (gp->pdev->vendor == PCI_VENDOR_ID_SUN && |
@@ -2123,7 +2119,7 @@ static void gem_reinit_chip(struct gem *gp) | |||
2123 | /* Must be invoked with no lock held. */ | 2119 | /* Must be invoked with no lock held. */ |
2124 | static void gem_stop_phy(struct gem *gp, int wol) | 2120 | static void gem_stop_phy(struct gem *gp, int wol) |
2125 | { | 2121 | { |
2126 | u32 mif_cfg; | 2122 | u32 mifcfg; |
2127 | unsigned long flags; | 2123 | unsigned long flags; |
2128 | 2124 | ||
2129 | /* Let the chip settle down a bit, it seems that helps | 2125 | /* Let the chip settle down a bit, it seems that helps |
@@ -2134,9 +2130,9 @@ static void gem_stop_phy(struct gem *gp, int wol) | |||
2134 | /* Make sure we aren't polling PHY status change. We | 2130 | /* Make sure we aren't polling PHY status change. We |
2135 | * don't currently use that feature though | 2131 | * don't currently use that feature though |
2136 | */ | 2132 | */ |
2137 | mif_cfg = readl(gp->regs + MIF_CFG); | 2133 | mifcfg = readl(gp->regs + MIF_CFG); |
2138 | mif_cfg &= ~MIF_CFG_POLL; | 2134 | mifcfg &= ~MIF_CFG_POLL; |
2139 | writel(mif_cfg, gp->regs + MIF_CFG); | 2135 | writel(mifcfg, gp->regs + MIF_CFG); |
2140 | 2136 | ||
2141 | if (wol && gp->has_wol) { | 2137 | if (wol && gp->has_wol) { |
2142 | unsigned char *e = &gp->dev->dev_addr[0]; | 2138 | unsigned char *e = &gp->dev->dev_addr[0]; |
@@ -2186,8 +2182,7 @@ static void gem_stop_phy(struct gem *gp, int wol) | |||
2186 | /* According to Apple, we must set the MDIO pins to this begnign | 2182 | /* According to Apple, we must set the MDIO pins to this begnign |
2187 | * state or we may 1) eat more current, 2) damage some PHYs | 2183 | * state or we may 1) eat more current, 2) damage some PHYs |
2188 | */ | 2184 | */ |
2189 | mif_cfg = 0; | 2185 | writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG); |
2190 | writel(mif_cfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG); | ||
2191 | writel(0, gp->regs + MIF_BBCLK); | 2186 | writel(0, gp->regs + MIF_BBCLK); |
2192 | writel(0, gp->regs + MIF_BBDATA); | 2187 | writel(0, gp->regs + MIF_BBDATA); |
2193 | writel(0, gp->regs + MIF_BBOENAB); | 2188 | writel(0, gp->regs + MIF_BBOENAB); |