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authorDavid S. Miller <davem@davemloft.net>2008-06-18 00:37:14 -0400
committerDavid S. Miller <davem@davemloft.net>2008-06-18 00:37:14 -0400
commit5bbc1722d52ad3df062d5742a7e958276e57ebd7 (patch)
tree8aa544f9a8623fba2fae933819627ceb839eac1f
parent30902dc3cb0ea1cfc7ac2b17bcf478ff98420d74 (diff)
parentae7b6487ec9c2e2a1551b9d291aa0dbbe0addf48 (diff)
Merge branch 'davem-next' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6
Diffstat
-rw-r--r--Documentation/networking/bonding.txt14
-rw-r--r--MAINTAINERS18
-rw-r--r--drivers/net/Kconfig1
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/bonding/bond_main.c66
-rw-r--r--drivers/net/bonding/bond_sysfs.c22
-rw-r--r--drivers/net/bonding/bonding.h4
-rw-r--r--drivers/net/ibm_emac/Kconfig70
-rw-r--r--drivers/net/ibm_emac/Makefile11
-rw-r--r--drivers/net/ibm_emac/ibm_emac.h329
-rw-r--r--drivers/net/ibm_emac/ibm_emac_core.c2263
-rw-r--r--drivers/net/ibm_emac/ibm_emac_core.h222
-rw-r--r--drivers/net/ibm_emac/ibm_emac_debug.c211
-rw-r--r--drivers/net/ibm_emac/ibm_emac_debug.h62
-rw-r--r--drivers/net/ibm_emac/ibm_emac_mal.c570
-rw-r--r--drivers/net/ibm_emac/ibm_emac_mal.h267
-rw-r--r--drivers/net/ibm_emac/ibm_emac_phy.c398
-rw-r--r--drivers/net/ibm_emac/ibm_emac_phy.h80
-rw-r--r--drivers/net/ibm_emac/ibm_emac_rgmii.c200
-rw-r--r--drivers/net/ibm_emac/ibm_emac_rgmii.h64
-rw-r--r--drivers/net/ibm_emac/ibm_emac_tah.c110
-rw-r--r--drivers/net/ibm_emac/ibm_emac_tah.h87
-rw-r--r--drivers/net/ibm_emac/ibm_emac_zmii.c253
-rw-r--r--drivers/net/ibm_emac/ibm_emac_zmii.h82
-rw-r--r--drivers/net/mv643xx_eth.c4557
-rw-r--r--drivers/net/sky2.c66
-rw-r--r--drivers/net/sky2.h1
-rw-r--r--include/linux/mv643xx_eth.h65
-rw-r--r--include/linux/netdevice.h4
-rw-r--r--include/linux/notifier.h1
-rw-r--r--net/core/dev.c6
-rw-r--r--net/core/net-sysfs.c13
32 files changed, 2060 insertions, 8058 deletions
diff --git a/Documentation/networking/bonding.txt b/Documentation/networking/bonding.txt
index 8e6b8d3c7410..7fa7fe71d7a8 100644
--- a/Documentation/networking/bonding.txt
+++ b/Documentation/networking/bonding.txt
@@ -376,7 +376,8 @@ max_bonds
376 Specifies the number of bonding devices to create for this 376 Specifies the number of bonding devices to create for this
377 instance of the bonding driver. E.g., if max_bonds is 3, and 377 instance of the bonding driver. E.g., if max_bonds is 3, and
378 the bonding driver is not already loaded, then bond0, bond1 378 the bonding driver is not already loaded, then bond0, bond1
379 and bond2 will be created. The default value is 1. 379 and bond2 will be created. The default value is 1. Specifying
380 a value of 0 will load bonding, but will not create any devices.
380 381
381miimon 382miimon
382 383
@@ -539,6 +540,17 @@ mode
539 swapped with the new curr_active_slave that was 540 swapped with the new curr_active_slave that was
540 chosen. 541 chosen.
541 542
543num_grat_arp
544
545 Specifies the number of gratuitous ARPs to be issued after a
546 failover event. One gratuitous ARP is issued immediately after
547 the failover, subsequent ARPs are sent at a rate of one per link
548 monitor interval (arp_interval or miimon, whichever is active).
549
550 The valid range is 0 - 255; the default value is 1. This option
551 affects only the active-backup mode. This option was added for
552 bonding version 3.3.0.
553
542primary 554primary
543 555
544 A string (eth0, eth2, etc) specifying which slave is the 556 A string (eth0, eth2, etc) specifying which slave is the
diff --git a/MAINTAINERS b/MAINTAINERS
index cd587eec9fa7..d0ea6ec2552f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2147,6 +2147,8 @@ P: Jesse Brandeburg
2147M: jesse.brandeburg@intel.com 2147M: jesse.brandeburg@intel.com
2148P: Bruce Allan 2148P: Bruce Allan
2149M: bruce.w.allan@intel.com 2149M: bruce.w.allan@intel.com
2150P: PJ Waskiewicz
2151M: peter.p.waskiewicz.jr@intel.com
2150P: John Ronciak 2152P: John Ronciak
2151M: john.ronciak@intel.com 2153M: john.ronciak@intel.com
2152L: e1000-devel@lists.sourceforge.net 2154L: e1000-devel@lists.sourceforge.net
@@ -2690,12 +2692,10 @@ L: libertas-dev@lists.infradead.org
2690S: Maintained 2692S: Maintained
2691 2693
2692MARVELL MV643XX ETHERNET DRIVER 2694MARVELL MV643XX ETHERNET DRIVER
2693P: Dale Farnsworth 2695P: Lennert Buytenhek
2694M: dale@farnsworth.org 2696M: buytenh@marvell.com
2695P: Manish Lachwani
2696M: mlachwani@mvista.com
2697L: netdev@vger.kernel.org 2697L: netdev@vger.kernel.org
2698S: Odd Fixes for 2.4; Maintained for 2.6. 2698S: Supported
2699 2699
2700MATROX FRAMEBUFFER DRIVER 2700MATROX FRAMEBUFFER DRIVER
2701P: Petr Vandrovec 2701P: Petr Vandrovec
@@ -3233,14 +3233,6 @@ L: linux-kernel@vger.kernel.org
3233T: git git.infradead.org/battery-2.6.git 3233T: git git.infradead.org/battery-2.6.git
3234S: Maintained 3234S: Maintained
3235 3235
3236POWERPC 4xx EMAC DRIVER
3237P: Eugene Surovegin
3238M: ebs@ebshome.net
3239W: http://kernel.ebshome.net/emac/
3240L: linuxppc-dev@ozlabs.org
3241L: netdev@vger.kernel.org
3242S: Maintained
3243
3244PNP SUPPORT 3236PNP SUPPORT
3245P: Adam Belay 3237P: Adam Belay
3246M: ambx1@neo.rr.com 3238M: ambx1@neo.rr.com
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 20b5367f7e0b..0e0f6696ccac 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1255,7 +1255,6 @@ config IBMVETH
1255 To compile this driver as a module, choose M here. The module will 1255 To compile this driver as a module, choose M here. The module will
1256 be called ibmveth. 1256 be called ibmveth.
1257 1257
1258source "drivers/net/ibm_emac/Kconfig"
1259source "drivers/net/ibm_newemac/Kconfig" 1258source "drivers/net/ibm_newemac/Kconfig"
1260 1259
1261config NET_PCI 1260config NET_PCI
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index c96fe2036800..c9faa4605905 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -4,7 +4,6 @@
4 4
5obj-$(CONFIG_E1000) += e1000/ 5obj-$(CONFIG_E1000) += e1000/
6obj-$(CONFIG_E1000E) += e1000e/ 6obj-$(CONFIG_E1000E) += e1000e/
7obj-$(CONFIG_IBM_EMAC) += ibm_emac/
8obj-$(CONFIG_IBM_NEW_EMAC) += ibm_newemac/ 7obj-$(CONFIG_IBM_NEW_EMAC) += ibm_newemac/
9obj-$(CONFIG_IGB) += igb/ 8obj-$(CONFIG_IGB) += igb/
10obj-$(CONFIG_IXGBE) += ixgbe/ 9obj-$(CONFIG_IXGBE) += ixgbe/
diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c
index 5b4af3cc2a44..d57b65dc2c72 100644
--- a/drivers/net/bonding/bond_main.c
+++ b/drivers/net/bonding/bond_main.c
@@ -1189,22 +1189,21 @@ void bond_change_active_slave(struct bonding *bond, struct slave *new_active)
1189 1189
1190 if (new_active) { 1190 if (new_active) {
1191 bond_set_slave_active_flags(new_active); 1191 bond_set_slave_active_flags(new_active);
1192 }
1193 1192
1194 if (new_active && bond->params.fail_over_mac) 1193 if (bond->params.fail_over_mac)
1195 bond_do_fail_over_mac(bond, new_active, old_active); 1194 bond_do_fail_over_mac(bond, new_active,
1195 old_active);
1196 1196
1197 bond->send_grat_arp = bond->params.num_grat_arp; 1197 bond->send_grat_arp = bond->params.num_grat_arp;
1198 if (bond->curr_active_slave && 1198 bond_send_gratuitous_arp(bond);
1199 test_bit(__LINK_STATE_LINKWATCH_PENDING, 1199
1200 &bond->curr_active_slave->dev->state)) { 1200 write_unlock_bh(&bond->curr_slave_lock);
1201 dprintk("delaying gratuitous arp on %s\n", 1201 read_unlock(&bond->lock);
1202 bond->curr_active_slave->dev->name); 1202
1203 } else { 1203 netdev_bonding_change(bond->dev);
1204 if (bond->send_grat_arp > 0) { 1204
1205 bond_send_gratuitous_arp(bond); 1205 read_lock(&bond->lock);
1206 bond->send_grat_arp--; 1206 write_lock_bh(&bond->curr_slave_lock);
1207 }
1208 } 1207 }
1209 } 1208 }
1210} 1209}
@@ -2235,17 +2234,6 @@ static int __bond_mii_monitor(struct bonding *bond, int have_locks)
2235 * program could monitor the link itself if needed. 2234 * program could monitor the link itself if needed.
2236 */ 2235 */
2237 2236
2238 if (bond->send_grat_arp) {
2239 if (bond->curr_active_slave && test_bit(__LINK_STATE_LINKWATCH_PENDING,
2240 &bond->curr_active_slave->dev->state))
2241 dprintk("Needs to send gratuitous arp but not yet\n");
2242 else {
2243 dprintk("sending delayed gratuitous arp on on %s\n",
2244 bond->curr_active_slave->dev->name);
2245 bond_send_gratuitous_arp(bond);
2246 bond->send_grat_arp--;
2247 }
2248 }
2249 read_lock(&bond->curr_slave_lock); 2237 read_lock(&bond->curr_slave_lock);
2250 oldcurrent = bond->curr_active_slave; 2238 oldcurrent = bond->curr_active_slave;
2251 read_unlock(&bond->curr_slave_lock); 2239 read_unlock(&bond->curr_slave_lock);
@@ -2486,6 +2474,13 @@ void bond_mii_monitor(struct work_struct *work)
2486 read_unlock(&bond->lock); 2474 read_unlock(&bond->lock);
2487 return; 2475 return;
2488 } 2476 }
2477
2478 if (bond->send_grat_arp) {
2479 read_lock(&bond->curr_slave_lock);
2480 bond_send_gratuitous_arp(bond);
2481 read_unlock(&bond->curr_slave_lock);
2482 }
2483
2489 if (__bond_mii_monitor(bond, 0)) { 2484 if (__bond_mii_monitor(bond, 0)) {
2490 read_unlock(&bond->lock); 2485 read_unlock(&bond->lock);
2491 rtnl_lock(); 2486 rtnl_lock();
@@ -2651,6 +2646,8 @@ static void bond_arp_send_all(struct bonding *bond, struct slave *slave)
2651/* 2646/*
2652 * Kick out a gratuitous ARP for an IP on the bonding master plus one 2647 * Kick out a gratuitous ARP for an IP on the bonding master plus one
2653 * for each VLAN above us. 2648 * for each VLAN above us.
2649 *
2650 * Caller must hold curr_slave_lock for read or better
2654 */ 2651 */
2655static void bond_send_gratuitous_arp(struct bonding *bond) 2652static void bond_send_gratuitous_arp(struct bonding *bond)
2656{ 2653{
@@ -2660,9 +2657,13 @@ static void bond_send_gratuitous_arp(struct bonding *bond)
2660 2657
2661 dprintk("bond_send_grat_arp: bond %s slave %s\n", bond->dev->name, 2658 dprintk("bond_send_grat_arp: bond %s slave %s\n", bond->dev->name,
2662 slave ? slave->dev->name : "NULL"); 2659 slave ? slave->dev->name : "NULL");
2663 if (!slave) 2660
2661 if (!slave || !bond->send_grat_arp ||
2662 test_bit(__LINK_STATE_LINKWATCH_PENDING, &slave->dev->state))
2664 return; 2663 return;
2665 2664
2665 bond->send_grat_arp--;
2666
2666 if (bond->master_ip) { 2667 if (bond->master_ip) {
2667 bond_arp_send(slave->dev, ARPOP_REPLY, bond->master_ip, 2668 bond_arp_send(slave->dev, ARPOP_REPLY, bond->master_ip,
2668 bond->master_ip, 0); 2669 bond->master_ip, 0);
@@ -3166,6 +3167,12 @@ void bond_activebackup_arp_mon(struct work_struct *work)
3166 if (bond->slave_cnt == 0) 3167 if (bond->slave_cnt == 0)
3167 goto re_arm; 3168 goto re_arm;
3168 3169
3170 if (bond->send_grat_arp) {
3171 read_lock(&bond->curr_slave_lock);
3172 bond_send_gratuitous_arp(bond);
3173 read_unlock(&bond->curr_slave_lock);
3174 }
3175
3169 if (bond_ab_arp_inspect(bond, delta_in_ticks)) { 3176 if (bond_ab_arp_inspect(bond, delta_in_ticks)) {
3170 read_unlock(&bond->lock); 3177 read_unlock(&bond->lock);
3171 rtnl_lock(); 3178 rtnl_lock();
@@ -3840,6 +3847,7 @@ static int bond_close(struct net_device *bond_dev)
3840 3847
3841 write_lock_bh(&bond->lock); 3848 write_lock_bh(&bond->lock);
3842 3849
3850 bond->send_grat_arp = 0;
3843 3851
3844 /* signal timers not to re-arm */ 3852 /* signal timers not to re-arm */
3845 bond->kill_timers = 1; 3853 bond->kill_timers = 1;
@@ -4742,11 +4750,11 @@ static int bond_check_params(struct bond_params *params)
4742 } 4750 }
4743 } 4751 }
4744 4752
4745 if (max_bonds < 1 || max_bonds > INT_MAX) { 4753 if (max_bonds < 0 || max_bonds > INT_MAX) {
4746 printk(KERN_WARNING DRV_NAME 4754 printk(KERN_WARNING DRV_NAME
4747 ": Warning: max_bonds (%d) not in range %d-%d, so it " 4755 ": Warning: max_bonds (%d) not in range %d-%d, so it "
4748 "was reset to BOND_DEFAULT_MAX_BONDS (%d)\n", 4756 "was reset to BOND_DEFAULT_MAX_BONDS (%d)\n",
4749 max_bonds, 1, INT_MAX, BOND_DEFAULT_MAX_BONDS); 4757 max_bonds, 0, INT_MAX, BOND_DEFAULT_MAX_BONDS);
4750 max_bonds = BOND_DEFAULT_MAX_BONDS; 4758 max_bonds = BOND_DEFAULT_MAX_BONDS;
4751 } 4759 }
4752 4760
@@ -4945,7 +4953,7 @@ static int bond_check_params(struct bond_params *params)
4945 4953
4946 printk("\n"); 4954 printk("\n");
4947 4955
4948 } else { 4956 } else if (max_bonds) {
4949 /* miimon and arp_interval not set, we need one so things 4957 /* miimon and arp_interval not set, we need one so things
4950 * work as expected, see bonding.txt for details 4958 * work as expected, see bonding.txt for details
4951 */ 4959 */
diff --git a/drivers/net/bonding/bond_sysfs.c b/drivers/net/bonding/bond_sysfs.c
index dd265c69b0df..6caac0ffb2f2 100644
--- a/drivers/net/bonding/bond_sysfs.c
+++ b/drivers/net/bonding/bond_sysfs.c
@@ -53,7 +53,6 @@ extern struct bond_parm_tbl arp_validate_tbl[];
53extern struct bond_parm_tbl fail_over_mac_tbl[]; 53extern struct bond_parm_tbl fail_over_mac_tbl[];
54 54
55static int expected_refcount = -1; 55static int expected_refcount = -1;
56static struct class *netdev_class;
57/*--------------------------- Data Structures -----------------------------*/ 56/*--------------------------- Data Structures -----------------------------*/
58 57
59/* Bonding sysfs lock. Why can't we just use the subsystem lock? 58/* Bonding sysfs lock. Why can't we just use the subsystem lock?
@@ -1447,19 +1446,9 @@ static struct attribute_group bonding_group = {
1447 */ 1446 */
1448int bond_create_sysfs(void) 1447int bond_create_sysfs(void)
1449{ 1448{
1450 int ret = 0; 1449 int ret;
1451 struct bonding *firstbond;
1452
1453 /* get the netdev class pointer */
1454 firstbond = container_of(bond_dev_list.next, struct bonding, bond_list);
1455 if (!firstbond)
1456 return -ENODEV;
1457
1458 netdev_class = firstbond->dev->dev.class;
1459 if (!netdev_class)
1460 return -ENODEV;
1461 1450
1462 ret = class_create_file(netdev_class, &class_attr_bonding_masters); 1451 ret = netdev_class_create_file(&class_attr_bonding_masters);
1463 /* 1452 /*
1464 * Permit multiple loads of the module by ignoring failures to 1453 * Permit multiple loads of the module by ignoring failures to
1465 * create the bonding_masters sysfs file. Bonding devices 1454 * create the bonding_masters sysfs file. Bonding devices
@@ -1478,10 +1467,6 @@ int bond_create_sysfs(void)
1478 printk(KERN_ERR 1467 printk(KERN_ERR
1479 "network device named %s already exists in sysfs", 1468 "network device named %s already exists in sysfs",
1480 class_attr_bonding_masters.attr.name); 1469 class_attr_bonding_masters.attr.name);
1481 else {
1482 netdev_class = NULL;
1483 return 0;
1484 }
1485 } 1470 }
1486 1471
1487 return ret; 1472 return ret;
@@ -1493,8 +1478,7 @@ int bond_create_sysfs(void)
1493 */ 1478 */
1494void bond_destroy_sysfs(void) 1479void bond_destroy_sysfs(void)
1495{ 1480{
1496 if (netdev_class) 1481 netdev_class_remove_file(&class_attr_bonding_masters);
1497 class_remove_file(netdev_class, &class_attr_bonding_masters);
1498} 1482}
1499 1483
1500/* 1484/*
diff --git a/drivers/net/bonding/bonding.h b/drivers/net/bonding/bonding.h
index 89fd9963db7a..fb730ec0396f 100644
--- a/drivers/net/bonding/bonding.h
+++ b/drivers/net/bonding/bonding.h
@@ -22,8 +22,8 @@
22#include "bond_3ad.h" 22#include "bond_3ad.h"
23#include "bond_alb.h" 23#include "bond_alb.h"
24 24
25#define DRV_VERSION "3.2.5" 25#define DRV_VERSION "3.3.0"
26#define DRV_RELDATE "March 21, 2008" 26#define DRV_RELDATE "June 10, 2008"
27#define DRV_NAME "bonding" 27#define DRV_NAME "bonding"
28#define DRV_DESCRIPTION "Ethernet Channel Bonding Driver" 28#define DRV_DESCRIPTION "Ethernet Channel Bonding Driver"
29 29
diff --git a/drivers/net/ibm_emac/Kconfig b/drivers/net/ibm_emac/Kconfig
deleted file mode 100644
index f61c48047dc0..000000000000
--- a/drivers/net/ibm_emac/Kconfig
+++ /dev/null
@@ -1,70 +0,0 @@
1config IBM_EMAC
2 tristate "PowerPC 4xx on-chip Ethernet support"
3 depends on 4xx && !PPC_MERGE
4 help
5 This driver supports the PowerPC 4xx EMAC family of on-chip
6 Ethernet controllers.
7
8config IBM_EMAC_RXB
9 int "Number of receive buffers"
10 depends on IBM_EMAC
11 default "128"
12
13config IBM_EMAC_TXB
14 int "Number of transmit buffers"
15 depends on IBM_EMAC
16 default "64"
17
18config IBM_EMAC_POLL_WEIGHT
19 int "MAL NAPI polling weight"
20 depends on IBM_EMAC
21 default "32"
22
23config IBM_EMAC_RX_COPY_THRESHOLD
24 int "RX skb copy threshold (bytes)"
25 depends on IBM_EMAC
26 default "256"
27
28config IBM_EMAC_RX_SKB_HEADROOM
29 int "Additional RX skb headroom (bytes)"
30 depends on IBM_EMAC
31 default "0"
32 help
33 Additional receive skb headroom. Note, that driver
34 will always reserve at least 2 bytes to make IP header
35 aligned, so usually there is no need to add any additional
36 headroom.
37
38 If unsure, set to 0.
39
40config IBM_EMAC_PHY_RX_CLK_FIX
41 bool "PHY Rx clock workaround"
42 depends on IBM_EMAC && (405EP || 440GX || 440EP || 440GR)
43 help
44 Enable this if EMAC attached to a PHY which doesn't generate
45 RX clock if there is no link, if this is the case, you will
46 see "TX disable timeout" or "RX disable timeout" in the system
47 log.
48
49 If unsure, say N.
50
51config IBM_EMAC_DEBUG
52 bool "Debugging"
53 depends on IBM_EMAC
54 default n
55
56config IBM_EMAC_ZMII
57 bool
58 depends on IBM_EMAC && (NP405H || NP405L || 44x)
59 default y
60
61config IBM_EMAC_RGMII
62 bool
63 depends on IBM_EMAC && 440GX
64 default y
65
66config IBM_EMAC_TAH
67 bool
68 depends on IBM_EMAC && 440GX
69 default y
70
diff --git a/drivers/net/ibm_emac/Makefile b/drivers/net/ibm_emac/Makefile
deleted file mode 100644
index f98ddf0e807a..000000000000
--- a/drivers/net/ibm_emac/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
1#
2# Makefile for the PowerPC 4xx on-chip ethernet driver
3#
4
5obj-$(CONFIG_IBM_EMAC) += ibm_emac.o
6
7ibm_emac-objs := ibm_emac_mal.o ibm_emac_core.o ibm_emac_phy.o
8ibm_emac-$(CONFIG_IBM_EMAC_ZMII) += ibm_emac_zmii.o
9ibm_emac-$(CONFIG_IBM_EMAC_RGMII) += ibm_emac_rgmii.o
10ibm_emac-$(CONFIG_IBM_EMAC_TAH) += ibm_emac_tah.o
11ibm_emac-$(CONFIG_IBM_EMAC_DEBUG) += ibm_emac_debug.o
diff --git a/drivers/net/ibm_emac/ibm_emac.h b/drivers/net/ibm_emac/ibm_emac.h
deleted file mode 100644
index 97ed22bb4320..000000000000
--- a/drivers/net/ibm_emac/ibm_emac.h
+++ /dev/null
@@ -1,329 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac.h
3 *
4 * Register definitions for PowerPC 4xx on-chip ethernet contoller
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Matt Porter <mporter@kernel.crashing.org>
11 * Armin Kuster <akuster@mvista.com>
12 * Copyright 2002-2004 MontaVista Software Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 *
19 */
20#ifndef __IBM_EMAC_H_
21#define __IBM_EMAC_H_
22
23#include <linux/types.h>
24
25/* This is a simple check to prevent use of this driver on non-tested SoCs */
26#if !defined(CONFIG_405GP) && !defined(CONFIG_405GPR) && !defined(CONFIG_405EP) && \
27 !defined(CONFIG_440GP) && !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && \
28 !defined(CONFIG_440EP) && !defined(CONFIG_NP405H) && !defined(CONFIG_440SPE) && \
29 !defined(CONFIG_440GR)
30#error "Unknown SoC. Please, check chip user manual and make sure EMAC defines are OK"
31#endif
32
33/* EMAC registers Write Access rules */
34struct emac_regs {
35 u32 mr0; /* special */
36 u32 mr1; /* Reset */
37 u32 tmr0; /* special */
38 u32 tmr1; /* special */
39 u32 rmr; /* Reset */
40 u32 isr; /* Always */
41 u32 iser; /* Reset */
42 u32 iahr; /* Reset, R, T */
43 u32 ialr; /* Reset, R, T */
44 u32 vtpid; /* Reset, R, T */
45 u32 vtci; /* Reset, R, T */
46 u32 ptr; /* Reset, T */
47 u32 iaht1; /* Reset, R */
48 u32 iaht2; /* Reset, R */
49 u32 iaht3; /* Reset, R */
50 u32 iaht4; /* Reset, R */
51 u32 gaht1; /* Reset, R */
52 u32 gaht2; /* Reset, R */
53 u32 gaht3; /* Reset, R */
54 u32 gaht4; /* Reset, R */
55 u32 lsah;
56 u32 lsal;
57 u32 ipgvr; /* Reset, T */
58 u32 stacr; /* special */
59 u32 trtr; /* special */
60 u32 rwmr; /* Reset */
61 u32 octx;
62 u32 ocrx;
63 u32 ipcr;
64};
65
66#if !defined(CONFIG_IBM_EMAC4)
67#define EMAC_ETHTOOL_REGS_VER 0
68#define EMAC_ETHTOOL_REGS_SIZE (sizeof(struct emac_regs) - sizeof(u32))
69#else
70#define EMAC_ETHTOOL_REGS_VER 1
71#define EMAC_ETHTOOL_REGS_SIZE sizeof(struct emac_regs)
72#endif
73
74/* EMACx_MR0 */
75#define EMAC_MR0_RXI 0x80000000
76#define EMAC_MR0_TXI 0x40000000
77#define EMAC_MR0_SRST 0x20000000
78#define EMAC_MR0_TXE 0x10000000
79#define EMAC_MR0_RXE 0x08000000
80#define EMAC_MR0_WKE 0x04000000
81
82/* EMACx_MR1 */
83#define EMAC_MR1_FDE 0x80000000
84#define EMAC_MR1_ILE 0x40000000
85#define EMAC_MR1_VLE 0x20000000
86#define EMAC_MR1_EIFC 0x10000000
87#define EMAC_MR1_APP 0x08000000
88#define EMAC_MR1_IST 0x01000000
89
90#define EMAC_MR1_MF_MASK 0x00c00000
91#define EMAC_MR1_MF_10 0x00000000
92#define EMAC_MR1_MF_100 0x00400000
93#if !defined(CONFIG_IBM_EMAC4)
94#define EMAC_MR1_MF_1000 0x00000000
95#define EMAC_MR1_MF_1000GPCS 0x00000000
96#define EMAC_MR1_MF_IPPA(id) 0x00000000
97#else
98#define EMAC_MR1_MF_1000 0x00800000
99#define EMAC_MR1_MF_1000GPCS 0x00c00000
100#define EMAC_MR1_MF_IPPA(id) (((id) & 0x1f) << 6)
101#endif
102
103#define EMAC_TX_FIFO_SIZE 2048
104
105#if !defined(CONFIG_IBM_EMAC4)
106#define EMAC_MR1_RFS_4K 0x00300000
107#define EMAC_MR1_RFS_16K 0x00000000
108#define EMAC_RX_FIFO_SIZE(gige) 4096
109#define EMAC_MR1_TFS_2K 0x00080000
110#define EMAC_MR1_TR0_MULT 0x00008000
111#define EMAC_MR1_JPSM 0x00000000
112#define EMAC_MR1_MWSW_001 0x00000000
113#define EMAC_MR1_BASE(opb) (EMAC_MR1_TFS_2K | EMAC_MR1_TR0_MULT)
114#else
115#define EMAC_MR1_RFS_4K 0x00180000
116#define EMAC_MR1_RFS_16K 0x00280000
117#define EMAC_RX_FIFO_SIZE(gige) ((gige) ? 16384 : 4096)
118#define EMAC_MR1_TFS_2K 0x00020000
119#define EMAC_MR1_TR 0x00008000
120#define EMAC_MR1_MWSW_001 0x00001000
121#define EMAC_MR1_JPSM 0x00000800
122#define EMAC_MR1_OBCI_MASK 0x00000038
123#define EMAC_MR1_OBCI_50 0x00000000
124#define EMAC_MR1_OBCI_66 0x00000008
125#define EMAC_MR1_OBCI_83 0x00000010
126#define EMAC_MR1_OBCI_100 0x00000018
127#define EMAC_MR1_OBCI_100P 0x00000020
128#define EMAC_MR1_OBCI(freq) ((freq) <= 50 ? EMAC_MR1_OBCI_50 : \
129 (freq) <= 66 ? EMAC_MR1_OBCI_66 : \
130 (freq) <= 83 ? EMAC_MR1_OBCI_83 : \
131 (freq) <= 100 ? EMAC_MR1_OBCI_100 : EMAC_MR1_OBCI_100P)
132#define EMAC_MR1_BASE(opb) (EMAC_MR1_TFS_2K | EMAC_MR1_TR | \
133 EMAC_MR1_OBCI(opb))
134#endif
135
136/* EMACx_TMR0 */
137#define EMAC_TMR0_GNP 0x80000000
138#if !defined(CONFIG_IBM_EMAC4)
139#define EMAC_TMR0_DEFAULT 0x00000000
140#else
141#define EMAC_TMR0_TFAE_2_32 0x00000001
142#define EMAC_TMR0_TFAE_4_64 0x00000002
143#define EMAC_TMR0_TFAE_8_128 0x00000003
144#define EMAC_TMR0_TFAE_16_256 0x00000004
145#define EMAC_TMR0_TFAE_32_512 0x00000005
146#define EMAC_TMR0_TFAE_64_1024 0x00000006
147#define EMAC_TMR0_TFAE_128_2048 0x00000007
148#define EMAC_TMR0_DEFAULT EMAC_TMR0_TFAE_2_32
149#endif
150#define EMAC_TMR0_XMIT (EMAC_TMR0_GNP | EMAC_TMR0_DEFAULT)
151
152/* EMACx_TMR1 */
153
154/* IBM manuals are not very clear here.
155 * This is my interpretation of how things are. --ebs
156 */
157#if defined(CONFIG_40x)
158#define EMAC_FIFO_ENTRY_SIZE 8
159#define EMAC_MAL_BURST_SIZE (16 * 4)
160#else
161#define EMAC_FIFO_ENTRY_SIZE 16
162#define EMAC_MAL_BURST_SIZE (64 * 4)
163#endif
164
165#if !defined(CONFIG_IBM_EMAC4)
166#define EMAC_TMR1(l,h) (((l) << 27) | (((h) & 0xff) << 16))
167#else
168#define EMAC_TMR1(l,h) (((l) << 27) | (((h) & 0x3ff) << 14))
169#endif
170
171/* EMACx_RMR */
172#define EMAC_RMR_SP 0x80000000
173#define EMAC_RMR_SFCS 0x40000000
174#define EMAC_RMR_RRP 0x20000000
175#define EMAC_RMR_RFP 0x10000000
176#define EMAC_RMR_ROP 0x08000000
177#define EMAC_RMR_RPIR 0x04000000
178#define EMAC_RMR_PPP 0x02000000
179#define EMAC_RMR_PME 0x01000000
180#define EMAC_RMR_PMME 0x00800000
181#define EMAC_RMR_IAE 0x00400000
182#define EMAC_RMR_MIAE 0x00200000
183#define EMAC_RMR_BAE 0x00100000
184#define EMAC_RMR_MAE 0x00080000
185#if !defined(CONFIG_IBM_EMAC4)
186#define EMAC_RMR_BASE 0x00000000
187#else
188#define EMAC_RMR_RFAF_2_32 0x00000001
189#define EMAC_RMR_RFAF_4_64 0x00000002
190#define EMAC_RMR_RFAF_8_128 0x00000003
191#define EMAC_RMR_RFAF_16_256 0x00000004
192#define EMAC_RMR_RFAF_32_512 0x00000005
193#define EMAC_RMR_RFAF_64_1024 0x00000006
194#define EMAC_RMR_RFAF_128_2048 0x00000007
195#define EMAC_RMR_BASE EMAC_RMR_RFAF_128_2048
196#endif
197
198/* EMACx_ISR & EMACx_ISER */
199#if !defined(CONFIG_IBM_EMAC4)
200#define EMAC_ISR_TXPE 0x00000000
201#define EMAC_ISR_RXPE 0x00000000
202#define EMAC_ISR_TXUE 0x00000000
203#define EMAC_ISR_RXOE 0x00000000
204#else
205#define EMAC_ISR_TXPE 0x20000000
206#define EMAC_ISR_RXPE 0x10000000
207#define EMAC_ISR_TXUE 0x08000000
208#define EMAC_ISR_RXOE 0x04000000
209#endif
210#define EMAC_ISR_OVR 0x02000000
211#define EMAC_ISR_PP 0x01000000
212#define EMAC_ISR_BP 0x00800000
213#define EMAC_ISR_RP 0x00400000
214#define EMAC_ISR_SE 0x00200000
215#define EMAC_ISR_ALE 0x00100000
216#define EMAC_ISR_BFCS 0x00080000
217#define EMAC_ISR_PTLE 0x00040000
218#define EMAC_ISR_ORE 0x00020000
219#define EMAC_ISR_IRE 0x00010000
220#define EMAC_ISR_SQE 0x00000080
221#define EMAC_ISR_TE 0x00000040
222#define EMAC_ISR_MOS 0x00000002
223#define EMAC_ISR_MOF 0x00000001
224
225/* EMACx_STACR */
226#define EMAC_STACR_PHYD_MASK 0xffff
227#define EMAC_STACR_PHYD_SHIFT 16
228#define EMAC_STACR_OC 0x00008000
229#define EMAC_STACR_PHYE 0x00004000
230#define EMAC_STACR_STAC_MASK 0x00003000
231#define EMAC_STACR_STAC_READ 0x00001000
232#define EMAC_STACR_STAC_WRITE 0x00002000
233#if !defined(CONFIG_IBM_EMAC4)
234#define EMAC_STACR_OPBC_MASK 0x00000C00
235#define EMAC_STACR_OPBC_50 0x00000000
236#define EMAC_STACR_OPBC_66 0x00000400
237#define EMAC_STACR_OPBC_83 0x00000800
238#define EMAC_STACR_OPBC_100 0x00000C00
239#define EMAC_STACR_OPBC(freq) ((freq) <= 50 ? EMAC_STACR_OPBC_50 : \
240 (freq) <= 66 ? EMAC_STACR_OPBC_66 : \
241 (freq) <= 83 ? EMAC_STACR_OPBC_83 : EMAC_STACR_OPBC_100)
242#define EMAC_STACR_BASE(opb) EMAC_STACR_OPBC(opb)
243#else
244#define EMAC_STACR_BASE(opb) 0x00000000
245#endif
246#define EMAC_STACR_PCDA_MASK 0x1f
247#define EMAC_STACR_PCDA_SHIFT 5
248#define EMAC_STACR_PRA_MASK 0x1f
249
250/*
251 * For the 440SPe, AMCC inexplicably changed the polarity of
252 * the "operation complete" bit in the MII control register.
253 */
254#if defined(CONFIG_440SPE)
255static inline int emac_phy_done(u32 stacr)
256{
257 return !(stacr & EMAC_STACR_OC);
258};
259#define EMAC_STACR_START EMAC_STACR_OC
260
261#else /* CONFIG_440SPE */
262static inline int emac_phy_done(u32 stacr)
263{
264 return stacr & EMAC_STACR_OC;
265};
266#define EMAC_STACR_START 0
267#endif /* !CONFIG_440SPE */
268
269/* EMACx_TRTR */
270#if !defined(CONFIG_IBM_EMAC4)
271#define EMAC_TRTR_SHIFT 27
272#else
273#define EMAC_TRTR_SHIFT 24
274#endif
275#define EMAC_TRTR(size) ((((size) >> 6) - 1) << EMAC_TRTR_SHIFT)
276
277/* EMACx_RWMR */
278#if !defined(CONFIG_IBM_EMAC4)
279#define EMAC_RWMR(l,h) (((l) << 23) | ( ((h) & 0x1ff) << 7))
280#else
281#define EMAC_RWMR(l,h) (((l) << 22) | ( ((h) & 0x3ff) << 6))
282#endif
283
284/* EMAC specific TX descriptor control fields (write access) */
285#define EMAC_TX_CTRL_GFCS 0x0200
286#define EMAC_TX_CTRL_GP 0x0100
287#define EMAC_TX_CTRL_ISA 0x0080
288#define EMAC_TX_CTRL_RSA 0x0040
289#define EMAC_TX_CTRL_IVT 0x0020
290#define EMAC_TX_CTRL_RVT 0x0010
291#define EMAC_TX_CTRL_TAH_CSUM 0x000e
292
293/* EMAC specific TX descriptor status fields (read access) */
294#define EMAC_TX_ST_BFCS 0x0200
295#define EMAC_TX_ST_LCS 0x0080
296#define EMAC_TX_ST_ED 0x0040
297#define EMAC_TX_ST_EC 0x0020
298#define EMAC_TX_ST_LC 0x0010
299#define EMAC_TX_ST_MC 0x0008
300#define EMAC_TX_ST_SC 0x0004
301#define EMAC_TX_ST_UR 0x0002
302#define EMAC_TX_ST_SQE 0x0001
303#if !defined(CONFIG_IBM_EMAC_TAH)
304#define EMAC_IS_BAD_TX(v) ((v) & (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
305 EMAC_TX_ST_EC | EMAC_TX_ST_LC | \
306 EMAC_TX_ST_MC | EMAC_TX_ST_UR))
307#else
308#define EMAC_IS_BAD_TX(v) ((v) & (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
309 EMAC_TX_ST_EC | EMAC_TX_ST_LC))
310#endif
311
312/* EMAC specific RX descriptor status fields (read access) */
313#define EMAC_RX_ST_OE 0x0200
314#define EMAC_RX_ST_PP 0x0100
315#define EMAC_RX_ST_BP 0x0080
316#define EMAC_RX_ST_RP 0x0040
317#define EMAC_RX_ST_SE 0x0020
318#define EMAC_RX_ST_AE 0x0010
319#define EMAC_RX_ST_BFCS 0x0008
320#define EMAC_RX_ST_PTL 0x0004
321#define EMAC_RX_ST_ORE 0x0002
322#define EMAC_RX_ST_IRE 0x0001
323#define EMAC_RX_TAH_BAD_CSUM 0x0003
324#define EMAC_BAD_RX_MASK (EMAC_RX_ST_OE | EMAC_RX_ST_BP | \
325 EMAC_RX_ST_RP | EMAC_RX_ST_SE | \
326 EMAC_RX_ST_AE | EMAC_RX_ST_BFCS | \
327 EMAC_RX_ST_PTL | EMAC_RX_ST_ORE | \
328 EMAC_RX_ST_IRE )
329#endif /* __IBM_EMAC_H_ */
diff --git a/drivers/net/ibm_emac/ibm_emac_core.c b/drivers/net/ibm_emac/ibm_emac_core.c
deleted file mode 100644
index 73664f226f32..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_core.c
+++ /dev/null
@@ -1,2263 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_core.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Matt Porter <mporter@kernel.crashing.org>
11 * (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
12 * Armin Kuster <akuster@mvista.com>
13 * Johnnie Peters <jpeters@mvista.com>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/string.h>
25#include <linux/errno.h>
26#include <linux/interrupt.h>
27#include <linux/delay.h>
28#include <linux/init.h>
29#include <linux/types.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/crc32.h>
34#include <linux/ethtool.h>
35#include <linux/mii.h>
36#include <linux/bitops.h>
37
38#include <asm/processor.h>
39#include <asm/io.h>
40#include <asm/dma.h>
41#include <asm/uaccess.h>
42#include <asm/ocp.h>
43
44#include "ibm_emac_core.h"
45#include "ibm_emac_debug.h"
46
47/*
48 * Lack of dma_unmap_???? calls is intentional.
49 *
50 * API-correct usage requires additional support state information to be
51 * maintained for every RX and TX buffer descriptor (BD). Unfortunately, due to
52 * EMAC design (e.g. TX buffer passed from network stack can be split into
53 * several BDs, dma_map_single/dma_map_page can be used to map particular BD),
54 * maintaining such information will add additional overhead.
55 * Current DMA API implementation for 4xx processors only ensures cache coherency
56 * and dma_unmap_???? routines are empty and are likely to stay this way.
57 * I decided to omit dma_unmap_??? calls because I don't want to add additional
58 * complexity just for the sake of following some abstract API, when it doesn't
59 * add any real benefit to the driver. I understand that this decision maybe
60 * controversial, but I really tried to make code API-correct and efficient
61 * at the same time and didn't come up with code I liked :(. --ebs
62 */
63
64#define DRV_NAME "emac"
65#define DRV_VERSION "3.54"
66#define DRV_DESC "PPC 4xx OCP EMAC driver"
67
68MODULE_DESCRIPTION(DRV_DESC);
69MODULE_AUTHOR
70 ("Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>");
71MODULE_LICENSE("GPL");
72
73/* minimum number of free TX descriptors required to wake up TX process */
74#define EMAC_TX_WAKEUP_THRESH (NUM_TX_BUFF / 4)
75
76/* If packet size is less than this number, we allocate small skb and copy packet
77 * contents into it instead of just sending original big skb up
78 */
79#define EMAC_RX_COPY_THRESH CONFIG_IBM_EMAC_RX_COPY_THRESHOLD
80
81/* Since multiple EMACs share MDIO lines in various ways, we need
82 * to avoid re-using the same PHY ID in cases where the arch didn't
83 * setup precise phy_map entries
84 */
85static u32 busy_phy_map;
86
87#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX) && \
88 (defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR))
89/* 405EP has "EMAC to PHY Control Register" (CPC0_EPCTL) which can help us
90 * with PHY RX clock problem.
91 * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX, which
92 * also allows controlling each EMAC clock
93 */
94static inline void EMAC_RX_CLK_TX(int idx)
95{
96 unsigned long flags;
97 local_irq_save(flags);
98
99#if defined(CONFIG_405EP)
100 mtdcr(0xf3, mfdcr(0xf3) | (1 << idx));
101#else /* CONFIG_440EP || CONFIG_440GR */
102 SDR_WRITE(DCRN_SDR_MFR, SDR_READ(DCRN_SDR_MFR) | (0x08000000 >> idx));
103#endif
104
105 local_irq_restore(flags);
106}
107
108static inline void EMAC_RX_CLK_DEFAULT(int idx)
109{
110 unsigned long flags;
111 local_irq_save(flags);
112
113#if defined(CONFIG_405EP)
114 mtdcr(0xf3, mfdcr(0xf3) & ~(1 << idx));
115#else /* CONFIG_440EP */
116 SDR_WRITE(DCRN_SDR_MFR, SDR_READ(DCRN_SDR_MFR) & ~(0x08000000 >> idx));
117#endif
118
119 local_irq_restore(flags);
120}
121#else
122#define EMAC_RX_CLK_TX(idx) ((void)0)
123#define EMAC_RX_CLK_DEFAULT(idx) ((void)0)
124#endif
125
126#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX) && defined(CONFIG_440GX)
127/* We can switch Ethernet clock to the internal source through SDR0_MFR[ECS],
128 * unfortunately this is less flexible than 440EP case, because it's a global
129 * setting for all EMACs, therefore we do this clock trick only during probe.
130 */
131#define EMAC_CLK_INTERNAL SDR_WRITE(DCRN_SDR_MFR, \
132 SDR_READ(DCRN_SDR_MFR) | 0x08000000)
133#define EMAC_CLK_EXTERNAL SDR_WRITE(DCRN_SDR_MFR, \
134 SDR_READ(DCRN_SDR_MFR) & ~0x08000000)
135#else
136#define EMAC_CLK_INTERNAL ((void)0)
137#define EMAC_CLK_EXTERNAL ((void)0)
138#endif
139
140/* I don't want to litter system log with timeout errors
141 * when we have brain-damaged PHY.
142 */
143static inline void emac_report_timeout_error(struct ocp_enet_private *dev,
144 const char *error)
145{
146#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX)
147 DBG("%d: %s" NL, dev->def->index, error);
148#else
149 if (net_ratelimit())
150 printk(KERN_ERR "emac%d: %s\n", dev->def->index, error);
151#endif
152}
153
154/* PHY polling intervals */
155#define PHY_POLL_LINK_ON HZ
156#define PHY_POLL_LINK_OFF (HZ / 5)
157
158/* Graceful stop timeouts in us.
159 * We should allow up to 1 frame time (full-duplex, ignoring collisions)
160 */
161#define STOP_TIMEOUT_10 1230
162#define STOP_TIMEOUT_100 124
163#define STOP_TIMEOUT_1000 13
164#define STOP_TIMEOUT_1000_JUMBO 73
165
166/* Please, keep in sync with struct ibm_emac_stats/ibm_emac_error_stats */
167static const char emac_stats_keys[EMAC_ETHTOOL_STATS_COUNT][ETH_GSTRING_LEN] = {
168 "rx_packets", "rx_bytes", "tx_packets", "tx_bytes", "rx_packets_csum",
169 "tx_packets_csum", "tx_undo", "rx_dropped_stack", "rx_dropped_oom",
170 "rx_dropped_error", "rx_dropped_resize", "rx_dropped_mtu",
171 "rx_stopped", "rx_bd_errors", "rx_bd_overrun", "rx_bd_bad_packet",
172 "rx_bd_runt_packet", "rx_bd_short_event", "rx_bd_alignment_error",
173 "rx_bd_bad_fcs", "rx_bd_packet_too_long", "rx_bd_out_of_range",
174 "rx_bd_in_range", "rx_parity", "rx_fifo_overrun", "rx_overrun",
175 "rx_bad_packet", "rx_runt_packet", "rx_short_event",
176 "rx_alignment_error", "rx_bad_fcs", "rx_packet_too_long",
177 "rx_out_of_range", "rx_in_range", "tx_dropped", "tx_bd_errors",
178 "tx_bd_bad_fcs", "tx_bd_carrier_loss", "tx_bd_excessive_deferral",
179 "tx_bd_excessive_collisions", "tx_bd_late_collision",
180 "tx_bd_multple_collisions", "tx_bd_single_collision",
181 "tx_bd_underrun", "tx_bd_sqe", "tx_parity", "tx_underrun", "tx_sqe",
182 "tx_errors"
183};
184
185static irqreturn_t emac_irq(int irq, void *dev_instance);
186static void emac_clean_tx_ring(struct ocp_enet_private *dev);
187
188static inline int emac_phy_supports_gige(int phy_mode)
189{
190 return phy_mode == PHY_MODE_GMII ||
191 phy_mode == PHY_MODE_RGMII ||
192 phy_mode == PHY_MODE_TBI ||
193 phy_mode == PHY_MODE_RTBI;
194}
195
196static inline int emac_phy_gpcs(int phy_mode)
197{
198 return phy_mode == PHY_MODE_TBI ||
199 phy_mode == PHY_MODE_RTBI;
200}
201
202static inline void emac_tx_enable(struct ocp_enet_private *dev)
203{
204 struct emac_regs __iomem *p = dev->emacp;
205 unsigned long flags;
206 u32 r;
207
208 local_irq_save(flags);
209
210 DBG("%d: tx_enable" NL, dev->def->index);
211
212 r = in_be32(&p->mr0);
213 if (!(r & EMAC_MR0_TXE))
214 out_be32(&p->mr0, r | EMAC_MR0_TXE);
215 local_irq_restore(flags);
216}
217
218static void emac_tx_disable(struct ocp_enet_private *dev)
219{
220 struct emac_regs __iomem *p = dev->emacp;
221 unsigned long flags;
222 u32 r;
223
224 local_irq_save(flags);
225
226 DBG("%d: tx_disable" NL, dev->def->index);
227
228 r = in_be32(&p->mr0);
229 if (r & EMAC_MR0_TXE) {
230 int n = dev->stop_timeout;
231 out_be32(&p->mr0, r & ~EMAC_MR0_TXE);
232 while (!(in_be32(&p->mr0) & EMAC_MR0_TXI) && n) {
233 udelay(1);
234 --n;
235 }
236 if (unlikely(!n))
237 emac_report_timeout_error(dev, "TX disable timeout");
238 }
239 local_irq_restore(flags);
240}
241
242static void emac_rx_enable(struct ocp_enet_private *dev)
243{
244 struct emac_regs __iomem *p = dev->emacp;
245 unsigned long flags;
246 u32 r;
247
248 local_irq_save(flags);
249 if (unlikely(dev->commac.rx_stopped))
250 goto out;
251
252 DBG("%d: rx_enable" NL, dev->def->index);
253
254 r = in_be32(&p->mr0);
255 if (!(r & EMAC_MR0_RXE)) {
256 if (unlikely(!(r & EMAC_MR0_RXI))) {
257 /* Wait if previous async disable is still in progress */
258 int n = dev->stop_timeout;
259 while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
260 udelay(1);
261 --n;
262 }
263 if (unlikely(!n))
264 emac_report_timeout_error(dev,
265 "RX disable timeout");
266 }
267 out_be32(&p->mr0, r | EMAC_MR0_RXE);
268 }
269 out:
270 local_irq_restore(flags);
271}
272
273static void emac_rx_disable(struct ocp_enet_private *dev)
274{
275 struct emac_regs __iomem *p = dev->emacp;
276 unsigned long flags;
277 u32 r;
278
279 local_irq_save(flags);
280
281 DBG("%d: rx_disable" NL, dev->def->index);
282
283 r = in_be32(&p->mr0);
284 if (r & EMAC_MR0_RXE) {
285 int n = dev->stop_timeout;
286 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
287 while (!(in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
288 udelay(1);
289 --n;
290 }
291 if (unlikely(!n))
292 emac_report_timeout_error(dev, "RX disable timeout");
293 }
294 local_irq_restore(flags);
295}
296
297static inline void emac_rx_disable_async(struct ocp_enet_private *dev)
298{
299 struct emac_regs __iomem *p = dev->emacp;
300 unsigned long flags;
301 u32 r;
302
303 local_irq_save(flags);
304
305 DBG("%d: rx_disable_async" NL, dev->def->index);
306
307 r = in_be32(&p->mr0);
308 if (r & EMAC_MR0_RXE)
309 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
310 local_irq_restore(flags);
311}
312
313static int emac_reset(struct ocp_enet_private *dev)
314{
315 struct emac_regs __iomem *p = dev->emacp;
316 unsigned long flags;
317 int n = 20;
318
319 DBG("%d: reset" NL, dev->def->index);
320
321 local_irq_save(flags);
322
323 if (!dev->reset_failed) {
324 /* 40x erratum suggests stopping RX channel before reset,
325 * we stop TX as well
326 */
327 emac_rx_disable(dev);
328 emac_tx_disable(dev);
329 }
330
331 out_be32(&p->mr0, EMAC_MR0_SRST);
332 while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n)
333 --n;
334 local_irq_restore(flags);
335
336 if (n) {
337 dev->reset_failed = 0;
338 return 0;
339 } else {
340 emac_report_timeout_error(dev, "reset timeout");
341 dev->reset_failed = 1;
342 return -ETIMEDOUT;
343 }
344}
345
346static void emac_hash_mc(struct ocp_enet_private *dev)
347{
348 struct emac_regs __iomem *p = dev->emacp;
349 u16 gaht[4] = { 0 };
350 struct dev_mc_list *dmi;
351
352 DBG("%d: hash_mc %d" NL, dev->def->index, dev->ndev->mc_count);
353
354 for (dmi = dev->ndev->mc_list; dmi; dmi = dmi->next) {
355 int bit;
356 DECLARE_MAC_BUF(mac);
357 DBG2("%d: mc %s" NL,
358 dev->def->index, print_mac(mac, dmi->dmi_addr));
359
360 bit = 63 - (ether_crc(ETH_ALEN, dmi->dmi_addr) >> 26);
361 gaht[bit >> 4] |= 0x8000 >> (bit & 0x0f);
362 }
363 out_be32(&p->gaht1, gaht[0]);
364 out_be32(&p->gaht2, gaht[1]);
365 out_be32(&p->gaht3, gaht[2]);
366 out_be32(&p->gaht4, gaht[3]);
367}
368
369static inline u32 emac_iff2rmr(struct net_device *ndev)
370{
371 u32 r = EMAC_RMR_SP | EMAC_RMR_SFCS | EMAC_RMR_IAE | EMAC_RMR_BAE |
372 EMAC_RMR_BASE;
373
374 if (ndev->flags & IFF_PROMISC)
375 r |= EMAC_RMR_PME;
376 else if (ndev->flags & IFF_ALLMULTI || ndev->mc_count > 32)
377 r |= EMAC_RMR_PMME;
378 else if (ndev->mc_count > 0)
379 r |= EMAC_RMR_MAE;
380
381 return r;
382}
383
384static inline int emac_opb_mhz(void)
385{
386 return (ocp_sys_info.opb_bus_freq + 500000) / 1000000;
387}
388
389/* BHs disabled */
390static int emac_configure(struct ocp_enet_private *dev)
391{
392 struct emac_regs __iomem *p = dev->emacp;
393 struct net_device *ndev = dev->ndev;
394 int gige;
395 u32 r;
396
397 DBG("%d: configure" NL, dev->def->index);
398
399 if (emac_reset(dev) < 0)
400 return -ETIMEDOUT;
401
402 tah_reset(dev->tah_dev);
403
404 /* Mode register */
405 r = EMAC_MR1_BASE(emac_opb_mhz()) | EMAC_MR1_VLE | EMAC_MR1_IST;
406 if (dev->phy.duplex == DUPLEX_FULL)
407 r |= EMAC_MR1_FDE | EMAC_MR1_MWSW_001;
408 dev->stop_timeout = STOP_TIMEOUT_10;
409 switch (dev->phy.speed) {
410 case SPEED_1000:
411 if (emac_phy_gpcs(dev->phy.mode)) {
412 r |= EMAC_MR1_MF_1000GPCS |
413 EMAC_MR1_MF_IPPA(dev->phy.address);
414
415 /* Put some arbitrary OUI, Manuf & Rev IDs so we can
416 * identify this GPCS PHY later.
417 */
418 out_be32(&p->ipcr, 0xdeadbeef);
419 } else
420 r |= EMAC_MR1_MF_1000;
421 r |= EMAC_MR1_RFS_16K;
422 gige = 1;
423
424 if (dev->ndev->mtu > ETH_DATA_LEN) {
425 r |= EMAC_MR1_JPSM;
426 dev->stop_timeout = STOP_TIMEOUT_1000_JUMBO;
427 } else
428 dev->stop_timeout = STOP_TIMEOUT_1000;
429 break;
430 case SPEED_100:
431 r |= EMAC_MR1_MF_100;
432 dev->stop_timeout = STOP_TIMEOUT_100;
433 /* Fall through */
434 default:
435 r |= EMAC_MR1_RFS_4K;
436 gige = 0;
437 break;
438 }
439
440 if (dev->rgmii_dev)
441 rgmii_set_speed(dev->rgmii_dev, dev->rgmii_input,
442 dev->phy.speed);
443 else
444 zmii_set_speed(dev->zmii_dev, dev->zmii_input, dev->phy.speed);
445
446#if !defined(CONFIG_40x)
447 /* on 40x erratum forces us to NOT use integrated flow control,
448 * let's hope it works on 44x ;)
449 */
450 if (dev->phy.duplex == DUPLEX_FULL) {
451 if (dev->phy.pause)
452 r |= EMAC_MR1_EIFC | EMAC_MR1_APP;
453 else if (dev->phy.asym_pause)
454 r |= EMAC_MR1_APP;
455 }
456#endif
457 out_be32(&p->mr1, r);
458
459 /* Set individual MAC address */
460 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
461 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
462 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
463 ndev->dev_addr[5]);
464
465 /* VLAN Tag Protocol ID */
466 out_be32(&p->vtpid, 0x8100);
467
468 /* Receive mode register */
469 r = emac_iff2rmr(ndev);
470 if (r & EMAC_RMR_MAE)
471 emac_hash_mc(dev);
472 out_be32(&p->rmr, r);
473
474 /* FIFOs thresholds */
475 r = EMAC_TMR1((EMAC_MAL_BURST_SIZE / EMAC_FIFO_ENTRY_SIZE) + 1,
476 EMAC_TX_FIFO_SIZE / 2 / EMAC_FIFO_ENTRY_SIZE);
477 out_be32(&p->tmr1, r);
478 out_be32(&p->trtr, EMAC_TRTR(EMAC_TX_FIFO_SIZE / 2));
479
480 /* PAUSE frame is sent when RX FIFO reaches its high-water mark,
481 there should be still enough space in FIFO to allow the our link
482 partner time to process this frame and also time to send PAUSE
483 frame itself.
484
485 Here is the worst case scenario for the RX FIFO "headroom"
486 (from "The Switch Book") (100Mbps, without preamble, inter-frame gap):
487
488 1) One maximum-length frame on TX 1522 bytes
489 2) One PAUSE frame time 64 bytes
490 3) PAUSE frame decode time allowance 64 bytes
491 4) One maximum-length frame on RX 1522 bytes
492 5) Round-trip propagation delay of the link (100Mb) 15 bytes
493 ----------
494 3187 bytes
495
496 I chose to set high-water mark to RX_FIFO_SIZE / 4 (1024 bytes)
497 low-water mark to RX_FIFO_SIZE / 8 (512 bytes)
498 */
499 r = EMAC_RWMR(EMAC_RX_FIFO_SIZE(gige) / 8 / EMAC_FIFO_ENTRY_SIZE,
500 EMAC_RX_FIFO_SIZE(gige) / 4 / EMAC_FIFO_ENTRY_SIZE);
501 out_be32(&p->rwmr, r);
502
503 /* Set PAUSE timer to the maximum */
504 out_be32(&p->ptr, 0xffff);
505
506 /* IRQ sources */
507 out_be32(&p->iser, EMAC_ISR_TXPE | EMAC_ISR_RXPE | /* EMAC_ISR_TXUE |
508 EMAC_ISR_RXOE | */ EMAC_ISR_OVR | EMAC_ISR_BP | EMAC_ISR_SE |
509 EMAC_ISR_ALE | EMAC_ISR_BFCS | EMAC_ISR_PTLE | EMAC_ISR_ORE |
510 EMAC_ISR_IRE | EMAC_ISR_TE);
511
512 /* We need to take GPCS PHY out of isolate mode after EMAC reset */
513 if (emac_phy_gpcs(dev->phy.mode))
514 mii_reset_phy(&dev->phy);
515
516 return 0;
517}
518
519/* BHs disabled */
520static void emac_reinitialize(struct ocp_enet_private *dev)
521{
522 DBG("%d: reinitialize" NL, dev->def->index);
523
524 if (!emac_configure(dev)) {
525 emac_tx_enable(dev);
526 emac_rx_enable(dev);
527 }
528}
529
530/* BHs disabled */
531static void emac_full_tx_reset(struct net_device *ndev)
532{
533 struct ocp_enet_private *dev = ndev->priv;
534 struct ocp_func_emac_data *emacdata = dev->def->additions;
535
536 DBG("%d: full_tx_reset" NL, dev->def->index);
537
538 emac_tx_disable(dev);
539 mal_disable_tx_channel(dev->mal, emacdata->mal_tx_chan);
540 emac_clean_tx_ring(dev);
541 dev->tx_cnt = dev->tx_slot = dev->ack_slot = 0;
542
543 emac_configure(dev);
544
545 mal_enable_tx_channel(dev->mal, emacdata->mal_tx_chan);
546 emac_tx_enable(dev);
547 emac_rx_enable(dev);
548
549 netif_wake_queue(ndev);
550}
551
552static int __emac_mdio_read(struct ocp_enet_private *dev, u8 id, u8 reg)
553{
554 struct emac_regs __iomem *p = dev->emacp;
555 u32 r;
556 int n;
557
558 DBG2("%d: mdio_read(%02x,%02x)" NL, dev->def->index, id, reg);
559
560 /* Enable proper MDIO port */
561 zmii_enable_mdio(dev->zmii_dev, dev->zmii_input);
562
563 /* Wait for management interface to become idle */
564 n = 10;
565 while (!emac_phy_done(in_be32(&p->stacr))) {
566 udelay(1);
567 if (!--n)
568 goto to;
569 }
570
571 /* Issue read command */
572 out_be32(&p->stacr,
573 EMAC_STACR_BASE(emac_opb_mhz()) | EMAC_STACR_STAC_READ |
574 (reg & EMAC_STACR_PRA_MASK)
575 | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT)
576 | EMAC_STACR_START);
577
578 /* Wait for read to complete */
579 n = 100;
580 while (!emac_phy_done(r = in_be32(&p->stacr))) {
581 udelay(1);
582 if (!--n)
583 goto to;
584 }
585
586 if (unlikely(r & EMAC_STACR_PHYE)) {
587 DBG("%d: mdio_read(%02x, %02x) failed" NL, dev->def->index,
588 id, reg);
589 return -EREMOTEIO;
590 }
591
592 r = ((r >> EMAC_STACR_PHYD_SHIFT) & EMAC_STACR_PHYD_MASK);
593 DBG2("%d: mdio_read -> %04x" NL, dev->def->index, r);
594 return r;
595 to:
596 DBG("%d: MII management interface timeout (read)" NL, dev->def->index);
597 return -ETIMEDOUT;
598}
599
600static void __emac_mdio_write(struct ocp_enet_private *dev, u8 id, u8 reg,
601 u16 val)
602{
603 struct emac_regs __iomem *p = dev->emacp;
604 int n;
605
606 DBG2("%d: mdio_write(%02x,%02x,%04x)" NL, dev->def->index, id, reg,
607 val);
608
609 /* Enable proper MDIO port */
610 zmii_enable_mdio(dev->zmii_dev, dev->zmii_input);
611
612 /* Wait for management interface to be idle */
613 n = 10;
614 while (!emac_phy_done(in_be32(&p->stacr))) {
615 udelay(1);
616 if (!--n)
617 goto to;
618 }
619
620 /* Issue write command */
621 out_be32(&p->stacr,
622 EMAC_STACR_BASE(emac_opb_mhz()) | EMAC_STACR_STAC_WRITE |
623 (reg & EMAC_STACR_PRA_MASK) |
624 ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) |
625 (val << EMAC_STACR_PHYD_SHIFT) | EMAC_STACR_START);
626
627 /* Wait for write to complete */
628 n = 100;
629 while (!emac_phy_done(in_be32(&p->stacr))) {
630 udelay(1);
631 if (!--n)
632 goto to;
633 }
634 return;
635 to:
636 DBG("%d: MII management interface timeout (write)" NL, dev->def->index);
637}
638
639static int emac_mdio_read(struct net_device *ndev, int id, int reg)
640{
641 struct ocp_enet_private *dev = ndev->priv;
642 int res;
643
644 local_bh_disable();
645 res = __emac_mdio_read(dev->mdio_dev ? dev->mdio_dev : dev, (u8) id,
646 (u8) reg);
647 local_bh_enable();
648 return res;
649}
650
651static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val)
652{
653 struct ocp_enet_private *dev = ndev->priv;
654
655 local_bh_disable();
656 __emac_mdio_write(dev->mdio_dev ? dev->mdio_dev : dev, (u8) id,
657 (u8) reg, (u16) val);
658 local_bh_enable();
659}
660
661/* BHs disabled */
662static void emac_set_multicast_list(struct net_device *ndev)
663{
664 struct ocp_enet_private *dev = ndev->priv;
665 struct emac_regs __iomem *p = dev->emacp;
666 u32 rmr = emac_iff2rmr(ndev);
667
668 DBG("%d: multicast %08x" NL, dev->def->index, rmr);
669 BUG_ON(!netif_running(dev->ndev));
670
671 /* I decided to relax register access rules here to avoid
672 * full EMAC reset.
673 *
674 * There is a real problem with EMAC4 core if we use MWSW_001 bit
675 * in MR1 register and do a full EMAC reset.
676 * One TX BD status update is delayed and, after EMAC reset, it
677 * never happens, resulting in TX hung (it'll be recovered by TX
678 * timeout handler eventually, but this is just gross).
679 * So we either have to do full TX reset or try to cheat here :)
680 *
681 * The only required change is to RX mode register, so I *think* all
682 * we need is just to stop RX channel. This seems to work on all
683 * tested SoCs. --ebs
684 */
685 emac_rx_disable(dev);
686 if (rmr & EMAC_RMR_MAE)
687 emac_hash_mc(dev);
688 out_be32(&p->rmr, rmr);
689 emac_rx_enable(dev);
690}
691
692/* BHs disabled */
693static int emac_resize_rx_ring(struct ocp_enet_private *dev, int new_mtu)
694{
695 struct ocp_func_emac_data *emacdata = dev->def->additions;
696 int rx_sync_size = emac_rx_sync_size(new_mtu);
697 int rx_skb_size = emac_rx_skb_size(new_mtu);
698 int i, ret = 0;
699
700 emac_rx_disable(dev);
701 mal_disable_rx_channel(dev->mal, emacdata->mal_rx_chan);
702
703 if (dev->rx_sg_skb) {
704 ++dev->estats.rx_dropped_resize;
705 dev_kfree_skb(dev->rx_sg_skb);
706 dev->rx_sg_skb = NULL;
707 }
708
709 /* Make a first pass over RX ring and mark BDs ready, dropping
710 * non-processed packets on the way. We need this as a separate pass
711 * to simplify error recovery in the case of allocation failure later.
712 */
713 for (i = 0; i < NUM_RX_BUFF; ++i) {
714 if (dev->rx_desc[i].ctrl & MAL_RX_CTRL_FIRST)
715 ++dev->estats.rx_dropped_resize;
716
717 dev->rx_desc[i].data_len = 0;
718 dev->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY |
719 (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
720 }
721
722 /* Reallocate RX ring only if bigger skb buffers are required */
723 if (rx_skb_size <= dev->rx_skb_size)
724 goto skip;
725
726 /* Second pass, allocate new skbs */
727 for (i = 0; i < NUM_RX_BUFF; ++i) {
728 struct sk_buff *skb = alloc_skb(rx_skb_size, GFP_ATOMIC);
729 if (!skb) {
730 ret = -ENOMEM;
731 goto oom;
732 }
733
734 BUG_ON(!dev->rx_skb[i]);
735 dev_kfree_skb(dev->rx_skb[i]);
736
737 skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
738 dev->rx_desc[i].data_ptr =
739 dma_map_single(dev->ldev, skb->data - 2, rx_sync_size,
740 DMA_FROM_DEVICE) + 2;
741 dev->rx_skb[i] = skb;
742 }
743 skip:
744 /* Check if we need to change "Jumbo" bit in MR1 */
745 if ((new_mtu > ETH_DATA_LEN) ^ (dev->ndev->mtu > ETH_DATA_LEN)) {
746 /* This is to prevent starting RX channel in emac_rx_enable() */
747 dev->commac.rx_stopped = 1;
748
749 dev->ndev->mtu = new_mtu;
750 emac_full_tx_reset(dev->ndev);
751 }
752
753 mal_set_rcbs(dev->mal, emacdata->mal_rx_chan, emac_rx_size(new_mtu));
754 oom:
755 /* Restart RX */
756 dev->commac.rx_stopped = dev->rx_slot = 0;
757 mal_enable_rx_channel(dev->mal, emacdata->mal_rx_chan);
758 emac_rx_enable(dev);
759
760 return ret;
761}
762
763/* Process ctx, rtnl_lock semaphore */
764static int emac_change_mtu(struct net_device *ndev, int new_mtu)
765{
766 struct ocp_enet_private *dev = ndev->priv;
767 int ret = 0;
768
769 if (new_mtu < EMAC_MIN_MTU || new_mtu > EMAC_MAX_MTU)
770 return -EINVAL;
771
772 DBG("%d: change_mtu(%d)" NL, dev->def->index, new_mtu);
773
774 local_bh_disable();
775 if (netif_running(ndev)) {
776 /* Check if we really need to reinitalize RX ring */
777 if (emac_rx_skb_size(ndev->mtu) != emac_rx_skb_size(new_mtu))
778 ret = emac_resize_rx_ring(dev, new_mtu);
779 }
780
781 if (!ret) {
782 ndev->mtu = new_mtu;
783 dev->rx_skb_size = emac_rx_skb_size(new_mtu);
784 dev->rx_sync_size = emac_rx_sync_size(new_mtu);
785 }
786 local_bh_enable();
787
788 return ret;
789}
790
791static void emac_clean_tx_ring(struct ocp_enet_private *dev)
792{
793 int i;
794 for (i = 0; i < NUM_TX_BUFF; ++i) {
795 if (dev->tx_skb[i]) {
796 dev_kfree_skb(dev->tx_skb[i]);
797 dev->tx_skb[i] = NULL;
798 if (dev->tx_desc[i].ctrl & MAL_TX_CTRL_READY)
799 ++dev->estats.tx_dropped;
800 }
801 dev->tx_desc[i].ctrl = 0;
802 dev->tx_desc[i].data_ptr = 0;
803 }
804}
805
806static void emac_clean_rx_ring(struct ocp_enet_private *dev)
807{
808 int i;
809 for (i = 0; i < NUM_RX_BUFF; ++i)
810 if (dev->rx_skb[i]) {
811 dev->rx_desc[i].ctrl = 0;
812 dev_kfree_skb(dev->rx_skb[i]);
813 dev->rx_skb[i] = NULL;
814 dev->rx_desc[i].data_ptr = 0;
815 }
816
817 if (dev->rx_sg_skb) {
818 dev_kfree_skb(dev->rx_sg_skb);
819 dev->rx_sg_skb = NULL;
820 }
821}
822
823static inline int emac_alloc_rx_skb(struct ocp_enet_private *dev, int slot,
824 gfp_t flags)
825{
826 struct sk_buff *skb = alloc_skb(dev->rx_skb_size, flags);
827 if (unlikely(!skb))
828 return -ENOMEM;
829
830 dev->rx_skb[slot] = skb;
831 dev->rx_desc[slot].data_len = 0;
832
833 skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
834 dev->rx_desc[slot].data_ptr =
835 dma_map_single(dev->ldev, skb->data - 2, dev->rx_sync_size,
836 DMA_FROM_DEVICE) + 2;
837 barrier();
838 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
839 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
840
841 return 0;
842}
843
844static void emac_print_link_status(struct ocp_enet_private *dev)
845{
846 if (netif_carrier_ok(dev->ndev))
847 printk(KERN_INFO "%s: link is up, %d %s%s\n",
848 dev->ndev->name, dev->phy.speed,
849 dev->phy.duplex == DUPLEX_FULL ? "FDX" : "HDX",
850 dev->phy.pause ? ", pause enabled" :
851 dev->phy.asym_pause ? ", assymetric pause enabled" : "");
852 else
853 printk(KERN_INFO "%s: link is down\n", dev->ndev->name);
854}
855
856/* Process ctx, rtnl_lock semaphore */
857static int emac_open(struct net_device *ndev)
858{
859 struct ocp_enet_private *dev = ndev->priv;
860 struct ocp_func_emac_data *emacdata = dev->def->additions;
861 int err, i;
862
863 DBG("%d: open" NL, dev->def->index);
864
865 /* Setup error IRQ handler */
866 err = request_irq(dev->def->irq, emac_irq, 0, "EMAC", dev);
867 if (err) {
868 printk(KERN_ERR "%s: failed to request IRQ %d\n",
869 ndev->name, dev->def->irq);
870 return err;
871 }
872
873 /* Allocate RX ring */
874 for (i = 0; i < NUM_RX_BUFF; ++i)
875 if (emac_alloc_rx_skb(dev, i, GFP_KERNEL)) {
876 printk(KERN_ERR "%s: failed to allocate RX ring\n",
877 ndev->name);
878 goto oom;
879 }
880
881 local_bh_disable();
882 dev->tx_cnt = dev->tx_slot = dev->ack_slot = dev->rx_slot =
883 dev->commac.rx_stopped = 0;
884 dev->rx_sg_skb = NULL;
885
886 if (dev->phy.address >= 0) {
887 int link_poll_interval;
888 if (dev->phy.def->ops->poll_link(&dev->phy)) {
889 dev->phy.def->ops->read_link(&dev->phy);
890 EMAC_RX_CLK_DEFAULT(dev->def->index);
891 netif_carrier_on(dev->ndev);
892 link_poll_interval = PHY_POLL_LINK_ON;
893 } else {
894 EMAC_RX_CLK_TX(dev->def->index);
895 netif_carrier_off(dev->ndev);
896 link_poll_interval = PHY_POLL_LINK_OFF;
897 }
898 mod_timer(&dev->link_timer, jiffies + link_poll_interval);
899 emac_print_link_status(dev);
900 } else
901 netif_carrier_on(dev->ndev);
902
903 emac_configure(dev);
904 mal_poll_add(dev->mal, &dev->commac);
905 mal_enable_tx_channel(dev->mal, emacdata->mal_tx_chan);
906 mal_set_rcbs(dev->mal, emacdata->mal_rx_chan, emac_rx_size(ndev->mtu));
907 mal_enable_rx_channel(dev->mal, emacdata->mal_rx_chan);
908 emac_tx_enable(dev);
909 emac_rx_enable(dev);
910 netif_start_queue(ndev);
911 local_bh_enable();
912
913 return 0;
914 oom:
915 emac_clean_rx_ring(dev);
916 free_irq(dev->def->irq, dev);
917 return -ENOMEM;
918}
919
920/* BHs disabled */
921static int emac_link_differs(struct ocp_enet_private *dev)
922{
923 u32 r = in_be32(&dev->emacp->mr1);
924
925 int duplex = r & EMAC_MR1_FDE ? DUPLEX_FULL : DUPLEX_HALF;
926 int speed, pause, asym_pause;
927
928 if (r & EMAC_MR1_MF_1000)
929 speed = SPEED_1000;
930 else if (r & EMAC_MR1_MF_100)
931 speed = SPEED_100;
932 else
933 speed = SPEED_10;
934
935 switch (r & (EMAC_MR1_EIFC | EMAC_MR1_APP)) {
936 case (EMAC_MR1_EIFC | EMAC_MR1_APP):
937 pause = 1;
938 asym_pause = 0;
939 break;
940 case EMAC_MR1_APP:
941 pause = 0;
942 asym_pause = 1;
943 break;
944 default:
945 pause = asym_pause = 0;
946 }
947 return speed != dev->phy.speed || duplex != dev->phy.duplex ||
948 pause != dev->phy.pause || asym_pause != dev->phy.asym_pause;
949}
950
951/* BHs disabled */
952static void emac_link_timer(unsigned long data)
953{
954 struct ocp_enet_private *dev = (struct ocp_enet_private *)data;
955 int link_poll_interval;
956
957 DBG2("%d: link timer" NL, dev->def->index);
958
959 if (dev->phy.def->ops->poll_link(&dev->phy)) {
960 if (!netif_carrier_ok(dev->ndev)) {
961 EMAC_RX_CLK_DEFAULT(dev->def->index);
962
963 /* Get new link parameters */
964 dev->phy.def->ops->read_link(&dev->phy);
965
966 if (dev->tah_dev || emac_link_differs(dev))
967 emac_full_tx_reset(dev->ndev);
968
969 netif_carrier_on(dev->ndev);
970 emac_print_link_status(dev);
971 }
972 link_poll_interval = PHY_POLL_LINK_ON;
973 } else {
974 if (netif_carrier_ok(dev->ndev)) {
975 EMAC_RX_CLK_TX(dev->def->index);
976#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX)
977 emac_reinitialize(dev);
978#endif
979 netif_carrier_off(dev->ndev);
980 emac_print_link_status(dev);
981 }
982
983 /* Retry reset if the previous attempt failed.
984 * This is needed mostly for CONFIG_IBM_EMAC_PHY_RX_CLK_FIX
985 * case, but I left it here because it shouldn't trigger for
986 * sane PHYs anyway.
987 */
988 if (unlikely(dev->reset_failed))
989 emac_reinitialize(dev);
990
991 link_poll_interval = PHY_POLL_LINK_OFF;
992 }
993 mod_timer(&dev->link_timer, jiffies + link_poll_interval);
994}
995
996/* BHs disabled */
997static void emac_force_link_update(struct ocp_enet_private *dev)
998{
999 netif_carrier_off(dev->ndev);
1000 if (timer_pending(&dev->link_timer))
1001 mod_timer(&dev->link_timer, jiffies + PHY_POLL_LINK_OFF);
1002}
1003
1004/* Process ctx, rtnl_lock semaphore */
1005static int emac_close(struct net_device *ndev)
1006{
1007 struct ocp_enet_private *dev = ndev->priv;
1008 struct ocp_func_emac_data *emacdata = dev->def->additions;
1009
1010 DBG("%d: close" NL, dev->def->index);
1011
1012 local_bh_disable();
1013
1014 if (dev->phy.address >= 0)
1015 del_timer_sync(&dev->link_timer);
1016
1017 netif_stop_queue(ndev);
1018 emac_rx_disable(dev);
1019 emac_tx_disable(dev);
1020 mal_disable_rx_channel(dev->mal, emacdata->mal_rx_chan);
1021 mal_disable_tx_channel(dev->mal, emacdata->mal_tx_chan);
1022 mal_poll_del(dev->mal, &dev->commac);
1023 local_bh_enable();
1024
1025 emac_clean_tx_ring(dev);
1026 emac_clean_rx_ring(dev);
1027 free_irq(dev->def->irq, dev);
1028
1029 return 0;
1030}
1031
1032static inline u16 emac_tx_csum(struct ocp_enet_private *dev,
1033 struct sk_buff *skb)
1034{
1035#if defined(CONFIG_IBM_EMAC_TAH)
1036 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1037 ++dev->stats.tx_packets_csum;
1038 return EMAC_TX_CTRL_TAH_CSUM;
1039 }
1040#endif
1041 return 0;
1042}
1043
1044static inline int emac_xmit_finish(struct ocp_enet_private *dev, int len)
1045{
1046 struct emac_regs __iomem *p = dev->emacp;
1047 struct net_device *ndev = dev->ndev;
1048
1049 /* Send the packet out */
1050 out_be32(&p->tmr0, EMAC_TMR0_XMIT);
1051
1052 if (unlikely(++dev->tx_cnt == NUM_TX_BUFF)) {
1053 netif_stop_queue(ndev);
1054 DBG2("%d: stopped TX queue" NL, dev->def->index);
1055 }
1056
1057 ndev->trans_start = jiffies;
1058 ++dev->stats.tx_packets;
1059 dev->stats.tx_bytes += len;
1060
1061 return 0;
1062}
1063
1064/* BHs disabled */
1065static int emac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1066{
1067 struct ocp_enet_private *dev = ndev->priv;
1068 unsigned int len = skb->len;
1069 int slot;
1070
1071 u16 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1072 MAL_TX_CTRL_LAST | emac_tx_csum(dev, skb);
1073
1074 slot = dev->tx_slot++;
1075 if (dev->tx_slot == NUM_TX_BUFF) {
1076 dev->tx_slot = 0;
1077 ctrl |= MAL_TX_CTRL_WRAP;
1078 }
1079
1080 DBG2("%d: xmit(%u) %d" NL, dev->def->index, len, slot);
1081
1082 dev->tx_skb[slot] = skb;
1083 dev->tx_desc[slot].data_ptr = dma_map_single(dev->ldev, skb->data, len,
1084 DMA_TO_DEVICE);
1085 dev->tx_desc[slot].data_len = (u16) len;
1086 barrier();
1087 dev->tx_desc[slot].ctrl = ctrl;
1088
1089 return emac_xmit_finish(dev, len);
1090}
1091
1092#if defined(CONFIG_IBM_EMAC_TAH)
1093static inline int emac_xmit_split(struct ocp_enet_private *dev, int slot,
1094 u32 pd, int len, int last, u16 base_ctrl)
1095{
1096 while (1) {
1097 u16 ctrl = base_ctrl;
1098 int chunk = min(len, MAL_MAX_TX_SIZE);
1099 len -= chunk;
1100
1101 slot = (slot + 1) % NUM_TX_BUFF;
1102
1103 if (last && !len)
1104 ctrl |= MAL_TX_CTRL_LAST;
1105 if (slot == NUM_TX_BUFF - 1)
1106 ctrl |= MAL_TX_CTRL_WRAP;
1107
1108 dev->tx_skb[slot] = NULL;
1109 dev->tx_desc[slot].data_ptr = pd;
1110 dev->tx_desc[slot].data_len = (u16) chunk;
1111 dev->tx_desc[slot].ctrl = ctrl;
1112 ++dev->tx_cnt;
1113
1114 if (!len)
1115 break;
1116
1117 pd += chunk;
1118 }
1119 return slot;
1120}
1121
1122/* BHs disabled (SG version for TAH equipped EMACs) */
1123static int emac_start_xmit_sg(struct sk_buff *skb, struct net_device *ndev)
1124{
1125 struct ocp_enet_private *dev = ndev->priv;
1126 int nr_frags = skb_shinfo(skb)->nr_frags;
1127 int len = skb->len, chunk;
1128 int slot, i;
1129 u16 ctrl;
1130 u32 pd;
1131
1132 /* This is common "fast" path */
1133 if (likely(!nr_frags && len <= MAL_MAX_TX_SIZE))
1134 return emac_start_xmit(skb, ndev);
1135
1136 len -= skb->data_len;
1137
1138 /* Note, this is only an *estimation*, we can still run out of empty
1139 * slots because of the additional fragmentation into
1140 * MAL_MAX_TX_SIZE-sized chunks
1141 */
1142 if (unlikely(dev->tx_cnt + nr_frags + mal_tx_chunks(len) > NUM_TX_BUFF))
1143 goto stop_queue;
1144
1145 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1146 emac_tx_csum(dev, skb);
1147 slot = dev->tx_slot;
1148
1149 /* skb data */
1150 dev->tx_skb[slot] = NULL;
1151 chunk = min(len, MAL_MAX_TX_SIZE);
1152 dev->tx_desc[slot].data_ptr = pd =
1153 dma_map_single(dev->ldev, skb->data, len, DMA_TO_DEVICE);
1154 dev->tx_desc[slot].data_len = (u16) chunk;
1155 len -= chunk;
1156 if (unlikely(len))
1157 slot = emac_xmit_split(dev, slot, pd + chunk, len, !nr_frags,
1158 ctrl);
1159 /* skb fragments */
1160 for (i = 0; i < nr_frags; ++i) {
1161 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
1162 len = frag->size;
1163
1164 if (unlikely(dev->tx_cnt + mal_tx_chunks(len) >= NUM_TX_BUFF))
1165 goto undo_frame;
1166
1167 pd = dma_map_page(dev->ldev, frag->page, frag->page_offset, len,
1168 DMA_TO_DEVICE);
1169
1170 slot = emac_xmit_split(dev, slot, pd, len, i == nr_frags - 1,
1171 ctrl);
1172 }
1173
1174 DBG2("%d: xmit_sg(%u) %d - %d" NL, dev->def->index, skb->len,
1175 dev->tx_slot, slot);
1176
1177 /* Attach skb to the last slot so we don't release it too early */
1178 dev->tx_skb[slot] = skb;
1179
1180 /* Send the packet out */
1181 if (dev->tx_slot == NUM_TX_BUFF - 1)
1182 ctrl |= MAL_TX_CTRL_WRAP;
1183 barrier();
1184 dev->tx_desc[dev->tx_slot].ctrl = ctrl;
1185 dev->tx_slot = (slot + 1) % NUM_TX_BUFF;
1186
1187 return emac_xmit_finish(dev, skb->len);
1188
1189 undo_frame:
1190 /* Well, too bad. Our previous estimation was overly optimistic.
1191 * Undo everything.
1192 */
1193 while (slot != dev->tx_slot) {
1194 dev->tx_desc[slot].ctrl = 0;
1195 --dev->tx_cnt;
1196 if (--slot < 0)
1197 slot = NUM_TX_BUFF - 1;
1198 }
1199 ++dev->estats.tx_undo;
1200
1201 stop_queue:
1202 netif_stop_queue(ndev);
1203 DBG2("%d: stopped TX queue" NL, dev->def->index);
1204 return 1;
1205}
1206#else
1207# define emac_start_xmit_sg emac_start_xmit
1208#endif /* !defined(CONFIG_IBM_EMAC_TAH) */
1209
1210/* BHs disabled */
1211static void emac_parse_tx_error(struct ocp_enet_private *dev, u16 ctrl)
1212{
1213 struct ibm_emac_error_stats *st = &dev->estats;
1214 DBG("%d: BD TX error %04x" NL, dev->def->index, ctrl);
1215
1216 ++st->tx_bd_errors;
1217 if (ctrl & EMAC_TX_ST_BFCS)
1218 ++st->tx_bd_bad_fcs;
1219 if (ctrl & EMAC_TX_ST_LCS)
1220 ++st->tx_bd_carrier_loss;
1221 if (ctrl & EMAC_TX_ST_ED)
1222 ++st->tx_bd_excessive_deferral;
1223 if (ctrl & EMAC_TX_ST_EC)
1224 ++st->tx_bd_excessive_collisions;
1225 if (ctrl & EMAC_TX_ST_LC)
1226 ++st->tx_bd_late_collision;
1227 if (ctrl & EMAC_TX_ST_MC)
1228 ++st->tx_bd_multple_collisions;
1229 if (ctrl & EMAC_TX_ST_SC)
1230 ++st->tx_bd_single_collision;
1231 if (ctrl & EMAC_TX_ST_UR)
1232 ++st->tx_bd_underrun;
1233 if (ctrl & EMAC_TX_ST_SQE)
1234 ++st->tx_bd_sqe;
1235}
1236
1237static void emac_poll_tx(void *param)
1238{
1239 struct ocp_enet_private *dev = param;
1240 DBG2("%d: poll_tx, %d %d" NL, dev->def->index, dev->tx_cnt,
1241 dev->ack_slot);
1242
1243 if (dev->tx_cnt) {
1244 u16 ctrl;
1245 int slot = dev->ack_slot, n = 0;
1246 again:
1247 ctrl = dev->tx_desc[slot].ctrl;
1248 if (!(ctrl & MAL_TX_CTRL_READY)) {
1249 struct sk_buff *skb = dev->tx_skb[slot];
1250 ++n;
1251
1252 if (skb) {
1253 dev_kfree_skb(skb);
1254 dev->tx_skb[slot] = NULL;
1255 }
1256 slot = (slot + 1) % NUM_TX_BUFF;
1257
1258 if (unlikely(EMAC_IS_BAD_TX(ctrl)))
1259 emac_parse_tx_error(dev, ctrl);
1260
1261 if (--dev->tx_cnt)
1262 goto again;
1263 }
1264 if (n) {
1265 dev->ack_slot = slot;
1266 if (netif_queue_stopped(dev->ndev) &&
1267 dev->tx_cnt < EMAC_TX_WAKEUP_THRESH)
1268 netif_wake_queue(dev->ndev);
1269
1270 DBG2("%d: tx %d pkts" NL, dev->def->index, n);
1271 }
1272 }
1273}
1274
1275static inline void emac_recycle_rx_skb(struct ocp_enet_private *dev, int slot,
1276 int len)
1277{
1278 struct sk_buff *skb = dev->rx_skb[slot];
1279 DBG2("%d: recycle %d %d" NL, dev->def->index, slot, len);
1280
1281 if (len)
1282 dma_map_single(dev->ldev, skb->data - 2,
1283 EMAC_DMA_ALIGN(len + 2), DMA_FROM_DEVICE);
1284
1285 dev->rx_desc[slot].data_len = 0;
1286 barrier();
1287 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1288 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1289}
1290
1291static void emac_parse_rx_error(struct ocp_enet_private *dev, u16 ctrl)
1292{
1293 struct ibm_emac_error_stats *st = &dev->estats;
1294 DBG("%d: BD RX error %04x" NL, dev->def->index, ctrl);
1295
1296 ++st->rx_bd_errors;
1297 if (ctrl & EMAC_RX_ST_OE)
1298 ++st->rx_bd_overrun;
1299 if (ctrl & EMAC_RX_ST_BP)
1300 ++st->rx_bd_bad_packet;
1301 if (ctrl & EMAC_RX_ST_RP)
1302 ++st->rx_bd_runt_packet;
1303 if (ctrl & EMAC_RX_ST_SE)
1304 ++st->rx_bd_short_event;
1305 if (ctrl & EMAC_RX_ST_AE)
1306 ++st->rx_bd_alignment_error;
1307 if (ctrl & EMAC_RX_ST_BFCS)
1308 ++st->rx_bd_bad_fcs;
1309 if (ctrl & EMAC_RX_ST_PTL)
1310 ++st->rx_bd_packet_too_long;
1311 if (ctrl & EMAC_RX_ST_ORE)
1312 ++st->rx_bd_out_of_range;
1313 if (ctrl & EMAC_RX_ST_IRE)
1314 ++st->rx_bd_in_range;
1315}
1316
1317static inline void emac_rx_csum(struct ocp_enet_private *dev,
1318 struct sk_buff *skb, u16 ctrl)
1319{
1320#if defined(CONFIG_IBM_EMAC_TAH)
1321 if (!ctrl && dev->tah_dev) {
1322 skb->ip_summed = CHECKSUM_UNNECESSARY;
1323 ++dev->stats.rx_packets_csum;
1324 }
1325#endif
1326}
1327
1328static inline int emac_rx_sg_append(struct ocp_enet_private *dev, int slot)
1329{
1330 if (likely(dev->rx_sg_skb != NULL)) {
1331 int len = dev->rx_desc[slot].data_len;
1332 int tot_len = dev->rx_sg_skb->len + len;
1333
1334 if (unlikely(tot_len + 2 > dev->rx_skb_size)) {
1335 ++dev->estats.rx_dropped_mtu;
1336 dev_kfree_skb(dev->rx_sg_skb);
1337 dev->rx_sg_skb = NULL;
1338 } else {
1339 cacheable_memcpy(skb_tail_pointer(dev->rx_sg_skb),
1340 dev->rx_skb[slot]->data, len);
1341 skb_put(dev->rx_sg_skb, len);
1342 emac_recycle_rx_skb(dev, slot, len);
1343 return 0;
1344 }
1345 }
1346 emac_recycle_rx_skb(dev, slot, 0);
1347 return -1;
1348}
1349
1350/* BHs disabled */
1351static int emac_poll_rx(void *param, int budget)
1352{
1353 struct ocp_enet_private *dev = param;
1354 int slot = dev->rx_slot, received = 0;
1355
1356 DBG2("%d: poll_rx(%d)" NL, dev->def->index, budget);
1357
1358 again:
1359 while (budget > 0) {
1360 int len;
1361 struct sk_buff *skb;
1362 u16 ctrl = dev->rx_desc[slot].ctrl;
1363
1364 if (ctrl & MAL_RX_CTRL_EMPTY)
1365 break;
1366
1367 skb = dev->rx_skb[slot];
1368 barrier();
1369 len = dev->rx_desc[slot].data_len;
1370
1371 if (unlikely(!MAL_IS_SINGLE_RX(ctrl)))
1372 goto sg;
1373
1374 ctrl &= EMAC_BAD_RX_MASK;
1375 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1376 emac_parse_rx_error(dev, ctrl);
1377 ++dev->estats.rx_dropped_error;
1378 emac_recycle_rx_skb(dev, slot, 0);
1379 len = 0;
1380 goto next;
1381 }
1382
1383 if (len && len < EMAC_RX_COPY_THRESH) {
1384 struct sk_buff *copy_skb =
1385 alloc_skb(len + EMAC_RX_SKB_HEADROOM + 2, GFP_ATOMIC);
1386 if (unlikely(!copy_skb))
1387 goto oom;
1388
1389 skb_reserve(copy_skb, EMAC_RX_SKB_HEADROOM + 2);
1390 cacheable_memcpy(copy_skb->data - 2, skb->data - 2,
1391 len + 2);
1392 emac_recycle_rx_skb(dev, slot, len);
1393 skb = copy_skb;
1394 } else if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC)))
1395 goto oom;
1396
1397 skb_put(skb, len);
1398 push_packet:
1399 skb->protocol = eth_type_trans(skb, dev->ndev);
1400 emac_rx_csum(dev, skb, ctrl);
1401
1402 if (unlikely(netif_receive_skb(skb) == NET_RX_DROP))
1403 ++dev->estats.rx_dropped_stack;
1404 next:
1405 ++dev->stats.rx_packets;
1406 skip:
1407 dev->stats.rx_bytes += len;
1408 slot = (slot + 1) % NUM_RX_BUFF;
1409 --budget;
1410 ++received;
1411 continue;
1412 sg:
1413 if (ctrl & MAL_RX_CTRL_FIRST) {
1414 BUG_ON(dev->rx_sg_skb);
1415 if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC))) {
1416 DBG("%d: rx OOM %d" NL, dev->def->index, slot);
1417 ++dev->estats.rx_dropped_oom;
1418 emac_recycle_rx_skb(dev, slot, 0);
1419 } else {
1420 dev->rx_sg_skb = skb;
1421 skb_put(skb, len);
1422 }
1423 } else if (!emac_rx_sg_append(dev, slot) &&
1424 (ctrl & MAL_RX_CTRL_LAST)) {
1425
1426 skb = dev->rx_sg_skb;
1427 dev->rx_sg_skb = NULL;
1428
1429 ctrl &= EMAC_BAD_RX_MASK;
1430 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1431 emac_parse_rx_error(dev, ctrl);
1432 ++dev->estats.rx_dropped_error;
1433 dev_kfree_skb(skb);
1434 len = 0;
1435 } else
1436 goto push_packet;
1437 }
1438 goto skip;
1439 oom:
1440 DBG("%d: rx OOM %d" NL, dev->def->index, slot);
1441 /* Drop the packet and recycle skb */
1442 ++dev->estats.rx_dropped_oom;
1443 emac_recycle_rx_skb(dev, slot, 0);
1444 goto next;
1445 }
1446
1447 if (received) {
1448 DBG2("%d: rx %d BDs" NL, dev->def->index, received);
1449 dev->rx_slot = slot;
1450 }
1451
1452 if (unlikely(budget && dev->commac.rx_stopped)) {
1453 struct ocp_func_emac_data *emacdata = dev->def->additions;
1454
1455 barrier();
1456 if (!(dev->rx_desc[slot].ctrl & MAL_RX_CTRL_EMPTY)) {
1457 DBG2("%d: rx restart" NL, dev->def->index);
1458 received = 0;
1459 goto again;
1460 }
1461
1462 if (dev->rx_sg_skb) {
1463 DBG2("%d: dropping partial rx packet" NL,
1464 dev->def->index);
1465 ++dev->estats.rx_dropped_error;
1466 dev_kfree_skb(dev->rx_sg_skb);
1467 dev->rx_sg_skb = NULL;
1468 }
1469
1470 dev->commac.rx_stopped = 0;
1471 mal_enable_rx_channel(dev->mal, emacdata->mal_rx_chan);
1472 emac_rx_enable(dev);
1473 dev->rx_slot = 0;
1474 }
1475 return received;
1476}
1477
1478/* BHs disabled */
1479static int emac_peek_rx(void *param)
1480{
1481 struct ocp_enet_private *dev = param;
1482 return !(dev->rx_desc[dev->rx_slot].ctrl & MAL_RX_CTRL_EMPTY);
1483}
1484
1485/* BHs disabled */
1486static int emac_peek_rx_sg(void *param)
1487{
1488 struct ocp_enet_private *dev = param;
1489 int slot = dev->rx_slot;
1490 while (1) {
1491 u16 ctrl = dev->rx_desc[slot].ctrl;
1492 if (ctrl & MAL_RX_CTRL_EMPTY)
1493 return 0;
1494 else if (ctrl & MAL_RX_CTRL_LAST)
1495 return 1;
1496
1497 slot = (slot + 1) % NUM_RX_BUFF;
1498
1499 /* I'm just being paranoid here :) */
1500 if (unlikely(slot == dev->rx_slot))
1501 return 0;
1502 }
1503}
1504
1505/* Hard IRQ */
1506static void emac_rxde(void *param)
1507{
1508 struct ocp_enet_private *dev = param;
1509 ++dev->estats.rx_stopped;
1510 emac_rx_disable_async(dev);
1511}
1512
1513/* Hard IRQ */
1514static irqreturn_t emac_irq(int irq, void *dev_instance)
1515{
1516 struct ocp_enet_private *dev = dev_instance;
1517 struct emac_regs __iomem *p = dev->emacp;
1518 struct ibm_emac_error_stats *st = &dev->estats;
1519
1520 u32 isr = in_be32(&p->isr);
1521 out_be32(&p->isr, isr);
1522
1523 DBG("%d: isr = %08x" NL, dev->def->index, isr);
1524
1525 if (isr & EMAC_ISR_TXPE)
1526 ++st->tx_parity;
1527 if (isr & EMAC_ISR_RXPE)
1528 ++st->rx_parity;
1529 if (isr & EMAC_ISR_TXUE)
1530 ++st->tx_underrun;
1531 if (isr & EMAC_ISR_RXOE)
1532 ++st->rx_fifo_overrun;
1533 if (isr & EMAC_ISR_OVR)
1534 ++st->rx_overrun;
1535 if (isr & EMAC_ISR_BP)
1536 ++st->rx_bad_packet;
1537 if (isr & EMAC_ISR_RP)
1538 ++st->rx_runt_packet;
1539 if (isr & EMAC_ISR_SE)
1540 ++st->rx_short_event;
1541 if (isr & EMAC_ISR_ALE)
1542 ++st->rx_alignment_error;
1543 if (isr & EMAC_ISR_BFCS)
1544 ++st->rx_bad_fcs;
1545 if (isr & EMAC_ISR_PTLE)
1546 ++st->rx_packet_too_long;
1547 if (isr & EMAC_ISR_ORE)
1548 ++st->rx_out_of_range;
1549 if (isr & EMAC_ISR_IRE)
1550 ++st->rx_in_range;
1551 if (isr & EMAC_ISR_SQE)
1552 ++st->tx_sqe;
1553 if (isr & EMAC_ISR_TE)
1554 ++st->tx_errors;
1555
1556 return IRQ_HANDLED;
1557}
1558
1559static struct net_device_stats *emac_stats(struct net_device *ndev)
1560{
1561 struct ocp_enet_private *dev = ndev->priv;
1562 struct ibm_emac_stats *st = &dev->stats;
1563 struct ibm_emac_error_stats *est = &dev->estats;
1564 struct net_device_stats *nst = &dev->nstats;
1565
1566 DBG2("%d: stats" NL, dev->def->index);
1567
1568 /* Compute "legacy" statistics */
1569 local_irq_disable();
1570 nst->rx_packets = (unsigned long)st->rx_packets;
1571 nst->rx_bytes = (unsigned long)st->rx_bytes;
1572 nst->tx_packets = (unsigned long)st->tx_packets;
1573 nst->tx_bytes = (unsigned long)st->tx_bytes;
1574 nst->rx_dropped = (unsigned long)(est->rx_dropped_oom +
1575 est->rx_dropped_error +
1576 est->rx_dropped_resize +
1577 est->rx_dropped_mtu);
1578 nst->tx_dropped = (unsigned long)est->tx_dropped;
1579
1580 nst->rx_errors = (unsigned long)est->rx_bd_errors;
1581 nst->rx_fifo_errors = (unsigned long)(est->rx_bd_overrun +
1582 est->rx_fifo_overrun +
1583 est->rx_overrun);
1584 nst->rx_frame_errors = (unsigned long)(est->rx_bd_alignment_error +
1585 est->rx_alignment_error);
1586 nst->rx_crc_errors = (unsigned long)(est->rx_bd_bad_fcs +
1587 est->rx_bad_fcs);
1588 nst->rx_length_errors = (unsigned long)(est->rx_bd_runt_packet +
1589 est->rx_bd_short_event +
1590 est->rx_bd_packet_too_long +
1591 est->rx_bd_out_of_range +
1592 est->rx_bd_in_range +
1593 est->rx_runt_packet +
1594 est->rx_short_event +
1595 est->rx_packet_too_long +
1596 est->rx_out_of_range +
1597 est->rx_in_range);
1598
1599 nst->tx_errors = (unsigned long)(est->tx_bd_errors + est->tx_errors);
1600 nst->tx_fifo_errors = (unsigned long)(est->tx_bd_underrun +
1601 est->tx_underrun);
1602 nst->tx_carrier_errors = (unsigned long)est->tx_bd_carrier_loss;
1603 nst->collisions = (unsigned long)(est->tx_bd_excessive_deferral +
1604 est->tx_bd_excessive_collisions +
1605 est->tx_bd_late_collision +
1606 est->tx_bd_multple_collisions);
1607 local_irq_enable();
1608 return nst;
1609}
1610
1611static void emac_remove(struct ocp_device *ocpdev)
1612{
1613 struct ocp_enet_private *dev = ocp_get_drvdata(ocpdev);
1614
1615 DBG("%d: remove" NL, dev->def->index);
1616
1617 ocp_set_drvdata(ocpdev, NULL);
1618 unregister_netdev(dev->ndev);
1619
1620 tah_fini(dev->tah_dev);
1621 rgmii_fini(dev->rgmii_dev, dev->rgmii_input);
1622 zmii_fini(dev->zmii_dev, dev->zmii_input);
1623
1624 emac_dbg_register(dev->def->index, NULL);
1625
1626 mal_unregister_commac(dev->mal, &dev->commac);
1627 iounmap(dev->emacp);
1628 kfree(dev->ndev);
1629}
1630
1631static struct mal_commac_ops emac_commac_ops = {
1632 .poll_tx = &emac_poll_tx,
1633 .poll_rx = &emac_poll_rx,
1634 .peek_rx = &emac_peek_rx,
1635 .rxde = &emac_rxde,
1636};
1637
1638static struct mal_commac_ops emac_commac_sg_ops = {
1639 .poll_tx = &emac_poll_tx,
1640 .poll_rx = &emac_poll_rx,
1641 .peek_rx = &emac_peek_rx_sg,
1642 .rxde = &emac_rxde,
1643};
1644
1645/* Ethtool support */
1646static int emac_ethtool_get_settings(struct net_device *ndev,
1647 struct ethtool_cmd *cmd)
1648{
1649 struct ocp_enet_private *dev = ndev->priv;
1650
1651 cmd->supported = dev->phy.features;
1652 cmd->port = PORT_MII;
1653 cmd->phy_address = dev->phy.address;
1654 cmd->transceiver =
1655 dev->phy.address >= 0 ? XCVR_EXTERNAL : XCVR_INTERNAL;
1656
1657 local_bh_disable();
1658 cmd->advertising = dev->phy.advertising;
1659 cmd->autoneg = dev->phy.autoneg;
1660 cmd->speed = dev->phy.speed;
1661 cmd->duplex = dev->phy.duplex;
1662 local_bh_enable();
1663
1664 return 0;
1665}
1666
1667static int emac_ethtool_set_settings(struct net_device *ndev,
1668 struct ethtool_cmd *cmd)
1669{
1670 struct ocp_enet_private *dev = ndev->priv;
1671 u32 f = dev->phy.features;
1672
1673 DBG("%d: set_settings(%d, %d, %d, 0x%08x)" NL, dev->def->index,
1674 cmd->autoneg, cmd->speed, cmd->duplex, cmd->advertising);
1675
1676 /* Basic sanity checks */
1677 if (dev->phy.address < 0)
1678 return -EOPNOTSUPP;
1679 if (cmd->autoneg != AUTONEG_ENABLE && cmd->autoneg != AUTONEG_DISABLE)
1680 return -EINVAL;
1681 if (cmd->autoneg == AUTONEG_ENABLE && cmd->advertising == 0)
1682 return -EINVAL;
1683 if (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL)
1684 return -EINVAL;
1685
1686 if (cmd->autoneg == AUTONEG_DISABLE) {
1687 switch (cmd->speed) {
1688 case SPEED_10:
1689 if (cmd->duplex == DUPLEX_HALF
1690 && !(f & SUPPORTED_10baseT_Half))
1691 return -EINVAL;
1692 if (cmd->duplex == DUPLEX_FULL
1693 && !(f & SUPPORTED_10baseT_Full))
1694 return -EINVAL;
1695 break;
1696 case SPEED_100:
1697 if (cmd->duplex == DUPLEX_HALF
1698 && !(f & SUPPORTED_100baseT_Half))
1699 return -EINVAL;
1700 if (cmd->duplex == DUPLEX_FULL
1701 && !(f & SUPPORTED_100baseT_Full))
1702 return -EINVAL;
1703 break;
1704 case SPEED_1000:
1705 if (cmd->duplex == DUPLEX_HALF
1706 && !(f & SUPPORTED_1000baseT_Half))
1707 return -EINVAL;
1708 if (cmd->duplex == DUPLEX_FULL
1709 && !(f & SUPPORTED_1000baseT_Full))
1710 return -EINVAL;
1711 break;
1712 default:
1713 return -EINVAL;
1714 }
1715
1716 local_bh_disable();
1717 dev->phy.def->ops->setup_forced(&dev->phy, cmd->speed,
1718 cmd->duplex);
1719
1720 } else {
1721 if (!(f & SUPPORTED_Autoneg))
1722 return -EINVAL;
1723
1724 local_bh_disable();
1725 dev->phy.def->ops->setup_aneg(&dev->phy,
1726 (cmd->advertising & f) |
1727 (dev->phy.advertising &
1728 (ADVERTISED_Pause |
1729 ADVERTISED_Asym_Pause)));
1730 }
1731 emac_force_link_update(dev);
1732 local_bh_enable();
1733
1734 return 0;
1735}
1736
1737static void emac_ethtool_get_ringparam(struct net_device *ndev,
1738 struct ethtool_ringparam *rp)
1739{
1740 rp->rx_max_pending = rp->rx_pending = NUM_RX_BUFF;
1741 rp->tx_max_pending = rp->tx_pending = NUM_TX_BUFF;
1742}
1743
1744static void emac_ethtool_get_pauseparam(struct net_device *ndev,
1745 struct ethtool_pauseparam *pp)
1746{
1747 struct ocp_enet_private *dev = ndev->priv;
1748
1749 local_bh_disable();
1750 if ((dev->phy.features & SUPPORTED_Autoneg) &&
1751 (dev->phy.advertising & (ADVERTISED_Pause | ADVERTISED_Asym_Pause)))
1752 pp->autoneg = 1;
1753
1754 if (dev->phy.duplex == DUPLEX_FULL) {
1755 if (dev->phy.pause)
1756 pp->rx_pause = pp->tx_pause = 1;
1757 else if (dev->phy.asym_pause)
1758 pp->tx_pause = 1;
1759 }
1760 local_bh_enable();
1761}
1762
1763static u32 emac_ethtool_get_rx_csum(struct net_device *ndev)
1764{
1765 struct ocp_enet_private *dev = ndev->priv;
1766 return dev->tah_dev != 0;
1767}
1768
1769static int emac_get_regs_len(struct ocp_enet_private *dev)
1770{
1771 return sizeof(struct emac_ethtool_regs_subhdr) + EMAC_ETHTOOL_REGS_SIZE;
1772}
1773
1774static int emac_ethtool_get_regs_len(struct net_device *ndev)
1775{
1776 struct ocp_enet_private *dev = ndev->priv;
1777 return sizeof(struct emac_ethtool_regs_hdr) +
1778 emac_get_regs_len(dev) + mal_get_regs_len(dev->mal) +
1779 zmii_get_regs_len(dev->zmii_dev) +
1780 rgmii_get_regs_len(dev->rgmii_dev) +
1781 tah_get_regs_len(dev->tah_dev);
1782}
1783
1784static void *emac_dump_regs(struct ocp_enet_private *dev, void *buf)
1785{
1786 struct emac_ethtool_regs_subhdr *hdr = buf;
1787
1788 hdr->version = EMAC_ETHTOOL_REGS_VER;
1789 hdr->index = dev->def->index;
1790 memcpy_fromio(hdr + 1, dev->emacp, EMAC_ETHTOOL_REGS_SIZE);
1791 return ((void *)(hdr + 1) + EMAC_ETHTOOL_REGS_SIZE);
1792}
1793
1794static void emac_ethtool_get_regs(struct net_device *ndev,
1795 struct ethtool_regs *regs, void *buf)
1796{
1797 struct ocp_enet_private *dev = ndev->priv;
1798 struct emac_ethtool_regs_hdr *hdr = buf;
1799
1800 hdr->components = 0;
1801 buf = hdr + 1;
1802
1803 local_irq_disable();
1804 buf = mal_dump_regs(dev->mal, buf);
1805 buf = emac_dump_regs(dev, buf);
1806 if (dev->zmii_dev) {
1807 hdr->components |= EMAC_ETHTOOL_REGS_ZMII;
1808 buf = zmii_dump_regs(dev->zmii_dev, buf);
1809 }
1810 if (dev->rgmii_dev) {
1811 hdr->components |= EMAC_ETHTOOL_REGS_RGMII;
1812 buf = rgmii_dump_regs(dev->rgmii_dev, buf);
1813 }
1814 if (dev->tah_dev) {
1815 hdr->components |= EMAC_ETHTOOL_REGS_TAH;
1816 buf = tah_dump_regs(dev->tah_dev, buf);
1817 }
1818 local_irq_enable();
1819}
1820
1821static int emac_ethtool_nway_reset(struct net_device *ndev)
1822{
1823 struct ocp_enet_private *dev = ndev->priv;
1824 int res = 0;
1825
1826 DBG("%d: nway_reset" NL, dev->def->index);
1827
1828 if (dev->phy.address < 0)
1829 return -EOPNOTSUPP;
1830
1831 local_bh_disable();
1832 if (!dev->phy.autoneg) {
1833 res = -EINVAL;
1834 goto out;
1835 }
1836
1837 dev->phy.def->ops->setup_aneg(&dev->phy, dev->phy.advertising);
1838 emac_force_link_update(dev);
1839
1840 out:
1841 local_bh_enable();
1842 return res;
1843}
1844
1845static int emac_get_sset_count(struct net_device *ndev, int sset)
1846{
1847 switch (sset) {
1848 case ETH_SS_STATS:
1849 return EMAC_ETHTOOL_STATS_COUNT;
1850 default:
1851 return -EOPNOTSUPP;
1852 }
1853}
1854
1855static void emac_ethtool_get_strings(struct net_device *ndev, u32 stringset,
1856 u8 * buf)
1857{
1858 if (stringset == ETH_SS_STATS)
1859 memcpy(buf, &emac_stats_keys, sizeof(emac_stats_keys));
1860}
1861
1862static void emac_ethtool_get_ethtool_stats(struct net_device *ndev,
1863 struct ethtool_stats *estats,
1864 u64 * tmp_stats)
1865{
1866 struct ocp_enet_private *dev = ndev->priv;
1867 local_irq_disable();
1868 memcpy(tmp_stats, &dev->stats, sizeof(dev->stats));
1869 tmp_stats += sizeof(dev->stats) / sizeof(u64);
1870 memcpy(tmp_stats, &dev->estats, sizeof(dev->estats));
1871 local_irq_enable();
1872}
1873
1874static void emac_ethtool_get_drvinfo(struct net_device *ndev,
1875 struct ethtool_drvinfo *info)
1876{
1877 struct ocp_enet_private *dev = ndev->priv;
1878
1879 strcpy(info->driver, "ibm_emac");
1880 strcpy(info->version, DRV_VERSION);
1881 info->fw_version[0] = '\0';
1882 sprintf(info->bus_info, "PPC 4xx EMAC %d", dev->def->index);
1883 info->regdump_len = emac_ethtool_get_regs_len(ndev);
1884}
1885
1886static const struct ethtool_ops emac_ethtool_ops = {
1887 .get_settings = emac_ethtool_get_settings,
1888 .set_settings = emac_ethtool_set_settings,
1889 .get_drvinfo = emac_ethtool_get_drvinfo,
1890
1891 .get_regs_len = emac_ethtool_get_regs_len,
1892 .get_regs = emac_ethtool_get_regs,
1893
1894 .nway_reset = emac_ethtool_nway_reset,
1895
1896 .get_ringparam = emac_ethtool_get_ringparam,
1897 .get_pauseparam = emac_ethtool_get_pauseparam,
1898
1899 .get_rx_csum = emac_ethtool_get_rx_csum,
1900
1901 .get_strings = emac_ethtool_get_strings,
1902 .get_sset_count = emac_get_sset_count,
1903 .get_ethtool_stats = emac_ethtool_get_ethtool_stats,
1904
1905 .get_link = ethtool_op_get_link,
1906};
1907
1908static int emac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1909{
1910 struct ocp_enet_private *dev = ndev->priv;
1911 uint16_t *data = (uint16_t *) & rq->ifr_ifru;
1912
1913 DBG("%d: ioctl %08x" NL, dev->def->index, cmd);
1914
1915 if (dev->phy.address < 0)
1916 return -EOPNOTSUPP;
1917
1918 switch (cmd) {
1919 case SIOCGMIIPHY:
1920 case SIOCDEVPRIVATE:
1921 data[0] = dev->phy.address;
1922 /* Fall through */
1923 case SIOCGMIIREG:
1924 case SIOCDEVPRIVATE + 1:
1925 data[3] = emac_mdio_read(ndev, dev->phy.address, data[1]);
1926 return 0;
1927
1928 case SIOCSMIIREG:
1929 case SIOCDEVPRIVATE + 2:
1930 if (!capable(CAP_NET_ADMIN))
1931 return -EPERM;
1932 emac_mdio_write(ndev, dev->phy.address, data[1], data[2]);
1933 return 0;
1934 default:
1935 return -EOPNOTSUPP;
1936 }
1937}
1938
1939static int __init emac_probe(struct ocp_device *ocpdev)
1940{
1941 struct ocp_func_emac_data *emacdata = ocpdev->def->additions;
1942 struct net_device *ndev;
1943 struct ocp_device *maldev;
1944 struct ocp_enet_private *dev;
1945 int err, i;
1946 DECLARE_MAC_BUF(mac);
1947
1948 DBG("%d: probe" NL, ocpdev->def->index);
1949
1950 if (!emacdata) {
1951 printk(KERN_ERR "emac%d: Missing additional data!\n",
1952 ocpdev->def->index);
1953 return -ENODEV;
1954 }
1955
1956 /* Allocate our net_device structure */
1957 ndev = alloc_etherdev(sizeof(struct ocp_enet_private));
1958 if (!ndev) {
1959 printk(KERN_ERR "emac%d: could not allocate ethernet device!\n",
1960 ocpdev->def->index);
1961 return -ENOMEM;
1962 }
1963 dev = ndev->priv;
1964 dev->ndev = ndev;
1965 dev->ldev = &ocpdev->dev;
1966 dev->def = ocpdev->def;
1967
1968 /* Find MAL device we are connected to */
1969 maldev =
1970 ocp_find_device(OCP_VENDOR_IBM, OCP_FUNC_MAL, emacdata->mal_idx);
1971 if (!maldev) {
1972 printk(KERN_ERR "emac%d: unknown mal%d device!\n",
1973 dev->def->index, emacdata->mal_idx);
1974 err = -ENODEV;
1975 goto out;
1976 }
1977 dev->mal = ocp_get_drvdata(maldev);
1978 if (!dev->mal) {
1979 printk(KERN_ERR "emac%d: mal%d hasn't been initialized yet!\n",
1980 dev->def->index, emacdata->mal_idx);
1981 err = -ENODEV;
1982 goto out;
1983 }
1984
1985 /* Register with MAL */
1986 dev->commac.ops = &emac_commac_ops;
1987 dev->commac.dev = dev;
1988 dev->commac.tx_chan_mask = MAL_CHAN_MASK(emacdata->mal_tx_chan);
1989 dev->commac.rx_chan_mask = MAL_CHAN_MASK(emacdata->mal_rx_chan);
1990 err = mal_register_commac(dev->mal, &dev->commac);
1991 if (err) {
1992 printk(KERN_ERR "emac%d: failed to register with mal%d!\n",
1993 dev->def->index, emacdata->mal_idx);
1994 goto out;
1995 }
1996 dev->rx_skb_size = emac_rx_skb_size(ndev->mtu);
1997 dev->rx_sync_size = emac_rx_sync_size(ndev->mtu);
1998
1999 /* Get pointers to BD rings */
2000 dev->tx_desc =
2001 dev->mal->bd_virt + mal_tx_bd_offset(dev->mal,
2002 emacdata->mal_tx_chan);
2003 dev->rx_desc =
2004 dev->mal->bd_virt + mal_rx_bd_offset(dev->mal,
2005 emacdata->mal_rx_chan);
2006
2007 DBG("%d: tx_desc %p" NL, ocpdev->def->index, dev->tx_desc);
2008 DBG("%d: rx_desc %p" NL, ocpdev->def->index, dev->rx_desc);
2009
2010 /* Clean rings */
2011 memset(dev->tx_desc, 0, NUM_TX_BUFF * sizeof(struct mal_descriptor));
2012 memset(dev->rx_desc, 0, NUM_RX_BUFF * sizeof(struct mal_descriptor));
2013
2014 /* If we depend on another EMAC for MDIO, check whether it was probed already */
2015 if (emacdata->mdio_idx >= 0 && emacdata->mdio_idx != ocpdev->def->index) {
2016 struct ocp_device *mdiodev =
2017 ocp_find_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC,
2018 emacdata->mdio_idx);
2019 if (!mdiodev) {
2020 printk(KERN_ERR "emac%d: unknown emac%d device!\n",
2021 dev->def->index, emacdata->mdio_idx);
2022 err = -ENODEV;
2023 goto out2;
2024 }
2025 dev->mdio_dev = ocp_get_drvdata(mdiodev);
2026 if (!dev->mdio_dev) {
2027 printk(KERN_ERR
2028 "emac%d: emac%d hasn't been initialized yet!\n",
2029 dev->def->index, emacdata->mdio_idx);
2030 err = -ENODEV;
2031 goto out2;
2032 }
2033 }
2034
2035 /* Attach to ZMII, if needed */
2036 if ((err = zmii_attach(dev)) != 0)
2037 goto out2;
2038
2039 /* Attach to RGMII, if needed */
2040 if ((err = rgmii_attach(dev)) != 0)
2041 goto out3;
2042
2043 /* Attach to TAH, if needed */
2044 if ((err = tah_attach(dev)) != 0)
2045 goto out4;
2046
2047 /* Map EMAC regs */
2048 dev->emacp = ioremap(dev->def->paddr, sizeof(struct emac_regs));
2049 if (!dev->emacp) {
2050 printk(KERN_ERR "emac%d: could not ioremap device registers!\n",
2051 dev->def->index);
2052 err = -ENOMEM;
2053 goto out5;
2054 }
2055
2056 /* Fill in MAC address */
2057 for (i = 0; i < 6; ++i)
2058 ndev->dev_addr[i] = emacdata->mac_addr[i];
2059
2060 /* Set some link defaults before we can find out real parameters */
2061 dev->phy.speed = SPEED_100;
2062 dev->phy.duplex = DUPLEX_FULL;
2063 dev->phy.autoneg = AUTONEG_DISABLE;
2064 dev->phy.pause = dev->phy.asym_pause = 0;
2065 dev->stop_timeout = STOP_TIMEOUT_100;
2066 init_timer(&dev->link_timer);
2067 dev->link_timer.function = emac_link_timer;
2068 dev->link_timer.data = (unsigned long)dev;
2069
2070 /* Find PHY if any */
2071 dev->phy.dev = ndev;
2072 dev->phy.mode = emacdata->phy_mode;
2073 if (emacdata->phy_map != 0xffffffff) {
2074 u32 phy_map = emacdata->phy_map | busy_phy_map;
2075 u32 adv;
2076
2077 DBG("%d: PHY maps %08x %08x" NL, dev->def->index,
2078 emacdata->phy_map, busy_phy_map);
2079
2080 EMAC_RX_CLK_TX(dev->def->index);
2081
2082 dev->phy.mdio_read = emac_mdio_read;
2083 dev->phy.mdio_write = emac_mdio_write;
2084
2085 /* Configure EMAC with defaults so we can at least use MDIO
2086 * This is needed mostly for 440GX
2087 */
2088 if (emac_phy_gpcs(dev->phy.mode)) {
2089 /* XXX
2090 * Make GPCS PHY address equal to EMAC index.
2091 * We probably should take into account busy_phy_map
2092 * and/or phy_map here.
2093 */
2094 dev->phy.address = dev->def->index;
2095 }
2096
2097 emac_configure(dev);
2098
2099 for (i = 0; i < 0x20; phy_map >>= 1, ++i)
2100 if (!(phy_map & 1)) {
2101 int r;
2102 busy_phy_map |= 1 << i;
2103
2104 /* Quick check if there is a PHY at the address */
2105 r = emac_mdio_read(dev->ndev, i, MII_BMCR);
2106 if (r == 0xffff || r < 0)
2107 continue;
2108 if (!mii_phy_probe(&dev->phy, i))
2109 break;
2110 }
2111 if (i == 0x20) {
2112 printk(KERN_WARNING "emac%d: can't find PHY!\n",
2113 dev->def->index);
2114 goto out6;
2115 }
2116
2117 /* Init PHY */
2118 if (dev->phy.def->ops->init)
2119 dev->phy.def->ops->init(&dev->phy);
2120
2121 /* Disable any PHY features not supported by the platform */
2122 dev->phy.def->features &= ~emacdata->phy_feat_exc;
2123
2124 /* Setup initial link parameters */
2125 if (dev->phy.features & SUPPORTED_Autoneg) {
2126 adv = dev->phy.features;
2127#if !defined(CONFIG_40x)
2128 adv |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
2129#endif
2130 /* Restart autonegotiation */
2131 dev->phy.def->ops->setup_aneg(&dev->phy, adv);
2132 } else {
2133 u32 f = dev->phy.def->features;
2134 int speed = SPEED_10, fd = DUPLEX_HALF;
2135
2136 /* Select highest supported speed/duplex */
2137 if (f & SUPPORTED_1000baseT_Full) {
2138 speed = SPEED_1000;
2139 fd = DUPLEX_FULL;
2140 } else if (f & SUPPORTED_1000baseT_Half)
2141 speed = SPEED_1000;
2142 else if (f & SUPPORTED_100baseT_Full) {
2143 speed = SPEED_100;
2144 fd = DUPLEX_FULL;
2145 } else if (f & SUPPORTED_100baseT_Half)
2146 speed = SPEED_100;
2147 else if (f & SUPPORTED_10baseT_Full)
2148 fd = DUPLEX_FULL;
2149
2150 /* Force link parameters */
2151 dev->phy.def->ops->setup_forced(&dev->phy, speed, fd);
2152 }
2153 } else {
2154 emac_reset(dev);
2155
2156 /* PHY-less configuration.
2157 * XXX I probably should move these settings to emacdata
2158 */
2159 dev->phy.address = -1;
2160 dev->phy.features = SUPPORTED_100baseT_Full | SUPPORTED_MII;
2161 dev->phy.pause = 1;
2162 }
2163
2164 /* Fill in the driver function table */
2165 ndev->open = &emac_open;
2166 if (dev->tah_dev) {
2167 ndev->hard_start_xmit = &emac_start_xmit_sg;
2168 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
2169 } else
2170 ndev->hard_start_xmit = &emac_start_xmit;
2171 ndev->tx_timeout = &emac_full_tx_reset;
2172 ndev->watchdog_timeo = 5 * HZ;
2173 ndev->stop = &emac_close;
2174 ndev->get_stats = &emac_stats;
2175 ndev->set_multicast_list = &emac_set_multicast_list;
2176 ndev->do_ioctl = &emac_ioctl;
2177 if (emac_phy_supports_gige(emacdata->phy_mode)) {
2178 ndev->change_mtu = &emac_change_mtu;
2179 dev->commac.ops = &emac_commac_sg_ops;
2180 }
2181 SET_ETHTOOL_OPS(ndev, &emac_ethtool_ops);
2182
2183 netif_carrier_off(ndev);
2184 netif_stop_queue(ndev);
2185
2186 err = register_netdev(ndev);
2187 if (err) {
2188 printk(KERN_ERR "emac%d: failed to register net device (%d)!\n",
2189 dev->def->index, err);
2190 goto out6;
2191 }
2192
2193 ocp_set_drvdata(ocpdev, dev);
2194
2195 printk("%s: emac%d, MAC %s\n",
2196 ndev->name, dev->def->index, print_mac(mac, ndev->dev_addr));
2197
2198 if (dev->phy.address >= 0)
2199 printk("%s: found %s PHY (0x%02x)\n", ndev->name,
2200 dev->phy.def->name, dev->phy.address);
2201
2202 emac_dbg_register(dev->def->index, dev);
2203
2204 return 0;
2205 out6:
2206 iounmap(dev->emacp);
2207 out5:
2208 tah_fini(dev->tah_dev);
2209 out4:
2210 rgmii_fini(dev->rgmii_dev, dev->rgmii_input);
2211 out3:
2212 zmii_fini(dev->zmii_dev, dev->zmii_input);
2213 out2:
2214 mal_unregister_commac(dev->mal, &dev->commac);
2215 out:
2216 kfree(ndev);
2217 return err;
2218}
2219
2220static struct ocp_device_id emac_ids[] = {
2221 { .vendor = OCP_VENDOR_IBM, .function = OCP_FUNC_EMAC },
2222 { .vendor = OCP_VENDOR_INVALID}
2223};
2224
2225static struct ocp_driver emac_driver = {
2226 .name = "emac",
2227 .id_table = emac_ids,
2228 .probe = emac_probe,
2229 .remove = emac_remove,
2230};
2231
2232static int __init emac_init(void)
2233{
2234 printk(KERN_INFO DRV_DESC ", version " DRV_VERSION "\n");
2235
2236 DBG(": init" NL);
2237
2238 if (mal_init())
2239 return -ENODEV;
2240
2241 EMAC_CLK_INTERNAL;
2242 if (ocp_register_driver(&emac_driver)) {
2243 EMAC_CLK_EXTERNAL;
2244 ocp_unregister_driver(&emac_driver);
2245 mal_exit();
2246 return -ENODEV;
2247 }
2248 EMAC_CLK_EXTERNAL;
2249
2250 emac_init_debug();
2251 return 0;
2252}
2253
2254static void __exit emac_exit(void)
2255{
2256 DBG(": exit" NL);
2257 ocp_unregister_driver(&emac_driver);
2258 mal_exit();
2259 emac_fini_debug();
2260}
2261
2262module_init(emac_init);
2263module_exit(emac_exit);
diff --git a/drivers/net/ibm_emac/ibm_emac_core.h b/drivers/net/ibm_emac/ibm_emac_core.h
deleted file mode 100644
index dabb94afeb98..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_core.h
+++ /dev/null
@@ -1,222 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_core.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Armin Kuster <akuster@mvista.com>
11 * Johnnie Peters <jpeters@mvista.com>
12 * Copyright 2000, 2001 MontaVista Softare Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 *
19 */
20#ifndef __IBM_EMAC_CORE_H_
21#define __IBM_EMAC_CORE_H_
22
23#include <linux/netdevice.h>
24#include <linux/dma-mapping.h>
25#include <asm/ocp.h>
26
27#include "ibm_emac.h"
28#include "ibm_emac_phy.h"
29#include "ibm_emac_zmii.h"
30#include "ibm_emac_rgmii.h"
31#include "ibm_emac_mal.h"
32#include "ibm_emac_tah.h"
33
34#define NUM_TX_BUFF CONFIG_IBM_EMAC_TXB
35#define NUM_RX_BUFF CONFIG_IBM_EMAC_RXB
36
37/* Simple sanity check */
38#if NUM_TX_BUFF > 256 || NUM_RX_BUFF > 256
39#error Invalid number of buffer descriptors (greater than 256)
40#endif
41
42// XXX
43#define EMAC_MIN_MTU 46
44#define EMAC_MAX_MTU 9000
45
46/* Maximum L2 header length (VLAN tagged, no FCS) */
47#define EMAC_MTU_OVERHEAD (6 * 2 + 2 + 4)
48
49/* RX BD size for the given MTU */
50static inline int emac_rx_size(int mtu)
51{
52 if (mtu > ETH_DATA_LEN)
53 return MAL_MAX_RX_SIZE;
54 else
55 return mal_rx_size(ETH_DATA_LEN + EMAC_MTU_OVERHEAD);
56}
57
58#define EMAC_DMA_ALIGN(x) ALIGN((x), dma_get_cache_alignment())
59
60#define EMAC_RX_SKB_HEADROOM \
61 EMAC_DMA_ALIGN(CONFIG_IBM_EMAC_RX_SKB_HEADROOM)
62
63/* Size of RX skb for the given MTU */
64static inline int emac_rx_skb_size(int mtu)
65{
66 int size = max(mtu + EMAC_MTU_OVERHEAD, emac_rx_size(mtu));
67 return EMAC_DMA_ALIGN(size + 2) + EMAC_RX_SKB_HEADROOM;
68}
69
70/* RX DMA sync size */
71static inline int emac_rx_sync_size(int mtu)
72{
73 return EMAC_DMA_ALIGN(emac_rx_size(mtu) + 2);
74}
75
76/* Driver statistcs is split into two parts to make it more cache friendly:
77 * - normal statistics (packet count, etc)
78 * - error statistics
79 *
80 * When statistics is requested by ethtool, these parts are concatenated,
81 * normal one goes first.
82 *
83 * Please, keep these structures in sync with emac_stats_keys.
84 */
85
86/* Normal TX/RX Statistics */
87struct ibm_emac_stats {
88 u64 rx_packets;
89 u64 rx_bytes;
90 u64 tx_packets;
91 u64 tx_bytes;
92 u64 rx_packets_csum;
93 u64 tx_packets_csum;
94};
95
96/* Error statistics */
97struct ibm_emac_error_stats {
98 u64 tx_undo;
99
100 /* Software RX Errors */
101 u64 rx_dropped_stack;
102 u64 rx_dropped_oom;
103 u64 rx_dropped_error;
104 u64 rx_dropped_resize;
105 u64 rx_dropped_mtu;
106 u64 rx_stopped;
107 /* BD reported RX errors */
108 u64 rx_bd_errors;
109 u64 rx_bd_overrun;
110 u64 rx_bd_bad_packet;
111 u64 rx_bd_runt_packet;
112 u64 rx_bd_short_event;
113 u64 rx_bd_alignment_error;
114 u64 rx_bd_bad_fcs;
115 u64 rx_bd_packet_too_long;
116 u64 rx_bd_out_of_range;
117 u64 rx_bd_in_range;
118 /* EMAC IRQ reported RX errors */
119 u64 rx_parity;
120 u64 rx_fifo_overrun;
121 u64 rx_overrun;
122 u64 rx_bad_packet;
123 u64 rx_runt_packet;
124 u64 rx_short_event;
125 u64 rx_alignment_error;
126 u64 rx_bad_fcs;
127 u64 rx_packet_too_long;
128 u64 rx_out_of_range;
129 u64 rx_in_range;
130
131 /* Software TX Errors */
132 u64 tx_dropped;
133 /* BD reported TX errors */
134 u64 tx_bd_errors;
135 u64 tx_bd_bad_fcs;
136 u64 tx_bd_carrier_loss;
137 u64 tx_bd_excessive_deferral;
138 u64 tx_bd_excessive_collisions;
139 u64 tx_bd_late_collision;
140 u64 tx_bd_multple_collisions;
141 u64 tx_bd_single_collision;
142 u64 tx_bd_underrun;
143 u64 tx_bd_sqe;
144 /* EMAC IRQ reported TX errors */
145 u64 tx_parity;
146 u64 tx_underrun;
147 u64 tx_sqe;
148 u64 tx_errors;
149};
150
151#define EMAC_ETHTOOL_STATS_COUNT ((sizeof(struct ibm_emac_stats) + \
152 sizeof(struct ibm_emac_error_stats)) \
153 / sizeof(u64))
154
155struct ocp_enet_private {
156 struct net_device *ndev; /* 0 */
157 struct emac_regs __iomem *emacp;
158
159 struct mal_descriptor *tx_desc;
160 int tx_cnt;
161 int tx_slot;
162 int ack_slot;
163
164 struct mal_descriptor *rx_desc;
165 int rx_slot;
166 struct sk_buff *rx_sg_skb; /* 1 */
167 int rx_skb_size;
168 int rx_sync_size;
169
170 struct ibm_emac_stats stats;
171 struct ocp_device *tah_dev;
172
173 struct ibm_ocp_mal *mal;
174 struct mal_commac commac;
175
176 struct sk_buff *tx_skb[NUM_TX_BUFF];
177 struct sk_buff *rx_skb[NUM_RX_BUFF];
178
179 struct ocp_device *zmii_dev;
180 int zmii_input;
181 struct ocp_enet_private *mdio_dev;
182 struct ocp_device *rgmii_dev;
183 int rgmii_input;
184
185 struct ocp_def *def;
186
187 struct mii_phy phy;
188 struct timer_list link_timer;
189 int reset_failed;
190
191 int stop_timeout; /* in us */
192
193 struct ibm_emac_error_stats estats;
194 struct net_device_stats nstats;
195
196 struct device* ldev;
197};
198
199/* Ethtool get_regs complex data.
200 * We want to get not just EMAC registers, but also MAL, ZMII, RGMII, TAH
201 * when available.
202 *
203 * Returned BLOB consists of the ibm_emac_ethtool_regs_hdr,
204 * MAL registers, EMAC registers and optional ZMII, RGMII, TAH registers.
205 * Each register component is preceded with emac_ethtool_regs_subhdr.
206 * Order of the optional headers follows their relative bit posititions
207 * in emac_ethtool_regs_hdr.components
208 */
209#define EMAC_ETHTOOL_REGS_ZMII 0x00000001
210#define EMAC_ETHTOOL_REGS_RGMII 0x00000002
211#define EMAC_ETHTOOL_REGS_TAH 0x00000004
212
213struct emac_ethtool_regs_hdr {
214 u32 components;
215};
216
217struct emac_ethtool_regs_subhdr {
218 u32 version;
219 u32 index;
220};
221
222#endif /* __IBM_EMAC_CORE_H_ */
diff --git a/drivers/net/ibm_emac/ibm_emac_debug.c b/drivers/net/ibm_emac/ibm_emac_debug.c
deleted file mode 100644
index 1f70906cfb98..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_debug.c
+++ /dev/null
@@ -1,211 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_debug.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, debug print routines.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/netdevice.h>
19#include <linux/sysrq.h>
20#include <asm/io.h>
21
22#include "ibm_emac_core.h"
23
24static void emac_desc_dump(int idx, struct ocp_enet_private *p)
25{
26 int i;
27 printk("** EMAC%d TX BDs **\n"
28 " tx_cnt = %d tx_slot = %d ack_slot = %d\n",
29 idx, p->tx_cnt, p->tx_slot, p->ack_slot);
30 for (i = 0; i < NUM_TX_BUFF / 2; ++i)
31 printk
32 ("bd[%2d] 0x%08x %c 0x%04x %4u - bd[%2d] 0x%08x %c 0x%04x %4u\n",
33 i, p->tx_desc[i].data_ptr, p->tx_skb[i] ? 'V' : ' ',
34 p->tx_desc[i].ctrl, p->tx_desc[i].data_len,
35 NUM_TX_BUFF / 2 + i,
36 p->tx_desc[NUM_TX_BUFF / 2 + i].data_ptr,
37 p->tx_skb[NUM_TX_BUFF / 2 + i] ? 'V' : ' ',
38 p->tx_desc[NUM_TX_BUFF / 2 + i].ctrl,
39 p->tx_desc[NUM_TX_BUFF / 2 + i].data_len);
40
41 printk("** EMAC%d RX BDs **\n"
42 " rx_slot = %d rx_stopped = %d rx_skb_size = %d rx_sync_size = %d\n"
43 " rx_sg_skb = 0x%p\n",
44 idx, p->rx_slot, p->commac.rx_stopped, p->rx_skb_size,
45 p->rx_sync_size, p->rx_sg_skb);
46 for (i = 0; i < NUM_RX_BUFF / 2; ++i)
47 printk
48 ("bd[%2d] 0x%08x %c 0x%04x %4u - bd[%2d] 0x%08x %c 0x%04x %4u\n",
49 i, p->rx_desc[i].data_ptr, p->rx_skb[i] ? 'V' : ' ',
50 p->rx_desc[i].ctrl, p->rx_desc[i].data_len,
51 NUM_RX_BUFF / 2 + i,
52 p->rx_desc[NUM_RX_BUFF / 2 + i].data_ptr,
53 p->rx_skb[NUM_RX_BUFF / 2 + i] ? 'V' : ' ',
54 p->rx_desc[NUM_RX_BUFF / 2 + i].ctrl,
55 p->rx_desc[NUM_RX_BUFF / 2 + i].data_len);
56}
57
58static void emac_mac_dump(int idx, struct ocp_enet_private *dev)
59{
60 struct emac_regs __iomem *p = dev->emacp;
61
62 printk("** EMAC%d registers **\n"
63 "MR0 = 0x%08x MR1 = 0x%08x TMR0 = 0x%08x TMR1 = 0x%08x\n"
64 "RMR = 0x%08x ISR = 0x%08x ISER = 0x%08x\n"
65 "IAR = %04x%08x VTPID = 0x%04x VTCI = 0x%04x\n"
66 "IAHT: 0x%04x 0x%04x 0x%04x 0x%04x "
67 "GAHT: 0x%04x 0x%04x 0x%04x 0x%04x\n"
68 "LSA = %04x%08x IPGVR = 0x%04x\n"
69 "STACR = 0x%08x TRTR = 0x%08x RWMR = 0x%08x\n"
70 "OCTX = 0x%08x OCRX = 0x%08x IPCR = 0x%08x\n",
71 idx, in_be32(&p->mr0), in_be32(&p->mr1),
72 in_be32(&p->tmr0), in_be32(&p->tmr1),
73 in_be32(&p->rmr), in_be32(&p->isr), in_be32(&p->iser),
74 in_be32(&p->iahr), in_be32(&p->ialr), in_be32(&p->vtpid),
75 in_be32(&p->vtci),
76 in_be32(&p->iaht1), in_be32(&p->iaht2), in_be32(&p->iaht3),
77 in_be32(&p->iaht4),
78 in_be32(&p->gaht1), in_be32(&p->gaht2), in_be32(&p->gaht3),
79 in_be32(&p->gaht4),
80 in_be32(&p->lsah), in_be32(&p->lsal), in_be32(&p->ipgvr),
81 in_be32(&p->stacr), in_be32(&p->trtr), in_be32(&p->rwmr),
82 in_be32(&p->octx), in_be32(&p->ocrx), in_be32(&p->ipcr)
83 );
84
85 emac_desc_dump(idx, dev);
86}
87
88static void emac_mal_dump(struct ibm_ocp_mal *mal)
89{
90 struct ocp_func_mal_data *maldata = mal->def->additions;
91 int i;
92
93 printk("** MAL%d Registers **\n"
94 "CFG = 0x%08x ESR = 0x%08x IER = 0x%08x\n"
95 "TX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x\n"
96 "RX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x\n",
97 mal->def->index,
98 get_mal_dcrn(mal, MAL_CFG), get_mal_dcrn(mal, MAL_ESR),
99 get_mal_dcrn(mal, MAL_IER),
100 get_mal_dcrn(mal, MAL_TXCASR), get_mal_dcrn(mal, MAL_TXCARR),
101 get_mal_dcrn(mal, MAL_TXEOBISR), get_mal_dcrn(mal, MAL_TXDEIR),
102 get_mal_dcrn(mal, MAL_RXCASR), get_mal_dcrn(mal, MAL_RXCARR),
103 get_mal_dcrn(mal, MAL_RXEOBISR), get_mal_dcrn(mal, MAL_RXDEIR)
104 );
105
106 printk("TX|");
107 for (i = 0; i < maldata->num_tx_chans; ++i) {
108 if (i && !(i % 4))
109 printk("\n ");
110 printk("CTP%d = 0x%08x ", i, get_mal_dcrn(mal, MAL_TXCTPR(i)));
111 }
112 printk("\nRX|");
113 for (i = 0; i < maldata->num_rx_chans; ++i) {
114 if (i && !(i % 4))
115 printk("\n ");
116 printk("CTP%d = 0x%08x ", i, get_mal_dcrn(mal, MAL_RXCTPR(i)));
117 }
118 printk("\n ");
119 for (i = 0; i < maldata->num_rx_chans; ++i) {
120 u32 r = get_mal_dcrn(mal, MAL_RCBS(i));
121 if (i && !(i % 3))
122 printk("\n ");
123 printk("RCBS%d = 0x%08x (%d) ", i, r, r * 16);
124 }
125 printk("\n");
126}
127
128static struct ocp_enet_private *__emacs[4];
129static struct ibm_ocp_mal *__mals[1];
130
131void emac_dbg_register(int idx, struct ocp_enet_private *dev)
132{
133 unsigned long flags;
134
135 if (idx >= ARRAY_SIZE(__emacs)) {
136 printk(KERN_WARNING
137 "invalid index %d when registering EMAC for debugging\n",
138 idx);
139 return;
140 }
141
142 local_irq_save(flags);
143 __emacs[idx] = dev;
144 local_irq_restore(flags);
145}
146
147void mal_dbg_register(int idx, struct ibm_ocp_mal *mal)
148{
149 unsigned long flags;
150
151 if (idx >= ARRAY_SIZE(__mals)) {
152 printk(KERN_WARNING
153 "invalid index %d when registering MAL for debugging\n",
154 idx);
155 return;
156 }
157
158 local_irq_save(flags);
159 __mals[idx] = mal;
160 local_irq_restore(flags);
161}
162
163void emac_dbg_dump_all(void)
164{
165 unsigned int i;
166 unsigned long flags;
167
168 local_irq_save(flags);
169
170 for (i = 0; i < ARRAY_SIZE(__mals); ++i)
171 if (__mals[i])
172 emac_mal_dump(__mals[i]);
173
174 for (i = 0; i < ARRAY_SIZE(__emacs); ++i)
175 if (__emacs[i])
176 emac_mac_dump(i, __emacs[i]);
177
178 local_irq_restore(flags);
179}
180
181#if defined(CONFIG_MAGIC_SYSRQ)
182static void emac_sysrq_handler(int key, struct tty_struct *tty)
183{
184 emac_dbg_dump_all();
185}
186
187static struct sysrq_key_op emac_sysrq_op = {
188 .handler = emac_sysrq_handler,
189 .help_msg = "emaC",
190 .action_msg = "Show EMAC(s) status",
191};
192
193int __init emac_init_debug(void)
194{
195 return register_sysrq_key('c', &emac_sysrq_op);
196}
197
198void __exit emac_fini_debug(void)
199{
200 unregister_sysrq_key('c', &emac_sysrq_op);
201}
202
203#else
204int __init emac_init_debug(void)
205{
206 return 0;
207}
208void __exit emac_fini_debug(void)
209{
210}
211#endif /* CONFIG_MAGIC_SYSRQ */
diff --git a/drivers/net/ibm_emac/ibm_emac_debug.h b/drivers/net/ibm_emac/ibm_emac_debug.h
deleted file mode 100644
index 6c7dccc84bf5..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_debug.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_debug.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, debug print routines.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15#ifndef __IBM_EMAC_DEBUG_H_
16#define __IBM_EMAC_DEBUG_H_
17
18#include <linux/init.h>
19#include "ibm_emac_core.h"
20#include "ibm_emac_mal.h"
21
22#if defined(CONFIG_IBM_EMAC_DEBUG)
23void emac_dbg_register(int idx, struct ocp_enet_private *dev);
24void mal_dbg_register(int idx, struct ibm_ocp_mal *mal);
25int emac_init_debug(void) __init;
26void emac_fini_debug(void) __exit;
27void emac_dbg_dump_all(void);
28# define DBG_LEVEL 1
29#else
30# define emac_dbg_register(x,y) ((void)0)
31# define mal_dbg_register(x,y) ((void)0)
32# define emac_init_debug() ((void)0)
33# define emac_fini_debug() ((void)0)
34# define emac_dbg_dump_all() ((void)0)
35# define DBG_LEVEL 0
36#endif
37
38#if DBG_LEVEL > 0
39# define DBG(f,x...) printk("emac" f, ##x)
40# define MAL_DBG(f,x...) printk("mal" f, ##x)
41# define ZMII_DBG(f,x...) printk("zmii" f, ##x)
42# define RGMII_DBG(f,x...) printk("rgmii" f, ##x)
43# define NL "\n"
44#else
45# define DBG(f,x...) ((void)0)
46# define MAL_DBG(f,x...) ((void)0)
47# define ZMII_DBG(f,x...) ((void)0)
48# define RGMII_DBG(f,x...) ((void)0)
49#endif
50#if DBG_LEVEL > 1
51# define DBG2(f,x...) DBG(f, ##x)
52# define MAL_DBG2(f,x...) MAL_DBG(f, ##x)
53# define ZMII_DBG2(f,x...) ZMII_DBG(f, ##x)
54# define RGMII_DBG2(f,x...) RGMII_DBG(f, ##x)
55#else
56# define DBG2(f,x...) ((void)0)
57# define MAL_DBG2(f,x...) ((void)0)
58# define ZMII_DBG2(f,x...) ((void)0)
59# define RGMII_DBG2(f,x...) ((void)0)
60#endif
61
62#endif /* __IBM_EMAC_DEBUG_H_ */
diff --git a/drivers/net/ibm_emac/ibm_emac_mal.c b/drivers/net/ibm_emac/ibm_emac_mal.c
deleted file mode 100644
index dcd8826fc749..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_mal.c
+++ /dev/null
@@ -1,570 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_mal.c
3 *
4 * Memory Access Layer (MAL) support
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Benjamin Herrenschmidt <benh@kernel.crashing.org>,
11 * David Gibson <hermes@gibson.dropbear.id.au>,
12 *
13 * Armin Kuster <akuster@mvista.com>
14 * Copyright 2002 MontaVista Softare Inc.
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 */
22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/errno.h>
25#include <linux/netdevice.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/dma-mapping.h>
29
30#include <asm/ocp.h>
31
32#include "ibm_emac_core.h"
33#include "ibm_emac_mal.h"
34#include "ibm_emac_debug.h"
35
36int __init mal_register_commac(struct ibm_ocp_mal *mal,
37 struct mal_commac *commac)
38{
39 unsigned long flags;
40 local_irq_save(flags);
41
42 MAL_DBG("%d: reg(%08x, %08x)" NL, mal->def->index,
43 commac->tx_chan_mask, commac->rx_chan_mask);
44
45 /* Don't let multiple commacs claim the same channel(s) */
46 if ((mal->tx_chan_mask & commac->tx_chan_mask) ||
47 (mal->rx_chan_mask & commac->rx_chan_mask)) {
48 local_irq_restore(flags);
49 printk(KERN_WARNING "mal%d: COMMAC channels conflict!\n",
50 mal->def->index);
51 return -EBUSY;
52 }
53
54 mal->tx_chan_mask |= commac->tx_chan_mask;
55 mal->rx_chan_mask |= commac->rx_chan_mask;
56 list_add(&commac->list, &mal->list);
57
58 local_irq_restore(flags);
59 return 0;
60}
61
62void mal_unregister_commac(struct ibm_ocp_mal *mal, struct mal_commac *commac)
63{
64 unsigned long flags;
65 local_irq_save(flags);
66
67 MAL_DBG("%d: unreg(%08x, %08x)" NL, mal->def->index,
68 commac->tx_chan_mask, commac->rx_chan_mask);
69
70 mal->tx_chan_mask &= ~commac->tx_chan_mask;
71 mal->rx_chan_mask &= ~commac->rx_chan_mask;
72 list_del_init(&commac->list);
73
74 local_irq_restore(flags);
75}
76
77int mal_set_rcbs(struct ibm_ocp_mal *mal, int channel, unsigned long size)
78{
79 struct ocp_func_mal_data *maldata = mal->def->additions;
80 BUG_ON(channel < 0 || channel >= maldata->num_rx_chans ||
81 size > MAL_MAX_RX_SIZE);
82
83 MAL_DBG("%d: set_rbcs(%d, %lu)" NL, mal->def->index, channel, size);
84
85 if (size & 0xf) {
86 printk(KERN_WARNING
87 "mal%d: incorrect RX size %lu for the channel %d\n",
88 mal->def->index, size, channel);
89 return -EINVAL;
90 }
91
92 set_mal_dcrn(mal, MAL_RCBS(channel), size >> 4);
93 return 0;
94}
95
96int mal_tx_bd_offset(struct ibm_ocp_mal *mal, int channel)
97{
98 struct ocp_func_mal_data *maldata = mal->def->additions;
99 BUG_ON(channel < 0 || channel >= maldata->num_tx_chans);
100 return channel * NUM_TX_BUFF;
101}
102
103int mal_rx_bd_offset(struct ibm_ocp_mal *mal, int channel)
104{
105 struct ocp_func_mal_data *maldata = mal->def->additions;
106 BUG_ON(channel < 0 || channel >= maldata->num_rx_chans);
107 return maldata->num_tx_chans * NUM_TX_BUFF + channel * NUM_RX_BUFF;
108}
109
110void mal_enable_tx_channel(struct ibm_ocp_mal *mal, int channel)
111{
112 local_bh_disable();
113 MAL_DBG("%d: enable_tx(%d)" NL, mal->def->index, channel);
114 set_mal_dcrn(mal, MAL_TXCASR,
115 get_mal_dcrn(mal, MAL_TXCASR) | MAL_CHAN_MASK(channel));
116 local_bh_enable();
117}
118
119void mal_disable_tx_channel(struct ibm_ocp_mal *mal, int channel)
120{
121 set_mal_dcrn(mal, MAL_TXCARR, MAL_CHAN_MASK(channel));
122 MAL_DBG("%d: disable_tx(%d)" NL, mal->def->index, channel);
123}
124
125void mal_enable_rx_channel(struct ibm_ocp_mal *mal, int channel)
126{
127 local_bh_disable();
128 MAL_DBG("%d: enable_rx(%d)" NL, mal->def->index, channel);
129 set_mal_dcrn(mal, MAL_RXCASR,
130 get_mal_dcrn(mal, MAL_RXCASR) | MAL_CHAN_MASK(channel));
131 local_bh_enable();
132}
133
134void mal_disable_rx_channel(struct ibm_ocp_mal *mal, int channel)
135{
136 set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel));
137 MAL_DBG("%d: disable_rx(%d)" NL, mal->def->index, channel);
138}
139
140void mal_poll_add(struct ibm_ocp_mal *mal, struct mal_commac *commac)
141{
142 local_bh_disable();
143 MAL_DBG("%d: poll_add(%p)" NL, mal->def->index, commac);
144 list_add_tail(&commac->poll_list, &mal->poll_list);
145 local_bh_enable();
146}
147
148void mal_poll_del(struct ibm_ocp_mal *mal, struct mal_commac *commac)
149{
150 local_bh_disable();
151 MAL_DBG("%d: poll_del(%p)" NL, mal->def->index, commac);
152 list_del(&commac->poll_list);
153 local_bh_enable();
154}
155
156/* synchronized by mal_poll() */
157static inline void mal_enable_eob_irq(struct ibm_ocp_mal *mal)
158{
159 MAL_DBG2("%d: enable_irq" NL, mal->def->index);
160 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) | MAL_CFG_EOPIE);
161}
162
163/* synchronized by __LINK_STATE_RX_SCHED bit in ndev->state */
164static inline void mal_disable_eob_irq(struct ibm_ocp_mal *mal)
165{
166 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) & ~MAL_CFG_EOPIE);
167 MAL_DBG2("%d: disable_irq" NL, mal->def->index);
168}
169
170static irqreturn_t mal_serr(int irq, void *dev_instance)
171{
172 struct ibm_ocp_mal *mal = dev_instance;
173 u32 esr = get_mal_dcrn(mal, MAL_ESR);
174
175 /* Clear the error status register */
176 set_mal_dcrn(mal, MAL_ESR, esr);
177
178 MAL_DBG("%d: SERR %08x" NL, mal->def->index, esr);
179
180 if (esr & MAL_ESR_EVB) {
181 if (esr & MAL_ESR_DE) {
182 /* We ignore Descriptor error,
183 * TXDE or RXDE interrupt will be generated anyway.
184 */
185 return IRQ_HANDLED;
186 }
187
188 if (esr & MAL_ESR_PEIN) {
189 /* PLB error, it's probably buggy hardware or
190 * incorrect physical address in BD (i.e. bug)
191 */
192 if (net_ratelimit())
193 printk(KERN_ERR
194 "mal%d: system error, PLB (ESR = 0x%08x)\n",
195 mal->def->index, esr);
196 return IRQ_HANDLED;
197 }
198
199 /* OPB error, it's probably buggy hardware or incorrect EBC setup */
200 if (net_ratelimit())
201 printk(KERN_ERR
202 "mal%d: system error, OPB (ESR = 0x%08x)\n",
203 mal->def->index, esr);
204 }
205 return IRQ_HANDLED;
206}
207
208static inline void mal_schedule_poll(struct ibm_ocp_mal *mal)
209{
210 if (likely(napi_schedule_prep(&mal->napi))) {
211 MAL_DBG2("%d: schedule_poll" NL, mal->def->index);
212 mal_disable_eob_irq(mal);
213 __napi_schedule(&mal->napi);
214 } else
215 MAL_DBG2("%d: already in poll" NL, mal->def->index);
216}
217
218static irqreturn_t mal_txeob(int irq, void *dev_instance)
219{
220 struct ibm_ocp_mal *mal = dev_instance;
221 u32 r = get_mal_dcrn(mal, MAL_TXEOBISR);
222 MAL_DBG2("%d: txeob %08x" NL, mal->def->index, r);
223 mal_schedule_poll(mal);
224 set_mal_dcrn(mal, MAL_TXEOBISR, r);
225 return IRQ_HANDLED;
226}
227
228static irqreturn_t mal_rxeob(int irq, void *dev_instance)
229{
230 struct ibm_ocp_mal *mal = dev_instance;
231 u32 r = get_mal_dcrn(mal, MAL_RXEOBISR);
232 MAL_DBG2("%d: rxeob %08x" NL, mal->def->index, r);
233 mal_schedule_poll(mal);
234 set_mal_dcrn(mal, MAL_RXEOBISR, r);
235 return IRQ_HANDLED;
236}
237
238static irqreturn_t mal_txde(int irq, void *dev_instance)
239{
240 struct ibm_ocp_mal *mal = dev_instance;
241 u32 deir = get_mal_dcrn(mal, MAL_TXDEIR);
242 set_mal_dcrn(mal, MAL_TXDEIR, deir);
243
244 MAL_DBG("%d: txde %08x" NL, mal->def->index, deir);
245
246 if (net_ratelimit())
247 printk(KERN_ERR
248 "mal%d: TX descriptor error (TXDEIR = 0x%08x)\n",
249 mal->def->index, deir);
250
251 return IRQ_HANDLED;
252}
253
254static irqreturn_t mal_rxde(int irq, void *dev_instance)
255{
256 struct ibm_ocp_mal *mal = dev_instance;
257 struct list_head *l;
258 u32 deir = get_mal_dcrn(mal, MAL_RXDEIR);
259
260 MAL_DBG("%d: rxde %08x" NL, mal->def->index, deir);
261
262 list_for_each(l, &mal->list) {
263 struct mal_commac *mc = list_entry(l, struct mal_commac, list);
264 if (deir & mc->rx_chan_mask) {
265 mc->rx_stopped = 1;
266 mc->ops->rxde(mc->dev);
267 }
268 }
269
270 mal_schedule_poll(mal);
271 set_mal_dcrn(mal, MAL_RXDEIR, deir);
272
273 return IRQ_HANDLED;
274}
275
276static int mal_poll(struct napi_struct *napi, int budget)
277{
278 struct ibm_ocp_mal *mal = container_of(napi, struct ibm_ocp_mal, napi);
279 struct list_head *l;
280 int received = 0;
281
282 MAL_DBG2("%d: poll(%d) %d ->" NL, mal->def->index, *budget,
283 rx_work_limit);
284 again:
285 /* Process TX skbs */
286 list_for_each(l, &mal->poll_list) {
287 struct mal_commac *mc =
288 list_entry(l, struct mal_commac, poll_list);
289 mc->ops->poll_tx(mc->dev);
290 }
291
292 /* Process RX skbs.
293 * We _might_ need something more smart here to enforce polling fairness.
294 */
295 list_for_each(l, &mal->poll_list) {
296 struct mal_commac *mc =
297 list_entry(l, struct mal_commac, poll_list);
298 int n = mc->ops->poll_rx(mc->dev, budget);
299 if (n) {
300 received += n;
301 budget -= n;
302 if (budget <= 0)
303 goto more_work; // XXX What if this is the last one ?
304 }
305 }
306
307 /* We need to disable IRQs to protect from RXDE IRQ here */
308 local_irq_disable();
309 __napi_complete(napi);
310 mal_enable_eob_irq(mal);
311 local_irq_enable();
312
313 /* Check for "rotting" packet(s) */
314 list_for_each(l, &mal->poll_list) {
315 struct mal_commac *mc =
316 list_entry(l, struct mal_commac, poll_list);
317 if (unlikely(mc->ops->peek_rx(mc->dev) || mc->rx_stopped)) {
318 MAL_DBG2("%d: rotting packet" NL, mal->def->index);
319 if (napi_reschedule(napi))
320 mal_disable_eob_irq(mal);
321 else
322 MAL_DBG2("%d: already in poll list" NL,
323 mal->def->index);
324
325 if (budget > 0)
326 goto again;
327 else
328 goto more_work;
329 }
330 mc->ops->poll_tx(mc->dev);
331 }
332
333 more_work:
334 MAL_DBG2("%d: poll() %d <- %d" NL, mal->def->index, budget, received);
335 return received;
336}
337
338static void mal_reset(struct ibm_ocp_mal *mal)
339{
340 int n = 10;
341 MAL_DBG("%d: reset" NL, mal->def->index);
342
343 set_mal_dcrn(mal, MAL_CFG, MAL_CFG_SR);
344
345 /* Wait for reset to complete (1 system clock) */
346 while ((get_mal_dcrn(mal, MAL_CFG) & MAL_CFG_SR) && n)
347 --n;
348
349 if (unlikely(!n))
350 printk(KERN_ERR "mal%d: reset timeout\n", mal->def->index);
351}
352
353int mal_get_regs_len(struct ibm_ocp_mal *mal)
354{
355 return sizeof(struct emac_ethtool_regs_subhdr) +
356 sizeof(struct ibm_mal_regs);
357}
358
359void *mal_dump_regs(struct ibm_ocp_mal *mal, void *buf)
360{
361 struct emac_ethtool_regs_subhdr *hdr = buf;
362 struct ibm_mal_regs *regs = (struct ibm_mal_regs *)(hdr + 1);
363 struct ocp_func_mal_data *maldata = mal->def->additions;
364 int i;
365
366 hdr->version = MAL_VERSION;
367 hdr->index = mal->def->index;
368
369 regs->tx_count = maldata->num_tx_chans;
370 regs->rx_count = maldata->num_rx_chans;
371
372 regs->cfg = get_mal_dcrn(mal, MAL_CFG);
373 regs->esr = get_mal_dcrn(mal, MAL_ESR);
374 regs->ier = get_mal_dcrn(mal, MAL_IER);
375 regs->tx_casr = get_mal_dcrn(mal, MAL_TXCASR);
376 regs->tx_carr = get_mal_dcrn(mal, MAL_TXCARR);
377 regs->tx_eobisr = get_mal_dcrn(mal, MAL_TXEOBISR);
378 regs->tx_deir = get_mal_dcrn(mal, MAL_TXDEIR);
379 regs->rx_casr = get_mal_dcrn(mal, MAL_RXCASR);
380 regs->rx_carr = get_mal_dcrn(mal, MAL_RXCARR);
381 regs->rx_eobisr = get_mal_dcrn(mal, MAL_RXEOBISR);
382 regs->rx_deir = get_mal_dcrn(mal, MAL_RXDEIR);
383
384 for (i = 0; i < regs->tx_count; ++i)
385 regs->tx_ctpr[i] = get_mal_dcrn(mal, MAL_TXCTPR(i));
386
387 for (i = 0; i < regs->rx_count; ++i) {
388 regs->rx_ctpr[i] = get_mal_dcrn(mal, MAL_RXCTPR(i));
389 regs->rcbs[i] = get_mal_dcrn(mal, MAL_RCBS(i));
390 }
391 return regs + 1;
392}
393
394static int __init mal_probe(struct ocp_device *ocpdev)
395{
396 struct ibm_ocp_mal *mal;
397 struct ocp_func_mal_data *maldata;
398 int err = 0, i, bd_size;
399
400 MAL_DBG("%d: probe" NL, ocpdev->def->index);
401
402 maldata = ocpdev->def->additions;
403 if (maldata == NULL) {
404 printk(KERN_ERR "mal%d: missing additional data!\n",
405 ocpdev->def->index);
406 return -ENODEV;
407 }
408
409 mal = kzalloc(sizeof(struct ibm_ocp_mal), GFP_KERNEL);
410 if (!mal) {
411 printk(KERN_ERR
412 "mal%d: out of memory allocating MAL structure!\n",
413 ocpdev->def->index);
414 return -ENOMEM;
415 }
416
417 /* XXX This only works for native dcr for now */
418 mal->dcrhost = dcr_map(NULL, maldata->dcr_base, 0);
419
420 mal->def = ocpdev->def;
421
422 INIT_LIST_HEAD(&mal->poll_list);
423 mal->napi.weight = CONFIG_IBM_EMAC_POLL_WEIGHT;
424 mal->napi.poll = mal_poll;
425
426 INIT_LIST_HEAD(&mal->list);
427
428 /* Load power-on reset defaults */
429 mal_reset(mal);
430
431 /* Set the MAL configuration register */
432 set_mal_dcrn(mal, MAL_CFG, MAL_CFG_DEFAULT | MAL_CFG_PLBB |
433 MAL_CFG_OPBBL | MAL_CFG_LEA);
434
435 mal_enable_eob_irq(mal);
436
437 /* Allocate space for BD rings */
438 BUG_ON(maldata->num_tx_chans <= 0 || maldata->num_tx_chans > 32);
439 BUG_ON(maldata->num_rx_chans <= 0 || maldata->num_rx_chans > 32);
440 bd_size = sizeof(struct mal_descriptor) *
441 (NUM_TX_BUFF * maldata->num_tx_chans +
442 NUM_RX_BUFF * maldata->num_rx_chans);
443 mal->bd_virt =
444 dma_alloc_coherent(&ocpdev->dev, bd_size, &mal->bd_dma, GFP_KERNEL);
445
446 if (!mal->bd_virt) {
447 printk(KERN_ERR
448 "mal%d: out of memory allocating RX/TX descriptors!\n",
449 mal->def->index);
450 err = -ENOMEM;
451 goto fail;
452 }
453 memset(mal->bd_virt, 0, bd_size);
454
455 for (i = 0; i < maldata->num_tx_chans; ++i)
456 set_mal_dcrn(mal, MAL_TXCTPR(i), mal->bd_dma +
457 sizeof(struct mal_descriptor) *
458 mal_tx_bd_offset(mal, i));
459
460 for (i = 0; i < maldata->num_rx_chans; ++i)
461 set_mal_dcrn(mal, MAL_RXCTPR(i), mal->bd_dma +
462 sizeof(struct mal_descriptor) *
463 mal_rx_bd_offset(mal, i));
464
465 err = request_irq(maldata->serr_irq, mal_serr, 0, "MAL SERR", mal);
466 if (err)
467 goto fail2;
468 err = request_irq(maldata->txde_irq, mal_txde, 0, "MAL TX DE", mal);
469 if (err)
470 goto fail3;
471 err = request_irq(maldata->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal);
472 if (err)
473 goto fail4;
474 err = request_irq(maldata->rxde_irq, mal_rxde, 0, "MAL RX DE", mal);
475 if (err)
476 goto fail5;
477 err = request_irq(maldata->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal);
478 if (err)
479 goto fail6;
480
481 /* Enable all MAL SERR interrupt sources */
482 set_mal_dcrn(mal, MAL_IER, MAL_IER_EVENTS);
483
484 /* Advertise this instance to the rest of the world */
485 ocp_set_drvdata(ocpdev, mal);
486
487 mal_dbg_register(mal->def->index, mal);
488
489 printk(KERN_INFO "mal%d: initialized, %d TX channels, %d RX channels\n",
490 mal->def->index, maldata->num_tx_chans, maldata->num_rx_chans);
491 return 0;
492
493 fail6:
494 free_irq(maldata->rxde_irq, mal);
495 fail5:
496 free_irq(maldata->txeob_irq, mal);
497 fail4:
498 free_irq(maldata->txde_irq, mal);
499 fail3:
500 free_irq(maldata->serr_irq, mal);
501 fail2:
502 dma_free_coherent(&ocpdev->dev, bd_size, mal->bd_virt, mal->bd_dma);
503 fail:
504 kfree(mal);
505 return err;
506}
507
508static void __exit mal_remove(struct ocp_device *ocpdev)
509{
510 struct ibm_ocp_mal *mal = ocp_get_drvdata(ocpdev);
511 struct ocp_func_mal_data *maldata = mal->def->additions;
512
513 MAL_DBG("%d: remove" NL, mal->def->index);
514
515 /* Synchronize with scheduled polling */
516 napi_disable(&mal->napi);
517
518 if (!list_empty(&mal->list)) {
519 /* This is *very* bad */
520 printk(KERN_EMERG
521 "mal%d: commac list is not empty on remove!\n",
522 mal->def->index);
523 }
524
525 ocp_set_drvdata(ocpdev, NULL);
526
527 free_irq(maldata->serr_irq, mal);
528 free_irq(maldata->txde_irq, mal);
529 free_irq(maldata->txeob_irq, mal);
530 free_irq(maldata->rxde_irq, mal);
531 free_irq(maldata->rxeob_irq, mal);
532
533 mal_reset(mal);
534
535 mal_dbg_register(mal->def->index, NULL);
536
537 dma_free_coherent(&ocpdev->dev,
538 sizeof(struct mal_descriptor) *
539 (NUM_TX_BUFF * maldata->num_tx_chans +
540 NUM_RX_BUFF * maldata->num_rx_chans), mal->bd_virt,
541 mal->bd_dma);
542
543 kfree(mal);
544}
545
546/* Structure for a device driver */
547static struct ocp_device_id mal_ids[] = {
548 { .vendor = OCP_VENDOR_IBM, .function = OCP_FUNC_MAL },
549 { .vendor = OCP_VENDOR_INVALID}
550};
551
552static struct ocp_driver mal_driver = {
553 .name = "mal",
554 .id_table = mal_ids,
555
556 .probe = mal_probe,
557 .remove = mal_remove,
558};
559
560int __init mal_init(void)
561{
562 MAL_DBG(": init" NL);
563 return ocp_register_driver(&mal_driver);
564}
565
566void __exit mal_exit(void)
567{
568 MAL_DBG(": exit" NL);
569 ocp_unregister_driver(&mal_driver);
570}
diff --git a/drivers/net/ibm_emac/ibm_emac_mal.h b/drivers/net/ibm_emac/ibm_emac_mal.h
deleted file mode 100644
index b8adbe6d4b01..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_mal.h
+++ /dev/null
@@ -1,267 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_mal.h
3 *
4 * Memory Access Layer (MAL) support
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Armin Kuster <akuster@mvista.com>
11 * Copyright 2002 MontaVista Softare Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19#ifndef __IBM_EMAC_MAL_H_
20#define __IBM_EMAC_MAL_H_
21
22#include <linux/init.h>
23#include <linux/list.h>
24#include <linux/netdevice.h>
25
26#include <asm/io.h>
27#include <asm/dcr.h>
28
29/*
30 * These MAL "versions" probably aren't the real versions IBM uses for these
31 * MAL cores, I assigned them just to make #ifdefs in this file nicer and
32 * reflect the fact that 40x and 44x have slightly different MALs. --ebs
33 */
34#if defined(CONFIG_405GP) || defined(CONFIG_405GPR) || defined(CONFIG_405EP) || \
35 defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_NP405H)
36#define MAL_VERSION 1
37#elif defined(CONFIG_440GP) || defined(CONFIG_440GX) || defined(CONFIG_440SP) || \
38 defined(CONFIG_440SPE)
39#define MAL_VERSION 2
40#else
41#error "Unknown SoC, please check chip manual and choose MAL 'version'"
42#endif
43
44/* MALx DCR registers */
45#define MAL_CFG 0x00
46#define MAL_CFG_SR 0x80000000
47#define MAL_CFG_PLBB 0x00004000
48#define MAL_CFG_OPBBL 0x00000080
49#define MAL_CFG_EOPIE 0x00000004
50#define MAL_CFG_LEA 0x00000002
51#define MAL_CFG_SD 0x00000001
52#if MAL_VERSION == 1
53#define MAL_CFG_PLBP_MASK 0x00c00000
54#define MAL_CFG_PLBP_10 0x00800000
55#define MAL_CFG_GA 0x00200000
56#define MAL_CFG_OA 0x00100000
57#define MAL_CFG_PLBLE 0x00080000
58#define MAL_CFG_PLBT_MASK 0x00078000
59#define MAL_CFG_DEFAULT (MAL_CFG_PLBP_10 | MAL_CFG_PLBT_MASK)
60#elif MAL_VERSION == 2
61#define MAL_CFG_RPP_MASK 0x00c00000
62#define MAL_CFG_RPP_10 0x00800000
63#define MAL_CFG_RMBS_MASK 0x00300000
64#define MAL_CFG_WPP_MASK 0x000c0000
65#define MAL_CFG_WPP_10 0x00080000
66#define MAL_CFG_WMBS_MASK 0x00030000
67#define MAL_CFG_PLBLE 0x00008000
68#define MAL_CFG_DEFAULT (MAL_CFG_RMBS_MASK | MAL_CFG_WMBS_MASK | \
69 MAL_CFG_RPP_10 | MAL_CFG_WPP_10)
70#else
71#error "Unknown MAL version"
72#endif
73
74#define MAL_ESR 0x01
75#define MAL_ESR_EVB 0x80000000
76#define MAL_ESR_CIDT 0x40000000
77#define MAL_ESR_CID_MASK 0x3e000000
78#define MAL_ESR_CID_SHIFT 25
79#define MAL_ESR_DE 0x00100000
80#define MAL_ESR_OTE 0x00040000
81#define MAL_ESR_OSE 0x00020000
82#define MAL_ESR_PEIN 0x00010000
83#define MAL_ESR_DEI 0x00000010
84#define MAL_ESR_OTEI 0x00000004
85#define MAL_ESR_OSEI 0x00000002
86#define MAL_ESR_PBEI 0x00000001
87#if MAL_VERSION == 1
88#define MAL_ESR_ONE 0x00080000
89#define MAL_ESR_ONEI 0x00000008
90#elif MAL_VERSION == 2
91#define MAL_ESR_PTE 0x00800000
92#define MAL_ESR_PRE 0x00400000
93#define MAL_ESR_PWE 0x00200000
94#define MAL_ESR_PTEI 0x00000080
95#define MAL_ESR_PREI 0x00000040
96#define MAL_ESR_PWEI 0x00000020
97#else
98#error "Unknown MAL version"
99#endif
100
101#define MAL_IER 0x02
102#define MAL_IER_DE 0x00000010
103#define MAL_IER_OTE 0x00000004
104#define MAL_IER_OE 0x00000002
105#define MAL_IER_PE 0x00000001
106#if MAL_VERSION == 1
107#define MAL_IER_NWE 0x00000008
108#define MAL_IER_SOC_EVENTS MAL_IER_NWE
109#elif MAL_VERSION == 2
110#define MAL_IER_PT 0x00000080
111#define MAL_IER_PRE 0x00000040
112#define MAL_IER_PWE 0x00000020
113#define MAL_IER_SOC_EVENTS (MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE)
114#else
115#error "Unknown MAL version"
116#endif
117#define MAL_IER_EVENTS (MAL_IER_SOC_EVENTS | MAL_IER_OTE | \
118 MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE)
119
120#define MAL_TXCASR 0x04
121#define MAL_TXCARR 0x05
122#define MAL_TXEOBISR 0x06
123#define MAL_TXDEIR 0x07
124#define MAL_RXCASR 0x10
125#define MAL_RXCARR 0x11
126#define MAL_RXEOBISR 0x12
127#define MAL_RXDEIR 0x13
128#define MAL_TXCTPR(n) ((n) + 0x20)
129#define MAL_RXCTPR(n) ((n) + 0x40)
130#define MAL_RCBS(n) ((n) + 0x60)
131
132/* In reality MAL can handle TX buffers up to 4095 bytes long,
133 * but this isn't a good round number :) --ebs
134 */
135#define MAL_MAX_TX_SIZE 4080
136#define MAL_MAX_RX_SIZE 4080
137
138static inline int mal_rx_size(int len)
139{
140 len = (len + 0xf) & ~0xf;
141 return len > MAL_MAX_RX_SIZE ? MAL_MAX_RX_SIZE : len;
142}
143
144static inline int mal_tx_chunks(int len)
145{
146 return (len + MAL_MAX_TX_SIZE - 1) / MAL_MAX_TX_SIZE;
147}
148
149#define MAL_CHAN_MASK(n) (0x80000000 >> (n))
150
151/* MAL Buffer Descriptor structure */
152struct mal_descriptor {
153 u16 ctrl; /* MAL / Commac status control bits */
154 u16 data_len; /* Max length is 4K-1 (12 bits) */
155 u32 data_ptr; /* pointer to actual data buffer */
156};
157
158/* the following defines are for the MadMAL status and control registers. */
159/* MADMAL transmit and receive status/control bits */
160#define MAL_RX_CTRL_EMPTY 0x8000
161#define MAL_RX_CTRL_WRAP 0x4000
162#define MAL_RX_CTRL_CM 0x2000
163#define MAL_RX_CTRL_LAST 0x1000
164#define MAL_RX_CTRL_FIRST 0x0800
165#define MAL_RX_CTRL_INTR 0x0400
166#define MAL_RX_CTRL_SINGLE (MAL_RX_CTRL_LAST | MAL_RX_CTRL_FIRST)
167#define MAL_IS_SINGLE_RX(ctrl) (((ctrl) & MAL_RX_CTRL_SINGLE) == MAL_RX_CTRL_SINGLE)
168
169#define MAL_TX_CTRL_READY 0x8000
170#define MAL_TX_CTRL_WRAP 0x4000
171#define MAL_TX_CTRL_CM 0x2000
172#define MAL_TX_CTRL_LAST 0x1000
173#define MAL_TX_CTRL_INTR 0x0400
174
175struct mal_commac_ops {
176 void (*poll_tx) (void *dev);
177 int (*poll_rx) (void *dev, int budget);
178 int (*peek_rx) (void *dev);
179 void (*rxde) (void *dev);
180};
181
182struct mal_commac {
183 struct mal_commac_ops *ops;
184 void *dev;
185 struct list_head poll_list;
186 int rx_stopped;
187
188 u32 tx_chan_mask;
189 u32 rx_chan_mask;
190 struct list_head list;
191};
192
193struct ibm_ocp_mal {
194 dcr_host_t dcrhost;
195
196 struct list_head poll_list;
197 struct napi_struct napi;
198
199 struct list_head list;
200 u32 tx_chan_mask;
201 u32 rx_chan_mask;
202
203 dma_addr_t bd_dma;
204 struct mal_descriptor *bd_virt;
205
206 struct ocp_def *def;
207};
208
209static inline u32 get_mal_dcrn(struct ibm_ocp_mal *mal, int reg)
210{
211 return dcr_read(mal->dcrhost, reg);
212}
213
214static inline void set_mal_dcrn(struct ibm_ocp_mal *mal, int reg, u32 val)
215{
216 dcr_write(mal->dcrhost, reg, val);
217}
218
219/* Register MAL devices */
220int mal_init(void) __init;
221void mal_exit(void) __exit;
222
223int mal_register_commac(struct ibm_ocp_mal *mal,
224 struct mal_commac *commac) __init;
225void mal_unregister_commac(struct ibm_ocp_mal *mal, struct mal_commac *commac);
226int mal_set_rcbs(struct ibm_ocp_mal *mal, int channel, unsigned long size);
227
228/* Returns BD ring offset for a particular channel
229 (in 'struct mal_descriptor' elements)
230*/
231int mal_tx_bd_offset(struct ibm_ocp_mal *mal, int channel);
232int mal_rx_bd_offset(struct ibm_ocp_mal *mal, int channel);
233
234void mal_enable_tx_channel(struct ibm_ocp_mal *mal, int channel);
235void mal_disable_tx_channel(struct ibm_ocp_mal *mal, int channel);
236void mal_enable_rx_channel(struct ibm_ocp_mal *mal, int channel);
237void mal_disable_rx_channel(struct ibm_ocp_mal *mal, int channel);
238
239/* Add/remove EMAC to/from MAL polling list */
240void mal_poll_add(struct ibm_ocp_mal *mal, struct mal_commac *commac);
241void mal_poll_del(struct ibm_ocp_mal *mal, struct mal_commac *commac);
242
243/* Ethtool MAL registers */
244struct ibm_mal_regs {
245 u32 tx_count;
246 u32 rx_count;
247
248 u32 cfg;
249 u32 esr;
250 u32 ier;
251 u32 tx_casr;
252 u32 tx_carr;
253 u32 tx_eobisr;
254 u32 tx_deir;
255 u32 rx_casr;
256 u32 rx_carr;
257 u32 rx_eobisr;
258 u32 rx_deir;
259 u32 tx_ctpr[32];
260 u32 rx_ctpr[32];
261 u32 rcbs[32];
262};
263
264int mal_get_regs_len(struct ibm_ocp_mal *mal);
265void *mal_dump_regs(struct ibm_ocp_mal *mal, void *buf);
266
267#endif /* __IBM_EMAC_MAL_H_ */
diff --git a/drivers/net/ibm_emac/ibm_emac_phy.c b/drivers/net/ibm_emac/ibm_emac_phy.c
deleted file mode 100644
index e57862b34cae..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_phy.c
+++ /dev/null
@@ -1,398 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_phy.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, PHY support.
5 * Borrowed from sungem_phy.c, though I only kept the generic MII
6 * driver for now.
7 *
8 * This file should be shared with other drivers or eventually
9 * merged as the "low level" part of miilib
10 *
11 * (c) 2003, Benjamin Herrenscmidt (benh@kernel.crashing.org)
12 * (c) 2004-2005, Eugene Surovegin <ebs@ebshome.net>
13 *
14 */
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/netdevice.h>
19#include <linux/mii.h>
20#include <linux/ethtool.h>
21#include <linux/delay.h>
22
23#include <asm/ocp.h>
24
25#include "ibm_emac_core.h"
26#include "ibm_emac_phy.h"
27
28static inline int phy_read(struct mii_phy *phy, int reg)
29{
30 return phy->mdio_read(phy->dev, phy->address, reg);
31}
32
33static inline void phy_write(struct mii_phy *phy, int reg, int val)
34{
35 phy->mdio_write(phy->dev, phy->address, reg, val);
36}
37
38/*
39 * polls MII_BMCR until BMCR_RESET bit clears or operation times out.
40 *
41 * returns:
42 * >= 0 => success, value in BMCR returned to caller
43 * -EBUSY => failure, RESET bit never cleared
44 * otherwise => failure, lower level PHY read failed
45 */
46static int mii_spin_reset_complete(struct mii_phy *phy)
47{
48 int val;
49 int limit = 10000;
50
51 while (limit--) {
52 val = phy_read(phy, MII_BMCR);
53 if (val >= 0 && !(val & BMCR_RESET))
54 return val; /* success */
55 udelay(10);
56 }
57 if (val & BMCR_RESET)
58 val = -EBUSY;
59
60 if (net_ratelimit())
61 printk(KERN_ERR "emac%d: PHY reset timeout (%d)\n",
62 ((struct ocp_enet_private *)phy->dev->priv)->def->index,
63 val);
64 return val;
65}
66
67int mii_reset_phy(struct mii_phy *phy)
68{
69 int val;
70
71 val = phy_read(phy, MII_BMCR);
72 val &= ~BMCR_ISOLATE;
73 val |= BMCR_RESET;
74 phy_write(phy, MII_BMCR, val);
75
76 udelay(300);
77
78 val = mii_spin_reset_complete(phy);
79 if (val >= 0 && (val & BMCR_ISOLATE))
80 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE);
81
82 return val < 0;
83}
84
85static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
86{
87 int ctl, adv;
88
89 phy->autoneg = AUTONEG_ENABLE;
90 phy->speed = SPEED_10;
91 phy->duplex = DUPLEX_HALF;
92 phy->pause = phy->asym_pause = 0;
93 phy->advertising = advertise;
94
95 /* Setup standard advertise */
96 adv = phy_read(phy, MII_ADVERTISE);
97 if (adv < 0)
98 return adv;
99 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP |
100 ADVERTISE_PAUSE_ASYM);
101 if (advertise & ADVERTISED_10baseT_Half)
102 adv |= ADVERTISE_10HALF;
103 if (advertise & ADVERTISED_10baseT_Full)
104 adv |= ADVERTISE_10FULL;
105 if (advertise & ADVERTISED_100baseT_Half)
106 adv |= ADVERTISE_100HALF;
107 if (advertise & ADVERTISED_100baseT_Full)
108 adv |= ADVERTISE_100FULL;
109 if (advertise & ADVERTISED_Pause)
110 adv |= ADVERTISE_PAUSE_CAP;
111 if (advertise & ADVERTISED_Asym_Pause)
112 adv |= ADVERTISE_PAUSE_ASYM;
113 phy_write(phy, MII_ADVERTISE, adv);
114
115 if (phy->features &
116 (SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half)) {
117 adv = phy_read(phy, MII_CTRL1000);
118 if (adv < 0)
119 return adv;
120 adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
121 if (advertise & ADVERTISED_1000baseT_Full)
122 adv |= ADVERTISE_1000FULL;
123 if (advertise & ADVERTISED_1000baseT_Half)
124 adv |= ADVERTISE_1000HALF;
125 phy_write(phy, MII_CTRL1000, adv);
126 }
127
128 /* Start/Restart aneg */
129 /* on some PHYs (e.g. National DP83843) a write to MII_ADVERTISE
130 * causes BMCR_RESET to be set on the next read of MII_BMCR, which
131 * if not checked for causes the PHY to be reset below */
132 ctl = mii_spin_reset_complete(phy);
133 if (ctl < 0)
134 return ctl;
135
136 ctl |= BMCR_ANENABLE | BMCR_ANRESTART;
137 phy_write(phy, MII_BMCR, ctl);
138
139 return 0;
140}
141
142static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
143{
144 int ctl;
145
146 phy->autoneg = AUTONEG_DISABLE;
147 phy->speed = speed;
148 phy->duplex = fd;
149 phy->pause = phy->asym_pause = 0;
150
151 /* First reset the PHY */
152 mii_reset_phy(phy);
153
154 ctl = phy_read(phy, MII_BMCR);
155 if (ctl < 0)
156 return ctl;
157 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_ANENABLE | BMCR_SPEED1000);
158
159 /* Select speed & duplex */
160 switch (speed) {
161 case SPEED_10:
162 break;
163 case SPEED_100:
164 ctl |= BMCR_SPEED100;
165 break;
166 case SPEED_1000:
167 ctl |= BMCR_SPEED1000;
168 break;
169 default:
170 return -EINVAL;
171 }
172 if (fd == DUPLEX_FULL)
173 ctl |= BMCR_FULLDPLX;
174 phy_write(phy, MII_BMCR, ctl);
175
176 return 0;
177}
178
179static int genmii_poll_link(struct mii_phy *phy)
180{
181 int status;
182
183 /* Clear latched value with dummy read */
184 phy_read(phy, MII_BMSR);
185 status = phy_read(phy, MII_BMSR);
186 if (status < 0 || (status & BMSR_LSTATUS) == 0)
187 return 0;
188 if (phy->autoneg == AUTONEG_ENABLE && !(status & BMSR_ANEGCOMPLETE))
189 return 0;
190 return 1;
191}
192
193static int genmii_read_link(struct mii_phy *phy)
194{
195 if (phy->autoneg == AUTONEG_ENABLE) {
196 int glpa = 0;
197 int lpa = phy_read(phy, MII_LPA) & phy_read(phy, MII_ADVERTISE);
198 if (lpa < 0)
199 return lpa;
200
201 if (phy->features &
202 (SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half)) {
203 int adv = phy_read(phy, MII_CTRL1000);
204 glpa = phy_read(phy, MII_STAT1000);
205
206 if (glpa < 0 || adv < 0)
207 return adv;
208
209 glpa &= adv << 2;
210 }
211
212 phy->speed = SPEED_10;
213 phy->duplex = DUPLEX_HALF;
214 phy->pause = phy->asym_pause = 0;
215
216 if (glpa & (LPA_1000FULL | LPA_1000HALF)) {
217 phy->speed = SPEED_1000;
218 if (glpa & LPA_1000FULL)
219 phy->duplex = DUPLEX_FULL;
220 } else if (lpa & (LPA_100FULL | LPA_100HALF)) {
221 phy->speed = SPEED_100;
222 if (lpa & LPA_100FULL)
223 phy->duplex = DUPLEX_FULL;
224 } else if (lpa & LPA_10FULL)
225 phy->duplex = DUPLEX_FULL;
226
227 if (phy->duplex == DUPLEX_FULL) {
228 phy->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
229 phy->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
230 }
231 } else {
232 int bmcr = phy_read(phy, MII_BMCR);
233 if (bmcr < 0)
234 return bmcr;
235
236 if (bmcr & BMCR_FULLDPLX)
237 phy->duplex = DUPLEX_FULL;
238 else
239 phy->duplex = DUPLEX_HALF;
240 if (bmcr & BMCR_SPEED1000)
241 phy->speed = SPEED_1000;
242 else if (bmcr & BMCR_SPEED100)
243 phy->speed = SPEED_100;
244 else
245 phy->speed = SPEED_10;
246
247 phy->pause = phy->asym_pause = 0;
248 }
249 return 0;
250}
251
252/* Generic implementation for most 10/100/1000 PHYs */
253static struct mii_phy_ops generic_phy_ops = {
254 .setup_aneg = genmii_setup_aneg,
255 .setup_forced = genmii_setup_forced,
256 .poll_link = genmii_poll_link,
257 .read_link = genmii_read_link
258};
259
260static struct mii_phy_def genmii_phy_def = {
261 .phy_id = 0x00000000,
262 .phy_id_mask = 0x00000000,
263 .name = "Generic MII",
264 .ops = &generic_phy_ops
265};
266
267/* CIS8201 */
268#define MII_CIS8201_10BTCSR 0x16
269#define TENBTCSR_ECHO_DISABLE 0x2000
270#define MII_CIS8201_EPCR 0x17
271#define EPCR_MODE_MASK 0x3000
272#define EPCR_GMII_MODE 0x0000
273#define EPCR_RGMII_MODE 0x1000
274#define EPCR_TBI_MODE 0x2000
275#define EPCR_RTBI_MODE 0x3000
276#define MII_CIS8201_ACSR 0x1c
277#define ACSR_PIN_PRIO_SELECT 0x0004
278
279static int cis8201_init(struct mii_phy *phy)
280{
281 int epcr;
282
283 epcr = phy_read(phy, MII_CIS8201_EPCR);
284 if (epcr < 0)
285 return epcr;
286
287 epcr &= ~EPCR_MODE_MASK;
288
289 switch (phy->mode) {
290 case PHY_MODE_TBI:
291 epcr |= EPCR_TBI_MODE;
292 break;
293 case PHY_MODE_RTBI:
294 epcr |= EPCR_RTBI_MODE;
295 break;
296 case PHY_MODE_GMII:
297 epcr |= EPCR_GMII_MODE;
298 break;
299 case PHY_MODE_RGMII:
300 default:
301 epcr |= EPCR_RGMII_MODE;
302 }
303
304 phy_write(phy, MII_CIS8201_EPCR, epcr);
305
306 /* MII regs override strap pins */
307 phy_write(phy, MII_CIS8201_ACSR,
308 phy_read(phy, MII_CIS8201_ACSR) | ACSR_PIN_PRIO_SELECT);
309
310 /* Disable TX_EN -> CRS echo mode, otherwise 10/HDX doesn't work */
311 phy_write(phy, MII_CIS8201_10BTCSR,
312 phy_read(phy, MII_CIS8201_10BTCSR) | TENBTCSR_ECHO_DISABLE);
313
314 return 0;
315}
316
317static struct mii_phy_ops cis8201_phy_ops = {
318 .init = cis8201_init,
319 .setup_aneg = genmii_setup_aneg,
320 .setup_forced = genmii_setup_forced,
321 .poll_link = genmii_poll_link,
322 .read_link = genmii_read_link
323};
324
325static struct mii_phy_def cis8201_phy_def = {
326 .phy_id = 0x000fc410,
327 .phy_id_mask = 0x000ffff0,
328 .name = "CIS8201 Gigabit Ethernet",
329 .ops = &cis8201_phy_ops
330};
331
332static struct mii_phy_def *mii_phy_table[] = {
333 &cis8201_phy_def,
334 &genmii_phy_def,
335 NULL
336};
337
338int mii_phy_probe(struct mii_phy *phy, int address)
339{
340 struct mii_phy_def *def;
341 int i;
342 int id;
343
344 phy->autoneg = AUTONEG_DISABLE;
345 phy->advertising = 0;
346 phy->address = address;
347 phy->speed = SPEED_10;
348 phy->duplex = DUPLEX_HALF;
349 phy->pause = phy->asym_pause = 0;
350
351 /* Take PHY out of isolate mode and reset it. */
352 if (mii_reset_phy(phy))
353 return -ENODEV;
354
355 /* Read ID and find matching entry */
356 id = (phy_read(phy, MII_PHYSID1) << 16) | phy_read(phy, MII_PHYSID2);
357 if (id < 0)
358 return -ENODEV;
359 for (i = 0; (def = mii_phy_table[i]) != NULL; i++)
360 if ((id & def->phy_id_mask) == def->phy_id)
361 break;
362 /* Should never be NULL (we have a generic entry), but... */
363 if (!def)
364 return -ENODEV;
365
366 phy->def = def;
367
368 /* Determine PHY features if needed */
369 phy->features = def->features;
370 if (!phy->features) {
371 u16 bmsr = phy_read(phy, MII_BMSR);
372 if (bmsr & BMSR_ANEGCAPABLE)
373 phy->features |= SUPPORTED_Autoneg;
374 if (bmsr & BMSR_10HALF)
375 phy->features |= SUPPORTED_10baseT_Half;
376 if (bmsr & BMSR_10FULL)
377 phy->features |= SUPPORTED_10baseT_Full;
378 if (bmsr & BMSR_100HALF)
379 phy->features |= SUPPORTED_100baseT_Half;
380 if (bmsr & BMSR_100FULL)
381 phy->features |= SUPPORTED_100baseT_Full;
382 if (bmsr & BMSR_ESTATEN) {
383 u16 esr = phy_read(phy, MII_ESTATUS);
384 if (esr & ESTATUS_1000_TFULL)
385 phy->features |= SUPPORTED_1000baseT_Full;
386 if (esr & ESTATUS_1000_THALF)
387 phy->features |= SUPPORTED_1000baseT_Half;
388 }
389 phy->features |= SUPPORTED_MII;
390 }
391
392 /* Setup default advertising */
393 phy->advertising = phy->features;
394
395 return 0;
396}
397
398MODULE_LICENSE("GPL");
diff --git a/drivers/net/ibm_emac/ibm_emac_phy.h b/drivers/net/ibm_emac/ibm_emac_phy.h
deleted file mode 100644
index a70e0fea54c4..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_phy.h
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_phy.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, PHY support
5 *
6 * Benjamin Herrenschmidt <benh@kernel.crashing.org>
7 * February 2003
8 *
9 * Minor additions by Eugene Surovegin <ebs@ebshome.net>, 2004
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * This file basically duplicates sungem_phy.{c,h} with different PHYs
17 * supported. I'm looking into merging that in a single mii layer more
18 * flexible than mii.c
19 */
20
21#ifndef _IBM_OCP_PHY_H_
22#define _IBM_OCP_PHY_H_
23
24struct mii_phy;
25
26/* Operations supported by any kind of PHY */
27struct mii_phy_ops {
28 int (*init) (struct mii_phy * phy);
29 int (*suspend) (struct mii_phy * phy, int wol_options);
30 int (*setup_aneg) (struct mii_phy * phy, u32 advertise);
31 int (*setup_forced) (struct mii_phy * phy, int speed, int fd);
32 int (*poll_link) (struct mii_phy * phy);
33 int (*read_link) (struct mii_phy * phy);
34};
35
36/* Structure used to statically define an mii/gii based PHY */
37struct mii_phy_def {
38 u32 phy_id; /* Concatenated ID1 << 16 | ID2 */
39 u32 phy_id_mask; /* Significant bits */
40 u32 features; /* Ethtool SUPPORTED_* defines or
41 0 for autodetect */
42 int magic_aneg; /* Autoneg does all speed test for us */
43 const char *name;
44 const struct mii_phy_ops *ops;
45};
46
47/* An instance of a PHY, partially borrowed from mii_if_info */
48struct mii_phy {
49 struct mii_phy_def *def;
50 u32 advertising; /* Ethtool ADVERTISED_* defines */
51 u32 features; /* Copied from mii_phy_def.features
52 or determined automaticaly */
53 int address; /* PHY address */
54 int mode; /* PHY mode */
55
56 /* 1: autoneg enabled, 0: disabled */
57 int autoneg;
58
59 /* forced speed & duplex (no autoneg)
60 * partner speed & duplex & pause (autoneg)
61 */
62 int speed;
63 int duplex;
64 int pause;
65 int asym_pause;
66
67 /* Provided by host chip */
68 struct net_device *dev;
69 int (*mdio_read) (struct net_device * dev, int addr, int reg);
70 void (*mdio_write) (struct net_device * dev, int addr, int reg,
71 int val);
72};
73
74/* Pass in a struct mii_phy with dev, mdio_read and mdio_write
75 * filled, the remaining fields will be filled on return
76 */
77int mii_phy_probe(struct mii_phy *phy, int address);
78int mii_reset_phy(struct mii_phy *phy);
79
80#endif /* _IBM_OCP_PHY_H_ */
diff --git a/drivers/net/ibm_emac/ibm_emac_rgmii.c b/drivers/net/ibm_emac/ibm_emac_rgmii.c
deleted file mode 100644
index 9dbb5e5936c3..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_rgmii.c
+++ /dev/null
@@ -1,200 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_rgmii.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, RGMII bridge support.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Matt Porter <mporter@kernel.crashing.org>
11 * Copyright 2004 MontaVista Software, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19#include <linux/kernel.h>
20#include <linux/ethtool.h>
21#include <asm/io.h>
22
23#include "ibm_emac_core.h"
24#include "ibm_emac_debug.h"
25
26/* RGMIIx_FER */
27#define RGMII_FER_MASK(idx) (0x7 << ((idx) * 4))
28#define RGMII_FER_RTBI(idx) (0x4 << ((idx) * 4))
29#define RGMII_FER_RGMII(idx) (0x5 << ((idx) * 4))
30#define RGMII_FER_TBI(idx) (0x6 << ((idx) * 4))
31#define RGMII_FER_GMII(idx) (0x7 << ((idx) * 4))
32
33/* RGMIIx_SSR */
34#define RGMII_SSR_MASK(idx) (0x7 << ((idx) * 8))
35#define RGMII_SSR_100(idx) (0x2 << ((idx) * 8))
36#define RGMII_SSR_1000(idx) (0x4 << ((idx) * 8))
37
38/* RGMII bridge supports only GMII/TBI and RGMII/RTBI PHYs */
39static inline int rgmii_valid_mode(int phy_mode)
40{
41 return phy_mode == PHY_MODE_GMII ||
42 phy_mode == PHY_MODE_RGMII ||
43 phy_mode == PHY_MODE_TBI ||
44 phy_mode == PHY_MODE_RTBI;
45}
46
47static inline const char *rgmii_mode_name(int mode)
48{
49 switch (mode) {
50 case PHY_MODE_RGMII:
51 return "RGMII";
52 case PHY_MODE_TBI:
53 return "TBI";
54 case PHY_MODE_GMII:
55 return "GMII";
56 case PHY_MODE_RTBI:
57 return "RTBI";
58 default:
59 BUG();
60 }
61}
62
63static inline u32 rgmii_mode_mask(int mode, int input)
64{
65 switch (mode) {
66 case PHY_MODE_RGMII:
67 return RGMII_FER_RGMII(input);
68 case PHY_MODE_TBI:
69 return RGMII_FER_TBI(input);
70 case PHY_MODE_GMII:
71 return RGMII_FER_GMII(input);
72 case PHY_MODE_RTBI:
73 return RGMII_FER_RTBI(input);
74 default:
75 BUG();
76 }
77}
78
79static int __init rgmii_init(struct ocp_device *ocpdev, int input, int mode)
80{
81 struct ibm_ocp_rgmii *dev = ocp_get_drvdata(ocpdev);
82 struct rgmii_regs *p;
83
84 RGMII_DBG("%d: init(%d, %d)" NL, ocpdev->def->index, input, mode);
85
86 if (!dev) {
87 dev = kzalloc(sizeof(struct ibm_ocp_rgmii), GFP_KERNEL);
88 if (!dev) {
89 printk(KERN_ERR
90 "rgmii%d: couldn't allocate device structure!\n",
91 ocpdev->def->index);
92 return -ENOMEM;
93 }
94
95 p = (struct rgmii_regs *)ioremap(ocpdev->def->paddr,
96 sizeof(struct rgmii_regs));
97 if (!p) {
98 printk(KERN_ERR
99 "rgmii%d: could not ioremap device registers!\n",
100 ocpdev->def->index);
101 kfree(dev);
102 return -ENOMEM;
103 }
104
105 dev->base = p;
106 ocp_set_drvdata(ocpdev, dev);
107
108 /* Disable all inputs by default */
109 out_be32(&p->fer, 0);
110 } else
111 p = dev->base;
112
113 /* Enable this input */
114 out_be32(&p->fer, in_be32(&p->fer) | rgmii_mode_mask(mode, input));
115
116 printk(KERN_NOTICE "rgmii%d: input %d in %s mode\n",
117 ocpdev->def->index, input, rgmii_mode_name(mode));
118
119 ++dev->users;
120 return 0;
121}
122
123int __init rgmii_attach(void *emac)
124{
125 struct ocp_enet_private *dev = emac;
126 struct ocp_func_emac_data *emacdata = dev->def->additions;
127
128 /* Check if we need to attach to a RGMII */
129 if (emacdata->rgmii_idx >= 0 && rgmii_valid_mode(emacdata->phy_mode)) {
130 dev->rgmii_input = emacdata->rgmii_mux;
131 dev->rgmii_dev =
132 ocp_find_device(OCP_VENDOR_IBM, OCP_FUNC_RGMII,
133 emacdata->rgmii_idx);
134 if (!dev->rgmii_dev) {
135 printk(KERN_ERR "emac%d: unknown rgmii%d!\n",
136 dev->def->index, emacdata->rgmii_idx);
137 return -ENODEV;
138 }
139 if (rgmii_init
140 (dev->rgmii_dev, dev->rgmii_input, emacdata->phy_mode)) {
141 printk(KERN_ERR
142 "emac%d: rgmii%d initialization failed!\n",
143 dev->def->index, emacdata->rgmii_idx);
144 return -ENODEV;
145 }
146 }
147 return 0;
148}
149
150void rgmii_set_speed(struct ocp_device *ocpdev, int input, int speed)
151{
152 struct ibm_ocp_rgmii *dev = ocp_get_drvdata(ocpdev);
153 u32 ssr = in_be32(&dev->base->ssr) & ~RGMII_SSR_MASK(input);
154
155 RGMII_DBG("%d: speed(%d, %d)" NL, ocpdev->def->index, input, speed);
156
157 if (speed == SPEED_1000)
158 ssr |= RGMII_SSR_1000(input);
159 else if (speed == SPEED_100)
160 ssr |= RGMII_SSR_100(input);
161
162 out_be32(&dev->base->ssr, ssr);
163}
164
165void __rgmii_fini(struct ocp_device *ocpdev, int input)
166{
167 struct ibm_ocp_rgmii *dev = ocp_get_drvdata(ocpdev);
168 BUG_ON(!dev || dev->users == 0);
169
170 RGMII_DBG("%d: fini(%d)" NL, ocpdev->def->index, input);
171
172 /* Disable this input */
173 out_be32(&dev->base->fer,
174 in_be32(&dev->base->fer) & ~RGMII_FER_MASK(input));
175
176 if (!--dev->users) {
177 /* Free everything if this is the last user */
178 ocp_set_drvdata(ocpdev, NULL);
179 iounmap((void *)dev->base);
180 kfree(dev);
181 }
182}
183
184int __rgmii_get_regs_len(struct ocp_device *ocpdev)
185{
186 return sizeof(struct emac_ethtool_regs_subhdr) +
187 sizeof(struct rgmii_regs);
188}
189
190void *rgmii_dump_regs(struct ocp_device *ocpdev, void *buf)
191{
192 struct ibm_ocp_rgmii *dev = ocp_get_drvdata(ocpdev);
193 struct emac_ethtool_regs_subhdr *hdr = buf;
194 struct rgmii_regs *regs = (struct rgmii_regs *)(hdr + 1);
195
196 hdr->version = 0;
197 hdr->index = ocpdev->def->index;
198 memcpy_fromio(regs, dev->base, sizeof(struct rgmii_regs));
199 return regs + 1;
200}
diff --git a/drivers/net/ibm_emac/ibm_emac_rgmii.h b/drivers/net/ibm_emac/ibm_emac_rgmii.h
deleted file mode 100644
index 971e45815c6c..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_rgmii.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_rgmii.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, RGMII bridge support.
5 *
6 * Based on ocp_zmii.h/ibm_emac_zmii.h
7 * Armin Kuster akuster@mvista.com
8 *
9 * Copyright 2004 MontaVista Software, Inc.
10 * Matt Porter <mporter@kernel.crashing.org>
11 *
12 * Copyright (c) 2004, 2005 Zultys Technologies.
13 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21#ifndef _IBM_EMAC_RGMII_H_
22#define _IBM_EMAC_RGMII_H_
23
24
25/* RGMII bridge */
26struct rgmii_regs {
27 u32 fer; /* Function enable register */
28 u32 ssr; /* Speed select register */
29};
30
31/* RGMII device */
32struct ibm_ocp_rgmii {
33 struct rgmii_regs __iomem *base;
34 int users; /* number of EMACs using this RGMII bridge */
35};
36
37#ifdef CONFIG_IBM_EMAC_RGMII
38int rgmii_attach(void *emac) __init;
39
40void __rgmii_fini(struct ocp_device *ocpdev, int input);
41static inline void rgmii_fini(struct ocp_device *ocpdev, int input)
42{
43 if (ocpdev)
44 __rgmii_fini(ocpdev, input);
45}
46
47void rgmii_set_speed(struct ocp_device *ocpdev, int input, int speed);
48
49int __rgmii_get_regs_len(struct ocp_device *ocpdev);
50static inline int rgmii_get_regs_len(struct ocp_device *ocpdev)
51{
52 return ocpdev ? __rgmii_get_regs_len(ocpdev) : 0;
53}
54
55void *rgmii_dump_regs(struct ocp_device *ocpdev, void *buf);
56#else
57# define rgmii_attach(x) 0
58# define rgmii_fini(x,y) ((void)0)
59# define rgmii_set_speed(x,y,z) ((void)0)
60# define rgmii_get_regs_len(x) 0
61# define rgmii_dump_regs(x,buf) (buf)
62#endif /* !CONFIG_IBM_EMAC_RGMII */
63
64#endif /* _IBM_EMAC_RGMII_H_ */
diff --git a/drivers/net/ibm_emac/ibm_emac_tah.c b/drivers/net/ibm_emac/ibm_emac_tah.c
deleted file mode 100644
index 3c2d5ba522a1..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_tah.c
+++ /dev/null
@@ -1,110 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_tah.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, TAH support.
5 *
6 * Copyright 2004 MontaVista Software, Inc.
7 * Matt Porter <mporter@kernel.crashing.org>
8 *
9 * Copyright (c) 2005 Eugene Surovegin <ebs@ebshome.net>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16#include <asm/io.h>
17
18#include "ibm_emac_core.h"
19
20static int __init tah_init(struct ocp_device *ocpdev)
21{
22 struct tah_regs *p;
23
24 if (ocp_get_drvdata(ocpdev)) {
25 printk(KERN_ERR "tah%d: already in use!\n", ocpdev->def->index);
26 return -EBUSY;
27 }
28
29 /* Initialize TAH and enable IPv4 checksum verification, no TSO yet */
30 p = (struct tah_regs *)ioremap(ocpdev->def->paddr, sizeof(*p));
31 if (!p) {
32 printk(KERN_ERR "tah%d: could not ioremap device registers!\n",
33 ocpdev->def->index);
34 return -ENOMEM;
35 }
36 ocp_set_drvdata(ocpdev, p);
37 __tah_reset(ocpdev);
38
39 return 0;
40}
41
42int __init tah_attach(void *emac)
43{
44 struct ocp_enet_private *dev = emac;
45 struct ocp_func_emac_data *emacdata = dev->def->additions;
46
47 /* Check if we need to attach to a TAH */
48 if (emacdata->tah_idx >= 0) {
49 dev->tah_dev = ocp_find_device(OCP_ANY_ID, OCP_FUNC_TAH,
50 emacdata->tah_idx);
51 if (!dev->tah_dev) {
52 printk(KERN_ERR "emac%d: unknown tah%d!\n",
53 dev->def->index, emacdata->tah_idx);
54 return -ENODEV;
55 }
56 if (tah_init(dev->tah_dev)) {
57 printk(KERN_ERR
58 "emac%d: tah%d initialization failed!\n",
59 dev->def->index, emacdata->tah_idx);
60 return -ENODEV;
61 }
62 }
63 return 0;
64}
65
66void __tah_fini(struct ocp_device *ocpdev)
67{
68 struct tah_regs *p = ocp_get_drvdata(ocpdev);
69 BUG_ON(!p);
70 ocp_set_drvdata(ocpdev, NULL);
71 iounmap((void *)p);
72}
73
74void __tah_reset(struct ocp_device *ocpdev)
75{
76 struct tah_regs *p = ocp_get_drvdata(ocpdev);
77 int n;
78
79 /* Reset TAH */
80 out_be32(&p->mr, TAH_MR_SR);
81 n = 100;
82 while ((in_be32(&p->mr) & TAH_MR_SR) && n)
83 --n;
84
85 if (unlikely(!n))
86 printk(KERN_ERR "tah%d: reset timeout\n", ocpdev->def->index);
87
88 /* 10KB TAH TX FIFO accomodates the max MTU of 9000 */
89 out_be32(&p->mr,
90 TAH_MR_CVR | TAH_MR_ST_768 | TAH_MR_TFS_10KB | TAH_MR_DTFP |
91 TAH_MR_DIG);
92}
93
94int __tah_get_regs_len(struct ocp_device *ocpdev)
95{
96 return sizeof(struct emac_ethtool_regs_subhdr) +
97 sizeof(struct tah_regs);
98}
99
100void *tah_dump_regs(struct ocp_device *ocpdev, void *buf)
101{
102 struct tah_regs *dev = ocp_get_drvdata(ocpdev);
103 struct emac_ethtool_regs_subhdr *hdr = buf;
104 struct tah_regs *regs = (struct tah_regs *)(hdr + 1);
105
106 hdr->version = 0;
107 hdr->index = ocpdev->def->index;
108 memcpy_fromio(regs, dev, sizeof(struct tah_regs));
109 return regs + 1;
110}
diff --git a/drivers/net/ibm_emac/ibm_emac_tah.h b/drivers/net/ibm_emac/ibm_emac_tah.h
deleted file mode 100644
index ccf64915e1e4..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_tah.h
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_tah.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, TAH support.
5 *
6 * Copyright 2004 MontaVista Software, Inc.
7 * Matt Porter <mporter@kernel.crashing.org>
8 *
9 * Copyright (c) 2005 Eugene Surovegin <ebs@ebshome.net>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17#ifndef _IBM_EMAC_TAH_H
18#define _IBM_EMAC_TAH_H
19
20#include <linux/init.h>
21#include <asm/ocp.h>
22
23/* TAH */
24struct tah_regs {
25 u32 revid;
26 u32 pad[3];
27 u32 mr;
28 u32 ssr0;
29 u32 ssr1;
30 u32 ssr2;
31 u32 ssr3;
32 u32 ssr4;
33 u32 ssr5;
34 u32 tsr;
35};
36
37/* TAH engine */
38#define TAH_MR_CVR 0x80000000
39#define TAH_MR_SR 0x40000000
40#define TAH_MR_ST_256 0x01000000
41#define TAH_MR_ST_512 0x02000000
42#define TAH_MR_ST_768 0x03000000
43#define TAH_MR_ST_1024 0x04000000
44#define TAH_MR_ST_1280 0x05000000
45#define TAH_MR_ST_1536 0x06000000
46#define TAH_MR_TFS_16KB 0x00000000
47#define TAH_MR_TFS_2KB 0x00200000
48#define TAH_MR_TFS_4KB 0x00400000
49#define TAH_MR_TFS_6KB 0x00600000
50#define TAH_MR_TFS_8KB 0x00800000
51#define TAH_MR_TFS_10KB 0x00a00000
52#define TAH_MR_DTFP 0x00100000
53#define TAH_MR_DIG 0x00080000
54
55#ifdef CONFIG_IBM_EMAC_TAH
56int tah_attach(void *emac) __init;
57
58void __tah_fini(struct ocp_device *ocpdev);
59static inline void tah_fini(struct ocp_device *ocpdev)
60{
61 if (ocpdev)
62 __tah_fini(ocpdev);
63}
64
65void __tah_reset(struct ocp_device *ocpdev);
66static inline void tah_reset(struct ocp_device *ocpdev)
67{
68 if (ocpdev)
69 __tah_reset(ocpdev);
70}
71
72int __tah_get_regs_len(struct ocp_device *ocpdev);
73static inline int tah_get_regs_len(struct ocp_device *ocpdev)
74{
75 return ocpdev ? __tah_get_regs_len(ocpdev) : 0;
76}
77
78void *tah_dump_regs(struct ocp_device *ocpdev, void *buf);
79#else
80# define tah_attach(x) 0
81# define tah_fini(x) ((void)0)
82# define tah_reset(x) ((void)0)
83# define tah_get_regs_len(x) 0
84# define tah_dump_regs(x,buf) (buf)
85#endif /* !CONFIG_IBM_EMAC_TAH */
86
87#endif /* _IBM_EMAC_TAH_H */
diff --git a/drivers/net/ibm_emac/ibm_emac_zmii.c b/drivers/net/ibm_emac/ibm_emac_zmii.c
deleted file mode 100644
index 2c0fdb0cabff..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_zmii.c
+++ /dev/null
@@ -1,253 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_zmii.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, ZMII bridge support.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Armin Kuster <akuster@mvista.com>
11 * Copyright 2001 MontaVista Softare Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19#include <linux/kernel.h>
20#include <linux/ethtool.h>
21#include <asm/io.h>
22
23#include "ibm_emac_core.h"
24#include "ibm_emac_debug.h"
25
26/* ZMIIx_FER */
27#define ZMII_FER_MDI(idx) (0x80000000 >> ((idx) * 4))
28#define ZMII_FER_MDI_ALL (ZMII_FER_MDI(0) | ZMII_FER_MDI(1) | \
29 ZMII_FER_MDI(2) | ZMII_FER_MDI(3))
30
31#define ZMII_FER_SMII(idx) (0x40000000 >> ((idx) * 4))
32#define ZMII_FER_RMII(idx) (0x20000000 >> ((idx) * 4))
33#define ZMII_FER_MII(idx) (0x10000000 >> ((idx) * 4))
34
35/* ZMIIx_SSR */
36#define ZMII_SSR_SCI(idx) (0x40000000 >> ((idx) * 4))
37#define ZMII_SSR_FSS(idx) (0x20000000 >> ((idx) * 4))
38#define ZMII_SSR_SP(idx) (0x10000000 >> ((idx) * 4))
39
40/* ZMII only supports MII, RMII and SMII
41 * we also support autodetection for backward compatibility
42 */
43static inline int zmii_valid_mode(int mode)
44{
45 return mode == PHY_MODE_MII ||
46 mode == PHY_MODE_RMII ||
47 mode == PHY_MODE_SMII ||
48 mode == PHY_MODE_NA;
49}
50
51static inline const char *zmii_mode_name(int mode)
52{
53 switch (mode) {
54 case PHY_MODE_MII:
55 return "MII";
56 case PHY_MODE_RMII:
57 return "RMII";
58 case PHY_MODE_SMII:
59 return "SMII";
60 default:
61 BUG();
62 }
63}
64
65static inline u32 zmii_mode_mask(int mode, int input)
66{
67 switch (mode) {
68 case PHY_MODE_MII:
69 return ZMII_FER_MII(input);
70 case PHY_MODE_RMII:
71 return ZMII_FER_RMII(input);
72 case PHY_MODE_SMII:
73 return ZMII_FER_SMII(input);
74 default:
75 return 0;
76 }
77}
78
79static int __init zmii_init(struct ocp_device *ocpdev, int input, int *mode)
80{
81 struct ibm_ocp_zmii *dev = ocp_get_drvdata(ocpdev);
82 struct zmii_regs __iomem *p;
83
84 ZMII_DBG("%d: init(%d, %d)" NL, ocpdev->def->index, input, *mode);
85
86 if (!dev) {
87 dev = kzalloc(sizeof(struct ibm_ocp_zmii), GFP_KERNEL);
88 if (!dev) {
89 printk(KERN_ERR
90 "zmii%d: couldn't allocate device structure!\n",
91 ocpdev->def->index);
92 return -ENOMEM;
93 }
94 dev->mode = PHY_MODE_NA;
95
96 p = ioremap(ocpdev->def->paddr, sizeof(struct zmii_regs));
97 if (!p) {
98 printk(KERN_ERR
99 "zmii%d: could not ioremap device registers!\n",
100 ocpdev->def->index);
101 kfree(dev);
102 return -ENOMEM;
103 }
104 dev->base = p;
105 ocp_set_drvdata(ocpdev, dev);
106
107 /* We may need FER value for autodetection later */
108 dev->fer_save = in_be32(&p->fer);
109
110 /* Disable all inputs by default */
111 out_be32(&p->fer, 0);
112 } else
113 p = dev->base;
114
115 if (!zmii_valid_mode(*mode)) {
116 /* Probably an EMAC connected to RGMII,
117 * but it still may need ZMII for MDIO
118 */
119 goto out;
120 }
121
122 /* Autodetect ZMII mode if not specified.
123 * This is only for backward compatibility with the old driver.
124 * Please, always specify PHY mode in your board port to avoid
125 * any surprises.
126 */
127 if (dev->mode == PHY_MODE_NA) {
128 if (*mode == PHY_MODE_NA) {
129 u32 r = dev->fer_save;
130
131 ZMII_DBG("%d: autodetecting mode, FER = 0x%08x" NL,
132 ocpdev->def->index, r);
133
134 if (r & (ZMII_FER_MII(0) | ZMII_FER_MII(1)))
135 dev->mode = PHY_MODE_MII;
136 else if (r & (ZMII_FER_RMII(0) | ZMII_FER_RMII(1)))
137 dev->mode = PHY_MODE_RMII;
138 else
139 dev->mode = PHY_MODE_SMII;
140 } else
141 dev->mode = *mode;
142
143 printk(KERN_NOTICE "zmii%d: bridge in %s mode\n",
144 ocpdev->def->index, zmii_mode_name(dev->mode));
145 } else {
146 /* All inputs must use the same mode */
147 if (*mode != PHY_MODE_NA && *mode != dev->mode) {
148 printk(KERN_ERR
149 "zmii%d: invalid mode %d specified for input %d\n",
150 ocpdev->def->index, *mode, input);
151 return -EINVAL;
152 }
153 }
154
155 /* Report back correct PHY mode,
156 * it may be used during PHY initialization.
157 */
158 *mode = dev->mode;
159
160 /* Enable this input */
161 out_be32(&p->fer, in_be32(&p->fer) | zmii_mode_mask(dev->mode, input));
162 out:
163 ++dev->users;
164 return 0;
165}
166
167int __init zmii_attach(void *emac)
168{
169 struct ocp_enet_private *dev = emac;
170 struct ocp_func_emac_data *emacdata = dev->def->additions;
171
172 if (emacdata->zmii_idx >= 0) {
173 dev->zmii_input = emacdata->zmii_mux;
174 dev->zmii_dev =
175 ocp_find_device(OCP_VENDOR_IBM, OCP_FUNC_ZMII,
176 emacdata->zmii_idx);
177 if (!dev->zmii_dev) {
178 printk(KERN_ERR "emac%d: unknown zmii%d!\n",
179 dev->def->index, emacdata->zmii_idx);
180 return -ENODEV;
181 }
182 if (zmii_init
183 (dev->zmii_dev, dev->zmii_input, &emacdata->phy_mode)) {
184 printk(KERN_ERR
185 "emac%d: zmii%d initialization failed!\n",
186 dev->def->index, emacdata->zmii_idx);
187 return -ENODEV;
188 }
189 }
190 return 0;
191}
192
193void __zmii_enable_mdio(struct ocp_device *ocpdev, int input)
194{
195 struct ibm_ocp_zmii *dev = ocp_get_drvdata(ocpdev);
196 u32 fer = in_be32(&dev->base->fer) & ~ZMII_FER_MDI_ALL;
197
198 ZMII_DBG2("%d: mdio(%d)" NL, ocpdev->def->index, input);
199
200 out_be32(&dev->base->fer, fer | ZMII_FER_MDI(input));
201}
202
203void __zmii_set_speed(struct ocp_device *ocpdev, int input, int speed)
204{
205 struct ibm_ocp_zmii *dev = ocp_get_drvdata(ocpdev);
206 u32 ssr = in_be32(&dev->base->ssr);
207
208 ZMII_DBG("%d: speed(%d, %d)" NL, ocpdev->def->index, input, speed);
209
210 if (speed == SPEED_100)
211 ssr |= ZMII_SSR_SP(input);
212 else
213 ssr &= ~ZMII_SSR_SP(input);
214
215 out_be32(&dev->base->ssr, ssr);
216}
217
218void __zmii_fini(struct ocp_device *ocpdev, int input)
219{
220 struct ibm_ocp_zmii *dev = ocp_get_drvdata(ocpdev);
221 BUG_ON(!dev || dev->users == 0);
222
223 ZMII_DBG("%d: fini(%d)" NL, ocpdev->def->index, input);
224
225 /* Disable this input */
226 out_be32(&dev->base->fer,
227 in_be32(&dev->base->fer) & ~zmii_mode_mask(dev->mode, input));
228
229 if (!--dev->users) {
230 /* Free everything if this is the last user */
231 ocp_set_drvdata(ocpdev, NULL);
232 iounmap(dev->base);
233 kfree(dev);
234 }
235}
236
237int __zmii_get_regs_len(struct ocp_device *ocpdev)
238{
239 return sizeof(struct emac_ethtool_regs_subhdr) +
240 sizeof(struct zmii_regs);
241}
242
243void *zmii_dump_regs(struct ocp_device *ocpdev, void *buf)
244{
245 struct ibm_ocp_zmii *dev = ocp_get_drvdata(ocpdev);
246 struct emac_ethtool_regs_subhdr *hdr = buf;
247 struct zmii_regs *regs = (struct zmii_regs *)(hdr + 1);
248
249 hdr->version = 0;
250 hdr->index = ocpdev->def->index;
251 memcpy_fromio(regs, dev->base, sizeof(struct zmii_regs));
252 return regs + 1;
253}
diff --git a/drivers/net/ibm_emac/ibm_emac_zmii.h b/drivers/net/ibm_emac/ibm_emac_zmii.h
deleted file mode 100644
index fad6d8bf983a..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_zmii.h
+++ /dev/null
@@ -1,82 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_zmii.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, ZMII bridge support.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Armin Kuster <akuster@mvista.com>
11 * Copyright 2001 MontaVista Softare Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19#ifndef _IBM_EMAC_ZMII_H_
20#define _IBM_EMAC_ZMII_H_
21
22#include <linux/init.h>
23#include <asm/ocp.h>
24
25/* ZMII bridge registers */
26struct zmii_regs {
27 u32 fer; /* Function enable reg */
28 u32 ssr; /* Speed select reg */
29 u32 smiirs; /* SMII status reg */
30};
31
32/* ZMII device */
33struct ibm_ocp_zmii {
34 struct zmii_regs __iomem *base;
35 int mode; /* subset of PHY_MODE_XXXX */
36 int users; /* number of EMACs using this ZMII bridge */
37 u32 fer_save; /* FER value left by firmware */
38};
39
40#ifdef CONFIG_IBM_EMAC_ZMII
41int zmii_attach(void *emac) __init;
42
43void __zmii_fini(struct ocp_device *ocpdev, int input);
44static inline void zmii_fini(struct ocp_device *ocpdev, int input)
45{
46 if (ocpdev)
47 __zmii_fini(ocpdev, input);
48}
49
50void __zmii_enable_mdio(struct ocp_device *ocpdev, int input);
51static inline void zmii_enable_mdio(struct ocp_device *ocpdev, int input)
52{
53 if (ocpdev)
54 __zmii_enable_mdio(ocpdev, input);
55}
56
57void __zmii_set_speed(struct ocp_device *ocpdev, int input, int speed);
58static inline void zmii_set_speed(struct ocp_device *ocpdev, int input,
59 int speed)
60{
61 if (ocpdev)
62 __zmii_set_speed(ocpdev, input, speed);
63}
64
65int __zmii_get_regs_len(struct ocp_device *ocpdev);
66static inline int zmii_get_regs_len(struct ocp_device *ocpdev)
67{
68 return ocpdev ? __zmii_get_regs_len(ocpdev) : 0;
69}
70
71void *zmii_dump_regs(struct ocp_device *ocpdev, void *buf);
72
73#else
74# define zmii_attach(x) 0
75# define zmii_fini(x,y) ((void)0)
76# define zmii_enable_mdio(x,y) ((void)0)
77# define zmii_set_speed(x,y,z) ((void)0)
78# define zmii_get_regs_len(x) 0
79# define zmii_dump_regs(x,buf) (buf)
80#endif /* !CONFIG_IBM_EMAC_ZMII */
81
82#endif /* _IBM_EMAC_ZMII_H_ */
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
index b7915cdcc6a5..83a877f3a553 100644
--- a/drivers/net/mv643xx_eth.c
+++ b/drivers/net/mv643xx_eth.c
@@ -34,406 +34,145 @@
34 * along with this program; if not, write to the Free Software 34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */ 36 */
37
37#include <linux/init.h> 38#include <linux/init.h>
38#include <linux/dma-mapping.h> 39#include <linux/dma-mapping.h>
39#include <linux/in.h> 40#include <linux/in.h>
40#include <linux/ip.h>
41#include <linux/tcp.h> 41#include <linux/tcp.h>
42#include <linux/udp.h> 42#include <linux/udp.h>
43#include <linux/etherdevice.h> 43#include <linux/etherdevice.h>
44
45#include <linux/bitops.h>
46#include <linux/delay.h> 44#include <linux/delay.h>
47#include <linux/ethtool.h> 45#include <linux/ethtool.h>
48#include <linux/platform_device.h> 46#include <linux/platform_device.h>
49
50#include <linux/module.h> 47#include <linux/module.h>
51#include <linux/kernel.h> 48#include <linux/kernel.h>
52#include <linux/spinlock.h> 49#include <linux/spinlock.h>
53#include <linux/workqueue.h> 50#include <linux/workqueue.h>
54#include <linux/mii.h> 51#include <linux/mii.h>
55
56#include <linux/mv643xx_eth.h> 52#include <linux/mv643xx_eth.h>
57
58#include <asm/io.h> 53#include <asm/io.h>
59#include <asm/types.h> 54#include <asm/types.h>
60#include <asm/pgtable.h>
61#include <asm/system.h> 55#include <asm/system.h>
62#include <asm/delay.h>
63#include <asm/dma-mapping.h>
64 56
65#define MV643XX_CHECKSUM_OFFLOAD_TX 57static char mv643xx_eth_driver_name[] = "mv643xx_eth";
66#define MV643XX_NAPI 58static char mv643xx_eth_driver_version[] = "1.1";
67#define MV643XX_TX_FAST_REFILL
68#undef MV643XX_COAL
69 59
70#define MV643XX_TX_COAL 100 60#define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
71#ifdef MV643XX_COAL 61#define MV643XX_ETH_NAPI
72#define MV643XX_RX_COAL 100 62#define MV643XX_ETH_TX_FAST_REFILL
73#endif
74 63
75#ifdef MV643XX_CHECKSUM_OFFLOAD_TX 64#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
76#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1) 65#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
77#else 66#else
78#define MAX_DESCS_PER_SKB 1 67#define MAX_DESCS_PER_SKB 1
79#endif 68#endif
80 69
81#define ETH_VLAN_HLEN 4
82#define ETH_FCS_LEN 4
83#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
84#define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
85 ETH_VLAN_HLEN + ETH_FCS_LEN)
86#define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \
87 dma_get_cache_alignment())
88
89/* 70/*
90 * Registers shared between all ports. 71 * Registers shared between all ports.
91 */ 72 */
92#define PHY_ADDR_REG 0x0000 73#define PHY_ADDR 0x0000
93#define SMI_REG 0x0004 74#define SMI_REG 0x0004
94#define WINDOW_BASE(i) (0x0200 + ((i) << 3)) 75#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
95#define WINDOW_SIZE(i) (0x0204 + ((i) << 3)) 76#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
96#define WINDOW_REMAP_HIGH(i) (0x0280 + ((i) << 2)) 77#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
97#define WINDOW_BAR_ENABLE 0x0290 78#define WINDOW_BAR_ENABLE 0x0290
98#define WINDOW_PROTECT(i) (0x0294 + ((i) << 4)) 79#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
99 80
100/* 81/*
101 * Per-port registers. 82 * Per-port registers.
102 */ 83 */
103#define PORT_CONFIG_REG(p) (0x0400 + ((p) << 10)) 84#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
104#define PORT_CONFIG_EXTEND_REG(p) (0x0404 + ((p) << 10)) 85#define UNICAST_PROMISCUOUS_MODE 0x00000001
105#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10)) 86#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
106#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10)) 87#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
107#define SDMA_CONFIG_REG(p) (0x041c + ((p) << 10)) 88#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
108#define PORT_SERIAL_CONTROL_REG(p) (0x043c + ((p) << 10)) 89#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
109#define PORT_STATUS_REG(p) (0x0444 + ((p) << 10)) 90#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
110#define TRANSMIT_QUEUE_COMMAND_REG(p) (0x0448 + ((p) << 10)) 91#define PORT_STATUS(p) (0x0444 + ((p) << 10))
111#define MAXIMUM_TRANSMIT_UNIT(p) (0x0458 + ((p) << 10)) 92#define TX_FIFO_EMPTY 0x00000400
112#define INTERRUPT_CAUSE_REG(p) (0x0460 + ((p) << 10)) 93#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
113#define INTERRUPT_CAUSE_EXTEND_REG(p) (0x0464 + ((p) << 10)) 94#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
114#define INTERRUPT_MASK_REG(p) (0x0468 + ((p) << 10)) 95#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
115#define INTERRUPT_EXTEND_MASK_REG(p) (0x046c + ((p) << 10)) 96#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
116#define TX_FIFO_URGENT_THRESHOLD_REG(p) (0x0474 + ((p) << 10)) 97#define TX_BW_BURST(p) (0x045c + ((p) << 10))
117#define RX_CURRENT_QUEUE_DESC_PTR_0(p) (0x060c + ((p) << 10)) 98#define INT_CAUSE(p) (0x0460 + ((p) << 10))
118#define RECEIVE_QUEUE_COMMAND_REG(p) (0x0680 + ((p) << 10)) 99#define INT_TX_END 0x07f80000
119#define TX_CURRENT_QUEUE_DESC_PTR_0(p) (0x06c0 + ((p) << 10)) 100#define INT_RX 0x0007fbfc
120#define MIB_COUNTERS_BASE(p) (0x1000 + ((p) << 7)) 101#define INT_EXT 0x00000002
121#define DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(p) (0x1400 + ((p) << 10)) 102#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
122#define DA_FILTER_OTHER_MULTICAST_TABLE_BASE(p) (0x1500 + ((p) << 10)) 103#define INT_EXT_LINK 0x00100000
123#define DA_FILTER_UNICAST_TABLE_BASE(p) (0x1600 + ((p) << 10)) 104#define INT_EXT_PHY 0x00010000
124 105#define INT_EXT_TX_ERROR_0 0x00000100
125/* These macros describe Ethernet Port configuration reg (Px_cR) bits */ 106#define INT_EXT_TX_0 0x00000001
126#define UNICAST_NORMAL_MODE (0 << 0) 107#define INT_EXT_TX 0x0000ffff
127#define UNICAST_PROMISCUOUS_MODE (1 << 0) 108#define INT_MASK(p) (0x0468 + ((p) << 10))
128#define DEFAULT_RX_QUEUE(queue) ((queue) << 1) 109#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
129#define DEFAULT_RX_ARP_QUEUE(queue) ((queue) << 4) 110#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
130#define RECEIVE_BC_IF_NOT_IP_OR_ARP (0 << 7) 111#define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
131#define REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7) 112#define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
132#define RECEIVE_BC_IF_IP (0 << 8) 113#define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
133#define REJECT_BC_IF_IP (1 << 8) 114#define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
134#define RECEIVE_BC_IF_ARP (0 << 9) 115#define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
135#define REJECT_BC_IF_ARP (1 << 9) 116#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
136#define TX_AM_NO_UPDATE_ERROR_SUMMARY (1 << 12) 117#define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
137#define CAPTURE_TCP_FRAMES_DIS (0 << 14) 118#define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
138#define CAPTURE_TCP_FRAMES_EN (1 << 14) 119#define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
139#define CAPTURE_UDP_FRAMES_DIS (0 << 15) 120#define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
140#define CAPTURE_UDP_FRAMES_EN (1 << 15) 121#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
141#define DEFAULT_RX_TCP_QUEUE(queue) ((queue) << 16) 122#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
142#define DEFAULT_RX_UDP_QUEUE(queue) ((queue) << 19) 123#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
143#define DEFAULT_RX_BPDU_QUEUE(queue) ((queue) << 22) 124#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
144 125
145#define PORT_CONFIG_DEFAULT_VALUE \ 126
146 UNICAST_NORMAL_MODE | \ 127/*
147 DEFAULT_RX_QUEUE(0) | \ 128 * SDMA configuration register.
148 DEFAULT_RX_ARP_QUEUE(0) | \ 129 */
149 RECEIVE_BC_IF_NOT_IP_OR_ARP | \
150 RECEIVE_BC_IF_IP | \
151 RECEIVE_BC_IF_ARP | \
152 CAPTURE_TCP_FRAMES_DIS | \
153 CAPTURE_UDP_FRAMES_DIS | \
154 DEFAULT_RX_TCP_QUEUE(0) | \
155 DEFAULT_RX_UDP_QUEUE(0) | \
156 DEFAULT_RX_BPDU_QUEUE(0)
157
158/* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
159#define CLASSIFY_EN (1 << 0)
160#define SPAN_BPDU_PACKETS_AS_NORMAL (0 << 1)
161#define SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1 << 1)
162#define PARTITION_DISABLE (0 << 2)
163#define PARTITION_ENABLE (1 << 2)
164
165#define PORT_CONFIG_EXTEND_DEFAULT_VALUE \
166 SPAN_BPDU_PACKETS_AS_NORMAL | \
167 PARTITION_DISABLE
168
169/* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
170#define RIFB (1 << 0)
171#define RX_BURST_SIZE_1_64BIT (0 << 1)
172#define RX_BURST_SIZE_2_64BIT (1 << 1)
173#define RX_BURST_SIZE_4_64BIT (2 << 1) 130#define RX_BURST_SIZE_4_64BIT (2 << 1)
174#define RX_BURST_SIZE_8_64BIT (3 << 1)
175#define RX_BURST_SIZE_16_64BIT (4 << 1)
176#define BLM_RX_NO_SWAP (1 << 4) 131#define BLM_RX_NO_SWAP (1 << 4)
177#define BLM_RX_BYTE_SWAP (0 << 4)
178#define BLM_TX_NO_SWAP (1 << 5) 132#define BLM_TX_NO_SWAP (1 << 5)
179#define BLM_TX_BYTE_SWAP (0 << 5)
180#define DESCRIPTORS_BYTE_SWAP (1 << 6)
181#define DESCRIPTORS_NO_SWAP (0 << 6)
182#define IPG_INT_RX(value) (((value) & 0x3fff) << 8)
183#define TX_BURST_SIZE_1_64BIT (0 << 22)
184#define TX_BURST_SIZE_2_64BIT (1 << 22)
185#define TX_BURST_SIZE_4_64BIT (2 << 22) 133#define TX_BURST_SIZE_4_64BIT (2 << 22)
186#define TX_BURST_SIZE_8_64BIT (3 << 22)
187#define TX_BURST_SIZE_16_64BIT (4 << 22)
188 134
189#if defined(__BIG_ENDIAN) 135#if defined(__BIG_ENDIAN)
190#define PORT_SDMA_CONFIG_DEFAULT_VALUE \ 136#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
191 RX_BURST_SIZE_4_64BIT | \ 137 RX_BURST_SIZE_4_64BIT | \
192 IPG_INT_RX(0) | \
193 TX_BURST_SIZE_4_64BIT 138 TX_BURST_SIZE_4_64BIT
194#elif defined(__LITTLE_ENDIAN) 139#elif defined(__LITTLE_ENDIAN)
195#define PORT_SDMA_CONFIG_DEFAULT_VALUE \ 140#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
196 RX_BURST_SIZE_4_64BIT | \ 141 RX_BURST_SIZE_4_64BIT | \
197 BLM_RX_NO_SWAP | \ 142 BLM_RX_NO_SWAP | \
198 BLM_TX_NO_SWAP | \ 143 BLM_TX_NO_SWAP | \
199 IPG_INT_RX(0) | \
200 TX_BURST_SIZE_4_64BIT 144 TX_BURST_SIZE_4_64BIT
201#else 145#else
202#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined 146#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
203#endif 147#endif
204 148
205/* These macros describe Ethernet Port serial control reg (PSCR) bits */ 149
206#define SERIAL_PORT_DISABLE (0 << 0) 150/*
207#define SERIAL_PORT_ENABLE (1 << 0) 151 * Port serial control register.
208#define DO_NOT_FORCE_LINK_PASS (0 << 1) 152 */
209#define FORCE_LINK_PASS (1 << 1) 153#define SET_MII_SPEED_TO_100 (1 << 24)
210#define ENABLE_AUTO_NEG_FOR_DUPLX (0 << 2) 154#define SET_GMII_SPEED_TO_1000 (1 << 23)
211#define DISABLE_AUTO_NEG_FOR_DUPLX (1 << 2) 155#define SET_FULL_DUPLEX_MODE (1 << 21)
212#define ENABLE_AUTO_NEG_FOR_FLOW_CTRL (0 << 3)
213#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
214#define ADV_NO_FLOW_CTRL (0 << 4)
215#define ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
216#define FORCE_FC_MODE_NO_PAUSE_DIS_TX (0 << 5)
217#define FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
218#define FORCE_BP_MODE_NO_JAM (0 << 7)
219#define FORCE_BP_MODE_JAM_TX (1 << 7)
220#define FORCE_BP_MODE_JAM_TX_ON_RX_ERR (2 << 7)
221#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
222#define FORCE_LINK_FAIL (0 << 10)
223#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
224#define RETRANSMIT_16_ATTEMPTS (0 << 11)
225#define RETRANSMIT_FOREVER (1 << 11)
226#define ENABLE_AUTO_NEG_SPEED_GMII (0 << 13)
227#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
228#define DTE_ADV_0 (0 << 14)
229#define DTE_ADV_1 (1 << 14)
230#define DISABLE_AUTO_NEG_BYPASS (0 << 15)
231#define ENABLE_AUTO_NEG_BYPASS (1 << 15)
232#define AUTO_NEG_NO_CHANGE (0 << 16)
233#define RESTART_AUTO_NEG (1 << 16)
234#define MAX_RX_PACKET_1518BYTE (0 << 17)
235#define MAX_RX_PACKET_1522BYTE (1 << 17) 156#define MAX_RX_PACKET_1522BYTE (1 << 17)
236#define MAX_RX_PACKET_1552BYTE (2 << 17)
237#define MAX_RX_PACKET_9022BYTE (3 << 17)
238#define MAX_RX_PACKET_9192BYTE (4 << 17)
239#define MAX_RX_PACKET_9700BYTE (5 << 17) 157#define MAX_RX_PACKET_9700BYTE (5 << 17)
240#define MAX_RX_PACKET_MASK (7 << 17) 158#define MAX_RX_PACKET_MASK (7 << 17)
241#define CLR_EXT_LOOPBACK (0 << 20) 159#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
242#define SET_EXT_LOOPBACK (1 << 20) 160#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
243#define SET_HALF_DUPLEX_MODE (0 << 21) 161#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
244#define SET_FULL_DUPLEX_MODE (1 << 21) 162#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
245#define DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (0 << 22) 163#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
246#define ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22) 164#define FORCE_LINK_PASS (1 << 1)
247#define SET_GMII_SPEED_TO_10_100 (0 << 23) 165#define SERIAL_PORT_ENABLE (1 << 0)
248#define SET_GMII_SPEED_TO_1000 (1 << 23)
249#define SET_MII_SPEED_TO_10 (0 << 24)
250#define SET_MII_SPEED_TO_100 (1 << 24)
251 166
252#define PORT_SERIAL_CONTROL_DEFAULT_VALUE \ 167#define DEFAULT_RX_QUEUE_SIZE 400
253 DO_NOT_FORCE_LINK_PASS | \ 168#define DEFAULT_TX_QUEUE_SIZE 800
254 ENABLE_AUTO_NEG_FOR_DUPLX | \ 169
255 DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ 170
256 ADV_SYMMETRIC_FLOW_CTRL | \ 171/*
257 FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ 172 * RX/TX descriptors.
258 FORCE_BP_MODE_NO_JAM | \
259 (1 << 9) /* reserved */ | \
260 DO_NOT_FORCE_LINK_FAIL | \
261 RETRANSMIT_16_ATTEMPTS | \
262 ENABLE_AUTO_NEG_SPEED_GMII | \
263 DTE_ADV_0 | \
264 DISABLE_AUTO_NEG_BYPASS | \
265 AUTO_NEG_NO_CHANGE | \
266 MAX_RX_PACKET_9700BYTE | \
267 CLR_EXT_LOOPBACK | \
268 SET_FULL_DUPLEX_MODE | \
269 ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
270
271/* These macros describe Ethernet Serial Status reg (PSR) bits */
272#define PORT_STATUS_MODE_10_BIT (1 << 0)
273#define PORT_STATUS_LINK_UP (1 << 1)
274#define PORT_STATUS_FULL_DUPLEX (1 << 2)
275#define PORT_STATUS_FLOW_CONTROL (1 << 3)
276#define PORT_STATUS_GMII_1000 (1 << 4)
277#define PORT_STATUS_MII_100 (1 << 5)
278/* PSR bit 6 is undocumented */
279#define PORT_STATUS_TX_IN_PROGRESS (1 << 7)
280#define PORT_STATUS_AUTONEG_BYPASSED (1 << 8)
281#define PORT_STATUS_PARTITION (1 << 9)
282#define PORT_STATUS_TX_FIFO_EMPTY (1 << 10)
283/* PSR bits 11-31 are reserved */
284
285#define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
286#define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
287
288#define DESC_SIZE 64
289
290#define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
291#define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
292
293#define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2)
294#define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9)
295#define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
296#define ETH_INT_CAUSE_EXT 0x00000002
297#define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
298
299#define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0)
300#define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
301#define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
302#define ETH_INT_CAUSE_PHY 0x00010000
303#define ETH_INT_CAUSE_STATE 0x00100000
304#define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \
305 ETH_INT_CAUSE_STATE)
306
307#define ETH_INT_MASK_ALL 0x00000000
308#define ETH_INT_MASK_ALL_EXT 0x00000000
309
310#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
311#define PHY_WAIT_MICRO_SECONDS 10
312
313/* Buffer offset from buffer pointer */
314#define RX_BUF_OFFSET 0x2
315
316/* Gigabit Ethernet Unit Global Registers */
317
318/* MIB Counters register definitions */
319#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
320#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
321#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
322#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
323#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
324#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
325#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
326#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
327#define ETH_MIB_FRAMES_64_OCTETS 0x20
328#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
329#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
330#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
331#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
332#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
333#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
334#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
335#define ETH_MIB_GOOD_FRAMES_SENT 0x40
336#define ETH_MIB_EXCESSIVE_COLLISION 0x44
337#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
338#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
339#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
340#define ETH_MIB_FC_SENT 0x54
341#define ETH_MIB_GOOD_FC_RECEIVED 0x58
342#define ETH_MIB_BAD_FC_RECEIVED 0x5c
343#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
344#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
345#define ETH_MIB_OVERSIZE_RECEIVED 0x68
346#define ETH_MIB_JABBER_RECEIVED 0x6c
347#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
348#define ETH_MIB_BAD_CRC_EVENT 0x74
349#define ETH_MIB_COLLISION 0x78
350#define ETH_MIB_LATE_COLLISION 0x7c
351
352/* Port serial status reg (PSR) */
353#define ETH_INTERFACE_PCM 0x00000001
354#define ETH_LINK_IS_UP 0x00000002
355#define ETH_PORT_AT_FULL_DUPLEX 0x00000004
356#define ETH_RX_FLOW_CTRL_ENABLED 0x00000008
357#define ETH_GMII_SPEED_1000 0x00000010
358#define ETH_MII_SPEED_100 0x00000020
359#define ETH_TX_IN_PROGRESS 0x00000080
360#define ETH_BYPASS_ACTIVE 0x00000100
361#define ETH_PORT_AT_PARTITION_STATE 0x00000200
362#define ETH_PORT_TX_FIFO_EMPTY 0x00000400
363
364/* SMI reg */
365#define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
366#define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
367#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */
368#define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
369
370/* Interrupt Cause Register Bit Definitions */
371
372/* SDMA command status fields macros */
373
374/* Tx & Rx descriptors status */
375#define ETH_ERROR_SUMMARY 0x00000001
376
377/* Tx & Rx descriptors command */
378#define ETH_BUFFER_OWNED_BY_DMA 0x80000000
379
380/* Tx descriptors status */
381#define ETH_LC_ERROR 0
382#define ETH_UR_ERROR 0x00000002
383#define ETH_RL_ERROR 0x00000004
384#define ETH_LLC_SNAP_FORMAT 0x00000200
385
386/* Rx descriptors status */
387#define ETH_OVERRUN_ERROR 0x00000002
388#define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004
389#define ETH_RESOURCE_ERROR 0x00000006
390#define ETH_VLAN_TAGGED 0x00080000
391#define ETH_BPDU_FRAME 0x00100000
392#define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000
393#define ETH_OTHER_FRAME_TYPE 0x00400000
394#define ETH_LAYER_2_IS_ETH_V_2 0x00800000
395#define ETH_FRAME_TYPE_IP_V_4 0x01000000
396#define ETH_FRAME_HEADER_OK 0x02000000
397#define ETH_RX_LAST_DESC 0x04000000
398#define ETH_RX_FIRST_DESC 0x08000000
399#define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000
400#define ETH_RX_ENABLE_INTERRUPT 0x20000000
401#define ETH_LAYER_4_CHECKSUM_OK 0x40000000
402
403/* Rx descriptors byte count */
404#define ETH_FRAME_FRAGMENTED 0x00000004
405
406/* Tx descriptors command */
407#define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400
408#define ETH_FRAME_SET_TO_VLAN 0x00008000
409#define ETH_UDP_FRAME 0x00010000
410#define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
411#define ETH_GEN_IP_V_4_CHECKSUM 0x00040000
412#define ETH_ZERO_PADDING 0x00080000
413#define ETH_TX_LAST_DESC 0x00100000
414#define ETH_TX_FIRST_DESC 0x00200000
415#define ETH_GEN_CRC 0x00400000
416#define ETH_TX_ENABLE_INTERRUPT 0x00800000
417#define ETH_AUTO_MODE 0x40000000
418
419#define ETH_TX_IHL_SHIFT 11
420
421/* typedefs */
422
423typedef enum _eth_func_ret_status {
424 ETH_OK, /* Returned as expected. */
425 ETH_ERROR, /* Fundamental error. */
426 ETH_RETRY, /* Could not process request. Try later.*/
427 ETH_END_OF_JOB, /* Ring has nothing to process. */
428 ETH_QUEUE_FULL, /* Ring resource error. */
429 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
430} ETH_FUNC_RET_STATUS;
431
432/* These are for big-endian machines. Little endian needs different
433 * definitions.
434 */ 173 */
435#if defined(__BIG_ENDIAN) 174#if defined(__BIG_ENDIAN)
436struct eth_rx_desc { 175struct rx_desc {
437 u16 byte_cnt; /* Descriptor buffer byte count */ 176 u16 byte_cnt; /* Descriptor buffer byte count */
438 u16 buf_size; /* Buffer size */ 177 u16 buf_size; /* Buffer size */
439 u32 cmd_sts; /* Descriptor command status */ 178 u32 cmd_sts; /* Descriptor command status */
@@ -441,7 +180,7 @@ struct eth_rx_desc {
441 u32 buf_ptr; /* Descriptor buffer pointer */ 180 u32 buf_ptr; /* Descriptor buffer pointer */
442}; 181};
443 182
444struct eth_tx_desc { 183struct tx_desc {
445 u16 byte_cnt; /* buffer byte count */ 184 u16 byte_cnt; /* buffer byte count */
446 u16 l4i_chk; /* CPU provided TCP checksum */ 185 u16 l4i_chk; /* CPU provided TCP checksum */
447 u32 cmd_sts; /* Command/status field */ 186 u32 cmd_sts; /* Command/status field */
@@ -449,7 +188,7 @@ struct eth_tx_desc {
449 u32 buf_ptr; /* pointer to buffer for this descriptor*/ 188 u32 buf_ptr; /* pointer to buffer for this descriptor*/
450}; 189};
451#elif defined(__LITTLE_ENDIAN) 190#elif defined(__LITTLE_ENDIAN)
452struct eth_rx_desc { 191struct rx_desc {
453 u32 cmd_sts; /* Descriptor command status */ 192 u32 cmd_sts; /* Descriptor command status */
454 u16 buf_size; /* Buffer size */ 193 u16 buf_size; /* Buffer size */
455 u16 byte_cnt; /* Descriptor buffer byte count */ 194 u16 byte_cnt; /* Descriptor buffer byte count */
@@ -457,7 +196,7 @@ struct eth_rx_desc {
457 u32 next_desc_ptr; /* Next descriptor pointer */ 196 u32 next_desc_ptr; /* Next descriptor pointer */
458}; 197};
459 198
460struct eth_tx_desc { 199struct tx_desc {
461 u32 cmd_sts; /* Command/status field */ 200 u32 cmd_sts; /* Command/status field */
462 u16 l4i_chk; /* CPU provided TCP checksum */ 201 u16 l4i_chk; /* CPU provided TCP checksum */
463 u16 byte_cnt; /* buffer byte count */ 202 u16 byte_cnt; /* buffer byte count */
@@ -468,18 +207,59 @@ struct eth_tx_desc {
468#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined 207#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
469#endif 208#endif
470 209
471/* Unified struct for Rx and Tx operations. The user is not required to */ 210/* RX & TX descriptor command */
472/* be familier with neither Tx nor Rx descriptors. */ 211#define BUFFER_OWNED_BY_DMA 0x80000000
473struct pkt_info { 212
474 unsigned short byte_cnt; /* Descriptor buffer byte count */ 213/* RX & TX descriptor status */
475 unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */ 214#define ERROR_SUMMARY 0x00000001
476 unsigned int cmd_sts; /* Descriptor command status */ 215
477 dma_addr_t buf_ptr; /* Descriptor buffer pointer */ 216/* RX descriptor status */
478 struct sk_buff *return_info; /* User resource return information */ 217#define LAYER_4_CHECKSUM_OK 0x40000000
218#define RX_ENABLE_INTERRUPT 0x20000000
219#define RX_FIRST_DESC 0x08000000
220#define RX_LAST_DESC 0x04000000
221
222/* TX descriptor command */
223#define TX_ENABLE_INTERRUPT 0x00800000
224#define GEN_CRC 0x00400000
225#define TX_FIRST_DESC 0x00200000
226#define TX_LAST_DESC 0x00100000
227#define ZERO_PADDING 0x00080000
228#define GEN_IP_V4_CHECKSUM 0x00040000
229#define GEN_TCP_UDP_CHECKSUM 0x00020000
230#define UDP_FRAME 0x00010000
231
232#define TX_IHL_SHIFT 11
233
234
235/* global *******************************************************************/
236struct mv643xx_eth_shared_private {
237 /*
238 * Ethernet controller base address.
239 */
240 void __iomem *base;
241
242 /*
243 * Protects access to SMI_REG, which is shared between ports.
244 */
245 spinlock_t phy_lock;
246
247 /*
248 * Per-port MBUS window access register value.
249 */
250 u32 win_protect;
251
252 /*
253 * Hardware-specific parameters.
254 */
255 unsigned int t_clk;
256 int extended_rx_coal_limit;
257 int tx_bw_control_moved;
479}; 258};
480 259
481/* Ethernet port specific information */ 260
482struct mv643xx_mib_counters { 261/* per-port *****************************************************************/
262struct mib_counters {
483 u64 good_octets_received; 263 u64 good_octets_received;
484 u32 bad_octets_received; 264 u32 bad_octets_received;
485 u32 internal_mac_transmit_err; 265 u32 internal_mac_transmit_err;
@@ -512,461 +292,282 @@ struct mv643xx_mib_counters {
512 u32 late_collision; 292 u32 late_collision;
513}; 293};
514 294
515struct mv643xx_shared_private { 295struct rx_queue {
516 void __iomem *eth_base; 296 int index;
517
518 /* used to protect SMI_REG, which is shared across ports */
519 spinlock_t phy_lock;
520 297
521 u32 win_protect; 298 int rx_ring_size;
522
523 unsigned int t_clk;
524};
525
526struct mv643xx_private {
527 struct mv643xx_shared_private *shared;
528 int port_num; /* User Ethernet port number */
529
530 struct mv643xx_shared_private *shared_smi;
531
532 u32 rx_sram_addr; /* Base address of rx sram area */
533 u32 rx_sram_size; /* Size of rx sram area */
534 u32 tx_sram_addr; /* Base address of tx sram area */
535 u32 tx_sram_size; /* Size of tx sram area */
536 299
537 int rx_resource_err; /* Rx ring resource error flag */ 300 int rx_desc_count;
301 int rx_curr_desc;
302 int rx_used_desc;
538 303
539 /* Tx/Rx rings managment indexes fields. For driver use */ 304 struct rx_desc *rx_desc_area;
305 dma_addr_t rx_desc_dma;
306 int rx_desc_area_size;
307 struct sk_buff **rx_skb;
540 308
541 /* Next available and first returning Rx resource */ 309 struct timer_list rx_oom;
542 int rx_curr_desc_q, rx_used_desc_q; 310};
543 311
544 /* Next available and first returning Tx resource */ 312struct tx_queue {
545 int tx_curr_desc_q, tx_used_desc_q; 313 int index;
546 314
547#ifdef MV643XX_TX_FAST_REFILL 315 int tx_ring_size;
548 u32 tx_clean_threshold;
549#endif
550 316
551 struct eth_rx_desc *p_rx_desc_area; 317 int tx_desc_count;
552 dma_addr_t rx_desc_dma; 318 int tx_curr_desc;
553 int rx_desc_area_size; 319 int tx_used_desc;
554 struct sk_buff **rx_skb;
555 320
556 struct eth_tx_desc *p_tx_desc_area; 321 struct tx_desc *tx_desc_area;
557 dma_addr_t tx_desc_dma; 322 dma_addr_t tx_desc_dma;
558 int tx_desc_area_size; 323 int tx_desc_area_size;
559 struct sk_buff **tx_skb; 324 struct sk_buff **tx_skb;
325};
560 326
561 struct work_struct tx_timeout_task; 327struct mv643xx_eth_private {
328 struct mv643xx_eth_shared_private *shared;
329 int port_num;
562 330
563 struct net_device *dev; 331 struct net_device *dev;
564 struct napi_struct napi; 332
565 struct net_device_stats stats; 333 struct mv643xx_eth_shared_private *shared_smi;
566 struct mv643xx_mib_counters mib_counters; 334 int phy_addr;
335
567 spinlock_t lock; 336 spinlock_t lock;
568 /* Size of Tx Ring per queue */ 337
569 int tx_ring_size; 338 struct mib_counters mib_counters;
570 /* Number of tx descriptors in use */ 339 struct work_struct tx_timeout_task;
571 int tx_desc_count; 340 struct mii_if_info mii;
572 /* Size of Rx Ring per queue */
573 int rx_ring_size;
574 /* Number of rx descriptors in use */
575 int rx_desc_count;
576 341
577 /* 342 /*
578 * Used in case RX Ring is empty, which can be caused when 343 * RX state.
579 * system does not have resources (skb's)
580 */ 344 */
581 struct timer_list timeout; 345 int default_rx_ring_size;
582 346 unsigned long rx_desc_sram_addr;
583 u32 rx_int_coal; 347 int rx_desc_sram_size;
584 u32 tx_int_coal; 348 u8 rxq_mask;
585 struct mii_if_info mii; 349 int rxq_primary;
586}; 350 struct napi_struct napi;
351 struct rx_queue rxq[8];
587 352
588/* Static function declarations */ 353 /*
589static void eth_port_init(struct mv643xx_private *mp); 354 * TX state.
590static void eth_port_reset(struct mv643xx_private *mp); 355 */
591static void eth_port_start(struct net_device *dev); 356 int default_tx_ring_size;
592 357 unsigned long tx_desc_sram_addr;
593static void ethernet_phy_reset(struct mv643xx_private *mp); 358 int tx_desc_sram_size;
594 359 u8 txq_mask;
595static void eth_port_write_smi_reg(struct mv643xx_private *mp, 360 int txq_primary;
596 unsigned int phy_reg, unsigned int value); 361 struct tx_queue txq[8];
597 362#ifdef MV643XX_ETH_TX_FAST_REFILL
598static void eth_port_read_smi_reg(struct mv643xx_private *mp, 363 int tx_clean_threshold;
599 unsigned int phy_reg, unsigned int *value);
600
601static void eth_clear_mib_counters(struct mv643xx_private *mp);
602
603static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
604 struct pkt_info *p_pkt_info);
605static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
606 struct pkt_info *p_pkt_info);
607
608static void eth_port_uc_addr_get(struct mv643xx_private *mp,
609 unsigned char *p_addr);
610static void eth_port_uc_addr_set(struct mv643xx_private *mp,
611 unsigned char *p_addr);
612static void eth_port_set_multicast_list(struct net_device *);
613static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp,
614 unsigned int queues);
615static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp,
616 unsigned int queues);
617static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp);
618static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp);
619static int mv643xx_eth_open(struct net_device *);
620static int mv643xx_eth_stop(struct net_device *);
621static void eth_port_init_mac_tables(struct mv643xx_private *mp);
622#ifdef MV643XX_NAPI
623static int mv643xx_poll(struct napi_struct *napi, int budget);
624#endif 364#endif
625static int ethernet_phy_get(struct mv643xx_private *mp); 365};
626static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr);
627static int ethernet_phy_detect(struct mv643xx_private *mp);
628static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location);
629static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val);
630static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
631static const struct ethtool_ops mv643xx_ethtool_ops;
632 366
633static char mv643xx_driver_name[] = "mv643xx_eth";
634static char mv643xx_driver_version[] = "1.0";
635 367
636static inline u32 rdl(struct mv643xx_private *mp, int offset) 368/* port register accessors **************************************************/
369static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
637{ 370{
638 return readl(mp->shared->eth_base + offset); 371 return readl(mp->shared->base + offset);
639} 372}
640 373
641static inline void wrl(struct mv643xx_private *mp, int offset, u32 data) 374static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
642{ 375{
643 writel(data, mp->shared->eth_base + offset); 376 writel(data, mp->shared->base + offset);
644} 377}
645 378
646/*
647 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
648 *
649 * Input : pointer to ethernet interface network device structure
650 * new mtu size
651 * Output : 0 upon success, -EINVAL upon failure
652 */
653static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
654{
655 if ((new_mtu > 9500) || (new_mtu < 64))
656 return -EINVAL;
657 379
658 dev->mtu = new_mtu; 380/* rxq/txq helper functions *************************************************/
659 if (!netif_running(dev)) 381static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
660 return 0;
661
662 /*
663 * Stop and then re-open the interface. This will allocate RX
664 * skbs of the new MTU.
665 * There is a possible danger that the open will not succeed,
666 * due to memory being full, which might fail the open function.
667 */
668 mv643xx_eth_stop(dev);
669 if (mv643xx_eth_open(dev)) {
670 printk(KERN_ERR "%s: Fatal error on opening device\n",
671 dev->name);
672 }
673
674 return 0;
675}
676
677/*
678 * mv643xx_eth_rx_refill_descs
679 *
680 * Fills / refills RX queue on a certain gigabit ethernet port
681 *
682 * Input : pointer to ethernet interface network device structure
683 * Output : N/A
684 */
685static void mv643xx_eth_rx_refill_descs(struct net_device *dev)
686{ 382{
687 struct mv643xx_private *mp = netdev_priv(dev); 383 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
688 struct pkt_info pkt_info;
689 struct sk_buff *skb;
690 int unaligned;
691
692 while (mp->rx_desc_count < mp->rx_ring_size) {
693 skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment());
694 if (!skb)
695 break;
696 mp->rx_desc_count++;
697 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
698 if (unaligned)
699 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
700 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
701 pkt_info.byte_cnt = ETH_RX_SKB_SIZE;
702 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
703 ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
704 pkt_info.return_info = skb;
705 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
706 printk(KERN_ERR
707 "%s: Error allocating RX Ring\n", dev->name);
708 break;
709 }
710 skb_reserve(skb, ETH_HW_IP_ALIGN);
711 }
712 /*
713 * If RX ring is empty of SKB, set a timer to try allocating
714 * again at a later time.
715 */
716 if (mp->rx_desc_count == 0) {
717 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
718 mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */
719 add_timer(&mp->timeout);
720 }
721} 384}
722 385
723/* 386static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
724 * mv643xx_eth_rx_refill_descs_timer_wrapper
725 *
726 * Timer routine to wake up RX queue filling task. This function is
727 * used only in case the RX queue is empty, and all alloc_skb has
728 * failed (due to out of memory event).
729 *
730 * Input : pointer to ethernet interface network device structure
731 * Output : N/A
732 */
733static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data)
734{ 387{
735 mv643xx_eth_rx_refill_descs((struct net_device *)data); 388 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
736} 389}
737 390
738/* 391static void rxq_enable(struct rx_queue *rxq)
739 * mv643xx_eth_update_mac_address
740 *
741 * Update the MAC address of the port in the address table
742 *
743 * Input : pointer to ethernet interface network device structure
744 * Output : N/A
745 */
746static void mv643xx_eth_update_mac_address(struct net_device *dev)
747{ 392{
748 struct mv643xx_private *mp = netdev_priv(dev); 393 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
749 394 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
750 eth_port_init_mac_tables(mp);
751 eth_port_uc_addr_set(mp, dev->dev_addr);
752} 395}
753 396
754/* 397static void rxq_disable(struct rx_queue *rxq)
755 * mv643xx_eth_set_rx_mode
756 *
757 * Change from promiscuos to regular rx mode
758 *
759 * Input : pointer to ethernet interface network device structure
760 * Output : N/A
761 */
762static void mv643xx_eth_set_rx_mode(struct net_device *dev)
763{ 398{
764 struct mv643xx_private *mp = netdev_priv(dev); 399 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
765 u32 config_reg; 400 u8 mask = 1 << rxq->index;
766 401
767 config_reg = rdl(mp, PORT_CONFIG_REG(mp->port_num)); 402 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
768 if (dev->flags & IFF_PROMISC) 403 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
769 config_reg |= (u32) UNICAST_PROMISCUOUS_MODE; 404 udelay(10);
770 else
771 config_reg &= ~(u32) UNICAST_PROMISCUOUS_MODE;
772 wrl(mp, PORT_CONFIG_REG(mp->port_num), config_reg);
773
774 eth_port_set_multicast_list(dev);
775} 405}
776 406
777/* 407static void txq_enable(struct tx_queue *txq)
778 * mv643xx_eth_set_mac_address
779 *
780 * Change the interface's mac address.
781 * No special hardware thing should be done because interface is always
782 * put in promiscuous mode.
783 *
784 * Input : pointer to ethernet interface network device structure and
785 * a pointer to the designated entry to be added to the cache.
786 * Output : zero upon success, negative upon failure
787 */
788static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
789{ 408{
790 int i; 409 struct mv643xx_eth_private *mp = txq_to_mp(txq);
791 410 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
792 for (i = 0; i < 6; i++)
793 /* +2 is for the offset of the HW addr type */
794 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
795 mv643xx_eth_update_mac_address(dev);
796 return 0;
797} 411}
798 412
799/* 413static void txq_disable(struct tx_queue *txq)
800 * mv643xx_eth_tx_timeout
801 *
802 * Called upon a timeout on transmitting a packet
803 *
804 * Input : pointer to ethernet interface network device structure.
805 * Output : N/A
806 */
807static void mv643xx_eth_tx_timeout(struct net_device *dev)
808{ 414{
809 struct mv643xx_private *mp = netdev_priv(dev); 415 struct mv643xx_eth_private *mp = txq_to_mp(txq);
810 416 u8 mask = 1 << txq->index;
811 printk(KERN_INFO "%s: TX timeout ", dev->name);
812 417
813 /* Do the reset outside of interrupt context */ 418 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
814 schedule_work(&mp->tx_timeout_task); 419 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
420 udelay(10);
815} 421}
816 422
817/* 423static void __txq_maybe_wake(struct tx_queue *txq)
818 * mv643xx_eth_tx_timeout_task
819 *
820 * Actual routine to reset the adapter when a timeout on Tx has occurred
821 */
822static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
823{ 424{
824 struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private, 425 struct mv643xx_eth_private *mp = txq_to_mp(txq);
825 tx_timeout_task);
826 struct net_device *dev = mp->dev;
827 426
828 if (!netif_running(dev)) 427 /*
829 return; 428 * netif_{stop,wake}_queue() flow control only applies to
429 * the primary queue.
430 */
431 BUG_ON(txq->index != mp->txq_primary);
830 432
831 netif_stop_queue(dev); 433 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
434 netif_wake_queue(mp->dev);
435}
832 436
833 eth_port_reset(mp);
834 eth_port_start(dev);
835 437
836 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB) 438/* rx ***********************************************************************/
837 netif_wake_queue(dev); 439static void txq_reclaim(struct tx_queue *txq, int force);
838}
839 440
840/** 441static void rxq_refill(struct rx_queue *rxq)
841 * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors
842 *
843 * If force is non-zero, frees uncompleted descriptors as well
844 */
845static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
846{ 442{
847 struct mv643xx_private *mp = netdev_priv(dev); 443 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
848 struct eth_tx_desc *desc;
849 u32 cmd_sts;
850 struct sk_buff *skb;
851 unsigned long flags; 444 unsigned long flags;
852 int tx_index;
853 dma_addr_t addr;
854 int count;
855 int released = 0;
856 445
857 while (mp->tx_desc_count > 0) { 446 spin_lock_irqsave(&mp->lock, flags);
858 spin_lock_irqsave(&mp->lock, flags);
859
860 /* tx_desc_count might have changed before acquiring the lock */
861 if (mp->tx_desc_count <= 0) {
862 spin_unlock_irqrestore(&mp->lock, flags);
863 return released;
864 }
865
866 tx_index = mp->tx_used_desc_q;
867 desc = &mp->p_tx_desc_area[tx_index];
868 cmd_sts = desc->cmd_sts;
869 447
870 if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) { 448 while (rxq->rx_desc_count < rxq->rx_ring_size) {
871 spin_unlock_irqrestore(&mp->lock, flags); 449 int skb_size;
872 return released; 450 struct sk_buff *skb;
873 } 451 int unaligned;
452 int rx;
874 453
875 mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size; 454 /*
876 mp->tx_desc_count--; 455 * Reserve 2+14 bytes for an ethernet header (the
456 * hardware automatically prepends 2 bytes of dummy
457 * data to each received packet), 4 bytes for a VLAN
458 * header, and 4 bytes for the trailing FCS -- 24
459 * bytes total.
460 */
461 skb_size = mp->dev->mtu + 24;
877 462
878 addr = desc->buf_ptr; 463 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
879 count = desc->byte_cnt; 464 if (skb == NULL)
880 skb = mp->tx_skb[tx_index]; 465 break;
881 if (skb)
882 mp->tx_skb[tx_index] = NULL;
883 466
884 if (cmd_sts & ETH_ERROR_SUMMARY) { 467 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
885 printk("%s: Error in TX\n", dev->name); 468 if (unaligned)
886 dev->stats.tx_errors++; 469 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
887 }
888 470
889 spin_unlock_irqrestore(&mp->lock, flags); 471 rxq->rx_desc_count++;
472 rx = rxq->rx_used_desc;
473 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
890 474
891 if (cmd_sts & ETH_TX_FIRST_DESC) 475 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
892 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE); 476 skb_size, DMA_FROM_DEVICE);
893 else 477 rxq->rx_desc_area[rx].buf_size = skb_size;
894 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE); 478 rxq->rx_skb[rx] = skb;
479 wmb();
480 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
481 RX_ENABLE_INTERRUPT;
482 wmb();
895 483
896 if (skb) 484 /*
897 dev_kfree_skb_irq(skb); 485 * The hardware automatically prepends 2 bytes of
486 * dummy data to each received packet, so that the
487 * IP header ends up 16-byte aligned.
488 */
489 skb_reserve(skb, 2);
490 }
898 491
899 released = 1; 492 if (rxq->rx_desc_count != rxq->rx_ring_size) {
493 rxq->rx_oom.expires = jiffies + (HZ / 10);
494 add_timer(&rxq->rx_oom);
900 } 495 }
901 496
902 return released; 497 spin_unlock_irqrestore(&mp->lock, flags);
903} 498}
904 499
905static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev) 500static inline void rxq_refill_timer_wrapper(unsigned long data)
906{ 501{
907 struct mv643xx_private *mp = netdev_priv(dev); 502 rxq_refill((struct rx_queue *)data);
908
909 if (mv643xx_eth_free_tx_descs(dev, 0) &&
910 mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
911 netif_wake_queue(dev);
912} 503}
913 504
914static void mv643xx_eth_free_all_tx_descs(struct net_device *dev) 505static int rxq_process(struct rx_queue *rxq, int budget)
915{ 506{
916 mv643xx_eth_free_tx_descs(dev, 1); 507 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
917} 508 struct net_device_stats *stats = &mp->dev->stats;
509 int rx;
918 510
919/* 511 rx = 0;
920 * mv643xx_eth_receive 512 while (rx < budget) {
921 * 513 struct rx_desc *rx_desc;
922 * This function is forward packets that are received from the port's 514 unsigned int cmd_sts;
923 * queues toward kernel core or FastRoute them to another interface. 515 struct sk_buff *skb;
924 * 516 unsigned long flags;
925 * Input : dev - a pointer to the required interface 517
926 * max - maximum number to receive (0 means unlimted) 518 spin_lock_irqsave(&mp->lock, flags);
927 * 519
928 * Output : number of served packets 520 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
929 */ 521
930static int mv643xx_eth_receive_queue(struct net_device *dev, int budget) 522 cmd_sts = rx_desc->cmd_sts;
931{ 523 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
932 struct mv643xx_private *mp = netdev_priv(dev); 524 spin_unlock_irqrestore(&mp->lock, flags);
933 struct net_device_stats *stats = &dev->stats; 525 break;
934 unsigned int received_packets = 0; 526 }
935 struct sk_buff *skb; 527 rmb();
936 struct pkt_info pkt_info; 528
529 skb = rxq->rx_skb[rxq->rx_curr_desc];
530 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
937 531
938 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) { 532 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
939 dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE, 533
940 DMA_FROM_DEVICE); 534 spin_unlock_irqrestore(&mp->lock, flags);
941 mp->rx_desc_count--; 535
942 received_packets++; 536 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
537 mp->dev->mtu + 24, DMA_FROM_DEVICE);
538 rxq->rx_desc_count--;
539 rx++;
943 540
944 /* 541 /*
945 * Update statistics. 542 * Update statistics.
946 * Note byte count includes 4 byte CRC count 543 *
544 * Note that the descriptor byte count includes 2 dummy
545 * bytes automatically inserted by the hardware at the
546 * start of the packet (which we don't count), and a 4
547 * byte CRC at the end of the packet (which we do count).
947 */ 548 */
948 stats->rx_packets++; 549 stats->rx_packets++;
949 stats->rx_bytes += pkt_info.byte_cnt; 550 stats->rx_bytes += rx_desc->byte_cnt - 2;
950 skb = pkt_info.return_info; 551
951 /* 552 /*
952 * In case received a packet without first / last bits on OR 553 * In case we received a packet without first / last bits
953 * the error summary bit is on, the packets needs to be dropeed. 554 * on, or the error summary bit is set, the packet needs
555 * to be dropped.
954 */ 556 */
955 if (((pkt_info.cmd_sts 557 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
956 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != 558 (RX_FIRST_DESC | RX_LAST_DESC))
957 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) 559 || (cmd_sts & ERROR_SUMMARY)) {
958 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
959 stats->rx_dropped++; 560 stats->rx_dropped++;
960 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC | 561
961 ETH_RX_LAST_DESC)) != 562 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
962 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) { 563 (RX_FIRST_DESC | RX_LAST_DESC)) {
963 if (net_ratelimit()) 564 if (net_ratelimit())
964 printk(KERN_ERR 565 dev_printk(KERN_ERR, &mp->dev->dev,
965 "%s: Received packet spread " 566 "received packet spanning "
966 "on multiple descriptors\n", 567 "multiple descriptors\n");
967 dev->name);
968 } 568 }
969 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) 569
570 if (cmd_sts & ERROR_SUMMARY)
970 stats->rx_errors++; 571 stats->rx_errors++;
971 572
972 dev_kfree_skb_irq(skb); 573 dev_kfree_skb_irq(skb);
@@ -975,2391 +576,2003 @@ static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
975 * The -4 is for the CRC in the trailer of the 576 * The -4 is for the CRC in the trailer of the
976 * received packet 577 * received packet
977 */ 578 */
978 skb_put(skb, pkt_info.byte_cnt - 4); 579 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
979 580
980 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) { 581 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
981 skb->ip_summed = CHECKSUM_UNNECESSARY; 582 skb->ip_summed = CHECKSUM_UNNECESSARY;
982 skb->csum = htons( 583 skb->csum = htons(
983 (pkt_info.cmd_sts & 0x0007fff8) >> 3); 584 (cmd_sts & 0x0007fff8) >> 3);
984 } 585 }
985 skb->protocol = eth_type_trans(skb, dev); 586 skb->protocol = eth_type_trans(skb, mp->dev);
986#ifdef MV643XX_NAPI 587#ifdef MV643XX_ETH_NAPI
987 netif_receive_skb(skb); 588 netif_receive_skb(skb);
988#else 589#else
989 netif_rx(skb); 590 netif_rx(skb);
990#endif 591#endif
991 } 592 }
992 dev->last_rx = jiffies; 593
594 mp->dev->last_rx = jiffies;
993 } 595 }
994 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
995 596
996 return received_packets; 597 rxq_refill(rxq);
598
599 return rx;
997} 600}
998 601
999/* Set the mv643xx port configuration register for the speed/duplex mode. */ 602#ifdef MV643XX_ETH_NAPI
1000static void mv643xx_eth_update_pscr(struct net_device *dev, 603static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
1001 struct ethtool_cmd *ecmd)
1002{ 604{
1003 struct mv643xx_private *mp = netdev_priv(dev); 605 struct mv643xx_eth_private *mp;
1004 int port_num = mp->port_num; 606 int rx;
1005 u32 o_pscr, n_pscr; 607 int i;
1006 unsigned int queues;
1007 608
1008 o_pscr = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num)); 609 mp = container_of(napi, struct mv643xx_eth_private, napi);
1009 n_pscr = o_pscr;
1010 610
1011 /* clear speed, duplex and rx buffer size fields */ 611#ifdef MV643XX_ETH_TX_FAST_REFILL
1012 n_pscr &= ~(SET_MII_SPEED_TO_100 | 612 if (++mp->tx_clean_threshold > 5) {
1013 SET_GMII_SPEED_TO_1000 | 613 mp->tx_clean_threshold = 0;
1014 SET_FULL_DUPLEX_MODE | 614 for (i = 0; i < 8; i++)
1015 MAX_RX_PACKET_MASK); 615 if (mp->txq_mask & (1 << i))
1016 616 txq_reclaim(mp->txq + i, 0);
1017 if (ecmd->duplex == DUPLEX_FULL)
1018 n_pscr |= SET_FULL_DUPLEX_MODE;
1019
1020 if (ecmd->speed == SPEED_1000)
1021 n_pscr |= SET_GMII_SPEED_TO_1000 |
1022 MAX_RX_PACKET_9700BYTE;
1023 else {
1024 if (ecmd->speed == SPEED_100)
1025 n_pscr |= SET_MII_SPEED_TO_100;
1026 n_pscr |= MAX_RX_PACKET_1522BYTE;
1027 } 617 }
618#endif
1028 619
1029 if (n_pscr != o_pscr) { 620 rx = 0;
1030 if ((o_pscr & SERIAL_PORT_ENABLE) == 0) 621 for (i = 7; rx < budget && i >= 0; i--)
1031 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr); 622 if (mp->rxq_mask & (1 << i))
1032 else { 623 rx += rxq_process(mp->rxq + i, budget - rx);
1033 queues = mv643xx_eth_port_disable_tx(mp); 624
1034 625 if (rx < budget) {
1035 o_pscr &= ~SERIAL_PORT_ENABLE; 626 netif_rx_complete(mp->dev, napi);
1036 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), o_pscr); 627 wrl(mp, INT_CAUSE(mp->port_num), 0);
1037 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr); 628 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
1038 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr); 629 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
1039 if (queues)
1040 mv643xx_eth_port_enable_tx(mp, queues);
1041 }
1042 } 630 }
631
632 return rx;
1043} 633}
634#endif
1044 635
1045/*
1046 * mv643xx_eth_int_handler
1047 *
1048 * Main interrupt handler for the gigbit ethernet ports
1049 *
1050 * Input : irq - irq number (not used)
1051 * dev_id - a pointer to the required interface's data structure
1052 * regs - not used
1053 * Output : N/A
1054 */
1055 636
1056static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id) 637/* tx ***********************************************************************/
638static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1057{ 639{
1058 struct net_device *dev = (struct net_device *)dev_id; 640 int frag;
1059 struct mv643xx_private *mp = netdev_priv(dev);
1060 u32 eth_int_cause, eth_int_cause_ext = 0;
1061 unsigned int port_num = mp->port_num;
1062
1063 /* Read interrupt cause registers */
1064 eth_int_cause = rdl(mp, INTERRUPT_CAUSE_REG(port_num)) &
1065 ETH_INT_UNMASK_ALL;
1066 if (eth_int_cause & ETH_INT_CAUSE_EXT) {
1067 eth_int_cause_ext = rdl(mp,
1068 INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
1069 ETH_INT_UNMASK_ALL_EXT;
1070 wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num),
1071 ~eth_int_cause_ext);
1072 }
1073
1074 /* PHY status changed */
1075 if (eth_int_cause_ext & (ETH_INT_CAUSE_PHY | ETH_INT_CAUSE_STATE)) {
1076 struct ethtool_cmd cmd;
1077 641
1078 if (mii_link_ok(&mp->mii)) { 642 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1079 mii_ethtool_gset(&mp->mii, &cmd); 643 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
1080 mv643xx_eth_update_pscr(dev, &cmd); 644 if (fragp->size <= 8 && fragp->page_offset & 7)
1081 mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED); 645 return 1;
1082 if (!netif_carrier_ok(dev)) {
1083 netif_carrier_on(dev);
1084 if (mp->tx_ring_size - mp->tx_desc_count >=
1085 MAX_DESCS_PER_SKB)
1086 netif_wake_queue(dev);
1087 }
1088 } else if (netif_carrier_ok(dev)) {
1089 netif_stop_queue(dev);
1090 netif_carrier_off(dev);
1091 }
1092 } 646 }
1093 647
1094#ifdef MV643XX_NAPI 648 return 0;
1095 if (eth_int_cause & ETH_INT_CAUSE_RX) { 649}
1096 /* schedule the NAPI poll routine to maintain port */
1097 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
1098 650
1099 /* wait for previous write to complete */ 651static int txq_alloc_desc_index(struct tx_queue *txq)
1100 rdl(mp, INTERRUPT_MASK_REG(port_num)); 652{
653 int tx_desc_curr;
1101 654
1102 netif_rx_schedule(dev, &mp->napi); 655 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
1103 }
1104#else
1105 if (eth_int_cause & ETH_INT_CAUSE_RX)
1106 mv643xx_eth_receive_queue(dev, INT_MAX);
1107#endif
1108 if (eth_int_cause_ext & ETH_INT_CAUSE_TX)
1109 mv643xx_eth_free_completed_tx_descs(dev);
1110 656
1111 /* 657 tx_desc_curr = txq->tx_curr_desc;
1112 * If no real interrupt occured, exit. 658 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
1113 * This can happen when using gigE interrupt coalescing mechanism.
1114 */
1115 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
1116 return IRQ_NONE;
1117 659
1118 return IRQ_HANDLED; 660 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
1119}
1120 661
1121#ifdef MV643XX_COAL 662 return tx_desc_curr;
663}
1122 664
1123/* 665static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
1124 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
1125 *
1126 * DESCRIPTION:
1127 * This routine sets the RX coalescing interrupt mechanism parameter.
1128 * This parameter is a timeout counter, that counts in 64 t_clk
1129 * chunks ; that when timeout event occurs a maskable interrupt
1130 * occurs.
1131 * The parameter is calculated using the tClk of the MV-643xx chip
1132 * , and the required delay of the interrupt in usec.
1133 *
1134 * INPUT:
1135 * struct mv643xx_private *mp Ethernet port
1136 * unsigned int delay Delay in usec
1137 *
1138 * OUTPUT:
1139 * Interrupt coalescing mechanism value is set in MV-643xx chip.
1140 *
1141 * RETURN:
1142 * The interrupt coalescing value set in the gigE port.
1143 *
1144 */
1145static unsigned int eth_port_set_rx_coal(struct mv643xx_private *mp,
1146 unsigned int delay)
1147{ 666{
1148 unsigned int port_num = mp->port_num; 667 int nr_frags = skb_shinfo(skb)->nr_frags;
1149 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; 668 int frag;
1150 669
1151 /* Set RX Coalescing mechanism */ 670 for (frag = 0; frag < nr_frags; frag++) {
1152 wrl(mp, SDMA_CONFIG_REG(port_num), 671 skb_frag_t *this_frag;
1153 ((coal & 0x3fff) << 8) | 672 int tx_index;
1154 (rdl(mp, SDMA_CONFIG_REG(port_num)) 673 struct tx_desc *desc;
1155 & 0xffc000ff));
1156 674
1157 return coal; 675 this_frag = &skb_shinfo(skb)->frags[frag];
1158} 676 tx_index = txq_alloc_desc_index(txq);
1159#endif 677 desc = &txq->tx_desc_area[tx_index];
1160 678
1161/* 679 /*
1162 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path 680 * The last fragment will generate an interrupt
1163 * 681 * which will free the skb on TX completion.
1164 * DESCRIPTION: 682 */
1165 * This routine sets the TX coalescing interrupt mechanism parameter. 683 if (frag == nr_frags - 1) {
1166 * This parameter is a timeout counter, that counts in 64 t_clk 684 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
1167 * chunks ; that when timeout event occurs a maskable interrupt 685 ZERO_PADDING | TX_LAST_DESC |
1168 * occurs. 686 TX_ENABLE_INTERRUPT;
1169 * The parameter is calculated using the t_cLK frequency of the 687 txq->tx_skb[tx_index] = skb;
1170 * MV-643xx chip and the required delay in the interrupt in uSec 688 } else {
1171 * 689 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
1172 * INPUT: 690 txq->tx_skb[tx_index] = NULL;
1173 * struct mv643xx_private *mp Ethernet port 691 }
1174 * unsigned int delay Delay in uSeconds
1175 *
1176 * OUTPUT:
1177 * Interrupt coalescing mechanism value is set in MV-643xx chip.
1178 *
1179 * RETURN:
1180 * The interrupt coalescing value set in the gigE port.
1181 *
1182 */
1183static unsigned int eth_port_set_tx_coal(struct mv643xx_private *mp,
1184 unsigned int delay)
1185{
1186 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1187 692
1188 /* Set TX Coalescing mechanism */ 693 desc->l4i_chk = 0;
1189 wrl(mp, TX_FIFO_URGENT_THRESHOLD_REG(mp->port_num), coal << 4); 694 desc->byte_cnt = this_frag->size;
695 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
696 this_frag->page_offset,
697 this_frag->size,
698 DMA_TO_DEVICE);
699 }
700}
1190 701
1191 return coal; 702static inline __be16 sum16_as_be(__sum16 sum)
703{
704 return (__force __be16)sum;
1192} 705}
1193 706
1194/* 707static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1195 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
1196 *
1197 * DESCRIPTION:
1198 * This function prepares a Rx chained list of descriptors and packet
1199 * buffers in a form of a ring. The routine must be called after port
1200 * initialization routine and before port start routine.
1201 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1202 * devices in the system (i.e. DRAM). This function uses the ethernet
1203 * struct 'virtual to physical' routine (set by the user) to set the ring
1204 * with physical addresses.
1205 *
1206 * INPUT:
1207 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1208 *
1209 * OUTPUT:
1210 * The routine updates the Ethernet port control struct with information
1211 * regarding the Rx descriptors and buffers.
1212 *
1213 * RETURN:
1214 * None.
1215 */
1216static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
1217{ 708{
1218 volatile struct eth_rx_desc *p_rx_desc; 709 int nr_frags = skb_shinfo(skb)->nr_frags;
1219 int rx_desc_num = mp->rx_ring_size; 710 int tx_index;
1220 int i; 711 struct tx_desc *desc;
712 u32 cmd_sts;
713 int length;
1221 714
1222 /* initialize the next_desc_ptr links in the Rx descriptors ring */ 715 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
1223 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area; 716
1224 for (i = 0; i < rx_desc_num; i++) { 717 tx_index = txq_alloc_desc_index(txq);
1225 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma + 718 desc = &txq->tx_desc_area[tx_index];
1226 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc); 719
720 if (nr_frags) {
721 txq_submit_frag_skb(txq, skb);
722
723 length = skb_headlen(skb);
724 txq->tx_skb[tx_index] = NULL;
725 } else {
726 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
727 length = skb->len;
728 txq->tx_skb[tx_index] = skb;
1227 } 729 }
1228 730
1229 /* Save Rx desc pointer to driver struct. */ 731 desc->byte_cnt = length;
1230 mp->rx_curr_desc_q = 0; 732 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
1231 mp->rx_used_desc_q = 0;
1232 733
1233 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc); 734 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1234} 735 BUG_ON(skb->protocol != htons(ETH_P_IP));
1235 736
1236/* 737 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
1237 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. 738 GEN_IP_V4_CHECKSUM |
1238 * 739 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
1239 * DESCRIPTION:
1240 * This function prepares a Tx chained list of descriptors and packet
1241 * buffers in a form of a ring. The routine must be called after port
1242 * initialization routine and before port start routine.
1243 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1244 * devices in the system (i.e. DRAM). This function uses the ethernet
1245 * struct 'virtual to physical' routine (set by the user) to set the ring
1246 * with physical addresses.
1247 *
1248 * INPUT:
1249 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1250 *
1251 * OUTPUT:
1252 * The routine updates the Ethernet port control struct with information
1253 * regarding the Tx descriptors and buffers.
1254 *
1255 * RETURN:
1256 * None.
1257 */
1258static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
1259{
1260 int tx_desc_num = mp->tx_ring_size;
1261 struct eth_tx_desc *p_tx_desc;
1262 int i;
1263 740
1264 /* Initialize the next_desc_ptr links in the Tx descriptors ring */ 741 switch (ip_hdr(skb)->protocol) {
1265 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area; 742 case IPPROTO_UDP:
1266 for (i = 0; i < tx_desc_num; i++) { 743 cmd_sts |= UDP_FRAME;
1267 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma + 744 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
1268 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc); 745 break;
746 case IPPROTO_TCP:
747 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
748 break;
749 default:
750 BUG();
751 }
752 } else {
753 /* Errata BTS #50, IHL must be 5 if no HW checksum */
754 cmd_sts |= 5 << TX_IHL_SHIFT;
755 desc->l4i_chk = 0;
1269 } 756 }
1270 757
1271 mp->tx_curr_desc_q = 0; 758 /* ensure all other descriptors are written before first cmd_sts */
1272 mp->tx_used_desc_q = 0; 759 wmb();
760 desc->cmd_sts = cmd_sts;
761
762 /* ensure all descriptors are written before poking hardware */
763 wmb();
764 txq_enable(txq);
1273 765
1274 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc); 766 txq->tx_desc_count += nr_frags + 1;
1275} 767}
1276 768
1277static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 769static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1278{ 770{
1279 struct mv643xx_private *mp = netdev_priv(dev); 771 struct mv643xx_eth_private *mp = netdev_priv(dev);
1280 int err; 772 struct net_device_stats *stats = &dev->stats;
773 struct tx_queue *txq;
774 unsigned long flags;
1281 775
1282 spin_lock_irq(&mp->lock); 776 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
1283 err = mii_ethtool_sset(&mp->mii, cmd); 777 stats->tx_dropped++;
1284 spin_unlock_irq(&mp->lock); 778 dev_printk(KERN_DEBUG, &dev->dev,
779 "failed to linearize skb with tiny "
780 "unaligned fragment\n");
781 return NETDEV_TX_BUSY;
782 }
1285 783
1286 return err; 784 spin_lock_irqsave(&mp->lock, flags);
1287}
1288 785
1289static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 786 txq = mp->txq + mp->txq_primary;
1290{
1291 struct mv643xx_private *mp = netdev_priv(dev);
1292 int err;
1293 787
1294 spin_lock_irq(&mp->lock); 788 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
1295 err = mii_ethtool_gset(&mp->mii, cmd); 789 spin_unlock_irqrestore(&mp->lock, flags);
1296 spin_unlock_irq(&mp->lock); 790 if (txq->index == mp->txq_primary && net_ratelimit())
791 dev_printk(KERN_ERR, &dev->dev,
792 "primary tx queue full?!\n");
793 kfree_skb(skb);
794 return NETDEV_TX_OK;
795 }
1297 796
1298 /* The PHY may support 1000baseT_Half, but the mv643xx does not */ 797 txq_submit_skb(txq, skb);
1299 cmd->supported &= ~SUPPORTED_1000baseT_Half; 798 stats->tx_bytes += skb->len;
1300 cmd->advertising &= ~ADVERTISED_1000baseT_Half; 799 stats->tx_packets++;
800 dev->trans_start = jiffies;
1301 801
1302 return err; 802 if (txq->index == mp->txq_primary) {
803 int entries_left;
804
805 entries_left = txq->tx_ring_size - txq->tx_desc_count;
806 if (entries_left < MAX_DESCS_PER_SKB)
807 netif_stop_queue(dev);
808 }
809
810 spin_unlock_irqrestore(&mp->lock, flags);
811
812 return NETDEV_TX_OK;
1303} 813}
1304 814
815
816/* tx rate control **********************************************************/
1305/* 817/*
1306 * mv643xx_eth_open 818 * Set total maximum TX rate (shared by all TX queues for this port)
1307 * 819 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1308 * This function is called when openning the network device. The function
1309 * should initialize all the hardware, initialize cyclic Rx/Tx
1310 * descriptors chain and buffers and allocate an IRQ to the network
1311 * device.
1312 *
1313 * Input : a pointer to the network device structure
1314 *
1315 * Output : zero of success , nonzero if fails.
1316 */ 820 */
1317 821static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1318static int mv643xx_eth_open(struct net_device *dev)
1319{ 822{
1320 struct mv643xx_private *mp = netdev_priv(dev); 823 int token_rate;
1321 unsigned int port_num = mp->port_num; 824 int mtu;
1322 unsigned int size; 825 int bucket_size;
1323 int err;
1324 826
1325 /* Clear any pending ethernet port interrupts */ 827 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1326 wrl(mp, INTERRUPT_CAUSE_REG(port_num), 0); 828 if (token_rate > 1023)
1327 wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); 829 token_rate = 1023;
1328 /* wait for previous write to complete */
1329 rdl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num));
1330 830
1331 err = request_irq(dev->irq, mv643xx_eth_int_handler, 831 mtu = (mp->dev->mtu + 255) >> 8;
1332 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev); 832 if (mtu > 63)
1333 if (err) { 833 mtu = 63;
1334 printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name);
1335 return -EAGAIN;
1336 }
1337 834
1338 eth_port_init(mp); 835 bucket_size = (burst + 255) >> 8;
836 if (bucket_size > 65535)
837 bucket_size = 65535;
1339 838
1340 memset(&mp->timeout, 0, sizeof(struct timer_list)); 839 if (mp->shared->tx_bw_control_moved) {
1341 mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper; 840 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
1342 mp->timeout.data = (unsigned long)dev; 841 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
1343 842 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
1344 /* Allocate RX and TX skb rings */ 843 } else {
1345 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size, 844 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
1346 GFP_KERNEL); 845 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
1347 if (!mp->rx_skb) { 846 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
1348 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
1349 err = -ENOMEM;
1350 goto out_free_irq;
1351 }
1352 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
1353 GFP_KERNEL);
1354 if (!mp->tx_skb) {
1355 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
1356 err = -ENOMEM;
1357 goto out_free_rx_skb;
1358 } 847 }
848}
1359 849
1360 /* Allocate TX ring */ 850static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1361 mp->tx_desc_count = 0; 851{
1362 size = mp->tx_ring_size * sizeof(struct eth_tx_desc); 852 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1363 mp->tx_desc_area_size = size; 853 int token_rate;
1364 854 int bucket_size;
1365 if (mp->tx_sram_size) {
1366 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
1367 mp->tx_sram_size);
1368 mp->tx_desc_dma = mp->tx_sram_addr;
1369 } else
1370 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
1371 &mp->tx_desc_dma,
1372 GFP_KERNEL);
1373 855
1374 if (!mp->p_tx_desc_area) { 856 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1375 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n", 857 if (token_rate > 1023)
1376 dev->name, size); 858 token_rate = 1023;
1377 err = -ENOMEM;
1378 goto out_free_tx_skb;
1379 }
1380 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
1381 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
1382
1383 ether_init_tx_desc_ring(mp);
1384
1385 /* Allocate RX ring */
1386 mp->rx_desc_count = 0;
1387 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
1388 mp->rx_desc_area_size = size;
1389
1390 if (mp->rx_sram_size) {
1391 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
1392 mp->rx_sram_size);
1393 mp->rx_desc_dma = mp->rx_sram_addr;
1394 } else
1395 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
1396 &mp->rx_desc_dma,
1397 GFP_KERNEL);
1398 859
1399 if (!mp->p_rx_desc_area) { 860 bucket_size = (burst + 255) >> 8;
1400 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n", 861 if (bucket_size > 65535)
1401 dev->name, size); 862 bucket_size = 65535;
1402 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
1403 dev->name);
1404 if (mp->rx_sram_size)
1405 iounmap(mp->p_tx_desc_area);
1406 else
1407 dma_free_coherent(NULL, mp->tx_desc_area_size,
1408 mp->p_tx_desc_area, mp->tx_desc_dma);
1409 err = -ENOMEM;
1410 goto out_free_tx_skb;
1411 }
1412 memset((void *)mp->p_rx_desc_area, 0, size);
1413 863
1414 ether_init_rx_desc_ring(mp); 864 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
1415 865 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
1416 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */ 866 (bucket_size << 10) | token_rate);
867}
1417 868
1418#ifdef MV643XX_NAPI 869static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1419 napi_enable(&mp->napi); 870{
1420#endif 871 struct mv643xx_eth_private *mp = txq_to_mp(txq);
872 int off;
873 u32 val;
1421 874
1422 eth_port_start(dev); 875 /*
876 * Turn on fixed priority mode.
877 */
878 if (mp->shared->tx_bw_control_moved)
879 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
880 else
881 off = TXQ_FIX_PRIO_CONF(mp->port_num);
1423 882
1424 /* Interrupt Coalescing */ 883 val = rdl(mp, off);
884 val |= 1 << txq->index;
885 wrl(mp, off, val);
886}
1425 887
1426#ifdef MV643XX_COAL 888static void txq_set_wrr(struct tx_queue *txq, int weight)
1427 mp->rx_int_coal = 889{
1428 eth_port_set_rx_coal(mp, MV643XX_RX_COAL); 890 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1429#endif 891 int off;
892 u32 val;
1430 893
1431 mp->tx_int_coal = 894 /*
1432 eth_port_set_tx_coal(mp, MV643XX_TX_COAL); 895 * Turn off fixed priority mode.
896 */
897 if (mp->shared->tx_bw_control_moved)
898 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
899 else
900 off = TXQ_FIX_PRIO_CONF(mp->port_num);
1433 901
1434 /* Unmask phy and link status changes interrupts */ 902 val = rdl(mp, off);
1435 wrl(mp, INTERRUPT_EXTEND_MASK_REG(port_num), ETH_INT_UNMASK_ALL_EXT); 903 val &= ~(1 << txq->index);
904 wrl(mp, off, val);
1436 905
1437 /* Unmask RX buffer and TX end interrupt */ 906 /*
1438 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); 907 * Configure WRR weight for this queue.
908 */
909 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
1439 910
1440 return 0; 911 val = rdl(mp, off);
912 val = (val & ~0xff) | (weight & 0xff);
913 wrl(mp, off, val);
914}
1441 915
1442out_free_tx_skb:
1443 kfree(mp->tx_skb);
1444out_free_rx_skb:
1445 kfree(mp->rx_skb);
1446out_free_irq:
1447 free_irq(dev->irq, dev);
1448 916
1449 return err; 917/* mii management interface *************************************************/
1450} 918#define SMI_BUSY 0x10000000
919#define SMI_READ_VALID 0x08000000
920#define SMI_OPCODE_READ 0x04000000
921#define SMI_OPCODE_WRITE 0x00000000
1451 922
1452static void mv643xx_eth_free_tx_rings(struct net_device *dev) 923static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
924 unsigned int reg, unsigned int *value)
1453{ 925{
1454 struct mv643xx_private *mp = netdev_priv(dev); 926 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
927 unsigned long flags;
928 int i;
1455 929
1456 /* Stop Tx Queues */ 930 /* the SMI register is a shared resource */
1457 mv643xx_eth_port_disable_tx(mp); 931 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
1458 932
1459 /* Free outstanding skb's on TX ring */ 933 /* wait for the SMI register to become available */
1460 mv643xx_eth_free_all_tx_descs(dev); 934 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
935 if (i == 1000) {
936 printk("%s: PHY busy timeout\n", mp->dev->name);
937 goto out;
938 }
939 udelay(10);
940 }
1461 941
1462 BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q); 942 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1463 943
1464 /* Free TX ring */ 944 /* now wait for the data to be valid */
1465 if (mp->tx_sram_size) 945 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
1466 iounmap(mp->p_tx_desc_area); 946 if (i == 1000) {
1467 else 947 printk("%s: PHY read timeout\n", mp->dev->name);
1468 dma_free_coherent(NULL, mp->tx_desc_area_size, 948 goto out;
1469 mp->p_tx_desc_area, mp->tx_desc_dma); 949 }
950 udelay(10);
951 }
952
953 *value = readl(smi_reg) & 0xffff;
954out:
955 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1470} 956}
1471 957
1472static void mv643xx_eth_free_rx_rings(struct net_device *dev) 958static void smi_reg_write(struct mv643xx_eth_private *mp,
959 unsigned int addr,
960 unsigned int reg, unsigned int value)
1473{ 961{
1474 struct mv643xx_private *mp = netdev_priv(dev); 962 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
1475 int curr; 963 unsigned long flags;
964 int i;
1476 965
1477 /* Stop RX Queues */ 966 /* the SMI register is a shared resource */
1478 mv643xx_eth_port_disable_rx(mp); 967 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
1479 968
1480 /* Free preallocated skb's on RX rings */ 969 /* wait for the SMI register to become available */
1481 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) { 970 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
1482 if (mp->rx_skb[curr]) { 971 if (i == 1000) {
1483 dev_kfree_skb(mp->rx_skb[curr]); 972 printk("%s: PHY busy timeout\n", mp->dev->name);
1484 mp->rx_desc_count--; 973 goto out;
1485 } 974 }
975 udelay(10);
1486 } 976 }
1487 977
1488 if (mp->rx_desc_count) 978 writel(SMI_OPCODE_WRITE | (reg << 21) |
1489 printk(KERN_ERR 979 (addr << 16) | (value & 0xffff), smi_reg);
1490 "%s: Error in freeing Rx Ring. %d skb's still" 980out:
1491 " stuck in RX Ring - ignoring them\n", dev->name, 981 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1492 mp->rx_desc_count);
1493 /* Free RX ring */
1494 if (mp->rx_sram_size)
1495 iounmap(mp->p_rx_desc_area);
1496 else
1497 dma_free_coherent(NULL, mp->rx_desc_area_size,
1498 mp->p_rx_desc_area, mp->rx_desc_dma);
1499} 982}
1500 983
1501/*
1502 * mv643xx_eth_stop
1503 *
1504 * This function is used when closing the network device.
1505 * It updates the hardware,
1506 * release all memory that holds buffers and descriptors and release the IRQ.
1507 * Input : a pointer to the device structure
1508 * Output : zero if success , nonzero if fails
1509 */
1510 984
1511static int mv643xx_eth_stop(struct net_device *dev) 985/* mib counters *************************************************************/
986static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1512{ 987{
1513 struct mv643xx_private *mp = netdev_priv(dev); 988 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1514 unsigned int port_num = mp->port_num; 989}
1515 990
1516 /* Mask all interrupts on ethernet port */ 991static void mib_counters_clear(struct mv643xx_eth_private *mp)
1517 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); 992{
1518 /* wait for previous write to complete */ 993 int i;
1519 rdl(mp, INTERRUPT_MASK_REG(port_num));
1520 994
1521#ifdef MV643XX_NAPI 995 for (i = 0; i < 0x80; i += 4)
1522 napi_disable(&mp->napi); 996 mib_read(mp, i);
1523#endif 997}
1524 netif_carrier_off(dev); 998
1525 netif_stop_queue(dev); 999static void mib_counters_update(struct mv643xx_eth_private *mp)
1000{
1001 struct mib_counters *p = &mp->mib_counters;
1002
1003 p->good_octets_received += mib_read(mp, 0x00);
1004 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1005 p->bad_octets_received += mib_read(mp, 0x08);
1006 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1007 p->good_frames_received += mib_read(mp, 0x10);
1008 p->bad_frames_received += mib_read(mp, 0x14);
1009 p->broadcast_frames_received += mib_read(mp, 0x18);
1010 p->multicast_frames_received += mib_read(mp, 0x1c);
1011 p->frames_64_octets += mib_read(mp, 0x20);
1012 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1013 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1014 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1015 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1016 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1017 p->good_octets_sent += mib_read(mp, 0x38);
1018 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1019 p->good_frames_sent += mib_read(mp, 0x40);
1020 p->excessive_collision += mib_read(mp, 0x44);
1021 p->multicast_frames_sent += mib_read(mp, 0x48);
1022 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1023 p->unrec_mac_control_received += mib_read(mp, 0x50);
1024 p->fc_sent += mib_read(mp, 0x54);
1025 p->good_fc_received += mib_read(mp, 0x58);
1026 p->bad_fc_received += mib_read(mp, 0x5c);
1027 p->undersize_received += mib_read(mp, 0x60);
1028 p->fragments_received += mib_read(mp, 0x64);
1029 p->oversize_received += mib_read(mp, 0x68);
1030 p->jabber_received += mib_read(mp, 0x6c);
1031 p->mac_receive_error += mib_read(mp, 0x70);
1032 p->bad_crc_event += mib_read(mp, 0x74);
1033 p->collision += mib_read(mp, 0x78);
1034 p->late_collision += mib_read(mp, 0x7c);
1035}
1036
1037
1038/* ethtool ******************************************************************/
1039struct mv643xx_eth_stats {
1040 char stat_string[ETH_GSTRING_LEN];
1041 int sizeof_stat;
1042 int netdev_off;
1043 int mp_off;
1044};
1045
1046#define SSTAT(m) \
1047 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1048 offsetof(struct net_device, stats.m), -1 }
1049
1050#define MIBSTAT(m) \
1051 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1052 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1053
1054static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1055 SSTAT(rx_packets),
1056 SSTAT(tx_packets),
1057 SSTAT(rx_bytes),
1058 SSTAT(tx_bytes),
1059 SSTAT(rx_errors),
1060 SSTAT(tx_errors),
1061 SSTAT(rx_dropped),
1062 SSTAT(tx_dropped),
1063 MIBSTAT(good_octets_received),
1064 MIBSTAT(bad_octets_received),
1065 MIBSTAT(internal_mac_transmit_err),
1066 MIBSTAT(good_frames_received),
1067 MIBSTAT(bad_frames_received),
1068 MIBSTAT(broadcast_frames_received),
1069 MIBSTAT(multicast_frames_received),
1070 MIBSTAT(frames_64_octets),
1071 MIBSTAT(frames_65_to_127_octets),
1072 MIBSTAT(frames_128_to_255_octets),
1073 MIBSTAT(frames_256_to_511_octets),
1074 MIBSTAT(frames_512_to_1023_octets),
1075 MIBSTAT(frames_1024_to_max_octets),
1076 MIBSTAT(good_octets_sent),
1077 MIBSTAT(good_frames_sent),
1078 MIBSTAT(excessive_collision),
1079 MIBSTAT(multicast_frames_sent),
1080 MIBSTAT(broadcast_frames_sent),
1081 MIBSTAT(unrec_mac_control_received),
1082 MIBSTAT(fc_sent),
1083 MIBSTAT(good_fc_received),
1084 MIBSTAT(bad_fc_received),
1085 MIBSTAT(undersize_received),
1086 MIBSTAT(fragments_received),
1087 MIBSTAT(oversize_received),
1088 MIBSTAT(jabber_received),
1089 MIBSTAT(mac_receive_error),
1090 MIBSTAT(bad_crc_event),
1091 MIBSTAT(collision),
1092 MIBSTAT(late_collision),
1093};
1526 1094
1527 eth_port_reset(mp); 1095static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1096{
1097 struct mv643xx_eth_private *mp = netdev_priv(dev);
1098 int err;
1528 1099
1529 mv643xx_eth_free_tx_rings(dev); 1100 spin_lock_irq(&mp->lock);
1530 mv643xx_eth_free_rx_rings(dev); 1101 err = mii_ethtool_gset(&mp->mii, cmd);
1102 spin_unlock_irq(&mp->lock);
1531 1103
1532 free_irq(dev->irq, dev); 1104 /*
1105 * The MAC does not support 1000baseT_Half.
1106 */
1107 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1108 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1109
1110 return err;
1111}
1112
1113static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1114{
1115 cmd->supported = SUPPORTED_MII;
1116 cmd->advertising = ADVERTISED_MII;
1117 cmd->speed = SPEED_1000;
1118 cmd->duplex = DUPLEX_FULL;
1119 cmd->port = PORT_MII;
1120 cmd->phy_address = 0;
1121 cmd->transceiver = XCVR_INTERNAL;
1122 cmd->autoneg = AUTONEG_DISABLE;
1123 cmd->maxtxpkt = 1;
1124 cmd->maxrxpkt = 1;
1533 1125
1534 return 0; 1126 return 0;
1535} 1127}
1536 1128
1537#ifdef MV643XX_NAPI 1129static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1538/*
1539 * mv643xx_poll
1540 *
1541 * This function is used in case of NAPI
1542 */
1543static int mv643xx_poll(struct napi_struct *napi, int budget)
1544{ 1130{
1545 struct mv643xx_private *mp = container_of(napi, struct mv643xx_private, napi); 1131 struct mv643xx_eth_private *mp = netdev_priv(dev);
1546 struct net_device *dev = mp->dev; 1132 int err;
1547 unsigned int port_num = mp->port_num;
1548 int work_done;
1549 1133
1550#ifdef MV643XX_TX_FAST_REFILL 1134 /*
1551 if (++mp->tx_clean_threshold > 5) { 1135 * The MAC does not support 1000baseT_Half.
1552 mv643xx_eth_free_completed_tx_descs(dev); 1136 */
1553 mp->tx_clean_threshold = 0; 1137 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1554 }
1555#endif
1556 1138
1557 work_done = 0; 1139 spin_lock_irq(&mp->lock);
1558 if ((rdl(mp, RX_CURRENT_QUEUE_DESC_PTR_0(port_num))) 1140 err = mii_ethtool_sset(&mp->mii, cmd);
1559 != (u32) mp->rx_used_desc_q) 1141 spin_unlock_irq(&mp->lock);
1560 work_done = mv643xx_eth_receive_queue(dev, budget);
1561 1142
1562 if (work_done < budget) { 1143 return err;
1563 netif_rx_complete(dev, napi); 1144}
1564 wrl(mp, INTERRUPT_CAUSE_REG(port_num), 0);
1565 wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1566 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
1567 }
1568 1145
1569 return work_done; 1146static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1147{
1148 return -EINVAL;
1570} 1149}
1571#endif
1572 1150
1573/** 1151static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1574 * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments 1152 struct ethtool_drvinfo *drvinfo)
1575 * 1153{
1576 * Hardware can't handle unaligned fragments smaller than 9 bytes. 1154 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1577 * This helper function detects that case. 1155 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1578 */ 1156 strncpy(drvinfo->fw_version, "N/A", 32);
1157 strncpy(drvinfo->bus_info, "platform", 32);
1158 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1159}
1579 1160
1580static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) 1161static int mv643xx_eth_nway_reset(struct net_device *dev)
1581{ 1162{
1582 unsigned int frag; 1163 struct mv643xx_eth_private *mp = netdev_priv(dev);
1583 skb_frag_t *fragp;
1584 1164
1585 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { 1165 return mii_nway_restart(&mp->mii);
1586 fragp = &skb_shinfo(skb)->frags[frag];
1587 if (fragp->size <= 8 && fragp->page_offset & 0x7)
1588 return 1;
1589 }
1590 return 0;
1591} 1166}
1592 1167
1593/** 1168static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1594 * eth_alloc_tx_desc_index - return the index of the next available tx desc
1595 */
1596static int eth_alloc_tx_desc_index(struct mv643xx_private *mp)
1597{ 1169{
1598 int tx_desc_curr; 1170 return -EINVAL;
1599 1171}
1600 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
1601 1172
1602 tx_desc_curr = mp->tx_curr_desc_q; 1173static u32 mv643xx_eth_get_link(struct net_device *dev)
1603 mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size; 1174{
1175 struct mv643xx_eth_private *mp = netdev_priv(dev);
1604 1176
1605 BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q); 1177 return mii_link_ok(&mp->mii);
1178}
1606 1179
1607 return tx_desc_curr; 1180static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1181{
1182 return 1;
1608} 1183}
1609 1184
1610/** 1185static void mv643xx_eth_get_strings(struct net_device *dev,
1611 * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments. 1186 uint32_t stringset, uint8_t *data)
1612 *
1613 * Ensure the data for each fragment to be transmitted is mapped properly,
1614 * then fill in descriptors in the tx hw queue.
1615 */
1616static void eth_tx_fill_frag_descs(struct mv643xx_private *mp,
1617 struct sk_buff *skb)
1618{ 1187{
1619 int frag; 1188 int i;
1620 int tx_index;
1621 struct eth_tx_desc *desc;
1622 1189
1623 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { 1190 if (stringset == ETH_SS_STATS) {
1624 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; 1191 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1625 1192 memcpy(data + i * ETH_GSTRING_LEN,
1626 tx_index = eth_alloc_tx_desc_index(mp); 1193 mv643xx_eth_stats[i].stat_string,
1627 desc = &mp->p_tx_desc_area[tx_index]; 1194 ETH_GSTRING_LEN);
1628 1195 }
1629 desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA;
1630 /* Last Frag enables interrupt and frees the skb */
1631 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1632 desc->cmd_sts |= ETH_ZERO_PADDING |
1633 ETH_TX_LAST_DESC |
1634 ETH_TX_ENABLE_INTERRUPT;
1635 mp->tx_skb[tx_index] = skb;
1636 } else
1637 mp->tx_skb[tx_index] = NULL;
1638
1639 desc = &mp->p_tx_desc_area[tx_index];
1640 desc->l4i_chk = 0;
1641 desc->byte_cnt = this_frag->size;
1642 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
1643 this_frag->page_offset,
1644 this_frag->size,
1645 DMA_TO_DEVICE);
1646 } 1196 }
1647} 1197}
1648 1198
1649static inline __be16 sum16_as_be(__sum16 sum) 1199static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1200 struct ethtool_stats *stats,
1201 uint64_t *data)
1650{ 1202{
1651 return (__force __be16)sum; 1203 struct mv643xx_eth_private *mp = dev->priv;
1652} 1204 int i;
1653 1205
1654/** 1206 mib_counters_update(mp);
1655 * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw
1656 *
1657 * Ensure the data for an skb to be transmitted is mapped properly,
1658 * then fill in descriptors in the tx hw queue and start the hardware.
1659 */
1660static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp,
1661 struct sk_buff *skb)
1662{
1663 int tx_index;
1664 struct eth_tx_desc *desc;
1665 u32 cmd_sts;
1666 int length;
1667 int nr_frags = skb_shinfo(skb)->nr_frags;
1668 1207
1669 cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA; 1208 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1209 const struct mv643xx_eth_stats *stat;
1210 void *p;
1670 1211
1671 tx_index = eth_alloc_tx_desc_index(mp); 1212 stat = mv643xx_eth_stats + i;
1672 desc = &mp->p_tx_desc_area[tx_index];
1673 1213
1674 if (nr_frags) { 1214 if (stat->netdev_off >= 0)
1675 eth_tx_fill_frag_descs(mp, skb); 1215 p = ((void *)mp->dev) + stat->netdev_off;
1216 else
1217 p = ((void *)mp) + stat->mp_off;
1676 1218
1677 length = skb_headlen(skb); 1219 data[i] = (stat->sizeof_stat == 8) ?
1678 mp->tx_skb[tx_index] = NULL; 1220 *(uint64_t *)p : *(uint32_t *)p;
1679 } else {
1680 cmd_sts |= ETH_ZERO_PADDING |
1681 ETH_TX_LAST_DESC |
1682 ETH_TX_ENABLE_INTERRUPT;
1683 length = skb->len;
1684 mp->tx_skb[tx_index] = skb;
1685 } 1221 }
1222}
1686 1223
1687 desc->byte_cnt = length; 1224static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1688 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); 1225{
1226 if (sset == ETH_SS_STATS)
1227 return ARRAY_SIZE(mv643xx_eth_stats);
1689 1228
1690 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1229 return -EOPNOTSUPP;
1691 BUG_ON(skb->protocol != htons(ETH_P_IP)); 1230}
1692 1231
1693 cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM | 1232static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1694 ETH_GEN_IP_V_4_CHECKSUM | 1233 .get_settings = mv643xx_eth_get_settings,
1695 ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT; 1234 .set_settings = mv643xx_eth_set_settings,
1235 .get_drvinfo = mv643xx_eth_get_drvinfo,
1236 .nway_reset = mv643xx_eth_nway_reset,
1237 .get_link = mv643xx_eth_get_link,
1238 .set_sg = ethtool_op_set_sg,
1239 .get_strings = mv643xx_eth_get_strings,
1240 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1241 .get_sset_count = mv643xx_eth_get_sset_count,
1242};
1696 1243
1697 switch (ip_hdr(skb)->protocol) { 1244static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1698 case IPPROTO_UDP: 1245 .get_settings = mv643xx_eth_get_settings_phyless,
1699 cmd_sts |= ETH_UDP_FRAME; 1246 .set_settings = mv643xx_eth_set_settings_phyless,
1700 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check)); 1247 .get_drvinfo = mv643xx_eth_get_drvinfo,
1701 break; 1248 .nway_reset = mv643xx_eth_nway_reset_phyless,
1702 case IPPROTO_TCP: 1249 .get_link = mv643xx_eth_get_link_phyless,
1703 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check)); 1250 .set_sg = ethtool_op_set_sg,
1704 break; 1251 .get_strings = mv643xx_eth_get_strings,
1705 default: 1252 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1706 BUG(); 1253 .get_sset_count = mv643xx_eth_get_sset_count,
1707 } 1254};
1708 } else {
1709 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1710 cmd_sts |= 5 << ETH_TX_IHL_SHIFT;
1711 desc->l4i_chk = 0;
1712 }
1713 1255
1714 /* ensure all other descriptors are written before first cmd_sts */
1715 wmb();
1716 desc->cmd_sts = cmd_sts;
1717 1256
1718 /* ensure all descriptors are written before poking hardware */ 1257/* address handling *********************************************************/
1719 wmb(); 1258static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1720 mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED); 1259{
1260 unsigned int mac_h;
1261 unsigned int mac_l;
1262
1263 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1264 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1721 1265
1722 mp->tx_desc_count += nr_frags + 1; 1266 addr[0] = (mac_h >> 24) & 0xff;
1267 addr[1] = (mac_h >> 16) & 0xff;
1268 addr[2] = (mac_h >> 8) & 0xff;
1269 addr[3] = mac_h & 0xff;
1270 addr[4] = (mac_l >> 8) & 0xff;
1271 addr[5] = mac_l & 0xff;
1723} 1272}
1724 1273
1725/** 1274static void init_mac_tables(struct mv643xx_eth_private *mp)
1726 * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission
1727 *
1728 */
1729static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1730{ 1275{
1731 struct mv643xx_private *mp = netdev_priv(dev); 1276 int i;
1732 struct net_device_stats *stats = &dev->stats;
1733 unsigned long flags;
1734
1735 BUG_ON(netif_queue_stopped(dev));
1736 1277
1737 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { 1278 for (i = 0; i < 0x100; i += 4) {
1738 stats->tx_dropped++; 1279 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1739 printk(KERN_DEBUG "%s: failed to linearize tiny " 1280 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1740 "unaligned fragment\n", dev->name);
1741 return NETDEV_TX_BUSY;
1742 } 1281 }
1743 1282
1744 spin_lock_irqsave(&mp->lock, flags); 1283 for (i = 0; i < 0x10; i += 4)
1284 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1285}
1745 1286
1746 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) { 1287static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1747 printk(KERN_ERR "%s: transmit with queue full\n", dev->name); 1288 int table, unsigned char entry)
1748 netif_stop_queue(dev); 1289{
1749 spin_unlock_irqrestore(&mp->lock, flags); 1290 unsigned int table_reg;
1750 return NETDEV_TX_BUSY;
1751 }
1752 1291
1753 eth_tx_submit_descs_for_skb(mp, skb); 1292 /* Set "accepts frame bit" at specified table entry */
1754 stats->tx_bytes += skb->len; 1293 table_reg = rdl(mp, table + (entry & 0xfc));
1755 stats->tx_packets++; 1294 table_reg |= 0x01 << (8 * (entry & 3));
1756 dev->trans_start = jiffies; 1295 wrl(mp, table + (entry & 0xfc), table_reg);
1296}
1757 1297
1758 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) 1298static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1759 netif_stop_queue(dev); 1299{
1300 unsigned int mac_h;
1301 unsigned int mac_l;
1302 int table;
1760 1303
1761 spin_unlock_irqrestore(&mp->lock, flags); 1304 mac_l = (addr[4] << 8) | addr[5];
1305 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1762 1306
1763 return NETDEV_TX_OK; 1307 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1308 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1309
1310 table = UNICAST_TABLE(mp->port_num);
1311 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1764} 1312}
1765 1313
1766#ifdef CONFIG_NET_POLL_CONTROLLER 1314static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1767static void mv643xx_netpoll(struct net_device *netdev)
1768{ 1315{
1769 struct mv643xx_private *mp = netdev_priv(netdev); 1316 struct mv643xx_eth_private *mp = netdev_priv(dev);
1770 int port_num = mp->port_num;
1771 1317
1772 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); 1318 /* +2 is for the offset of the HW addr type */
1773 /* wait for previous write to complete */ 1319 memcpy(dev->dev_addr, addr + 2, 6);
1774 rdl(mp, INTERRUPT_MASK_REG(port_num));
1775 1320
1776 mv643xx_eth_int_handler(netdev->irq, netdev); 1321 init_mac_tables(mp);
1322 uc_addr_set(mp, dev->dev_addr);
1777 1323
1778 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); 1324 return 0;
1779} 1325}
1780#endif
1781 1326
1782static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address, 1327static int addr_crc(unsigned char *addr)
1783 int speed, int duplex,
1784 struct ethtool_cmd *cmd)
1785{ 1328{
1786 struct mv643xx_private *mp = netdev_priv(dev); 1329 int crc = 0;
1330 int i;
1787 1331
1788 memset(cmd, 0, sizeof(*cmd)); 1332 for (i = 0; i < 6; i++) {
1333 int j;
1789 1334
1790 cmd->port = PORT_MII; 1335 crc = (crc ^ addr[i]) << 8;
1791 cmd->transceiver = XCVR_INTERNAL; 1336 for (j = 7; j >= 0; j--) {
1792 cmd->phy_address = phy_address; 1337 if (crc & (0x100 << j))
1793 1338 crc ^= 0x107 << j;
1794 if (speed == 0) { 1339 }
1795 cmd->autoneg = AUTONEG_ENABLE;
1796 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
1797 cmd->speed = SPEED_100;
1798 cmd->advertising = ADVERTISED_10baseT_Half |
1799 ADVERTISED_10baseT_Full |
1800 ADVERTISED_100baseT_Half |
1801 ADVERTISED_100baseT_Full;
1802 if (mp->mii.supports_gmii)
1803 cmd->advertising |= ADVERTISED_1000baseT_Full;
1804 } else {
1805 cmd->autoneg = AUTONEG_DISABLE;
1806 cmd->speed = speed;
1807 cmd->duplex = duplex;
1808 } 1340 }
1341
1342 return crc;
1809} 1343}
1810 1344
1811/*/ 1345static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1812 * mv643xx_eth_probe
1813 *
1814 * First function called after registering the network device.
1815 * It's purpose is to initialize the device as an ethernet device,
1816 * fill the ethernet device structure with pointers * to functions,
1817 * and set the MAC address of the interface
1818 *
1819 * Input : struct device *
1820 * Output : -ENOMEM if failed , 0 if success
1821 */
1822static int mv643xx_eth_probe(struct platform_device *pdev)
1823{ 1346{
1824 struct mv643xx_eth_platform_data *pd; 1347 struct mv643xx_eth_private *mp = netdev_priv(dev);
1825 int port_num; 1348 u32 port_config;
1826 struct mv643xx_private *mp; 1349 struct dev_addr_list *addr;
1827 struct net_device *dev; 1350 int i;
1828 u8 *p;
1829 struct resource *res;
1830 int err;
1831 struct ethtool_cmd cmd;
1832 int duplex = DUPLEX_HALF;
1833 int speed = 0; /* default to auto-negotiation */
1834 DECLARE_MAC_BUF(mac);
1835 1351
1836 pd = pdev->dev.platform_data; 1352 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1837 if (pd == NULL) { 1353 if (dev->flags & IFF_PROMISC)
1838 printk(KERN_ERR "No mv643xx_eth_platform_data\n"); 1354 port_config |= UNICAST_PROMISCUOUS_MODE;
1839 return -ENODEV; 1355 else
1356 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1357 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1358
1359 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1360 int port_num = mp->port_num;
1361 u32 accept = 0x01010101;
1362
1363 for (i = 0; i < 0x100; i += 4) {
1364 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1365 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1366 }
1367 return;
1840 } 1368 }
1841 1369
1842 if (pd->shared == NULL) { 1370 for (i = 0; i < 0x100; i += 4) {
1843 printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n"); 1371 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1844 return -ENODEV; 1372 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1845 } 1373 }
1846 1374
1847 dev = alloc_etherdev(sizeof(struct mv643xx_private)); 1375 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1848 if (!dev) 1376 u8 *a = addr->da_addr;
1849 return -ENOMEM; 1377 int table;
1850 1378
1851 platform_set_drvdata(pdev, dev); 1379 if (addr->da_addrlen != 6)
1380 continue;
1852 1381
1853 mp = netdev_priv(dev); 1382 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1854 mp->dev = dev; 1383 table = SPECIAL_MCAST_TABLE(mp->port_num);
1855#ifdef MV643XX_NAPI 1384 set_filter_table_entry(mp, table, a[5]);
1856 netif_napi_add(dev, &mp->napi, mv643xx_poll, 64); 1385 } else {
1857#endif 1386 int crc = addr_crc(a);
1858 1387
1859 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1388 table = OTHER_MCAST_TABLE(mp->port_num);
1860 BUG_ON(!res); 1389 set_filter_table_entry(mp, table, crc);
1861 dev->irq = res->start; 1390 }
1391 }
1392}
1862 1393
1863 dev->open = mv643xx_eth_open;
1864 dev->stop = mv643xx_eth_stop;
1865 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1866 dev->set_mac_address = mv643xx_eth_set_mac_address;
1867 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1868 1394
1869 /* No need to Tx Timeout */ 1395/* rx/tx queue initialisation ***********************************************/
1870 dev->tx_timeout = mv643xx_eth_tx_timeout; 1396static int rxq_init(struct mv643xx_eth_private *mp, int index)
1397{
1398 struct rx_queue *rxq = mp->rxq + index;
1399 struct rx_desc *rx_desc;
1400 int size;
1401 int i;
1871 1402
1872#ifdef CONFIG_NET_POLL_CONTROLLER 1403 rxq->index = index;
1873 dev->poll_controller = mv643xx_netpoll;
1874#endif
1875 1404
1876 dev->watchdog_timeo = 2 * HZ; 1405 rxq->rx_ring_size = mp->default_rx_ring_size;
1877 dev->base_addr = 0;
1878 dev->change_mtu = mv643xx_eth_change_mtu;
1879 dev->do_ioctl = mv643xx_eth_do_ioctl;
1880 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1881 1406
1882#ifdef MV643XX_CHECKSUM_OFFLOAD_TX 1407 rxq->rx_desc_count = 0;
1883#ifdef MAX_SKB_FRAGS 1408 rxq->rx_curr_desc = 0;
1884 /* 1409 rxq->rx_used_desc = 0;
1885 * Zero copy can only work if we use Discovery II memory. Else, we will
1886 * have to map the buffers to ISA memory which is only 16 MB
1887 */
1888 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
1889#endif
1890#endif
1891 1410
1892 /* Configure the timeout task */ 1411 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1893 INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
1894 1412
1895 spin_lock_init(&mp->lock); 1413 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
1414 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1415 mp->rx_desc_sram_size);
1416 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1417 } else {
1418 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1419 &rxq->rx_desc_dma,
1420 GFP_KERNEL);
1421 }
1896 1422
1897 mp->shared = platform_get_drvdata(pd->shared); 1423 if (rxq->rx_desc_area == NULL) {
1898 port_num = mp->port_num = pd->port_number; 1424 dev_printk(KERN_ERR, &mp->dev->dev,
1425 "can't allocate rx ring (%d bytes)\n", size);
1426 goto out;
1427 }
1428 memset(rxq->rx_desc_area, 0, size);
1899 1429
1900 if (mp->shared->win_protect) 1430 rxq->rx_desc_area_size = size;
1901 wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect); 1431 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1432 GFP_KERNEL);
1433 if (rxq->rx_skb == NULL) {
1434 dev_printk(KERN_ERR, &mp->dev->dev,
1435 "can't allocate rx skb ring\n");
1436 goto out_free;
1437 }
1902 1438
1903 mp->shared_smi = mp->shared; 1439 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1904 if (pd->shared_smi != NULL) 1440 for (i = 0; i < rxq->rx_ring_size; i++) {
1905 mp->shared_smi = platform_get_drvdata(pd->shared_smi); 1441 int nexti = (i + 1) % rxq->rx_ring_size;
1442 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1443 nexti * sizeof(struct rx_desc);
1444 }
1906 1445
1907 /* set default config values */ 1446 init_timer(&rxq->rx_oom);
1908 eth_port_uc_addr_get(mp, dev->dev_addr); 1447 rxq->rx_oom.data = (unsigned long)rxq;
1909 mp->rx_ring_size = PORT_DEFAULT_RECEIVE_QUEUE_SIZE; 1448 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1910 mp->tx_ring_size = PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1911 1449
1912 if (is_valid_ether_addr(pd->mac_addr)) 1450 return 0;
1913 memcpy(dev->dev_addr, pd->mac_addr, 6);
1914 1451
1915 if (pd->phy_addr || pd->force_phy_addr)
1916 ethernet_phy_set(mp, pd->phy_addr);
1917 1452
1918 if (pd->rx_queue_size) 1453out_free:
1919 mp->rx_ring_size = pd->rx_queue_size; 1454 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
1455 iounmap(rxq->rx_desc_area);
1456 else
1457 dma_free_coherent(NULL, size,
1458 rxq->rx_desc_area,
1459 rxq->rx_desc_dma);
1920 1460
1921 if (pd->tx_queue_size) 1461out:
1922 mp->tx_ring_size = pd->tx_queue_size; 1462 return -ENOMEM;
1463}
1923 1464
1924 if (pd->tx_sram_size) { 1465static void rxq_deinit(struct rx_queue *rxq)
1925 mp->tx_sram_size = pd->tx_sram_size; 1466{
1926 mp->tx_sram_addr = pd->tx_sram_addr; 1467 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1927 } 1468 int i;
1928 1469
1929 if (pd->rx_sram_size) { 1470 rxq_disable(rxq);
1930 mp->rx_sram_size = pd->rx_sram_size;
1931 mp->rx_sram_addr = pd->rx_sram_addr;
1932 }
1933 1471
1934 duplex = pd->duplex; 1472 del_timer_sync(&rxq->rx_oom);
1935 speed = pd->speed;
1936 1473
1937 /* Hook up MII support for ethtool */ 1474 for (i = 0; i < rxq->rx_ring_size; i++) {
1938 mp->mii.dev = dev; 1475 if (rxq->rx_skb[i]) {
1939 mp->mii.mdio_read = mv643xx_mdio_read; 1476 dev_kfree_skb(rxq->rx_skb[i]);
1940 mp->mii.mdio_write = mv643xx_mdio_write; 1477 rxq->rx_desc_count--;
1941 mp->mii.phy_id = ethernet_phy_get(mp); 1478 }
1942 mp->mii.phy_id_mask = 0x3f; 1479 }
1943 mp->mii.reg_num_mask = 0x1f;
1944 1480
1945 err = ethernet_phy_detect(mp); 1481 if (rxq->rx_desc_count) {
1946 if (err) { 1482 dev_printk(KERN_ERR, &mp->dev->dev,
1947 pr_debug("%s: No PHY detected at addr %d\n", 1483 "error freeing rx ring -- %d skbs stuck\n",
1948 dev->name, ethernet_phy_get(mp)); 1484 rxq->rx_desc_count);
1949 goto out;
1950 } 1485 }
1951 1486
1952 ethernet_phy_reset(mp); 1487 if (rxq->index == mp->rxq_primary &&
1953 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii); 1488 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1954 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd); 1489 iounmap(rxq->rx_desc_area);
1955 mv643xx_eth_update_pscr(dev, &cmd); 1490 else
1956 mv643xx_set_settings(dev, &cmd); 1491 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1492 rxq->rx_desc_area, rxq->rx_desc_dma);
1957 1493
1958 SET_NETDEV_DEV(dev, &pdev->dev); 1494 kfree(rxq->rx_skb);
1959 err = register_netdev(dev); 1495}
1960 if (err)
1961 goto out;
1962 1496
1963 p = dev->dev_addr; 1497static int txq_init(struct mv643xx_eth_private *mp, int index)
1964 printk(KERN_NOTICE 1498{
1965 "%s: port %d with MAC address %s\n", 1499 struct tx_queue *txq = mp->txq + index;
1966 dev->name, port_num, print_mac(mac, p)); 1500 struct tx_desc *tx_desc;
1501 int size;
1502 int i;
1967 1503
1968 if (dev->features & NETIF_F_SG) 1504 txq->index = index;
1969 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1970 1505
1971 if (dev->features & NETIF_F_IP_CSUM) 1506 txq->tx_ring_size = mp->default_tx_ring_size;
1972 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1973 dev->name);
1974 1507
1975#ifdef MV643XX_CHECKSUM_OFFLOAD_TX 1508 txq->tx_desc_count = 0;
1976 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name); 1509 txq->tx_curr_desc = 0;
1977#endif 1510 txq->tx_used_desc = 0;
1978 1511
1979#ifdef MV643XX_COAL 1512 size = txq->tx_ring_size * sizeof(struct tx_desc);
1980 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1981 dev->name);
1982#endif
1983 1513
1984#ifdef MV643XX_NAPI 1514 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
1985 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name); 1515 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1986#endif 1516 mp->tx_desc_sram_size);
1517 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1518 } else {
1519 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1520 &txq->tx_desc_dma,
1521 GFP_KERNEL);
1522 }
1523
1524 if (txq->tx_desc_area == NULL) {
1525 dev_printk(KERN_ERR, &mp->dev->dev,
1526 "can't allocate tx ring (%d bytes)\n", size);
1527 goto out;
1528 }
1529 memset(txq->tx_desc_area, 0, size);
1987 1530
1988 if (mp->tx_sram_size > 0) 1531 txq->tx_desc_area_size = size;
1989 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name); 1532 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1533 GFP_KERNEL);
1534 if (txq->tx_skb == NULL) {
1535 dev_printk(KERN_ERR, &mp->dev->dev,
1536 "can't allocate tx skb ring\n");
1537 goto out_free;
1538 }
1539
1540 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1541 for (i = 0; i < txq->tx_ring_size; i++) {
1542 int nexti = (i + 1) % txq->tx_ring_size;
1543 tx_desc[i].next_desc_ptr = txq->tx_desc_dma +
1544 nexti * sizeof(struct tx_desc);
1545 }
1990 1546
1991 return 0; 1547 return 0;
1992 1548
1993out:
1994 free_netdev(dev);
1995 1549
1996 return err; 1550out_free:
1551 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
1552 iounmap(txq->tx_desc_area);
1553 else
1554 dma_free_coherent(NULL, size,
1555 txq->tx_desc_area,
1556 txq->tx_desc_dma);
1557
1558out:
1559 return -ENOMEM;
1997} 1560}
1998 1561
1999static int mv643xx_eth_remove(struct platform_device *pdev) 1562static void txq_reclaim(struct tx_queue *txq, int force)
2000{ 1563{
2001 struct net_device *dev = platform_get_drvdata(pdev); 1564 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1565 unsigned long flags;
2002 1566
2003 unregister_netdev(dev); 1567 spin_lock_irqsave(&mp->lock, flags);
2004 flush_scheduled_work(); 1568 while (txq->tx_desc_count > 0) {
1569 int tx_index;
1570 struct tx_desc *desc;
1571 u32 cmd_sts;
1572 struct sk_buff *skb;
1573 dma_addr_t addr;
1574 int count;
1575
1576 tx_index = txq->tx_used_desc;
1577 desc = &txq->tx_desc_area[tx_index];
1578 cmd_sts = desc->cmd_sts;
2005 1579
2006 free_netdev(dev); 1580 if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA))
2007 platform_set_drvdata(pdev, NULL); 1581 break;
2008 return 0;
2009}
2010 1582
2011static void mv643xx_eth_conf_mbus_windows(struct mv643xx_shared_private *msp, 1583 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
2012 struct mbus_dram_target_info *dram) 1584 txq->tx_desc_count--;
2013{
2014 void __iomem *base = msp->eth_base;
2015 u32 win_enable;
2016 u32 win_protect;
2017 int i;
2018 1585
2019 for (i = 0; i < 6; i++) { 1586 addr = desc->buf_ptr;
2020 writel(0, base + WINDOW_BASE(i)); 1587 count = desc->byte_cnt;
2021 writel(0, base + WINDOW_SIZE(i)); 1588 skb = txq->tx_skb[tx_index];
2022 if (i < 4) 1589 txq->tx_skb[tx_index] = NULL;
2023 writel(0, base + WINDOW_REMAP_HIGH(i));
2024 }
2025 1590
2026 win_enable = 0x3f; 1591 if (cmd_sts & ERROR_SUMMARY) {
2027 win_protect = 0; 1592 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1593 mp->dev->stats.tx_errors++;
1594 }
2028 1595
2029 for (i = 0; i < dram->num_cs; i++) { 1596 /*
2030 struct mbus_dram_window *cs = dram->cs + i; 1597 * Drop mp->lock while we free the skb.
1598 */
1599 spin_unlock_irqrestore(&mp->lock, flags);
2031 1600
2032 writel((cs->base & 0xffff0000) | 1601 if (cmd_sts & TX_FIRST_DESC)
2033 (cs->mbus_attr << 8) | 1602 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
2034 dram->mbus_dram_target_id, base + WINDOW_BASE(i)); 1603 else
2035 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); 1604 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
2036 1605
2037 win_enable &= ~(1 << i); 1606 if (skb)
2038 win_protect |= 3 << (2 * i); 1607 dev_kfree_skb_irq(skb);
2039 }
2040 1608
2041 writel(win_enable, base + WINDOW_BAR_ENABLE); 1609 spin_lock_irqsave(&mp->lock, flags);
2042 msp->win_protect = win_protect; 1610 }
1611 spin_unlock_irqrestore(&mp->lock, flags);
2043} 1612}
2044 1613
2045static int mv643xx_eth_shared_probe(struct platform_device *pdev) 1614static void txq_deinit(struct tx_queue *txq)
2046{ 1615{
2047 static int mv643xx_version_printed = 0; 1616 struct mv643xx_eth_private *mp = txq_to_mp(txq);
2048 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2049 struct mv643xx_shared_private *msp;
2050 struct resource *res;
2051 int ret;
2052 1617
2053 if (!mv643xx_version_printed++) 1618 txq_disable(txq);
2054 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n"); 1619 txq_reclaim(txq, 1);
2055 1620
2056 ret = -EINVAL; 1621 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
2057 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2058 if (res == NULL)
2059 goto out;
2060 1622
2061 ret = -ENOMEM; 1623 if (txq->index == mp->txq_primary &&
2062 msp = kmalloc(sizeof(*msp), GFP_KERNEL); 1624 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
2063 if (msp == NULL) 1625 iounmap(txq->tx_desc_area);
2064 goto out; 1626 else
2065 memset(msp, 0, sizeof(*msp)); 1627 dma_free_coherent(NULL, txq->tx_desc_area_size,
1628 txq->tx_desc_area, txq->tx_desc_dma);
2066 1629
2067 msp->eth_base = ioremap(res->start, res->end - res->start + 1); 1630 kfree(txq->tx_skb);
2068 if (msp->eth_base == NULL) 1631}
2069 goto out_free;
2070 1632
2071 spin_lock_init(&msp->phy_lock);
2072 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2073 1633
2074 platform_set_drvdata(pdev, msp); 1634/* netdev ops and related ***************************************************/
1635static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
1636{
1637 u32 pscr_o;
1638 u32 pscr_n;
2075 1639
2076 /* 1640 pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2077 * (Re-)program MBUS remapping windows if we are asked to.
2078 */
2079 if (pd != NULL && pd->dram != NULL)
2080 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2081 1641
2082 return 0; 1642 /* clear speed, duplex and rx buffer size fields */
1643 pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 |
1644 SET_GMII_SPEED_TO_1000 |
1645 SET_FULL_DUPLEX_MODE |
1646 MAX_RX_PACKET_MASK);
2083 1647
2084out_free: 1648 if (speed == SPEED_1000) {
2085 kfree(msp); 1649 pscr_n |= SET_GMII_SPEED_TO_1000 | MAX_RX_PACKET_9700BYTE;
2086out: 1650 } else {
2087 return ret; 1651 if (speed == SPEED_100)
2088} 1652 pscr_n |= SET_MII_SPEED_TO_100;
1653 pscr_n |= MAX_RX_PACKET_1522BYTE;
1654 }
2089 1655
2090static int mv643xx_eth_shared_remove(struct platform_device *pdev) 1656 if (duplex == DUPLEX_FULL)
2091{ 1657 pscr_n |= SET_FULL_DUPLEX_MODE;
2092 struct mv643xx_shared_private *msp = platform_get_drvdata(pdev);
2093 1658
2094 iounmap(msp->eth_base); 1659 if (pscr_n != pscr_o) {
2095 kfree(msp); 1660 if ((pscr_o & SERIAL_PORT_ENABLE) == 0)
1661 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1662 else {
1663 int i;
2096 1664
2097 return 0; 1665 for (i = 0; i < 8; i++)
1666 if (mp->txq_mask & (1 << i))
1667 txq_disable(mp->txq + i);
1668
1669 pscr_o &= ~SERIAL_PORT_ENABLE;
1670 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o);
1671 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1672 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1673
1674 for (i = 0; i < 8; i++)
1675 if (mp->txq_mask & (1 << i))
1676 txq_enable(mp->txq + i);
1677 }
1678 }
2098} 1679}
2099 1680
2100static void mv643xx_eth_shutdown(struct platform_device *pdev) 1681static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2101{ 1682{
2102 struct net_device *dev = platform_get_drvdata(pdev); 1683 struct net_device *dev = (struct net_device *)dev_id;
2103 struct mv643xx_private *mp = netdev_priv(dev); 1684 struct mv643xx_eth_private *mp = netdev_priv(dev);
2104 unsigned int port_num = mp->port_num; 1685 u32 int_cause;
1686 u32 int_cause_ext;
1687 u32 txq_active;
1688
1689 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1690 (INT_TX_END | INT_RX | INT_EXT);
1691 if (int_cause == 0)
1692 return IRQ_NONE;
2105 1693
2106 /* Mask all interrupts on ethernet port */ 1694 int_cause_ext = 0;
2107 wrl(mp, INTERRUPT_MASK_REG(port_num), 0); 1695 if (int_cause & INT_EXT) {
2108 rdl(mp, INTERRUPT_MASK_REG(port_num)); 1696 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
1697 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1698 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1699 }
2109 1700
2110 eth_port_reset(mp); 1701 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) {
2111} 1702 if (mp->phy_addr == -1 || mii_link_ok(&mp->mii)) {
1703 int i;
2112 1704
2113static struct platform_driver mv643xx_eth_driver = { 1705 if (mp->phy_addr != -1) {
2114 .probe = mv643xx_eth_probe, 1706 struct ethtool_cmd cmd;
2115 .remove = mv643xx_eth_remove,
2116 .shutdown = mv643xx_eth_shutdown,
2117 .driver = {
2118 .name = MV643XX_ETH_NAME,
2119 .owner = THIS_MODULE,
2120 },
2121};
2122 1707
2123static struct platform_driver mv643xx_eth_shared_driver = { 1708 mii_ethtool_gset(&mp->mii, &cmd);
2124 .probe = mv643xx_eth_shared_probe, 1709 update_pscr(mp, cmd.speed, cmd.duplex);
2125 .remove = mv643xx_eth_shared_remove, 1710 }
2126 .driver = {
2127 .name = MV643XX_ETH_SHARED_NAME,
2128 .owner = THIS_MODULE,
2129 },
2130};
2131 1711
2132/* 1712 for (i = 0; i < 8; i++)
2133 * mv643xx_init_module 1713 if (mp->txq_mask & (1 << i))
2134 * 1714 txq_enable(mp->txq + i);
2135 * Registers the network drivers into the Linux kernel
2136 *
2137 * Input : N/A
2138 *
2139 * Output : N/A
2140 */
2141static int __init mv643xx_init_module(void)
2142{
2143 int rc;
2144 1715
2145 rc = platform_driver_register(&mv643xx_eth_shared_driver); 1716 if (!netif_carrier_ok(dev)) {
2146 if (!rc) { 1717 netif_carrier_on(dev);
2147 rc = platform_driver_register(&mv643xx_eth_driver); 1718 __txq_maybe_wake(mp->txq + mp->txq_primary);
2148 if (rc) 1719 }
2149 platform_driver_unregister(&mv643xx_eth_shared_driver); 1720 } else if (netif_carrier_ok(dev)) {
1721 netif_stop_queue(dev);
1722 netif_carrier_off(dev);
1723 }
2150 } 1724 }
2151 return rc;
2152}
2153 1725
2154/* 1726 /*
2155 * mv643xx_cleanup_module 1727 * RxBuffer or RxError set for any of the 8 queues?
2156 * 1728 */
2157 * Registers the network drivers into the Linux kernel 1729#ifdef MV643XX_ETH_NAPI
2158 * 1730 if (int_cause & INT_RX) {
2159 * Input : N/A 1731 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2160 * 1732 rdl(mp, INT_MASK(mp->port_num));
2161 * Output : N/A
2162 */
2163static void __exit mv643xx_cleanup_module(void)
2164{
2165 platform_driver_unregister(&mv643xx_eth_driver);
2166 platform_driver_unregister(&mv643xx_eth_shared_driver);
2167}
2168 1733
2169module_init(mv643xx_init_module); 1734 netif_rx_schedule(dev, &mp->napi);
2170module_exit(mv643xx_cleanup_module); 1735 }
1736#else
1737 if (int_cause & INT_RX) {
1738 int i;
2171 1739
2172MODULE_LICENSE("GPL"); 1740 for (i = 7; i >= 0; i--)
2173MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani" 1741 if (mp->rxq_mask & (1 << i))
2174 " and Dale Farnsworth"); 1742 rxq_process(mp->rxq + i, INT_MAX);
2175MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); 1743 }
2176MODULE_ALIAS("platform:" MV643XX_ETH_NAME); 1744#endif
2177MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2178 1745
2179/* 1746 txq_active = rdl(mp, TXQ_COMMAND(mp->port_num));
2180 * The second part is the low level driver of the gigE ethernet ports.
2181 */
2182 1747
2183/* 1748 /*
2184 * Marvell's Gigabit Ethernet controller low level driver 1749 * TxBuffer or TxError set for any of the 8 queues?
2185 * 1750 */
2186 * DESCRIPTION: 1751 if (int_cause_ext & INT_EXT_TX) {
2187 * This file introduce low level API to Marvell's Gigabit Ethernet 1752 int i;
2188 * controller. This Gigabit Ethernet Controller driver API controls
2189 * 1) Operations (i.e. port init, start, reset etc').
2190 * 2) Data flow (i.e. port send, receive etc').
2191 * Each Gigabit Ethernet port is controlled via
2192 * struct mv643xx_private.
2193 * This struct includes user configuration information as well as
2194 * driver internal data needed for its operations.
2195 *
2196 * Supported Features:
2197 * - This low level driver is OS independent. Allocating memory for
2198 * the descriptor rings and buffers are not within the scope of
2199 * this driver.
2200 * - The user is free from Rx/Tx queue managing.
2201 * - This low level driver introduce functionality API that enable
2202 * the to operate Marvell's Gigabit Ethernet Controller in a
2203 * convenient way.
2204 * - Simple Gigabit Ethernet port operation API.
2205 * - Simple Gigabit Ethernet port data flow API.
2206 * - Data flow and operation API support per queue functionality.
2207 * - Support cached descriptors for better performance.
2208 * - Enable access to all four DRAM banks and internal SRAM memory
2209 * spaces.
2210 * - PHY access and control API.
2211 * - Port control register configuration API.
2212 * - Full control over Unicast and Multicast MAC configurations.
2213 *
2214 * Operation flow:
2215 *
2216 * Initialization phase
2217 * This phase complete the initialization of the the
2218 * mv643xx_private struct.
2219 * User information regarding port configuration has to be set
2220 * prior to calling the port initialization routine.
2221 *
2222 * In this phase any port Tx/Rx activity is halted, MIB counters
2223 * are cleared, PHY address is set according to user parameter and
2224 * access to DRAM and internal SRAM memory spaces.
2225 *
2226 * Driver ring initialization
2227 * Allocating memory for the descriptor rings and buffers is not
2228 * within the scope of this driver. Thus, the user is required to
2229 * allocate memory for the descriptors ring and buffers. Those
2230 * memory parameters are used by the Rx and Tx ring initialization
2231 * routines in order to curve the descriptor linked list in a form
2232 * of a ring.
2233 * Note: Pay special attention to alignment issues when using
2234 * cached descriptors/buffers. In this phase the driver store
2235 * information in the mv643xx_private struct regarding each queue
2236 * ring.
2237 *
2238 * Driver start
2239 * This phase prepares the Ethernet port for Rx and Tx activity.
2240 * It uses the information stored in the mv643xx_private struct to
2241 * initialize the various port registers.
2242 *
2243 * Data flow:
2244 * All packet references to/from the driver are done using
2245 * struct pkt_info.
2246 * This struct is a unified struct used with Rx and Tx operations.
2247 * This way the user is not required to be familiar with neither
2248 * Tx nor Rx descriptors structures.
2249 * The driver's descriptors rings are management by indexes.
2250 * Those indexes controls the ring resources and used to indicate
2251 * a SW resource error:
2252 * 'current'
2253 * This index points to the current available resource for use. For
2254 * example in Rx process this index will point to the descriptor
2255 * that will be passed to the user upon calling the receive
2256 * routine. In Tx process, this index will point to the descriptor
2257 * that will be assigned with the user packet info and transmitted.
2258 * 'used'
2259 * This index points to the descriptor that need to restore its
2260 * resources. For example in Rx process, using the Rx buffer return
2261 * API will attach the buffer returned in packet info to the
2262 * descriptor pointed by 'used'. In Tx process, using the Tx
2263 * descriptor return will merely return the user packet info with
2264 * the command status of the transmitted buffer pointed by the
2265 * 'used' index. Nevertheless, it is essential to use this routine
2266 * to update the 'used' index.
2267 * 'first'
2268 * This index supports Tx Scatter-Gather. It points to the first
2269 * descriptor of a packet assembled of multiple buffers. For
2270 * example when in middle of Such packet we have a Tx resource
2271 * error the 'curr' index get the value of 'first' to indicate
2272 * that the ring returned to its state before trying to transmit
2273 * this packet.
2274 *
2275 * Receive operation:
2276 * The eth_port_receive API set the packet information struct,
2277 * passed by the caller, with received information from the
2278 * 'current' SDMA descriptor.
2279 * It is the user responsibility to return this resource back
2280 * to the Rx descriptor ring to enable the reuse of this source.
2281 * Return Rx resource is done using the eth_rx_return_buff API.
2282 *
2283 * Prior to calling the initialization routine eth_port_init() the user
2284 * must set the following fields under mv643xx_private struct:
2285 * port_num User Ethernet port number.
2286 * port_config User port configuration value.
2287 * port_config_extend User port config extend value.
2288 * port_sdma_config User port SDMA config value.
2289 * port_serial_control User port serial control value.
2290 *
2291 * This driver data flow is done using the struct pkt_info which
2292 * is a unified struct for Rx and Tx operations:
2293 *
2294 * byte_cnt Tx/Rx descriptor buffer byte count.
2295 * l4i_chk CPU provided TCP Checksum. For Tx operation
2296 * only.
2297 * cmd_sts Tx/Rx descriptor command status.
2298 * buf_ptr Tx/Rx descriptor buffer pointer.
2299 * return_info Tx/Rx user resource return information.
2300 */
2301 1753
2302/* Ethernet Port routines */ 1754 for (i = 0; i < 8; i++)
2303static void eth_port_set_filter_table_entry(struct mv643xx_private *mp, 1755 if (mp->txq_mask & (1 << i))
2304 int table, unsigned char entry); 1756 txq_reclaim(mp->txq + i, 0);
1757 }
2305 1758
2306/* 1759 /*
2307 * eth_port_init - Initialize the Ethernet port driver 1760 * Any TxEnd interrupts?
2308 * 1761 */
2309 * DESCRIPTION: 1762 if (int_cause & INT_TX_END) {
2310 * This function prepares the ethernet port to start its activity: 1763 int i;
2311 * 1) Completes the ethernet port driver struct initialization toward port 1764
2312 * start routine. 1765 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
2313 * 2) Resets the device to a quiescent state in case of warm reboot. 1766 for (i = 0; i < 8; i++) {
2314 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. 1767 struct tx_queue *txq = mp->txq + i;
2315 * 4) Clean MAC tables. The reset status of those tables is unknown. 1768 if (txq->tx_desc_count && !((txq_active >> i) & 1))
2316 * 5) Set PHY address. 1769 txq_enable(txq);
2317 * Note: Call this routine prior to eth_port_start routine and after 1770 }
2318 * setting user values in the user fields of Ethernet port control 1771 }
2319 * struct.
2320 *
2321 * INPUT:
2322 * struct mv643xx_private *mp Ethernet port control struct
2323 *
2324 * OUTPUT:
2325 * See description.
2326 *
2327 * RETURN:
2328 * None.
2329 */
2330static void eth_port_init(struct mv643xx_private *mp)
2331{
2332 mp->rx_resource_err = 0;
2333 1772
2334 eth_port_reset(mp); 1773 /*
1774 * Enough space again in the primary TX queue for a full packet?
1775 */
1776 if (int_cause_ext & INT_EXT_TX) {
1777 struct tx_queue *txq = mp->txq + mp->txq_primary;
1778 __txq_maybe_wake(txq);
1779 }
2335 1780
2336 eth_port_init_mac_tables(mp); 1781 return IRQ_HANDLED;
2337} 1782}
2338 1783
2339/* 1784static void phy_reset(struct mv643xx_eth_private *mp)
2340 * eth_port_start - Start the Ethernet port activity.
2341 *
2342 * DESCRIPTION:
2343 * This routine prepares the Ethernet port for Rx and Tx activity:
2344 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
2345 * has been initialized a descriptor's ring (using
2346 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
2347 * 2. Initialize and enable the Ethernet configuration port by writing to
2348 * the port's configuration and command registers.
2349 * 3. Initialize and enable the SDMA by writing to the SDMA's
2350 * configuration and command registers. After completing these steps,
2351 * the ethernet port SDMA can starts to perform Rx and Tx activities.
2352 *
2353 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
2354 * to calling this function (use ether_init_tx_desc_ring for Tx queues
2355 * and ether_init_rx_desc_ring for Rx queues).
2356 *
2357 * INPUT:
2358 * dev - a pointer to the required interface
2359 *
2360 * OUTPUT:
2361 * Ethernet port is ready to receive and transmit.
2362 *
2363 * RETURN:
2364 * None.
2365 */
2366static void eth_port_start(struct net_device *dev)
2367{ 1785{
2368 struct mv643xx_private *mp = netdev_priv(dev); 1786 unsigned int data;
2369 unsigned int port_num = mp->port_num;
2370 int tx_curr_desc, rx_curr_desc;
2371 u32 pscr;
2372 struct ethtool_cmd ethtool_cmd;
2373
2374 /* Assignment of Tx CTRP of given queue */
2375 tx_curr_desc = mp->tx_curr_desc_q;
2376 wrl(mp, TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
2377 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
2378
2379 /* Assignment of Rx CRDP of given queue */
2380 rx_curr_desc = mp->rx_curr_desc_q;
2381 wrl(mp, RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
2382 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
2383 1787
2384 /* Add the assigned Ethernet address to the port's address table */ 1788 smi_reg_read(mp, mp->phy_addr, 0, &data);
2385 eth_port_uc_addr_set(mp, dev->dev_addr); 1789 data |= 0x8000;
1790 smi_reg_write(mp, mp->phy_addr, 0, data);
2386 1791
2387 /* Assign port configuration and command. */ 1792 do {
2388 wrl(mp, PORT_CONFIG_REG(port_num), 1793 udelay(1);
2389 PORT_CONFIG_DEFAULT_VALUE); 1794 smi_reg_read(mp, mp->phy_addr, 0, &data);
2390 1795 } while (data & 0x8000);
2391 wrl(mp, PORT_CONFIG_EXTEND_REG(port_num), 1796}
2392 PORT_CONFIG_EXTEND_DEFAULT_VALUE);
2393 1797
2394 pscr = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num)); 1798static void port_start(struct mv643xx_eth_private *mp)
1799{
1800 u32 pscr;
1801 int i;
2395 1802
1803 /*
1804 * Configure basic link parameters.
1805 */
1806 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2396 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS); 1807 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
2397 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr); 1808 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2398
2399 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL | 1809 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
2400 DISABLE_AUTO_NEG_SPEED_GMII | 1810 DISABLE_AUTO_NEG_SPEED_GMII |
2401 DISABLE_AUTO_NEG_FOR_DUPLX | 1811 DISABLE_AUTO_NEG_FOR_DUPLEX |
2402 DO_NOT_FORCE_LINK_FAIL | 1812 DO_NOT_FORCE_LINK_FAIL |
2403 SERIAL_PORT_CONTROL_RESERVED; 1813 SERIAL_PORT_CONTROL_RESERVED;
1814 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1815 pscr |= SERIAL_PORT_ENABLE;
1816 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2404 1817
2405 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr); 1818 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
2406 1819
2407 pscr |= SERIAL_PORT_ENABLE; 1820 /*
2408 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr); 1821 * Perform PHY reset, if there is a PHY.
1822 */
1823 if (mp->phy_addr != -1) {
1824 struct ethtool_cmd cmd;
2409 1825
2410 /* Assign port SDMA configuration */ 1826 mv643xx_eth_get_settings(mp->dev, &cmd);
2411 wrl(mp, SDMA_CONFIG_REG(port_num), 1827 phy_reset(mp);
2412 PORT_SDMA_CONFIG_DEFAULT_VALUE); 1828 mv643xx_eth_set_settings(mp->dev, &cmd);
1829 }
2413 1830
2414 /* Enable port Rx. */ 1831 /*
2415 mv643xx_eth_port_enable_rx(mp, ETH_RX_QUEUES_ENABLED); 1832 * Configure TX path and queues.
1833 */
1834 tx_set_rate(mp, 1000000000, 16777216);
1835 for (i = 0; i < 8; i++) {
1836 struct tx_queue *txq = mp->txq + i;
1837 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, i);
1838 u32 addr;
2416 1839
2417 /* Disable port bandwidth limits by clearing MTU register */ 1840 if ((mp->txq_mask & (1 << i)) == 0)
2418 wrl(mp, MAXIMUM_TRANSMIT_UNIT(port_num), 0); 1841 continue;
2419 1842
2420 /* save phy settings across reset */ 1843 addr = (u32)txq->tx_desc_dma;
2421 mv643xx_get_settings(dev, &ethtool_cmd); 1844 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
2422 ethernet_phy_reset(mp); 1845 wrl(mp, off, addr);
2423 mv643xx_set_settings(dev, &ethtool_cmd);
2424}
2425 1846
2426/* 1847 txq_set_rate(txq, 1000000000, 16777216);
2427 * eth_port_uc_addr_set - Write a MAC address into the port's hw registers 1848 txq_set_fixed_prio_mode(txq);
2428 */ 1849 }
2429static void eth_port_uc_addr_set(struct mv643xx_private *mp,
2430 unsigned char *p_addr)
2431{
2432 unsigned int port_num = mp->port_num;
2433 unsigned int mac_h;
2434 unsigned int mac_l;
2435 int table;
2436 1850
2437 mac_l = (p_addr[4] << 8) | (p_addr[5]); 1851 /*
2438 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | 1852 * Add configured unicast address to address filter table.
2439 (p_addr[3] << 0); 1853 */
1854 uc_addr_set(mp, mp->dev->dev_addr);
2440 1855
2441 wrl(mp, MAC_ADDR_LOW(port_num), mac_l); 1856 /*
2442 wrl(mp, MAC_ADDR_HIGH(port_num), mac_h); 1857 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1858 * frames to RX queue #0.
1859 */
1860 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
2443 1861
2444 /* Accept frames with this address */ 1862 /*
2445 table = DA_FILTER_UNICAST_TABLE_BASE(port_num); 1863 * Treat BPDUs as normal multicasts, and disable partition mode.
2446 eth_port_set_filter_table_entry(mp, table, p_addr[5] & 0x0f); 1864 */
2447} 1865 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
2448 1866
2449/* 1867 /*
2450 * eth_port_uc_addr_get - Read the MAC address from the port's hw registers 1868 * Enable the receive queues.
2451 */ 1869 */
2452static void eth_port_uc_addr_get(struct mv643xx_private *mp, 1870 for (i = 0; i < 8; i++) {
2453 unsigned char *p_addr) 1871 struct rx_queue *rxq = mp->rxq + i;
2454{ 1872 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
2455 unsigned int port_num = mp->port_num; 1873 u32 addr;
2456 unsigned int mac_h; 1874
2457 unsigned int mac_l; 1875 if ((mp->rxq_mask & (1 << i)) == 0)
1876 continue;
2458 1877
2459 mac_h = rdl(mp, MAC_ADDR_HIGH(port_num)); 1878 addr = (u32)rxq->rx_desc_dma;
2460 mac_l = rdl(mp, MAC_ADDR_LOW(port_num)); 1879 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1880 wrl(mp, off, addr);
2461 1881
2462 p_addr[0] = (mac_h >> 24) & 0xff; 1882 rxq_enable(rxq);
2463 p_addr[1] = (mac_h >> 16) & 0xff; 1883 }
2464 p_addr[2] = (mac_h >> 8) & 0xff;
2465 p_addr[3] = mac_h & 0xff;
2466 p_addr[4] = (mac_l >> 8) & 0xff;
2467 p_addr[5] = mac_l & 0xff;
2468} 1884}
2469 1885
2470/* 1886static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2471 * The entries in each table are indexed by a hash of a packet's MAC
2472 * address. One bit in each entry determines whether the packet is
2473 * accepted. There are 4 entries (each 8 bits wide) in each register
2474 * of the table. The bits in each entry are defined as follows:
2475 * 0 Accept=1, Drop=0
2476 * 3-1 Queue (ETH_Q0=0)
2477 * 7-4 Reserved = 0;
2478 */
2479static void eth_port_set_filter_table_entry(struct mv643xx_private *mp,
2480 int table, unsigned char entry)
2481{ 1887{
2482 unsigned int table_reg; 1888 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2483 unsigned int tbl_offset; 1889 u32 val;
2484 unsigned int reg_offset; 1890
1891 val = rdl(mp, SDMA_CONFIG(mp->port_num));
1892 if (mp->shared->extended_rx_coal_limit) {
1893 if (coal > 0xffff)
1894 coal = 0xffff;
1895 val &= ~0x023fff80;
1896 val |= (coal & 0x8000) << 10;
1897 val |= (coal & 0x7fff) << 7;
1898 } else {
1899 if (coal > 0x3fff)
1900 coal = 0x3fff;
1901 val &= ~0x003fff00;
1902 val |= (coal & 0x3fff) << 8;
1903 }
1904 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1905}
2485 1906
2486 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */ 1907static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2487 reg_offset = entry % 4; /* Entry offset within the register */ 1908{
1909 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2488 1910
2489 /* Set "accepts frame bit" at specified table entry */ 1911 if (coal > 0x3fff)
2490 table_reg = rdl(mp, table + tbl_offset); 1912 coal = 0x3fff;
2491 table_reg |= 0x01 << (8 * reg_offset); 1913 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
2492 wrl(mp, table + tbl_offset, table_reg);
2493} 1914}
2494 1915
2495/* 1916static int mv643xx_eth_open(struct net_device *dev)
2496 * eth_port_mc_addr - Multicast address settings.
2497 *
2498 * The MV device supports multicast using two tables:
2499 * 1) Special Multicast Table for MAC addresses of the form
2500 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
2501 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2502 * Table entries in the DA-Filter table.
2503 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
2504 * is used as an index to the Other Multicast Table entries in the
2505 * DA-Filter table. This function calculates the CRC-8bit value.
2506 * In either case, eth_port_set_filter_table_entry() is then called
2507 * to set to set the actual table entry.
2508 */
2509static void eth_port_mc_addr(struct mv643xx_private *mp, unsigned char *p_addr)
2510{ 1917{
2511 unsigned int port_num = mp->port_num; 1918 struct mv643xx_eth_private *mp = netdev_priv(dev);
2512 unsigned int mac_h; 1919 int err;
2513 unsigned int mac_l;
2514 unsigned char crc_result = 0;
2515 int table;
2516 int mac_array[48];
2517 int crc[8];
2518 int i; 1920 int i;
2519 1921
2520 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) && 1922 wrl(mp, INT_CAUSE(mp->port_num), 0);
2521 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) { 1923 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2522 table = DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port_num); 1924 rdl(mp, INT_CAUSE_EXT(mp->port_num));
2523 eth_port_set_filter_table_entry(mp, table, p_addr[5]); 1925
2524 return; 1926 err = request_irq(dev->irq, mv643xx_eth_irq,
1927 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
1928 dev->name, dev);
1929 if (err) {
1930 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
1931 return -EAGAIN;
2525 } 1932 }
2526 1933
2527 /* Calculate CRC-8 out of the given address */ 1934 init_mac_tables(mp);
2528 mac_h = (p_addr[0] << 8) | (p_addr[1]);
2529 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
2530 (p_addr[4] << 8) | (p_addr[5] << 0);
2531
2532 for (i = 0; i < 32; i++)
2533 mac_array[i] = (mac_l >> i) & 0x1;
2534 for (i = 32; i < 48; i++)
2535 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
2536
2537 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
2538 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
2539 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
2540 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
2541 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
2542
2543 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2544 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
2545 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
2546 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
2547 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
2548 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
2549 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
2550
2551 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
2552 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
2553 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
2554 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
2555 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
2556 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
2557
2558 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2559 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
2560 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
2561 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
2562 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
2563 mac_array[3] ^ mac_array[2] ^ mac_array[1];
2564
2565 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
2566 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
2567 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
2568 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
2569 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
2570 mac_array[3] ^ mac_array[2];
2571
2572 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
2573 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
2574 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
2575 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
2576 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
2577 mac_array[4] ^ mac_array[3];
2578
2579 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
2580 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
2581 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
2582 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
2583 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
2584 mac_array[4];
2585
2586 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
2587 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
2588 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
2589 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
2590 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
2591 1935
2592 for (i = 0; i < 8; i++) 1936 for (i = 0; i < 8; i++) {
2593 crc_result = crc_result | (crc[i] << i); 1937 if ((mp->rxq_mask & (1 << i)) == 0)
1938 continue;
2594 1939
2595 table = DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port_num); 1940 err = rxq_init(mp, i);
2596 eth_port_set_filter_table_entry(mp, table, crc_result); 1941 if (err) {
2597} 1942 while (--i >= 0)
1943 if (mp->rxq_mask & (1 << i))
1944 rxq_deinit(mp->rxq + i);
1945 goto out;
1946 }
2598 1947
2599/* 1948 rxq_refill(mp->rxq + i);
2600 * Set the entire multicast list based on dev->mc_list. 1949 }
2601 */
2602static void eth_port_set_multicast_list(struct net_device *dev)
2603{
2604 1950
2605 struct dev_mc_list *mc_list; 1951 for (i = 0; i < 8; i++) {
2606 int i; 1952 if ((mp->txq_mask & (1 << i)) == 0)
2607 int table_index; 1953 continue;
2608 struct mv643xx_private *mp = netdev_priv(dev);
2609 unsigned int eth_port_num = mp->port_num;
2610 1954
2611 /* If the device is in promiscuous mode or in all multicast mode, 1955 err = txq_init(mp, i);
2612 * we will fully populate both multicast tables with accept. 1956 if (err) {
2613 * This is guaranteed to yield a match on all multicast addresses... 1957 while (--i >= 0)
2614 */ 1958 if (mp->txq_mask & (1 << i))
2615 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) { 1959 txq_deinit(mp->txq + i);
2616 for (table_index = 0; table_index <= 0xFC; table_index += 4) { 1960 goto out_free;
2617 /* Set all entries in DA filter special multicast
2618 * table (Ex_dFSMT)
2619 * Set for ETH_Q0 for now
2620 * Bits
2621 * 0 Accept=1, Drop=0
2622 * 3-1 Queue ETH_Q0=0
2623 * 7-4 Reserved = 0;
2624 */
2625 wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2626
2627 /* Set all entries in DA filter other multicast
2628 * table (Ex_dFOMT)
2629 * Set for ETH_Q0 for now
2630 * Bits
2631 * 0 Accept=1, Drop=0
2632 * 3-1 Queue ETH_Q0=0
2633 * 7-4 Reserved = 0;
2634 */
2635 wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2636 } 1961 }
2637 return;
2638 } 1962 }
2639 1963
2640 /* We will clear out multicast tables every time we get the list. 1964#ifdef MV643XX_ETH_NAPI
2641 * Then add the entire new list... 1965 napi_enable(&mp->napi);
2642 */ 1966#endif
2643 for (table_index = 0; table_index <= 0xFC; table_index += 4) { 1967
2644 /* Clear DA filter special multicast table (Ex_dFSMT) */ 1968 port_start(mp);
2645 wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2646 (eth_port_num) + table_index, 0);
2647
2648 /* Clear DA filter other multicast table (Ex_dFOMT) */
2649 wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2650 (eth_port_num) + table_index, 0);
2651 }
2652 1969
2653 /* Get pointer to net_device multicast list and add each one... */ 1970 set_rx_coal(mp, 0);
2654 for (i = 0, mc_list = dev->mc_list; 1971 set_tx_coal(mp, 0);
2655 (i < 256) && (mc_list != NULL) && (i < dev->mc_count); 1972
2656 i++, mc_list = mc_list->next) 1973 wrl(mp, INT_MASK_EXT(mp->port_num),
2657 if (mc_list->dmi_addrlen == 6) 1974 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
2658 eth_port_mc_addr(mp, mc_list->dmi_addr); 1975
1976 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
1977
1978 return 0;
1979
1980
1981out_free:
1982 for (i = 0; i < 8; i++)
1983 if (mp->rxq_mask & (1 << i))
1984 rxq_deinit(mp->rxq + i);
1985out:
1986 free_irq(dev->irq, dev);
1987
1988 return err;
2659} 1989}
2660 1990
2661/* 1991static void port_reset(struct mv643xx_eth_private *mp)
2662 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables 1992{
2663 * 1993 unsigned int data;
2664 * DESCRIPTION: 1994 int i;
2665 * Go through all the DA filter tables (Unicast, Special Multicast & 1995
2666 * Other Multicast) and set each entry to 0. 1996 for (i = 0; i < 8; i++) {
2667 * 1997 if (mp->rxq_mask & (1 << i))
2668 * INPUT: 1998 rxq_disable(mp->rxq + i);
2669 * struct mv643xx_private *mp Ethernet Port. 1999 if (mp->txq_mask & (1 << i))
2670 * 2000 txq_disable(mp->txq + i);
2671 * OUTPUT:
2672 * Multicast and Unicast packets are rejected.
2673 *
2674 * RETURN:
2675 * None.
2676 */
2677static void eth_port_init_mac_tables(struct mv643xx_private *mp)
2678{
2679 unsigned int port_num = mp->port_num;
2680 int table_index;
2681
2682 /* Clear DA filter unicast table (Ex_dFUT) */
2683 for (table_index = 0; table_index <= 0xC; table_index += 4)
2684 wrl(mp, DA_FILTER_UNICAST_TABLE_BASE(port_num) +
2685 table_index, 0);
2686
2687 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2688 /* Clear DA filter special multicast table (Ex_dFSMT) */
2689 wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port_num) +
2690 table_index, 0);
2691 /* Clear DA filter other multicast table (Ex_dFOMT) */
2692 wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port_num) +
2693 table_index, 0);
2694 } 2001 }
2002 while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY))
2003 udelay(10);
2004
2005 /* Reset the Enable bit in the Configuration Register */
2006 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2007 data &= ~(SERIAL_PORT_ENABLE |
2008 DO_NOT_FORCE_LINK_FAIL |
2009 FORCE_LINK_PASS);
2010 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2695} 2011}
2696 2012
2697/* 2013static int mv643xx_eth_stop(struct net_device *dev)
2698 * eth_clear_mib_counters - Clear all MIB counters
2699 *
2700 * DESCRIPTION:
2701 * This function clears all MIB counters of a specific ethernet port.
2702 * A read from the MIB counter will reset the counter.
2703 *
2704 * INPUT:
2705 * struct mv643xx_private *mp Ethernet Port.
2706 *
2707 * OUTPUT:
2708 * After reading all MIB counters, the counters resets.
2709 *
2710 * RETURN:
2711 * MIB counter value.
2712 *
2713 */
2714static void eth_clear_mib_counters(struct mv643xx_private *mp)
2715{ 2014{
2716 unsigned int port_num = mp->port_num; 2015 struct mv643xx_eth_private *mp = netdev_priv(dev);
2717 int i; 2016 int i;
2718 2017
2719 /* Perform dummy reads from MIB counters */ 2018 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2720 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; 2019 rdl(mp, INT_MASK(mp->port_num));
2721 i += 4) 2020
2722 rdl(mp, MIB_COUNTERS_BASE(port_num) + i); 2021#ifdef MV643XX_ETH_NAPI
2022 napi_disable(&mp->napi);
2023#endif
2024 netif_carrier_off(dev);
2025 netif_stop_queue(dev);
2026
2027 free_irq(dev->irq, dev);
2028
2029 port_reset(mp);
2030 mib_counters_update(mp);
2031
2032 for (i = 0; i < 8; i++) {
2033 if (mp->rxq_mask & (1 << i))
2034 rxq_deinit(mp->rxq + i);
2035 if (mp->txq_mask & (1 << i))
2036 txq_deinit(mp->txq + i);
2037 }
2038
2039 return 0;
2723} 2040}
2724 2041
2725static inline u32 read_mib(struct mv643xx_private *mp, int offset) 2042static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2726{ 2043{
2727 return rdl(mp, MIB_COUNTERS_BASE(mp->port_num) + offset); 2044 struct mv643xx_eth_private *mp = netdev_priv(dev);
2045
2046 if (mp->phy_addr != -1)
2047 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2048
2049 return -EOPNOTSUPP;
2728} 2050}
2729 2051
2730static void eth_update_mib_counters(struct mv643xx_private *mp) 2052static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2731{ 2053{
2732 struct mv643xx_mib_counters *p = &mp->mib_counters; 2054 struct mv643xx_eth_private *mp = netdev_priv(dev);
2733 int offset;
2734 2055
2735 p->good_octets_received += 2056 if (new_mtu < 64 || new_mtu > 9500)
2736 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); 2057 return -EINVAL;
2737 p->good_octets_received +=
2738 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2739 2058
2740 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED; 2059 dev->mtu = new_mtu;
2741 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS; 2060 tx_set_rate(mp, 1000000000, 16777216);
2742 offset += 4)
2743 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
2744 2061
2745 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW); 2062 if (!netif_running(dev))
2746 p->good_octets_sent += 2063 return 0;
2747 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2748 2064
2749 for (offset = ETH_MIB_GOOD_FRAMES_SENT; 2065 /*
2750 offset <= ETH_MIB_LATE_COLLISION; 2066 * Stop and then re-open the interface. This will allocate RX
2751 offset += 4) 2067 * skbs of the new MTU.
2752 *(u32 *)((char *)p + offset) += read_mib(mp, offset); 2068 * There is a possible danger that the open will not succeed,
2069 * due to memory being full.
2070 */
2071 mv643xx_eth_stop(dev);
2072 if (mv643xx_eth_open(dev)) {
2073 dev_printk(KERN_ERR, &dev->dev,
2074 "fatal error on re-opening device after "
2075 "MTU change\n");
2076 }
2077
2078 return 0;
2753} 2079}
2754 2080
2755/* 2081static void tx_timeout_task(struct work_struct *ugly)
2756 * ethernet_phy_detect - Detect whether a phy is present
2757 *
2758 * DESCRIPTION:
2759 * This function tests whether there is a PHY present on
2760 * the specified port.
2761 *
2762 * INPUT:
2763 * struct mv643xx_private *mp Ethernet Port.
2764 *
2765 * OUTPUT:
2766 * None
2767 *
2768 * RETURN:
2769 * 0 on success
2770 * -ENODEV on failure
2771 *
2772 */
2773static int ethernet_phy_detect(struct mv643xx_private *mp)
2774{ 2082{
2775 unsigned int phy_reg_data0; 2083 struct mv643xx_eth_private *mp;
2776 int auto_neg;
2777 2084
2778 eth_port_read_smi_reg(mp, 0, &phy_reg_data0); 2085 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2779 auto_neg = phy_reg_data0 & 0x1000; 2086 if (netif_running(mp->dev)) {
2780 phy_reg_data0 ^= 0x1000; /* invert auto_neg */ 2087 netif_stop_queue(mp->dev);
2781 eth_port_write_smi_reg(mp, 0, phy_reg_data0);
2782 2088
2783 eth_port_read_smi_reg(mp, 0, &phy_reg_data0); 2089 port_reset(mp);
2784 if ((phy_reg_data0 & 0x1000) == auto_neg) 2090 port_start(mp);
2785 return -ENODEV; /* change didn't take */
2786 2091
2787 phy_reg_data0 ^= 0x1000; 2092 __txq_maybe_wake(mp->txq + mp->txq_primary);
2788 eth_port_write_smi_reg(mp, 0, phy_reg_data0); 2093 }
2789 return 0;
2790} 2094}
2791 2095
2792/* 2096static void mv643xx_eth_tx_timeout(struct net_device *dev)
2793 * ethernet_phy_get - Get the ethernet port PHY address.
2794 *
2795 * DESCRIPTION:
2796 * This routine returns the given ethernet port PHY address.
2797 *
2798 * INPUT:
2799 * struct mv643xx_private *mp Ethernet Port.
2800 *
2801 * OUTPUT:
2802 * None.
2803 *
2804 * RETURN:
2805 * PHY address.
2806 *
2807 */
2808static int ethernet_phy_get(struct mv643xx_private *mp)
2809{ 2097{
2810 unsigned int reg_data; 2098 struct mv643xx_eth_private *mp = netdev_priv(dev);
2811 2099
2812 reg_data = rdl(mp, PHY_ADDR_REG); 2100 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2813 2101
2814 return ((reg_data >> (5 * mp->port_num)) & 0x1f); 2102 schedule_work(&mp->tx_timeout_task);
2815} 2103}
2816 2104
2817/* 2105#ifdef CONFIG_NET_POLL_CONTROLLER
2818 * ethernet_phy_set - Set the ethernet port PHY address. 2106static void mv643xx_eth_netpoll(struct net_device *dev)
2819 *
2820 * DESCRIPTION:
2821 * This routine sets the given ethernet port PHY address.
2822 *
2823 * INPUT:
2824 * struct mv643xx_private *mp Ethernet Port.
2825 * int phy_addr PHY address.
2826 *
2827 * OUTPUT:
2828 * None.
2829 *
2830 * RETURN:
2831 * None.
2832 *
2833 */
2834static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr)
2835{ 2107{
2836 u32 reg_data; 2108 struct mv643xx_eth_private *mp = netdev_priv(dev);
2837 int addr_shift = 5 * mp->port_num; 2109
2110 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2111 rdl(mp, INT_MASK(mp->port_num));
2112
2113 mv643xx_eth_irq(dev->irq, dev);
2838 2114
2839 reg_data = rdl(mp, PHY_ADDR_REG); 2115 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_CAUSE_EXT);
2840 reg_data &= ~(0x1f << addr_shift);
2841 reg_data |= (phy_addr & 0x1f) << addr_shift;
2842 wrl(mp, PHY_ADDR_REG, reg_data);
2843} 2116}
2117#endif
2844 2118
2845/* 2119static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2846 * ethernet_phy_reset - Reset Ethernet port PHY.
2847 *
2848 * DESCRIPTION:
2849 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2850 *
2851 * INPUT:
2852 * struct mv643xx_private *mp Ethernet Port.
2853 *
2854 * OUTPUT:
2855 * The PHY is reset.
2856 *
2857 * RETURN:
2858 * None.
2859 *
2860 */
2861static void ethernet_phy_reset(struct mv643xx_private *mp)
2862{ 2120{
2863 unsigned int phy_reg_data; 2121 struct mv643xx_eth_private *mp = netdev_priv(dev);
2122 int val;
2864 2123
2865 /* Reset the PHY */ 2124 smi_reg_read(mp, addr, reg, &val);
2866 eth_port_read_smi_reg(mp, 0, &phy_reg_data);
2867 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2868 eth_port_write_smi_reg(mp, 0, phy_reg_data);
2869 2125
2870 /* wait for PHY to come out of reset */ 2126 return val;
2871 do {
2872 udelay(1);
2873 eth_port_read_smi_reg(mp, 0, &phy_reg_data);
2874 } while (phy_reg_data & 0x8000);
2875} 2127}
2876 2128
2877static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp, 2129static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2878 unsigned int queues)
2879{ 2130{
2880 wrl(mp, TRANSMIT_QUEUE_COMMAND_REG(mp->port_num), queues); 2131 struct mv643xx_eth_private *mp = netdev_priv(dev);
2132 smi_reg_write(mp, addr, reg, val);
2881} 2133}
2882 2134
2883static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp,
2884 unsigned int queues)
2885{
2886 wrl(mp, RECEIVE_QUEUE_COMMAND_REG(mp->port_num), queues);
2887}
2888 2135
2889static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp) 2136/* platform glue ************************************************************/
2137static void
2138mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2139 struct mbus_dram_target_info *dram)
2890{ 2140{
2891 unsigned int port_num = mp->port_num; 2141 void __iomem *base = msp->base;
2892 u32 queues; 2142 u32 win_enable;
2143 u32 win_protect;
2144 int i;
2893 2145
2894 /* Stop Tx port activity. Check port Tx activity. */ 2146 for (i = 0; i < 6; i++) {
2895 queues = rdl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF; 2147 writel(0, base + WINDOW_BASE(i));
2896 if (queues) { 2148 writel(0, base + WINDOW_SIZE(i));
2897 /* Issue stop command for active queues only */ 2149 if (i < 4)
2898 wrl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num), (queues << 8)); 2150 writel(0, base + WINDOW_REMAP_HIGH(i));
2151 }
2899 2152
2900 /* Wait for all Tx activity to terminate. */ 2153 win_enable = 0x3f;
2901 /* Check port cause register that all Tx queues are stopped */ 2154 win_protect = 0;
2902 while (rdl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF)
2903 udelay(PHY_WAIT_MICRO_SECONDS);
2904 2155
2905 /* Wait for Tx FIFO to empty */ 2156 for (i = 0; i < dram->num_cs; i++) {
2906 while (rdl(mp, PORT_STATUS_REG(port_num)) & 2157 struct mbus_dram_window *cs = dram->cs + i;
2907 ETH_PORT_TX_FIFO_EMPTY) 2158
2908 udelay(PHY_WAIT_MICRO_SECONDS); 2159 writel((cs->base & 0xffff0000) |
2160 (cs->mbus_attr << 8) |
2161 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2162 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2163
2164 win_enable &= ~(1 << i);
2165 win_protect |= 3 << (2 * i);
2909 } 2166 }
2910 2167
2911 return queues; 2168 writel(win_enable, base + WINDOW_BAR_ENABLE);
2169 msp->win_protect = win_protect;
2912} 2170}
2913 2171
2914static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp) 2172static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2915{ 2173{
2916 unsigned int port_num = mp->port_num; 2174 /*
2917 u32 queues; 2175 * Check whether we have a 14-bit coal limit field in bits
2918 2176 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2919 /* Stop Rx port activity. Check port Rx activity. */ 2177 * SDMA config register.
2920 queues = rdl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF; 2178 */
2921 if (queues) { 2179 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2922 /* Issue stop command for active queues only */ 2180 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2923 wrl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num), (queues << 8)); 2181 msp->extended_rx_coal_limit = 1;
2924 2182 else
2925 /* Wait for all Rx activity to terminate. */ 2183 msp->extended_rx_coal_limit = 0;
2926 /* Check port cause register that all Rx queues are stopped */
2927 while (rdl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF)
2928 udelay(PHY_WAIT_MICRO_SECONDS);
2929 }
2930 2184
2931 return queues; 2185 /*
2186 * Check whether the TX rate control registers are in the
2187 * old or the new place.
2188 */
2189 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2190 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2191 msp->tx_bw_control_moved = 1;
2192 else
2193 msp->tx_bw_control_moved = 0;
2932} 2194}
2933 2195
2934/* 2196static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2935 * eth_port_reset - Reset Ethernet port
2936 *
2937 * DESCRIPTION:
2938 * This routine resets the chip by aborting any SDMA engine activity and
2939 * clearing the MIB counters. The Receiver and the Transmit unit are in
2940 * idle state after this command is performed and the port is disabled.
2941 *
2942 * INPUT:
2943 * struct mv643xx_private *mp Ethernet Port.
2944 *
2945 * OUTPUT:
2946 * Channel activity is halted.
2947 *
2948 * RETURN:
2949 * None.
2950 *
2951 */
2952static void eth_port_reset(struct mv643xx_private *mp)
2953{ 2197{
2954 unsigned int port_num = mp->port_num; 2198 static int mv643xx_eth_version_printed = 0;
2955 unsigned int reg_data; 2199 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2200 struct mv643xx_eth_shared_private *msp;
2201 struct resource *res;
2202 int ret;
2956 2203
2957 mv643xx_eth_port_disable_tx(mp); 2204 if (!mv643xx_eth_version_printed++)
2958 mv643xx_eth_port_disable_rx(mp); 2205 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
2959 2206
2960 /* Clear all MIB counters */ 2207 ret = -EINVAL;
2961 eth_clear_mib_counters(mp); 2208 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2209 if (res == NULL)
2210 goto out;
2962 2211
2963 /* Reset the Enable bit in the Configuration Register */ 2212 ret = -ENOMEM;
2964 reg_data = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num)); 2213 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2965 reg_data &= ~(SERIAL_PORT_ENABLE | 2214 if (msp == NULL)
2966 DO_NOT_FORCE_LINK_FAIL | 2215 goto out;
2967 FORCE_LINK_PASS); 2216 memset(msp, 0, sizeof(*msp));
2968 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2969}
2970 2217
2218 msp->base = ioremap(res->start, res->end - res->start + 1);
2219 if (msp->base == NULL)
2220 goto out_free;
2971 2221
2972/* 2222 spin_lock_init(&msp->phy_lock);
2973 * eth_port_read_smi_reg - Read PHY registers
2974 *
2975 * DESCRIPTION:
2976 * This routine utilize the SMI interface to interact with the PHY in
2977 * order to perform PHY register read.
2978 *
2979 * INPUT:
2980 * struct mv643xx_private *mp Ethernet Port.
2981 * unsigned int phy_reg PHY register address offset.
2982 * unsigned int *value Register value buffer.
2983 *
2984 * OUTPUT:
2985 * Write the value of a specified PHY register into given buffer.
2986 *
2987 * RETURN:
2988 * false if the PHY is busy or read data is not in valid state.
2989 * true otherwise.
2990 *
2991 */
2992static void eth_port_read_smi_reg(struct mv643xx_private *mp,
2993 unsigned int phy_reg, unsigned int *value)
2994{
2995 void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG;
2996 int phy_addr = ethernet_phy_get(mp);
2997 unsigned long flags;
2998 int i;
2999 2223
3000 /* the SMI register is a shared resource */ 2224 /*
3001 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); 2225 * (Re-)program MBUS remapping windows if we are asked to.
2226 */
2227 if (pd != NULL && pd->dram != NULL)
2228 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
3002 2229
3003 /* wait for the SMI register to become available */ 2230 /*
3004 for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) { 2231 * Detect hardware parameters.
3005 if (i == PHY_WAIT_ITERATIONS) { 2232 */
3006 printk("%s: PHY busy timeout\n", mp->dev->name); 2233 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
3007 goto out; 2234 infer_hw_params(msp);
3008 }
3009 udelay(PHY_WAIT_MICRO_SECONDS);
3010 }
3011 2235
3012 writel((phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ, 2236 platform_set_drvdata(pdev, msp);
3013 smi_reg);
3014 2237
3015 /* now wait for the data to be valid */ 2238 return 0;
3016 for (i = 0; !(readl(smi_reg) & ETH_SMI_READ_VALID); i++) {
3017 if (i == PHY_WAIT_ITERATIONS) {
3018 printk("%s: PHY read timeout\n", mp->dev->name);
3019 goto out;
3020 }
3021 udelay(PHY_WAIT_MICRO_SECONDS);
3022 }
3023 2239
3024 *value = readl(smi_reg) & 0xffff; 2240out_free:
2241 kfree(msp);
3025out: 2242out:
3026 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); 2243 return ret;
3027} 2244}
3028 2245
3029/* 2246static int mv643xx_eth_shared_remove(struct platform_device *pdev)
3030 * eth_port_write_smi_reg - Write to PHY registers
3031 *
3032 * DESCRIPTION:
3033 * This routine utilize the SMI interface to interact with the PHY in
3034 * order to perform writes to PHY registers.
3035 *
3036 * INPUT:
3037 * struct mv643xx_private *mp Ethernet Port.
3038 * unsigned int phy_reg PHY register address offset.
3039 * unsigned int value Register value.
3040 *
3041 * OUTPUT:
3042 * Write the given value to the specified PHY register.
3043 *
3044 * RETURN:
3045 * false if the PHY is busy.
3046 * true otherwise.
3047 *
3048 */
3049static void eth_port_write_smi_reg(struct mv643xx_private *mp,
3050 unsigned int phy_reg, unsigned int value)
3051{ 2247{
3052 void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG; 2248 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
3053 int phy_addr = ethernet_phy_get(mp);
3054 unsigned long flags;
3055 int i;
3056
3057 /* the SMI register is a shared resource */
3058 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
3059 2249
3060 /* wait for the SMI register to become available */ 2250 iounmap(msp->base);
3061 for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) { 2251 kfree(msp);
3062 if (i == PHY_WAIT_ITERATIONS) {
3063 printk("%s: PHY busy timeout\n", mp->dev->name);
3064 goto out;
3065 }
3066 udelay(PHY_WAIT_MICRO_SECONDS);
3067 }
3068 2252
3069 writel((phy_addr << 16) | (phy_reg << 21) | 2253 return 0;
3070 ETH_SMI_OPCODE_WRITE | (value & 0xffff), smi_reg);
3071out:
3072 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
3073} 2254}
3074 2255
3075/* 2256static struct platform_driver mv643xx_eth_shared_driver = {
3076 * Wrappers for MII support library. 2257 .probe = mv643xx_eth_shared_probe,
3077 */ 2258 .remove = mv643xx_eth_shared_remove,
3078static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location) 2259 .driver = {
2260 .name = MV643XX_ETH_SHARED_NAME,
2261 .owner = THIS_MODULE,
2262 },
2263};
2264
2265static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
3079{ 2266{
3080 struct mv643xx_private *mp = netdev_priv(dev); 2267 int addr_shift = 5 * mp->port_num;
3081 int val; 2268 u32 data;
3082 2269
3083 eth_port_read_smi_reg(mp, location, &val); 2270 data = rdl(mp, PHY_ADDR);
3084 return val; 2271 data &= ~(0x1f << addr_shift);
2272 data |= (phy_addr & 0x1f) << addr_shift;
2273 wrl(mp, PHY_ADDR, data);
3085} 2274}
3086 2275
3087static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val) 2276static int phy_addr_get(struct mv643xx_eth_private *mp)
3088{ 2277{
3089 struct mv643xx_private *mp = netdev_priv(dev); 2278 unsigned int data;
3090 eth_port_write_smi_reg(mp, location, val); 2279
2280 data = rdl(mp, PHY_ADDR);
2281
2282 return (data >> (5 * mp->port_num)) & 0x1f;
3091} 2283}
3092 2284
3093/* 2285static void set_params(struct mv643xx_eth_private *mp,
3094 * eth_port_receive - Get received information from Rx ring. 2286 struct mv643xx_eth_platform_data *pd)
3095 *
3096 * DESCRIPTION:
3097 * This routine returns the received data to the caller. There is no
3098 * data copying during routine operation. All information is returned
3099 * using pointer to packet information struct passed from the caller.
3100 * If the routine exhausts Rx ring resources then the resource error flag
3101 * is set.
3102 *
3103 * INPUT:
3104 * struct mv643xx_private *mp Ethernet Port Control srtuct.
3105 * struct pkt_info *p_pkt_info User packet buffer.
3106 *
3107 * OUTPUT:
3108 * Rx ring current and used indexes are updated.
3109 *
3110 * RETURN:
3111 * ETH_ERROR in case the routine can not access Rx desc ring.
3112 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
3113 * ETH_END_OF_JOB if there is no received data.
3114 * ETH_OK otherwise.
3115 */
3116static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
3117 struct pkt_info *p_pkt_info)
3118{ 2287{
3119 int rx_next_curr_desc, rx_curr_desc, rx_used_desc; 2288 struct net_device *dev = mp->dev;
3120 volatile struct eth_rx_desc *p_rx_desc;
3121 unsigned int command_status;
3122 unsigned long flags;
3123 2289
3124 /* Do not process Rx ring in case of Rx ring resource error */ 2290 if (is_valid_ether_addr(pd->mac_addr))
3125 if (mp->rx_resource_err) 2291 memcpy(dev->dev_addr, pd->mac_addr, 6);
3126 return ETH_QUEUE_FULL; 2292 else
2293 uc_addr_get(mp, dev->dev_addr);
3127 2294
3128 spin_lock_irqsave(&mp->lock, flags); 2295 if (pd->phy_addr == -1) {
2296 mp->shared_smi = NULL;
2297 mp->phy_addr = -1;
2298 } else {
2299 mp->shared_smi = mp->shared;
2300 if (pd->shared_smi != NULL)
2301 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
3129 2302
3130 /* Get the Rx Desc ring 'curr and 'used' indexes */ 2303 if (pd->force_phy_addr || pd->phy_addr) {
3131 rx_curr_desc = mp->rx_curr_desc_q; 2304 mp->phy_addr = pd->phy_addr & 0x3f;
3132 rx_used_desc = mp->rx_used_desc_q; 2305 phy_addr_set(mp, mp->phy_addr);
2306 } else {
2307 mp->phy_addr = phy_addr_get(mp);
2308 }
2309 }
3133 2310
3134 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc]; 2311 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2312 if (pd->rx_queue_size)
2313 mp->default_rx_ring_size = pd->rx_queue_size;
2314 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2315 mp->rx_desc_sram_size = pd->rx_sram_size;
3135 2316
3136 /* The following parameters are used to save readings from memory */ 2317 if (pd->rx_queue_mask)
3137 command_status = p_rx_desc->cmd_sts; 2318 mp->rxq_mask = pd->rx_queue_mask;
3138 rmb(); 2319 else
2320 mp->rxq_mask = 0x01;
2321 mp->rxq_primary = fls(mp->rxq_mask) - 1;
3139 2322
3140 /* Nothing to receive... */ 2323 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
3141 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { 2324 if (pd->tx_queue_size)
3142 spin_unlock_irqrestore(&mp->lock, flags); 2325 mp->default_tx_ring_size = pd->tx_queue_size;
3143 return ETH_END_OF_JOB; 2326 mp->tx_desc_sram_addr = pd->tx_sram_addr;
3144 } 2327 mp->tx_desc_sram_size = pd->tx_sram_size;
3145 2328
3146 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET; 2329 if (pd->tx_queue_mask)
3147 p_pkt_info->cmd_sts = command_status; 2330 mp->txq_mask = pd->tx_queue_mask;
3148 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET; 2331 else
3149 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc]; 2332 mp->txq_mask = 0x01;
3150 p_pkt_info->l4i_chk = p_rx_desc->buf_size; 2333 mp->txq_primary = fls(mp->txq_mask) - 1;
2334}
3151 2335
3152 /* 2336static int phy_detect(struct mv643xx_eth_private *mp)
3153 * Clean the return info field to indicate that the 2337{
3154 * packet has been moved to the upper layers 2338 unsigned int data;
3155 */ 2339 unsigned int data2;
3156 mp->rx_skb[rx_curr_desc] = NULL;
3157 2340
3158 /* Update current index in data structure */ 2341 smi_reg_read(mp, mp->phy_addr, 0, &data);
3159 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size; 2342 smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000);
3160 mp->rx_curr_desc_q = rx_next_curr_desc;
3161 2343
3162 /* Rx descriptors exhausted. Set the Rx ring resource error flag */ 2344 smi_reg_read(mp, mp->phy_addr, 0, &data2);
3163 if (rx_next_curr_desc == rx_used_desc) 2345 if (((data ^ data2) & 0x1000) == 0)
3164 mp->rx_resource_err = 1; 2346 return -ENODEV;
3165 2347
3166 spin_unlock_irqrestore(&mp->lock, flags); 2348 smi_reg_write(mp, mp->phy_addr, 0, data);
3167 2349
3168 return ETH_OK; 2350 return 0;
3169} 2351}
3170 2352
3171/* 2353static int phy_init(struct mv643xx_eth_private *mp,
3172 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. 2354 struct mv643xx_eth_platform_data *pd)
3173 *
3174 * DESCRIPTION:
3175 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
3176 * next 'used' descriptor and attached the returned buffer to it.
3177 * In case the Rx ring was in "resource error" condition, where there are
3178 * no available Rx resources, the function resets the resource error flag.
3179 *
3180 * INPUT:
3181 * struct mv643xx_private *mp Ethernet Port Control srtuct.
3182 * struct pkt_info *p_pkt_info Information on returned buffer.
3183 *
3184 * OUTPUT:
3185 * New available Rx resource in Rx descriptor ring.
3186 *
3187 * RETURN:
3188 * ETH_ERROR in case the routine can not access Rx desc ring.
3189 * ETH_OK otherwise.
3190 */
3191static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
3192 struct pkt_info *p_pkt_info)
3193{ 2355{
3194 int used_rx_desc; /* Where to return Rx resource */ 2356 struct ethtool_cmd cmd;
3195 volatile struct eth_rx_desc *p_used_rx_desc; 2357 int err;
3196 unsigned long flags;
3197 2358
3198 spin_lock_irqsave(&mp->lock, flags); 2359 err = phy_detect(mp);
2360 if (err) {
2361 dev_printk(KERN_INFO, &mp->dev->dev,
2362 "no PHY detected at addr %d\n", mp->phy_addr);
2363 return err;
2364 }
2365 phy_reset(mp);
3199 2366
3200 /* Get 'used' Rx descriptor */ 2367 mp->mii.phy_id = mp->phy_addr;
3201 used_rx_desc = mp->rx_used_desc_q; 2368 mp->mii.phy_id_mask = 0x3f;
3202 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc]; 2369 mp->mii.reg_num_mask = 0x1f;
2370 mp->mii.dev = mp->dev;
2371 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2372 mp->mii.mdio_write = mv643xx_eth_mdio_write;
3203 2373
3204 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; 2374 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
3205 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
3206 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
3207 2375
3208 /* Flush the write pipe */ 2376 memset(&cmd, 0, sizeof(cmd));
2377
2378 cmd.port = PORT_MII;
2379 cmd.transceiver = XCVR_INTERNAL;
2380 cmd.phy_address = mp->phy_addr;
2381 if (pd->speed == 0) {
2382 cmd.autoneg = AUTONEG_ENABLE;
2383 cmd.speed = SPEED_100;
2384 cmd.advertising = ADVERTISED_10baseT_Half |
2385 ADVERTISED_10baseT_Full |
2386 ADVERTISED_100baseT_Half |
2387 ADVERTISED_100baseT_Full;
2388 if (mp->mii.supports_gmii)
2389 cmd.advertising |= ADVERTISED_1000baseT_Full;
2390 } else {
2391 cmd.autoneg = AUTONEG_DISABLE;
2392 cmd.speed = pd->speed;
2393 cmd.duplex = pd->duplex;
2394 }
3209 2395
3210 /* Return the descriptor to DMA ownership */ 2396 update_pscr(mp, cmd.speed, cmd.duplex);
3211 wmb(); 2397 mv643xx_eth_set_settings(mp->dev, &cmd);
3212 p_used_rx_desc->cmd_sts =
3213 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
3214 wmb();
3215 2398
3216 /* Move the used descriptor pointer to the next descriptor */ 2399 return 0;
3217 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size; 2400}
3218 2401
3219 /* Any Rx return cancels the Rx resource error status */ 2402static int mv643xx_eth_probe(struct platform_device *pdev)
3220 mp->rx_resource_err = 0; 2403{
2404 struct mv643xx_eth_platform_data *pd;
2405 struct mv643xx_eth_private *mp;
2406 struct net_device *dev;
2407 struct resource *res;
2408 DECLARE_MAC_BUF(mac);
2409 int err;
3221 2410
3222 spin_unlock_irqrestore(&mp->lock, flags); 2411 pd = pdev->dev.platform_data;
2412 if (pd == NULL) {
2413 dev_printk(KERN_ERR, &pdev->dev,
2414 "no mv643xx_eth_platform_data\n");
2415 return -ENODEV;
2416 }
3223 2417
3224 return ETH_OK; 2418 if (pd->shared == NULL) {
3225} 2419 dev_printk(KERN_ERR, &pdev->dev,
2420 "no mv643xx_eth_platform_data->shared\n");
2421 return -ENODEV;
2422 }
3226 2423
3227/************* Begin ethtool support *************************/ 2424 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2425 if (!dev)
2426 return -ENOMEM;
3228 2427
3229struct mv643xx_stats { 2428 mp = netdev_priv(dev);
3230 char stat_string[ETH_GSTRING_LEN]; 2429 platform_set_drvdata(pdev, mp);
3231 int sizeof_stat;
3232 int stat_offset;
3233};
3234 2430
3235#define MV643XX_STAT(m) FIELD_SIZEOF(struct mv643xx_private, m), \ 2431 mp->shared = platform_get_drvdata(pd->shared);
3236 offsetof(struct mv643xx_private, m) 2432 mp->port_num = pd->port_number;
3237
3238static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
3239 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
3240 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
3241 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
3242 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
3243 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
3244 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
3245 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
3246 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
3247 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
3248 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
3249 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
3250 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
3251 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
3252 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
3253 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
3254 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
3255 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
3256 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
3257 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
3258 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
3259 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
3260 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
3261 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
3262 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
3263 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
3264 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
3265 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
3266 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
3267 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
3268 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
3269 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
3270 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
3271 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
3272 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
3273 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
3274 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
3275 { "collision", MV643XX_STAT(mib_counters.collision) },
3276 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
3277};
3278 2433
3279#define MV643XX_STATS_LEN ARRAY_SIZE(mv643xx_gstrings_stats) 2434 mp->dev = dev;
2435#ifdef MV643XX_ETH_NAPI
2436 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
2437#endif
3280 2438
3281static void mv643xx_get_drvinfo(struct net_device *netdev, 2439 set_params(mp, pd);
3282 struct ethtool_drvinfo *drvinfo)
3283{
3284 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
3285 strncpy(drvinfo->version, mv643xx_driver_version, 32);
3286 strncpy(drvinfo->fw_version, "N/A", 32);
3287 strncpy(drvinfo->bus_info, "mv643xx", 32);
3288 drvinfo->n_stats = MV643XX_STATS_LEN;
3289}
3290 2440
3291static int mv643xx_get_sset_count(struct net_device *netdev, int sset) 2441 spin_lock_init(&mp->lock);
3292{
3293 switch (sset) {
3294 case ETH_SS_STATS:
3295 return MV643XX_STATS_LEN;
3296 default:
3297 return -EOPNOTSUPP;
3298 }
3299}
3300 2442
3301static void mv643xx_get_ethtool_stats(struct net_device *netdev, 2443 mib_counters_clear(mp);
3302 struct ethtool_stats *stats, uint64_t *data) 2444 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
3303{
3304 struct mv643xx_private *mp = netdev->priv;
3305 int i;
3306 2445
3307 eth_update_mib_counters(mp); 2446 if (mp->phy_addr != -1) {
2447 err = phy_init(mp, pd);
2448 if (err)
2449 goto out;
3308 2450
3309 for (i = 0; i < MV643XX_STATS_LEN; i++) { 2451 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
3310 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset; 2452 } else {
3311 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat == 2453 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
3312 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
3313 } 2454 }
3314}
3315 2455
3316static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset,
3317 uint8_t *data)
3318{
3319 int i;
3320 2456
3321 switch(stringset) { 2457 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
3322 case ETH_SS_STATS: 2458 BUG_ON(!res);
3323 for (i=0; i < MV643XX_STATS_LEN; i++) { 2459 dev->irq = res->start;
3324 memcpy(data + i * ETH_GSTRING_LEN, 2460
3325 mv643xx_gstrings_stats[i].stat_string, 2461 dev->hard_start_xmit = mv643xx_eth_xmit;
3326 ETH_GSTRING_LEN); 2462 dev->open = mv643xx_eth_open;
3327 } 2463 dev->stop = mv643xx_eth_stop;
3328 break; 2464 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
3329 } 2465 dev->set_mac_address = mv643xx_eth_set_mac_address;
2466 dev->do_ioctl = mv643xx_eth_ioctl;
2467 dev->change_mtu = mv643xx_eth_change_mtu;
2468 dev->tx_timeout = mv643xx_eth_tx_timeout;
2469#ifdef CONFIG_NET_POLL_CONTROLLER
2470 dev->poll_controller = mv643xx_eth_netpoll;
2471#endif
2472 dev->watchdog_timeo = 2 * HZ;
2473 dev->base_addr = 0;
2474
2475#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2476 /*
2477 * Zero copy can only work if we use Discovery II memory. Else, we will
2478 * have to map the buffers to ISA memory which is only 16 MB
2479 */
2480 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2481#endif
2482
2483 SET_NETDEV_DEV(dev, &pdev->dev);
2484
2485 if (mp->shared->win_protect)
2486 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2487
2488 err = register_netdev(dev);
2489 if (err)
2490 goto out;
2491
2492 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2493 mp->port_num, print_mac(mac, dev->dev_addr));
2494
2495 if (dev->features & NETIF_F_SG)
2496 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
2497
2498 if (dev->features & NETIF_F_IP_CSUM)
2499 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
2500
2501#ifdef MV643XX_ETH_NAPI
2502 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
2503#endif
2504
2505 if (mp->tx_desc_sram_size > 0)
2506 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2507
2508 return 0;
2509
2510out:
2511 free_netdev(dev);
2512
2513 return err;
3330} 2514}
3331 2515
3332static u32 mv643xx_eth_get_link(struct net_device *dev) 2516static int mv643xx_eth_remove(struct platform_device *pdev)
3333{ 2517{
3334 struct mv643xx_private *mp = netdev_priv(dev); 2518 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3335 2519
3336 return mii_link_ok(&mp->mii); 2520 unregister_netdev(mp->dev);
2521 flush_scheduled_work();
2522 free_netdev(mp->dev);
2523
2524 platform_set_drvdata(pdev, NULL);
2525
2526 return 0;
3337} 2527}
3338 2528
3339static int mv643xx_eth_nway_restart(struct net_device *dev) 2529static void mv643xx_eth_shutdown(struct platform_device *pdev)
3340{ 2530{
3341 struct mv643xx_private *mp = netdev_priv(dev); 2531 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3342 2532
3343 return mii_nway_restart(&mp->mii); 2533 /* Mask all interrupts on ethernet port */
2534 wrl(mp, INT_MASK(mp->port_num), 0);
2535 rdl(mp, INT_MASK(mp->port_num));
2536
2537 if (netif_running(mp->dev))
2538 port_reset(mp);
3344} 2539}
3345 2540
3346static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2541static struct platform_driver mv643xx_eth_driver = {
2542 .probe = mv643xx_eth_probe,
2543 .remove = mv643xx_eth_remove,
2544 .shutdown = mv643xx_eth_shutdown,
2545 .driver = {
2546 .name = MV643XX_ETH_NAME,
2547 .owner = THIS_MODULE,
2548 },
2549};
2550
2551static int __init mv643xx_eth_init_module(void)
3347{ 2552{
3348 struct mv643xx_private *mp = netdev_priv(dev); 2553 int rc;
2554
2555 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2556 if (!rc) {
2557 rc = platform_driver_register(&mv643xx_eth_driver);
2558 if (rc)
2559 platform_driver_unregister(&mv643xx_eth_shared_driver);
2560 }
3349 2561
3350 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL); 2562 return rc;
3351} 2563}
2564module_init(mv643xx_eth_init_module);
3352 2565
3353static const struct ethtool_ops mv643xx_ethtool_ops = { 2566static void __exit mv643xx_eth_cleanup_module(void)
3354 .get_settings = mv643xx_get_settings, 2567{
3355 .set_settings = mv643xx_set_settings, 2568 platform_driver_unregister(&mv643xx_eth_driver);
3356 .get_drvinfo = mv643xx_get_drvinfo, 2569 platform_driver_unregister(&mv643xx_eth_shared_driver);
3357 .get_link = mv643xx_eth_get_link, 2570}
3358 .set_sg = ethtool_op_set_sg, 2571module_exit(mv643xx_eth_cleanup_module);
3359 .get_sset_count = mv643xx_get_sset_count,
3360 .get_ethtool_stats = mv643xx_get_ethtool_stats,
3361 .get_strings = mv643xx_get_strings,
3362 .nway_reset = mv643xx_eth_nway_restart,
3363};
3364 2572
3365/************* End ethtool support *************************/ 2573MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2574 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2575MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2576MODULE_LICENSE("GPL");
2577MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2578MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index 7f1cfc48e1b2..64b7effe49dd 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -51,7 +51,7 @@
51#include "sky2.h" 51#include "sky2.h"
52 52
53#define DRV_NAME "sky2" 53#define DRV_NAME "sky2"
54#define DRV_VERSION "1.21" 54#define DRV_VERSION "1.22"
55#define PFX DRV_NAME " " 55#define PFX DRV_NAME " "
56 56
57/* 57/*
@@ -98,7 +98,7 @@ static int disable_msi = 0;
98module_param(disable_msi, int, 0); 98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); 99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100 100
101static const struct pci_device_id sky2_id_table[] = { 101static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */ 102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */ 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */ 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
@@ -136,6 +136,7 @@ static const struct pci_device_id sky2_id_table[] = {
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */ 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */ 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */ 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
139 { 0 } 140 { 0 }
140}; 141};
141 142
@@ -146,17 +147,6 @@ static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
146static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; 147static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
147static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 }; 148static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
148 149
149/* This driver supports yukon2 chipset only */
150static const char *yukon2_name[] = {
151 "XL", /* 0xb3 */
152 "EC Ultra", /* 0xb4 */
153 "Extreme", /* 0xb5 */
154 "EC", /* 0xb6 */
155 "FE", /* 0xb7 */
156 "FE+", /* 0xb8 */
157 "Supreme", /* 0xb9 */
158};
159
160static void sky2_set_multicast(struct net_device *dev); 150static void sky2_set_multicast(struct net_device *dev);
161 151
162/* Access to PHY via serial interconnect */ 152/* Access to PHY via serial interconnect */
@@ -658,8 +648,7 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
658 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); 648 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
659 } 649 }
660 650
661 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 651 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
662 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
663 /* apply fixes in PHY AFE */ 652 /* apply fixes in PHY AFE */
664 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); 653 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
665 654
@@ -667,9 +656,11 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
667 gm_phy_write(hw, port, 0x18, 0xaa99); 656 gm_phy_write(hw, port, 0x18, 0xaa99);
668 gm_phy_write(hw, port, 0x17, 0x2011); 657 gm_phy_write(hw, port, 0x17, 0x2011);
669 658
670 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ 659 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
671 gm_phy_write(hw, port, 0x18, 0xa204); 660 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
672 gm_phy_write(hw, port, 0x17, 0x2002); 661 gm_phy_write(hw, port, 0x18, 0xa204);
662 gm_phy_write(hw, port, 0x17, 0x2002);
663 }
673 664
674 /* set page register to 0 */ 665 /* set page register to 0 */
675 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 666 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
@@ -678,7 +669,8 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
678 /* apply workaround for integrated resistors calibration */ 669 /* apply workaround for integrated resistors calibration */
679 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17); 670 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
680 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60); 671 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
681 } else if (hw->chip_id != CHIP_ID_YUKON_EX) { 672 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
673 hw->chip_id < CHIP_ID_YUKON_SUPR) {
682 /* no effect on Yukon-XL */ 674 /* no effect on Yukon-XL */
683 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); 675 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
684 676
@@ -2818,6 +2810,7 @@ static u32 sky2_mhz(const struct sky2_hw *hw)
2818 case CHIP_ID_YUKON_EC_U: 2810 case CHIP_ID_YUKON_EC_U:
2819 case CHIP_ID_YUKON_EX: 2811 case CHIP_ID_YUKON_EX:
2820 case CHIP_ID_YUKON_SUPR: 2812 case CHIP_ID_YUKON_SUPR:
2813 case CHIP_ID_YUKON_UL_2:
2821 return 125; 2814 return 125;
2822 2815
2823 case CHIP_ID_YUKON_FE: 2816 case CHIP_ID_YUKON_FE:
@@ -2910,6 +2903,11 @@ static int __devinit sky2_init(struct sky2_hw *hw)
2910 | SKY2_HW_ADV_POWER_CTL; 2903 | SKY2_HW_ADV_POWER_CTL;
2911 break; 2904 break;
2912 2905
2906 case CHIP_ID_YUKON_UL_2:
2907 hw->flags = SKY2_HW_GIGABIT
2908 | SKY2_HW_ADV_POWER_CTL;
2909 break;
2910
2913 default: 2911 default:
2914 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", 2912 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2915 hw->chip_id); 2913 hw->chip_id);
@@ -4265,12 +4263,34 @@ static int __devinit pci_wake_enabled(struct pci_dev *dev)
4265 return value & PCI_PM_CTRL_PME_ENABLE; 4263 return value & PCI_PM_CTRL_PME_ENABLE;
4266} 4264}
4267 4265
4266/* This driver supports yukon2 chipset only */
4267static const char *sky2_name(u8 chipid, char *buf, int sz)
4268{
4269 const char *name[] = {
4270 "XL", /* 0xb3 */
4271 "EC Ultra", /* 0xb4 */
4272 "Extreme", /* 0xb5 */
4273 "EC", /* 0xb6 */
4274 "FE", /* 0xb7 */
4275 "FE+", /* 0xb8 */
4276 "Supreme", /* 0xb9 */
4277 "UL 2", /* 0xba */
4278 };
4279
4280 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
4281 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4282 else
4283 snprintf(buf, sz, "(chip %#x)", chipid);
4284 return buf;
4285}
4286
4268static int __devinit sky2_probe(struct pci_dev *pdev, 4287static int __devinit sky2_probe(struct pci_dev *pdev,
4269 const struct pci_device_id *ent) 4288 const struct pci_device_id *ent)
4270{ 4289{
4271 struct net_device *dev; 4290 struct net_device *dev;
4272 struct sky2_hw *hw; 4291 struct sky2_hw *hw;
4273 int err, using_dac = 0, wol_default; 4292 int err, using_dac = 0, wol_default;
4293 char buf1[16];
4274 4294
4275 err = pci_enable_device(pdev); 4295 err = pci_enable_device(pdev);
4276 if (err) { 4296 if (err) {
@@ -4341,10 +4361,10 @@ static int __devinit sky2_probe(struct pci_dev *pdev,
4341 if (err) 4361 if (err)
4342 goto err_out_iounmap; 4362 goto err_out_iounmap;
4343 4363
4344 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n", 4364 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-2 %s rev %d\n",
4345 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0), 4365 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4346 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL], 4366 pdev->irq, sky2_name(hw->chip_id, buf1, sizeof(buf1)),
4347 hw->chip_id, hw->chip_rev); 4367 hw->chip_rev);
4348 4368
4349 sky2_reset(hw); 4369 sky2_reset(hw);
4350 4370
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index 1fa82bf029d9..4d9c4a19bb85 100644
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -441,6 +441,7 @@ enum {
441 CHIP_ID_YUKON_FE = 0xb7, /* YUKON-2 FE */ 441 CHIP_ID_YUKON_FE = 0xb7, /* YUKON-2 FE */
442 CHIP_ID_YUKON_FE_P = 0xb8, /* YUKON-2 FE+ */ 442 CHIP_ID_YUKON_FE_P = 0xb8, /* YUKON-2 FE+ */
443 CHIP_ID_YUKON_SUPR = 0xb9, /* YUKON-2 Supreme */ 443 CHIP_ID_YUKON_SUPR = 0xb9, /* YUKON-2 Supreme */
444 CHIP_ID_YUKON_UL_2 = 0xba, /* YUKON-2 Ultra 2 */
444}; 445};
445enum yukon_ec_rev { 446enum yukon_ec_rev {
446 CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */ 447 CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
diff --git a/include/linux/mv643xx_eth.h b/include/linux/mv643xx_eth.h
index a15cdd4a8e58..12078577aef6 100644
--- a/include/linux/mv643xx_eth.h
+++ b/include/linux/mv643xx_eth.h
@@ -17,30 +17,59 @@
17 17
18struct mv643xx_eth_shared_platform_data { 18struct mv643xx_eth_shared_platform_data {
19 struct mbus_dram_target_info *dram; 19 struct mbus_dram_target_info *dram;
20 unsigned int t_clk; 20 unsigned int t_clk;
21}; 21};
22 22
23struct mv643xx_eth_platform_data { 23struct mv643xx_eth_platform_data {
24 /*
25 * Pointer back to our parent instance, and our port number.
26 */
24 struct platform_device *shared; 27 struct platform_device *shared;
25 int port_number; 28 int port_number;
26 29
30 /*
31 * Whether a PHY is present, and if yes, at which address.
32 */
27 struct platform_device *shared_smi; 33 struct platform_device *shared_smi;
34 int force_phy_addr;
35 int phy_addr;
28 36
29 u16 force_phy_addr; /* force override if phy_addr == 0 */ 37 /*
30 u16 phy_addr; 38 * Use this MAC address if it is valid, overriding the
31 39 * address that is already in the hardware.
32 /* If speed is 0, then speed and duplex are autonegotiated. */ 40 */
33 int speed; /* 0, SPEED_10, SPEED_100, SPEED_1000 */ 41 u8 mac_addr[6];
34 int duplex; /* DUPLEX_HALF or DUPLEX_FULL */ 42
35 43 /*
36 /* non-zero values of the following fields override defaults */ 44 * If speed is 0, autonegotiation is enabled.
37 u32 tx_queue_size; 45 * Valid values for speed: 0, SPEED_10, SPEED_100, SPEED_1000.
38 u32 rx_queue_size; 46 * Valid values for duplex: DUPLEX_HALF, DUPLEX_FULL.
39 u32 tx_sram_addr; 47 */
40 u32 tx_sram_size; 48 int speed;
41 u32 rx_sram_addr; 49 int duplex;
42 u32 rx_sram_size; 50
43 u8 mac_addr[6]; /* mac address if non-zero*/ 51 /*
52 * Which RX/TX queues to use.
53 */
54 int rx_queue_mask;
55 int tx_queue_mask;
56
57 /*
58 * Override default RX/TX queue sizes if nonzero.
59 */
60 int rx_queue_size;
61 int tx_queue_size;
62
63 /*
64 * Use on-chip SRAM for RX/TX descriptors if size is nonzero
65 * and sufficient to contain all descriptors for the requested
66 * ring sizes.
67 */
68 unsigned long rx_sram_addr;
69 int rx_sram_size;
70 unsigned long tx_sram_addr;
71 int tx_sram_size;
44}; 72};
45 73
46#endif /* __LINUX_MV643XX_ETH_H */ 74
75#endif
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index 06d8ea5992df..4bf613cd9e2d 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -1479,6 +1479,7 @@ extern void __dev_addr_unsync(struct dev_addr_list **to, int *to_count, struct
1479extern void dev_set_promiscuity(struct net_device *dev, int inc); 1479extern void dev_set_promiscuity(struct net_device *dev, int inc);
1480extern void dev_set_allmulti(struct net_device *dev, int inc); 1480extern void dev_set_allmulti(struct net_device *dev, int inc);
1481extern void netdev_state_change(struct net_device *dev); 1481extern void netdev_state_change(struct net_device *dev);
1482extern void netdev_bonding_change(struct net_device *dev);
1482extern void netdev_features_change(struct net_device *dev); 1483extern void netdev_features_change(struct net_device *dev);
1483/* Load a device via the kmod */ 1484/* Load a device via the kmod */
1484extern void dev_load(struct net *net, const char *name); 1485extern void dev_load(struct net *net, const char *name);
@@ -1505,6 +1506,9 @@ extern void *dev_seq_next(struct seq_file *seq, void *v, loff_t *pos);
1505extern void dev_seq_stop(struct seq_file *seq, void *v); 1506extern void dev_seq_stop(struct seq_file *seq, void *v);
1506#endif 1507#endif
1507 1508
1509extern int netdev_class_create_file(struct class_attribute *class_attr);
1510extern void netdev_class_remove_file(struct class_attribute *class_attr);
1511
1508extern void linkwatch_run_queue(void); 1512extern void linkwatch_run_queue(void);
1509 1513
1510extern int netdev_compute_features(unsigned long all, unsigned long one); 1514extern int netdev_compute_features(unsigned long all, unsigned long one);
diff --git a/include/linux/notifier.h b/include/linux/notifier.h
index 0ff6224d172a..bd3d72ddf333 100644
--- a/include/linux/notifier.h
+++ b/include/linux/notifier.h
@@ -197,6 +197,7 @@ static inline int notifier_to_errno(int ret)
197#define NETDEV_GOING_DOWN 0x0009 197#define NETDEV_GOING_DOWN 0x0009
198#define NETDEV_CHANGENAME 0x000A 198#define NETDEV_CHANGENAME 0x000A
199#define NETDEV_FEAT_CHANGE 0x000B 199#define NETDEV_FEAT_CHANGE 0x000B
200#define NETDEV_BONDING_FAILOVER 0x000C
200 201
201#define SYS_DOWN 0x0001 /* Notify of system down */ 202#define SYS_DOWN 0x0001 /* Notify of system down */
202#define SYS_RESTART SYS_DOWN 203#define SYS_RESTART SYS_DOWN
diff --git a/net/core/dev.c b/net/core/dev.c
index 68d8df0992ab..0e45742e7158 100644
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -961,6 +961,12 @@ void netdev_state_change(struct net_device *dev)
961 } 961 }
962} 962}
963 963
964void netdev_bonding_change(struct net_device *dev)
965{
966 call_netdevice_notifiers(NETDEV_BONDING_FAILOVER, dev);
967}
968EXPORT_SYMBOL(netdev_bonding_change);
969
964/** 970/**
965 * dev_load - load a network module 971 * dev_load - load a network module
966 * @net: the applicable net namespace 972 * @net: the applicable net namespace
diff --git a/net/core/net-sysfs.c b/net/core/net-sysfs.c
index dccd737ea2e3..3f7941319217 100644
--- a/net/core/net-sysfs.c
+++ b/net/core/net-sysfs.c
@@ -468,6 +468,19 @@ int netdev_register_kobject(struct net_device *net)
468 return device_add(dev); 468 return device_add(dev);
469} 469}
470 470
471int netdev_class_create_file(struct class_attribute *class_attr)
472{
473 return class_create_file(&net_class, class_attr);
474}
475
476void netdev_class_remove_file(struct class_attribute *class_attr)
477{
478 class_remove_file(&net_class, class_attr);
479}
480
481EXPORT_SYMBOL(netdev_class_create_file);
482EXPORT_SYMBOL(netdev_class_remove_file);
483
471void netdev_initialize_kobject(struct net_device *net) 484void netdev_initialize_kobject(struct net_device *net)
472{ 485{
473 struct device *device = &(net->dev); 486 struct device *device = &(net->dev);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-03 10:25:47 -0500