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authorMichael Hennerich <michael.hennerich@analog.com>2007-10-21 04:54:27 -0400
committerBryan Wu <bryan.wu@analog.com>2007-10-21 04:54:27 -0400
commit590031450a52c373bf72f5fb156fbcc0c78c6f2c (patch)
tree0e631bc6e8af9422635535459aaaf10fdddab357
parentcfa76f024f7c9e65169425804e5b32e71f66d0ee (diff)
Blackfin arch: add new processor ADSP-BF52x arch/mach support
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat
-rw-r--r--arch/blackfin/Kconfig51
-rw-r--r--arch/blackfin/Makefile6
-rw-r--r--arch/blackfin/configs/BF527-EZKIT_defconfig1241
-rw-r--r--arch/blackfin/kernel/bfin_gpio.c35
-rw-r--r--arch/blackfin/kernel/reboot.c2
-rw-r--r--arch/blackfin/mach-bf527/Kconfig251
-rw-r--r--arch/blackfin/mach-bf527/Makefile9
-rw-r--r--arch/blackfin/mach-bf527/boards/Makefile7
-rw-r--r--arch/blackfin/mach-bf527/boards/eth_mac.c50
-rw-r--r--arch/blackfin/mach-bf527/boards/ezkit.c737
-rw-r--r--arch/blackfin/mach-bf527/cpu.c161
-rw-r--r--arch/blackfin/mach-bf527/dma.c115
-rw-r--r--arch/blackfin/mach-bf527/head.S456
-rw-r--r--arch/blackfin/mach-bf527/ints-priority.c100
-rw-r--r--arch/blackfin/mach-common/ints-priority-sc.c41
-rw-r--r--include/asm-blackfin/bf5xx_timers.h2
-rw-r--r--include/asm-blackfin/gpio.h3
-rw-r--r--include/asm-blackfin/mach-bf527/anomaly.h8
-rw-r--r--include/asm-blackfin/mach-bf527/bf527.h127
-rw-r--r--include/asm-blackfin/mach-bf527/bfin_serial_5xx.h152
-rw-r--r--include/asm-blackfin/mach-bf527/blackfin.h78
-rw-r--r--include/asm-blackfin/mach-bf527/cdefBF52x_base.h19
-rw-r--r--include/asm-blackfin/mach-bf527/defBF527.h4
-rw-r--r--include/asm-blackfin/mach-bf527/defBF52x_base.h9
-rw-r--r--include/asm-blackfin/mach-bf527/dma.h60
-rw-r--r--include/asm-blackfin/mach-bf527/irq.h263
-rw-r--r--include/asm-blackfin/mach-bf527/mem_init.h337
-rw-r--r--include/asm-blackfin/mach-bf527/mem_map.h98
-rw-r--r--include/asm-blackfin/mach-bf527/portmux.h205
29 files changed, 4590 insertions, 37 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index ad28dc76fc97..178305350993 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -71,7 +71,7 @@ config GENERIC_CALIBRATE_DELAY
71 71
72config IRQCHIP_DEMUX_GPIO 72config IRQCHIP_DEMUX_GPIO
73 bool 73 bool
74 depends on (BF53x || BF561 || BF54x) 74 depends on (BF52x || BF53x || BF561 || BF54x)
75 default y 75 default y
76 76
77source "init/Kconfig" 77source "init/Kconfig"
@@ -85,6 +85,21 @@ choice
85 prompt "CPU" 85 prompt "CPU"
86 default BF533 86 default BF533
87 87
88config BF522
89 bool "BF522"
90 help
91 BF522 Processor Support.
92
93config BF525
94 bool "BF525"
95 help
96 BF525 Processor Support.
97
98config BF527
99 bool "BF527"
100 help
101 BF527 Processor Support.
102
88config BF531 103config BF531
89 bool "BF531" 104 bool "BF531"
90 help 105 help
@@ -144,13 +159,18 @@ endchoice
144 159
145choice 160choice
146 prompt "Silicon Rev" 161 prompt "Silicon Rev"
162 default BF_REV_0_1 if BF527
147 default BF_REV_0_2 if BF537 163 default BF_REV_0_2 if BF537
148 default BF_REV_0_3 if BF533 164 default BF_REV_0_3 if BF533
149 default BF_REV_0_0 if BF549 165 default BF_REV_0_0 if BF549
150 166
151config BF_REV_0_0 167config BF_REV_0_0
152 bool "0.0" 168 bool "0.0"
153 depends on (BF549) 169 depends on (BF549 || BF527)
170
171config BF_REV_0_1
172 bool "0.2"
173 depends on (BF549 || BF527)
154 174
155config BF_REV_0_2 175config BF_REV_0_2
156 bool "0.2" 176 bool "0.2"
@@ -176,6 +196,11 @@ config BF_REV_NONE
176 196
177endchoice 197endchoice
178 198
199config BF52x
200 bool
201 depends on (BF522 || BF525 || BF527)
202 default y
203
179config BF53x 204config BF53x
180 bool 205 bool
181 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) 206 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
@@ -204,6 +229,12 @@ choice
204 configuration to ensure that all the other settings are 229 configuration to ensure that all the other settings are
205 correct. 230 correct.
206 231
232config BFIN527_EZKIT
233 bool "BF527-EZKIT"
234 depends on (BF522 || BF525 || BF527)
235 help
236 BF533-EZKIT-LITE board Support.
237
207config BFIN533_EZKIT 238config BFIN533_EZKIT
208 bool "BF533-EZKIT" 239 bool "BF533-EZKIT"
209 depends on (BF533 || BF532 || BF531) 240 depends on (BF533 || BF532 || BF531)
@@ -299,11 +330,17 @@ config MEM_MT48LC8M32B2B5_7
299 depends on (BFIN561_BLUETECHNIX_CM) 330 depends on (BFIN561_BLUETECHNIX_CM)
300 default y 331 default y
301 332
333config MEM_MT48LC32M16A2TG_75
334 bool
335 depends on (BFIN527_EZKIT)
336 default y
337
302config BFIN_SHARED_FLASH_ENET 338config BFIN_SHARED_FLASH_ENET
303 bool 339 bool
304 depends on (BFIN533_STAMP) 340 depends on (BFIN533_STAMP)
305 default y 341 default y
306 342
343source "arch/blackfin/mach-bf527/Kconfig"
307source "arch/blackfin/mach-bf533/Kconfig" 344source "arch/blackfin/mach-bf533/Kconfig"
308source "arch/blackfin/mach-bf561/Kconfig" 345source "arch/blackfin/mach-bf561/Kconfig"
309source "arch/blackfin/mach-bf537/Kconfig" 346source "arch/blackfin/mach-bf537/Kconfig"
@@ -329,7 +366,7 @@ config CLKIN_HZ
329 int "Crystal Frequency in Hz" 366 int "Crystal Frequency in Hz"
330 default "11059200" if BFIN533_STAMP 367 default "11059200" if BFIN533_STAMP
331 default "27000000" if BFIN533_EZKIT 368 default "27000000" if BFIN533_EZKIT
332 default "25000000" if BFIN537_STAMP 369 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT)
333 default "30000000" if BFIN561_EZKIT 370 default "30000000" if BFIN561_EZKIT
334 default "24576000" if PNAV10 371 default "24576000" if PNAV10
335 help 372 help
@@ -362,7 +399,7 @@ config VCO_MULT
362 range 1 64 399 range 1 64
363 default "22" if BFIN533_EZKIT 400 default "22" if BFIN533_EZKIT
364 default "45" if BFIN533_STAMP 401 default "45" if BFIN533_STAMP
365 default "20" if BFIN537_STAMP 402 default "20" if (BFIN537_STAMP || BFIN527_EZKIT)
366 default "22" if BFIN533_BLUETECHNIX_CM 403 default "22" if BFIN533_BLUETECHNIX_CM
367 default "20" if BFIN537_BLUETECHNIX_CM 404 default "20" if BFIN537_BLUETECHNIX_CM
368 default "20" if BFIN561_BLUETECHNIX_CM 405 default "20" if BFIN561_BLUETECHNIX_CM
@@ -398,7 +435,7 @@ config SCLK_DIV
398 range 1 15 435 range 1 15
399 default 5 if BFIN533_EZKIT 436 default 5 if BFIN533_EZKIT
400 default 5 if BFIN533_STAMP 437 default 5 if BFIN533_STAMP
401 default 4 if BFIN537_STAMP 438 default 4 if (BFIN537_STAMP || BFIN527_EZKIT)
402 default 5 if BFIN533_BLUETECHNIX_CM 439 default 5 if BFIN533_BLUETECHNIX_CM
403 default 4 if BFIN537_BLUETECHNIX_CM 440 default 4 if BFIN537_BLUETECHNIX_CM
404 default 4 if BFIN561_BLUETECHNIX_CM 441 default 4 if BFIN561_BLUETECHNIX_CM
@@ -450,6 +487,7 @@ comment "Memory Setup"
450config MEM_SIZE 487config MEM_SIZE
451 int "SDRAM Memory Size in MBytes" 488 int "SDRAM Memory Size in MBytes"
452 default 32 if BFIN533_EZKIT 489 default 32 if BFIN533_EZKIT
490 default 64 if BFIN527_EZKIT
453 default 64 if BFIN537_STAMP 491 default 64 if BFIN537_STAMP
454 default 64 if BFIN561_EZKIT 492 default 64 if BFIN561_EZKIT
455 default 128 if BFIN533_STAMP 493 default 128 if BFIN533_STAMP
@@ -459,6 +497,7 @@ config MEM_ADD_WIDTH
459 int "SDRAM Memory Address Width" 497 int "SDRAM Memory Address Width"
460 default 9 if BFIN533_EZKIT 498 default 9 if BFIN533_EZKIT
461 default 9 if BFIN561_EZKIT 499 default 9 if BFIN561_EZKIT
500 default 10 if BFIN527_EZKIT
462 default 10 if BFIN537_STAMP 501 default 10 if BFIN537_STAMP
463 default 11 if BFIN533_STAMP 502 default 11 if BFIN533_STAMP
464 default 10 if PNAV10 503 default 10 if PNAV10
@@ -751,7 +790,7 @@ config LARGE_ALLOCS
751 790
752config BFIN_DMA_5XX 791config BFIN_DMA_5XX
753 bool "Enable DMA Support" 792 bool "Enable DMA Support"
754 depends on (BF533 || BF532 || BF531 || BF537 || BF536 || BF534 || BF561 || BF54x) 793 depends on (BF52x || BF53x || BF561 || BF54x)
755 default y 794 default y
756 help 795 help
757 DMA driver for BF5xx. 796 DMA driver for BF5xx.
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index 368933760d28..d80421c7b302 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -18,6 +18,9 @@ KALLSYMS += --symbol-prefix=_
18KBUILD_DEFCONFIG := BF537-STAMP_defconfig 18KBUILD_DEFCONFIG := BF537-STAMP_defconfig
19 19
20# setup the machine name and the machine dependent settings 20# setup the machine name and the machine dependent settings
21machine-$(CONFIG_BF522) := bf527
22machine-$(CONFIG_BF525) := bf527
23machine-$(CONFIG_BF527) := bf527
21machine-$(CONFIG_BF531) := bf533 24machine-$(CONFIG_BF531) := bf533
22machine-$(CONFIG_BF532) := bf533 25machine-$(CONFIG_BF532) := bf533
23machine-$(CONFIG_BF533) := bf533 26machine-$(CONFIG_BF533) := bf533
@@ -32,6 +35,9 @@ machine-$(CONFIG_BF561) := bf561
32MACHINE := $(machine-y) 35MACHINE := $(machine-y)
33export MACHINE 36export MACHINE
34 37
38cpu-$(CONFIG_BF522) := bf522
39cpu-$(CONFIG_BF525) := bf525
40cpu-$(CONFIG_BF527) := bf527
35cpu-$(CONFIG_BF531) := bf531 41cpu-$(CONFIG_BF531) := bf531
36cpu-$(CONFIG_BF532) := bf532 42cpu-$(CONFIG_BF532) := bf532
37cpu-$(CONFIG_BF533) := bf533 43cpu-$(CONFIG_BF533) := bf533
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig
new file mode 100644
index 000000000000..df974e785ee2
--- /dev/null
+++ b/arch/blackfin/configs/BF527-EZKIT_defconfig
@@ -0,0 +1,1241 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.22.9
4#
5# CONFIG_MMU is not set
6# CONFIG_FPU is not set
7CONFIG_RWSEM_GENERIC_SPINLOCK=y
8# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
9CONFIG_BLACKFIN=y
10CONFIG_ZONE_DMA=y
11CONFIG_BFIN=y
12CONFIG_SEMAPHORE_SLEEPERS=y
13CONFIG_GENERIC_FIND_NEXT_BIT=y
14CONFIG_GENERIC_HWEIGHT=y
15CONFIG_GENERIC_HARDIRQS=y
16CONFIG_GENERIC_IRQ_PROBE=y
17# CONFIG_GENERIC_TIME is not set
18CONFIG_GENERIC_GPIO=y
19CONFIG_FORCE_MAX_ZONEORDER=14
20CONFIG_GENERIC_CALIBRATE_DELAY=y
21CONFIG_IRQCHIP_DEMUX_GPIO=y
22CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
23
24#
25# Code maturity level options
26#
27CONFIG_EXPERIMENTAL=y
28CONFIG_BROKEN_ON_SMP=y
29CONFIG_INIT_ENV_ARG_LIMIT=32
30
31#
32# General setup
33#
34CONFIG_LOCALVERSION=""
35CONFIG_LOCALVERSION_AUTO=y
36CONFIG_SYSVIPC=y
37# CONFIG_IPC_NS is not set
38CONFIG_SYSVIPC_SYSCTL=y
39# CONFIG_POSIX_MQUEUE is not set
40# CONFIG_BSD_PROCESS_ACCT is not set
41# CONFIG_TASKSTATS is not set
42# CONFIG_UTS_NS is not set
43# CONFIG_AUDIT is not set
44CONFIG_IKCONFIG=y
45CONFIG_IKCONFIG_PROC=y
46CONFIG_LOG_BUF_SHIFT=14
47CONFIG_SYSFS_DEPRECATED=y
48# CONFIG_RELAY is not set
49CONFIG_BLK_DEV_INITRD=y
50CONFIG_INITRAMFS_SOURCE=""
51# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
52CONFIG_SYSCTL=y
53CONFIG_EMBEDDED=y
54CONFIG_UID16=y
55CONFIG_SYSCTL_SYSCALL=y
56CONFIG_KALLSYMS=y
57# CONFIG_KALLSYMS_EXTRA_PASS is not set
58CONFIG_HOTPLUG=y
59CONFIG_PRINTK=y
60CONFIG_BUG=y
61CONFIG_ELF_CORE=y
62CONFIG_BASE_FULL=y
63CONFIG_FUTEX=y
64CONFIG_ANON_INODES=y
65CONFIG_EPOLL=y
66CONFIG_SIGNALFD=y
67CONFIG_EVENTFD=y
68CONFIG_VM_EVENT_COUNTERS=y
69CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3
70# CONFIG_NP2 is not set
71CONFIG_SLAB=y
72# CONFIG_SLUB is not set
73# CONFIG_SLOB is not set
74CONFIG_RT_MUTEXES=y
75CONFIG_TINY_SHMEM=y
76CONFIG_BASE_SMALL=0
77
78#
79# Loadable module support
80#
81CONFIG_MODULES=y
82CONFIG_MODULE_UNLOAD=y
83# CONFIG_MODULE_FORCE_UNLOAD is not set
84# CONFIG_MODVERSIONS is not set
85# CONFIG_MODULE_SRCVERSION_ALL is not set
86CONFIG_KMOD=y
87
88#
89# Block layer
90#
91CONFIG_BLOCK=y
92# CONFIG_LBD is not set
93# CONFIG_BLK_DEV_IO_TRACE is not set
94# CONFIG_LSF is not set
95
96#
97# IO Schedulers
98#
99CONFIG_IOSCHED_NOOP=y
100CONFIG_IOSCHED_AS=y
101# CONFIG_IOSCHED_DEADLINE is not set
102CONFIG_IOSCHED_CFQ=y
103CONFIG_DEFAULT_AS=y
104# CONFIG_DEFAULT_DEADLINE is not set
105# CONFIG_DEFAULT_CFQ is not set
106# CONFIG_DEFAULT_NOOP is not set
107CONFIG_DEFAULT_IOSCHED="anticipatory"
108# CONFIG_PREEMPT_NONE is not set
109CONFIG_PREEMPT_VOLUNTARY=y
110# CONFIG_PREEMPT is not set
111
112#
113# Blackfin Processor Options
114#
115
116#
117# Processor and Board Settings
118#
119# CONFIG_BF522 is not set
120# CONFIG_BF525 is not set
121CONFIG_BF527=y
122# CONFIG_BF531 is not set
123# CONFIG_BF532 is not set
124# CONFIG_BF533 is not set
125# CONFIG_BF534 is not set
126# CONFIG_BF536 is not set
127# CONFIG_BF537 is not set
128# CONFIG_BF542 is not set
129# CONFIG_BF544 is not set
130# CONFIG_BF548 is not set
131# CONFIG_BF549 is not set
132# CONFIG_BF561 is not set
133CONFIG_BF_REV_0_0=y
134# CONFIG_BF_REV_0_1 is not set
135# CONFIG_BF_REV_0_2 is not set
136# CONFIG_BF_REV_0_3 is not set
137# CONFIG_BF_REV_0_4 is not set
138# CONFIG_BF_REV_0_5 is not set
139# CONFIG_BF_REV_ANY is not set
140# CONFIG_BF_REV_NONE is not set
141CONFIG_BF52x=y
142CONFIG_BFIN_SINGLE_CORE=y
143CONFIG_BFIN527_EZKIT=y
144# CONFIG_BFIN533_EZKIT is not set
145# CONFIG_BFIN533_STAMP is not set
146# CONFIG_BFIN537_STAMP is not set
147# CONFIG_BFIN533_BLUETECHNIX_CM is not set
148# CONFIG_BFIN537_BLUETECHNIX_CM is not set
149# CONFIG_BFIN548_EZKIT is not set
150# CONFIG_BFIN561_BLUETECHNIX_CM is not set
151# CONFIG_BFIN561_EZKIT is not set
152# CONFIG_BFIN561_TEPLA is not set
153# CONFIG_PNAV10 is not set
154# CONFIG_GENERIC_BOARD is not set
155CONFIG_MEM_MT48LC32M16A2TG_75=y
156
157#
158# BF527 Specific Configuration
159#
160
161#
162# Alternative Multiplexing Scheme
163#
164# CONFIG_BF527_SPORT0_PORTF is not set
165CONFIG_BF527_SPORT0_PORTG=y
166CONFIG_BF527_SPORT0_TSCLK_PG10=y
167# CONFIG_BF527_SPORT0_TSCLK_PG14 is not set
168# CONFIG_BF527_UART1_PORTF is not set
169CONFIG_BF527_UART1_PORTG=y
170# CONFIG_BF527_NAND_D_PORTF is not set
171CONFIG_BF527_NAND_D_PORTH=y
172
173#
174# Interrupt Priority Assignment
175#
176
177#
178# Priority
179#
180CONFIG_IRQ_PLL_WAKEUP=7
181CONFIG_IRQ_DMA0_ERROR=7
182CONFIG_IRQ_DMAR0_BLK=7
183CONFIG_IRQ_DMAR1_BLK=7
184CONFIG_IRQ_DMAR0_OVR=7
185CONFIG_IRQ_DMAR1_OVR=7
186CONFIG_IRQ_PPI_ERROR=7
187CONFIG_IRQ_MAC_ERROR=7
188CONFIG_IRQ_SPORT0_ERROR=7
189CONFIG_IRQ_SPORT1_ERROR=7
190CONFIG_IRQ_UART0_ERROR=7
191CONFIG_IRQ_UART1_ERROR=7
192CONFIG_IRQ_RTC=8
193CONFIG_IRQ_PPI=8
194CONFIG_IRQ_SPORT0_RX=9
195CONFIG_IRQ_SPORT0_TX=9
196CONFIG_IRQ_SPORT1_RX=9
197CONFIG_IRQ_SPORT1_TX=9
198CONFIG_IRQ_TWI=10
199CONFIG_IRQ_SPI=10
200CONFIG_IRQ_UART0_RX=10
201CONFIG_IRQ_UART0_TX=10
202CONFIG_IRQ_UART1_RX=10
203CONFIG_IRQ_UART1_TX=10
204CONFIG_IRQ_OPTSEC=11
205CONFIG_IRQ_CNT=11
206CONFIG_IRQ_MAC_RX=11
207CONFIG_IRQ_PORTH_INTA=11
208CONFIG_IRQ_MAC_TX=11
209CONFIG_IRQ_PORTH_INTB=11
210CONFIG_IRQ_TMR0=12
211CONFIG_IRQ_TMR1=12
212CONFIG_IRQ_TMR2=12
213CONFIG_IRQ_TMR3=12
214CONFIG_IRQ_TMR4=12
215CONFIG_IRQ_TMR5=12
216CONFIG_IRQ_TMR6=12
217CONFIG_IRQ_TMR7=12
218CONFIG_IRQ_PORTG_INTA=12
219CONFIG_IRQ_PORTG_INTB=12
220CONFIG_IRQ_MEM_DMA0=13
221CONFIG_IRQ_MEM_DMA1=13
222CONFIG_IRQ_WATCH=13
223CONFIG_IRQ_PORTF_INTA=13
224CONFIG_IRQ_PORTF_INTB=13
225CONFIG_IRQ_SPI_ERROR=7
226CONFIG_IRQ_NFC_ERROR=7
227CONFIG_IRQ_HDMA_ERROR=7
228CONFIG_IRQ_HDMA=7
229CONFIG_IRQ_USB_EINT=10
230CONFIG_IRQ_USB_INT0=11
231CONFIG_IRQ_USB_INT1=11
232CONFIG_IRQ_USB_INT2=11
233CONFIG_IRQ_USB_DMA=11
234
235#
236# Board customizations
237#
238# CONFIG_CMDLINE_BOOL is not set
239
240#
241# Clock/PLL Setup
242#
243CONFIG_CLKIN_HZ=25000000
244# CONFIG_BFIN_KERNEL_CLOCK is not set
245CONFIG_MAX_VCO_HZ=600000000
246CONFIG_MIN_VCO_HZ=50000000
247CONFIG_MAX_SCLK_HZ=133000000
248CONFIG_MIN_SCLK_HZ=27000000
249
250#
251# Kernel Timer/Scheduler
252#
253# CONFIG_HZ_100 is not set
254CONFIG_HZ_250=y
255# CONFIG_HZ_300 is not set
256# CONFIG_HZ_1000 is not set
257CONFIG_HZ=250
258
259#
260# Memory Setup
261#
262CONFIG_MEM_SIZE=64
263CONFIG_MEM_ADD_WIDTH=10
264CONFIG_BOOT_LOAD=0x1000
265CONFIG_BFIN_SCRATCH_REG_RETN=y
266# CONFIG_BFIN_SCRATCH_REG_RETE is not set
267# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
268
269#
270# Blackfin Kernel Optimizations
271#
272
273#
274# Memory Optimizations
275#
276CONFIG_I_ENTRY_L1=y
277CONFIG_EXCPT_IRQ_SYSC_L1=y
278CONFIG_DO_IRQ_L1=y
279CONFIG_CORE_TIMER_IRQ_L1=y
280CONFIG_IDLE_L1=y
281# CONFIG_SCHEDULE_L1 is not set
282CONFIG_ARITHMETIC_OPS_L1=y
283CONFIG_ACCESS_OK_L1=y
284# CONFIG_MEMSET_L1 is not set
285# CONFIG_MEMCPY_L1 is not set
286# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
287# CONFIG_IP_CHECKSUM_L1 is not set
288CONFIG_CACHELINE_ALIGNED_L1=y
289# CONFIG_SYSCALL_TAB_L1 is not set
290# CONFIG_CPLB_SWITCH_TAB_L1 is not set
291CONFIG_RAMKERNEL=y
292# CONFIG_ROMKERNEL is not set
293CONFIG_SELECT_MEMORY_MODEL=y
294CONFIG_FLATMEM_MANUAL=y
295# CONFIG_DISCONTIGMEM_MANUAL is not set
296# CONFIG_SPARSEMEM_MANUAL is not set
297CONFIG_FLATMEM=y
298CONFIG_FLAT_NODE_MEM_MAP=y
299# CONFIG_SPARSEMEM_STATIC is not set
300CONFIG_SPLIT_PTLOCK_CPUS=4
301# CONFIG_RESOURCES_64BIT is not set
302CONFIG_ZONE_DMA_FLAG=1
303CONFIG_LARGE_ALLOCS=y
304CONFIG_BFIN_DMA_5XX=y
305# CONFIG_DMA_UNCACHED_2M is not set
306CONFIG_DMA_UNCACHED_1M=y
307# CONFIG_DMA_UNCACHED_NONE is not set
308
309#
310# Cache Support
311#
312CONFIG_BFIN_ICACHE=y
313CONFIG_BFIN_DCACHE=y
314# CONFIG_BFIN_DCACHE_BANKA is not set
315# CONFIG_BFIN_ICACHE_LOCK is not set
316# CONFIG_BFIN_WB is not set
317CONFIG_BFIN_WT=y
318CONFIG_L1_MAX_PIECE=16
319
320#
321# Asynchonous Memory Configuration
322#
323
324#
325# EBIU_AMBCTL Global Control
326#
327CONFIG_C_AMCKEN=y
328CONFIG_C_CDPRIO=y
329# CONFIG_C_AMBEN is not set
330# CONFIG_C_AMBEN_B0 is not set
331# CONFIG_C_AMBEN_B0_B1 is not set
332# CONFIG_C_AMBEN_B0_B1_B2 is not set
333CONFIG_C_AMBEN_ALL=y
334
335#
336# EBIU_AMBCTL Control
337#
338CONFIG_BANK_0=0x7BB0
339CONFIG_BANK_1=0x5554
340CONFIG_BANK_2=0x7BB0
341CONFIG_BANK_3=0xFFC0
342
343#
344# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
345#
346# CONFIG_PCI is not set
347# CONFIG_ARCH_SUPPORTS_MSI is not set
348
349#
350# PCCARD (PCMCIA/CardBus) support
351#
352# CONFIG_PCCARD is not set
353
354#
355# Executable file formats
356#
357CONFIG_BINFMT_ELF_FDPIC=y
358CONFIG_BINFMT_FLAT=y
359CONFIG_BINFMT_ZFLAT=y
360# CONFIG_BINFMT_SHARED_FLAT is not set
361# CONFIG_BINFMT_MISC is not set
362
363#
364# Power management options
365#
366# CONFIG_PM is not set
367
368#
369# Networking
370#
371CONFIG_NET=y
372
373#
374# Networking options
375#
376CONFIG_PACKET=y
377# CONFIG_PACKET_MMAP is not set
378CONFIG_UNIX=y
379CONFIG_XFRM=y
380# CONFIG_XFRM_USER is not set
381# CONFIG_XFRM_SUB_POLICY is not set
382# CONFIG_XFRM_MIGRATE is not set
383# CONFIG_NET_KEY is not set
384CONFIG_INET=y
385# CONFIG_IP_MULTICAST is not set
386# CONFIG_IP_ADVANCED_ROUTER is not set
387CONFIG_IP_FIB_HASH=y
388CONFIG_IP_PNP=y
389# CONFIG_IP_PNP_DHCP is not set
390# CONFIG_IP_PNP_BOOTP is not set
391# CONFIG_IP_PNP_RARP is not set
392# CONFIG_NET_IPIP is not set
393# CONFIG_NET_IPGRE is not set
394# CONFIG_ARPD is not set
395CONFIG_SYN_COOKIES=y
396# CONFIG_INET_AH is not set
397# CONFIG_INET_ESP is not set
398# CONFIG_INET_IPCOMP is not set
399# CONFIG_INET_XFRM_TUNNEL is not set
400# CONFIG_INET_TUNNEL is not set
401CONFIG_INET_XFRM_MODE_TRANSPORT=y
402CONFIG_INET_XFRM_MODE_TUNNEL=y
403CONFIG_INET_XFRM_MODE_BEET=y
404CONFIG_INET_DIAG=y
405CONFIG_INET_TCP_DIAG=y
406# CONFIG_TCP_CONG_ADVANCED is not set
407CONFIG_TCP_CONG_CUBIC=y
408CONFIG_DEFAULT_TCP_CONG="cubic"
409# CONFIG_TCP_MD5SIG is not set
410# CONFIG_IPV6 is not set
411# CONFIG_INET6_XFRM_TUNNEL is not set
412# CONFIG_INET6_TUNNEL is not set
413# CONFIG_NETLABEL is not set
414# CONFIG_NETWORK_SECMARK is not set
415# CONFIG_NETFILTER is not set
416# CONFIG_IP_DCCP is not set
417# CONFIG_IP_SCTP is not set
418# CONFIG_TIPC is not set
419# CONFIG_ATM is not set
420# CONFIG_BRIDGE is not set
421# CONFIG_VLAN_8021Q is not set
422# CONFIG_DECNET is not set
423# CONFIG_LLC2 is not set
424# CONFIG_IPX is not set
425# CONFIG_ATALK is not set
426# CONFIG_X25 is not set
427# CONFIG_LAPB is not set
428# CONFIG_ECONET is not set
429# CONFIG_WAN_ROUTER is not set
430
431#
432# QoS and/or fair queueing
433#
434# CONFIG_NET_SCHED is not set
435
436#
437# Network testing
438#
439# CONFIG_NET_PKTGEN is not set
440# CONFIG_HAMRADIO is not set
441# CONFIG_IRDA is not set
442# CONFIG_BT is not set
443# CONFIG_AF_RXRPC is not set
444
445#
446# Wireless
447#
448# CONFIG_CFG80211 is not set
449# CONFIG_WIRELESS_EXT is not set
450# CONFIG_MAC80211 is not set
451# CONFIG_IEEE80211 is not set
452# CONFIG_RFKILL is not set
453
454#
455# Device Drivers
456#
457
458#
459# Generic Driver Options
460#
461CONFIG_STANDALONE=y
462CONFIG_PREVENT_FIRMWARE_BUILD=y
463# CONFIG_FW_LOADER is not set
464# CONFIG_SYS_HYPERVISOR is not set
465
466#
467# Connector - unified userspace <-> kernelspace linker
468#
469# CONFIG_CONNECTOR is not set
470CONFIG_MTD=y
471# CONFIG_MTD_DEBUG is not set
472# CONFIG_MTD_CONCAT is not set
473CONFIG_MTD_PARTITIONS=y
474# CONFIG_MTD_REDBOOT_PARTS is not set
475# CONFIG_MTD_CMDLINE_PARTS is not set
476
477#
478# User Modules And Translation Layers
479#
480CONFIG_MTD_CHAR=m
481CONFIG_MTD_BLKDEVS=y
482CONFIG_MTD_BLOCK=y
483# CONFIG_FTL is not set
484# CONFIG_NFTL is not set
485# CONFIG_INFTL is not set
486# CONFIG_RFD_FTL is not set
487# CONFIG_SSFDC is not set
488
489#
490# RAM/ROM/Flash chip drivers
491#
492# CONFIG_MTD_CFI is not set
493CONFIG_MTD_JEDECPROBE=m
494CONFIG_MTD_GEN_PROBE=m
495# CONFIG_MTD_CFI_ADV_OPTIONS is not set
496CONFIG_MTD_MAP_BANK_WIDTH_1=y
497CONFIG_MTD_MAP_BANK_WIDTH_2=y
498CONFIG_MTD_MAP_BANK_WIDTH_4=y
499# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
500# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
501# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
502CONFIG_MTD_CFI_I1=y
503CONFIG_MTD_CFI_I2=y
504# CONFIG_MTD_CFI_I4 is not set
505# CONFIG_MTD_CFI_I8 is not set
506# CONFIG_MTD_CFI_INTELEXT is not set
507# CONFIG_MTD_CFI_AMDSTD is not set
508# CONFIG_MTD_CFI_STAA is not set
509CONFIG_MTD_MW320D=m
510CONFIG_MTD_RAM=y
511CONFIG_MTD_ROM=m
512# CONFIG_MTD_ABSENT is not set
513
514#
515# Mapping drivers for chip access
516#
517CONFIG_MTD_COMPLEX_MAPPINGS=y
518# CONFIG_MTD_PHYSMAP is not set
519CONFIG_MTD_BF5xx=m
520CONFIG_BFIN_FLASH_SIZE=0x400000
521CONFIG_EBIU_FLASH_BASE=0x20000000
522# CONFIG_MTD_UCLINUX is not set
523# CONFIG_MTD_PLATRAM is not set
524
525#
526# Self-contained MTD device drivers
527#
528# CONFIG_MTD_DATAFLASH is not set
529# CONFIG_MTD_M25P80 is not set
530# CONFIG_MTD_SLRAM is not set
531# CONFIG_MTD_PHRAM is not set
532# CONFIG_MTD_MTDRAM is not set
533# CONFIG_MTD_BLOCK2MTD is not set
534
535#
536# Disk-On-Chip Device Drivers
537#
538# CONFIG_MTD_DOC2000 is not set
539# CONFIG_MTD_DOC2001 is not set
540# CONFIG_MTD_DOC2001PLUS is not set
541CONFIG_MTD_NAND=m
542# CONFIG_MTD_NAND_VERIFY_WRITE is not set
543# CONFIG_MTD_NAND_ECC_SMC is not set
544# CONFIG_MTD_NAND_MUSEUM_IDS is not set
545CONFIG_MTD_NAND_BFIN=m
546CONFIG_BFIN_NAND_BASE=0x20212000
547CONFIG_BFIN_NAND_CLE=2
548CONFIG_BFIN_NAND_ALE=1
549CONFIG_BFIN_NAND_READY=3
550CONFIG_MTD_NAND_IDS=m
551# CONFIG_MTD_NAND_DISKONCHIP is not set
552# CONFIG_MTD_NAND_NANDSIM is not set
553# CONFIG_MTD_NAND_PLATFORM is not set
554# CONFIG_MTD_ONENAND is not set
555
556#
557# UBI - Unsorted block images
558#
559# CONFIG_MTD_UBI is not set
560
561#
562# Parallel port support
563#
564# CONFIG_PARPORT is not set
565
566#
567# Plug and Play support
568#
569# CONFIG_PNPACPI is not set
570
571#
572# Block devices
573#
574# CONFIG_BLK_DEV_COW_COMMON is not set
575# CONFIG_BLK_DEV_LOOP is not set
576# CONFIG_BLK_DEV_NBD is not set
577CONFIG_BLK_DEV_RAM=y
578CONFIG_BLK_DEV_RAM_COUNT=16
579CONFIG_BLK_DEV_RAM_SIZE=4096
580CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
581# CONFIG_CDROM_PKTCDVD is not set
582# CONFIG_ATA_OVER_ETH is not set
583
584#
585# Misc devices
586#
587# CONFIG_IDE is not set
588
589#
590# SCSI device support
591#
592# CONFIG_RAID_ATTRS is not set
593# CONFIG_SCSI is not set
594# CONFIG_SCSI_NETLINK is not set
595# CONFIG_ATA is not set
596
597#
598# Multi-device support (RAID and LVM)
599#
600# CONFIG_MD is not set
601
602#
603# Network device support
604#
605CONFIG_NETDEVICES=y
606# CONFIG_DUMMY is not set
607# CONFIG_BONDING is not set
608# CONFIG_EQUALIZER is not set
609# CONFIG_TUN is not set
610CONFIG_PHYLIB=y
611
612#
613# MII PHY device drivers
614#
615# CONFIG_MARVELL_PHY is not set
616# CONFIG_DAVICOM_PHY is not set
617# CONFIG_QSEMI_PHY is not set
618# CONFIG_LXT_PHY is not set
619# CONFIG_CICADA_PHY is not set
620# CONFIG_VITESSE_PHY is not set
621# CONFIG_SMSC_PHY is not set
622# CONFIG_BROADCOM_PHY is not set
623# CONFIG_FIXED_PHY is not set
624
625#
626# Ethernet (10 or 100Mbit)
627#
628CONFIG_NET_ETHERNET=y
629CONFIG_MII=y
630# CONFIG_SMC91X is not set
631CONFIG_BFIN_MAC=y
632CONFIG_BFIN_MAC_USE_L1=y
633CONFIG_BFIN_TX_DESC_NUM=10
634CONFIG_BFIN_RX_DESC_NUM=20
635CONFIG_BFIN_MAC_RMII=y
636# CONFIG_SMSC911X is not set
637# CONFIG_DM9000 is not set
638CONFIG_NETDEV_1000=y
639CONFIG_NETDEV_10000=y
640
641#
642# Wireless LAN
643#
644# CONFIG_WLAN_PRE80211 is not set
645# CONFIG_WLAN_80211 is not set
646# CONFIG_WAN is not set
647# CONFIG_PPP is not set
648# CONFIG_SLIP is not set
649# CONFIG_SHAPER is not set
650# CONFIG_NETCONSOLE is not set
651# CONFIG_NETPOLL is not set
652# CONFIG_NET_POLL_CONTROLLER is not set
653
654#
655# ISDN subsystem
656#
657# CONFIG_ISDN is not set
658
659#
660# Telephony Support
661#
662# CONFIG_PHONE is not set
663
664#
665# Input device support
666#
667CONFIG_INPUT=y
668# CONFIG_INPUT_FF_MEMLESS is not set
669# CONFIG_INPUT_POLLDEV is not set
670
671#
672# Userland interfaces
673#
674# CONFIG_INPUT_MOUSEDEV is not set
675# CONFIG_INPUT_JOYDEV is not set
676# CONFIG_INPUT_TSDEV is not set
677# CONFIG_INPUT_EVDEV is not set
678# CONFIG_INPUT_EVBUG is not set
679
680#
681# Input Device Drivers
682#
683# CONFIG_INPUT_KEYBOARD is not set
684# CONFIG_INPUT_MOUSE is not set
685# CONFIG_INPUT_JOYSTICK is not set
686# CONFIG_INPUT_TABLET is not set
687# CONFIG_INPUT_TOUCHSCREEN is not set
688CONFIG_INPUT_MISC=y
689# CONFIG_INPUT_ATI_REMOTE is not set
690# CONFIG_INPUT_ATI_REMOTE2 is not set
691# CONFIG_INPUT_KEYSPAN_REMOTE is not set
692# CONFIG_INPUT_POWERMATE is not set
693# CONFIG_INPUT_YEALINK is not set
694# CONFIG_INPUT_UINPUT is not set
695# CONFIG_BF53X_PFBUTTONS is not set
696# CONFIG_TWI_KEYPAD is not set
697
698#
699# Hardware I/O ports
700#
701# CONFIG_SERIO is not set
702# CONFIG_GAMEPORT is not set
703
704#
705# Character devices
706#
707# CONFIG_AD9960 is not set
708# CONFIG_SPI_ADC_BF533 is not set
709# CONFIG_BF5xx_PFLAGS is not set
710# CONFIG_BF5xx_PPIFCD is not set
711# CONFIG_BF5xx_TIMERS is not set
712# CONFIG_BF5xx_PPI is not set
713# CONFIG_BFIN_SPORT is not set
714# CONFIG_BFIN_TIMER_LATENCY is not set
715# CONFIG_TWI_LCD is not set
716# CONFIG_AD5304 is not set
717# CONFIG_BF5xx_TEA5764 is not set
718# CONFIG_BF5xx_FBDMA is not set
719# CONFIG_VT is not set
720# CONFIG_SERIAL_NONSTANDARD is not set
721
722#
723# Serial drivers
724#
725# CONFIG_SERIAL_8250 is not set
726
727#
728# Non-8250 serial port support
729#
730CONFIG_SERIAL_BFIN=y
731CONFIG_SERIAL_BFIN_CONSOLE=y
732# CONFIG_SERIAL_BFIN_DMA is not set
733CONFIG_SERIAL_BFIN_PIO=y
734# CONFIG_SERIAL_BFIN_UART0 is not set
735CONFIG_SERIAL_BFIN_UART1=y
736# CONFIG_BFIN_UART1_CTSRTS is not set
737CONFIG_SERIAL_CORE=y
738CONFIG_SERIAL_CORE_CONSOLE=y
739# CONFIG_SERIAL_BFIN_SPORT is not set
740CONFIG_UNIX98_PTYS=y
741# CONFIG_LEGACY_PTYS is not set
742
743#
744# CAN, the car bus and industrial fieldbus
745#
746# CONFIG_CAN4LINUX is not set
747
748#
749# IPMI
750#
751# CONFIG_IPMI_HANDLER is not set
752CONFIG_WATCHDOG=y
753# CONFIG_WATCHDOG_NOWAYOUT is not set
754
755#
756# Watchdog Device Drivers
757#
758# CONFIG_SOFT_WATCHDOG is not set
759CONFIG_BFIN_WDT=y
760CONFIG_HW_RANDOM=y
761# CONFIG_GEN_RTC is not set
762# CONFIG_R3964 is not set
763# CONFIG_RAW_DRIVER is not set
764
765#
766# TPM devices
767#
768# CONFIG_TCG_TPM is not set
769CONFIG_I2C=y
770CONFIG_I2C_BOARDINFO=y
771CONFIG_I2C_CHARDEV=m
772
773#
774# I2C Algorithms
775#
776# CONFIG_I2C_ALGOBIT is not set
777# CONFIG_I2C_ALGOPCF is not set
778# CONFIG_I2C_ALGOPCA is not set
779
780#
781# I2C Hardware Bus support
782#
783# CONFIG_I2C_BLACKFIN_GPIO is not set
784CONFIG_I2C_BLACKFIN_TWI=m
785CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
786# CONFIG_I2C_GPIO is not set
787# CONFIG_I2C_OCORES is not set
788# CONFIG_I2C_PARPORT_LIGHT is not set
789# CONFIG_I2C_SIMTEC is not set
790# CONFIG_I2C_STUB is not set
791
792#
793# Miscellaneous I2C Chip support
794#
795# CONFIG_SENSORS_DS1337 is not set
796# CONFIG_SENSORS_DS1374 is not set
797# CONFIG_SENSORS_AD5252 is not set
798# CONFIG_SENSORS_EEPROM is not set
799# CONFIG_SENSORS_PCF8574 is not set
800# CONFIG_SENSORS_PCF8575 is not set
801# CONFIG_SENSORS_PCA9543 is not set
802# CONFIG_SENSORS_PCA9539 is not set
803# CONFIG_SENSORS_PCF8591 is not set
804# CONFIG_SENSORS_MAX6875 is not set
805# CONFIG_I2C_DEBUG_CORE is not set
806# CONFIG_I2C_DEBUG_ALGO is not set
807# CONFIG_I2C_DEBUG_BUS is not set
808# CONFIG_I2C_DEBUG_CHIP is not set
809
810#
811# SPI support
812#
813CONFIG_SPI=y
814CONFIG_SPI_MASTER=y
815
816#
817# SPI Master Controller Drivers
818#
819CONFIG_SPI_BFIN=y
820# CONFIG_SPI_BITBANG is not set
821
822#
823# SPI Protocol Masters
824#
825# CONFIG_SPI_AT25 is not set
826# CONFIG_SPI_SPIDEV is not set
827
828#
829# Dallas's 1-wire bus
830#
831# CONFIG_W1 is not set
832CONFIG_HWMON=y
833# CONFIG_HWMON_VID is not set
834# CONFIG_SENSORS_ABITUGURU is not set
835# CONFIG_SENSORS_AD7418 is not set
836# CONFIG_SENSORS_ADM1021 is not set
837# CONFIG_SENSORS_ADM1025 is not set
838# CONFIG_SENSORS_ADM1026 is not set
839# CONFIG_SENSORS_ADM1029 is not set
840# CONFIG_SENSORS_ADM1031 is not set
841# CONFIG_SENSORS_ADM9240 is not set
842# CONFIG_SENSORS_ASB100 is not set
843# CONFIG_SENSORS_ATXP1 is not set
844# CONFIG_SENSORS_DS1621 is not set
845# CONFIG_SENSORS_F71805F is not set
846# CONFIG_SENSORS_FSCHER is not set
847# CONFIG_SENSORS_FSCPOS is not set
848# CONFIG_SENSORS_GL518SM is not set
849# CONFIG_SENSORS_GL520SM is not set
850# CONFIG_SENSORS_IT87 is not set
851# CONFIG_SENSORS_LM63 is not set
852# CONFIG_SENSORS_LM70 is not set
853# CONFIG_SENSORS_LM75 is not set
854# CONFIG_SENSORS_LM77 is not set
855# CONFIG_SENSORS_LM78 is not set
856# CONFIG_SENSORS_LM80 is not set
857# CONFIG_SENSORS_LM83 is not set
858# CONFIG_SENSORS_LM85 is not set
859# CONFIG_SENSORS_LM87 is not set
860# CONFIG_SENSORS_LM90 is not set
861# CONFIG_SENSORS_LM92 is not set
862# CONFIG_SENSORS_MAX1619 is not set
863# CONFIG_SENSORS_MAX6650 is not set
864# CONFIG_SENSORS_PC87360 is not set
865# CONFIG_SENSORS_PC87427 is not set
866# CONFIG_SENSORS_SMSC47M1 is not set
867# CONFIG_SENSORS_SMSC47M192 is not set
868# CONFIG_SENSORS_SMSC47B397 is not set
869# CONFIG_SENSORS_VT1211 is not set
870# CONFIG_SENSORS_W83781D is not set
871# CONFIG_SENSORS_W83791D is not set
872# CONFIG_SENSORS_W83792D is not set
873# CONFIG_SENSORS_W83793 is not set
874# CONFIG_SENSORS_W83L785TS is not set
875# CONFIG_SENSORS_W83627HF is not set
876# CONFIG_SENSORS_W83627EHF is not set
877# CONFIG_HWMON_DEBUG_CHIP is not set
878
879#
880# Multifunction device drivers
881#
882# CONFIG_MFD_SM501 is not set
883
884#
885# Multimedia devices
886#
887# CONFIG_VIDEO_DEV is not set
888# CONFIG_DVB_CORE is not set
889# CONFIG_DAB is not set
890
891#
892# Graphics support
893#
894# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
895
896#
897# Display device support
898#
899# CONFIG_DISPLAY_SUPPORT is not set
900# CONFIG_VGASTATE is not set
901# CONFIG_FB is not set
902
903#
904# Sound
905#
906# CONFIG_SOUND is not set
907
908#
909# HID Devices
910#
911CONFIG_HID=y
912# CONFIG_HID_DEBUG is not set
913
914#
915# USB support
916#
917CONFIG_USB_ARCH_HAS_HCD=y
918# CONFIG_USB_ARCH_HAS_OHCI is not set
919# CONFIG_USB_ARCH_HAS_EHCI is not set
920# CONFIG_USB is not set
921
922#
923# Enable Host or Gadget support to see Inventra options
924#
925
926#
927# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
928#
929
930#
931# USB Gadget Support
932#
933# CONFIG_USB_GADGET is not set
934# CONFIG_MMC is not set
935
936#
937# LED devices
938#
939# CONFIG_NEW_LEDS is not set
940
941#
942# LED drivers
943#
944
945#
946# LED Triggers
947#
948
949#
950# InfiniBand support
951#
952
953#
954# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
955#
956
957#
958# Real Time Clock
959#
960CONFIG_RTC_LIB=y
961CONFIG_RTC_CLASS=y
962CONFIG_RTC_HCTOSYS=y
963CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
964# CONFIG_RTC_DEBUG is not set
965
966#
967# RTC interfaces
968#
969CONFIG_RTC_INTF_SYSFS=y
970CONFIG_RTC_INTF_PROC=y
971CONFIG_RTC_INTF_DEV=y
972# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
973# CONFIG_RTC_DRV_TEST is not set
974
975#
976# I2C RTC drivers
977#
978# CONFIG_RTC_DRV_DS1307 is not set
979# CONFIG_RTC_DRV_DS1672 is not set
980# CONFIG_RTC_DRV_MAX6900 is not set
981# CONFIG_RTC_DRV_RS5C372 is not set
982# CONFIG_RTC_DRV_ISL1208 is not set
983# CONFIG_RTC_DRV_X1205 is not set
984# CONFIG_RTC_DRV_PCF8563 is not set
985# CONFIG_RTC_DRV_PCF8583 is not set
986
987#
988# SPI RTC drivers
989#
990# CONFIG_RTC_DRV_RS5C348 is not set
991# CONFIG_RTC_DRV_MAX6902 is not set
992
993#
994# Platform RTC drivers
995#
996# CONFIG_RTC_DRV_DS1553 is not set
997# CONFIG_RTC_DRV_DS1742 is not set
998# CONFIG_RTC_DRV_M48T86 is not set
999# CONFIG_RTC_DRV_V3020 is not set
1000
1001#
1002# on-CPU RTC drivers
1003#
1004CONFIG_RTC_DRV_BFIN=y
1005
1006#
1007# DMA Engine support
1008#
1009# CONFIG_DMA_ENGINE is not set
1010
1011#
1012# DMA Clients
1013#
1014
1015#
1016# DMA Devices
1017#
1018
1019#
1020# PBX support
1021#
1022# CONFIG_PBX is not set
1023
1024#
1025# File systems
1026#
1027# CONFIG_EXT2_FS is not set
1028# CONFIG_EXT3_FS is not set
1029# CONFIG_EXT4DEV_FS is not set
1030# CONFIG_REISERFS_FS is not set
1031# CONFIG_JFS_FS is not set
1032# CONFIG_FS_POSIX_ACL is not set
1033# CONFIG_XFS_FS is not set
1034# CONFIG_GFS2_FS is not set
1035# CONFIG_OCFS2_FS is not set
1036# CONFIG_MINIX_FS is not set
1037# CONFIG_ROMFS_FS is not set
1038CONFIG_INOTIFY=y
1039CONFIG_INOTIFY_USER=y
1040# CONFIG_QUOTA is not set
1041# CONFIG_DNOTIFY is not set
1042# CONFIG_AUTOFS_FS is not set
1043# CONFIG_AUTOFS4_FS is not set
1044# CONFIG_FUSE_FS is not set
1045
1046#
1047# CD-ROM/DVD Filesystems
1048#
1049# CONFIG_ISO9660_FS is not set
1050# CONFIG_UDF_FS is not set
1051
1052#
1053# DOS/FAT/NT Filesystems
1054#
1055# CONFIG_MSDOS_FS is not set
1056# CONFIG_VFAT_FS is not set
1057# CONFIG_NTFS_FS is not set
1058
1059#
1060# Pseudo filesystems
1061#
1062CONFIG_PROC_FS=y
1063CONFIG_PROC_SYSCTL=y
1064CONFIG_SYSFS=y
1065# CONFIG_TMPFS is not set
1066# CONFIG_HUGETLB_PAGE is not set
1067CONFIG_RAMFS=y
1068# CONFIG_CONFIGFS_FS is not set
1069
1070#
1071# Miscellaneous filesystems
1072#
1073# CONFIG_ADFS_FS is not set
1074# CONFIG_AFFS_FS is not set
1075# CONFIG_HFS_FS is not set
1076# CONFIG_HFSPLUS_FS is not set
1077# CONFIG_BEFS_FS is not set
1078# CONFIG_BFS_FS is not set
1079# CONFIG_EFS_FS is not set
1080CONFIG_YAFFS_FS=m
1081CONFIG_YAFFS_YAFFS1=y
1082# CONFIG_YAFFS_DOES_ECC is not set
1083CONFIG_YAFFS_YAFFS2=y
1084CONFIG_YAFFS_AUTO_YAFFS2=y
1085# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
1086CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10
1087# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
1088# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
1089CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
1090CONFIG_JFFS2_FS=m
1091CONFIG_JFFS2_FS_DEBUG=0
1092CONFIG_JFFS2_FS_WRITEBUFFER=y
1093# CONFIG_JFFS2_SUMMARY is not set
1094# CONFIG_JFFS2_FS_XATTR is not set
1095# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1096CONFIG_JFFS2_ZLIB=y
1097CONFIG_JFFS2_RTIME=y
1098# CONFIG_JFFS2_RUBIN is not set
1099# CONFIG_CRAMFS is not set
1100# CONFIG_VXFS_FS is not set
1101# CONFIG_HPFS_FS is not set
1102# CONFIG_QNX4FS_FS is not set
1103# CONFIG_SYSV_FS is not set
1104# CONFIG_UFS_FS is not set
1105
1106#
1107# Network File Systems
1108#
1109CONFIG_NFS_FS=m
1110CONFIG_NFS_V3=y
1111# CONFIG_NFS_V3_ACL is not set
1112# CONFIG_NFS_V4 is not set
1113# CONFIG_NFS_DIRECTIO is not set
1114# CONFIG_NFSD is not set
1115CONFIG_LOCKD=m
1116CONFIG_LOCKD_V4=y
1117CONFIG_NFS_COMMON=y
1118CONFIG_SUNRPC=m
1119# CONFIG_SUNRPC_BIND34 is not set
1120# CONFIG_RPCSEC_GSS_KRB5 is not set
1121# CONFIG_RPCSEC_GSS_SPKM3 is not set
1122CONFIG_SMB_FS=m
1123# CONFIG_SMB_NLS_DEFAULT is not set
1124# CONFIG_CIFS is not set
1125# CONFIG_NCP_FS is not set
1126# CONFIG_CODA_FS is not set
1127# CONFIG_AFS_FS is not set
1128# CONFIG_9P_FS is not set
1129
1130#
1131# Partition Types
1132#
1133# CONFIG_PARTITION_ADVANCED is not set
1134CONFIG_MSDOS_PARTITION=y
1135
1136#
1137# Native Language Support
1138#
1139CONFIG_NLS=m
1140CONFIG_NLS_DEFAULT="iso8859-1"
1141# CONFIG_NLS_CODEPAGE_437 is not set
1142# CONFIG_NLS_CODEPAGE_737 is not set
1143# CONFIG_NLS_CODEPAGE_775 is not set
1144# CONFIG_NLS_CODEPAGE_850 is not set
1145# CONFIG_NLS_CODEPAGE_852 is not set
1146# CONFIG_NLS_CODEPAGE_855 is not set
1147# CONFIG_NLS_CODEPAGE_857 is not set
1148# CONFIG_NLS_CODEPAGE_860 is not set
1149# CONFIG_NLS_CODEPAGE_861 is not set
1150# CONFIG_NLS_CODEPAGE_862 is not set
1151# CONFIG_NLS_CODEPAGE_863 is not set
1152# CONFIG_NLS_CODEPAGE_864 is not set
1153# CONFIG_NLS_CODEPAGE_865 is not set
1154# CONFIG_NLS_CODEPAGE_866 is not set
1155# CONFIG_NLS_CODEPAGE_869 is not set
1156# CONFIG_NLS_CODEPAGE_936 is not set
1157# CONFIG_NLS_CODEPAGE_950 is not set
1158# CONFIG_NLS_CODEPAGE_932 is not set
1159# CONFIG_NLS_CODEPAGE_949 is not set
1160# CONFIG_NLS_CODEPAGE_874 is not set
1161# CONFIG_NLS_ISO8859_8 is not set
1162# CONFIG_NLS_CODEPAGE_1250 is not set
1163# CONFIG_NLS_CODEPAGE_1251 is not set
1164# CONFIG_NLS_ASCII is not set
1165# CONFIG_NLS_ISO8859_1 is not set
1166# CONFIG_NLS_ISO8859_2 is not set
1167# CONFIG_NLS_ISO8859_3 is not set
1168# CONFIG_NLS_ISO8859_4 is not set
1169# CONFIG_NLS_ISO8859_5 is not set
1170# CONFIG_NLS_ISO8859_6 is not set
1171# CONFIG_NLS_ISO8859_7 is not set
1172# CONFIG_NLS_ISO8859_9 is not set
1173# CONFIG_NLS_ISO8859_13 is not set
1174# CONFIG_NLS_ISO8859_14 is not set
1175# CONFIG_NLS_ISO8859_15 is not set
1176# CONFIG_NLS_KOI8_R is not set
1177# CONFIG_NLS_KOI8_U is not set
1178# CONFIG_NLS_UTF8 is not set
1179
1180#
1181# Distributed Lock Manager
1182#
1183# CONFIG_DLM is not set
1184
1185#
1186# Profiling support
1187#
1188# CONFIG_PROFILING is not set
1189
1190#
1191# Kernel hacking
1192#
1193# CONFIG_PRINTK_TIME is not set
1194CONFIG_ENABLE_MUST_CHECK=y
1195CONFIG_MAGIC_SYSRQ=y
1196# CONFIG_UNUSED_SYMBOLS is not set
1197CONFIG_DEBUG_FS=y
1198# CONFIG_HEADERS_CHECK is not set
1199# CONFIG_DEBUG_KERNEL is not set
1200# CONFIG_DEBUG_BUGVERBOSE is not set
1201CONFIG_DEBUG_MMRS=y
1202CONFIG_DEBUG_HUNT_FOR_ZERO=y
1203CONFIG_DEBUG_BFIN_HWTRACE_ON=y
1204CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
1205# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set
1206# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set
1207CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
1208# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
1209# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
1210CONFIG_EARLY_PRINTK=y
1211CONFIG_CPLB_INFO=y
1212CONFIG_ACCESS_CHECK=y
1213
1214#
1215# Security options
1216#
1217# CONFIG_KEYS is not set
1218CONFIG_SECURITY=y
1219# CONFIG_SECURITY_NETWORK is not set
1220CONFIG_SECURITY_CAPABILITIES=y
1221
1222#
1223# Cryptographic options
1224#
1225# CONFIG_CRYPTO is not set
1226
1227#
1228# Library routines
1229#
1230CONFIG_BITREVERSE=y
1231# CONFIG_CRC_CCITT is not set
1232# CONFIG_CRC16 is not set
1233# CONFIG_CRC_ITU_T is not set
1234CONFIG_CRC32=y
1235# CONFIG_LIBCRC32C is not set
1236CONFIG_ZLIB_INFLATE=y
1237CONFIG_ZLIB_DEFLATE=m
1238CONFIG_PLIST=y
1239CONFIG_HAS_IOMEM=y
1240CONFIG_HAS_IOPORT=y
1241CONFIG_HAS_DMA=y
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index 3fe0cd49e8db..ce85d4bf34ca 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -124,7 +124,7 @@ static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
124}; 124};
125#endif 125#endif
126 126
127#ifdef BF537_FAMILY 127#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
128static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = { 128static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
129 (struct gpio_port_t *) PORTFIO, 129 (struct gpio_port_t *) PORTFIO,
130 (struct gpio_port_t *) PORTGIO, 130 (struct gpio_port_t *) PORTGIO,
@@ -139,6 +139,21 @@ static unsigned short *port_fer[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
139 139
140#endif 140#endif
141 141
142#ifdef BF527_FAMILY
143static unsigned short *port_mux[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
144 (unsigned short *) PORTF_MUX,
145 (unsigned short *) PORTG_MUX,
146 (unsigned short *) PORTH_MUX,
147};
148
149static const
150u8 pmux_offset[][16] =
151 {{ 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */
152 { 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */
153 { 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */
154 };
155#endif
156
142#ifdef BF561_FAMILY 157#ifdef BF561_FAMILY
143static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = { 158static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
144 (struct gpio_port_t *) FIO0_FLAG_D, 159 (struct gpio_port_t *) FIO0_FLAG_D,
@@ -186,6 +201,10 @@ static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB
186static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX}; 201static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX};
187#endif 202#endif
188 203
204#ifdef BF527_FAMILY
205static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB};
206#endif
207
189#ifdef BF561_FAMILY 208#ifdef BF561_FAMILY
190static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB}; 209static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB};
191#endif 210#endif
@@ -238,7 +257,7 @@ static int cmp_label(unsigned short ident, const char *label)
238 return -EINVAL; 257 return -EINVAL;
239} 258}
240 259
241#ifdef BF537_FAMILY 260#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
242static void port_setup(unsigned short gpio, unsigned short usage) 261static void port_setup(unsigned short gpio, unsigned short usage)
243{ 262{
244 if (!check_gpio(gpio)) { 263 if (!check_gpio(gpio)) {
@@ -354,6 +373,18 @@ inline u16 get_portmux(unsigned short portno)
354 373
355 return (pmux >> (2 * gpio_sub_n(portno)) & 0x3); 374 return (pmux >> (2 * gpio_sub_n(portno)) & 0x3);
356} 375}
376#elif defined(BF527_FAMILY)
377inline void portmux_setup(unsigned short portno, unsigned short function)
378{
379 u16 pmux, ident = P_IDENT(portno);
380 u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
381
382 pmux = *port_mux[gpio_bank(ident)];
383 pmux &= ~(3 << offset);
384 pmux |= (function & 3) << offset;
385 *port_mux[gpio_bank(ident)] = pmux;
386 SSYNC();
387}
357#else 388#else
358# define portmux_setup(...) do { } while (0) 389# define portmux_setup(...) do { } while (0)
359#endif 390#endif
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
index 356078ec462b..ae28aac6fec1 100644
--- a/arch/blackfin/kernel/reboot.c
+++ b/arch/blackfin/kernel/reboot.c
@@ -11,7 +11,7 @@
11#include <asm/reboot.h> 11#include <asm/reboot.h>
12#include <asm/system.h> 12#include <asm/system.h>
13 13
14#if defined(BF537_FAMILY) || defined(BF533_FAMILY) 14#if defined(BF537_FAMILY) || defined(BF533_FAMILY) || defined(BF527_FAMILY)
15#define SYSCR_VAL 0x0 15#define SYSCR_VAL 0x0
16#elif defined(BF561_FAMILY) 16#elif defined(BF561_FAMILY)
17#define SYSCR_VAL 0x20 17#define SYSCR_VAL 0x20
diff --git a/arch/blackfin/mach-bf527/Kconfig b/arch/blackfin/mach-bf527/Kconfig
new file mode 100644
index 000000000000..50321f723dee
--- /dev/null
+++ b/arch/blackfin/mach-bf527/Kconfig
@@ -0,0 +1,251 @@
1if (BF52x)
2
3menu "BF527 Specific Configuration"
4
5comment "Alternative Multiplexing Scheme"
6
7choice
8 prompt "SPORT0"
9 default BF527_SPORT0_PORTG
10 help
11 Select PORT used for SPORT0. See Hardware Reference Manual
12
13config BF527_SPORT0_PORTF
14 bool "PORT F"
15 help
16 PORT F
17
18config BF527_SPORT0_PORTG
19 bool "PORT G"
20 help
21 PORT G
22endchoice
23
24choice
25 prompt "SPORT0 TSCLK Location"
26 depends on BF527_SPORT0_PORTG
27 default BF527_SPORT0_TSCLK_PG10
28 help
29 Select PIN used for SPORT0_TSCLK. See Hardware Reference Manual
30
31config BF527_SPORT0_TSCLK_PG10
32 bool "PORT PG10"
33 help
34 PORT PG10
35
36config BF527_SPORT0_TSCLK_PG14
37 bool "PORT PG14"
38 help
39 PORT PG14
40endchoice
41
42choice
43 prompt "UART1"
44 default BF527_UART1_PORTG
45 help
46 Select PORT used for UART1. See Hardware Reference Manual
47
48config BF527_UART1_PORTF
49 bool "PORT F"
50 help
51 PORT F
52
53config BF527_UART1_PORTG
54 bool "PORT G"
55 help
56 PORT G
57endchoice
58
59choice
60 prompt "NAND (NFC) Data"
61 default BF527_NAND_D_PORTH
62 help
63 Select PORT used for NAND Data Bus. See Hardware Reference Manual
64
65config BF527_NAND_D_PORTF
66 bool "PORT F"
67 help
68 PORT F
69
70config BF527_NAND_D_PORTH
71 bool "PORT H"
72 help
73 PORT H
74endchoice
75
76comment "Interrupt Priority Assignment"
77menu "Priority"
78
79config IRQ_PLL_WAKEUP
80 int "IRQ_PLL_WAKEUP"
81 default 7
82config IRQ_DMA0_ERROR
83 int "IRQ_DMA0_ERROR"
84 default 7
85config IRQ_DMAR0_BLK
86 int "IRQ_DMAR0_BLK"
87 default 7
88config IRQ_DMAR1_BLK
89 int "IRQ_DMAR1_BLK"
90 default 7
91config IRQ_DMAR0_OVR
92 int "IRQ_DMAR0_OVR"
93 default 7
94config IRQ_DMAR1_OVR
95 int "IRQ_DMAR1_OVR"
96 default 7
97config IRQ_PPI_ERROR
98 int "IRQ_PPI_ERROR"
99 default 7
100config IRQ_MAC_ERROR
101 int "IRQ_MAC_ERROR"
102 default 7
103config IRQ_SPORT0_ERROR
104 int "IRQ_SPORT0_ERROR"
105 default 7
106config IRQ_SPORT1_ERROR
107 int "IRQ_SPORT1_ERROR"
108 default 7
109config IRQ_UART0_ERROR
110 int "IRQ_UART0_ERROR"
111 default 7
112config IRQ_UART1_ERROR
113 int "IRQ_UART1_ERROR"
114 default 7
115config IRQ_RTC
116 int "IRQ_RTC"
117 default 8
118config IRQ_PPI
119 int "IRQ_PPI"
120 default 8
121config IRQ_SPORT0_RX
122 int "IRQ_SPORT0_RX"
123 default 9
124config IRQ_SPORT0_TX
125 int "IRQ_SPORT0_TX"
126 default 9
127config IRQ_SPORT1_RX
128 int "IRQ_SPORT1_RX"
129 default 9
130config IRQ_SPORT1_TX
131 int "IRQ_SPORT1_TX"
132 default 9
133config IRQ_TWI
134 int "IRQ_TWI"
135 default 10
136config IRQ_SPI
137 int "IRQ_SPI"
138 default 10
139config IRQ_UART0_RX
140 int "IRQ_UART0_RX"
141 default 10
142config IRQ_UART0_TX
143 int "IRQ_UART0_TX"
144 default 10
145config IRQ_UART1_RX
146 int "IRQ_UART1_RX"
147 default 10
148config IRQ_UART1_TX
149 int "IRQ_UART1_TX"
150 default 10
151config IRQ_OPTSEC
152 int "IRQ_OPTSEC"
153 default 11
154config IRQ_CNT
155 int "IRQ_CNT"
156 default 11
157config IRQ_MAC_RX
158 int "IRQ_MAC_RX"
159 default 11
160config IRQ_PORTH_INTA
161 int "IRQ_PORTH_INTA"
162 default 11
163config IRQ_MAC_TX
164 int "IRQ_MAC_TX/NFC"
165 default 11
166config IRQ_PORTH_INTB
167 int "IRQ_PORTH_INTB"
168 default 11
169config IRQ_TMR0
170 int "IRQ_TMR0"
171 default 12
172config IRQ_TMR1
173 int "IRQ_TMR1"
174 default 12
175config IRQ_TMR2
176 int "IRQ_TMR2"
177 default 12
178config IRQ_TMR3
179 int "IRQ_TMR3"
180 default 12
181config IRQ_TMR4
182 int "IRQ_TMR4"
183 default 12
184config IRQ_TMR5
185 int "IRQ_TMR5"
186 default 12
187config IRQ_TMR6
188 int "IRQ_TMR6"
189 default 12
190config IRQ_TMR7
191 int "IRQ_TMR7"
192 default 12
193config IRQ_PORTG_INTA
194 int "IRQ_PORTG_INTA"
195 default 12
196config IRQ_PORTG_INTB
197 int "IRQ_PORTG_INTB"
198 default 12
199config IRQ_MEM_DMA0
200 int "IRQ_MEM_DMA0"
201 default 13
202config IRQ_MEM_DMA1
203 int "IRQ_MEM_DMA1"
204 default 13
205config IRQ_WATCH
206 int "IRQ_WATCH"
207 default 13
208config IRQ_PORTF_INTA
209 int "IRQ_PORTF_INTA"
210 default 13
211config IRQ_PORTF_INTB
212 int "IRQ_PORTF_INTB"
213 default 13
214config IRQ_SPI_ERROR
215 int "IRQ_SPI_ERROR"
216 default 7
217config IRQ_NFC_ERROR
218 int "IRQ_NFC_ERROR"
219 default 7
220config IRQ_HDMA_ERROR
221 int "IRQ_HDMA_ERROR"
222 default 7
223config IRQ_HDMA
224 int "IRQ_HDMA"
225 default 7
226config IRQ_USB_EINT
227 int "IRQ_USB_EINT"
228 default 10
229config IRQ_USB_INT0
230 int "IRQ_USB_INT0"
231 default 10
232config IRQ_USB_INT1
233 int "IRQ_USB_INT1"
234 default 10
235config IRQ_USB_INT2
236 int "IRQ_USB_INT2"
237 default 10
238config IRQ_USB_DMA
239 int "IRQ_USB_DMA"
240 default 10
241
242 help
243 Enter the priority numbers between 7-13 ONLY. Others are Reserved.
244 This applies to all the above. It is not recommended to assign the
245 highest priority number 7 to UART or any other device.
246
247endmenu
248
249endmenu
250
251endif
diff --git a/arch/blackfin/mach-bf527/Makefile b/arch/blackfin/mach-bf527/Makefile
new file mode 100644
index 000000000000..9f99f5d0bcd1
--- /dev/null
+++ b/arch/blackfin/mach-bf527/Makefile
@@ -0,0 +1,9 @@
1#
2# arch/blackfin/mach-bf527/Makefile
3#
4
5extra-y := head.o
6
7obj-y := ints-priority.o dma.o
8
9obj-$(CONFIG_CPU_FREQ) += cpu.o
diff --git a/arch/blackfin/mach-bf527/boards/Makefile b/arch/blackfin/mach-bf527/boards/Makefile
new file mode 100644
index 000000000000..912ac8ebc889
--- /dev/null
+++ b/arch/blackfin/mach-bf527/boards/Makefile
@@ -0,0 +1,7 @@
1#
2# arch/blackfin/mach-bf532/boards/Makefile
3#
4
5obj-y += eth_mac.o
6obj-$(CONFIG_BFIN527_EZKIT) += ezkit.o
7
diff --git a/arch/blackfin/mach-bf527/boards/eth_mac.c b/arch/blackfin/mach-bf527/boards/eth_mac.c
new file mode 100644
index 000000000000..a725cc8a9290
--- /dev/null
+++ b/arch/blackfin/mach-bf527/boards/eth_mac.c
@@ -0,0 +1,50 @@
1/*
2 * arch/blackfin/mach-bf537/board/eth_mac.c
3 *
4 * Copyright (C) 2007 Analog Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/module.h>
21#include <asm/blackfin.h>
22
23#if defined(CONFIG_GENERIC_BOARD) || defined(CONFIG_BFIN537_STAMP)
24
25/*
26 * Currently the MAC address is saved in Flash by U-Boot
27 */
28#define FLASH_MAC 0x203f0000
29
30void get_bf537_ether_addr(char *addr)
31{
32 unsigned int flash_mac = (unsigned int) FLASH_MAC;
33 *(u32 *)(&(addr[0])) = bfin_read32(flash_mac);
34 flash_mac += 4;
35 *(u16 *)(&(addr[4])) = bfin_read16(flash_mac);
36}
37
38#else
39
40/*
41 * Provide MAC address function for other specific board setting
42 */
43void get_bf537_ether_addr(char *addr)
44{
45 printk(KERN_WARNING "%s: No valid Ethernet MAC address found\n", __FILE__);
46}
47
48#endif
49
50EXPORT_SYMBOL(get_bf537_ether_addr);
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
new file mode 100644
index 000000000000..09fb624af5ac
--- /dev/null
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -0,0 +1,737 @@
1/*
2 * File: arch/blackfin/mach-bf527/boards/ezkit.c
3 * Based on: arch/blackfin/mach-bf537/boards/stamp.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2007 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h>
35#include <linux/spi/spi.h>
36#include <linux/spi/flash.h>
37#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
38#include <linux/usb_isp1362.h>
39#endif
40#include <linux/pata_platform.h>
41#include <linux/irq.h>
42#include <linux/interrupt.h>
43#include <linux/usb_sl811.h>
44#include <asm/dma.h>
45#include <asm/bfin5xx_spi.h>
46#include <asm/reboot.h>
47#include <linux/spi/ad7877.h>
48
49/*
50 * Name the Board for the /proc/cpuinfo
51 */
52char *bfin_board_name = "ADDS-BF527-EZKIT";
53
54/*
55 * Driver needs to know address, irq and flag pin.
56 */
57
58#define ISP1761_BASE 0x203C0000
59#define ISP1761_IRQ IRQ_PF7
60
61#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
62static struct resource bfin_isp1761_resources[] = {
63 [0] = {
64 .name = "isp1761-regs",
65 .start = ISP1761_BASE + 0x00000000,
66 .end = ISP1761_BASE + 0x000fffff,
67 .flags = IORESOURCE_MEM,
68 },
69 [1] = {
70 .start = ISP1761_IRQ,
71 .end = ISP1761_IRQ,
72 .flags = IORESOURCE_IRQ,
73 },
74};
75
76static struct platform_device bfin_isp1761_device = {
77 .name = "isp1761",
78 .id = 0,
79 .num_resources = ARRAY_SIZE(bfin_isp1761_resources),
80 .resource = bfin_isp1761_resources,
81};
82
83static struct platform_device *bfin_isp1761_devices[] = {
84 &bfin_isp1761_device,
85};
86
87int __init bfin_isp1761_init(void)
88{
89 unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices);
90
91 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
92 set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING);
93
94 return platform_add_devices(bfin_isp1761_devices, num_devices);
95}
96
97void __exit bfin_isp1761_exit(void)
98{
99 platform_device_unregister(&bfin_isp1761_device);
100}
101
102arch_initcall(bfin_isp1761_init);
103#endif
104
105#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
106static struct resource bfin_pcmcia_cf_resources[] = {
107 {
108 .start = 0x20310000, /* IO PORT */
109 .end = 0x20312000,
110 .flags = IORESOURCE_MEM,
111 }, {
112 .start = 0x20311000, /* Attribute Memory */
113 .end = 0x20311FFF,
114 .flags = IORESOURCE_MEM,
115 }, {
116 .start = IRQ_PF4,
117 .end = IRQ_PF4,
118 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
119 }, {
120 .start = 6, /* Card Detect PF6 */
121 .end = 6,
122 .flags = IORESOURCE_IRQ,
123 },
124};
125
126static struct platform_device bfin_pcmcia_cf_device = {
127 .name = "bfin_cf_pcmcia",
128 .id = -1,
129 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
130 .resource = bfin_pcmcia_cf_resources,
131};
132#endif
133
134#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
135static struct platform_device rtc_device = {
136 .name = "rtc-bfin",
137 .id = -1,
138};
139#endif
140
141#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
142static struct resource smc91x_resources[] = {
143 {
144 .name = "smc91x-regs",
145 .start = 0x20300300,
146 .end = 0x20300300 + 16,
147 .flags = IORESOURCE_MEM,
148 }, {
149
150 .start = IRQ_PF7,
151 .end = IRQ_PF7,
152 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
153 },
154};
155static struct platform_device smc91x_device = {
156 .name = "smc91x",
157 .id = 0,
158 .num_resources = ARRAY_SIZE(smc91x_resources),
159 .resource = smc91x_resources,
160};
161#endif
162
163#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
164static struct resource dm9000_resources[] = {
165 [0] = {
166 .start = 0x203FB800,
167 .end = 0x203FB800 + 8,
168 .flags = IORESOURCE_MEM,
169 },
170 [1] = {
171 .start = IRQ_PF9,
172 .end = IRQ_PF9,
173 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
174 },
175};
176
177static struct platform_device dm9000_device = {
178 .name = "dm9000",
179 .id = -1,
180 .num_resources = ARRAY_SIZE(dm9000_resources),
181 .resource = dm9000_resources,
182};
183#endif
184
185#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
186static struct resource sl811_hcd_resources[] = {
187 {
188 .start = 0x20340000,
189 .end = 0x20340000,
190 .flags = IORESOURCE_MEM,
191 }, {
192 .start = 0x20340004,
193 .end = 0x20340004,
194 .flags = IORESOURCE_MEM,
195 }, {
196 .start = CONFIG_USB_SL811_BFIN_IRQ,
197 .end = CONFIG_USB_SL811_BFIN_IRQ,
198 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
199 },
200};
201
202#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
203void sl811_port_power(struct device *dev, int is_on)
204{
205 gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
206 gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS);
207
208 if (is_on)
209 gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 1);
210 else
211 gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 0);
212}
213#endif
214
215static struct sl811_platform_data sl811_priv = {
216 .potpg = 10,
217 .power = 250, /* == 500mA */
218#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
219 .port_power = &sl811_port_power,
220#endif
221};
222
223static struct platform_device sl811_hcd_device = {
224 .name = "sl811-hcd",
225 .id = 0,
226 .dev = {
227 .platform_data = &sl811_priv,
228 },
229 .num_resources = ARRAY_SIZE(sl811_hcd_resources),
230 .resource = sl811_hcd_resources,
231};
232#endif
233
234#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
235static struct resource isp1362_hcd_resources[] = {
236 {
237 .start = 0x20360000,
238 .end = 0x20360000,
239 .flags = IORESOURCE_MEM,
240 }, {
241 .start = 0x20360004,
242 .end = 0x20360004,
243 .flags = IORESOURCE_MEM,
244 }, {
245 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
246 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
247 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
248 },
249};
250
251static struct isp1362_platform_data isp1362_priv = {
252 .sel15Kres = 1,
253 .clknotstop = 0,
254 .oc_enable = 0,
255 .int_act_high = 0,
256 .int_edge_triggered = 0,
257 .remote_wakeup_connected = 0,
258 .no_power_switching = 1,
259 .power_switching_mode = 0,
260};
261
262static struct platform_device isp1362_hcd_device = {
263 .name = "isp1362-hcd",
264 .id = 0,
265 .dev = {
266 .platform_data = &isp1362_priv,
267 },
268 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
269 .resource = isp1362_hcd_resources,
270};
271#endif
272
273#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
274static struct platform_device bfin_mac_device = {
275 .name = "bfin_mac",
276};
277#endif
278
279#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
280static struct resource net2272_bfin_resources[] = {
281 {
282 .start = 0x20300000,
283 .end = 0x20300000 + 0x100,
284 .flags = IORESOURCE_MEM,
285 }, {
286 .start = IRQ_PF7,
287 .end = IRQ_PF7,
288 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
289 },
290};
291
292static struct platform_device net2272_bfin_device = {
293 .name = "net2272",
294 .id = -1,
295 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
296 .resource = net2272_bfin_resources,
297};
298#endif
299
300#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
301/* all SPI peripherals info goes here */
302
303#if defined(CONFIG_MTD_M25P80) \
304 || defined(CONFIG_MTD_M25P80_MODULE)
305static struct mtd_partition bfin_spi_flash_partitions[] = {
306 {
307 .name = "bootloader",
308 .size = 0x00020000,
309 .offset = 0,
310 .mask_flags = MTD_CAP_ROM
311 }, {
312 .name = "kernel",
313 .size = 0xe0000,
314 .offset = 0x20000
315 }, {
316 .name = "file system",
317 .size = 0x700000,
318 .offset = 0x00100000,
319 }
320};
321
322static struct flash_platform_data bfin_spi_flash_data = {
323 .name = "m25p80",
324 .parts = bfin_spi_flash_partitions,
325 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
326 .type = "m25p64",
327};
328
329/* SPI flash chip (m25p64) */
330static struct bfin5xx_spi_chip spi_flash_chip_info = {
331 .enable_dma = 0, /* use dma transfer with this chip*/
332 .bits_per_word = 8,
333};
334#endif
335
336#if defined(CONFIG_SPI_ADC_BF533) \
337 || defined(CONFIG_SPI_ADC_BF533_MODULE)
338/* SPI ADC chip */
339static struct bfin5xx_spi_chip spi_adc_chip_info = {
340 .enable_dma = 1, /* use dma transfer with this chip*/
341 .bits_per_word = 16,
342};
343#endif
344
345#if defined(CONFIG_SND_BLACKFIN_AD1836) \
346 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
347static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
348 .enable_dma = 0,
349 .bits_per_word = 16,
350};
351#endif
352
353#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
354static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
355 .enable_dma = 0,
356 .bits_per_word = 16,
357};
358#endif
359
360#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
361static struct bfin5xx_spi_chip spi_mmc_chip_info = {
362 .enable_dma = 1,
363 .bits_per_word = 8,
364};
365#endif
366
367#if defined(CONFIG_PBX)
368static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
369 .ctl_reg = 0x4, /* send zero */
370 .enable_dma = 0,
371 .bits_per_word = 8,
372 .cs_change_per_word = 1,
373};
374#endif
375
376#if defined(CONFIG_AD5304) || defined(CONFIG_AD5304_MODULE)
377static struct bfin5xx_spi_chip ad5304_chip_info = {
378 .enable_dma = 0,
379 .bits_per_word = 16,
380};
381#endif
382
383#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
384static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
385 .enable_dma = 0,
386 .bits_per_word = 16,
387};
388
389static const struct ad7877_platform_data bfin_ad7877_ts_info = {
390 .model = 7877,
391 .vref_delay_usecs = 50, /* internal, no capacitor */
392 .x_plate_ohms = 419,
393 .y_plate_ohms = 486,
394 .pressure_max = 1000,
395 .pressure_min = 0,
396 .stopacq_polarity = 1,
397 .first_conversion_delay = 3,
398 .acquisition_time = 1,
399 .averaging = 1,
400 .pen_down_acc_interval = 1,
401};
402#endif
403
404static struct spi_board_info bfin_spi_board_info[] __initdata = {
405#if defined(CONFIG_MTD_M25P80) \
406 || defined(CONFIG_MTD_M25P80_MODULE)
407 {
408 /* the modalias must be the same as spi device driver name */
409 .modalias = "m25p80", /* Name of spi_driver for this device */
410 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
411 .bus_num = 0, /* Framework bus number */
412 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
413 .platform_data = &bfin_spi_flash_data,
414 .controller_data = &spi_flash_chip_info,
415 .mode = SPI_MODE_3,
416 },
417#endif
418
419#if defined(CONFIG_SPI_ADC_BF533) \
420 || defined(CONFIG_SPI_ADC_BF533_MODULE)
421 {
422 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
423 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
424 .bus_num = 0, /* Framework bus number */
425 .chip_select = 1, /* Framework chip select. */
426 .platform_data = NULL, /* No spi_driver specific config */
427 .controller_data = &spi_adc_chip_info,
428 },
429#endif
430
431#if defined(CONFIG_SND_BLACKFIN_AD1836) \
432 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
433 {
434 .modalias = "ad1836-spi",
435 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
436 .bus_num = 0,
437 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
438 .controller_data = &ad1836_spi_chip_info,
439 },
440#endif
441#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
442 {
443 .modalias = "ad9960-spi",
444 .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */
445 .bus_num = 0,
446 .chip_select = 1,
447 .controller_data = &ad9960_spi_chip_info,
448 },
449#endif
450#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
451 {
452 .modalias = "spi_mmc_dummy",
453 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
454 .bus_num = 0,
455 .chip_select = 0,
456 .platform_data = NULL,
457 .controller_data = &spi_mmc_chip_info,
458 .mode = SPI_MODE_3,
459 },
460 {
461 .modalias = "spi_mmc",
462 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
463 .bus_num = 0,
464 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
465 .platform_data = NULL,
466 .controller_data = &spi_mmc_chip_info,
467 .mode = SPI_MODE_3,
468 },
469#endif
470#if defined(CONFIG_PBX)
471 {
472 .modalias = "fxs-spi",
473 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
474 .bus_num = 0,
475 .chip_select = 8 - CONFIG_J11_JUMPER,
476 .controller_data = &spi_si3xxx_chip_info,
477 .mode = SPI_MODE_3,
478 },
479 {
480 .modalias = "fxo-spi",
481 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
482 .bus_num = 0,
483 .chip_select = 8 - CONFIG_J19_JUMPER,
484 .controller_data = &spi_si3xxx_chip_info,
485 .mode = SPI_MODE_3,
486 },
487#endif
488#if defined(CONFIG_AD5304) || defined(CONFIG_AD5304_MODULE)
489 {
490 .modalias = "ad5304_spi",
491 .max_speed_hz = 1250000, /* max spi clock (SCK) speed in HZ */
492 .bus_num = 0,
493 .chip_select = 2,
494 .platform_data = NULL,
495 .controller_data = &ad5304_chip_info,
496 .mode = SPI_MODE_2,
497 },
498#endif
499#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
500 {
501 .modalias = "ad7877",
502 .platform_data = &bfin_ad7877_ts_info,
503 .irq = IRQ_PF6,
504 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
505 .bus_num = 1,
506 .chip_select = 1,
507 .controller_data = &spi_ad7877_chip_info,
508 },
509#endif
510};
511
512/* SPI controller data */
513static struct bfin5xx_spi_master bfin_spi0_info = {
514 .num_chipselect = 8,
515 .enable_dma = 1, /* master has the ability to do dma transfer */
516};
517
518/* SPI (0) */
519static struct resource bfin_spi0_resource[] = {
520 [0] = {
521 .start = SPI0_REGBASE,
522 .end = SPI0_REGBASE + 0xFF,
523 .flags = IORESOURCE_MEM,
524 },
525 [1] = {
526 .start = CH_SPI,
527 .end = CH_SPI,
528 .flags = IORESOURCE_IRQ,
529 },
530};
531
532static struct platform_device bfin_spi0_device = {
533 .name = "bfin-spi",
534 .id = 0, /* Bus number */
535 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
536 .resource = bfin_spi0_resource,
537 .dev = {
538 .platform_data = &bfin_spi0_info, /* Passed to driver */
539 },
540};
541#endif /* spi master and devices */
542
543#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
544static struct platform_device bfin_fb_device = {
545 .name = "bf537-lq035",
546};
547#endif
548
549#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
550static struct platform_device bfin_fb_adv7393_device = {
551 .name = "bfin-adv7393",
552};
553#endif
554
555#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
556static struct resource bfin_uart_resources[] = {
557#ifdef CONFIG_SERIAL_BFIN_UART0
558 {
559 .start = 0xFFC00400,
560 .end = 0xFFC004FF,
561 .flags = IORESOURCE_MEM,
562 },
563#endif
564#ifdef CONFIG_SERIAL_BFIN_UART1
565 {
566 .start = 0xFFC02000,
567 .end = 0xFFC020FF,
568 .flags = IORESOURCE_MEM,
569 },
570#endif
571};
572
573static struct platform_device bfin_uart_device = {
574 .name = "bfin-uart",
575 .id = 1,
576 .num_resources = ARRAY_SIZE(bfin_uart_resources),
577 .resource = bfin_uart_resources,
578};
579#endif
580
581#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
582static struct resource bfin_twi0_resource[] = {
583 [0] = {
584 .start = TWI0_REGBASE,
585 .end = TWI0_REGBASE,
586 .flags = IORESOURCE_MEM,
587 },
588 [1] = {
589 .start = IRQ_TWI,
590 .end = IRQ_TWI,
591 .flags = IORESOURCE_IRQ,
592 },
593};
594
595static struct platform_device i2c_bfin_twi_device = {
596 .name = "i2c-bfin-twi",
597 .id = 0,
598 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
599 .resource = bfin_twi0_resource,
600};
601#endif
602
603#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
604static struct platform_device bfin_sport0_uart_device = {
605 .name = "bfin-sport-uart",
606 .id = 0,
607};
608
609static struct platform_device bfin_sport1_uart_device = {
610 .name = "bfin-sport-uart",
611 .id = 1,
612};
613#endif
614
615#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
616#define PATA_INT 55
617
618static struct pata_platform_info bfin_pata_platform_data = {
619 .ioport_shift = 1,
620 .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
621};
622
623static struct resource bfin_pata_resources[] = {
624 {
625 .start = 0x20314020,
626 .end = 0x2031403F,
627 .flags = IORESOURCE_MEM,
628 },
629 {
630 .start = 0x2031401C,
631 .end = 0x2031401F,
632 .flags = IORESOURCE_MEM,
633 },
634 {
635 .start = PATA_INT,
636 .end = PATA_INT,
637 .flags = IORESOURCE_IRQ,
638 },
639};
640
641static struct platform_device bfin_pata_device = {
642 .name = "pata_platform",
643 .id = -1,
644 .num_resources = ARRAY_SIZE(bfin_pata_resources),
645 .resource = bfin_pata_resources,
646 .dev = {
647 .platform_data = &bfin_pata_platform_data,
648 }
649};
650#endif
651
652static struct platform_device *stamp_devices[] __initdata = {
653#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
654 &bfin_pcmcia_cf_device,
655#endif
656
657#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
658 &rtc_device,
659#endif
660
661#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
662 &sl811_hcd_device,
663#endif
664
665#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
666 &isp1362_hcd_device,
667#endif
668
669#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
670 &smc91x_device,
671#endif
672
673#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
674 &dm9000_device,
675#endif
676
677#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
678 &bfin_mac_device,
679#endif
680
681#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
682 &net2272_bfin_device,
683#endif
684
685#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
686 &bfin_spi0_device,
687#endif
688
689#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
690 &bfin_fb_device,
691#endif
692
693#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
694 &bfin_fb_adv7393_device,
695#endif
696
697#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
698 &bfin_uart_device,
699#endif
700
701#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
702 &i2c_bfin_twi_device,
703#endif
704
705#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
706 &bfin_sport0_uart_device,
707 &bfin_sport1_uart_device,
708#endif
709
710#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
711 &bfin_pata_device,
712#endif
713};
714
715static int __init stamp_init(void)
716{
717 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
718 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
719#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
720 spi_register_board_info(bfin_spi_board_info,
721 ARRAY_SIZE(bfin_spi_board_info));
722#endif
723
724#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
725 irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
726#endif
727 return 0;
728}
729
730arch_initcall(stamp_init);
731
732void native_machine_restart(char *cmd)
733{
734 /* workaround reboot hang when booting from SPI */
735 if ((bfin_read_SYSCR() & 0x7) == 0x3)
736 bfin_gpio_reset_spi0_ssel1();
737}
diff --git a/arch/blackfin/mach-bf527/cpu.c b/arch/blackfin/mach-bf527/cpu.c
new file mode 100644
index 000000000000..1975402b1dbc
--- /dev/null
+++ b/arch/blackfin/mach-bf527/cpu.c
@@ -0,0 +1,161 @@
1/*
2 * File: arch/blackfin/mach-bf527/cpu.c
3 * Based on: arch/blackfin/mach-bf537/cpu.c
4 * Author: michael.kang@analog.com
5 *
6 * Created:
7 * Description: clock scaling for the bf527
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/kernel.h>
31#include <linux/types.h>
32#include <linux/init.h>
33#include <linux/cpufreq.h>
34#include <asm/dpmc.h>
35#include <linux/fs.h>
36#include <asm/bfin-global.h>
37
38/* CONFIG_CLKIN_HZ=11059200 */
39#define VCO5 (CONFIG_CLKIN_HZ*45) /*497664000 */
40#define VCO4 (CONFIG_CLKIN_HZ*36) /*398131200 */
41#define VCO3 (CONFIG_CLKIN_HZ*27) /*298598400 */
42#define VCO2 (CONFIG_CLKIN_HZ*18) /*199065600 */
43#define VCO1 (CONFIG_CLKIN_HZ*9) /*99532800 */
44#define VCO(x) VCO##x
45
46#define MFREQ(x) {VCO(x), VCO(x)/4}, {VCO(x), VCO(x)/2}, {VCO(x), VCO(x)}
47/* frequency */
48static struct cpufreq_frequency_table bf527_freq_table[] = {
49 MFREQ(1),
50 MFREQ(3),
51 {VCO4, VCO4 / 2}, {VCO4, VCO4},
52 MFREQ(5),
53 {0, CPUFREQ_TABLE_END},
54};
55
56/*
57 * dpmc_fops->ioctl()
58 * static int dpmc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
59 */
60static int bf527_getfreq(unsigned int cpu)
61{
62 unsigned long cclk_mhz;
63
64 /* The driver only support single cpu */
65 if (cpu == 0)
66 dpmc_fops.ioctl(NULL, NULL, IOCTL_GET_CORECLOCK, &cclk_mhz);
67 else
68 cclk_mhz = -1;
69
70 return cclk_mhz;
71}
72
73static int bf527_target(struct cpufreq_policy *policy,
74 unsigned int target_freq, unsigned int relation)
75{
76 unsigned long cclk_mhz;
77 unsigned long vco_mhz;
78 unsigned long flags;
79 unsigned int index;
80 struct cpufreq_freqs freqs;
81
82 if (cpufreq_frequency_table_target
83 (policy, bf527_freq_table, target_freq, relation, &index))
84 return -EINVAL;
85
86 cclk_mhz = bf527_freq_table[index].frequency;
87 vco_mhz = bf527_freq_table[index].index;
88
89 dpmc_fops.ioctl(NULL, NULL, IOCTL_CHANGE_FREQUENCY, &vco_mhz);
90 freqs.old = bf527_getfreq(0);
91 freqs.new = cclk_mhz;
92 freqs.cpu = 0;
93
94 pr_debug
95 ("cclk begin change to cclk %d,vco=%d,index=%d,target=%d,oldfreq=%d\n",
96 cclk_mhz, vco_mhz, index, target_freq, freqs.old);
97
98 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
99 local_irq_save(flags);
100 dpmc_fops.ioctl(NULL, NULL, IOCTL_SET_CCLK, &cclk_mhz);
101 local_irq_restore(flags);
102 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
103
104 vco_mhz = get_vco();
105 cclk_mhz = get_cclk();
106 return 0;
107}
108
109/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on
110 * this platform, anyway.
111 */
112static int bf527_verify_speed(struct cpufreq_policy *policy)
113{
114 return cpufreq_frequency_table_verify(policy, &bf527_freq_table);
115}
116
117static int __init __bf527_cpu_init(struct cpufreq_policy *policy)
118{
119 if (policy->cpu != 0)
120 return -EINVAL;
121
122 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
123
124 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
125 /*Now ,only support one cpu */
126 policy->cur = bf527_getfreq(0);
127 cpufreq_frequency_table_get_attr(bf527_freq_table, policy->cpu);
128 return cpufreq_frequency_table_cpuinfo(policy, bf527_freq_table);
129}
130
131static struct freq_attr *bf527_freq_attr[] = {
132 &cpufreq_freq_attr_scaling_available_freqs,
133 NULL,
134};
135
136static struct cpufreq_driver bf527_driver = {
137 .verify = bf527_verify_speed,
138 .target = bf527_target,
139 .get = bf527_getfreq,
140 .init = __bf527_cpu_init,
141 .name = "bf527",
142 .owner = THIS_MODULE,
143 .attr = bf527_freq_attr,
144};
145
146static int __init bf527_cpu_init(void)
147{
148 return cpufreq_register_driver(&bf527_driver);
149}
150
151static void __exit bf527_cpu_exit(void)
152{
153 cpufreq_unregister_driver(&bf527_driver);
154}
155
156MODULE_AUTHOR("Mickael Kang");
157MODULE_DESCRIPTION("cpufreq driver for bf527 CPU");
158MODULE_LICENSE("GPL");
159
160module_init(bf527_cpu_init);
161module_exit(bf527_cpu_exit);
diff --git a/arch/blackfin/mach-bf527/dma.c b/arch/blackfin/mach-bf527/dma.c
new file mode 100644
index 000000000000..522de24cc394
--- /dev/null
+++ b/arch/blackfin/mach-bf527/dma.c
@@ -0,0 +1,115 @@
1/*
2 * File: arch/blackfin/mach-bf527/dma.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: This file contains the simple DMA Implementation for Blackfin
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29#include <asm/blackfin.h>
30#include <asm/dma.h>
31
32struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
33 (struct dma_register *) DMA0_NEXT_DESC_PTR,
34 (struct dma_register *) DMA1_NEXT_DESC_PTR,
35 (struct dma_register *) DMA2_NEXT_DESC_PTR,
36 (struct dma_register *) DMA3_NEXT_DESC_PTR,
37 (struct dma_register *) DMA4_NEXT_DESC_PTR,
38 (struct dma_register *) DMA5_NEXT_DESC_PTR,
39 (struct dma_register *) DMA6_NEXT_DESC_PTR,
40 (struct dma_register *) DMA7_NEXT_DESC_PTR,
41 (struct dma_register *) DMA8_NEXT_DESC_PTR,
42 (struct dma_register *) DMA9_NEXT_DESC_PTR,
43 (struct dma_register *) DMA10_NEXT_DESC_PTR,
44 (struct dma_register *) DMA11_NEXT_DESC_PTR,
45 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
46 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
47 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
48 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
49};
50
51int channel2irq(unsigned int channel)
52{
53 int ret_irq = -1;
54
55 switch (channel) {
56 case CH_PPI:
57 ret_irq = IRQ_PPI;
58 break;
59
60 case CH_EMAC_RX:
61 ret_irq = IRQ_MAC_RX;
62 break;
63
64 case CH_EMAC_TX:
65 ret_irq = IRQ_MAC_TX;
66 break;
67
68 case CH_UART1_RX:
69 ret_irq = IRQ_UART1_RX;
70 break;
71
72 case CH_UART1_TX:
73 ret_irq = IRQ_UART1_TX;
74 break;
75
76 case CH_SPORT0_RX:
77 ret_irq = IRQ_SPORT0_RX;
78 break;
79
80 case CH_SPORT0_TX:
81 ret_irq = IRQ_SPORT0_TX;
82 break;
83
84 case CH_SPORT1_RX:
85 ret_irq = IRQ_SPORT1_RX;
86 break;
87
88 case CH_SPORT1_TX:
89 ret_irq = IRQ_SPORT1_TX;
90 break;
91
92 case CH_SPI:
93 ret_irq = IRQ_SPI;
94 break;
95
96 case CH_UART0_RX:
97 ret_irq = IRQ_UART0_RX;
98 break;
99
100 case CH_UART0_TX:
101 ret_irq = IRQ_UART0_TX;
102 break;
103
104 case CH_MEM_STREAM0_SRC:
105 case CH_MEM_STREAM0_DEST:
106 ret_irq = IRQ_MEM_DMA0;
107 break;
108
109 case CH_MEM_STREAM1_SRC:
110 case CH_MEM_STREAM1_DEST:
111 ret_irq = IRQ_MEM_DMA1;
112 break;
113 }
114 return ret_irq;
115}
diff --git a/arch/blackfin/mach-bf527/head.S b/arch/blackfin/mach-bf527/head.S
new file mode 100644
index 000000000000..cdb00a084965
--- /dev/null
+++ b/arch/blackfin/mach-bf527/head.S
@@ -0,0 +1,456 @@
1/*
2 * File: arch/blackfin/mach-bf527/head.S
3 * Based on: arch/blackfin/mach-bf533/head.S
4 * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
5 *
6 * Created: 1998
7 * Description: Startup code for Blackfin BF537
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/linkage.h>
31#include <linux/init.h>
32#include <asm/blackfin.h>
33#include <asm/trace.h>
34
35#if CONFIG_BFIN_KERNEL_CLOCK
36#include <asm/mach-common/clocks.h>
37#include <asm/mach/mem_init.h>
38#endif
39
40.global __rambase
41.global __ramstart
42.global __ramend
43.extern ___bss_stop
44.extern ___bss_start
45.extern _bf53x_relocate_l1_mem
46
47#define INITIAL_STACK 0xFFB01000
48
49__INIT
50
51ENTRY(__start)
52 /* R0: argument of command line string, passed from uboot, save it */
53 R7 = R0;
54 /* Enable Cycle Counter and Nesting Of Interrupts */
55#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
56 R0 = SYSCFG_SNEN;
57#else
58 R0 = SYSCFG_SNEN | SYSCFG_CCEN;
59#endif
60 SYSCFG = R0;
61 R0 = 0;
62
63 /* Clear Out All the data and pointer Registers */
64 R1 = R0;
65 R2 = R0;
66 R3 = R0;
67 R4 = R0;
68 R5 = R0;
69 R6 = R0;
70
71 P0 = R0;
72 P1 = R0;
73 P2 = R0;
74 P3 = R0;
75 P4 = R0;
76 P5 = R0;
77
78 LC0 = r0;
79 LC1 = r0;
80 L0 = r0;
81 L1 = r0;
82 L2 = r0;
83 L3 = r0;
84
85 /* Clear Out All the DAG Registers */
86 B0 = r0;
87 B1 = r0;
88 B2 = r0;
89 B3 = r0;
90
91 I0 = r0;
92 I1 = r0;
93 I2 = r0;
94 I3 = r0;
95
96 M0 = r0;
97 M1 = r0;
98 M2 = r0;
99 M3 = r0;
100
101 trace_buffer_init(p0,r0);
102 P0 = R1;
103 R0 = R1;
104
105 /* Turn off the icache */
106 p0.l = LO(IMEM_CONTROL);
107 p0.h = HI(IMEM_CONTROL);
108 R1 = [p0];
109 R0 = ~ENICPLB;
110 R0 = R0 & R1;
111
112 /* Anomaly 05000125 */
113#if ANOMALY_05000125
114 CLI R2;
115 SSYNC;
116#endif
117 [p0] = R0;
118 SSYNC;
119#if ANOMALY_05000125
120 STI R2;
121#endif
122
123 /* Turn off the dcache */
124 p0.l = LO(DMEM_CONTROL);
125 p0.h = HI(DMEM_CONTROL);
126 R1 = [p0];
127 R0 = ~ENDCPLB;
128 R0 = R0 & R1;
129
130 /* Anomaly 05000125 */
131#if ANOMALY_05000125
132 CLI R2;
133 SSYNC;
134#endif
135 [p0] = R0;
136 SSYNC;
137#if ANOMALY_05000125
138 STI R2;
139#endif
140
141
142#if defined(CONFIG_BF527)
143 p0.h = hi(EMAC_SYSTAT);
144 p0.l = lo(EMAC_SYSTAT);
145 R0.h = 0xFFFF; /* Clear EMAC Interrupt Status bits */
146 R0.l = 0xFFFF;
147 [P0] = R0;
148 SSYNC;
149#endif
150
151 /* Initialise UART - when booting from u-boot, the UART is not disabled
152 * so if we dont initalize here, our serial console gets hosed */
153 p0.h = hi(UART1_LCR);
154 p0.l = lo(UART1_LCR);
155 r0 = 0x0(Z);
156 w[p0] = r0.L; /* To enable DLL writes */
157 ssync;
158
159 p0.h = hi(UART1_DLL);
160 p0.l = lo(UART1_DLL);
161 r0 = 0x0(Z);
162 w[p0] = r0.L;
163 ssync;
164
165 p0.h = hi(UART1_DLH);
166 p0.l = lo(UART1_DLH);
167 r0 = 0x00(Z);
168 w[p0] = r0.L;
169 ssync;
170
171 p0.h = hi(UART1_GCTL);
172 p0.l = lo(UART1_GCTL);
173 r0 = 0x0(Z);
174 w[p0] = r0.L; /* To enable UART clock */
175 ssync;
176
177 /* Initialize stack pointer */
178 sp.l = lo(INITIAL_STACK);
179 sp.h = hi(INITIAL_STACK);
180 fp = sp;
181 usp = sp;
182
183#ifdef CONFIG_EARLY_PRINTK
184 SP += -12;
185 call _init_early_exception_vectors;
186 SP += 12;
187#endif
188
189 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
190 call _bf53x_relocate_l1_mem;
191#if CONFIG_BFIN_KERNEL_CLOCK
192 call _start_dma_code;
193#endif
194
195 /* Code for initializing Async memory banks */
196
197 p2.h = hi(EBIU_AMBCTL1);
198 p2.l = lo(EBIU_AMBCTL1);
199 r0.h = hi(AMBCTL1VAL);
200 r0.l = lo(AMBCTL1VAL);
201 [p2] = r0;
202 ssync;
203
204 p2.h = hi(EBIU_AMBCTL0);
205 p2.l = lo(EBIU_AMBCTL0);
206 r0.h = hi(AMBCTL0VAL);
207 r0.l = lo(AMBCTL0VAL);
208 [p2] = r0;
209 ssync;
210
211 p2.h = hi(EBIU_AMGCTL);
212 p2.l = lo(EBIU_AMGCTL);
213 r0 = AMGCTLVAL;
214 w[p2] = r0;
215 ssync;
216
217 /* This section keeps the processor in supervisor mode
218 * during kernel boot. Switches to user mode at end of boot.
219 * See page 3-9 of Hardware Reference manual for documentation.
220 */
221
222 /* EVT15 = _real_start */
223
224 p0.l = lo(EVT15);
225 p0.h = hi(EVT15);
226 p1.l = _real_start;
227 p1.h = _real_start;
228 [p0] = p1;
229 csync;
230
231 p0.l = lo(IMASK);
232 p0.h = hi(IMASK);
233 p1.l = IMASK_IVG15;
234 p1.h = 0x0;
235 [p0] = p1;
236 csync;
237
238 raise 15;
239 p0.l = .LWAIT_HERE;
240 p0.h = .LWAIT_HERE;
241 reti = p0;
242#if ANOMALY_05000281
243 nop; nop; nop;
244#endif
245 rti;
246
247.LWAIT_HERE:
248 jump .LWAIT_HERE;
249ENDPROC(__start)
250
251ENTRY(_real_start)
252 [ -- sp ] = reti;
253 p0.l = lo(WDOG_CTL);
254 p0.h = hi(WDOG_CTL);
255 r0 = 0xAD6(z);
256 w[p0] = r0; /* watchdog off for now */
257 ssync;
258
259 /* Code update for BSS size == 0
260 * Zero out the bss region.
261 */
262
263 p1.l = ___bss_start;
264 p1.h = ___bss_start;
265 p2.l = ___bss_stop;
266 p2.h = ___bss_stop;
267 r0 = 0;
268 p2 -= p1;
269 lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
270.L_clear_bss:
271 B[p1++] = r0;
272
273 /* In case there is a NULL pointer reference
274 * Zero out region before stext
275 */
276
277 p1.l = 0x0;
278 p1.h = 0x0;
279 r0.l = __stext;
280 r0.h = __stext;
281 r0 = r0 >> 1;
282 p2 = r0;
283 r0 = 0;
284 lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
285.L_clear_zero:
286 W[p1++] = r0;
287
288 /* pass the uboot arguments to the global value command line */
289 R0 = R7;
290 call _cmdline_init;
291
292 p1.l = __rambase;
293 p1.h = __rambase;
294 r0.l = __sdata;
295 r0.h = __sdata;
296 [p1] = r0;
297
298 p1.l = __ramstart;
299 p1.h = __ramstart;
300 p3.l = ___bss_stop;
301 p3.h = ___bss_stop;
302
303 r1 = p3;
304 [p1] = r1;
305
306 /*
307 * load the current thread pointer and stack
308 */
309 r1.l = _init_thread_union;
310 r1.h = _init_thread_union;
311
312 r2.l = 0x2000;
313 r2.h = 0x0000;
314 r1 = r1 + r2;
315 sp = r1;
316 usp = sp;
317 fp = sp;
318 jump.l _start_kernel;
319ENDPROC(_real_start)
320
321__FINIT
322
323.section .l1.text
324#if CONFIG_BFIN_KERNEL_CLOCK
325ENTRY(_start_dma_code)
326
327 /* Enable PHY CLK buffer output */
328 p0.h = hi(VR_CTL);
329 p0.l = lo(VR_CTL);
330 r0.l = w[p0];
331 bitset(r0, 14);
332 w[p0] = r0.l;
333 ssync;
334
335 p0.h = hi(SIC_IWR0);
336 p0.l = lo(SIC_IWR0);
337 r0.l = 0x1;
338 r0.h = 0x0;
339 [p0] = r0;
340 SSYNC;
341
342 /*
343 * Set PLL_CTL
344 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
345 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
346 * - [7] = output delay (add 200ps of delay to mem signals)
347 * - [6] = input delay (add 200ps of input delay to mem signals)
348 * - [5] = PDWN : 1=All Clocks off
349 * - [3] = STOPCK : 1=Core Clock off
350 * - [1] = PLL_OFF : 1=Disable Power to PLL
351 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
352 * all other bits set to zero
353 */
354
355 p0.h = hi(PLL_LOCKCNT);
356 p0.l = lo(PLL_LOCKCNT);
357 r0 = 0x300(Z);
358 w[p0] = r0.l;
359 ssync;
360
361 P2.H = hi(EBIU_SDGCTL);
362 P2.L = lo(EBIU_SDGCTL);
363 R0 = [P2];
364 BITSET (R0, 24);
365 [P2] = R0;
366 SSYNC;
367
368 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
369 r0 = r0 << 9; /* Shift it over, */
370 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
371 r0 = r1 | r0;
372 r1 = PLL_BYPASS; /* Bypass the PLL? */
373 r1 = r1 << 8; /* Shift it over */
374 r0 = r1 | r0; /* add them all together */
375
376 p0.h = hi(PLL_CTL);
377 p0.l = lo(PLL_CTL); /* Load the address */
378 cli r2; /* Disable interrupts */
379 ssync;
380 w[p0] = r0.l; /* Set the value */
381 idle; /* Wait for the PLL to stablize */
382 sti r2; /* Enable interrupts */
383
384.Lcheck_again:
385 p0.h = hi(PLL_STAT);
386 p0.l = lo(PLL_STAT);
387 R0 = W[P0](Z);
388 CC = BITTST(R0,5);
389 if ! CC jump .Lcheck_again;
390
391 /* Configure SCLK & CCLK Dividers */
392 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
393 p0.h = hi(PLL_DIV);
394 p0.l = lo(PLL_DIV);
395 w[p0] = r0.l;
396 ssync;
397
398 p0.l = lo(EBIU_SDRRC);
399 p0.h = hi(EBIU_SDRRC);
400 r0 = mem_SDRRC;
401 w[p0] = r0.l;
402 ssync;
403
404 p0.l = LO(EBIU_SDBCTL);
405 p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
406 r0 = mem_SDBCTL;
407 w[p0] = r0.l;
408 ssync;
409
410 P2.H = hi(EBIU_SDGCTL);
411 P2.L = lo(EBIU_SDGCTL);
412 R0 = [P2];
413 BITCLR (R0, 24);
414 p0.h = hi(EBIU_SDSTAT);
415 p0.l = lo(EBIU_SDSTAT);
416 r2.l = w[p0];
417 cc = bittst(r2,3);
418 if !cc jump .Lskip;
419 NOP;
420 BITSET (R0, 23);
421.Lskip:
422 [P2] = R0;
423 SSYNC;
424
425 R0.L = lo(mem_SDGCTL);
426 R0.H = hi(mem_SDGCTL);
427 R1 = [p2];
428 R1 = R1 | R0;
429 [P2] = R1;
430 SSYNC;
431
432 p0.h = hi(SIC_IWR0);
433 p0.l = lo(SIC_IWR0);
434 r0.l = lo(IWR_ENABLE_ALL);
435 r0.h = hi(IWR_ENABLE_ALL);
436 [p0] = r0;
437 SSYNC;
438
439 RTS;
440ENDPROC(_start_dma_code)
441#endif /* CONFIG_BFIN_KERNEL_CLOCK */
442
443.data
444
445/*
446 * Set up the usable of RAM stuff. Size of RAM is determined then
447 * an initial stack set up at the end.
448 */
449
450.align 4
451__rambase:
452.long 0
453__ramstart:
454.long 0
455__ramend:
456.long 0
diff --git a/arch/blackfin/mach-bf527/ints-priority.c b/arch/blackfin/mach-bf527/ints-priority.c
new file mode 100644
index 000000000000..1fa389793968
--- /dev/null
+++ b/arch/blackfin/mach-bf527/ints-priority.c
@@ -0,0 +1,100 @@
1/*
2 * File: arch/blackfin/mach-bf537/ints-priority.c
3 * Based on: arch/blackfin/mach-bf533/ints-priority.c
4 * Author: Michael Hennerich (michael.hennerich@analog.com)
5 *
6 * Created:
7 * Description: Set up the interrupt priorities
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/module.h>
31#include <linux/irq.h>
32#include <asm/blackfin.h>
33
34void program_IAR(void)
35{
36 /* Program the IAR0 Register with the configured priority */
37 bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
38 ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
39 ((CONFIG_IRQ_DMAR0_BLK - 7) << IRQ_DMAR0_BLK_POS) |
40 ((CONFIG_IRQ_DMAR1_BLK - 7) << IRQ_DMAR1_BLK_POS) |
41 ((CONFIG_IRQ_DMAR0_OVR - 7) << IRQ_DMAR0_OVR_POS) |
42 ((CONFIG_IRQ_DMAR1_OVR - 7) << IRQ_DMAR1_OVR_POS) |
43 ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
44 ((CONFIG_IRQ_MAC_ERROR - 7) << IRQ_MAC_ERROR_POS));
45
46
47 bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
48 ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
49 ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
50 ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
51 ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
52 ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS));
53
54 bfin_write_SIC_IAR2(((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
55 ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
56 ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
57 ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
58 ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
59 ((CONFIG_IRQ_SPI - 7) << IRQ_SPI_POS) |
60 ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
61 ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
62
63 bfin_write_SIC_IAR3(((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
64 ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
65 ((CONFIG_IRQ_OPTSEC - 7) << IRQ_OPTSEC_POS) |
66 ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
67 ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
68 ((CONFIG_IRQ_PORTH_INTA - 7) << IRQ_PORTH_INTA_POS) |
69 ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
70 ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS));
71
72 bfin_write_SIC_IAR4(((CONFIG_IRQ_TMR0 - 7) << IRQ_TMR0_POS) |
73 ((CONFIG_IRQ_TMR1 - 7) << IRQ_TMR1_POS) |
74 ((CONFIG_IRQ_TMR2 - 7) << IRQ_TMR2_POS) |
75 ((CONFIG_IRQ_TMR3 - 7) << IRQ_TMR3_POS) |
76 ((CONFIG_IRQ_TMR4 - 7) << IRQ_TMR4_POS) |
77 ((CONFIG_IRQ_TMR5 - 7) << IRQ_TMR5_POS) |
78 ((CONFIG_IRQ_TMR6 - 7) << IRQ_TMR6_POS) |
79 ((CONFIG_IRQ_TMR7 - 7) << IRQ_TMR7_POS));
80
81 bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) |
82 ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
83 ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
84 ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
85 ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS) |
86 ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
87 ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
88 ((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS));
89
90 bfin_write_SIC_IAR6(((CONFIG_IRQ_NFC_ERROR - 7) << IRQ_NFC_ERROR_POS) |
91 ((CONFIG_IRQ_HDMA_ERROR - 7) << IRQ_HDMA_ERROR_POS) |
92 ((CONFIG_IRQ_HDMA - 7) << IRQ_HDMA_POS) |
93 ((CONFIG_IRQ_USB_EINT - 7) << IRQ_USB_EINT_POS) |
94 ((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) |
95 ((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) |
96 ((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) |
97 ((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS));
98
99 SSYNC();
100}
diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c
index d3b7672b2b94..e06fe96b6fc3 100644
--- a/arch/blackfin/mach-common/ints-priority-sc.c
+++ b/arch/blackfin/mach-common/ints-priority-sc.c
@@ -92,10 +92,15 @@ static void __init search_IAR(void)
92 92
93 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) { 93 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
94 int iar_shift = (irqn & 7) * 4; 94 int iar_shift = (irqn & 7) * 4;
95 if (ivg == 95 if (ivg ==
96 (0xf & 96 (0xf &
97#ifndef CONFIG_BF52x
97 bfin_read32((unsigned long *)SIC_IAR0 + 98 bfin_read32((unsigned long *)SIC_IAR0 +
98 (irqn >> 3)) >> iar_shift)) { 99 (irqn >> 3)) >> iar_shift)) {
100#else
101 bfin_read32((unsigned long *)SIC_IAR0 +
102 ((irqn%32) >> 3) + ((irqn / 32) * 16)) >> iar_shift)) {
103#endif
99 ivg_table[irq_pos].irqno = IVG7 + irqn; 104 ivg_table[irq_pos].irqno = IVG7 + irqn;
100 ivg_table[irq_pos].isrflag = 1 << (irqn % 32); 105 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
101 ivg7_13[ivg].istop++; 106 ivg7_13[ivg].istop++;
@@ -140,7 +145,7 @@ static void bfin_core_unmask_irq(unsigned int irq)
140 145
141static void bfin_internal_mask_irq(unsigned int irq) 146static void bfin_internal_mask_irq(unsigned int irq)
142{ 147{
143#ifndef CONFIG_BF54x 148#ifdef CONFIG_BF53x
144 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & 149 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
145 ~(1 << (irq - (IRQ_CORETMR + 1)))); 150 ~(1 << (irq - (IRQ_CORETMR + 1))));
146#else 151#else
@@ -155,7 +160,7 @@ static void bfin_internal_mask_irq(unsigned int irq)
155 160
156static void bfin_internal_unmask_irq(unsigned int irq) 161static void bfin_internal_unmask_irq(unsigned int irq)
157{ 162{
158#ifndef CONFIG_BF54x 163#ifdef CONFIG_BF53x
159 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 164 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
160 (1 << (irq - (IRQ_CORETMR + 1)))); 165 (1 << (irq - (IRQ_CORETMR + 1))));
161#else 166#else
@@ -750,13 +755,15 @@ int __init init_arch_irq(void)
750 int irq; 755 int irq;
751 unsigned long ilat = 0; 756 unsigned long ilat = 0;
752 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ 757 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
753#ifdef CONFIG_BF54x 758#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
754 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); 759 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
755 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); 760 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
756 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
757 bfin_write_SIC_IWR0(IWR_ENABLE_ALL); 761 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
758 bfin_write_SIC_IWR1(IWR_ENABLE_ALL); 762 bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
763#ifdef CONFIG_BF54x
764 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
759 bfin_write_SIC_IWR2(IWR_ENABLE_ALL); 765 bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
766#endif
760#else 767#else
761 bfin_write_SIC_IMASK(SIC_UNMASK_ALL); 768 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
762 bfin_write_SIC_IWR(IWR_ENABLE_ALL); 769 bfin_write_SIC_IWR(IWR_ENABLE_ALL);
@@ -787,7 +794,7 @@ int __init init_arch_irq(void)
787 794
788 switch (irq) { 795 switch (irq) {
789#ifdef CONFIG_IRQCHIP_DEMUX_GPIO 796#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
790#ifndef CONFIG_BF54x 797#if defined(CONFIG_BF53x)
791 case IRQ_PROG_INTA: 798 case IRQ_PROG_INTA:
792 set_irq_chained_handler(irq, 799 set_irq_chained_handler(irq,
793 bfin_demux_gpio_irq); 800 bfin_demux_gpio_irq);
@@ -798,7 +805,7 @@ int __init init_arch_irq(void)
798 bfin_demux_gpio_irq); 805 bfin_demux_gpio_irq);
799 break; 806 break;
800#endif 807#endif
801#else 808#elif defined(CONFIG_BF54x)
802 case IRQ_PINT0: 809 case IRQ_PINT0:
803 set_irq_chained_handler(irq, 810 set_irq_chained_handler(irq,
804 bfin_demux_gpio_irq); 811 bfin_demux_gpio_irq);
@@ -815,7 +822,20 @@ int __init init_arch_irq(void)
815 set_irq_chained_handler(irq, 822 set_irq_chained_handler(irq,
816 bfin_demux_gpio_irq); 823 bfin_demux_gpio_irq);
817 break; 824 break;
818#endif /*CONFIG_BF54x */ 825#elif defined(CONFIG_BF52x)
826 case IRQ_PORTF_INTA:
827 set_irq_chained_handler(irq,
828 bfin_demux_gpio_irq);
829 break;
830 case IRQ_PORTG_INTA:
831 set_irq_chained_handler(irq,
832 bfin_demux_gpio_irq);
833 break;
834 case IRQ_PORTH_INTA:
835 set_irq_chained_handler(irq,
836 bfin_demux_gpio_irq);
837 break;
838#endif
819#endif 839#endif
820 default: 840 default:
821 set_irq_handler(irq, handle_simple_irq); 841 set_irq_handler(irq, handle_simple_irq);
@@ -880,14 +900,15 @@ void do_irq(int vec, struct pt_regs *fp)
880 } else { 900 } else {
881 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; 901 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
882 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; 902 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
883#ifdef CONFIG_BF54x 903#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
884 unsigned long sic_status[3]; 904 unsigned long sic_status[3];
885 905
886 SSYNC(); 906 SSYNC();
887 sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0); 907 sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0);
888 sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1); 908 sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1);
909#ifdef CONFIG_BF54x
889 sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2); 910 sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2);
890 911#endif
891 for (;; ivg++) { 912 for (;; ivg++) {
892 if (ivg >= ivg_stop) { 913 if (ivg >= ivg_stop) {
893 atomic_inc(&num_spurious); 914 atomic_inc(&num_spurious);
diff --git a/include/asm-blackfin/bf5xx_timers.h b/include/asm-blackfin/bf5xx_timers.h
index 86c770321b61..8e8246f32fec 100644
--- a/include/asm-blackfin/bf5xx_timers.h
+++ b/include/asm-blackfin/bf5xx_timers.h
@@ -16,7 +16,7 @@
16/* 16/*
17 * BF537: 8 timers: 17 * BF537: 8 timers:
18 */ 18 */
19#if defined(CONFIG_BF537) 19#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
20# define MAX_BLACKFIN_GPTIMERS 8 20# define MAX_BLACKFIN_GPTIMERS 8
21# define TIMER0_GROUP_REG TIMER_ENABLE 21# define TIMER0_GROUP_REG TIMER_ENABLE
22#endif 22#endif
diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h
index dd203cd93796..33ce98ef7e0f 100644
--- a/include/asm-blackfin/gpio.h
+++ b/include/asm-blackfin/gpio.h
@@ -29,6 +29,7 @@
29 29
30/* 30/*
31* Number BF537/6/4 BF561 BF533/2/1 31* Number BF537/6/4 BF561 BF533/2/1
32* BF527/5/2
32* 33*
33* GPIO_0 PF0 PF0 PF0 34* GPIO_0 PF0 PF0 PF0
34* GPIO_1 PF1 PF1 PF1 35* GPIO_1 PF1 PF1 PF1
@@ -164,7 +165,7 @@
164 165
165#endif 166#endif
166 167
167#ifdef BF537_FAMILY 168#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
168#define MAX_BLACKFIN_GPIOS 48 169#define MAX_BLACKFIN_GPIOS 48
169 170
170#define GPIO_PF0 0 171#define GPIO_PF0 0
diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h
index 991db986cd4b..a89120445be6 100644
--- a/include/asm-blackfin/mach-bf527/anomaly.h
+++ b/include/asm-blackfin/mach-bf527/anomaly.h
@@ -38,4 +38,12 @@
38 38
39/* Anomalies that don't exist on this proc */ 39/* Anomalies that don't exist on this proc */
40#define ANOMALY_05000323 (0) 40#define ANOMALY_05000323 (0)
41#define ANOMALY_05000244 (0)
42#define ANOMALY_05000198 (0)
43#define ANOMALY_05000125 (0)
44#define ANOMALY_05000158 (0)
45#define ANOMALY_05000273 (0)
46#define ANOMALY_05000263 (0)
47#define ANOMALY_05000311 (0)
48#define ANOMALY_05000230 (0)
41#endif 49#endif
diff --git a/include/asm-blackfin/mach-bf527/bf527.h b/include/asm-blackfin/mach-bf527/bf527.h
new file mode 100644
index 000000000000..056eb4b9cd25
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/bf527.h
@@ -0,0 +1,127 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/bf527.h
3 * Based on: include/asm-blackfin/mach-bf537/bf537.h
4 * Author: Michael Hennerich (michael.hennerich@analog.com)
5 *
6 * Created:
7 * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF527
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __MACH_BF527_H__
31#define __MACH_BF527_H__
32
33#define SUPPORTED_REVID 2
34
35#define OFFSET_(x) ((x) & 0x0000FFFF)
36
37/*some misc defines*/
38#define IMASK_IVG15 0x8000
39#define IMASK_IVG14 0x4000
40#define IMASK_IVG13 0x2000
41#define IMASK_IVG12 0x1000
42
43#define IMASK_IVG11 0x0800
44#define IMASK_IVG10 0x0400
45#define IMASK_IVG9 0x0200
46#define IMASK_IVG8 0x0100
47
48#define IMASK_IVG7 0x0080
49#define IMASK_IVGTMR 0x0040
50#define IMASK_IVGHW 0x0020
51
52/***************************/
53
54#define BFIN_DSUBBANKS 4
55#define BFIN_DWAYS 2
56#define BFIN_DLINES 64
57#define BFIN_ISUBBANKS 4
58#define BFIN_IWAYS 4
59#define BFIN_ILINES 32
60
61#define WAY0_L 0x1
62#define WAY1_L 0x2
63#define WAY01_L 0x3
64#define WAY2_L 0x4
65#define WAY02_L 0x5
66#define WAY12_L 0x6
67#define WAY012_L 0x7
68
69#define WAY3_L 0x8
70#define WAY03_L 0x9
71#define WAY13_L 0xA
72#define WAY013_L 0xB
73
74#define WAY32_L 0xC
75#define WAY320_L 0xD
76#define WAY321_L 0xE
77#define WAYALL_L 0xF
78
79#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
80
81/********************************* EBIU Settings ************************************/
82#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
83#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
84
85#ifdef CONFIG_C_AMBEN_ALL
86#define V_AMBEN AMBEN_ALL
87#endif
88#ifdef CONFIG_C_AMBEN
89#define V_AMBEN 0x0
90#endif
91#ifdef CONFIG_C_AMBEN_B0
92#define V_AMBEN AMBEN_B0
93#endif
94#ifdef CONFIG_C_AMBEN_B0_B1
95#define V_AMBEN AMBEN_B0_B1
96#endif
97#ifdef CONFIG_C_AMBEN_B0_B1_B2
98#define V_AMBEN AMBEN_B0_B1_B2
99#endif
100#ifdef CONFIG_C_AMCKEN
101#define V_AMCKEN AMCKEN
102#else
103#define V_AMCKEN 0x0
104#endif
105#ifdef CONFIG_C_CDPRIO
106#define V_CDPRIO 0x100
107#else
108#define V_CDPRIO 0x0
109#endif
110
111#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
112
113#ifdef CONFIG_BF527
114#define CPU "BF527"
115#endif
116#ifdef CONFIG_BF525
117#define CPU "BF525"
118#endif
119#ifdef CONFIG_BF522
120#define CPU "BF522"
121#endif
122#ifndef CPU
123#define CPU "UNKNOWN"
124#define CPUID 0x0
125#endif
126
127#endif /* __MACH_BF527_H__ */
diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
new file mode 100644
index 000000000000..0b867e6a76c4
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
@@ -0,0 +1,152 @@
1#include <linux/serial.h>
2#include <asm/dma.h>
3#include <asm/portmux.h>
4
5#define NR_PORTS 2
6
7#define OFFSET_THR 0x00 /* Transmit Holding register */
8#define OFFSET_RBR 0x00 /* Receive Buffer register */
9#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
10#define OFFSET_IER 0x04 /* Interrupt Enable Register */
11#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
12#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
13#define OFFSET_LCR 0x0C /* Line Control Register */
14#define OFFSET_MCR 0x10 /* Modem Control Register */
15#define OFFSET_LSR 0x14 /* Line Status Register */
16#define OFFSET_MSR 0x18 /* Modem Status Register */
17#define OFFSET_SCR 0x1C /* SCR Scratch Register */
18#define OFFSET_GCTL 0x24 /* Global Control Register */
19
20#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
21#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
22#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
23#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
24#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
25#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
26#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
27#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
28
29#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
30#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
31#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
32#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
33#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
34#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
35
36#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
37# define CONFIG_SERIAL_BFIN_CTSRTS
38
39# ifndef CONFIG_UART0_CTS_PIN
40# define CONFIG_UART0_CTS_PIN -1
41# endif
42
43# ifndef CONFIG_UART0_RTS_PIN
44# define CONFIG_UART0_RTS_PIN -1
45# endif
46
47# ifndef CONFIG_UART1_CTS_PIN
48# define CONFIG_UART1_CTS_PIN -1
49# endif
50
51# ifndef CONFIG_UART1_RTS_PIN
52# define CONFIG_UART1_RTS_PIN -1
53# endif
54#endif
55/*
56 * The pin configuration is different from schematic
57 */
58struct bfin_serial_port {
59 struct uart_port port;
60 unsigned int old_status;
61#ifdef CONFIG_SERIAL_BFIN_DMA
62 int tx_done;
63 int tx_count;
64 struct circ_buf rx_dma_buf;
65 struct timer_list rx_dma_timer;
66 int rx_dma_nrows;
67 unsigned int tx_dma_channel;
68 unsigned int rx_dma_channel;
69 struct work_struct tx_dma_workqueue;
70#else
71 struct work_struct cts_workqueue;
72#endif
73#ifdef CONFIG_SERIAL_BFIN_CTSRTS
74 int cts_pin;
75 int rts_pin;
76#endif
77};
78
79struct bfin_serial_port bfin_serial_ports[NR_PORTS];
80struct bfin_serial_res {
81 unsigned long uart_base_addr;
82 int uart_irq;
83#ifdef CONFIG_SERIAL_BFIN_DMA
84 unsigned int uart_tx_dma_channel;
85 unsigned int uart_rx_dma_channel;
86#endif
87#ifdef CONFIG_SERIAL_BFIN_CTSRTS
88 int uart_cts_pin;
89 int uart_rts_pin;
90#endif
91};
92
93struct bfin_serial_res bfin_serial_resource[] = {
94#ifdef CONFIG_SERIAL_BFIN_UART0
95 {
96 0xFFC00400,
97 IRQ_UART0_RX,
98#ifdef CONFIG_SERIAL_BFIN_DMA
99 CH_UART0_TX,
100 CH_UART0_RX,
101#endif
102#ifdef CONFIG_BFIN_UART0_CTSRTS
103 CONFIG_UART0_CTS_PIN,
104 CONFIG_UART0_RTS_PIN,
105#endif
106 },
107#endif
108#ifdef CONFIG_SERIAL_BFIN_UART1
109 {
110 0xFFC02000,
111 IRQ_UART1_RX,
112#ifdef CONFIG_SERIAL_BFIN_DMA
113 CH_UART1_TX,
114 CH_UART1_RX,
115#endif
116#ifdef CONFIG_BFIN_UART1_CTSRTS
117 CONFIG_UART1_CTS_PIN,
118 CONFIG_UART1_RTS_PIN,
119#endif
120 },
121#endif
122};
123
124int nr_ports = ARRAY_SIZE(bfin_serial_resource);
125
126#define DRIVER_NAME "bfin-uart"
127
128static void bfin_serial_hw_init(struct bfin_serial_port *uart)
129{
130
131#ifdef CONFIG_SERIAL_BFIN_UART0
132 peripheral_request(P_UART0_TX, DRIVER_NAME);
133 peripheral_request(P_UART0_RX, DRIVER_NAME);
134#endif
135
136#ifdef CONFIG_SERIAL_BFIN_UART1
137 peripheral_request(P_UART1_TX, DRIVER_NAME);
138 peripheral_request(P_UART1_RX, DRIVER_NAME);
139#endif
140
141#ifdef CONFIG_SERIAL_BFIN_CTSRTS
142 if (uart->cts_pin >= 0) {
143 gpio_request(uart->cts_pin, DRIVER_NAME);
144 gpio_direction_input(uart->cts_pin);
145 }
146
147 if (uart->rts_pin >= 0) {
148 gpio_request(uart->rts_pin, DRIVER_NAME);
149 gpio_direction_output(uart->rts_pin);
150 }
151#endif
152}
diff --git a/include/asm-blackfin/mach-bf527/blackfin.h b/include/asm-blackfin/mach-bf527/blackfin.h
new file mode 100644
index 000000000000..1bd07e30781c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/blackfin.h
@@ -0,0 +1,78 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/blackfin.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _MACH_BLACKFIN_H_
33#define _MACH_BLACKFIN_H_
34
35#define BF527_FAMILY
36
37#include "bf527.h"
38#include "mem_map.h"
39#include "defBF522.h"
40#include "anomaly.h"
41
42#if defined(CONFIG_BF527)
43#include "defBF527.h"
44#endif
45
46#if defined(CONFIG_BF525)
47#include "defBF525.h"
48#endif
49
50#if !defined(__ASSEMBLY__)
51#include "cdefBF522.h"
52
53#if defined(CONFIG_BF527)
54#include "cdefBF527.h"
55#endif
56
57#if defined(CONFIG_BF525)
58#include "cdefBF525.h"
59#endif
60#endif
61
62/* UART_IIR Register */
63#define STATUS(x) ((x << 1) & 0x06)
64#define STATUS_P1 0x02
65#define STATUS_P0 0x01
66
67/* DPMC*/
68#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
69#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
70#define STOPCK_OFF STOPCK
71
72/* PLL_DIV Masks */
73#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
74#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
75#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
76#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
77
78#endif
diff --git a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
index 5f801a0ef797..3f4de5d9d4cb 100644
--- a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
+++ b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
@@ -45,8 +45,8 @@
45#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) 45#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
46#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 46#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
47#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) 47#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
48#define bfin_read_CHIPID() bfin_read16(CHIPID) 48#define bfin_read_CHIPID() bfin_read32(CHIPID)
49#define bfin_write_CHIPID(val) bfin_write16(CHIPID, val) 49#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
50 50
51 51
52/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ 52/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
@@ -59,9 +59,8 @@
59#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) 59#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
60#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) 60#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
61#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) 61#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
62/* legacy register name (below) provided for backwards code compatibility */ 62#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
63#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) 63#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
64#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val)
65 64
66#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) 65#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
67#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) 66#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
@@ -74,15 +73,13 @@
74 73
75#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) 74#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
76#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) 75#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
77/* legacy register name (below) provided for backwards code compatibility */ 76#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
78#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR) 77#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
79#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val)
80 78
81#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) 79#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
82#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) 80#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
83/* legacy register name (below) provided for backwards code compatibility */ 81#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
84#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR) 82#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
85#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val)
86 83
87/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */ 84/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
88 85
diff --git a/include/asm-blackfin/mach-bf527/defBF527.h b/include/asm-blackfin/mach-bf527/defBF527.h
index 2be3293f9e26..82134f578f32 100644
--- a/include/asm-blackfin/mach-bf527/defBF527.h
+++ b/include/asm-blackfin/mach-bf527/defBF527.h
@@ -32,12 +32,12 @@
32#define _DEF_BF527_H 32#define _DEF_BF527_H
33 33
34/* Include all Core registers and bit definitions */ 34/* Include all Core registers and bit definitions */
35#include <def_LPBlackfin.h> 35#include <asm/mach-common/def_LPBlackfin.h>
36 36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */ 37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
38 38
39/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ 39/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
40#include <defBF52x_base.h> 40#include "defBF52x_base.h"
41 41
42/* The following are the #defines needed by ADSP-BF527 that are not in the common header */ 42/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
43/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ 43/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
diff --git a/include/asm-blackfin/mach-bf527/defBF52x_base.h b/include/asm-blackfin/mach-bf527/defBF52x_base.h
index b1ff67db01f8..d6c24c54699d 100644
--- a/include/asm-blackfin/mach-bf527/defBF52x_base.h
+++ b/include/asm-blackfin/mach-bf527/defBF52x_base.h
@@ -52,13 +52,13 @@
52#define SYSCR 0xFFC00104 /* System Configuration Register */ 52#define SYSCR 0xFFC00104 /* System Configuration Register */
53#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ 53#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
54 54
55#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ 55#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
56#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ 56#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
57#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ 57#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
58#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ 58#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
59#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ 59#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
60#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ 60#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
61#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ 61#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
62 62
63/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */ 63/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
64#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ 64#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
@@ -691,6 +691,8 @@
691 691
692/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/ 692/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
693/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */ 693/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
694
695#if 0
694#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */ 696#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
695 697
696#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */ 698#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
@@ -732,6 +734,7 @@
732#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */ 734#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
733#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */ 735#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
734#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */ 736#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
737#endif
735 738
736/* SIC_IAR0 Macros */ 739/* SIC_IAR0 Macros */
737#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */ 740#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
diff --git a/include/asm-blackfin/mach-bf527/dma.h b/include/asm-blackfin/mach-bf527/dma.h
new file mode 100644
index 000000000000..a41627ae9134
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/dma.h
@@ -0,0 +1,60 @@
1/*
2 * file: include/asm-blackfin/mach-bf527/dma.h
3 * based on: include/asm-blackfin/mach-bf537/dma.h
4 * author: Michael Hennerich (michael.hennerich@analog.com)
5 *
6 * created:
7 * description:
8 * system DMA map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _MACH_DMA_H_
33#define _MACH_DMA_H_
34
35#define MAX_BLACKFIN_DMA_CHANNEL 16
36
37#define CH_PPI 0 /* PPI receive/transmit or NFC */
38#define CH_NFC 0 /* PPI receive/transmit or NFC */
39#define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */
40#define CH_EMAC_HOSTDP 1 /* Ethernet MAC receive or HOSTDP */
41#define CH_EMAC_TX 2 /* Ethernet MAC transmit or NFC */
42#define CH_SPORT0_RX 3 /* SPORT0 receive */
43#define CH_SPORT0_TX 4 /* SPORT0 transmit */
44#define CH_SPORT1_RX 5 /* SPORT1 receive */
45#define CH_SPORT1_TX 6 /* SPORT1 transmit */
46#define CH_SPI 7 /* SPI transmit/receive */
47#define CH_UART0_RX 8 /* UART0 receive */
48#define CH_UART0_TX 9 /* UART0 transmit */
49#define CH_UART1_RX 10 /* UART1 receive */
50#define CH_UART1_TX 11 /* UART1 transmit */
51
52#define CH_MEM_STREAM0_DEST 12 /* TX */
53#define CH_MEM_STREAM0_SRC 13 /* RX */
54#define CH_MEM_STREAM1_DEST 14 /* TX */
55#define CH_MEM_STREAM1_SRC 15 /* RX */
56
57extern int channel2irq(unsigned int channel);
58extern struct dma_register *base_addr[];
59
60#endif
diff --git a/include/asm-blackfin/mach-bf527/irq.h b/include/asm-blackfin/mach-bf527/irq.h
new file mode 100644
index 000000000000..304f5bcfebe4
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/irq.h
@@ -0,0 +1,263 @@
1/*
2 * file: include/asm-blackfin/mach-bf527/irq.h
3 * based on: include/asm-blackfin/mach-bf537/irq.h
4 * author: Michael Hennerich (michael.hennerich@analog.com)
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _BF527_IRQ_H_
33#define _BF527_IRQ_H_
34
35/*
36 * Interrupt source definitions
37 Event Source Core Event Name
38 Core Emulation **
39 Events (highest priority) EMU 0
40 Reset RST 1
41 NMI NMI 2
42 Exception EVX 3
43 Reserved -- 4
44 Hardware Error IVHW 5
45 Core Timer IVTMR 6 *
46
47 .....
48
49 Software Interrupt 1 IVG14 31
50 Software Interrupt 2 --
51 (lowest priority) IVG15 32 *
52*/
53
54#define NR_PERI_INTS (2 * 32)
55
56/* The ABSTRACT IRQ definitions */
57/** the first seven of the following are fixed, the rest you change if you need to **/
58#define IRQ_EMU 0 /* Emulation */
59#define IRQ_RST 1 /* reset */
60#define IRQ_NMI 2 /* Non Maskable */
61#define IRQ_EVX 3 /* Exception */
62#define IRQ_UNUSED 4 /* - unused interrupt */
63#define IRQ_HWERR 5 /* Hardware Error */
64#define IRQ_CORETMR 6 /* Core timer */
65
66#define BFIN_IRQ(x) ((x) + 7)
67
68#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
69#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
70#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */
71#define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */
72#define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */
73#define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */
74#define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */
75#define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */
76#define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */
77#define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */
78#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
79#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
80#define IRQ_RTC BFIN_IRQ(14) /* RTC */
81#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */
82#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
83#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
84#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */
85#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
86#define IRQ_TWI BFIN_IRQ(20) /* TWI */
87#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */
88#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
89#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
90#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
91#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
92#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
93#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
94#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */
95#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
96#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
97#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
98#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
99#define IRQ_TMR0 BFIN_IRQ(32) /* Timer 0 */
100#define IRQ_TMR1 BFIN_IRQ(33) /* Timer 1 */
101#define IRQ_TMR2 BFIN_IRQ(34) /* Timer 2 */
102#define IRQ_TMR3 BFIN_IRQ(35) /* Timer 3 */
103#define IRQ_TMR4 BFIN_IRQ(36) /* Timer 4 */
104#define IRQ_TMR5 BFIN_IRQ(37) /* Timer 5 */
105#define IRQ_TMR6 BFIN_IRQ(38) /* Timer 6 */
106#define IRQ_TMR7 BFIN_IRQ(39) /* Timer 7 */
107#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */
108#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */
109#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */
110#define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */
111#define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */
112#define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */
113#define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */
114#define IRQ_SPI_ERROR BFIN_IRQ(47) /* SPI Status */
115#define IRQ_NFC_ERROR BFIN_IRQ(48) /* NAND Error */
116#define IRQ_HDMA_ERROR BFIN_IRQ(49) /* HDMA Error */
117#define IRQ_HDMA BFIN_IRQ(50) /* HDMA (TFI) */
118#define IRQ_USB_EINT BFIN_IRQ(51) /* USB_EINT Interrupt */
119#define IRQ_USB_INT0 BFIN_IRQ(52) /* USB_INT0 Interrupt */
120#define IRQ_USB_INT1 BFIN_IRQ(53) /* USB_INT1 Interrupt */
121#define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */
122#define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */
123
124#define SYS_IRQS BFIN_IRQ(63) /* 70 */
125
126#define IRQ_PF0 71
127#define IRQ_PF1 72
128#define IRQ_PF2 73
129#define IRQ_PF3 74
130#define IRQ_PF4 75
131#define IRQ_PF5 76
132#define IRQ_PF6 77
133#define IRQ_PF7 78
134#define IRQ_PF8 79
135#define IRQ_PF9 80
136#define IRQ_PF10 81
137#define IRQ_PF11 82
138#define IRQ_PF12 83
139#define IRQ_PF13 84
140#define IRQ_PF14 85
141#define IRQ_PF15 86
142
143#define IRQ_PG0 87
144#define IRQ_PG1 88
145#define IRQ_PG2 89
146#define IRQ_PG3 90
147#define IRQ_PG4 91
148#define IRQ_PG5 92
149#define IRQ_PG6 93
150#define IRQ_PG7 94
151#define IRQ_PG8 95
152#define IRQ_PG9 96
153#define IRQ_PG10 97
154#define IRQ_PG11 98
155#define IRQ_PG12 99
156#define IRQ_PG13 100
157#define IRQ_PG14 101
158#define IRQ_PG15 102
159
160#define IRQ_PH0 103
161#define IRQ_PH1 104
162#define IRQ_PH2 105
163#define IRQ_PH3 106
164#define IRQ_PH4 107
165#define IRQ_PH5 108
166#define IRQ_PH6 109
167#define IRQ_PH7 110
168#define IRQ_PH8 111
169#define IRQ_PH9 112
170#define IRQ_PH10 113
171#define IRQ_PH11 114
172#define IRQ_PH12 115
173#define IRQ_PH13 116
174#define IRQ_PH14 117
175#define IRQ_PH15 118
176
177#define GPIO_IRQ_BASE IRQ_PF0
178
179#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
180#define NR_IRQS (IRQ_PH15+1)
181#else
182#define NR_IRQS (SYS_IRQS+1)
183#endif
184
185#define IVG7 7
186#define IVG8 8
187#define IVG9 9
188#define IVG10 10
189#define IVG11 11
190#define IVG12 12
191#define IVG13 13
192#define IVG14 14
193#define IVG15 15
194
195/* IAR0 BIT FIELDS */
196#define IRQ_PLL_WAKEUP_POS 0
197#define IRQ_DMA0_ERROR_POS 4
198#define IRQ_DMAR0_BLK_POS 8
199#define IRQ_DMAR1_BLK_POS 12
200#define IRQ_DMAR0_OVR_POS 16
201#define IRQ_DMAR1_OVR_POS 20
202#define IRQ_PPI_ERROR_POS 24
203#define IRQ_MAC_ERROR_POS 28
204
205/* IAR1 BIT FIELDS */
206#define IRQ_SPORT0_ERROR_POS 0
207#define IRQ_SPORT1_ERROR_POS 4
208#define IRQ_UART0_ERROR_POS 16
209#define IRQ_UART1_ERROR_POS 20
210#define IRQ_RTC_POS 24
211#define IRQ_PPI_POS 28
212
213/* IAR2 BIT FIELDS */
214#define IRQ_SPORT0_RX_POS 0
215#define IRQ_SPORT0_TX_POS 4
216#define IRQ_SPORT1_RX_POS 8
217#define IRQ_SPORT1_TX_POS 12
218#define IRQ_TWI_POS 16
219#define IRQ_SPI_POS 20
220#define IRQ_UART0_RX_POS 24
221#define IRQ_UART0_TX_POS 28
222
223/* IAR3 BIT FIELDS */
224#define IRQ_UART1_RX_POS 0
225#define IRQ_UART1_TX_POS 4
226#define IRQ_OPTSEC_POS 8
227#define IRQ_CNT_POS 12
228#define IRQ_MAC_RX_POS 16
229#define IRQ_PORTH_INTA_POS 20
230#define IRQ_MAC_TX_POS 24
231#define IRQ_PORTH_INTB_POS 28
232
233/* IAR4 BIT FIELDS */
234#define IRQ_TMR0_POS 0
235#define IRQ_TMR1_POS 4
236#define IRQ_TMR2_POS 8
237#define IRQ_TMR3_POS 12
238#define IRQ_TMR4_POS 16
239#define IRQ_TMR5_POS 20
240#define IRQ_TMR6_POS 24
241#define IRQ_TMR7_POS 28
242
243/* IAR5 BIT FIELDS */
244#define IRQ_PORTG_INTA_POS 0
245#define IRQ_PORTG_INTB_POS 4
246#define IRQ_MEM_DMA0_POS 8
247#define IRQ_MEM_DMA1_POS 12
248#define IRQ_WATCH_POS 16
249#define IRQ_PORTF_INTA_POS 20
250#define IRQ_PORTF_INTB_POS 24
251#define IRQ_SPI_ERROR_POS 28
252
253/* IAR6 BIT FIELDS */
254#define IRQ_NFC_ERROR_POS 0
255#define IRQ_HDMA_ERROR_POS 4
256#define IRQ_HDMA_POS 8
257#define IRQ_USB_EINT_POS 12
258#define IRQ_USB_INT0_POS 16
259#define IRQ_USB_INT1_POS 20
260#define IRQ_USB_INT2_POS 24
261#define IRQ_USB_DMA_POS 28
262
263#endif /* _BF527_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf527/mem_init.h b/include/asm-blackfin/mach-bf527/mem_init.h
new file mode 100644
index 000000000000..008ca66719e2
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/mem_init.h
@@ -0,0 +1,337 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 * Copyright 2004-2007 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75 || CONFIG_MEM_MT48LC32M16A2TG_75)
33#if (CONFIG_SCLK_HZ > 119402985)
34#define SDRAM_tRP TRP_2
35#define SDRAM_tRP_num 2
36#define SDRAM_tRAS TRAS_7
37#define SDRAM_tRAS_num 7
38#define SDRAM_tRCD TRCD_2
39#define SDRAM_tWR TWR_2
40#endif
41#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
42#define SDRAM_tRP TRP_2
43#define SDRAM_tRP_num 2
44#define SDRAM_tRAS TRAS_6
45#define SDRAM_tRAS_num 6
46#define SDRAM_tRCD TRCD_2
47#define SDRAM_tWR TWR_2
48#endif
49#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
50#define SDRAM_tRP TRP_2
51#define SDRAM_tRP_num 2
52#define SDRAM_tRAS TRAS_5
53#define SDRAM_tRAS_num 5
54#define SDRAM_tRCD TRCD_2
55#define SDRAM_tWR TWR_2
56#endif
57#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
58#define SDRAM_tRP TRP_2
59#define SDRAM_tRP_num 2
60#define SDRAM_tRAS TRAS_4
61#define SDRAM_tRAS_num 4
62#define SDRAM_tRCD TRCD_2
63#define SDRAM_tWR TWR_2
64#endif
65#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
66#define SDRAM_tRP TRP_2
67#define SDRAM_tRP_num 2
68#define SDRAM_tRAS TRAS_3
69#define SDRAM_tRAS_num 3
70#define SDRAM_tRCD TRCD_2
71#define SDRAM_tWR TWR_2
72#endif
73#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
74#define SDRAM_tRP TRP_1
75#define SDRAM_tRP_num 1
76#define SDRAM_tRAS TRAS_4
77#define SDRAM_tRAS_num 3
78#define SDRAM_tRCD TRCD_1
79#define SDRAM_tWR TWR_2
80#endif
81#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
82#define SDRAM_tRP TRP_1
83#define SDRAM_tRP_num 1
84#define SDRAM_tRAS TRAS_3
85#define SDRAM_tRAS_num 3
86#define SDRAM_tRCD TRCD_1
87#define SDRAM_tWR TWR_2
88#endif
89#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
90#define SDRAM_tRP TRP_1
91#define SDRAM_tRP_num 1
92#define SDRAM_tRAS TRAS_2
93#define SDRAM_tRAS_num 2
94#define SDRAM_tRCD TRCD_1
95#define SDRAM_tWR TWR_2
96#endif
97#if (CONFIG_SCLK_HZ <= 29850746)
98#define SDRAM_tRP TRP_1
99#define SDRAM_tRP_num 1
100#define SDRAM_tRAS TRAS_1
101#define SDRAM_tRAS_num 1
102#define SDRAM_tRCD TRCD_1
103#define SDRAM_tWR TWR_2
104#endif
105#endif
106
107#if (CONFIG_MEM_MT48LC16M16A2TG_75)
108 /*SDRAM INFORMATION: */
109#define SDRAM_Tref 64 /* Refresh period in milliseconds */
110#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
111#define SDRAM_CL CL_3
112#endif
113
114#if (CONFIG_MEM_MT48LC16M8A2TG_75)
115 /*SDRAM INFORMATION: */
116#define SDRAM_Tref 64 /* Refresh period in milliseconds */
117#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
118#define SDRAM_CL CL_3
119#endif
120
121#if (CONFIG_MEM_MT48LC32M8A2_75)
122 /*SDRAM INFORMATION: */
123#define SDRAM_Tref 64 /* Refresh period in milliseconds */
124#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
125#define SDRAM_CL CL_3
126#endif
127
128#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
129 /*SDRAM INFORMATION: */
130#define SDRAM_Tref 64 /* Refresh period in milliseconds */
131#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
132#define SDRAM_CL CL_3
133#endif
134
135#if (CONFIG_MEM_GENERIC_BOARD)
136 /*SDRAM INFORMATION: Modify this for your board */
137#define SDRAM_Tref 64 /* Refresh period in milliseconds */
138#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
139#define SDRAM_CL CL_3
140#endif
141
142#if (CONFIG_MEM_MT48LC32M16A2TG_75)
143 /*SDRAM INFORMATION: */
144#define SDRAM_Tref 64 /* Refresh period in milliseconds */
145#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
146#define SDRAM_CL CL_3
147#endif
148
149#if (CONFIG_MEM_SIZE == 128)
150#define SDRAM_SIZE EBSZ_128
151#endif
152#if (CONFIG_MEM_SIZE == 64)
153#define SDRAM_SIZE EBSZ_64
154#endif
155#if (CONFIG_MEM_SIZE == 32)
156#define SDRAM_SIZE EBSZ_32
157#endif
158#if (CONFIG_MEM_SIZE == 16)
159#define SDRAM_SIZE EBSZ_16
160#endif
161#if (CONFIG_MEM_ADD_WIDTH == 11)
162#define SDRAM_WIDTH EBCAW_11
163#endif
164#if (CONFIG_MEM_ADD_WIDTH == 10)
165#define SDRAM_WIDTH EBCAW_10
166#endif
167#if (CONFIG_MEM_ADD_WIDTH == 9)
168#define SDRAM_WIDTH EBCAW_9
169#endif
170#if (CONFIG_MEM_ADD_WIDTH == 8)
171#define SDRAM_WIDTH EBCAW_8
172#endif
173
174#define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EBE)
175
176/* Equation from section 17 (p17-46) of BF533 HRM */
177#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
178
179/* Enable SCLK Out */
180#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
181
182#if defined CONFIG_CLKIN_HALF
183#define CLKIN_HALF 1
184#else
185#define CLKIN_HALF 0
186#endif
187
188#if defined CONFIG_PLL_BYPASS
189#define PLL_BYPASS 1
190#else
191#define PLL_BYPASS 0
192#endif
193
194/***************************************Currently Not Being Used *********************************/
195#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
196#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
197#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
198#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
199#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
200
201#if (flash_EBIU_AMBCTL_TT > 3)
202#define flash_EBIU_AMBCTL0_TT B0TT_4
203#endif
204#if (flash_EBIU_AMBCTL_TT == 3)
205#define flash_EBIU_AMBCTL0_TT B0TT_3
206#endif
207#if (flash_EBIU_AMBCTL_TT == 2)
208#define flash_EBIU_AMBCTL0_TT B0TT_2
209#endif
210#if (flash_EBIU_AMBCTL_TT < 2)
211#define flash_EBIU_AMBCTL0_TT B0TT_1
212#endif
213
214#if (flash_EBIU_AMBCTL_ST > 3)
215#define flash_EBIU_AMBCTL0_ST B0ST_4
216#endif
217#if (flash_EBIU_AMBCTL_ST == 3)
218#define flash_EBIU_AMBCTL0_ST B0ST_3
219#endif
220#if (flash_EBIU_AMBCTL_ST == 2)
221#define flash_EBIU_AMBCTL0_ST B0ST_2
222#endif
223#if (flash_EBIU_AMBCTL_ST < 2)
224#define flash_EBIU_AMBCTL0_ST B0ST_1
225#endif
226
227#if (flash_EBIU_AMBCTL_HT > 2)
228#define flash_EBIU_AMBCTL0_HT B0HT_3
229#endif
230#if (flash_EBIU_AMBCTL_HT == 2)
231#define flash_EBIU_AMBCTL0_HT B0HT_2
232#endif
233#if (flash_EBIU_AMBCTL_HT == 1)
234#define flash_EBIU_AMBCTL0_HT B0HT_1
235#endif
236#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
237#define flash_EBIU_AMBCTL0_HT B0HT_0
238#endif
239#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
240#define flash_EBIU_AMBCTL0_HT B0HT_1
241#endif
242
243#if (flash_EBIU_AMBCTL_WAT > 14)
244#define flash_EBIU_AMBCTL0_WAT B0WAT_15
245#endif
246#if (flash_EBIU_AMBCTL_WAT == 14)
247#define flash_EBIU_AMBCTL0_WAT B0WAT_14
248#endif
249#if (flash_EBIU_AMBCTL_WAT == 13)
250#define flash_EBIU_AMBCTL0_WAT B0WAT_13
251#endif
252#if (flash_EBIU_AMBCTL_WAT == 12)
253#define flash_EBIU_AMBCTL0_WAT B0WAT_12
254#endif
255#if (flash_EBIU_AMBCTL_WAT == 11)
256#define flash_EBIU_AMBCTL0_WAT B0WAT_11
257#endif
258#if (flash_EBIU_AMBCTL_WAT == 10)
259#define flash_EBIU_AMBCTL0_WAT B0WAT_10
260#endif
261#if (flash_EBIU_AMBCTL_WAT == 9)
262#define flash_EBIU_AMBCTL0_WAT B0WAT_9
263#endif
264#if (flash_EBIU_AMBCTL_WAT == 8)
265#define flash_EBIU_AMBCTL0_WAT B0WAT_8
266#endif
267#if (flash_EBIU_AMBCTL_WAT == 7)
268#define flash_EBIU_AMBCTL0_WAT B0WAT_7
269#endif
270#if (flash_EBIU_AMBCTL_WAT == 6)
271#define flash_EBIU_AMBCTL0_WAT B0WAT_6
272#endif
273#if (flash_EBIU_AMBCTL_WAT == 5)
274#define flash_EBIU_AMBCTL0_WAT B0WAT_5
275#endif
276#if (flash_EBIU_AMBCTL_WAT == 4)
277#define flash_EBIU_AMBCTL0_WAT B0WAT_4
278#endif
279#if (flash_EBIU_AMBCTL_WAT == 3)
280#define flash_EBIU_AMBCTL0_WAT B0WAT_3
281#endif
282#if (flash_EBIU_AMBCTL_WAT == 2)
283#define flash_EBIU_AMBCTL0_WAT B0WAT_2
284#endif
285#if (flash_EBIU_AMBCTL_WAT == 1)
286#define flash_EBIU_AMBCTL0_WAT B0WAT_1
287#endif
288
289#if (flash_EBIU_AMBCTL_RAT > 14)
290#define flash_EBIU_AMBCTL0_RAT B0RAT_15
291#endif
292#if (flash_EBIU_AMBCTL_RAT == 14)
293#define flash_EBIU_AMBCTL0_RAT B0RAT_14
294#endif
295#if (flash_EBIU_AMBCTL_RAT == 13)
296#define flash_EBIU_AMBCTL0_RAT B0RAT_13
297#endif
298#if (flash_EBIU_AMBCTL_RAT == 12)
299#define flash_EBIU_AMBCTL0_RAT B0RAT_12
300#endif
301#if (flash_EBIU_AMBCTL_RAT == 11)
302#define flash_EBIU_AMBCTL0_RAT B0RAT_11
303#endif
304#if (flash_EBIU_AMBCTL_RAT == 10)
305#define flash_EBIU_AMBCTL0_RAT B0RAT_10
306#endif
307#if (flash_EBIU_AMBCTL_RAT == 9)
308#define flash_EBIU_AMBCTL0_RAT B0RAT_9
309#endif
310#if (flash_EBIU_AMBCTL_RAT == 8)
311#define flash_EBIU_AMBCTL0_RAT B0RAT_8
312#endif
313#if (flash_EBIU_AMBCTL_RAT == 7)
314#define flash_EBIU_AMBCTL0_RAT B0RAT_7
315#endif
316#if (flash_EBIU_AMBCTL_RAT == 6)
317#define flash_EBIU_AMBCTL0_RAT B0RAT_6
318#endif
319#if (flash_EBIU_AMBCTL_RAT == 5)
320#define flash_EBIU_AMBCTL0_RAT B0RAT_5
321#endif
322#if (flash_EBIU_AMBCTL_RAT == 4)
323#define flash_EBIU_AMBCTL0_RAT B0RAT_4
324#endif
325#if (flash_EBIU_AMBCTL_RAT == 3)
326#define flash_EBIU_AMBCTL0_RAT B0RAT_3
327#endif
328#if (flash_EBIU_AMBCTL_RAT == 2)
329#define flash_EBIU_AMBCTL0_RAT B0RAT_2
330#endif
331#if (flash_EBIU_AMBCTL_RAT == 1)
332#define flash_EBIU_AMBCTL0_RAT B0RAT_1
333#endif
334
335#define flash_EBIU_AMBCTL0 \
336 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
337 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf527/mem_map.h b/include/asm-blackfin/mach-bf527/mem_map.h
new file mode 100644
index 000000000000..c5aa20102b24
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/mem_map.h
@@ -0,0 +1,98 @@
1/*
2 * file: include/asm-blackfin/mach-bf527/mem_map.h
3 * based on: include/asm-blackfin/mach-bf537/mem_map.h
4 * author: Michael Hennerich (michael.hennerich@analog.com)
5 *
6 * created:
7 * description:
8 * Memory MAP Common header file for blackfin BF527/5/2 of processors.
9 * rev:
10 *
11 * modified:
12 *
13 * bugs: enter bugs at http://blackfin.uclinux.org/
14 *
15 * this program is free software; you can redistribute it and/or modify
16 * it under the terms of the gnu general public license as published by
17 * the free software foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * this program is distributed in the hope that it will be useful,
21 * but without any warranty; without even the implied warranty of
22 * merchantability or fitness for a particular purpose. see the
23 * gnu general public license for more details.
24 *
25 * you should have received a copy of the gnu general public license
26 * along with this program; see the file copying.
27 * if not, write to the free software foundation,
28 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
29 */
30
31#ifndef _MEM_MAP_527_H_
32#define _MEM_MAP_527_H_
33
34#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
35#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
36
37/* Async Memory Banks */
38#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
39#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
40#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
41#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
42#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
43#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
44#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
45#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
46
47/* Boot ROM Memory */
48
49#define BOOT_ROM_START 0xEF000000
50
51/* Level 1 Memory */
52
53/* Memory Map for ADSP-BF527 ADSP-BF525 ADSP-BF522 processors */
54
55#ifdef CONFIG_BFIN_ICACHE
56#define BFIN_ICACHESIZE (16*1024)
57#else
58#define BFIN_ICACHESIZE (0*1024)
59#endif
60
61#define L1_CODE_START 0xFFA00000
62#define L1_DATA_A_START 0xFF800000
63#define L1_DATA_B_START 0xFF900000
64
65#define L1_CODE_LENGTH 0xC000
66
67#ifdef CONFIG_BFIN_DCACHE
68
69#ifdef CONFIG_BFIN_DCACHE_BANKA
70#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
71#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
72#define L1_DATA_B_LENGTH 0x8000
73#define BFIN_DCACHESIZE (16*1024)
74#define BFIN_DSUPBANKS 1
75#else
76#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
77#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
78#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
79#define BFIN_DCACHESIZE (32*1024)
80#define BFIN_DSUPBANKS 2
81#endif
82
83#else
84#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
85#define L1_DATA_A_LENGTH 0x8000
86#define L1_DATA_B_LENGTH 0x8000
87#define BFIN_DCACHESIZE (0*1024)
88#define BFIN_DSUPBANKS 0
89#endif /*CONFIG_BFIN_DCACHE */
90
91/* Scratch Pad Memory */
92
93#if defined(CONFIG_BF527) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
94#define L1_SCRATCH_START 0xFFB00000
95#define L1_SCRATCH_LENGTH 0x1000
96#endif
97
98#endif /* _MEM_MAP_527_H_ */
diff --git a/include/asm-blackfin/mach-bf527/portmux.h b/include/asm-blackfin/mach-bf527/portmux.h
new file mode 100644
index 000000000000..dcf001adc63c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/portmux.h
@@ -0,0 +1,205 @@
1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_
3
4#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
5#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
6#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
7#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
8#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
9#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
10#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
11#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
12#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
13#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
14#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
15#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
16#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
17#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
18#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
19#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
20
21#if defined(CONFIG_BF527_SPORT0_PORTF)
22#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
23#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
24#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
25#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
26#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
27#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
28#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
29#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
30#elif defined(CONFIG_BF527_SPORT0_PORTG)
31#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
32#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
33#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
34#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
35#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
36#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
37#if defined(CONFIG_BF527_SPORT0_TSCLK_PG10)
38#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
39#elif defined(CONFIG_BF527_SPORT0_TSCLK_PG14)
40#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
41#endif
42#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
43#endif
44
45#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
46#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
47#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
48#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
49#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
50#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
51#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
52#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
53
54#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
55#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
56
57#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
58#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
59
60#if defined(CONFIG_BF527_UART1_PORTF)
61#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
62#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
63#elif defined(CONFIG_BF527_UART1_PORTG)
64#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
65#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
66#endif
67
68#define P_HWAIT (P_DONTCARE)
69
70#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
71#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
72#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
73#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
74#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
75#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
76#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
77#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
78#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
79#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
80#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
81/* #define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) */
82#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
83#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
84#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
85#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
86#define P_MDC (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
87#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
88#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
89
90#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
91#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
92#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
93
94#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
95#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
96#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
97#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
98#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
99
100#if defined(CONFIG_BF527_NAND_D_PORTF)
101#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
102#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
103#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
104#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
105#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
106#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
107#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
108#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
109#elif defined(CONFIG_BF527_NAND_D_PORTH)
110#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
111#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
112#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
113#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
114#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
115#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
116#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
117#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
118#endif
119
120#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
121#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
122#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
123#define P_NAND_WE (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
124#define P_NAND_RE (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
125#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
126#define P_NAND_CLE (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
127#define P_NAND_ALE (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
128
129#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
130#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
131#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
132#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
133#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
134#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(2))
135#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
136#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
137#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
138#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(2))
139#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(2))
140#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(2))
141#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(2))
142#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(2))
143#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(2))
144#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(2))
145
146#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
147#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
148#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(1))
149#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(1))
150#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
151#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
152#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
153#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
154#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(1))
155#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(1))
156#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(1))
157#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(1))
158#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(1))
159#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
160#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
161#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
162#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
163#define P_MDIO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
164
165#define P_TWI0_SCL (P_DONTCARE)
166#define P_TWI0_SDA (P_DONTCARE)
167#define P_PPI0_FS1 (P_DONTCARE)
168#define P_TMR0 (P_DONTCARE)
169#define P_TMRCLK (P_DONTCARE)
170#define P_PPI0_CLK (P_DONTCARE)
171
172#define P_MII0 {\
173 P_MII0_ETxD0, \
174 P_MII0_ETxD1, \
175 P_MII0_ETxD2, \
176 P_MII0_ETxD3, \
177 P_MII0_ETxEN, \
178 P_MII0_TxCLK, \
179 P_MII0_PHYINT, \
180 P_MII0_COL, \
181 P_MII0_ERxD0, \
182 P_MII0_ERxD1, \
183 P_MII0_ERxD2, \
184 P_MII0_ERxD3, \
185 P_MII0_ERxDV, \
186 P_MII0_ERxCLK, \
187 P_MII0_ERxER, \
188 P_MII0_CRS, \
189 P_MDC, \
190 P_MDIO, 0}
191
192#define P_RMII0 {\
193 P_MII0_ETxD0, \
194 P_MII0_ETxD1, \
195 P_MII0_ETxEN, \
196 P_MII0_ERxD0, \
197 P_MII0_ERxD1, \
198 P_MII0_ERxER, \
199 P_RMII0_REF_CLK, \
200 P_RMII0_MDINT, \
201 P_RMII0_CRS_DV, \
202 P_MDC, \
203 P_MDIO, 0}
204
205#endif /* _MACH_PORTMUX_H_ */
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