[MIPS] Sibyte: Fix interrupt timer off by one bug.

    
From Dave Johnson <djohnson+linuxmips@sw.starentnetworks.com>:
    
The timers need to be loaded with 1 less than the desired interval not
the interval itself.
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 2 insertions, 2 deletions

diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c
index 511c89d65f38..adc0b5271a06 100644
--- a/arch/mips/sibyte/sb1250/time.c
+++ b/arch/mips/sibyte/sb1250/time.c
@@ -75,10 +75,10 @@ void sb1250_time_init(void)
         /* Disable the timer and set up the count */
         __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
 #ifdef CONFIG_SIMULATION
-        __raw_writeq(50000 / HZ,
+        __raw_writeq((50000 / HZ) - 1,
                      IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
 #else
-        __raw_writeq(1000000 / HZ,
+        __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1,
                      IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
 #endif