diff options
author | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2010-12-03 06:28:21 -0500 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2010-12-29 19:36:52 -0500 |
commit | df3d02962bc39155c8b4214ce6f0e84750c7921f (patch) | |
tree | 4998b0c7750e788b77e0ad50bbdcbebfb7c96f10 | |
parent | 27b31e56239b44608cad176c36c384c0265f8da5 (diff) |
ARM: SAMSUNG: Convert irq-vic-timer to irq_ functions
Conver the VIC timer interrupts to use the irq_ versions of the IRQ
operatiosn introduced in 2.6.37, storing the mask for the timer
interrupt in the chip_data of the irq_data in order to save having to
do a substraction and a shift on every operation.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
-rw-r--r-- | arch/arm/plat-samsung/irq-vic-timer.c | 22 |
1 files changed, 13 insertions, 9 deletions
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c index 0270519fcabc..7ce77ddb729d 100644 --- a/arch/arm/plat-samsung/irq-vic-timer.c +++ b/arch/arm/plat-samsung/irq-vic-timer.c | |||
@@ -29,38 +29,41 @@ static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc) | |||
29 | 29 | ||
30 | /* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ | 30 | /* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ |
31 | 31 | ||
32 | static void s3c_irq_timer_mask(unsigned int irq) | 32 | static void s3c_irq_timer_mask(struct irq_data *data) |
33 | { | 33 | { |
34 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); | 34 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); |
35 | u32 mask = (u32)data->chip_data; | ||
35 | 36 | ||
36 | reg &= 0x1f; /* mask out pending interrupts */ | 37 | reg &= 0x1f; /* mask out pending interrupts */ |
37 | reg &= ~(1 << (irq - IRQ_TIMER0)); | 38 | reg &= ~mask; |
38 | __raw_writel(reg, S3C64XX_TINT_CSTAT); | 39 | __raw_writel(reg, S3C64XX_TINT_CSTAT); |
39 | } | 40 | } |
40 | 41 | ||
41 | static void s3c_irq_timer_unmask(unsigned int irq) | 42 | static void s3c_irq_timer_unmask(struct irq_data *data) |
42 | { | 43 | { |
43 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); | 44 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); |
45 | u32 mask = (u32)data->chip_data; | ||
44 | 46 | ||
45 | reg &= 0x1f; /* mask out pending interrupts */ | 47 | reg &= 0x1f; /* mask out pending interrupts */ |
46 | reg |= 1 << (irq - IRQ_TIMER0); | 48 | reg |= mask; |
47 | __raw_writel(reg, S3C64XX_TINT_CSTAT); | 49 | __raw_writel(reg, S3C64XX_TINT_CSTAT); |
48 | } | 50 | } |
49 | 51 | ||
50 | static void s3c_irq_timer_ack(unsigned int irq) | 52 | static void s3c_irq_timer_ack(struct irq_data *data) |
51 | { | 53 | { |
52 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); | 54 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); |
55 | u32 mask = (u32)data->chip_data; | ||
53 | 56 | ||
54 | reg &= 0x1f; | 57 | reg &= 0x1f; |
55 | reg |= (1 << 5) << (irq - IRQ_TIMER0); | 58 | reg |= mask << 5; |
56 | __raw_writel(reg, S3C64XX_TINT_CSTAT); | 59 | __raw_writel(reg, S3C64XX_TINT_CSTAT); |
57 | } | 60 | } |
58 | 61 | ||
59 | static struct irq_chip s3c_irq_timer = { | 62 | static struct irq_chip s3c_irq_timer = { |
60 | .name = "s3c-timer", | 63 | .name = "s3c-timer", |
61 | .mask = s3c_irq_timer_mask, | 64 | .irq_mask = s3c_irq_timer_mask, |
62 | .unmask = s3c_irq_timer_unmask, | 65 | .irq_unmask = s3c_irq_timer_unmask, |
63 | .ack = s3c_irq_timer_ack, | 66 | .irq_ack = s3c_irq_timer_ack, |
64 | }; | 67 | }; |
65 | 68 | ||
66 | /** | 69 | /** |
@@ -79,6 +82,7 @@ void __init s3c_init_vic_timer_irq(unsigned int parent_irq, | |||
79 | set_irq_chained_handler(parent_irq, s3c_irq_demux_vic_timer); | 82 | set_irq_chained_handler(parent_irq, s3c_irq_demux_vic_timer); |
80 | 83 | ||
81 | set_irq_chip(timer_irq, &s3c_irq_timer); | 84 | set_irq_chip(timer_irq, &s3c_irq_timer); |
85 | set_irq_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0))); | ||
82 | set_irq_handler(timer_irq, handle_level_irq); | 86 | set_irq_handler(timer_irq, handle_level_irq); |
83 | set_irq_flags(timer_irq, IRQF_VALID); | 87 | set_irq_flags(timer_irq, IRQF_VALID); |
84 | 88 | ||