[ARM] 5034/1: fix arm{925,926,940,946} dma_flush_range() in WT mode

The CPU's dma_flush_range() operation needs to clean+invalidate the
given memory area if the cache is in writeback mode, or do just the
invalidate part if the cache is in writethrough mode, but the current
proc-arm{925,926,940,946} (incorrectly) do a cache clean in the
latter case.  This patch fixes that.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

4 files changed, 4 insertions, 4 deletions

diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 065087afb772..d045812f3399 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -332,7 +332,7 @@ ENTRY(arm925_dma_flush_range)
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
         mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 #else
-        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
+        mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
 #endif
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 997db8472b5c..4cd33169a7c9 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -295,7 +295,7 @@ ENTRY(arm926_dma_flush_range)
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
         mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 #else
-        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
+        mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
 #endif
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 44ead902bd54..1a3d63df8e90 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -222,7 +222,7 @@ ENTRY(arm940_dma_flush_range)
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
         mcr     p15, 0, r3, c7, c14, 2          @ clean/flush D entry
 #else
-        mcr     p15, 0, r3, c7, c10, 2          @ clean D entry
+        mcr     p15, 0, r3, c7, c6, 2           @ invalidate D entry
 #endif
         subs    r3, r3, #1 << 26
         bcs     2b                              @ entries 63 to 0
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 2218b0c01330..82d579ac9b98 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -265,7 +265,7 @@ ENTRY(arm946_dma_flush_range)
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
         mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 #else
-        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
+        mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
 #endif
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1