aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorYaniv Rosner <yaniv.rosner@broadcom.com>2010-09-01 05:51:33 -0400
committerDavid S. Miller <davem@davemloft.net>2010-09-01 13:44:34 -0400
commita1e4be39dc5a8d83102b835a3ee049f2a6057be9 (patch)
tree54f41b0277b4876758e8b6a9184edb2c1e810940
parent6f4ca066bc08877647aff2a7d68e36d14d06cb16 (diff)
bnx2x: Change BCM848xx LED configuration
Change 848xx LED configuration according to the new microcode (Boards were shipped with only with the new microcode) Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/bnx2x/bnx2x_link.c171
1 files changed, 49 insertions, 122 deletions
diff --git a/drivers/net/bnx2x/bnx2x_link.c b/drivers/net/bnx2x/bnx2x_link.c
index e2945b4695a8..8fce54cd6ba5 100644
--- a/drivers/net/bnx2x/bnx2x_link.c
+++ b/drivers/net/bnx2x/bnx2x_link.c
@@ -2203,6 +2203,10 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
2203 1<<15); 2203 1<<15);
2204 break; 2204 break;
2205 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: 2205 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
2206 msleep(1);
2207 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
2208 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2209 params->port);
2206 break; 2210 break;
2207 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 2211 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
2208 DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n"); 2212 DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n");
@@ -3477,112 +3481,54 @@ static void bnx2x_set_preemphasis(struct link_params *params)
3477} 3481}
3478 3482
3479 3483
3480static void bnx2x_8481_set_led4(struct link_params *params, 3484static void bnx2x_8481_set_led(struct link_params *params,
3481 u32 ext_phy_type, u8 ext_phy_addr) 3485 u32 ext_phy_type, u8 ext_phy_addr)
3482{
3483 struct bnx2x *bp = params->bp;
3484
3485 /* PHYC_CTL_LED_CTL */
3486 bnx2x_cl45_write(bp, params->port,
3487 ext_phy_type,
3488 ext_phy_addr,
3489 MDIO_PMA_DEVAD,
3490 MDIO_PMA_REG_8481_LINK_SIGNAL, 0xa482);
3491
3492 /* Unmask LED4 for 10G link */
3493 bnx2x_cl45_write(bp, params->port,
3494 ext_phy_type,
3495 ext_phy_addr,
3496 MDIO_PMA_DEVAD,
3497 MDIO_PMA_REG_8481_SIGNAL_MASK, (1<<6));
3498 /* 'Interrupt Mask' */
3499 bnx2x_cl45_write(bp, params->port,
3500 ext_phy_type,
3501 ext_phy_addr,
3502 MDIO_AN_DEVAD,
3503 0xFFFB, 0xFFFD);
3504}
3505static void bnx2x_8481_set_legacy_led_mode(struct link_params *params,
3506 u32 ext_phy_type, u8 ext_phy_addr)
3507{
3508 struct bnx2x *bp = params->bp;
3509
3510 /* LED1 (10G Link): Disable LED1 when 10/100/1000 link */
3511 /* LED2 (1G/100/10 Link): Enable LED2 when 10/100/1000 link) */
3512 bnx2x_cl45_write(bp, params->port,
3513 ext_phy_type,
3514 ext_phy_addr,
3515 MDIO_AN_DEVAD,
3516 MDIO_AN_REG_8481_LEGACY_SHADOW,
3517 (1<<15) | (0xd << 10) | (0xc<<4) | 0xe);
3518}
3519
3520static void bnx2x_8481_set_10G_led_mode(struct link_params *params,
3521 u32 ext_phy_type, u8 ext_phy_addr)
3522{ 3486{
3523 struct bnx2x *bp = params->bp; 3487 struct bnx2x *bp = params->bp;
3524 u16 val1; 3488 u16 val;
3525
3526 /* LED1 (10G Link) */
3527 /* Enable continuse based on source 7(10G-link) */
3528 bnx2x_cl45_read(bp, params->port, 3489 bnx2x_cl45_read(bp, params->port,
3529 ext_phy_type, 3490 ext_phy_type,
3530 ext_phy_addr, 3491 ext_phy_addr,
3531 MDIO_PMA_DEVAD, 3492 MDIO_PMA_DEVAD,
3532 MDIO_PMA_REG_8481_LINK_SIGNAL, 3493 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
3533 &val1); 3494 val &= 0xFE00;
3534 /* Set bit 2 to 0, and bits [1:0] to 10 */ 3495 val |= 0x0092;
3535 val1 &= ~((1<<0) | (1<<2) | (1<<7)); /* Clear bits 0,2,7*/
3536 val1 |= ((1<<1) | (1<<6)); /* Set bit 1, 6 */
3537 3496
3538 bnx2x_cl45_write(bp, params->port, 3497 bnx2x_cl45_write(bp, params->port,
3539 ext_phy_type, 3498 ext_phy_type,
3540 ext_phy_addr, 3499 ext_phy_addr,
3541 MDIO_PMA_DEVAD, 3500 MDIO_PMA_DEVAD,
3542 MDIO_PMA_REG_8481_LINK_SIGNAL, 3501 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
3543 val1);
3544 3502
3545 /* Unmask LED1 for 10G link */
3546 bnx2x_cl45_read(bp, params->port,
3547 ext_phy_type,
3548 ext_phy_addr,
3549 MDIO_PMA_DEVAD,
3550 MDIO_PMA_REG_8481_LED1_MASK,
3551 &val1);
3552 /* Set bit 2 to 0, and bits [1:0] to 10 */
3553 val1 |= (1<<7);
3554 bnx2x_cl45_write(bp, params->port, 3503 bnx2x_cl45_write(bp, params->port,
3555 ext_phy_type, 3504 ext_phy_type,
3556 ext_phy_addr, 3505 ext_phy_addr,
3557 MDIO_PMA_DEVAD, 3506 MDIO_PMA_DEVAD,
3558 MDIO_PMA_REG_8481_LED1_MASK, 3507 MDIO_PMA_REG_8481_LED1_MASK,
3559 val1); 3508 0x80);
3560 3509
3561 /* LED2 (1G/100/10G Link) */
3562 /* Mask LED2 for 10G link */
3563 bnx2x_cl45_write(bp, params->port, 3510 bnx2x_cl45_write(bp, params->port,
3564 ext_phy_type, 3511 ext_phy_type,
3565 ext_phy_addr, 3512 ext_phy_addr,
3566 MDIO_PMA_DEVAD, 3513 MDIO_PMA_DEVAD,
3567 MDIO_PMA_REG_8481_LED2_MASK, 3514 MDIO_PMA_REG_8481_LED2_MASK,
3568 0); 3515 0x18);
3569 3516
3570 /* Unmask LED3 for 10G link */
3571 bnx2x_cl45_write(bp, params->port, 3517 bnx2x_cl45_write(bp, params->port,
3572 ext_phy_type, 3518 ext_phy_type,
3573 ext_phy_addr, 3519 ext_phy_addr,
3574 MDIO_PMA_DEVAD, 3520 MDIO_PMA_DEVAD,
3575 MDIO_PMA_REG_8481_LED3_MASK, 3521 MDIO_PMA_REG_8481_LED3_MASK,
3576 0x6); 3522 0x0040);
3523
3524 /* 'Interrupt Mask' */
3577 bnx2x_cl45_write(bp, params->port, 3525 bnx2x_cl45_write(bp, params->port,
3578 ext_phy_type, 3526 ext_phy_type,
3579 ext_phy_addr, 3527 ext_phy_addr,
3580 MDIO_PMA_DEVAD, 3528 MDIO_AN_DEVAD,
3581 MDIO_PMA_REG_8481_LED3_BLINK, 3529 0xFFFB, 0xFFFD);
3582 0);
3583} 3530}
3584 3531
3585
3586static void bnx2x_init_internal_phy(struct link_params *params, 3532static void bnx2x_init_internal_phy(struct link_params *params,
3587 struct link_vars *vars, 3533 struct link_vars *vars,
3588 u8 enable_cl73) 3534 u8 enable_cl73)
@@ -4358,7 +4304,13 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
4358 indication arrives through its LED4 and not via 4304 indication arrives through its LED4 and not via
4359 its LASI signal, so we get steady signal 4305 its LASI signal, so we get steady signal
4360 instead of clear on read */ 4306 instead of clear on read */
4361 u16 autoneg_val, an_1000_val, an_10_100_val; 4307 u16 autoneg_val, an_1000_val, an_10_100_val, temp;
4308 temp = vars->line_speed;
4309 vars->line_speed = SPEED_10000;
4310 bnx2x_set_autoneg(params, vars, 0);
4311 bnx2x_program_serdes(params, vars);
4312 vars->line_speed = temp;
4313
4362 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, 4314 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
4363 1 << NIG_LATCH_BC_ENABLE_MI_INT); 4315 1 << NIG_LATCH_BC_ENABLE_MI_INT);
4364 4316
@@ -4368,7 +4320,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
4368 MDIO_PMA_DEVAD, 4320 MDIO_PMA_DEVAD,
4369 MDIO_PMA_REG_CTRL, 0x0000); 4321 MDIO_PMA_REG_CTRL, 0x0000);
4370 4322
4371 bnx2x_8481_set_led4(params, ext_phy_type, ext_phy_addr); 4323 bnx2x_8481_set_led(params, ext_phy_type, ext_phy_addr);
4372 4324
4373 bnx2x_cl45_read(bp, params->port, 4325 bnx2x_cl45_read(bp, params->port,
4374 ext_phy_type, 4326 ext_phy_type,
@@ -5184,9 +5136,6 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
5184 if (val2 & (1<<11)) { 5136 if (val2 & (1<<11)) {
5185 vars->line_speed = SPEED_10000; 5137 vars->line_speed = SPEED_10000;
5186 ext_phy_link_up = 1; 5138 ext_phy_link_up = 1;
5187 bnx2x_8481_set_10G_led_mode(params,
5188 ext_phy_type,
5189 ext_phy_addr);
5190 } else { /* Check Legacy speed link */ 5139 } else { /* Check Legacy speed link */
5191 u16 legacy_status, legacy_speed; 5140 u16 legacy_status, legacy_speed;
5192 5141
@@ -5234,9 +5183,6 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
5234 "= %d\n", 5183 "= %d\n",
5235 vars->line_speed, 5184 vars->line_speed,
5236 (vars->duplex == DUPLEX_FULL)); 5185 (vars->duplex == DUPLEX_FULL));
5237 bnx2x_8481_set_legacy_led_mode(params,
5238 ext_phy_type,
5239 ext_phy_addr);
5240 } 5186 }
5241 } 5187 }
5242 break; 5188 break;
@@ -6191,18 +6137,9 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
6191 } 6137 }
6192 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: 6138 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
6193 { 6139 {
6194 u8 ext_phy_addr = 6140 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
6195 XGXS_EXT_PHY_ADDR(params->ext_phy_config); 6141 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6196 bnx2x_cl45_write(bp, port, 6142 params->port);
6197 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
6198 ext_phy_addr,
6199 MDIO_AN_DEVAD,
6200 MDIO_AN_REG_CTRL, 0x0000);
6201 bnx2x_cl45_write(bp, port,
6202 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
6203 ext_phy_addr,
6204 MDIO_PMA_DEVAD,
6205 MDIO_PMA_REG_CTRL, 1);
6206 break; 6143 break;
6207 } 6144 }
6208 default: 6145 default:
@@ -6617,13 +6554,6 @@ static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6617 return 0; 6554 return 0;
6618} 6555}
6619 6556
6620
6621static u8 bnx2x_84823_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6622{
6623 /* HW reset */
6624 bnx2x_ext_phy_hw_reset(bp, 1);
6625 return 0;
6626}
6627u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base) 6557u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6628{ 6558{
6629 u8 rc = 0; 6559 u8 rc = 0;
@@ -6654,9 +6584,6 @@ u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6654 it for single port alone */ 6584 it for single port alone */
6655 rc = bnx2x_8726_common_init_phy(bp, shmem_base); 6585 rc = bnx2x_8726_common_init_phy(bp, shmem_base);
6656 break; 6586 break;
6657 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
6658 rc = bnx2x_84823_common_init_phy(bp, shmem_base);
6659 break;
6660 default: 6587 default:
6661 DP(NETIF_MSG_LINK, 6588 DP(NETIF_MSG_LINK,
6662 "bnx2x_common_init_phy: ext_phy 0x%x not required\n", 6589 "bnx2x_common_init_phy: ext_phy 0x%x not required\n",
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-17 22:21:32 -0500