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authorLinus Torvalds <torvalds@linux-foundation.org>2010-06-04 18:42:09 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-06-04 18:42:09 -0400
commit999fd1ab344dabd9c985b638bf4c29495b8e4619 (patch)
treeb4a238aafc79caa085e469ee28ab61301ca17f8f
parent9a9620db07b27700a4de9e86985735fffb78e2f8 (diff)
parentac422f9443191e050c16fe99baeb5c3d74934589 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (23 commits) sh: Make intc messages consistent via pr_fmt. sh: make sure static declaration on ms7724se sh: make sure static declaration on mach-migor sh: make sure static declaration on mach-ecovec24 sh: make sure static declaration on mach-ap325rxa clocksource: sh_cmt: compute mult and shift before registration clocksource: sh_tmu: compute mult and shift before registration sh: PIO disabling for x3proto and urquell. sh: mach-sdk7786: conditionally disable PIO support. sh: support for platforms without PIO. usb: r8a66597-hcd pio to mmio accessor conversion. usb: gadget: r8a66597-udc pio to mmio accessor conversion. usb: gadget: m66592-udc pio to mmio accessor conversion. sh: add romImage MMCIF boot for sh7724 and Ecovec V2 sh: add boot code to MMCIF driver header sh: prepare MMCIF driver header file sh: allow romImage data between head.S and the zero page sh: Add support MMCIF for ecovec sh: remove duplicated #include input: serio: disable i8042 for non-cayman sh platforms. ...
Diffstat
-rw-r--r--arch/sh/Kconfig16
-rw-r--r--arch/sh/boards/Kconfig3
-rw-r--r--arch/sh/boards/mach-ap325rxa/setup.c2
-rw-r--r--arch/sh/boards/mach-ecovec24/setup.c101
-rw-r--r--arch/sh/boards/mach-migor/setup.c2
-rw-r--r--arch/sh/boards/mach-se/7724/setup.c8
-rw-r--r--arch/sh/boot/romimage/Makefile13
-rw-r--r--arch/sh/boot/romimage/head.S42
-rw-r--r--arch/sh/boot/romimage/mmcif-sh7724.c72
-rw-r--r--arch/sh/boot/romimage/vmlinux.scr2
-rw-r--r--arch/sh/include/asm/io.h8
-rw-r--r--arch/sh/include/asm/machvec.h9
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7724.h1
-rw-r--r--arch/sh/include/mach-common/mach/romimage.h10
-rw-r--r--arch/sh/include/mach-ecovec24/mach/romimage.h27
-rw-r--r--arch/sh/include/mach-kfr2r09/mach/romimage.h10
-rw-r--r--arch/sh/kernel/Makefile3
-rw-r--r--arch/sh/kernel/dwarf.c19
-rw-r--r--arch/sh/kernel/io.c22
-rw-r--r--arch/sh/kernel/io_generic.c20
-rw-r--r--arch/sh/kernel/io_trapped.c4
-rw-r--r--arch/sh/kernel/machvec.c17
-rw-r--r--arch/sh/kernel/return_address.c2
-rw-r--r--drivers/clocksource/sh_cmt.c22
-rw-r--r--drivers/clocksource/sh_tmu.c20
-rw-r--r--drivers/input/serio/Kconfig3
-rw-r--r--drivers/mmc/host/sh_mmcif.c125
-rw-r--r--drivers/sh/intc.c12
-rw-r--r--drivers/usb/gadget/m66592-udc.h22
-rw-r--r--drivers/usb/gadget/r8a66597-udc.c4
-rw-r--r--drivers/usb/gadget/r8a66597-udc.h24
-rw-r--r--drivers/usb/host/r8a66597-hcd.c4
-rw-r--r--drivers/usb/host/r8a66597.h26
-rw-r--r--drivers/video/sh_mobile_lcdcfb.c6
-rw-r--r--include/linux/mmc/sh_mmcif.h161
-rw-r--r--include/linux/serial_sci.h4
36 files changed, 642 insertions, 204 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index c5ee4ce60b57..573fca1fbd9b 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -9,7 +9,7 @@ config SUPERH
9 def_bool y 9 def_bool y
10 select EMBEDDED 10 select EMBEDDED
11 select HAVE_CLK 11 select HAVE_CLK
12 select HAVE_IDE 12 select HAVE_IDE if HAS_IOPORT
13 select HAVE_LMB 13 select HAVE_LMB
14 select HAVE_OPROFILE 14 select HAVE_OPROFILE
15 select HAVE_GENERIC_DMA_COHERENT 15 select HAVE_GENERIC_DMA_COHERENT
@@ -174,6 +174,9 @@ config ARCH_HAS_DEFAULT_IDLE
174config ARCH_HAS_CPU_IDLE_WAIT 174config ARCH_HAS_CPU_IDLE_WAIT
175 def_bool y 175 def_bool y
176 176
177config NO_IOPORT
178 bool
179
177config IO_TRAPPED 180config IO_TRAPPED
178 bool 181 bool
179 182
@@ -776,6 +779,17 @@ config ENTRY_OFFSET
776 default "0x00010000" if PAGE_SIZE_64KB 779 default "0x00010000" if PAGE_SIZE_64KB
777 default "0x00000000" 780 default "0x00000000"
778 781
782config ROMIMAGE_MMCIF
783 bool "Include MMCIF loader in romImage (EXPERIMENTAL)"
784 depends on CPU_SUBTYPE_SH7724 && EXPERIMENTAL
785 help
786 Say Y here to include experimental MMCIF loading code in
787 romImage. With this enabled it is possible to write the romImage
788 kernel image to an MMC card and boot the kernel straight from
789 the reset vector. At reset the processor Mask ROM will load the
790 first part of the romImage which in turn loads the rest the kernel
791 image to RAM using the MMCIF hardware block.
792
779choice 793choice
780 prompt "Kernel command line" 794 prompt "Kernel command line"
781 optional 795 optional
diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig
index 938e87d51482..07b35ca2f644 100644
--- a/arch/sh/boards/Kconfig
+++ b/arch/sh/boards/Kconfig
@@ -154,6 +154,7 @@ config SH_SDK7786
154 bool "SDK7786" 154 bool "SDK7786"
155 depends on CPU_SUBTYPE_SH7786 155 depends on CPU_SUBTYPE_SH7786
156 select SYS_SUPPORTS_PCI 156 select SYS_SUPPORTS_PCI
157 select NO_IOPORT if !PCI
157 help 158 help
158 Select SDK7786 if configuring for a Renesas Technology Europe 159 Select SDK7786 if configuring for a Renesas Technology Europe
159 SH7786-65nm board. 160 SH7786-65nm board.
@@ -190,6 +191,7 @@ config SH_URQUELL
190 depends on CPU_SUBTYPE_SH7786 191 depends on CPU_SUBTYPE_SH7786
191 select ARCH_REQUIRE_GPIOLIB 192 select ARCH_REQUIRE_GPIOLIB
192 select SYS_SUPPORTS_PCI 193 select SYS_SUPPORTS_PCI
194 select NO_IOPORT if !PCI
193 195
194config SH_MIGOR 196config SH_MIGOR
195 bool "Migo-R" 197 bool "Migo-R"
@@ -286,6 +288,7 @@ config SH_LBOX_RE2
286config SH_X3PROTO 288config SH_X3PROTO
287 bool "SH-X3 Prototype board" 289 bool "SH-X3 Prototype board"
288 depends on CPU_SUBTYPE_SHX3 290 depends on CPU_SUBTYPE_SHX3
291 select NO_IOPORT if !PCI
289 292
290config SH_MAGIC_PANEL_R2 293config SH_MAGIC_PANEL_R2
291 bool "Magic Panel R2" 294 bool "Magic Panel R2"
diff --git a/arch/sh/boards/mach-ap325rxa/setup.c b/arch/sh/boards/mach-ap325rxa/setup.c
index 57e37e284208..3a170bd3f3d0 100644
--- a/arch/sh/boards/mach-ap325rxa/setup.c
+++ b/arch/sh/boards/mach-ap325rxa/setup.c
@@ -328,7 +328,7 @@ static struct soc_camera_platform_info camera_info = {
328 .set_capture = camera_set_capture, 328 .set_capture = camera_set_capture,
329}; 329};
330 330
331struct soc_camera_link camera_link = { 331static struct soc_camera_link camera_link = {
332 .bus_id = 0, 332 .bus_id = 0,
333 .add_device = ap325rxa_camera_add, 333 .add_device = ap325rxa_camera_add,
334 .del_device = ap325rxa_camera_del, 334 .del_device = ap325rxa_camera_del,
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
index 49714258732e..be1d114d3a43 100644
--- a/arch/sh/boards/mach-ecovec24/setup.c
+++ b/arch/sh/boards/mach-ecovec24/setup.c
@@ -12,6 +12,8 @@
12#include <linux/device.h> 12#include <linux/device.h>
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/mfd/sh_mobile_sdhi.h> 14#include <linux/mfd/sh_mobile_sdhi.h>
15#include <linux/mmc/host.h>
16#include <linux/mmc/sh_mmcif.h>
15#include <linux/mtd/physmap.h> 17#include <linux/mtd/physmap.h>
16#include <linux/gpio.h> 18#include <linux/gpio.h>
17#include <linux/interrupt.h> 19#include <linux/interrupt.h>
@@ -26,7 +28,6 @@
26#include <linux/mmc/host.h> 28#include <linux/mmc/host.h>
27#include <linux/input.h> 29#include <linux/input.h>
28#include <linux/input/sh_keysc.h> 30#include <linux/input/sh_keysc.h>
29#include <linux/mfd/sh_mobile_sdhi.h>
30#include <video/sh_mobile_lcdc.h> 31#include <video/sh_mobile_lcdc.h>
31#include <sound/sh_fsi.h> 32#include <sound/sh_fsi.h>
32#include <media/sh_mobile_ceu.h> 33#include <media/sh_mobile_ceu.h>
@@ -139,7 +140,7 @@ static struct resource sh_eth_resources[] = {
139 }, 140 },
140}; 141};
141 142
142struct sh_eth_plat_data sh_eth_plat = { 143static struct sh_eth_plat_data sh_eth_plat = {
143 .phy = 0x1f, /* SMSC LAN8700 */ 144 .phy = 0x1f, /* SMSC LAN8700 */
144 .edmac_endian = EDMAC_LITTLE_ENDIAN, 145 .edmac_endian = EDMAC_LITTLE_ENDIAN,
145 .ether_link_active_low = 1 146 .ether_link_active_low = 1
@@ -159,7 +160,7 @@ static struct platform_device sh_eth_device = {
159}; 160};
160 161
161/* USB0 host */ 162/* USB0 host */
162void usb0_port_power(int port, int power) 163static void usb0_port_power(int port, int power)
163{ 164{
164 gpio_set_value(GPIO_PTB4, power); 165 gpio_set_value(GPIO_PTB4, power);
165} 166}
@@ -195,7 +196,7 @@ static struct platform_device usb0_host_device = {
195}; 196};
196 197
197/* USB1 host/function */ 198/* USB1 host/function */
198void usb1_port_power(int port, int power) 199static void usb1_port_power(int port, int power)
199{ 200{
200 gpio_set_value(GPIO_PTB5, power); 201 gpio_set_value(GPIO_PTB5, power);
201} 202}
@@ -421,7 +422,7 @@ static int ts_init(void)
421 return 0; 422 return 0;
422} 423}
423 424
424struct tsc2007_platform_data tsc2007_info = { 425static struct tsc2007_platform_data tsc2007_info = {
425 .model = 2007, 426 .model = 2007,
426 .x_plate_ohms = 180, 427 .x_plate_ohms = 180,
427 .get_pendown_state = ts_get_pendown_state, 428 .get_pendown_state = ts_get_pendown_state,
@@ -436,7 +437,7 @@ static struct i2c_board_info ts_i2c_clients = {
436}; 437};
437 438
438#ifdef CONFIG_MFD_SH_MOBILE_SDHI 439#ifdef CONFIG_MFD_SH_MOBILE_SDHI
439/* SHDI0 */ 440/* SDHI0 */
440static void sdhi0_set_pwr(struct platform_device *pdev, int state) 441static void sdhi0_set_pwr(struct platform_device *pdev, int state)
441{ 442{
442 gpio_set_value(GPIO_PTB6, state); 443 gpio_set_value(GPIO_PTB6, state);
@@ -474,7 +475,8 @@ static struct platform_device sdhi0_device = {
474 }, 475 },
475}; 476};
476 477
477/* SHDI1 */ 478#if !defined(CONFIG_MMC_SH_MMCIF)
479/* SDHI1 */
478static void sdhi1_set_pwr(struct platform_device *pdev, int state) 480static void sdhi1_set_pwr(struct platform_device *pdev, int state)
479{ 481{
480 gpio_set_value(GPIO_PTB7, state); 482 gpio_set_value(GPIO_PTB7, state);
@@ -511,6 +513,7 @@ static struct platform_device sdhi1_device = {
511 .hwblk_id = HWBLK_SDHI1, 513 .hwblk_id = HWBLK_SDHI1,
512 }, 514 },
513}; 515};
516#endif /* CONFIG_MMC_SH_MMCIF */
514 517
515#else 518#else
516 519
@@ -720,7 +723,7 @@ static struct clk fsimckb_clk = {
720 .rate = 0, /* unknown */ 723 .rate = 0, /* unknown */
721}; 724};
722 725
723struct sh_fsi_platform_info fsi_info = { 726static struct sh_fsi_platform_info fsi_info = {
724 .portb_flags = SH_FSI_BRS_INV | 727 .portb_flags = SH_FSI_BRS_INV |
725 SH_FSI_OUT_SLAVE_MODE | 728 SH_FSI_OUT_SLAVE_MODE |
726 SH_FSI_IN_SLAVE_MODE | 729 SH_FSI_IN_SLAVE_MODE |
@@ -777,7 +780,7 @@ static struct platform_device irda_device = {
777#include <media/ak881x.h> 780#include <media/ak881x.h>
778#include <media/sh_vou.h> 781#include <media/sh_vou.h>
779 782
780struct ak881x_pdata ak881x_pdata = { 783static struct ak881x_pdata ak881x_pdata = {
781 .flags = AK881X_IF_MODE_SLAVE, 784 .flags = AK881X_IF_MODE_SLAVE,
782}; 785};
783 786
@@ -786,7 +789,7 @@ static struct i2c_board_info ak8813 = {
786 .platform_data = &ak881x_pdata, 789 .platform_data = &ak881x_pdata,
787}; 790};
788 791
789struct sh_vou_pdata sh_vou_pdata = { 792static struct sh_vou_pdata sh_vou_pdata = {
790 .bus_fmt = SH_VOU_BUS_8BIT, 793 .bus_fmt = SH_VOU_BUS_8BIT,
791 .flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW, 794 .flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW,
792 .board_info = &ak8813, 795 .board_info = &ak8813,
@@ -819,6 +822,58 @@ static struct platform_device vou_device = {
819 }, 822 },
820}; 823};
821 824
825#if defined(CONFIG_MMC_SH_MMCIF)
826/* SH_MMCIF */
827static void mmcif_set_pwr(struct platform_device *pdev, int state)
828{
829 gpio_set_value(GPIO_PTB7, state);
830}
831
832static void mmcif_down_pwr(struct platform_device *pdev)
833{
834 gpio_set_value(GPIO_PTB7, 0);
835}
836
837static struct resource sh_mmcif_resources[] = {
838 [0] = {
839 .name = "SH_MMCIF",
840 .start = 0xA4CA0000,
841 .end = 0xA4CA00FF,
842 .flags = IORESOURCE_MEM,
843 },
844 [1] = {
845 /* MMC2I */
846 .start = 29,
847 .flags = IORESOURCE_IRQ,
848 },
849 [2] = {
850 /* MMC3I */
851 .start = 30,
852 .flags = IORESOURCE_IRQ,
853 },
854};
855
856static struct sh_mmcif_plat_data sh_mmcif_plat = {
857 .set_pwr = mmcif_set_pwr,
858 .down_pwr = mmcif_down_pwr,
859 .sup_pclk = 0, /* SH7724: Max Pclk/2 */
860 .caps = MMC_CAP_4_BIT_DATA |
861 MMC_CAP_8_BIT_DATA |
862 MMC_CAP_NEEDS_POLL,
863 .ocr = MMC_VDD_32_33 | MMC_VDD_33_34,
864};
865
866static struct platform_device sh_mmcif_device = {
867 .name = "sh_mmcif",
868 .id = 0,
869 .dev = {
870 .platform_data = &sh_mmcif_plat,
871 },
872 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
873 .resource = sh_mmcif_resources,
874};
875#endif
876
822static struct platform_device *ecovec_devices[] __initdata = { 877static struct platform_device *ecovec_devices[] __initdata = {
823 &heartbeat_device, 878 &heartbeat_device,
824 &nor_flash_device, 879 &nor_flash_device,
@@ -831,7 +886,9 @@ static struct platform_device *ecovec_devices[] __initdata = {
831 &keysc_device, 886 &keysc_device,
832#ifdef CONFIG_MFD_SH_MOBILE_SDHI 887#ifdef CONFIG_MFD_SH_MOBILE_SDHI
833 &sdhi0_device, 888 &sdhi0_device,
889#if !defined(CONFIG_MMC_SH_MMCIF)
834 &sdhi1_device, 890 &sdhi1_device,
891#endif
835#else 892#else
836 &msiof0_device, 893 &msiof0_device,
837#endif 894#endif
@@ -841,6 +898,9 @@ static struct platform_device *ecovec_devices[] __initdata = {
841 &fsi_device, 898 &fsi_device,
842 &irda_device, 899 &irda_device,
843 &vou_device, 900 &vou_device,
901#if defined(CONFIG_MMC_SH_MMCIF)
902 &sh_mmcif_device,
903#endif
844}; 904};
845 905
846#ifdef CONFIG_I2C 906#ifdef CONFIG_I2C
@@ -1134,6 +1194,7 @@ static int __init arch_setup(void)
1134 gpio_request(GPIO_PTB6, NULL); 1194 gpio_request(GPIO_PTB6, NULL);
1135 gpio_direction_output(GPIO_PTB6, 0); 1195 gpio_direction_output(GPIO_PTB6, 0);
1136 1196
1197#if !defined(CONFIG_MMC_SH_MMCIF)
1137 /* enable SDHI1 on CN12 (needs DS2.6,7 set to ON,OFF) */ 1198 /* enable SDHI1 on CN12 (needs DS2.6,7 set to ON,OFF) */
1138 gpio_request(GPIO_FN_SDHI1CD, NULL); 1199 gpio_request(GPIO_FN_SDHI1CD, NULL);
1139 gpio_request(GPIO_FN_SDHI1WP, NULL); 1200 gpio_request(GPIO_FN_SDHI1WP, NULL);
@@ -1148,6 +1209,7 @@ static int __init arch_setup(void)
1148 1209
1149 /* I/O buffer drive ability is high for SDHI1 */ 1210 /* I/O buffer drive ability is high for SDHI1 */
1150 __raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA); 1211 __raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA);
1212#endif /* CONFIG_MMC_SH_MMCIF */
1151#else 1213#else
1152 /* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */ 1214 /* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */
1153 gpio_request(GPIO_FN_MSIOF0_TXD, NULL); 1215 gpio_request(GPIO_FN_MSIOF0_TXD, NULL);
@@ -1223,6 +1285,25 @@ static int __init arch_setup(void)
1223 gpio_request(GPIO_PTU5, NULL); 1285 gpio_request(GPIO_PTU5, NULL);
1224 gpio_direction_output(GPIO_PTU5, 0); 1286 gpio_direction_output(GPIO_PTU5, 0);
1225 1287
1288#if defined(CONFIG_MMC_SH_MMCIF)
1289 /* enable MMCIF (needs DS2.6,7 set to OFF,ON) */
1290 gpio_request(GPIO_FN_MMC_D7, NULL);
1291 gpio_request(GPIO_FN_MMC_D6, NULL);
1292 gpio_request(GPIO_FN_MMC_D5, NULL);
1293 gpio_request(GPIO_FN_MMC_D4, NULL);
1294 gpio_request(GPIO_FN_MMC_D3, NULL);
1295 gpio_request(GPIO_FN_MMC_D2, NULL);
1296 gpio_request(GPIO_FN_MMC_D1, NULL);
1297 gpio_request(GPIO_FN_MMC_D0, NULL);
1298 gpio_request(GPIO_FN_MMC_CLK, NULL);
1299 gpio_request(GPIO_FN_MMC_CMD, NULL);
1300 gpio_request(GPIO_PTB7, NULL);
1301 gpio_direction_output(GPIO_PTB7, 0);
1302
1303 /* I/O buffer drive ability is high for MMCIF */
1304 __raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA);
1305#endif
1306
1226 /* enable I2C device */ 1307 /* enable I2C device */
1227 i2c_register_board_info(0, i2c0_devices, 1308 i2c_register_board_info(0, i2c0_devices,
1228 ARRAY_SIZE(i2c0_devices)); 1309 ARRAY_SIZE(i2c0_devices));
diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c
index 87185de20446..662debe4ead2 100644
--- a/arch/sh/boards/mach-migor/setup.c
+++ b/arch/sh/boards/mach-migor/setup.c
@@ -181,7 +181,7 @@ static int migor_nand_flash_ready(struct mtd_info *mtd)
181 return gpio_get_value(GPIO_PTA1); /* NAND_RBn */ 181 return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
182} 182}
183 183
184struct platform_nand_data migor_nand_flash_data = { 184static struct platform_nand_data migor_nand_flash_data = {
185 .chip = { 185 .chip = {
186 .nr_chips = 1, 186 .nr_chips = 1,
187 .partitions = migor_nand_flash_partitions, 187 .partitions = migor_nand_flash_partitions,
diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c
index f9b82546c2df..552ebd9ba82b 100644
--- a/arch/sh/boards/mach-se/7724/setup.c
+++ b/arch/sh/boards/mach-se/7724/setup.c
@@ -283,7 +283,7 @@ static struct clk fsimcka_clk = {
283}; 283};
284 284
285/* change J20, J21, J22 pin to 1-2 connection to use slave mode */ 285/* change J20, J21, J22 pin to 1-2 connection to use slave mode */
286struct sh_fsi_platform_info fsi_info = { 286static struct sh_fsi_platform_info fsi_info = {
287 .porta_flags = SH_FSI_BRS_INV | 287 .porta_flags = SH_FSI_BRS_INV |
288 SH_FSI_OUT_SLAVE_MODE | 288 SH_FSI_OUT_SLAVE_MODE |
289 SH_FSI_IN_SLAVE_MODE | 289 SH_FSI_IN_SLAVE_MODE |
@@ -371,7 +371,7 @@ static struct resource sh_eth_resources[] = {
371 }, 371 },
372}; 372};
373 373
374struct sh_eth_plat_data sh_eth_plat = { 374static struct sh_eth_plat_data sh_eth_plat = {
375 .phy = 0x1f, /* SMSC LAN8187 */ 375 .phy = 0x1f, /* SMSC LAN8187 */
376 .edmac_endian = EDMAC_LITTLE_ENDIAN, 376 .edmac_endian = EDMAC_LITTLE_ENDIAN,
377}; 377};
@@ -535,7 +535,7 @@ static struct platform_device irda_device = {
535#include <media/ak881x.h> 535#include <media/ak881x.h>
536#include <media/sh_vou.h> 536#include <media/sh_vou.h>
537 537
538struct ak881x_pdata ak881x_pdata = { 538static struct ak881x_pdata ak881x_pdata = {
539 .flags = AK881X_IF_MODE_SLAVE, 539 .flags = AK881X_IF_MODE_SLAVE,
540}; 540};
541 541
@@ -545,7 +545,7 @@ static struct i2c_board_info ak8813 = {
545 .platform_data = &ak881x_pdata, 545 .platform_data = &ak881x_pdata,
546}; 546};
547 547
548struct sh_vou_pdata sh_vou_pdata = { 548static struct sh_vou_pdata sh_vou_pdata = {
549 .bus_fmt = SH_VOU_BUS_8BIT, 549 .bus_fmt = SH_VOU_BUS_8BIT,
550 .flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW, 550 .flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW,
551 .board_info = &ak8813, 551 .board_info = &ak8813,
diff --git a/arch/sh/boot/romimage/Makefile b/arch/sh/boot/romimage/Makefile
index f473a24a2d92..2216ee57f251 100644
--- a/arch/sh/boot/romimage/Makefile
+++ b/arch/sh/boot/romimage/Makefile
@@ -1,16 +1,21 @@
1# 1#
2# linux/arch/sh/boot/romimage/Makefile 2# linux/arch/sh/boot/romimage/Makefile
3# 3#
4# create an image suitable for burning to flash from zImage 4# create an romImage file suitable for burning to flash/mmc from zImage
5# 5#
6 6
7targets := vmlinux head.o zeropage.bin piggy.o 7targets := vmlinux head.o zeropage.bin piggy.o
8load-y := 0
8 9
9OBJECTS = $(obj)/head.o 10mmcif-load-$(CONFIG_CPU_SUBTYPE_SH7724) := 0xe5200000 # ILRAM
10LDFLAGS_vmlinux := --oformat $(ld-bfd) -Ttext 0 -e romstart \ 11mmcif-obj-$(CONFIG_CPU_SUBTYPE_SH7724) := $(obj)/mmcif-sh7724.o
12load-$(CONFIG_ROMIMAGE_MMCIF) := $(mmcif-load-y)
13obj-$(CONFIG_ROMIMAGE_MMCIF) := $(mmcif-obj-y)
14
15LDFLAGS_vmlinux := --oformat $(ld-bfd) -Ttext $(load-y) -e romstart \
11 -T $(obj)/../../kernel/vmlinux.lds 16 -T $(obj)/../../kernel/vmlinux.lds
12 17
13$(obj)/vmlinux: $(OBJECTS) $(obj)/piggy.o FORCE 18$(obj)/vmlinux: $(obj)/head.o $(obj-y) $(obj)/piggy.o FORCE
14 $(call if_changed,ld) 19 $(call if_changed,ld)
15 @: 20 @:
16 21
diff --git a/arch/sh/boot/romimage/head.S b/arch/sh/boot/romimage/head.S
index 93e779a405ec..4671d1b82150 100644
--- a/arch/sh/boot/romimage/head.S
+++ b/arch/sh/boot/romimage/head.S
@@ -12,8 +12,40 @@ romstart:
12 /* include board specific setup code */ 12 /* include board specific setup code */
13#include <mach/romimage.h> 13#include <mach/romimage.h>
14 14
15#ifdef CONFIG_ROMIMAGE_MMCIF
16 /* load the romImage to above the empty zero page */
17 mov.l empty_zero_page_dst, r4
18 mov.l empty_zero_page_dst_adj, r5
19 add r5, r4
20 mov.l bytes_to_load, r5
21 mov.l loader_function, r7
22 jsr @r7
23 mov r4, r15
24
25 mov.l empty_zero_page_dst, r4
26 mov.l empty_zero_page_dst_adj, r5
27 add r5, r4
28 mov.l loaded_code_offs, r5
29 add r5, r4
30 jmp @r4
31 nop
32
33 .balign 4
34empty_zero_page_dst_adj:
35 .long PAGE_SIZE
36bytes_to_load:
37 .long end_data - romstart
38loader_function:
39 .long mmcif_loader
40loaded_code_offs:
41 .long loaded_code - romstart
42loaded_code:
43#endif /* CONFIG_ROMIMAGE_MMCIF */
44
15 /* copy the empty_zero_page contents to where vmlinux expects it */ 45 /* copy the empty_zero_page contents to where vmlinux expects it */
16 mova empty_zero_page_src, r0 46 mova extra_data_pos, r0
47 mov.l extra_data_size, r1
48 add r1, r0
17 mov.l empty_zero_page_dst, r1 49 mov.l empty_zero_page_dst, r1
18 mov #(PAGE_SHIFT - 4), r4 50 mov #(PAGE_SHIFT - 4), r4
19 mov #1, r3 51 mov #1, r3
@@ -37,7 +69,9 @@ romstart:
37 mov #PAGE_SHIFT, r4 69 mov #PAGE_SHIFT, r4
38 mov #1, r1 70 mov #1, r1
39 shld r4, r1 71 shld r4, r1
40 mova empty_zero_page_src, r0 72 mova extra_data_pos, r0
73 add r1, r0
74 mov.l extra_data_size, r1
41 add r1, r0 75 add r1, r0
42 jmp @r0 76 jmp @r0
43 nop 77 nop
@@ -45,4 +79,6 @@ romstart:
45 .align 2 79 .align 2
46empty_zero_page_dst: 80empty_zero_page_dst:
47 .long _text 81 .long _text
48empty_zero_page_src: 82extra_data_pos:
83extra_data_size:
84 .long zero_page_pos - extra_data_pos
diff --git a/arch/sh/boot/romimage/mmcif-sh7724.c b/arch/sh/boot/romimage/mmcif-sh7724.c
new file mode 100644
index 000000000000..14863d7292cb
--- /dev/null
+++ b/arch/sh/boot/romimage/mmcif-sh7724.c
@@ -0,0 +1,72 @@
1/*
2 * sh7724 MMCIF loader
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/mmc/sh_mmcif.h>
12#include <mach/romimage.h>
13
14#define MMCIF_BASE (void __iomem *)0xa4ca0000
15
16#define MSTPCR2 0xa4150038
17#define PTWCR 0xa4050146
18#define PTXCR 0xa4050148
19#define PSELA 0xa405014e
20#define PSELE 0xa4050156
21#define HIZCRC 0xa405015c
22#define DRVCRA 0xa405018a
23
24enum { MMCIF_PROGRESS_ENTER, MMCIF_PROGRESS_INIT,
25 MMCIF_PROGRESS_LOAD, MMCIF_PROGRESS_DONE };
26
27/* SH7724 specific MMCIF loader
28 *
29 * loads the romImage from an MMC card starting from block 512
30 * use the following line to write the romImage to an MMC card
31 * # dd if=arch/sh/boot/romImage of=/dev/sdx bs=512 seek=512
32 */
33asmlinkage void mmcif_loader(unsigned char *buf, unsigned long no_bytes)
34{
35 mmcif_update_progress(MMCIF_PROGRESS_ENTER);
36
37 /* enable clock to the MMCIF hardware block */
38 __raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2);
39
40 /* setup pins D7-D0 */
41 __raw_writew(0x0000, PTWCR);
42
43 /* setup pins MMC_CLK, MMC_CMD */
44 __raw_writew(__raw_readw(PTXCR) & ~0x000f, PTXCR);
45
46 /* select D3-D0 pin function */
47 __raw_writew(__raw_readw(PSELA) & ~0x2000, PSELA);
48
49 /* select D7-D4 pin function */
50 __raw_writew(__raw_readw(PSELE) & ~0x3000, PSELE);
51
52 /* disable Hi-Z for the MMC pins */
53 __raw_writew(__raw_readw(HIZCRC) & ~0x0620, HIZCRC);
54
55 /* high drive capability for MMC pins */
56 __raw_writew(__raw_readw(DRVCRA) | 0x3000, DRVCRA);
57
58 mmcif_update_progress(MMCIF_PROGRESS_INIT);
59
60 /* setup MMCIF hardware */
61 sh_mmcif_boot_init(MMCIF_BASE);
62
63 mmcif_update_progress(MMCIF_PROGRESS_LOAD);
64
65 /* load kernel via MMCIF interface */
66 sh_mmcif_boot_slurp(MMCIF_BASE, buf, no_bytes);
67
68 /* disable clock to the MMCIF hardware block */
69 __raw_writel(__raw_readl(MSTPCR2) | 0x20000000, MSTPCR2);
70
71 mmcif_update_progress(MMCIF_PROGRESS_DONE);
72}
diff --git a/arch/sh/boot/romimage/vmlinux.scr b/arch/sh/boot/romimage/vmlinux.scr
index 287c08f8b4bb..590394e2f5f2 100644
--- a/arch/sh/boot/romimage/vmlinux.scr
+++ b/arch/sh/boot/romimage/vmlinux.scr
@@ -1,6 +1,8 @@
1SECTIONS 1SECTIONS
2{ 2{
3 .text : { 3 .text : {
4 zero_page_pos = .;
4 *(.data) 5 *(.data)
6 end_data = .;
5 } 7 }
6} 8}
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index f689554e17c1..b237d525d592 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -39,6 +39,8 @@
39#include <asm/io_generic.h> 39#include <asm/io_generic.h>
40#include <asm/io_trapped.h> 40#include <asm/io_trapped.h>
41 41
42#ifdef CONFIG_HAS_IOPORT
43
42#define inb(p) sh_mv.mv_inb((p)) 44#define inb(p) sh_mv.mv_inb((p))
43#define inw(p) sh_mv.mv_inw((p)) 45#define inw(p) sh_mv.mv_inw((p))
44#define inl(p) sh_mv.mv_inl((p)) 46#define inl(p) sh_mv.mv_inl((p))
@@ -60,6 +62,8 @@
60#define outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c)) 62#define outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c))
61#define outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c)) 63#define outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c))
62 64
65#endif
66
63#define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v)) 67#define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v))
64#define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v)) 68#define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
65#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v)) 69#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
@@ -240,6 +244,8 @@ __BUILD_MEMORY_STRING(q, u64)
240 244
241#define IO_SPACE_LIMIT 0xffffffff 245#define IO_SPACE_LIMIT 0xffffffff
242 246
247#ifdef CONFIG_HAS_IOPORT
248
243/* 249/*
244 * This function provides a method for the generic case where a 250 * This function provides a method for the generic case where a
245 * board-specific ioport_map simply needs to return the port + some 251 * board-specific ioport_map simply needs to return the port + some
@@ -255,6 +261,8 @@ static inline void __set_io_port_base(unsigned long pbase)
255 261
256#define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n)) 262#define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n))
257 263
264#endif
265
258/* We really want to try and get these to memcpy etc */ 266/* We really want to try and get these to memcpy etc */
259void memcpy_fromio(void *, const volatile void __iomem *, unsigned long); 267void memcpy_fromio(void *, const volatile void __iomem *, unsigned long);
260void memcpy_toio(volatile void __iomem *, const void *, unsigned long); 268void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
diff --git a/arch/sh/include/asm/machvec.h b/arch/sh/include/asm/machvec.h
index bc0218cb72e1..a0b0cf79cf8a 100644
--- a/arch/sh/include/asm/machvec.h
+++ b/arch/sh/include/asm/machvec.h
@@ -19,6 +19,10 @@ struct sh_machine_vector {
19 const char *mv_name; 19 const char *mv_name;
20 int mv_nr_irqs; 20 int mv_nr_irqs;
21 21
22 int (*mv_irq_demux)(int irq);
23 void (*mv_init_irq)(void);
24
25#ifdef CONFIG_HAS_IOPORT
22 u8 (*mv_inb)(unsigned long); 26 u8 (*mv_inb)(unsigned long);
23 u16 (*mv_inw)(unsigned long); 27 u16 (*mv_inw)(unsigned long);
24 u32 (*mv_inl)(unsigned long); 28 u32 (*mv_inl)(unsigned long);
@@ -40,12 +44,9 @@ struct sh_machine_vector {
40 void (*mv_outsw)(unsigned long, const void *src, unsigned long count); 44 void (*mv_outsw)(unsigned long, const void *src, unsigned long count);
41 void (*mv_outsl)(unsigned long, const void *src, unsigned long count); 45 void (*mv_outsl)(unsigned long, const void *src, unsigned long count);
42 46
43 int (*mv_irq_demux)(int irq);
44
45 void (*mv_init_irq)(void);
46
47 void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size); 47 void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size);
48 void (*mv_ioport_unmap)(void __iomem *); 48 void (*mv_ioport_unmap)(void __iomem *);
49#endif
49 50
50 int (*mv_clk_init)(void); 51 int (*mv_clk_init)(void);
51 int (*mv_mode_pins)(void); 52 int (*mv_mode_pins)(void);
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7724.h b/arch/sh/include/cpu-sh4/cpu/sh7724.h
index fbbf550cc529..4c27b68789b3 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7724.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7724.h
@@ -9,6 +9,7 @@
9 * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10] 9 * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10]
10 * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3] 10 * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
11 * MD8: Test Mode 11 * MD8: Test Mode
12 * BOOT: FBR - Boot Mode (L: MMCIF, H: Area0)
12 */ 13 */
13 14
14/* Pin Function Controller: 15/* Pin Function Controller:
diff --git a/arch/sh/include/mach-common/mach/romimage.h b/arch/sh/include/mach-common/mach/romimage.h
index 267e24112d82..08fb42269ecd 100644
--- a/arch/sh/include/mach-common/mach/romimage.h
+++ b/arch/sh/include/mach-common/mach/romimage.h
@@ -1 +1,11 @@
1#ifdef __ASSEMBLY__
2
1/* do nothing here by default */ 3/* do nothing here by default */
4
5#else /* __ASSEMBLY__ */
6
7extern inline void mmcif_update_progress(int nr)
8{
9}
10
11#endif /* __ASSEMBLY__ */
diff --git a/arch/sh/include/mach-ecovec24/mach/romimage.h b/arch/sh/include/mach-ecovec24/mach/romimage.h
index 1c8787ecb1c1..1dcf5e6c8d83 100644
--- a/arch/sh/include/mach-ecovec24/mach/romimage.h
+++ b/arch/sh/include/mach-ecovec24/mach/romimage.h
@@ -1,3 +1,5 @@
1#ifdef __ASSEMBLY__
2
1/* EcoVec board specific boot code: 3/* EcoVec board specific boot code:
2 * converts the "partner-jet-script.txt" script into assembly 4 * converts the "partner-jet-script.txt" script into assembly
3 * the assembly code is the first code to be executed in the romImage 5 * the assembly code is the first code to be executed in the romImage
@@ -18,3 +20,28 @@
18 .align 2 20 .align 2
191 : .long 0xa8000000 211 : .long 0xa8000000
202 : 222 :
23
24#else /* __ASSEMBLY__ */
25
26/* Ecovec board specific information:
27 *
28 * Set the following to enable MMCIF boot from the MMC card in CN12:
29 *
30 * DS1.5 = OFF (SH BOOT pin set to L)
31 * DS2.6 = OFF (Select MMCIF on CN12 instead of SDHI1)
32 * DS2.7 = ON (Select MMCIF on CN12 instead of SDHI1)
33 *
34 */
35#define HIZCRA 0xa4050158
36#define PGDR 0xa405012c
37
38extern inline void mmcif_update_progress(int nr)
39{
40 /* disable Hi-Z for LED pins */
41 __raw_writew(__raw_readw(HIZCRA) & ~(1 << 1), HIZCRA);
42
43 /* update progress on LED4, LED5, LED6 and LED7 */
44 __raw_writeb(1 << (nr - 1), PGDR);
45}
46
47#endif /* __ASSEMBLY__ */
diff --git a/arch/sh/include/mach-kfr2r09/mach/romimage.h b/arch/sh/include/mach-kfr2r09/mach/romimage.h
index a110823f2bde..976256a323f2 100644
--- a/arch/sh/include/mach-kfr2r09/mach/romimage.h
+++ b/arch/sh/include/mach-kfr2r09/mach/romimage.h
@@ -1,3 +1,5 @@
1#ifdef __ASSEMBLY__
2
1/* kfr2r09 board specific boot code: 3/* kfr2r09 board specific boot code:
2 * converts the "partner-jet-script.txt" script into assembly 4 * converts the "partner-jet-script.txt" script into assembly
3 * the assembly code is the first code to be executed in the romImage 5 * the assembly code is the first code to be executed in the romImage
@@ -18,3 +20,11 @@
18 .align 2 20 .align 2
191: .long 0xa8000000 211: .long 0xa8000000
202: 222:
23
24#else /* __ASSEMBLY__ */
25
26extern inline void mmcif_update_progress(int nr)
27{
28}
29
30#endif /* __ASSEMBLY__ */
diff --git a/arch/sh/kernel/Makefile b/arch/sh/kernel/Makefile
index 650b92f00ee5..e25f3c69525d 100644
--- a/arch/sh/kernel/Makefile
+++ b/arch/sh/kernel/Makefile
@@ -12,7 +12,7 @@ endif
12CFLAGS_REMOVE_return_address.o = -pg 12CFLAGS_REMOVE_return_address.o = -pg
13 13
14obj-y := clkdev.o debugtraps.o dma-nommu.o dumpstack.o \ 14obj-y := clkdev.o debugtraps.o dma-nommu.o dumpstack.o \
15 idle.o io.o io_generic.o irq.o \ 15 idle.o io.o irq.o \
16 irq_$(BITS).o machvec.o nmi_debug.o process.o \ 16 irq_$(BITS).o machvec.o nmi_debug.o process.o \
17 process_$(BITS).o ptrace_$(BITS).o \ 17 process_$(BITS).o ptrace_$(BITS).o \
18 reboot.o return_address.o \ 18 reboot.o return_address.o \
@@ -39,6 +39,7 @@ obj-$(CONFIG_DUMP_CODE) += disassemble.o
39obj-$(CONFIG_HIBERNATION) += swsusp.o 39obj-$(CONFIG_HIBERNATION) += swsusp.o
40obj-$(CONFIG_DWARF_UNWINDER) += dwarf.o 40obj-$(CONFIG_DWARF_UNWINDER) += dwarf.o
41obj-$(CONFIG_PERF_EVENTS) += perf_event.o perf_callchain.o 41obj-$(CONFIG_PERF_EVENTS) += perf_event.o perf_callchain.o
42obj-$(CONFIG_HAS_IOPORT) += io_generic.o
42 43
43obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o 44obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
44obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += localtimer.o 45obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += localtimer.o
diff --git a/arch/sh/kernel/dwarf.c b/arch/sh/kernel/dwarf.c
index 886d7d83ace3..49c09c7d5b77 100644
--- a/arch/sh/kernel/dwarf.c
+++ b/arch/sh/kernel/dwarf.c
@@ -49,6 +49,8 @@ static DEFINE_SPINLOCK(dwarf_fde_lock);
49 49
50static struct dwarf_cie *cached_cie; 50static struct dwarf_cie *cached_cie;
51 51
52static unsigned int dwarf_unwinder_ready;
53
52/** 54/**
53 * dwarf_frame_alloc_reg - allocate memory for a DWARF register 55 * dwarf_frame_alloc_reg - allocate memory for a DWARF register
54 * @frame: the DWARF frame whose list of registers we insert on 56 * @frame: the DWARF frame whose list of registers we insert on
@@ -582,6 +584,13 @@ struct dwarf_frame *dwarf_unwind_stack(unsigned long pc,
582 unsigned long addr; 584 unsigned long addr;
583 585
584 /* 586 /*
587 * If we've been called in to before initialization has
588 * completed, bail out immediately.
589 */
590 if (!dwarf_unwinder_ready)
591 return NULL;
592
593 /*
585 * If we're starting at the top of the stack we need get the 594 * If we're starting at the top of the stack we need get the
586 * contents of a physical register to get the CFA in order to 595 * contents of a physical register to get the CFA in order to
587 * begin the virtual unwinding of the stack. 596 * begin the virtual unwinding of the stack.
@@ -1167,7 +1176,7 @@ void module_dwarf_cleanup(struct module *mod)
1167 */ 1176 */
1168static int __init dwarf_unwinder_init(void) 1177static int __init dwarf_unwinder_init(void)
1169{ 1178{
1170 int err; 1179 int err = -ENOMEM;
1171 1180
1172 dwarf_frame_cachep = kmem_cache_create("dwarf_frames", 1181 dwarf_frame_cachep = kmem_cache_create("dwarf_frames",
1173 sizeof(struct dwarf_frame), 0, 1182 sizeof(struct dwarf_frame), 0,
@@ -1181,11 +1190,15 @@ static int __init dwarf_unwinder_init(void)
1181 mempool_alloc_slab, 1190 mempool_alloc_slab,
1182 mempool_free_slab, 1191 mempool_free_slab,
1183 dwarf_frame_cachep); 1192 dwarf_frame_cachep);
1193 if (!dwarf_frame_pool)
1194 goto out;
1184 1195
1185 dwarf_reg_pool = mempool_create(DWARF_REG_MIN_REQ, 1196 dwarf_reg_pool = mempool_create(DWARF_REG_MIN_REQ,
1186 mempool_alloc_slab, 1197 mempool_alloc_slab,
1187 mempool_free_slab, 1198 mempool_free_slab,
1188 dwarf_reg_cachep); 1199 dwarf_reg_cachep);
1200 if (!dwarf_reg_pool)
1201 goto out;
1189 1202
1190 err = dwarf_parse_section(__start_eh_frame, __stop_eh_frame, NULL); 1203 err = dwarf_parse_section(__start_eh_frame, __stop_eh_frame, NULL);
1191 if (err) 1204 if (err)
@@ -1195,11 +1208,13 @@ static int __init dwarf_unwinder_init(void)
1195 if (err) 1208 if (err)
1196 goto out; 1209 goto out;
1197 1210
1211 dwarf_unwinder_ready = 1;
1212
1198 return 0; 1213 return 0;
1199 1214
1200out: 1215out:
1201 printk(KERN_ERR "Failed to initialise DWARF unwinder: %d\n", err); 1216 printk(KERN_ERR "Failed to initialise DWARF unwinder: %d\n", err);
1202 dwarf_unwinder_cleanup(); 1217 dwarf_unwinder_cleanup();
1203 return -EINVAL; 1218 return err;
1204} 1219}
1205early_initcall(dwarf_unwinder_init); 1220early_initcall(dwarf_unwinder_init);
diff --git a/arch/sh/kernel/io.c b/arch/sh/kernel/io.c
index 4770c241c679..5c51b794ba2a 100644
--- a/arch/sh/kernel/io.c
+++ b/arch/sh/kernel/io.c
@@ -112,25 +112,3 @@ void memset_io(volatile void __iomem *dst, int c, unsigned long count)
112 } 112 }
113} 113}
114EXPORT_SYMBOL(memset_io); 114EXPORT_SYMBOL(memset_io);
115
116#ifndef CONFIG_GENERIC_IOMAP
117
118void __iomem *ioport_map(unsigned long port, unsigned int nr)
119{
120 void __iomem *ret;
121
122 ret = __ioport_map_trapped(port, nr);
123 if (ret)
124 return ret;
125
126 return __ioport_map(port, nr);
127}
128EXPORT_SYMBOL(ioport_map);
129
130void ioport_unmap(void __iomem *addr)
131{
132 sh_mv.mv_ioport_unmap(addr);
133}
134EXPORT_SYMBOL(ioport_unmap);
135
136#endif /* CONFIG_GENERIC_IOMAP */
diff --git a/arch/sh/kernel/io_generic.c b/arch/sh/kernel/io_generic.c
index e1e1dbd19557..447d78f666f9 100644
--- a/arch/sh/kernel/io_generic.c
+++ b/arch/sh/kernel/io_generic.c
@@ -158,3 +158,23 @@ void __iomem *generic_ioport_map(unsigned long addr, unsigned int size)
158void generic_ioport_unmap(void __iomem *addr) 158void generic_ioport_unmap(void __iomem *addr)
159{ 159{
160} 160}
161
162#ifndef CONFIG_GENERIC_IOMAP
163void __iomem *ioport_map(unsigned long port, unsigned int nr)
164{
165 void __iomem *ret;
166
167 ret = __ioport_map_trapped(port, nr);
168 if (ret)
169 return ret;
170
171 return __ioport_map(port, nr);
172}
173EXPORT_SYMBOL(ioport_map);
174
175void ioport_unmap(void __iomem *addr)
176{
177 sh_mv.mv_ioport_unmap(addr);
178}
179EXPORT_SYMBOL(ioport_unmap);
180#endif /* CONFIG_GENERIC_IOMAP */
diff --git a/arch/sh/kernel/io_trapped.c b/arch/sh/kernel/io_trapped.c
index 4a8bb4eeb8ad..2947d2bd1291 100644
--- a/arch/sh/kernel/io_trapped.c
+++ b/arch/sh/kernel/io_trapped.c
@@ -91,10 +91,14 @@ int register_trapped_io(struct trapped_io *tiop)
91 tiop->magic = IO_TRAPPED_MAGIC; 91 tiop->magic = IO_TRAPPED_MAGIC;
92 INIT_LIST_HEAD(&tiop->list); 92 INIT_LIST_HEAD(&tiop->list);
93 spin_lock_irq(&trapped_lock); 93 spin_lock_irq(&trapped_lock);
94#ifdef CONFIG_HAS_IOPORT
94 if (flags & IORESOURCE_IO) 95 if (flags & IORESOURCE_IO)
95 list_add(&tiop->list, &trapped_io); 96 list_add(&tiop->list, &trapped_io);
97#endif
98#ifdef CONFIG_HAS_IOMEM
96 if (flags & IORESOURCE_MEM) 99 if (flags & IORESOURCE_MEM)
97 list_add(&tiop->list, &trapped_mem); 100 list_add(&tiop->list, &trapped_mem);
101#endif
98 spin_unlock_irq(&trapped_lock); 102 spin_unlock_irq(&trapped_lock);
99 103
100 return 0; 104 return 0;
diff --git a/arch/sh/kernel/machvec.c b/arch/sh/kernel/machvec.c
index 85cfaf916fdc..9f9bb63616ad 100644
--- a/arch/sh/kernel/machvec.c
+++ b/arch/sh/kernel/machvec.c
@@ -118,6 +118,14 @@ void __init sh_mv_setup(void)
118 sh_mv.mv_##elem = generic_##elem; \ 118 sh_mv.mv_##elem = generic_##elem; \
119} while (0) 119} while (0)
120 120
121#ifdef CONFIG_HAS_IOPORT
122
123#ifdef P2SEG
124 __set_io_port_base(P2SEG);
125#else
126 __set_io_port_base(0);
127#endif
128
121 mv_set(inb); mv_set(inw); mv_set(inl); 129 mv_set(inb); mv_set(inw); mv_set(inl);
122 mv_set(outb); mv_set(outw); mv_set(outl); 130 mv_set(outb); mv_set(outw); mv_set(outl);
123 131
@@ -129,16 +137,13 @@ void __init sh_mv_setup(void)
129 137
130 mv_set(ioport_map); 138 mv_set(ioport_map);
131 mv_set(ioport_unmap); 139 mv_set(ioport_unmap);
140
141#endif
142
132 mv_set(irq_demux); 143 mv_set(irq_demux);
133 mv_set(mode_pins); 144 mv_set(mode_pins);
134 mv_set(mem_init); 145 mv_set(mem_init);
135 146
136 if (!sh_mv.mv_nr_irqs) 147 if (!sh_mv.mv_nr_irqs)
137 sh_mv.mv_nr_irqs = NR_IRQS; 148 sh_mv.mv_nr_irqs = NR_IRQS;
138
139#ifdef P2SEG
140 __set_io_port_base(P2SEG);
141#else
142 __set_io_port_base(0);
143#endif
144} 149}
diff --git a/arch/sh/kernel/return_address.c b/arch/sh/kernel/return_address.c
index cbf1dd5372b2..5124aeb28c3f 100644
--- a/arch/sh/kernel/return_address.c
+++ b/arch/sh/kernel/return_address.c
@@ -24,6 +24,8 @@ void *return_address(unsigned int depth)
24 struct dwarf_frame *tmp; 24 struct dwarf_frame *tmp;
25 25
26 tmp = dwarf_unwind_stack(ra, frame); 26 tmp = dwarf_unwind_stack(ra, frame);
27 if (!tmp)
28 return NULL;
27 29
28 if (frame) 30 if (frame)
29 dwarf_free_frame(frame); 31 dwarf_free_frame(frame);
diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
index f6677cb19789..f3d3898898ed 100644
--- a/drivers/clocksource/sh_cmt.c
+++ b/drivers/clocksource/sh_cmt.c
@@ -412,18 +412,10 @@ static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
412static int sh_cmt_clocksource_enable(struct clocksource *cs) 412static int sh_cmt_clocksource_enable(struct clocksource *cs)
413{ 413{
414 struct sh_cmt_priv *p = cs_to_sh_cmt(cs); 414 struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
415 int ret;
416 415
417 p->total_cycles = 0; 416 p->total_cycles = 0;
418 417
419 ret = sh_cmt_start(p, FLAG_CLOCKSOURCE); 418 return sh_cmt_start(p, FLAG_CLOCKSOURCE);
420 if (ret)
421 return ret;
422
423 /* TODO: calculate good shift from rate and counter bit width */
424 cs->shift = 0;
425 cs->mult = clocksource_hz2mult(p->rate, cs->shift);
426 return 0;
427} 419}
428 420
429static void sh_cmt_clocksource_disable(struct clocksource *cs) 421static void sh_cmt_clocksource_disable(struct clocksource *cs)
@@ -450,8 +442,20 @@ static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
450 cs->resume = sh_cmt_clocksource_resume; 442 cs->resume = sh_cmt_clocksource_resume;
451 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8); 443 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
452 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; 444 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
445
446 /* clk_get_rate() needs an enabled clock */
447 clk_enable(p->clk);
448 p->rate = clk_get_rate(p->clk) / (p->width == 16) ? 512 : 8;
449 clk_disable(p->clk);
450
451 /* TODO: calculate good shift from rate and counter bit width */
452 cs->shift = 10;
453 cs->mult = clocksource_hz2mult(p->rate, cs->shift);
454
453 dev_info(&p->pdev->dev, "used as clock source\n"); 455 dev_info(&p->pdev->dev, "used as clock source\n");
456
454 clocksource_register(cs); 457 clocksource_register(cs);
458
455 return 0; 459 return 0;
456} 460}
457 461
diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c
index 8e44e14ec4c2..de715901b82a 100644
--- a/drivers/clocksource/sh_tmu.c
+++ b/drivers/clocksource/sh_tmu.c
@@ -199,16 +199,8 @@ static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
199static int sh_tmu_clocksource_enable(struct clocksource *cs) 199static int sh_tmu_clocksource_enable(struct clocksource *cs)
200{ 200{
201 struct sh_tmu_priv *p = cs_to_sh_tmu(cs); 201 struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
202 int ret;
203
204 ret = sh_tmu_enable(p);
205 if (ret)
206 return ret;
207 202
208 /* TODO: calculate good shift from rate and counter bit width */ 203 return sh_tmu_enable(p);
209 cs->shift = 10;
210 cs->mult = clocksource_hz2mult(p->rate, cs->shift);
211 return 0;
212} 204}
213 205
214static void sh_tmu_clocksource_disable(struct clocksource *cs) 206static void sh_tmu_clocksource_disable(struct clocksource *cs)
@@ -228,6 +220,16 @@ static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
228 cs->disable = sh_tmu_clocksource_disable; 220 cs->disable = sh_tmu_clocksource_disable;
229 cs->mask = CLOCKSOURCE_MASK(32); 221 cs->mask = CLOCKSOURCE_MASK(32);
230 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; 222 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
223
224 /* clk_get_rate() needs an enabled clock */
225 clk_enable(p->clk);
226 /* channel will be configured at parent clock / 4 */
227 p->rate = clk_get_rate(p->clk) / 4;
228 clk_disable(p->clk);
229 /* TODO: calculate good shift from rate and counter bit width */
230 cs->shift = 10;
231 cs->mult = clocksource_hz2mult(p->rate, cs->shift);
232
231 dev_info(&p->pdev->dev, "used as clock source\n"); 233 dev_info(&p->pdev->dev, "used as clock source\n");
232 clocksource_register(cs); 234 clocksource_register(cs);
233 return 0; 235 return 0;
diff --git a/drivers/input/serio/Kconfig b/drivers/input/serio/Kconfig
index f34f1dbeb577..3bfe8fafc6ad 100644
--- a/drivers/input/serio/Kconfig
+++ b/drivers/input/serio/Kconfig
@@ -21,7 +21,8 @@ if SERIO
21config SERIO_I8042 21config SERIO_I8042
22 tristate "i8042 PC Keyboard controller" if EMBEDDED || !X86 22 tristate "i8042 PC Keyboard controller" if EMBEDDED || !X86
23 default y 23 default y
24 depends on !PARISC && (!ARM || ARCH_SHARK || FOOTBRIDGE_HOST) && !M68K && !BLACKFIN 24 depends on !PARISC && (!ARM || ARCH_SHARK || FOOTBRIDGE_HOST) && \
25 (!SUPERH || SH_CAYMAN) && !M68K && !BLACKFIN
25 help 26 help
26 i8042 is the chip over which the standard AT keyboard and PS/2 27 i8042 is the chip over which the standard AT keyboard and PS/2
27 mouse are connected to the computer. If you use these devices, 28 mouse are connected to the computer. If you use these devices,
diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c
index eb97830c0344..5d3f824bb5a3 100644
--- a/drivers/mmc/host/sh_mmcif.c
+++ b/drivers/mmc/host/sh_mmcif.c
@@ -30,25 +30,6 @@
30#define DRIVER_NAME "sh_mmcif" 30#define DRIVER_NAME "sh_mmcif"
31#define DRIVER_VERSION "2010-04-28" 31#define DRIVER_VERSION "2010-04-28"
32 32
33#define MMCIF_CE_CMD_SET 0x00000000
34#define MMCIF_CE_ARG 0x00000008
35#define MMCIF_CE_ARG_CMD12 0x0000000C
36#define MMCIF_CE_CMD_CTRL 0x00000010
37#define MMCIF_CE_BLOCK_SET 0x00000014
38#define MMCIF_CE_CLK_CTRL 0x00000018
39#define MMCIF_CE_BUF_ACC 0x0000001C
40#define MMCIF_CE_RESP3 0x00000020
41#define MMCIF_CE_RESP2 0x00000024
42#define MMCIF_CE_RESP1 0x00000028
43#define MMCIF_CE_RESP0 0x0000002C
44#define MMCIF_CE_RESP_CMD12 0x00000030
45#define MMCIF_CE_DATA 0x00000034
46#define MMCIF_CE_INT 0x00000040
47#define MMCIF_CE_INT_MASK 0x00000044
48#define MMCIF_CE_HOST_STS1 0x00000048
49#define MMCIF_CE_HOST_STS2 0x0000004C
50#define MMCIF_CE_VERSION 0x0000007C
51
52/* CE_CMD_SET */ 33/* CE_CMD_SET */
53#define CMD_MASK 0x3f000000 34#define CMD_MASK 0x3f000000
54#define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) 35#define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
@@ -207,27 +188,17 @@ struct sh_mmcif_host {
207 wait_queue_head_t intr_wait; 188 wait_queue_head_t intr_wait;
208}; 189};
209 190
210static inline u32 sh_mmcif_readl(struct sh_mmcif_host *host, unsigned int reg)
211{
212 return readl(host->addr + reg);
213}
214
215static inline void sh_mmcif_writel(struct sh_mmcif_host *host,
216 unsigned int reg, u32 val)
217{
218 writel(val, host->addr + reg);
219}
220 191
221static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, 192static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
222 unsigned int reg, u32 val) 193 unsigned int reg, u32 val)
223{ 194{
224 writel(val | sh_mmcif_readl(host, reg), host->addr + reg); 195 writel(val | readl(host->addr + reg), host->addr + reg);
225} 196}
226 197
227static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, 198static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
228 unsigned int reg, u32 val) 199 unsigned int reg, u32 val)
229{ 200{
230 writel(~val & sh_mmcif_readl(host, reg), host->addr + reg); 201 writel(~val & readl(host->addr + reg), host->addr + reg);
231} 202}
232 203
233 204
@@ -253,10 +224,10 @@ static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
253{ 224{
254 u32 tmp; 225 u32 tmp;
255 226
256 tmp = 0x010f0000 & sh_mmcif_readl(host, MMCIF_CE_CLK_CTRL); 227 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
257 228
258 sh_mmcif_writel(host, MMCIF_CE_VERSION, SOFT_RST_ON); 229 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
259 sh_mmcif_writel(host, MMCIF_CE_VERSION, SOFT_RST_OFF); 230 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
260 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | 231 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
261 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); 232 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
262 /* byte swap on */ 233 /* byte swap on */
@@ -271,12 +242,10 @@ static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
271 host->sd_error = 0; 242 host->sd_error = 0;
272 host->wait_int = 0; 243 host->wait_int = 0;
273 244
274 state1 = sh_mmcif_readl(host, MMCIF_CE_HOST_STS1); 245 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
275 state2 = sh_mmcif_readl(host, MMCIF_CE_HOST_STS2); 246 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
276 pr_debug("%s: ERR HOST_STS1 = %08x\n", \ 247 pr_debug("%s: ERR HOST_STS1 = %08x\n", DRIVER_NAME, state1);
277 DRIVER_NAME, sh_mmcif_readl(host, MMCIF_CE_HOST_STS1)); 248 pr_debug("%s: ERR HOST_STS2 = %08x\n", DRIVER_NAME, state2);
278 pr_debug("%s: ERR HOST_STS2 = %08x\n", \
279 DRIVER_NAME, sh_mmcif_readl(host, MMCIF_CE_HOST_STS2));
280 249
281 if (state1 & STS1_CMDSEQ) { 250 if (state1 & STS1_CMDSEQ) {
282 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 251 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
@@ -288,7 +257,7 @@ static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
288 "command sequence timeout err\n"); 257 "command sequence timeout err\n");
289 return -EIO; 258 return -EIO;
290 } 259 }
291 if (!(sh_mmcif_readl(host, MMCIF_CE_HOST_STS1) 260 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
292 & STS1_CMDSEQ)) 261 & STS1_CMDSEQ))
293 break; 262 break;
294 mdelay(1); 263 mdelay(1);
@@ -330,9 +299,9 @@ static int sh_mmcif_single_read(struct sh_mmcif_host *host,
330 299
331 host->wait_int = 0; 300 host->wait_int = 0;
332 blocksize = (BLOCK_SIZE_MASK & 301 blocksize = (BLOCK_SIZE_MASK &
333 sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET)) + 3; 302 sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
334 for (i = 0; i < blocksize / 4; i++) 303 for (i = 0; i < blocksize / 4; i++)
335 *p++ = sh_mmcif_readl(host, MMCIF_CE_DATA); 304 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
336 305
337 /* buffer read end */ 306 /* buffer read end */
338 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 307 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
@@ -353,7 +322,8 @@ static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
353 long time; 322 long time;
354 u32 blocksize, i, j, sec, *p; 323 u32 blocksize, i, j, sec, *p;
355 324
356 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET); 325 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
326 MMCIF_CE_BLOCK_SET);
357 for (j = 0; j < data->sg_len; j++) { 327 for (j = 0; j < data->sg_len; j++) {
358 p = sg_virt(data->sg); 328 p = sg_virt(data->sg);
359 host->wait_int = 0; 329 host->wait_int = 0;
@@ -370,7 +340,8 @@ static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
370 340
371 host->wait_int = 0; 341 host->wait_int = 0;
372 for (i = 0; i < blocksize / 4; i++) 342 for (i = 0; i < blocksize / 4; i++)
373 *p++ = sh_mmcif_readl(host, MMCIF_CE_DATA); 343 *p++ = sh_mmcif_readl(host->addr,
344 MMCIF_CE_DATA);
374 } 345 }
375 if (j < data->sg_len - 1) 346 if (j < data->sg_len - 1)
376 data->sg++; 347 data->sg++;
@@ -397,9 +368,9 @@ static int sh_mmcif_single_write(struct sh_mmcif_host *host,
397 368
398 host->wait_int = 0; 369 host->wait_int = 0;
399 blocksize = (BLOCK_SIZE_MASK & 370 blocksize = (BLOCK_SIZE_MASK &
400 sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET)) + 3; 371 sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
401 for (i = 0; i < blocksize / 4; i++) 372 for (i = 0; i < blocksize / 4; i++)
402 sh_mmcif_writel(host, MMCIF_CE_DATA, *p++); 373 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
403 374
404 /* buffer write end */ 375 /* buffer write end */
405 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 376 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
@@ -421,7 +392,8 @@ static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
421 long time; 392 long time;
422 u32 i, sec, j, blocksize, *p; 393 u32 i, sec, j, blocksize, *p;
423 394
424 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET); 395 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
396 MMCIF_CE_BLOCK_SET);
425 397
426 for (j = 0; j < data->sg_len; j++) { 398 for (j = 0; j < data->sg_len; j++) {
427 p = sg_virt(data->sg); 399 p = sg_virt(data->sg);
@@ -439,7 +411,8 @@ static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
439 411
440 host->wait_int = 0; 412 host->wait_int = 0;
441 for (i = 0; i < blocksize / 4; i++) 413 for (i = 0; i < blocksize / 4; i++)
442 sh_mmcif_writel(host, MMCIF_CE_DATA, *p++); 414 sh_mmcif_writel(host->addr,
415 MMCIF_CE_DATA, *p++);
443 } 416 }
444 if (j < data->sg_len - 1) 417 if (j < data->sg_len - 1)
445 data->sg++; 418 data->sg++;
@@ -451,18 +424,18 @@ static void sh_mmcif_get_response(struct sh_mmcif_host *host,
451 struct mmc_command *cmd) 424 struct mmc_command *cmd)
452{ 425{
453 if (cmd->flags & MMC_RSP_136) { 426 if (cmd->flags & MMC_RSP_136) {
454 cmd->resp[0] = sh_mmcif_readl(host, MMCIF_CE_RESP3); 427 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
455 cmd->resp[1] = sh_mmcif_readl(host, MMCIF_CE_RESP2); 428 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
456 cmd->resp[2] = sh_mmcif_readl(host, MMCIF_CE_RESP1); 429 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
457 cmd->resp[3] = sh_mmcif_readl(host, MMCIF_CE_RESP0); 430 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
458 } else 431 } else
459 cmd->resp[0] = sh_mmcif_readl(host, MMCIF_CE_RESP0); 432 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
460} 433}
461 434
462static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 435static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
463 struct mmc_command *cmd) 436 struct mmc_command *cmd)
464{ 437{
465 cmd->resp[0] = sh_mmcif_readl(host, MMCIF_CE_RESP_CMD12); 438 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
466} 439}
467 440
468static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 441static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
@@ -596,18 +569,19 @@ static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
596 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO; 569 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
597 570
598 if (host->data) { 571 if (host->data) {
599 sh_mmcif_writel(host, MMCIF_CE_BLOCK_SET, 0); 572 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
600 sh_mmcif_writel(host, MMCIF_CE_BLOCK_SET, mrq->data->blksz); 573 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
574 mrq->data->blksz);
601 } 575 }
602 opc = sh_mmcif_set_cmd(host, mrq, cmd, opc); 576 opc = sh_mmcif_set_cmd(host, mrq, cmd, opc);
603 577
604 sh_mmcif_writel(host, MMCIF_CE_INT, 0xD80430C0); 578 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
605 sh_mmcif_writel(host, MMCIF_CE_INT_MASK, mask); 579 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
606 /* set arg */ 580 /* set arg */
607 sh_mmcif_writel(host, MMCIF_CE_ARG, cmd->arg); 581 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
608 host->wait_int = 0; 582 host->wait_int = 0;
609 /* set cmd */ 583 /* set cmd */
610 sh_mmcif_writel(host, MMCIF_CE_CMD_SET, opc); 584 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
611 585
612 time = wait_event_interruptible_timeout(host->intr_wait, 586 time = wait_event_interruptible_timeout(host->intr_wait,
613 host->wait_int == 1 || host->sd_error == 1, host->timeout); 587 host->wait_int == 1 || host->sd_error == 1, host->timeout);
@@ -752,43 +726,44 @@ static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
752 u32 state = 0; 726 u32 state = 0;
753 int err = 0; 727 int err = 0;
754 728
755 state = sh_mmcif_readl(host, MMCIF_CE_INT); 729 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
756 730
757 if (state & INT_RBSYE) { 731 if (state & INT_RBSYE) {
758 sh_mmcif_writel(host, MMCIF_CE_INT, ~(INT_RBSYE | INT_CRSPE)); 732 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
733 ~(INT_RBSYE | INT_CRSPE));
759 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE); 734 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
760 } else if (state & INT_CRSPE) { 735 } else if (state & INT_CRSPE) {
761 sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_CRSPE); 736 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
762 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE); 737 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
763 } else if (state & INT_BUFREN) { 738 } else if (state & INT_BUFREN) {
764 sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_BUFREN); 739 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
765 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 740 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
766 } else if (state & INT_BUFWEN) { 741 } else if (state & INT_BUFWEN) {
767 sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_BUFWEN); 742 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
768 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 743 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
769 } else if (state & INT_CMD12DRE) { 744 } else if (state & INT_CMD12DRE) {
770 sh_mmcif_writel(host, MMCIF_CE_INT, 745 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
771 ~(INT_CMD12DRE | INT_CMD12RBE | 746 ~(INT_CMD12DRE | INT_CMD12RBE |
772 INT_CMD12CRE | INT_BUFRE)); 747 INT_CMD12CRE | INT_BUFRE));
773 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 748 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
774 } else if (state & INT_BUFRE) { 749 } else if (state & INT_BUFRE) {
775 sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_BUFRE); 750 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
776 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 751 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
777 } else if (state & INT_DTRANE) { 752 } else if (state & INT_DTRANE) {
778 sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_DTRANE); 753 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE);
779 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 754 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
780 } else if (state & INT_CMD12RBE) { 755 } else if (state & INT_CMD12RBE) {
781 sh_mmcif_writel(host, MMCIF_CE_INT, 756 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
782 ~(INT_CMD12RBE | INT_CMD12CRE)); 757 ~(INT_CMD12RBE | INT_CMD12CRE));
783 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 758 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
784 } else if (state & INT_ERR_STS) { 759 } else if (state & INT_ERR_STS) {
785 /* err interrupts */ 760 /* err interrupts */
786 sh_mmcif_writel(host, MMCIF_CE_INT, ~state); 761 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
787 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 762 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
788 err = 1; 763 err = 1;
789 } else { 764 } else {
790 pr_debug("%s: Not support int\n", DRIVER_NAME); 765 pr_debug("%s: Not support int\n", DRIVER_NAME);
791 sh_mmcif_writel(host, MMCIF_CE_INT, ~state); 766 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
792 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 767 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
793 err = 1; 768 err = 1;
794 } 769 }
@@ -894,12 +869,12 @@ static int __devinit sh_mmcif_probe(struct platform_device *pdev)
894 goto clean_up2; 869 goto clean_up2;
895 } 870 }
896 871
897 sh_mmcif_writel(host, MMCIF_CE_INT_MASK, MASK_ALL); 872 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
898 sh_mmcif_detect(host->mmc); 873 sh_mmcif_detect(host->mmc);
899 874
900 pr_info("%s: driver version %s\n", DRIVER_NAME, DRIVER_VERSION); 875 pr_info("%s: driver version %s\n", DRIVER_NAME, DRIVER_VERSION);
901 pr_debug("%s: chip ver H'%04x\n", DRIVER_NAME, 876 pr_debug("%s: chip ver H'%04x\n", DRIVER_NAME,
902 sh_mmcif_readl(host, MMCIF_CE_VERSION) & 0x0000ffff); 877 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
903 return ret; 878 return ret;
904 879
905clean_up2: 880clean_up2:
@@ -917,7 +892,7 @@ static int __devexit sh_mmcif_remove(struct platform_device *pdev)
917 struct sh_mmcif_host *host = platform_get_drvdata(pdev); 892 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
918 int irq[2]; 893 int irq[2];
919 894
920 sh_mmcif_writel(host, MMCIF_CE_INT_MASK, MASK_ALL); 895 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
921 896
922 irq[0] = platform_get_irq(pdev, 0); 897 irq[0] = platform_get_irq(pdev, 0);
923 irq[1] = platform_get_irq(pdev, 1); 898 irq[1] = platform_get_irq(pdev, 1);
diff --git a/drivers/sh/intc.c b/drivers/sh/intc.c
index c585574b9aed..e91a23e5ffd8 100644
--- a/drivers/sh/intc.c
+++ b/drivers/sh/intc.c
@@ -16,6 +16,8 @@
16 * License. See the file "COPYING" in the main directory of this archive 16 * License. See the file "COPYING" in the main directory of this archive
17 * for more details. 17 * for more details.
18 */ 18 */
19#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
19#include <linux/init.h> 21#include <linux/init.h>
20#include <linux/irq.h> 22#include <linux/irq.h>
21#include <linux/module.h> 23#include <linux/module.h>
@@ -855,8 +857,8 @@ static void __init intc_register_irq(struct intc_desc *desc,
855 primary = 1; 857 primary = 1;
856 858
857 if (!data[0] && !data[1]) 859 if (!data[0] && !data[1])
858 pr_warning("intc: missing unique irq mask for " 860 pr_warning("missing unique irq mask for irq %d (vect 0x%04x)\n",
859 "irq %d (vect 0x%04x)\n", irq, irq2evt(irq)); 861 irq, irq2evt(irq));
860 862
861 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1); 863 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
862 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1); 864 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
@@ -952,7 +954,7 @@ int __init register_intc_controller(struct intc_desc *desc)
952 struct intc_desc_int *d; 954 struct intc_desc_int *d;
953 struct resource *res; 955 struct resource *res;
954 956
955 pr_info("intc: Registered controller '%s' with %u IRQs\n", 957 pr_info("Registered controller '%s' with %u IRQs\n",
956 desc->name, hw->nr_vectors); 958 desc->name, hw->nr_vectors);
957 959
958 d = kzalloc(sizeof(*d), GFP_NOWAIT); 960 d = kzalloc(sizeof(*d), GFP_NOWAIT);
@@ -1148,7 +1150,7 @@ int register_intc_userimask(unsigned long addr)
1148 if (unlikely(!uimask)) 1150 if (unlikely(!uimask))
1149 return -ENOMEM; 1151 return -ENOMEM;
1150 1152
1151 pr_info("intc: userimask support registered for levels 0 -> %d\n", 1153 pr_info("userimask support registered for levels 0 -> %d\n",
1152 default_prio_level - 1); 1154 default_prio_level - 1);
1153 1155
1154 return 0; 1156 return 0;
@@ -1286,7 +1288,7 @@ static int __init register_intc_sysdevs(void)
1286 } 1288 }
1287 1289
1288 if (error) 1290 if (error)
1289 pr_err("intc: sysdev registration error\n"); 1291 pr_err("sysdev registration error\n");
1290 1292
1291 return error; 1293 return error;
1292} 1294}
diff --git a/drivers/usb/gadget/m66592-udc.h b/drivers/usb/gadget/m66592-udc.h
index 8b960deed680..c3caf1ac73ce 100644
--- a/drivers/usb/gadget/m66592-udc.h
+++ b/drivers/usb/gadget/m66592-udc.h
@@ -537,35 +537,35 @@ struct m66592 {
537/*-------------------------------------------------------------------------*/ 537/*-------------------------------------------------------------------------*/
538static inline u16 m66592_read(struct m66592 *m66592, unsigned long offset) 538static inline u16 m66592_read(struct m66592 *m66592, unsigned long offset)
539{ 539{
540 return inw((unsigned long)m66592->reg + offset); 540 return ioread16(m66592->reg + offset);
541} 541}
542 542
543static inline void m66592_read_fifo(struct m66592 *m66592, 543static inline void m66592_read_fifo(struct m66592 *m66592,
544 unsigned long offset, 544 unsigned long offset,
545 void *buf, unsigned long len) 545 void *buf, unsigned long len)
546{ 546{
547 unsigned long fifoaddr = (unsigned long)m66592->reg + offset; 547 void __iomem *fifoaddr = m66592->reg + offset;
548 548
549 if (m66592->pdata->on_chip) { 549 if (m66592->pdata->on_chip) {
550 len = (len + 3) / 4; 550 len = (len + 3) / 4;
551 insl(fifoaddr, buf, len); 551 ioread32_rep(fifoaddr, buf, len);
552 } else { 552 } else {
553 len = (len + 1) / 2; 553 len = (len + 1) / 2;
554 insw(fifoaddr, buf, len); 554 ioread16_rep(fifoaddr, buf, len);
555 } 555 }
556} 556}
557 557
558static inline void m66592_write(struct m66592 *m66592, u16 val, 558static inline void m66592_write(struct m66592 *m66592, u16 val,
559 unsigned long offset) 559 unsigned long offset)
560{ 560{
561 outw(val, (unsigned long)m66592->reg + offset); 561 iowrite16(val, m66592->reg + offset);
562} 562}
563 563
564static inline void m66592_write_fifo(struct m66592 *m66592, 564static inline void m66592_write_fifo(struct m66592 *m66592,
565 unsigned long offset, 565 unsigned long offset,
566 void *buf, unsigned long len) 566 void *buf, unsigned long len)
567{ 567{
568 unsigned long fifoaddr = (unsigned long)m66592->reg + offset; 568 void __iomem *fifoaddr = m66592->reg + offset;
569 569
570 if (m66592->pdata->on_chip) { 570 if (m66592->pdata->on_chip) {
571 unsigned long count; 571 unsigned long count;
@@ -573,25 +573,25 @@ static inline void m66592_write_fifo(struct m66592 *m66592,
573 int i; 573 int i;
574 574
575 count = len / 4; 575 count = len / 4;
576 outsl(fifoaddr, buf, count); 576 iowrite32_rep(fifoaddr, buf, count);
577 577
578 if (len & 0x00000003) { 578 if (len & 0x00000003) {
579 pb = buf + count * 4; 579 pb = buf + count * 4;
580 for (i = 0; i < (len & 0x00000003); i++) { 580 for (i = 0; i < (len & 0x00000003); i++) {
581 if (m66592_read(m66592, M66592_CFBCFG)) /* le */ 581 if (m66592_read(m66592, M66592_CFBCFG)) /* le */
582 outb(pb[i], fifoaddr + (3 - i)); 582 iowrite8(pb[i], fifoaddr + (3 - i));
583 else 583 else
584 outb(pb[i], fifoaddr + i); 584 iowrite8(pb[i], fifoaddr + i);
585 } 585 }
586 } 586 }
587 } else { 587 } else {
588 unsigned long odd = len & 0x0001; 588 unsigned long odd = len & 0x0001;
589 589
590 len = len / 2; 590 len = len / 2;
591 outsw(fifoaddr, buf, len); 591 iowrite16_rep(fifoaddr, buf, len);
592 if (odd) { 592 if (odd) {
593 unsigned char *p = buf + len*2; 593 unsigned char *p = buf + len*2;
594 outb(*p, fifoaddr); 594 iowrite8(*p, fifoaddr);
595 } 595 }
596 } 596 }
597} 597}
diff --git a/drivers/usb/gadget/r8a66597-udc.c b/drivers/usb/gadget/r8a66597-udc.c
index 888d8f166c0b..70a817842755 100644
--- a/drivers/usb/gadget/r8a66597-udc.c
+++ b/drivers/usb/gadget/r8a66597-udc.c
@@ -1500,7 +1500,7 @@ static int __exit r8a66597_remove(struct platform_device *pdev)
1500 struct r8a66597 *r8a66597 = dev_get_drvdata(&pdev->dev); 1500 struct r8a66597 *r8a66597 = dev_get_drvdata(&pdev->dev);
1501 1501
1502 del_timer_sync(&r8a66597->timer); 1502 del_timer_sync(&r8a66597->timer);
1503 iounmap((void *)r8a66597->reg); 1503 iounmap(r8a66597->reg);
1504 free_irq(platform_get_irq(pdev, 0), r8a66597); 1504 free_irq(platform_get_irq(pdev, 0), r8a66597);
1505 r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req); 1505 r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
1506#ifdef CONFIG_HAVE_CLK 1506#ifdef CONFIG_HAVE_CLK
@@ -1578,7 +1578,7 @@ static int __init r8a66597_probe(struct platform_device *pdev)
1578 init_timer(&r8a66597->timer); 1578 init_timer(&r8a66597->timer);
1579 r8a66597->timer.function = r8a66597_timer; 1579 r8a66597->timer.function = r8a66597_timer;
1580 r8a66597->timer.data = (unsigned long)r8a66597; 1580 r8a66597->timer.data = (unsigned long)r8a66597;
1581 r8a66597->reg = (unsigned long)reg; 1581 r8a66597->reg = reg;
1582 1582
1583#ifdef CONFIG_HAVE_CLK 1583#ifdef CONFIG_HAVE_CLK
1584 if (r8a66597->pdata->on_chip) { 1584 if (r8a66597->pdata->on_chip) {
diff --git a/drivers/usb/gadget/r8a66597-udc.h b/drivers/usb/gadget/r8a66597-udc.h
index 9a537aa07968..f763b5190afa 100644
--- a/drivers/usb/gadget/r8a66597-udc.h
+++ b/drivers/usb/gadget/r8a66597-udc.h
@@ -91,7 +91,7 @@ struct r8a66597_ep {
91 91
92struct r8a66597 { 92struct r8a66597 {
93 spinlock_t lock; 93 spinlock_t lock;
94 unsigned long reg; 94 void __iomem *reg;
95 95
96#ifdef CONFIG_HAVE_CLK 96#ifdef CONFIG_HAVE_CLK
97 struct clk *clk; 97 struct clk *clk;
@@ -127,7 +127,7 @@ struct r8a66597 {
127 127
128static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset) 128static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
129{ 129{
130 return inw(r8a66597->reg + offset); 130 return ioread16(r8a66597->reg + offset);
131} 131}
132 132
133static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597, 133static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
@@ -135,7 +135,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
135 unsigned char *buf, 135 unsigned char *buf,
136 int len) 136 int len)
137{ 137{
138 unsigned long fifoaddr = r8a66597->reg + offset; 138 void __iomem *fifoaddr = r8a66597->reg + offset;
139 unsigned int data; 139 unsigned int data;
140 int i; 140 int i;
141 141
@@ -144,7 +144,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
144 144
145 /* aligned buf case */ 145 /* aligned buf case */
146 if (len >= 4 && !((unsigned long)buf & 0x03)) { 146 if (len >= 4 && !((unsigned long)buf & 0x03)) {
147 insl(fifoaddr, buf, len / 4); 147 ioread32_rep(fifoaddr, buf, len / 4);
148 buf += len & ~0x03; 148 buf += len & ~0x03;
149 len &= 0x03; 149 len &= 0x03;
150 } 150 }
@@ -152,7 +152,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
152 /* unaligned buf case */ 152 /* unaligned buf case */
153 for (i = 0; i < len; i++) { 153 for (i = 0; i < len; i++) {
154 if (!(i & 0x03)) 154 if (!(i & 0x03))
155 data = inl(fifoaddr); 155 data = ioread32(fifoaddr);
156 156
157 buf[i] = (data >> ((i & 0x03) * 8)) & 0xff; 157 buf[i] = (data >> ((i & 0x03) * 8)) & 0xff;
158 } 158 }
@@ -161,7 +161,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
161 161
162 /* aligned buf case */ 162 /* aligned buf case */
163 if (len >= 2 && !((unsigned long)buf & 0x01)) { 163 if (len >= 2 && !((unsigned long)buf & 0x01)) {
164 insw(fifoaddr, buf, len / 2); 164 ioread16_rep(fifoaddr, buf, len / 2);
165 buf += len & ~0x01; 165 buf += len & ~0x01;
166 len &= 0x01; 166 len &= 0x01;
167 } 167 }
@@ -169,7 +169,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
169 /* unaligned buf case */ 169 /* unaligned buf case */
170 for (i = 0; i < len; i++) { 170 for (i = 0; i < len; i++) {
171 if (!(i & 0x01)) 171 if (!(i & 0x01))
172 data = inw(fifoaddr); 172 data = ioread16(fifoaddr);
173 173
174 buf[i] = (data >> ((i & 0x01) * 8)) & 0xff; 174 buf[i] = (data >> ((i & 0x01) * 8)) & 0xff;
175 } 175 }
@@ -179,7 +179,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
179static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val, 179static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
180 unsigned long offset) 180 unsigned long offset)
181{ 181{
182 outw(val, r8a66597->reg + offset); 182 iowrite16(val, r8a66597->reg + offset);
183} 183}
184 184
185static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597, 185static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
@@ -187,21 +187,21 @@ static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
187 unsigned char *buf, 187 unsigned char *buf,
188 int len) 188 int len)
189{ 189{
190 unsigned long fifoaddr = r8a66597->reg + offset; 190 void __iomem *fifoaddr = r8a66597->reg + offset;
191 int adj = 0; 191 int adj = 0;
192 int i; 192 int i;
193 193
194 if (r8a66597->pdata->on_chip) { 194 if (r8a66597->pdata->on_chip) {
195 /* 32-bit access only if buf is 32-bit aligned */ 195 /* 32-bit access only if buf is 32-bit aligned */
196 if (len >= 4 && !((unsigned long)buf & 0x03)) { 196 if (len >= 4 && !((unsigned long)buf & 0x03)) {
197 outsl(fifoaddr, buf, len / 4); 197 iowrite32_rep(fifoaddr, buf, len / 4);
198 buf += len & ~0x03; 198 buf += len & ~0x03;
199 len &= 0x03; 199 len &= 0x03;
200 } 200 }
201 } else { 201 } else {
202 /* 16-bit access only if buf is 16-bit aligned */ 202 /* 16-bit access only if buf is 16-bit aligned */
203 if (len >= 2 && !((unsigned long)buf & 0x01)) { 203 if (len >= 2 && !((unsigned long)buf & 0x01)) {
204 outsw(fifoaddr, buf, len / 2); 204 iowrite16_rep(fifoaddr, buf, len / 2);
205 buf += len & ~0x01; 205 buf += len & ~0x01;
206 len &= 0x01; 206 len &= 0x01;
207 } 207 }
@@ -216,7 +216,7 @@ static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
216 } 216 }
217 217
218 for (i = 0; i < len; i++) 218 for (i = 0; i < len; i++)
219 outb(buf[i], fifoaddr + adj - (i & adj)); 219 iowrite8(buf[i], fifoaddr + adj - (i & adj));
220} 220}
221 221
222static inline void r8a66597_mdfy(struct r8a66597 *r8a66597, 222static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c
index 6db57ab6079d..1a2bb4ce638f 100644
--- a/drivers/usb/host/r8a66597-hcd.c
+++ b/drivers/usb/host/r8a66597-hcd.c
@@ -2404,7 +2404,7 @@ static int __init_or_module r8a66597_remove(struct platform_device *pdev)
2404 2404
2405 del_timer_sync(&r8a66597->rh_timer); 2405 del_timer_sync(&r8a66597->rh_timer);
2406 usb_remove_hcd(hcd); 2406 usb_remove_hcd(hcd);
2407 iounmap((void *)r8a66597->reg); 2407 iounmap(r8a66597->reg);
2408#ifdef CONFIG_HAVE_CLK 2408#ifdef CONFIG_HAVE_CLK
2409 if (r8a66597->pdata->on_chip) 2409 if (r8a66597->pdata->on_chip)
2410 clk_put(r8a66597->clk); 2410 clk_put(r8a66597->clk);
@@ -2496,7 +2496,7 @@ static int __devinit r8a66597_probe(struct platform_device *pdev)
2496 init_timer(&r8a66597->rh_timer); 2496 init_timer(&r8a66597->rh_timer);
2497 r8a66597->rh_timer.function = r8a66597_timer; 2497 r8a66597->rh_timer.function = r8a66597_timer;
2498 r8a66597->rh_timer.data = (unsigned long)r8a66597; 2498 r8a66597->rh_timer.data = (unsigned long)r8a66597;
2499 r8a66597->reg = (unsigned long)reg; 2499 r8a66597->reg = reg;
2500 2500
2501 /* make sure no interrupts are pending */ 2501 /* make sure no interrupts are pending */
2502 ret = r8a66597_clock_enable(r8a66597); 2502 ret = r8a66597_clock_enable(r8a66597);
diff --git a/drivers/usb/host/r8a66597.h b/drivers/usb/host/r8a66597.h
index 228e3fb23854..95d0f5adfdcf 100644
--- a/drivers/usb/host/r8a66597.h
+++ b/drivers/usb/host/r8a66597.h
@@ -112,7 +112,7 @@ struct r8a66597_root_hub {
112 112
113struct r8a66597 { 113struct r8a66597 {
114 spinlock_t lock; 114 spinlock_t lock;
115 unsigned long reg; 115 void __iomem *reg;
116#ifdef CONFIG_HAVE_CLK 116#ifdef CONFIG_HAVE_CLK
117 struct clk *clk; 117 struct clk *clk;
118#endif 118#endif
@@ -170,67 +170,67 @@ static inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597,
170 170
171static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset) 171static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
172{ 172{
173 return inw(r8a66597->reg + offset); 173 return ioread16(r8a66597->reg + offset);
174} 174}
175 175
176static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597, 176static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
177 unsigned long offset, u16 *buf, 177 unsigned long offset, u16 *buf,
178 int len) 178 int len)
179{ 179{
180 unsigned long fifoaddr = r8a66597->reg + offset; 180 void __iomem *fifoaddr = r8a66597->reg + offset;
181 unsigned long count; 181 unsigned long count;
182 182
183 if (r8a66597->pdata->on_chip) { 183 if (r8a66597->pdata->on_chip) {
184 count = len / 4; 184 count = len / 4;
185 insl(fifoaddr, buf, count); 185 ioread32_rep(fifoaddr, buf, count);
186 186
187 if (len & 0x00000003) { 187 if (len & 0x00000003) {
188 unsigned long tmp = inl(fifoaddr); 188 unsigned long tmp = ioread32(fifoaddr);
189 memcpy((unsigned char *)buf + count * 4, &tmp, 189 memcpy((unsigned char *)buf + count * 4, &tmp,
190 len & 0x03); 190 len & 0x03);
191 } 191 }
192 } else { 192 } else {
193 len = (len + 1) / 2; 193 len = (len + 1) / 2;
194 insw(fifoaddr, buf, len); 194 ioread16_rep(fifoaddr, buf, len);
195 } 195 }
196} 196}
197 197
198static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val, 198static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
199 unsigned long offset) 199 unsigned long offset)
200{ 200{
201 outw(val, r8a66597->reg + offset); 201 iowrite16(val, r8a66597->reg + offset);
202} 202}
203 203
204static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597, 204static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
205 unsigned long offset, u16 *buf, 205 unsigned long offset, u16 *buf,
206 int len) 206 int len)
207{ 207{
208 unsigned long fifoaddr = r8a66597->reg + offset; 208 void __iomem *fifoaddr = r8a66597->reg + offset;
209 unsigned long count; 209 unsigned long count;
210 unsigned char *pb; 210 unsigned char *pb;
211 int i; 211 int i;
212 212
213 if (r8a66597->pdata->on_chip) { 213 if (r8a66597->pdata->on_chip) {
214 count = len / 4; 214 count = len / 4;
215 outsl(fifoaddr, buf, count); 215 iowrite32_rep(fifoaddr, buf, count);
216 216
217 if (len & 0x00000003) { 217 if (len & 0x00000003) {
218 pb = (unsigned char *)buf + count * 4; 218 pb = (unsigned char *)buf + count * 4;
219 for (i = 0; i < (len & 0x00000003); i++) { 219 for (i = 0; i < (len & 0x00000003); i++) {
220 if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND) 220 if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
221 outb(pb[i], fifoaddr + i); 221 iowrite8(pb[i], fifoaddr + i);
222 else 222 else
223 outb(pb[i], fifoaddr + 3 - i); 223 iowrite8(pb[i], fifoaddr + 3 - i);
224 } 224 }
225 } 225 }
226 } else { 226 } else {
227 int odd = len & 0x0001; 227 int odd = len & 0x0001;
228 228
229 len = len / 2; 229 len = len / 2;
230 outsw(fifoaddr, buf, len); 230 ioread16_rep(fifoaddr, buf, len);
231 if (unlikely(odd)) { 231 if (unlikely(odd)) {
232 buf = &buf[len]; 232 buf = &buf[len];
233 outb((unsigned char)*buf, fifoaddr); 233 iowrite8((unsigned char)*buf, fifoaddr);
234 } 234 }
235 } 235 }
236} 236}
diff --git a/drivers/video/sh_mobile_lcdcfb.c b/drivers/video/sh_mobile_lcdcfb.c
index e8c769944812..12c451a711e9 100644
--- a/drivers/video/sh_mobile_lcdcfb.c
+++ b/drivers/video/sh_mobile_lcdcfb.c
@@ -991,13 +991,13 @@ static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
991 priv->ch[j].lcdc = priv; 991 priv->ch[j].lcdc = priv;
992 memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i])); 992 memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
993 993
994 error = sh_mobile_lcdc_check_interface(&priv->ch[i]); 994 error = sh_mobile_lcdc_check_interface(&priv->ch[j]);
995 if (error) { 995 if (error) {
996 dev_err(&pdev->dev, "unsupported interface type\n"); 996 dev_err(&pdev->dev, "unsupported interface type\n");
997 goto err1; 997 goto err1;
998 } 998 }
999 init_waitqueue_head(&priv->ch[i].frame_end_wait); 999 init_waitqueue_head(&priv->ch[j].frame_end_wait);
1000 init_completion(&priv->ch[i].vsync_completion); 1000 init_completion(&priv->ch[j].vsync_completion);
1001 priv->ch[j].pan_offset = 0; 1001 priv->ch[j].pan_offset = 0;
1002 1002
1003 switch (pdata->ch[i].chan) { 1003 switch (pdata->ch[i].chan) {
diff --git a/include/linux/mmc/sh_mmcif.h b/include/linux/mmc/sh_mmcif.h
index aafe832f18aa..d4a2ebbdab4b 100644
--- a/include/linux/mmc/sh_mmcif.h
+++ b/include/linux/mmc/sh_mmcif.h
@@ -14,6 +14,9 @@
14#ifndef __SH_MMCIF_H__ 14#ifndef __SH_MMCIF_H__
15#define __SH_MMCIF_H__ 15#define __SH_MMCIF_H__
16 16
17#include <linux/platform_device.h>
18#include <linux/io.h>
19
17/* 20/*
18 * MMCIF : CE_CLK_CTRL [19:16] 21 * MMCIF : CE_CLK_CTRL [19:16]
19 * 1000 : Peripheral clock / 512 22 * 1000 : Peripheral clock / 512
@@ -36,4 +39,162 @@ struct sh_mmcif_plat_data {
36 u32 ocr; 39 u32 ocr;
37}; 40};
38 41
42#define MMCIF_CE_CMD_SET 0x00000000
43#define MMCIF_CE_ARG 0x00000008
44#define MMCIF_CE_ARG_CMD12 0x0000000C
45#define MMCIF_CE_CMD_CTRL 0x00000010
46#define MMCIF_CE_BLOCK_SET 0x00000014
47#define MMCIF_CE_CLK_CTRL 0x00000018
48#define MMCIF_CE_BUF_ACC 0x0000001C
49#define MMCIF_CE_RESP3 0x00000020
50#define MMCIF_CE_RESP2 0x00000024
51#define MMCIF_CE_RESP1 0x00000028
52#define MMCIF_CE_RESP0 0x0000002C
53#define MMCIF_CE_RESP_CMD12 0x00000030
54#define MMCIF_CE_DATA 0x00000034
55#define MMCIF_CE_INT 0x00000040
56#define MMCIF_CE_INT_MASK 0x00000044
57#define MMCIF_CE_HOST_STS1 0x00000048
58#define MMCIF_CE_HOST_STS2 0x0000004C
59#define MMCIF_CE_VERSION 0x0000007C
60
61extern inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
62{
63 return readl(addr + reg);
64}
65
66extern inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
67{
68 writel(val, addr + reg);
69}
70
71#define SH_MMCIF_BBS 512 /* boot block size */
72
73extern inline void sh_mmcif_boot_cmd_send(void __iomem *base,
74 unsigned long cmd, unsigned long arg)
75{
76 sh_mmcif_writel(base, MMCIF_CE_INT, 0);
77 sh_mmcif_writel(base, MMCIF_CE_ARG, arg);
78 sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
79}
80
81extern inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
82{
83 unsigned long tmp;
84 int cnt;
85
86 for (cnt = 0; cnt < 1000000; cnt++) {
87 tmp = sh_mmcif_readl(base, MMCIF_CE_INT);
88 if (tmp & mask) {
89 sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask);
90 return 0;
91 }
92 }
93
94 return -1;
95}
96
97extern inline int sh_mmcif_boot_cmd(void __iomem *base,
98 unsigned long cmd, unsigned long arg)
99{
100 sh_mmcif_boot_cmd_send(base, cmd, arg);
101 return sh_mmcif_boot_cmd_poll(base, 0x00010000);
102}
103
104extern inline int sh_mmcif_boot_do_read_single(void __iomem *base,
105 unsigned int block_nr,
106 unsigned long *buf)
107{
108 int k;
109
110 /* CMD13 - Status */
111 sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000);
112
113 if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900)
114 return -1;
115
116 /* CMD17 - Read */
117 sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS);
118 if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0)
119 return -1;
120
121 for (k = 0; k < (SH_MMCIF_BBS / 4); k++)
122 buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA);
123
124 return 0;
125}
126
127extern inline int sh_mmcif_boot_do_read(void __iomem *base,
128 unsigned long first_block,
129 unsigned long nr_blocks,
130 void *buf)
131{
132 unsigned long k;
133 int ret = 0;
134
135 /* CMD16 - Set the block size */
136 sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);
137
138 for (k = 0; !ret && k < nr_blocks; k++)
139 ret = sh_mmcif_boot_do_read_single(base, first_block + k,
140 buf + (k * SH_MMCIF_BBS));
141
142 return ret;
143}
144
145extern inline void sh_mmcif_boot_init(void __iomem *base)
146{
147 unsigned long tmp;
148
149 /* reset */
150 tmp = sh_mmcif_readl(base, MMCIF_CE_VERSION);
151 sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp | 0x80000000);
152 sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp & ~0x80000000);
153
154 /* byte swap */
155 sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, 0x00010000);
156
157 /* Set block size in MMCIF hardware */
158 sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
159
160 /* Enable the clock, set it to Bus clock/256 (about 325Khz)*/
161 sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01072fff);
162
163 /* CMD0 */
164 sh_mmcif_boot_cmd(base, 0x00000040, 0);
165
166 /* CMD1 - Get OCR */
167 do {
168 sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */
169 } while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000)
170 != 0x80000000);
171
172 /* CMD2 - Get CID */
173 sh_mmcif_boot_cmd(base, 0x02806040, 0);
174
175 /* CMD3 - Set card relative address */
176 sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);
177}
178
179extern inline void sh_mmcif_boot_slurp(void __iomem *base,
180 unsigned char *buf,
181 unsigned long no_bytes)
182{
183 unsigned long tmp;
184
185 /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
186 sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01012fff);
187
188 /* CMD9 - Get CSD */
189 sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
190
191 /* CMD7 - Select the card */
192 sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);
193
194 tmp = no_bytes / SH_MMCIF_BBS;
195 tmp += (no_bytes % SH_MMCIF_BBS) ? 1 : 0;
196
197 sh_mmcif_boot_do_read(base, 512, tmp, buf);
198}
199
39#endif /* __SH_MMCIF_H__ */ 200#endif /* __SH_MMCIF_H__ */
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h
index f5364a1de68b..baed2122c5a6 100644
--- a/include/linux/serial_sci.h
+++ b/include/linux/serial_sci.h
@@ -2,9 +2,7 @@
2#define __LINUX_SERIAL_SCI_H 2#define __LINUX_SERIAL_SCI_H
3 3
4#include <linux/serial_core.h> 4#include <linux/serial_core.h>
5#ifdef CONFIG_SERIAL_SH_SCI_DMA 5#include <linux/sh_dma.h>
6#include <asm/dmaengine.h>
7#endif
8 6
9/* 7/*
10 * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts) 8 * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-02 21:02:28 -0500