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authorTony Lindgren <tony@atomide.com>2009-11-11 18:20:53 -0500
committerTony Lindgren <tony@atomide.com>2009-11-11 18:20:53 -0500
commit4d0226042c05588be47b06bc1dbe7a09c9c540a4 (patch)
treedb16053ad7010c141a054ab0c8b5c243c311962f
parent774facda20d2f8f0f61fa312d8028dad18ac5ee4 (diff)
parentf265dc4c5d39f2bd369d97c87a7bd89061b159d4 (diff)
Merge branch 'pm-upstream/pm-off' of ssh://master.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into 7xx-iosplit-plat-merge
Diffstat
-rw-r--r--arch/arm/mach-omap2/control.c381
-rw-r--r--arch/arm/mach-omap2/gpmc.c98
-rw-r--r--arch/arm/mach-omap2/irq.c66
-rw-r--r--arch/arm/mach-omap2/pm-debug.c29
-rw-r--r--arch/arm/mach-omap2/pm.h10
-rw-r--r--arch/arm/mach-omap2/pm34xx.c362
-rw-r--r--arch/arm/mach-omap2/powerdomains34xx.h8
-rw-r--r--arch/arm/mach-omap2/prcm.c407
-rw-r--r--arch/arm/mach-omap2/prm-regbits-34xx.h2
-rw-r--r--arch/arm/mach-omap2/sdrc.c27
-rw-r--r--arch/arm/mach-omap2/serial.c2
-rw-r--r--arch/arm/mach-omap2/sleep34xx.S218
-rw-r--r--arch/arm/mach-omap2/timer-gp.c2
-rw-r--r--arch/arm/plat-omap/dma.c48
-rw-r--r--arch/arm/plat-omap/gpio.c92
-rw-r--r--arch/arm/plat-omap/include/plat/control.h62
-rw-r--r--arch/arm/plat-omap/include/plat/dma.h5
-rw-r--r--arch/arm/plat-omap/include/plat/gpio.h3
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc.h3
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h5
-rw-r--r--arch/arm/plat-omap/include/plat/prcm.h6
-rw-r--r--arch/arm/plat-omap/include/plat/sdrc.h8
-rw-r--r--arch/arm/plat-omap/include/plat/sram.h7
-rw-r--r--arch/arm/plat-omap/sram.c8
24 files changed, 1809 insertions, 50 deletions
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 6adb360c6d45..cdd1f35636dd 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -17,9 +17,125 @@
17 17
18#include <plat/common.h> 18#include <plat/common.h>
19#include <plat/control.h> 19#include <plat/control.h>
20#include <plat/sdrc.h>
21#include "cm-regbits-34xx.h"
22#include "prm-regbits-34xx.h"
23#include "cm.h"
24#include "prm.h"
25#include "sdrc.h"
20 26
21static void __iomem *omap2_ctrl_base; 27static void __iomem *omap2_ctrl_base;
22 28
29#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
30struct omap3_scratchpad {
31 u32 boot_config_ptr;
32 u32 public_restore_ptr;
33 u32 secure_ram_restore_ptr;
34 u32 sdrc_module_semaphore;
35 u32 prcm_block_offset;
36 u32 sdrc_block_offset;
37};
38
39struct omap3_scratchpad_prcm_block {
40 u32 prm_clksrc_ctrl;
41 u32 prm_clksel;
42 u32 cm_clksel_core;
43 u32 cm_clksel_wkup;
44 u32 cm_clken_pll;
45 u32 cm_autoidle_pll;
46 u32 cm_clksel1_pll;
47 u32 cm_clksel2_pll;
48 u32 cm_clksel3_pll;
49 u32 cm_clken_pll_mpu;
50 u32 cm_autoidle_pll_mpu;
51 u32 cm_clksel1_pll_mpu;
52 u32 cm_clksel2_pll_mpu;
53 u32 prcm_block_size;
54};
55
56struct omap3_scratchpad_sdrc_block {
57 u16 sysconfig;
58 u16 cs_cfg;
59 u16 sharing;
60 u16 err_type;
61 u32 dll_a_ctrl;
62 u32 dll_b_ctrl;
63 u32 power;
64 u32 cs_0;
65 u32 mcfg_0;
66 u16 mr_0;
67 u16 emr_1_0;
68 u16 emr_2_0;
69 u16 emr_3_0;
70 u32 actim_ctrla_0;
71 u32 actim_ctrlb_0;
72 u32 rfr_ctrl_0;
73 u32 cs_1;
74 u32 mcfg_1;
75 u16 mr_1;
76 u16 emr_1_1;
77 u16 emr_2_1;
78 u16 emr_3_1;
79 u32 actim_ctrla_1;
80 u32 actim_ctrlb_1;
81 u32 rfr_ctrl_1;
82 u16 dcdl_1_ctrl;
83 u16 dcdl_2_ctrl;
84 u32 flags;
85 u32 block_size;
86};
87
88void *omap3_secure_ram_storage;
89
90/*
91 * This is used to store ARM registers in SDRAM before attempting
92 * an MPU OFF. The save and restore happens from the SRAM sleep code.
93 * The address is stored in scratchpad, so that it can be used
94 * during the restore path.
95 */
96u32 omap3_arm_context[128];
97
98struct omap3_control_regs {
99 u32 sysconfig;
100 u32 devconf0;
101 u32 mem_dftrw0;
102 u32 mem_dftrw1;
103 u32 msuspendmux_0;
104 u32 msuspendmux_1;
105 u32 msuspendmux_2;
106 u32 msuspendmux_3;
107 u32 msuspendmux_4;
108 u32 msuspendmux_5;
109 u32 sec_ctrl;
110 u32 devconf1;
111 u32 csirxfe;
112 u32 iva2_bootaddr;
113 u32 iva2_bootmod;
114 u32 debobs_0;
115 u32 debobs_1;
116 u32 debobs_2;
117 u32 debobs_3;
118 u32 debobs_4;
119 u32 debobs_5;
120 u32 debobs_6;
121 u32 debobs_7;
122 u32 debobs_8;
123 u32 prog_io0;
124 u32 prog_io1;
125 u32 dss_dpll_spreading;
126 u32 core_dpll_spreading;
127 u32 per_dpll_spreading;
128 u32 usbhost_dpll_spreading;
129 u32 pbias_lite;
130 u32 temp_sensor;
131 u32 sramldo4;
132 u32 sramldo5;
133 u32 csi;
134};
135
136static struct omap3_control_regs control_context;
137#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
138
23#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) 139#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg))
24 140
25void __init omap2_set_globals_control(struct omap_globals *omap2_globals) 141void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
@@ -62,3 +178,268 @@ void omap_ctrl_writel(u32 val, u16 offset)
62 __raw_writel(val, OMAP_CTRL_REGADDR(offset)); 178 __raw_writel(val, OMAP_CTRL_REGADDR(offset));
63} 179}
64 180
181#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
182/*
183 * Clears the scratchpad contents in case of cold boot-
184 * called during bootup
185 */
186void omap3_clear_scratchpad_contents(void)
187{
188 u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
189 u32 *v_addr;
190 u32 offset = 0;
191 v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
192 if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
193 OMAP3430_GLOBAL_COLD_RST) {
194 for ( ; offset <= max_offset; offset += 0x4)
195 __raw_writel(0x0, (v_addr + offset));
196 prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST, OMAP3430_GR_MOD,
197 OMAP3_PRM_RSTST_OFFSET);
198 }
199}
200
201/* Populate the scratchpad structure with restore structure */
202void omap3_save_scratchpad_contents(void)
203{
204 void * __iomem scratchpad_address;
205 u32 arm_context_addr;
206 struct omap3_scratchpad scratchpad_contents;
207 struct omap3_scratchpad_prcm_block prcm_block_contents;
208 struct omap3_scratchpad_sdrc_block sdrc_block_contents;
209
210 /* Populate the Scratchpad contents */
211 scratchpad_contents.boot_config_ptr = 0x0;
212 if (omap_rev() != OMAP3430_REV_ES3_0 &&
213 omap_rev() != OMAP3430_REV_ES3_1)
214 scratchpad_contents.public_restore_ptr =
215 virt_to_phys(get_restore_pointer());
216 else
217 scratchpad_contents.public_restore_ptr =
218 virt_to_phys(get_es3_restore_pointer());
219 if (omap_type() == OMAP2_DEVICE_TYPE_GP)
220 scratchpad_contents.secure_ram_restore_ptr = 0x0;
221 else
222 scratchpad_contents.secure_ram_restore_ptr =
223 (u32) __pa(omap3_secure_ram_storage);
224 scratchpad_contents.sdrc_module_semaphore = 0x0;
225 scratchpad_contents.prcm_block_offset = 0x2C;
226 scratchpad_contents.sdrc_block_offset = 0x64;
227
228 /* Populate the PRCM block contents */
229 prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD,
230 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
231 prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD,
232 OMAP3_PRM_CLKSEL_OFFSET);
233 prcm_block_contents.cm_clksel_core =
234 cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
235 prcm_block_contents.cm_clksel_wkup =
236 cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
237 prcm_block_contents.cm_clken_pll =
238 cm_read_mod_reg(PLL_MOD, CM_CLKEN);
239 prcm_block_contents.cm_autoidle_pll =
240 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
241 prcm_block_contents.cm_clksel1_pll =
242 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
243 prcm_block_contents.cm_clksel2_pll =
244 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
245 prcm_block_contents.cm_clksel3_pll =
246 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
247 prcm_block_contents.cm_clken_pll_mpu =
248 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
249 prcm_block_contents.cm_autoidle_pll_mpu =
250 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
251 prcm_block_contents.cm_clksel1_pll_mpu =
252 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
253 prcm_block_contents.cm_clksel2_pll_mpu =
254 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
255 prcm_block_contents.prcm_block_size = 0x0;
256
257 /* Populate the SDRC block contents */
258 sdrc_block_contents.sysconfig =
259 (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
260 sdrc_block_contents.cs_cfg =
261 (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
262 sdrc_block_contents.sharing =
263 (sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
264 sdrc_block_contents.err_type =
265 (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
266 sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
267 sdrc_block_contents.dll_b_ctrl = 0x0;
268 /*
269 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
270 * be programed to issue automatic self refresh on timeout
271 * of AUTO_CNT = 1 prior to any transition to OFF mode.
272 */
273 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
274 && (omap_rev() >= OMAP3430_REV_ES3_0))
275 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
276 ~(SDRC_POWER_AUTOCOUNT_MASK|
277 SDRC_POWER_CLKCTRL_MASK)) |
278 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
279 SDRC_SELF_REFRESH_ON_AUTOCOUNT;
280 else
281 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
282
283 sdrc_block_contents.cs_0 = 0x0;
284 sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
285 sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
286 sdrc_block_contents.emr_1_0 = 0x0;
287 sdrc_block_contents.emr_2_0 = 0x0;
288 sdrc_block_contents.emr_3_0 = 0x0;
289 sdrc_block_contents.actim_ctrla_0 =
290 sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
291 sdrc_block_contents.actim_ctrlb_0 =
292 sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
293 sdrc_block_contents.rfr_ctrl_0 =
294 sdrc_read_reg(SDRC_RFR_CTRL_0);
295 sdrc_block_contents.cs_1 = 0x0;
296 sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
297 sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
298 sdrc_block_contents.emr_1_1 = 0x0;
299 sdrc_block_contents.emr_2_1 = 0x0;
300 sdrc_block_contents.emr_3_1 = 0x0;
301 sdrc_block_contents.actim_ctrla_1 =
302 sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
303 sdrc_block_contents.actim_ctrlb_1 =
304 sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
305 sdrc_block_contents.rfr_ctrl_1 =
306 sdrc_read_reg(SDRC_RFR_CTRL_1);
307 sdrc_block_contents.dcdl_1_ctrl = 0x0;
308 sdrc_block_contents.dcdl_2_ctrl = 0x0;
309 sdrc_block_contents.flags = 0x0;
310 sdrc_block_contents.block_size = 0x0;
311
312 arm_context_addr = virt_to_phys(omap3_arm_context);
313
314 /* Copy all the contents to the scratchpad location */
315 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
316 memcpy_toio(scratchpad_address, &scratchpad_contents,
317 sizeof(scratchpad_contents));
318 /* Scratchpad contents being 32 bits, a divide by 4 done here */
319 memcpy_toio(scratchpad_address +
320 scratchpad_contents.prcm_block_offset,
321 &prcm_block_contents, sizeof(prcm_block_contents));
322 memcpy_toio(scratchpad_address +
323 scratchpad_contents.sdrc_block_offset,
324 &sdrc_block_contents, sizeof(sdrc_block_contents));
325 /*
326 * Copies the address of the location in SDRAM where ARM
327 * registers get saved during a MPU OFF transition.
328 */
329 memcpy_toio(scratchpad_address +
330 scratchpad_contents.sdrc_block_offset +
331 sizeof(sdrc_block_contents), &arm_context_addr, 4);
332}
333
334void omap3_control_save_context(void)
335{
336 control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
337 control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
338 control_context.mem_dftrw0 =
339 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
340 control_context.mem_dftrw1 =
341 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
342 control_context.msuspendmux_0 =
343 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
344 control_context.msuspendmux_1 =
345 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
346 control_context.msuspendmux_2 =
347 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
348 control_context.msuspendmux_3 =
349 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
350 control_context.msuspendmux_4 =
351 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
352 control_context.msuspendmux_5 =
353 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
354 control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
355 control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
356 control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
357 control_context.iva2_bootaddr =
358 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
359 control_context.iva2_bootmod =
360 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
361 control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
362 control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
363 control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
364 control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
365 control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
366 control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
367 control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
368 control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
369 control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
370 control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
371 control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
372 control_context.dss_dpll_spreading =
373 omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
374 control_context.core_dpll_spreading =
375 omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
376 control_context.per_dpll_spreading =
377 omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
378 control_context.usbhost_dpll_spreading =
379 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
380 control_context.pbias_lite =
381 omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
382 control_context.temp_sensor =
383 omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
384 control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
385 control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
386 control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
387 return;
388}
389
390void omap3_control_restore_context(void)
391{
392 omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
393 omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
394 omap_ctrl_writel(control_context.mem_dftrw0,
395 OMAP343X_CONTROL_MEM_DFTRW0);
396 omap_ctrl_writel(control_context.mem_dftrw1,
397 OMAP343X_CONTROL_MEM_DFTRW1);
398 omap_ctrl_writel(control_context.msuspendmux_0,
399 OMAP2_CONTROL_MSUSPENDMUX_0);
400 omap_ctrl_writel(control_context.msuspendmux_1,
401 OMAP2_CONTROL_MSUSPENDMUX_1);
402 omap_ctrl_writel(control_context.msuspendmux_2,
403 OMAP2_CONTROL_MSUSPENDMUX_2);
404 omap_ctrl_writel(control_context.msuspendmux_3,
405 OMAP2_CONTROL_MSUSPENDMUX_3);
406 omap_ctrl_writel(control_context.msuspendmux_4,
407 OMAP2_CONTROL_MSUSPENDMUX_4);
408 omap_ctrl_writel(control_context.msuspendmux_5,
409 OMAP2_CONTROL_MSUSPENDMUX_5);
410 omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
411 omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
412 omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
413 omap_ctrl_writel(control_context.iva2_bootaddr,
414 OMAP343X_CONTROL_IVA2_BOOTADDR);
415 omap_ctrl_writel(control_context.iva2_bootmod,
416 OMAP343X_CONTROL_IVA2_BOOTMOD);
417 omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
418 omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
419 omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
420 omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
421 omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
422 omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
423 omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
424 omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
425 omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
426 omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
427 omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
428 omap_ctrl_writel(control_context.dss_dpll_spreading,
429 OMAP343X_CONTROL_DSS_DPLL_SPREADING);
430 omap_ctrl_writel(control_context.core_dpll_spreading,
431 OMAP343X_CONTROL_CORE_DPLL_SPREADING);
432 omap_ctrl_writel(control_context.per_dpll_spreading,
433 OMAP343X_CONTROL_PER_DPLL_SPREADING);
434 omap_ctrl_writel(control_context.usbhost_dpll_spreading,
435 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
436 omap_ctrl_writel(control_context.pbias_lite,
437 OMAP343X_CONTROL_PBIAS_LITE);
438 omap_ctrl_writel(control_context.temp_sensor,
439 OMAP343X_CONTROL_TEMP_SENSOR);
440 omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
441 omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
442 omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
443 return;
444}
445#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 004da696ace7..7d687845f391 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -62,6 +62,33 @@
62#define ENABLE_PREFETCH (0x1 << 7) 62#define ENABLE_PREFETCH (0x1 << 7)
63#define DMA_MPU_MODE 2 63#define DMA_MPU_MODE 2
64 64
65/* Structure to save gpmc cs context */
66struct gpmc_cs_config {
67 u32 config1;
68 u32 config2;
69 u32 config3;
70 u32 config4;
71 u32 config5;
72 u32 config6;
73 u32 config7;
74 int is_valid;
75};
76
77/*
78 * Structure to save/restore gpmc context
79 * to support core off on OMAP3
80 */
81struct omap3_gpmc_regs {
82 u32 sysconfig;
83 u32 irqenable;
84 u32 timeout_ctrl;
85 u32 config;
86 u32 prefetch_config1;
87 u32 prefetch_config2;
88 u32 prefetch_control;
89 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
90};
91
65static struct resource gpmc_mem_root; 92static struct resource gpmc_mem_root;
66static struct resource gpmc_cs_mem[GPMC_CS_NUM]; 93static struct resource gpmc_cs_mem[GPMC_CS_NUM];
67static DEFINE_SPINLOCK(gpmc_mem_lock); 94static DEFINE_SPINLOCK(gpmc_mem_lock);
@@ -261,7 +288,7 @@ static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
261 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f; 288 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
262 l &= ~(0x0f << 8); 289 l &= ~(0x0f << 8);
263 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8; 290 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
264 l |= 1 << 6; /* CSVALID */ 291 l |= GPMC_CONFIG7_CSVALID;
265 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); 292 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
266} 293}
267 294
@@ -270,7 +297,7 @@ static void gpmc_cs_disable_mem(int cs)
270 u32 l; 297 u32 l;
271 298
272 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 299 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
273 l &= ~(1 << 6); /* CSVALID */ 300 l &= ~GPMC_CONFIG7_CSVALID;
274 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); 301 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
275} 302}
276 303
@@ -290,7 +317,7 @@ static int gpmc_cs_mem_enabled(int cs)
290 u32 l; 317 u32 l;
291 318
292 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 319 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
293 return l & (1 << 6); 320 return l & GPMC_CONFIG7_CSVALID;
294} 321}
295 322
296int gpmc_cs_set_reserved(int cs, int reserved) 323int gpmc_cs_set_reserved(int cs, int reserved)
@@ -516,3 +543,68 @@ void __init gpmc_init(void)
516 gpmc_write_reg(GPMC_SYSCONFIG, l); 543 gpmc_write_reg(GPMC_SYSCONFIG, l);
517 gpmc_mem_init(); 544 gpmc_mem_init();
518} 545}
546
547#ifdef CONFIG_ARCH_OMAP3
548static struct omap3_gpmc_regs gpmc_context;
549
550void omap3_gpmc_save_context()
551{
552 int i;
553 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
554 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
555 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
556 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
557 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
558 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
559 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
560 for (i = 0; i < GPMC_CS_NUM; i++) {
561 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
562 if (gpmc_context.cs_context[i].is_valid) {
563 gpmc_context.cs_context[i].config1 =
564 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
565 gpmc_context.cs_context[i].config2 =
566 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
567 gpmc_context.cs_context[i].config3 =
568 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
569 gpmc_context.cs_context[i].config4 =
570 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
571 gpmc_context.cs_context[i].config5 =
572 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
573 gpmc_context.cs_context[i].config6 =
574 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
575 gpmc_context.cs_context[i].config7 =
576 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
577 }
578 }
579}
580
581void omap3_gpmc_restore_context()
582{
583 int i;
584 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
585 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
586 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
587 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
588 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
589 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
590 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
591 for (i = 0; i < GPMC_CS_NUM; i++) {
592 if (gpmc_context.cs_context[i].is_valid) {
593 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
594 gpmc_context.cs_context[i].config1);
595 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
596 gpmc_context.cs_context[i].config2);
597 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
598 gpmc_context.cs_context[i].config3);
599 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
600 gpmc_context.cs_context[i].config4);
601 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
602 gpmc_context.cs_context[i].config5);
603 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
604 gpmc_context.cs_context[i].config6);
605 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
606 gpmc_context.cs_context[i].config7);
607 }
608 }
609}
610#endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 1db121f437d2..e9bc782fa414 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -25,6 +25,10 @@
25#define INTC_SYSSTATUS 0x0014 25#define INTC_SYSSTATUS 0x0014
26#define INTC_SIR 0x0040 26#define INTC_SIR 0x0040
27#define INTC_CONTROL 0x0048 27#define INTC_CONTROL 0x0048
28#define INTC_PROTECTION 0x004C
29#define INTC_IDLE 0x0050
30#define INTC_THRESHOLD 0x0068
31#define INTC_MIR0 0x0084
28#define INTC_MIR_CLEAR0 0x0088 32#define INTC_MIR_CLEAR0 0x0088
29#define INTC_MIR_SET0 0x008c 33#define INTC_MIR_SET0 0x008c
30#define INTC_PENDING_IRQ0 0x0098 34#define INTC_PENDING_IRQ0 0x0098
@@ -48,6 +52,18 @@ static struct omap_irq_bank {
48 }, 52 },
49}; 53};
50 54
55/* Structure to save interrupt controller context */
56struct omap3_intc_regs {
57 u32 sysconfig;
58 u32 protection;
59 u32 idle;
60 u32 threshold;
61 u32 ilr[INTCPS_NR_IRQS];
62 u32 mir[INTCPS_NR_MIR_REGS];
63};
64
65static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
66
51/* INTC bank register get/set */ 67/* INTC bank register get/set */
52 68
53static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg) 69static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
@@ -209,3 +225,53 @@ void __init omap_init_irq(void)
209 } 225 }
210} 226}
211 227
228#ifdef CONFIG_ARCH_OMAP3
229void omap_intc_save_context(void)
230{
231 int ind = 0, i = 0;
232 for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
233 struct omap_irq_bank *bank = irq_banks + ind;
234 intc_context[ind].sysconfig =
235 intc_bank_read_reg(bank, INTC_SYSCONFIG);
236 intc_context[ind].protection =
237 intc_bank_read_reg(bank, INTC_PROTECTION);
238 intc_context[ind].idle =
239 intc_bank_read_reg(bank, INTC_IDLE);
240 intc_context[ind].threshold =
241 intc_bank_read_reg(bank, INTC_THRESHOLD);
242 for (i = 0; i < INTCPS_NR_IRQS; i++)
243 intc_context[ind].ilr[i] =
244 intc_bank_read_reg(bank, (0x100 + 0x4*i));
245 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
246 intc_context[ind].mir[i] =
247 intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
248 (0x20 * i));
249 }
250}
251
252void omap_intc_restore_context(void)
253{
254 int ind = 0, i = 0;
255
256 for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
257 struct omap_irq_bank *bank = irq_banks + ind;
258 intc_bank_write_reg(intc_context[ind].sysconfig,
259 bank, INTC_SYSCONFIG);
260 intc_bank_write_reg(intc_context[ind].sysconfig,
261 bank, INTC_SYSCONFIG);
262 intc_bank_write_reg(intc_context[ind].protection,
263 bank, INTC_PROTECTION);
264 intc_bank_write_reg(intc_context[ind].idle,
265 bank, INTC_IDLE);
266 intc_bank_write_reg(intc_context[ind].threshold,
267 bank, INTC_THRESHOLD);
268 for (i = 0; i < INTCPS_NR_IRQS; i++)
269 intc_bank_write_reg(intc_context[ind].ilr[i],
270 bank, (0x100 + 0x4*i));
271 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
272 intc_bank_write_reg(intc_context[ind].mir[i],
273 &irq_banks[0], INTC_MIR0 + (0x20 * i));
274 }
275 /* MIRs are saved and restore with other PRCM registers */
276}
277#endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 7eb2c12c8b7c..8baa30d2acfb 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -527,6 +527,29 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir)
527 return 0; 527 return 0;
528} 528}
529 529
530static int option_get(void *data, u64 *val)
531{
532 u32 *option = data;
533
534 *val = *option;
535
536 return 0;
537}
538
539static int option_set(void *data, u64 val)
540{
541 u32 *option = data;
542
543 *option = val;
544
545 if (option == &enable_off_mode)
546 omap3_pm_off_mode_enable(val);
547
548 return 0;
549}
550
551DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops, option_get, option_set, "%llu\n");
552
530static int __init pm_dbg_init(void) 553static int __init pm_dbg_init(void)
531{ 554{
532 int i; 555 int i;
@@ -569,6 +592,12 @@ static int __init pm_dbg_init(void)
569 592
570 } 593 }
571 594
595 (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUGO, d,
596 &enable_off_mode, &pm_dbg_option_fops);
597 (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUGO, d,
598 &sleep_while_idle, &pm_dbg_option_fops);
599 (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d,
600 &wakeup_timer_seconds, &pm_dbg_option_fops);
572 pm_dbg_init_done = 1; 601 pm_dbg_init_done = 1;
573 602
574 return 0; 603 return 0;
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 85b6face5392..7eb769f4ef30 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -13,9 +13,18 @@
13 13
14#include <plat/powerdomain.h> 14#include <plat/powerdomain.h>
15 15
16extern u32 enable_off_mode;
17extern u32 sleep_while_idle;
18
19extern void *omap3_secure_ram_storage;
20extern void omap3_pm_off_mode_enable(int);
21
16extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm); 22extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
17extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state); 23extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
18 24
25extern u32 wakeup_timer_seconds;
26extern struct omap_dm_timer *gptimer_wakeup;
27
19#ifdef CONFIG_PM_DEBUG 28#ifdef CONFIG_PM_DEBUG
20extern void omap2_pm_dump(int mode, int resume, unsigned int us); 29extern void omap2_pm_dump(int mode, int resume, unsigned int us);
21extern int omap2_pm_debug; 30extern int omap2_pm_debug;
@@ -36,6 +45,7 @@ extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
36 void __iomem *sdrc_power); 45 void __iomem *sdrc_power);
37extern void omap34xx_cpu_suspend(u32 *addr, int save_state); 46extern void omap34xx_cpu_suspend(u32 *addr, int save_state);
38extern void save_secure_ram_context(u32 *addr); 47extern void save_secure_ram_context(u32 *addr);
48extern void omap3_save_scratchpad_contents(void);
39 49
40extern unsigned int omap24xx_idle_loop_suspend_sz; 50extern unsigned int omap24xx_idle_loop_suspend_sz;
41extern unsigned int omap34xx_suspend_sz; 51extern unsigned int omap34xx_suspend_sz;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 391054900a6a..01b95eaae75a 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -5,6 +5,9 @@
5 * Tony Lindgren <tony@atomide.com> 5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander 6 * Jouni Hogander
7 * 7 *
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
10 *
8 * Copyright (C) 2005 Texas Instruments, Inc. 11 * Copyright (C) 2005 Texas Instruments, Inc.
9 * Richard Woodruff <r-woodruff2@ti.com> 12 * Richard Woodruff <r-woodruff2@ti.com>
10 * 13 *
@@ -22,12 +25,20 @@
22#include <linux/list.h> 25#include <linux/list.h>
23#include <linux/err.h> 26#include <linux/err.h>
24#include <linux/gpio.h> 27#include <linux/gpio.h>
28#include <linux/clk.h>
25 29
26#include <plat/sram.h> 30#include <plat/sram.h>
27#include <plat/clockdomain.h> 31#include <plat/clockdomain.h>
28#include <plat/powerdomain.h> 32#include <plat/powerdomain.h>
29#include <plat/control.h> 33#include <plat/control.h>
30#include <plat/serial.h> 34#include <plat/serial.h>
35#include <plat/sdrc.h>
36#include <plat/prcm.h>
37#include <plat/gpmc.h>
38#include <plat/dma.h>
39#include <plat/dmtimer.h>
40
41#include <asm/tlbflush.h>
31 42
32#include "cm.h" 43#include "cm.h"
33#include "cm-regbits-34xx.h" 44#include "cm-regbits-34xx.h"
@@ -35,6 +46,16 @@
35 46
36#include "prm.h" 47#include "prm.h"
37#include "pm.h" 48#include "pm.h"
49#include "sdrc.h"
50
51/* Scratchpad offsets */
52#define OMAP343X_TABLE_ADDRESS_OFFSET 0x31
53#define OMAP343X_TABLE_VALUE_OFFSET 0x30
54#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32
55
56u32 enable_off_mode;
57u32 sleep_while_idle;
58u32 wakeup_timer_seconds;
38 59
39struct power_state { 60struct power_state {
40 struct powerdomain *pwrdm; 61 struct powerdomain *pwrdm;
@@ -49,7 +70,114 @@ static LIST_HEAD(pwrst_list);
49 70
50static void (*_omap_sram_idle)(u32 *addr, int save_state); 71static void (*_omap_sram_idle)(u32 *addr, int save_state);
51 72
52static struct powerdomain *mpu_pwrdm; 73static int (*_omap_save_secure_sram)(u32 *addr);
74
75static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
76static struct powerdomain *core_pwrdm, *per_pwrdm;
77static struct powerdomain *cam_pwrdm;
78
79static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
80
81static inline void omap3_per_save_context(void)
82{
83 omap_gpio_save_context();
84}
85
86static inline void omap3_per_restore_context(void)
87{
88 omap_gpio_restore_context();
89}
90
91static void omap3_enable_io_chain(void)
92{
93 int timeout = 0;
94
95 if (omap_rev() >= OMAP3430_REV_ES3_1) {
96 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN);
97 /* Do a readback to assure write has been done */
98 prm_read_mod_reg(WKUP_MOD, PM_WKEN);
99
100 while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) &
101 OMAP3430_ST_IO_CHAIN)) {
102 timeout++;
103 if (timeout > 1000) {
104 printk(KERN_ERR "Wake up daisy chain "
105 "activation failed.\n");
106 return;
107 }
108 prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN,
109 WKUP_MOD, PM_WKST);
110 }
111 }
112}
113
114static void omap3_disable_io_chain(void)
115{
116 if (omap_rev() >= OMAP3430_REV_ES3_1)
117 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN);
118}
119
120static void omap3_core_save_context(void)
121{
122 u32 control_padconf_off;
123
124 /* Save the padconf registers */
125 control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
126 control_padconf_off |= START_PADCONF_SAVE;
127 omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
128 /* wait for the save to complete */
129 while (!omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
130 & PADCONF_SAVE_DONE)
131 ;
132 /* Save the Interrupt controller context */
133 omap_intc_save_context();
134 /* Save the GPMC context */
135 omap3_gpmc_save_context();
136 /* Save the system control module context, padconf already save above*/
137 omap3_control_save_context();
138 omap_dma_global_context_save();
139}
140
141static void omap3_core_restore_context(void)
142{
143 /* Restore the control module context, padconf restored by h/w */
144 omap3_control_restore_context();
145 /* Restore the GPMC context */
146 omap3_gpmc_restore_context();
147 /* Restore the interrupt controller context */
148 omap_intc_restore_context();
149 omap_dma_global_context_restore();
150}
151
152/*
153 * FIXME: This function should be called before entering off-mode after
154 * OMAP3 secure services have been accessed. Currently it is only called
155 * once during boot sequence, but this works as we are not using secure
156 * services.
157 */
158static void omap3_save_secure_ram_context(u32 target_mpu_state)
159{
160 u32 ret;
161
162 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
163 /*
164 * MPU next state must be set to POWER_ON temporarily,
165 * otherwise the WFI executed inside the ROM code
166 * will hang the system.
167 */
168 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
169 ret = _omap_save_secure_sram((u32 *)
170 __pa(omap3_secure_ram_storage));
171 pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
172 /* Following is for error tracking, it should not happen */
173 if (ret) {
174 printk(KERN_ERR "save_secure_sram() returns %08x\n",
175 ret);
176 while (1)
177 ;
178 }
179 }
180}
53 181
54/* 182/*
55 * PRCM Interrupt Handler Helper Function 183 * PRCM Interrupt Handler Helper Function
@@ -161,6 +289,35 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
161 return IRQ_HANDLED; 289 return IRQ_HANDLED;
162} 290}
163 291
292static void restore_control_register(u32 val)
293{
294 __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
295}
296
297/* Function to restore the table entry that was modified for enabling MMU */
298static void restore_table_entry(void)
299{
300 u32 *scratchpad_address;
301 u32 previous_value, control_reg_value;
302 u32 *address;
303
304 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
305
306 /* Get address of entry that was modified */
307 address = (u32 *)__raw_readl(scratchpad_address +
308 OMAP343X_TABLE_ADDRESS_OFFSET);
309 /* Get the previous value which needs to be restored */
310 previous_value = __raw_readl(scratchpad_address +
311 OMAP343X_TABLE_VALUE_OFFSET);
312 address = __va(address);
313 *address = previous_value;
314 flush_tlb_all();
315 control_reg_value = __raw_readl(scratchpad_address
316 + OMAP343X_CONTROL_REG_VALUE_OFFSET);
317 /* This will enable caches and prediction */
318 restore_control_register(control_reg_value);
319}
320
164static void omap_sram_idle(void) 321static void omap_sram_idle(void)
165{ 322{
166 /* Variable to tell what needs to be saved and restored 323 /* Variable to tell what needs to be saved and restored
@@ -169,17 +326,32 @@ static void omap_sram_idle(void)
169 /* save_state = 1 => Only L1 and logic lost */ 326 /* save_state = 1 => Only L1 and logic lost */
170 /* save_state = 2 => Only L2 lost */ 327 /* save_state = 2 => Only L2 lost */
171 /* save_state = 3 => L1, L2 and logic lost */ 328 /* save_state = 3 => L1, L2 and logic lost */
172 int save_state = 0, mpu_next_state; 329 int save_state = 0;
330 int mpu_next_state = PWRDM_POWER_ON;
331 int per_next_state = PWRDM_POWER_ON;
332 int core_next_state = PWRDM_POWER_ON;
333 int core_prev_state, per_prev_state;
334 u32 sdrc_pwr = 0;
335 int per_state_modified = 0;
173 336
174 if (!_omap_sram_idle) 337 if (!_omap_sram_idle)
175 return; 338 return;
176 339
340 pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
341 pwrdm_clear_all_prev_pwrst(neon_pwrdm);
342 pwrdm_clear_all_prev_pwrst(core_pwrdm);
343 pwrdm_clear_all_prev_pwrst(per_pwrdm);
344
177 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 345 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
178 switch (mpu_next_state) { 346 switch (mpu_next_state) {
347 case PWRDM_POWER_ON:
179 case PWRDM_POWER_RET: 348 case PWRDM_POWER_RET:
180 /* No need to save context */ 349 /* No need to save context */
181 save_state = 0; 350 save_state = 0;
182 break; 351 break;
352 case PWRDM_POWER_OFF:
353 save_state = 3;
354 break;
183 default: 355 default:
184 /* Invalid state */ 356 /* Invalid state */
185 printk(KERN_ERR "Invalid mpu state in sram_idle\n"); 357 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
@@ -187,21 +359,108 @@ static void omap_sram_idle(void)
187 } 359 }
188 pwrdm_pre_transition(); 360 pwrdm_pre_transition();
189 361
190 omap2_gpio_prepare_for_retention(); 362 /* NEON control */
191 omap_uart_prepare_idle(0); 363 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
192 omap_uart_prepare_idle(1); 364 set_pwrdm_state(neon_pwrdm, mpu_next_state);
193 omap_uart_prepare_idle(2); 365
366 /* PER */
367 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
368 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
369 if (per_next_state < PWRDM_POWER_ON) {
370 omap_uart_prepare_idle(2);
371 omap2_gpio_prepare_for_retention();
372 if (per_next_state == PWRDM_POWER_OFF) {
373 if (core_next_state == PWRDM_POWER_ON) {
374 per_next_state = PWRDM_POWER_RET;
375 pwrdm_set_next_pwrst(per_pwrdm, per_next_state);
376 per_state_modified = 1;
377 } else
378 omap3_per_save_context();
379 }
380 }
381
382 if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON)
383 omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]);
384
385 /* CORE */
386 if (core_next_state < PWRDM_POWER_ON) {
387 omap_uart_prepare_idle(0);
388 omap_uart_prepare_idle(1);
389 if (core_next_state == PWRDM_POWER_OFF) {
390 omap3_core_save_context();
391 omap3_prcm_save_context();
392 }
393 /* Enable IO-PAD and IO-CHAIN wakeups */
394 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
395 omap3_enable_io_chain();
396 }
194 397
195 _omap_sram_idle(NULL, save_state); 398 /*
399 * On EMU/HS devices ROM code restores a SRDC value
400 * from scratchpad which has automatic self refresh on timeout
401 * of AUTO_CNT = 1 enabled. This takes care of errata 1.142.
402 * Hence store/restore the SDRC_POWER register here.
403 */
404 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
405 omap_type() != OMAP2_DEVICE_TYPE_GP &&
406 core_next_state == PWRDM_POWER_OFF)
407 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
408
409 /*
410 * omap3_arm_context is the location where ARM registers
411 * get saved. The restore path then reads from this
412 * location and restores them back.
413 */
414 _omap_sram_idle(omap3_arm_context, save_state);
196 cpu_init(); 415 cpu_init();
197 416
198 omap_uart_resume_idle(2); 417 /* Restore normal SDRC POWER settings */
199 omap_uart_resume_idle(1); 418 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
200 omap_uart_resume_idle(0); 419 omap_type() != OMAP2_DEVICE_TYPE_GP &&
201 omap2_gpio_resume_after_retention(); 420 core_next_state == PWRDM_POWER_OFF)
421 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
422
423 /* Restore table entry modified during MMU restoration */
424 if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
425 restore_table_entry();
426
427 /* CORE */
428 if (core_next_state < PWRDM_POWER_ON) {
429 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
430 if (core_prev_state == PWRDM_POWER_OFF) {
431 omap3_core_restore_context();
432 omap3_prcm_restore_context();
433 omap3_sram_restore_context();
434 omap2_sms_restore_context();
435 }
436 omap_uart_resume_idle(0);
437 omap_uart_resume_idle(1);
438 if (core_next_state == PWRDM_POWER_OFF)
439 prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF,
440 OMAP3430_GR_MOD,
441 OMAP3_PRM_VOLTCTRL_OFFSET);
442 }
443
444 /* PER */
445 if (per_next_state < PWRDM_POWER_ON) {
446 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
447 if (per_prev_state == PWRDM_POWER_OFF)
448 omap3_per_restore_context();
449 omap2_gpio_resume_after_retention();
450 omap_uart_resume_idle(2);
451 if (per_state_modified)
452 pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF);
453 }
454
455 /* Disable IO-PAD and IO-CHAIN wakeup */
456 if (core_next_state < PWRDM_POWER_ON) {
457 prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
458 omap3_disable_io_chain();
459 }
202 460
203 pwrdm_post_transition(); 461 pwrdm_post_transition();
204 462
463 omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
205} 464}
206 465
207/* 466/*
@@ -246,6 +505,8 @@ static int omap3_fclks_active(void)
246 505
247static int omap3_can_sleep(void) 506static int omap3_can_sleep(void)
248{ 507{
508 if (!sleep_while_idle)
509 return 0;
249 if (!omap_uart_can_sleep()) 510 if (!omap_uart_can_sleep())
250 return 0; 511 return 0;
251 if (omap3_fclks_active()) 512 if (omap3_fclks_active())
@@ -319,6 +580,22 @@ out:
319#ifdef CONFIG_SUSPEND 580#ifdef CONFIG_SUSPEND
320static suspend_state_t suspend_state; 581static suspend_state_t suspend_state;
321 582
583static void omap2_pm_wakeup_on_timer(u32 seconds)
584{
585 u32 tick_rate, cycles;
586
587 if (!seconds)
588 return;
589
590 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
591 cycles = tick_rate * seconds;
592 omap_dm_timer_stop(gptimer_wakeup);
593 omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
594
595 pr_info("PM: Resume timer in %d secs (%d ticks at %d ticks/sec.)\n",
596 seconds, cycles, tick_rate);
597}
598
322static int omap3_pm_prepare(void) 599static int omap3_pm_prepare(void)
323{ 600{
324 disable_hlt(); 601 disable_hlt();
@@ -330,6 +607,9 @@ static int omap3_pm_suspend(void)
330 struct power_state *pwrst; 607 struct power_state *pwrst;
331 int state, ret = 0; 608 int state, ret = 0;
332 609
610 if (wakeup_timer_seconds)
611 omap2_pm_wakeup_on_timer(wakeup_timer_seconds);
612
333 /* Read current next_pwrsts */ 613 /* Read current next_pwrsts */
334 list_for_each_entry(pwrst, &pwrst_list, node) 614 list_for_each_entry(pwrst, &pwrst_list, node)
335 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 615 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
@@ -690,6 +970,22 @@ static void __init prcm_setup_regs(void)
690 omap3_d2d_idle(); 970 omap3_d2d_idle();
691} 971}
692 972
973void omap3_pm_off_mode_enable(int enable)
974{
975 struct power_state *pwrst;
976 u32 state;
977
978 if (enable)
979 state = PWRDM_POWER_OFF;
980 else
981 state = PWRDM_POWER_RET;
982
983 list_for_each_entry(pwrst, &pwrst_list, node) {
984 pwrst->next_state = state;
985 set_pwrdm_state(pwrst->pwrdm, state);
986 }
987}
988
693int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 989int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
694{ 990{
695 struct power_state *pwrst; 991 struct power_state *pwrst;
@@ -749,6 +1045,15 @@ static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
749 return 0; 1045 return 0;
750} 1046}
751 1047
1048void omap_push_sram_idle(void)
1049{
1050 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
1051 omap34xx_cpu_suspend_sz);
1052 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
1053 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
1054 save_secure_ram_context_sz);
1055}
1056
752static int __init omap3_pm_init(void) 1057static int __init omap3_pm_init(void)
753{ 1058{
754 struct power_state *pwrst, *tmp; 1059 struct power_state *pwrst, *tmp;
@@ -786,15 +1091,46 @@ static int __init omap3_pm_init(void)
786 goto err2; 1091 goto err2;
787 } 1092 }
788 1093
789 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, 1094 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
790 omap34xx_cpu_suspend_sz); 1095 per_pwrdm = pwrdm_lookup("per_pwrdm");
1096 core_pwrdm = pwrdm_lookup("core_pwrdm");
1097 cam_pwrdm = pwrdm_lookup("cam_pwrdm");
791 1098
1099 omap_push_sram_idle();
792#ifdef CONFIG_SUSPEND 1100#ifdef CONFIG_SUSPEND
793 suspend_set_ops(&omap_pm_ops); 1101 suspend_set_ops(&omap_pm_ops);
794#endif /* CONFIG_SUSPEND */ 1102#endif /* CONFIG_SUSPEND */
795 1103
796 pm_idle = omap3_pm_idle; 1104 pm_idle = omap3_pm_idle;
797 1105
1106 pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm);
1107 /*
1108 * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for
1109 * IO-pad wakeup. Otherwise it will unnecessarily waste power
1110 * waking up PER with every CORE wakeup - see
1111 * http://marc.info/?l=linux-omap&m=121852150710062&w=2
1112 */
1113 pwrdm_add_wkdep(per_pwrdm, core_pwrdm);
1114
1115 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
1116 omap3_secure_ram_storage =
1117 kmalloc(0x803F, GFP_KERNEL);
1118 if (!omap3_secure_ram_storage)
1119 printk(KERN_ERR "Memory allocation failed when"
1120 "allocating for secure sram context\n");
1121
1122 local_irq_disable();
1123 local_fiq_disable();
1124
1125 omap_dma_global_context_save();
1126 omap3_save_secure_ram_context(PWRDM_POWER_ON);
1127 omap_dma_global_context_restore();
1128
1129 local_irq_enable();
1130 local_fiq_enable();
1131 }
1132
1133 omap3_save_scratchpad_contents();
798err1: 1134err1:
799 return ret; 1135 return ret;
800err2: 1136err2:
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
index f70eb2da17e7..fd09b0827df0 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -338,7 +338,13 @@ static struct powerdomain usbhost_pwrdm = {
338 .sleepdep_srcs = dss_per_usbhost_sleepdeps, 338 .sleepdep_srcs = dss_per_usbhost_sleepdeps,
339 .pwrsts = PWRSTS_OFF_RET_ON, 339 .pwrsts = PWRSTS_OFF_RET_ON,
340 .pwrsts_logic_ret = PWRDM_POWER_RET, 340 .pwrsts_logic_ret = PWRDM_POWER_RET,
341 .flags = PWRDM_HAS_HDWR_SAR, /* for USBHOST ctrlr only */ 341 /*
342 * REVISIT: Enabling usb host save and restore mechanism seems to
343 * leave the usb host domain permanently in ACTIVE mode after
344 * changing the usb host power domain state from OFF to active once.
345 * Disabling for now.
346 */
347 /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
342 .banks = 1, 348 .banks = 1,
343 .pwrsts_mem_ret = { 349 .pwrsts_mem_ret = {
344 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ 350 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index b0d3ad05be2e..029d376198d4 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -7,6 +7,9 @@
7 * 7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com> 8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 * 9 *
10 * Copyright (C) 2007 Texas Instruments, Inc.
11 * Rajendra Nayak <rnayak@ti.com>
12 *
10 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc. 13 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
11 * 14 *
12 * This program is free software; you can redistribute it and/or modify 15 * This program is free software; you can redistribute it and/or modify
@@ -21,8 +24,11 @@
21 24
22#include <plat/common.h> 25#include <plat/common.h>
23#include <plat/prcm.h> 26#include <plat/prcm.h>
27#include <plat/irqs.h>
28#include <plat/control.h>
24 29
25#include "clock.h" 30#include "clock.h"
31#include "cm.h"
26#include "prm.h" 32#include "prm.h"
27#include "prm-regbits-24xx.h" 33#include "prm-regbits-24xx.h"
28 34
@@ -31,6 +37,89 @@ static void __iomem *cm_base;
31 37
32#define MAX_MODULE_ENABLE_WAIT 100000 38#define MAX_MODULE_ENABLE_WAIT 100000
33 39
40struct omap3_prcm_regs {
41 u32 control_padconf_sys_nirq;
42 u32 iva2_cm_clksel1;
43 u32 iva2_cm_clksel2;
44 u32 cm_sysconfig;
45 u32 sgx_cm_clksel;
46 u32 wkup_cm_clksel;
47 u32 dss_cm_clksel;
48 u32 cam_cm_clksel;
49 u32 per_cm_clksel;
50 u32 emu_cm_clksel;
51 u32 emu_cm_clkstctrl;
52 u32 pll_cm_autoidle2;
53 u32 pll_cm_clksel4;
54 u32 pll_cm_clksel5;
55 u32 pll_cm_clken;
56 u32 pll_cm_clken2;
57 u32 cm_polctrl;
58 u32 iva2_cm_fclken;
59 u32 iva2_cm_clken_pll;
60 u32 core_cm_fclken1;
61 u32 core_cm_fclken3;
62 u32 sgx_cm_fclken;
63 u32 wkup_cm_fclken;
64 u32 dss_cm_fclken;
65 u32 cam_cm_fclken;
66 u32 per_cm_fclken;
67 u32 usbhost_cm_fclken;
68 u32 core_cm_iclken1;
69 u32 core_cm_iclken2;
70 u32 core_cm_iclken3;
71 u32 sgx_cm_iclken;
72 u32 wkup_cm_iclken;
73 u32 dss_cm_iclken;
74 u32 cam_cm_iclken;
75 u32 per_cm_iclken;
76 u32 usbhost_cm_iclken;
77 u32 iva2_cm_autiidle2;
78 u32 mpu_cm_autoidle2;
79 u32 pll_cm_autoidle;
80 u32 iva2_cm_clkstctrl;
81 u32 mpu_cm_clkstctrl;
82 u32 core_cm_clkstctrl;
83 u32 sgx_cm_clkstctrl;
84 u32 dss_cm_clkstctrl;
85 u32 cam_cm_clkstctrl;
86 u32 per_cm_clkstctrl;
87 u32 neon_cm_clkstctrl;
88 u32 usbhost_cm_clkstctrl;
89 u32 core_cm_autoidle1;
90 u32 core_cm_autoidle2;
91 u32 core_cm_autoidle3;
92 u32 wkup_cm_autoidle;
93 u32 dss_cm_autoidle;
94 u32 cam_cm_autoidle;
95 u32 per_cm_autoidle;
96 u32 usbhost_cm_autoidle;
97 u32 sgx_cm_sleepdep;
98 u32 dss_cm_sleepdep;
99 u32 cam_cm_sleepdep;
100 u32 per_cm_sleepdep;
101 u32 usbhost_cm_sleepdep;
102 u32 cm_clkout_ctrl;
103 u32 prm_clkout_ctrl;
104 u32 sgx_pm_wkdep;
105 u32 dss_pm_wkdep;
106 u32 cam_pm_wkdep;
107 u32 per_pm_wkdep;
108 u32 neon_pm_wkdep;
109 u32 usbhost_pm_wkdep;
110 u32 core_pm_mpugrpsel1;
111 u32 iva2_pm_ivagrpsel1;
112 u32 core_pm_mpugrpsel3;
113 u32 core_pm_ivagrpsel3;
114 u32 wkup_pm_mpugrpsel;
115 u32 wkup_pm_ivagrpsel;
116 u32 per_pm_mpugrpsel;
117 u32 per_pm_ivagrpsel;
118 u32 wkup_pm_wken;
119};
120
121struct omap3_prcm_regs prcm_context;
122
34u32 omap_prcm_get_reset_sources(void) 123u32 omap_prcm_get_reset_sources(void)
35{ 124{
36 /* XXX This presumably needs modification for 34XX */ 125 /* XXX This presumably needs modification for 34XX */
@@ -46,9 +135,18 @@ void omap_prcm_arch_reset(char mode)
46 135
47 if (cpu_is_omap24xx()) 136 if (cpu_is_omap24xx())
48 prcm_offs = WKUP_MOD; 137 prcm_offs = WKUP_MOD;
49 else if (cpu_is_omap34xx()) 138 else if (cpu_is_omap34xx()) {
139 u32 l;
140
50 prcm_offs = OMAP3430_GR_MOD; 141 prcm_offs = OMAP3430_GR_MOD;
51 else 142 l = ('B' << 24) | ('M' << 16) | mode;
143 /* Reserve the first word in scratchpad for communicating
144 * with the boot ROM. A pointer to a data structure
145 * describing the boot process can be stored there,
146 * cf. OMAP34xx TRM, Initialization / Software Booting
147 * Configuration. */
148 omap_writel(l, OMAP343X_SCRATCHPAD + 4);
149 } else
52 WARN_ON(1); 150 WARN_ON(1);
53 151
54 prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL); 152 prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL);
@@ -168,3 +266,308 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
168 prm_base = omap2_globals->prm; 266 prm_base = omap2_globals->prm;
169 cm_base = omap2_globals->cm; 267 cm_base = omap2_globals->cm;
170} 268}
269
270#ifdef CONFIG_ARCH_OMAP3
271void omap3_prcm_save_context(void)
272{
273 prcm_context.control_padconf_sys_nirq =
274 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
275 prcm_context.iva2_cm_clksel1 =
276 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
277 prcm_context.iva2_cm_clksel2 =
278 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
279 prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
280 prcm_context.sgx_cm_clksel =
281 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
282 prcm_context.wkup_cm_clksel = cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
283 prcm_context.dss_cm_clksel =
284 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
285 prcm_context.cam_cm_clksel =
286 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
287 prcm_context.per_cm_clksel =
288 cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
289 prcm_context.emu_cm_clksel =
290 cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
291 prcm_context.emu_cm_clkstctrl =
292 cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSTCTRL);
293 prcm_context.pll_cm_autoidle2 =
294 cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
295 prcm_context.pll_cm_clksel4 =
296 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
297 prcm_context.pll_cm_clksel5 =
298 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
299 prcm_context.pll_cm_clken =
300 cm_read_mod_reg(PLL_MOD, CM_CLKEN);
301 prcm_context.pll_cm_clken2 =
302 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
303 prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
304 prcm_context.iva2_cm_fclken =
305 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
306 prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
307 OMAP3430_CM_CLKEN_PLL);
308 prcm_context.core_cm_fclken1 =
309 cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
310 prcm_context.core_cm_fclken3 =
311 cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
312 prcm_context.sgx_cm_fclken =
313 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
314 prcm_context.wkup_cm_fclken =
315 cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
316 prcm_context.dss_cm_fclken =
317 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
318 prcm_context.cam_cm_fclken =
319 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
320 prcm_context.per_cm_fclken =
321 cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
322 prcm_context.usbhost_cm_fclken =
323 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
324 prcm_context.core_cm_iclken1 =
325 cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
326 prcm_context.core_cm_iclken2 =
327 cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
328 prcm_context.core_cm_iclken3 =
329 cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
330 prcm_context.sgx_cm_iclken =
331 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
332 prcm_context.wkup_cm_iclken =
333 cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
334 prcm_context.dss_cm_iclken =
335 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
336 prcm_context.cam_cm_iclken =
337 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
338 prcm_context.per_cm_iclken =
339 cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
340 prcm_context.usbhost_cm_iclken =
341 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
342 prcm_context.iva2_cm_autiidle2 =
343 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
344 prcm_context.mpu_cm_autoidle2 =
345 cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
346 prcm_context.pll_cm_autoidle =
347 cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
348 prcm_context.iva2_cm_clkstctrl =
349 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL);
350 prcm_context.mpu_cm_clkstctrl =
351 cm_read_mod_reg(MPU_MOD, CM_CLKSTCTRL);
352 prcm_context.core_cm_clkstctrl =
353 cm_read_mod_reg(CORE_MOD, CM_CLKSTCTRL);
354 prcm_context.sgx_cm_clkstctrl =
355 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSTCTRL);
356 prcm_context.dss_cm_clkstctrl =
357 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSTCTRL);
358 prcm_context.cam_cm_clkstctrl =
359 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSTCTRL);
360 prcm_context.per_cm_clkstctrl =
361 cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSTCTRL);
362 prcm_context.neon_cm_clkstctrl =
363 cm_read_mod_reg(OMAP3430_NEON_MOD, CM_CLKSTCTRL);
364 prcm_context.usbhost_cm_clkstctrl =
365 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
366 prcm_context.core_cm_autoidle1 =
367 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
368 prcm_context.core_cm_autoidle2 =
369 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
370 prcm_context.core_cm_autoidle3 =
371 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
372 prcm_context.wkup_cm_autoidle =
373 cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
374 prcm_context.dss_cm_autoidle =
375 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
376 prcm_context.cam_cm_autoidle =
377 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
378 prcm_context.per_cm_autoidle =
379 cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
380 prcm_context.usbhost_cm_autoidle =
381 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
382 prcm_context.sgx_cm_sleepdep =
383 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);
384 prcm_context.dss_cm_sleepdep =
385 cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
386 prcm_context.cam_cm_sleepdep =
387 cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
388 prcm_context.per_cm_sleepdep =
389 cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
390 prcm_context.usbhost_cm_sleepdep =
391 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
392 prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD,
393 OMAP3_CM_CLKOUT_CTRL_OFFSET);
394 prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD,
395 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
396 prcm_context.sgx_pm_wkdep =
397 prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP);
398 prcm_context.dss_pm_wkdep =
399 prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP);
400 prcm_context.cam_pm_wkdep =
401 prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP);
402 prcm_context.per_pm_wkdep =
403 prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP);
404 prcm_context.neon_pm_wkdep =
405 prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP);
406 prcm_context.usbhost_pm_wkdep =
407 prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
408 prcm_context.core_pm_mpugrpsel1 =
409 prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1);
410 prcm_context.iva2_pm_ivagrpsel1 =
411 prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1);
412 prcm_context.core_pm_mpugrpsel3 =
413 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3);
414 prcm_context.core_pm_ivagrpsel3 =
415 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
416 prcm_context.wkup_pm_mpugrpsel =
417 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
418 prcm_context.wkup_pm_ivagrpsel =
419 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
420 prcm_context.per_pm_mpugrpsel =
421 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
422 prcm_context.per_pm_ivagrpsel =
423 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
424 prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
425 return;
426}
427
428void omap3_prcm_restore_context(void)
429{
430 omap_ctrl_writel(prcm_context.control_padconf_sys_nirq,
431 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
432 cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
433 CM_CLKSEL1);
434 cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
435 CM_CLKSEL2);
436 __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
437 cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
438 CM_CLKSEL);
439 cm_write_mod_reg(prcm_context.wkup_cm_clksel, WKUP_MOD, CM_CLKSEL);
440 cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
441 CM_CLKSEL);
442 cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
443 CM_CLKSEL);
444 cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD,
445 CM_CLKSEL);
446 cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
447 CM_CLKSEL1);
448 cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
449 CM_CLKSTCTRL);
450 cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
451 CM_AUTOIDLE2);
452 cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
453 OMAP3430ES2_CM_CLKSEL4);
454 cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
455 OMAP3430ES2_CM_CLKSEL5);
456 cm_write_mod_reg(prcm_context.pll_cm_clken, PLL_MOD, CM_CLKEN);
457 cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
458 OMAP3430ES2_CM_CLKEN2);
459 __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
460 cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
461 CM_FCLKEN);
462 cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
463 OMAP3430_CM_CLKEN_PLL);
464 cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1);
465 cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD,
466 OMAP3430ES2_CM_FCLKEN3);
467 cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
468 CM_FCLKEN);
469 cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
470 cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
471 CM_FCLKEN);
472 cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
473 CM_FCLKEN);
474 cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD,
475 CM_FCLKEN);
476 cm_write_mod_reg(prcm_context.usbhost_cm_fclken,
477 OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
478 cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1);
479 cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2);
480 cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3);
481 cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
482 CM_ICLKEN);
483 cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
484 cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
485 CM_ICLKEN);
486 cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
487 CM_ICLKEN);
488 cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD,
489 CM_ICLKEN);
490 cm_write_mod_reg(prcm_context.usbhost_cm_iclken,
491 OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
492 cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
493 CM_AUTOIDLE2);
494 cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
495 cm_write_mod_reg(prcm_context.pll_cm_autoidle, PLL_MOD, CM_AUTOIDLE);
496 cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
497 CM_CLKSTCTRL);
498 cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL);
499 cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD,
500 CM_CLKSTCTRL);
501 cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
502 CM_CLKSTCTRL);
503 cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
504 CM_CLKSTCTRL);
505 cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
506 CM_CLKSTCTRL);
507 cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
508 CM_CLKSTCTRL);
509 cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
510 CM_CLKSTCTRL);
511 cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl,
512 OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
513 cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD,
514 CM_AUTOIDLE1);
515 cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD,
516 CM_AUTOIDLE2);
517 cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD,
518 CM_AUTOIDLE3);
519 cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE);
520 cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
521 CM_AUTOIDLE);
522 cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
523 CM_AUTOIDLE);
524 cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD,
525 CM_AUTOIDLE);
526 cm_write_mod_reg(prcm_context.usbhost_cm_autoidle,
527 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
528 cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
529 OMAP3430_CM_SLEEPDEP);
530 cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
531 OMAP3430_CM_SLEEPDEP);
532 cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
533 OMAP3430_CM_SLEEPDEP);
534 cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
535 OMAP3430_CM_SLEEPDEP);
536 cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep,
537 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
538 cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
539 OMAP3_CM_CLKOUT_CTRL_OFFSET);
540 prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD,
541 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
542 prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD,
543 PM_WKDEP);
544 prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD,
545 PM_WKDEP);
546 prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD,
547 PM_WKDEP);
548 prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD,
549 PM_WKDEP);
550 prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD,
551 PM_WKDEP);
552 prm_write_mod_reg(prcm_context.usbhost_pm_wkdep,
553 OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
554 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD,
555 OMAP3430_PM_MPUGRPSEL1);
556 prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD,
557 OMAP3430_PM_IVAGRPSEL1);
558 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD,
559 OMAP3430ES2_PM_MPUGRPSEL3);
560 prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD,
561 OMAP3430ES2_PM_IVAGRPSEL3);
562 prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD,
563 OMAP3430_PM_MPUGRPSEL);
564 prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD,
565 OMAP3430_PM_IVAGRPSEL);
566 prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD,
567 OMAP3430_PM_MPUGRPSEL);
568 prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD,
569 OMAP3430_PM_IVAGRPSEL);
570 prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN);
571 return;
572}
573#endif
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index 9fd03a2ec95c..8f21bae6dc1c 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -365,6 +365,7 @@
365/* PM_PREPWSTST_GFX specific bits */ 365/* PM_PREPWSTST_GFX specific bits */
366 366
367/* PM_WKEN_WKUP specific bits */ 367/* PM_WKEN_WKUP specific bits */
368#define OMAP3430_EN_IO_CHAIN (1 << 16)
368#define OMAP3430_EN_IO (1 << 8) 369#define OMAP3430_EN_IO (1 << 8)
369#define OMAP3430_EN_GPIO1 (1 << 3) 370#define OMAP3430_EN_GPIO1 (1 << 3)
370 371
@@ -373,6 +374,7 @@
373/* PM_IVA2GRPSEL_WKUP specific bits */ 374/* PM_IVA2GRPSEL_WKUP specific bits */
374 375
375/* PM_WKST_WKUP specific bits */ 376/* PM_WKST_WKUP specific bits */
377#define OMAP3430_ST_IO_CHAIN (1 << 16)
376#define OMAP3430_ST_IO (1 << 8) 378#define OMAP3430_ST_IO (1 << 8)
377 379
378/* PRM_CLKSEL */ 380/* PRM_CLKSEL */
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index 07000de48f34..9a592199321c 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -37,12 +37,38 @@ static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
37void __iomem *omap2_sdrc_base; 37void __iomem *omap2_sdrc_base;
38void __iomem *omap2_sms_base; 38void __iomem *omap2_sms_base;
39 39
40struct omap2_sms_regs {
41 u32 sms_sysconfig;
42};
43
44static struct omap2_sms_regs sms_context;
45
40/* SDRC_POWER register bits */ 46/* SDRC_POWER register bits */
41#define SDRC_POWER_EXTCLKDIS_SHIFT 3 47#define SDRC_POWER_EXTCLKDIS_SHIFT 3
42#define SDRC_POWER_PWDENA_SHIFT 2 48#define SDRC_POWER_PWDENA_SHIFT 2
43#define SDRC_POWER_PAGEPOLICY_SHIFT 0 49#define SDRC_POWER_PAGEPOLICY_SHIFT 0
44 50
45/** 51/**
52 * omap2_sms_save_context - Save SMS registers
53 *
54 * Save SMS registers that need to be restored after off mode.
55 */
56void omap2_sms_save_context(void)
57{
58 sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG);
59}
60
61/**
62 * omap2_sms_restore_context - Restore SMS registers
63 *
64 * Restore SMS registers that need to be Restored after off mode.
65 */
66void omap2_sms_restore_context(void)
67{
68 sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG);
69}
70
71/**
46 * omap2_sdrc_get_params - return SDRC register values for a given clock rate 72 * omap2_sdrc_get_params - return SDRC register values for a given clock rate
47 * @r: SDRC clock rate (in Hz) 73 * @r: SDRC clock rate (in Hz)
48 * @sdrc_cs0: chip select 0 ram timings ** 74 * @sdrc_cs0: chip select 0 ram timings **
@@ -132,4 +158,5 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
132 l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) | 158 l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
133 (1 << SDRC_POWER_PAGEPOLICY_SHIFT); 159 (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
134 sdrc_write_reg(l, SDRC_POWER); 160 sdrc_write_reg(l, SDRC_POWER);
161 omap2_sms_save_context();
135} 162}
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index a5aecffe03ff..72df1b188135 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -155,8 +155,6 @@ static inline void __init omap_uart_reset(struct omap_uart_state *uart)
155 155
156#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) 156#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
157 157
158static int enable_off_mode; /* to be removed by full off-mode patches */
159
160static void omap_uart_save_context(struct omap_uart_state *uart) 158static void omap_uart_save_context(struct omap_uart_state *uart)
161{ 159{
162 u16 lcr = 0; 160 u16 lcr = 0;
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 6a749f2fea63..15268f8b61de 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -29,20 +29,33 @@
29#include <mach/io.h> 29#include <mach/io.h>
30#include <plat/control.h> 30#include <plat/control.h>
31 31
32#include "cm.h"
32#include "prm.h" 33#include "prm.h"
33#include "sdrc.h" 34#include "sdrc.h"
34 35
35#define PM_PREPWSTST_CORE_V OMAP34XX_PRM_REGADDR(CORE_MOD, \ 36#define PM_PREPWSTST_CORE_V OMAP34XX_PRM_REGADDR(CORE_MOD, \
36 OMAP3430_PM_PREPWSTST) 37 OMAP3430_PM_PREPWSTST)
38#define PM_PREPWSTST_CORE_P 0x48306AE8
37#define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \ 39#define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \
38 OMAP3430_PM_PREPWSTST) 40 OMAP3430_PM_PREPWSTST)
39#define PM_PWSTCTRL_MPU_P OMAP34XX_PRM_REGADDR(MPU_MOD, PM_PWSTCTRL) 41#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + PM_PWSTCTRL
42#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
43#define SRAM_BASE_P 0x40200000
44#define CONTROL_STAT 0x480022F0
40#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is 45#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is
41 * available */ 46 * available */
42#define SCRATCHPAD_BASE_P OMAP343X_CTRL_REGADDR(\ 47#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\
43 OMAP343X_CONTROL_MEM_WKUP +\ 48 + SCRATCHPAD_MEM_OFFS)
44 SCRATCHPAD_MEM_OFFS)
45#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) 49#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER)
50#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG)
51#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0)
52#define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0)
53#define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0)
54#define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1)
55#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1)
56#define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1)
57#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
58#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
46 59
47 .text 60 .text
48/* Function call to get the restore pointer for resume from OFF */ 61/* Function call to get the restore pointer for resume from OFF */
@@ -51,7 +64,93 @@ ENTRY(get_restore_pointer)
51 adr r0, restore 64 adr r0, restore
52 ldmfd sp!, {pc} @ restore regs and return 65 ldmfd sp!, {pc} @ restore regs and return
53ENTRY(get_restore_pointer_sz) 66ENTRY(get_restore_pointer_sz)
54 .word . - get_restore_pointer_sz 67 .word . - get_restore_pointer
68
69 .text
70/* Function call to get the restore pointer for for ES3 to resume from OFF */
71ENTRY(get_es3_restore_pointer)
72 stmfd sp!, {lr} @ save registers on stack
73 adr r0, restore_es3
74 ldmfd sp!, {pc} @ restore regs and return
75ENTRY(get_es3_restore_pointer_sz)
76 .word . - get_es3_restore_pointer
77
78ENTRY(es3_sdrc_fix)
79 ldr r4, sdrc_syscfg @ get config addr
80 ldr r5, [r4] @ get value
81 tst r5, #0x100 @ is part access blocked
82 it eq
83 biceq r5, r5, #0x100 @ clear bit if set
84 str r5, [r4] @ write back change
85 ldr r4, sdrc_mr_0 @ get config addr
86 ldr r5, [r4] @ get value
87 str r5, [r4] @ write back change
88 ldr r4, sdrc_emr2_0 @ get config addr
89 ldr r5, [r4] @ get value
90 str r5, [r4] @ write back change
91 ldr r4, sdrc_manual_0 @ get config addr
92 mov r5, #0x2 @ autorefresh command
93 str r5, [r4] @ kick off refreshes
94 ldr r4, sdrc_mr_1 @ get config addr
95 ldr r5, [r4] @ get value
96 str r5, [r4] @ write back change
97 ldr r4, sdrc_emr2_1 @ get config addr
98 ldr r5, [r4] @ get value
99 str r5, [r4] @ write back change
100 ldr r4, sdrc_manual_1 @ get config addr
101 mov r5, #0x2 @ autorefresh command
102 str r5, [r4] @ kick off refreshes
103 bx lr
104sdrc_syscfg:
105 .word SDRC_SYSCONFIG_P
106sdrc_mr_0:
107 .word SDRC_MR_0_P
108sdrc_emr2_0:
109 .word SDRC_EMR2_0_P
110sdrc_manual_0:
111 .word SDRC_MANUAL_0_P
112sdrc_mr_1:
113 .word SDRC_MR_1_P
114sdrc_emr2_1:
115 .word SDRC_EMR2_1_P
116sdrc_manual_1:
117 .word SDRC_MANUAL_1_P
118ENTRY(es3_sdrc_fix_sz)
119 .word . - es3_sdrc_fix
120
121/* Function to call rom code to save secure ram context */
122ENTRY(save_secure_ram_context)
123 stmfd sp!, {r1-r12, lr} @ save registers on stack
124save_secure_ram_debug:
125 /* b save_secure_ram_debug */ @ enable to debug save code
126 adr r3, api_params @ r3 points to parameters
127 str r0, [r3,#0x4] @ r0 has sdram address
128 ldr r12, high_mask
129 and r3, r3, r12
130 ldr r12, sram_phy_addr_mask
131 orr r3, r3, r12
132 mov r0, #25 @ set service ID for PPA
133 mov r12, r0 @ copy secure service ID in r12
134 mov r1, #0 @ set task id for ROM code in r1
135 mov r2, #4 @ set some flags in r2, r6
136 mov r6, #0xff
137 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
138 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
139 .word 0xE1600071 @ call SMI monitor (smi #1)
140 nop
141 nop
142 nop
143 nop
144 ldmfd sp!, {r1-r12, pc}
145sram_phy_addr_mask:
146 .word SRAM_BASE_P
147high_mask:
148 .word 0xffff
149api_params:
150 .word 0x4, 0x0, 0x0, 0x1, 0x1
151ENTRY(save_secure_ram_context_sz)
152 .word . - save_secure_ram_context
153
55/* 154/*
56 * Forces OMAP into idle state 155 * Forces OMAP into idle state
57 * 156 *
@@ -92,11 +191,29 @@ loop:
92 nop 191 nop
93 nop 192 nop
94 nop 193 nop
95 bl i_dll_wait 194 bl wait_sdrc_ok
96 195
97 ldmfd sp!, {r0-r12, pc} @ restore regs and return 196 ldmfd sp!, {r0-r12, pc} @ restore regs and return
197restore_es3:
198 /*b restore_es3*/ @ Enable to debug restore code
199 ldr r5, pm_prepwstst_core_p
200 ldr r4, [r5]
201 and r4, r4, #0x3
202 cmp r4, #0x0 @ Check if previous power state of CORE is OFF
203 bne restore
204 adr r0, es3_sdrc_fix
205 ldr r1, sram_base
206 ldr r2, es3_sdrc_fix_sz
207 mov r2, r2, ror #2
208copy_to_sram:
209 ldmia r0!, {r3} @ val = *src
210 stmia r1!, {r3} @ *dst = val
211 subs r2, r2, #0x1 @ num_words--
212 bne copy_to_sram
213 ldr r1, sram_base
214 blx r1
98restore: 215restore:
99 /* b restore*/ @ Enable to debug restore code 216 /* b restore*/ @ Enable to debug restore code
100 /* Check what was the reason for mpu reset and store the reason in r9*/ 217 /* Check what was the reason for mpu reset and store the reason in r9*/
101 /* 1 - Only L1 and logic lost */ 218 /* 1 - Only L1 and logic lost */
102 /* 2 - Only L2 lost - In this case, we wont be here */ 219 /* 2 - Only L2 lost - In this case, we wont be here */
@@ -108,9 +225,44 @@ restore:
108 moveq r9, #0x3 @ MPU OFF => L1 and L2 lost 225 moveq r9, #0x3 @ MPU OFF => L1 and L2 lost
109 movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation 226 movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation
110 bne logic_l1_restore 227 bne logic_l1_restore
228 ldr r0, control_stat
229 ldr r1, [r0]
230 and r1, #0x700
231 cmp r1, #0x300
232 beq l2_inv_gp
233 mov r0, #40 @ set service ID for PPA
234 mov r12, r0 @ copy secure Service ID in r12
235 mov r1, #0 @ set task id for ROM code in r1
236 mov r2, #4 @ set some flags in r2, r6
237 mov r6, #0xff
238 adr r3, l2_inv_api_params @ r3 points to dummy parameters
239 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
240 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
241 .word 0xE1600071 @ call SMI monitor (smi #1)
242 /* Write to Aux control register to set some bits */
243 mov r0, #42 @ set service ID for PPA
244 mov r12, r0 @ copy secure Service ID in r12
245 mov r1, #0 @ set task id for ROM code in r1
246 mov r2, #4 @ set some flags in r2, r6
247 mov r6, #0xff
248 adr r3, write_aux_control_params @ r3 points to parameters
249 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
250 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
251 .word 0xE1600071 @ call SMI monitor (smi #1)
252
253 b logic_l1_restore
254l2_inv_api_params:
255 .word 0x1, 0x00
256write_aux_control_params:
257 .word 0x1, 0x72
258l2_inv_gp:
111 /* Execute smi to invalidate L2 cache */ 259 /* Execute smi to invalidate L2 cache */
112 mov r12, #0x1 @ set up to invalide L2 260 mov r12, #0x1 @ set up to invalide L2
113smi: .word 0xE1600070 @ Call SMI monitor (smieq) 261smi: .word 0xE1600070 @ Call SMI monitor (smieq)
262 /* Write to Aux control register to set some bits */
263 mov r0, #0x72
264 mov r12, #0x3
265 .word 0xE1600070 @ Call SMI monitor (smieq)
114logic_l1_restore: 266logic_l1_restore:
115 mov r1, #0 267 mov r1, #0
116 /* Invalidate all instruction caches to PoU 268 /* Invalidate all instruction caches to PoU
@@ -391,33 +543,55 @@ skip_l2_inval:
391 nop 543 nop
392 nop 544 nop
393 nop 545 nop
394 bl i_dll_wait 546 bl wait_sdrc_ok
395 /* restore regs and return */ 547 /* restore regs and return */
396 ldmfd sp!, {r0-r12, pc} 548 ldmfd sp!, {r0-r12, pc}
397 549
398i_dll_wait: 550/* Make sure SDRC accesses are ok */
399 ldr r4, clk_stabilize_delay 551wait_sdrc_ok:
552 ldr r4, cm_idlest1_core
553 ldr r5, [r4]
554 and r5, r5, #0x2
555 cmp r5, #0
556 bne wait_sdrc_ok
557 ldr r4, sdrc_power
558 ldr r5, [r4]
559 bic r5, r5, #0x40
560 str r5, [r4]
561wait_dll_lock:
562 /* Is dll in lock mode? */
563 ldr r4, sdrc_dlla_ctrl
564 ldr r5, [r4]
565 tst r5, #0x4
566 bxne lr
567 /* wait till dll locks */
568 ldr r4, sdrc_dlla_status
569 ldr r5, [r4]
570 and r5, r5, #0x4
571 cmp r5, #0x4
572 bne wait_dll_lock
573 bx lr
400 574
401i_dll_delay: 575cm_idlest1_core:
402 subs r4, r4, #0x1 576 .word CM_IDLEST1_CORE_V
403 bne i_dll_delay 577sdrc_dlla_status:
404 ldr r4, sdrc_power 578 .word SDRC_DLLA_STATUS_V
405 ldr r5, [r4] 579sdrc_dlla_ctrl:
406 bic r5, r5, #0x40 580 .word SDRC_DLLA_CTRL_V
407 str r5, [r4]
408 bx lr
409pm_prepwstst_core: 581pm_prepwstst_core:
410 .word PM_PREPWSTST_CORE_V 582 .word PM_PREPWSTST_CORE_V
583pm_prepwstst_core_p:
584 .word PM_PREPWSTST_CORE_P
411pm_prepwstst_mpu: 585pm_prepwstst_mpu:
412 .word PM_PREPWSTST_MPU_V 586 .word PM_PREPWSTST_MPU_V
413pm_pwstctrl_mpu: 587pm_pwstctrl_mpu:
414 .word PM_PWSTCTRL_MPU_P 588 .word PM_PWSTCTRL_MPU_P
415scratchpad_base: 589scratchpad_base:
416 .word SCRATCHPAD_BASE_P 590 .word SCRATCHPAD_BASE_P
591sram_base:
592 .word SRAM_BASE_P + 0x8000
417sdrc_power: 593sdrc_power:
418 .word SDRC_POWER_V 594 .word SDRC_POWER_V
419context_mem:
420 .word 0x803E3E14
421clk_stabilize_delay: 595clk_stabilize_delay:
422 .word 0x000001FF 596 .word 0x000001FF
423assoc_mask: 597assoc_mask:
@@ -432,5 +606,7 @@ table_entry:
432 .word 0x00000C02 606 .word 0x00000C02
433cache_pred_disable_mask: 607cache_pred_disable_mask:
434 .word 0xFFFFE7FB 608 .word 0xFFFFE7FB
609control_stat:
610 .word CONTROL_STAT
435ENTRY(omap34xx_cpu_suspend_sz) 611ENTRY(omap34xx_cpu_suspend_sz)
436 .word . - omap34xx_cpu_suspend 612 .word . - omap34xx_cpu_suspend
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index df2b7094de98..cd04deaa88c5 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -47,6 +47,7 @@ static struct omap_dm_timer *gptimer;
47static struct clock_event_device clockevent_gpt; 47static struct clock_event_device clockevent_gpt;
48static u8 __initdata gptimer_id = 1; 48static u8 __initdata gptimer_id = 1;
49static u8 __initdata inited; 49static u8 __initdata inited;
50struct omap_dm_timer *gptimer_wakeup;
50 51
51static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) 52static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
52{ 53{
@@ -134,6 +135,7 @@ static void __init omap2_gp_clockevent_init(void)
134 135
135 gptimer = omap_dm_timer_request_specific(gptimer_id); 136 gptimer = omap_dm_timer_request_specific(gptimer_id);
136 BUG_ON(gptimer == NULL); 137 BUG_ON(gptimer == NULL);
138 gptimer_wakeup = gptimer;
137 139
138#if defined(CONFIG_OMAP_32K_TIMER) 140#if defined(CONFIG_OMAP_32K_TIMER)
139 src = OMAP_TIMER_SRC_32_KHZ; 141 src = OMAP_TIMER_SRC_32_KHZ;
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 3edffde7f439..8836da32d63b 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -54,6 +54,12 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
54 54
55static int enable_1510_mode; 55static int enable_1510_mode;
56 56
57static struct omap_dma_global_context_registers {
58 u32 dma_irqenable_l0;
59 u32 dma_ocp_sysconfig;
60 u32 dma_gcr;
61} omap_dma_global_context;
62
57struct omap_dma_lch { 63struct omap_dma_lch {
58 int next_lch; 64 int next_lch;
59 int dev_id; 65 int dev_id;
@@ -2341,6 +2347,39 @@ void omap_stop_lcd_dma(void)
2341} 2347}
2342EXPORT_SYMBOL(omap_stop_lcd_dma); 2348EXPORT_SYMBOL(omap_stop_lcd_dma);
2343 2349
2350void omap_dma_global_context_save(void)
2351{
2352 omap_dma_global_context.dma_irqenable_l0 =
2353 dma_read(IRQENABLE_L0);
2354 omap_dma_global_context.dma_ocp_sysconfig =
2355 dma_read(OCP_SYSCONFIG);
2356 omap_dma_global_context.dma_gcr = dma_read(GCR);
2357}
2358
2359void omap_dma_global_context_restore(void)
2360{
2361 int ch;
2362
2363 dma_write(omap_dma_global_context.dma_gcr, GCR);
2364 dma_write(omap_dma_global_context.dma_ocp_sysconfig,
2365 OCP_SYSCONFIG);
2366 dma_write(omap_dma_global_context.dma_irqenable_l0,
2367 IRQENABLE_L0);
2368
2369 /*
2370 * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
2371 * after secure sram context save and restore. Hence we need to
2372 * manually clear those IRQs to avoid spurious interrupts. This
2373 * affects only secure devices.
2374 */
2375 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
2376 dma_write(0x3 , IRQSTATUS_L0);
2377
2378 for (ch = 0; ch < dma_chan_count; ch++)
2379 if (dma_chan[ch].dev_id != -1)
2380 omap_clear_dma(ch);
2381}
2382
2344/*----------------------------------------------------------------------------*/ 2383/*----------------------------------------------------------------------------*/
2345 2384
2346static int __init omap_init_dma(void) 2385static int __init omap_init_dma(void)
@@ -2476,8 +2515,8 @@ static int __init omap_init_dma(void)
2476 setup_irq(irq, &omap24xx_dma_irq); 2515 setup_irq(irq, &omap24xx_dma_irq);
2477 } 2516 }
2478 2517
2479 /* Enable smartidle idlemodes and autoidle */
2480 if (cpu_is_omap34xx()) { 2518 if (cpu_is_omap34xx()) {
2519 /* Enable smartidle idlemodes and autoidle */
2481 u32 v = dma_read(OCP_SYSCONFIG); 2520 u32 v = dma_read(OCP_SYSCONFIG);
2482 v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK | 2521 v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
2483 DMA_SYSCONFIG_SIDLEMODE_MASK | 2522 DMA_SYSCONFIG_SIDLEMODE_MASK |
@@ -2486,6 +2525,13 @@ static int __init omap_init_dma(void)
2486 DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) | 2525 DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2487 DMA_SYSCONFIG_AUTOIDLE); 2526 DMA_SYSCONFIG_AUTOIDLE);
2488 dma_write(v , OCP_SYSCONFIG); 2527 dma_write(v , OCP_SYSCONFIG);
2528 /* reserve dma channels 0 and 1 in high security devices */
2529 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
2530 printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
2531 "HS ROM code\n");
2532 dma_chan[0].dev_id = 0;
2533 dma_chan[1].dev_id = 1;
2534 }
2489 } 2535 }
2490 2536
2491 2537
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 35a59ce5a2b4..b71052c6581b 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -290,6 +290,23 @@ static struct gpio_bank gpio_bank_34xx[6] = {
290 METHOD_GPIO_24XX }, 290 METHOD_GPIO_24XX },
291}; 291};
292 292
293struct omap3_gpio_regs {
294 u32 sysconfig;
295 u32 irqenable1;
296 u32 irqenable2;
297 u32 wake_en;
298 u32 ctrl;
299 u32 oe;
300 u32 leveldetect0;
301 u32 leveldetect1;
302 u32 risingdetect;
303 u32 fallingdetect;
304 u32 dataout;
305 u32 setwkuena;
306 u32 setdataout;
307};
308
309static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
293#endif 310#endif
294 311
295#ifdef CONFIG_ARCH_OMAP4 312#ifdef CONFIG_ARCH_OMAP4
@@ -2036,6 +2053,81 @@ void omap2_gpio_resume_after_retention(void)
2036 2053
2037#endif 2054#endif
2038 2055
2056#ifdef CONFIG_ARCH_OMAP34XX
2057/* save the registers of bank 2-6 */
2058void omap_gpio_save_context(void)
2059{
2060 int i;
2061
2062 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2063 for (i = 1; i < gpio_bank_count; i++) {
2064 struct gpio_bank *bank = &gpio_bank[i];
2065 gpio_context[i].sysconfig =
2066 __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
2067 gpio_context[i].irqenable1 =
2068 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2069 gpio_context[i].irqenable2 =
2070 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2071 gpio_context[i].wake_en =
2072 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2073 gpio_context[i].ctrl =
2074 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2075 gpio_context[i].oe =
2076 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2077 gpio_context[i].leveldetect0 =
2078 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2079 gpio_context[i].leveldetect1 =
2080 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2081 gpio_context[i].risingdetect =
2082 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2083 gpio_context[i].fallingdetect =
2084 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2085 gpio_context[i].dataout =
2086 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
2087 gpio_context[i].setwkuena =
2088 __raw_readl(bank->base + OMAP24XX_GPIO_SETWKUENA);
2089 gpio_context[i].setdataout =
2090 __raw_readl(bank->base + OMAP24XX_GPIO_SETDATAOUT);
2091 }
2092}
2093
2094/* restore the required registers of bank 2-6 */
2095void omap_gpio_restore_context(void)
2096{
2097 int i;
2098
2099 for (i = 1; i < gpio_bank_count; i++) {
2100 struct gpio_bank *bank = &gpio_bank[i];
2101 __raw_writel(gpio_context[i].sysconfig,
2102 bank->base + OMAP24XX_GPIO_SYSCONFIG);
2103 __raw_writel(gpio_context[i].irqenable1,
2104 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2105 __raw_writel(gpio_context[i].irqenable2,
2106 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2107 __raw_writel(gpio_context[i].wake_en,
2108 bank->base + OMAP24XX_GPIO_WAKE_EN);
2109 __raw_writel(gpio_context[i].ctrl,
2110 bank->base + OMAP24XX_GPIO_CTRL);
2111 __raw_writel(gpio_context[i].oe,
2112 bank->base + OMAP24XX_GPIO_OE);
2113 __raw_writel(gpio_context[i].leveldetect0,
2114 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2115 __raw_writel(gpio_context[i].leveldetect1,
2116 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2117 __raw_writel(gpio_context[i].risingdetect,
2118 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2119 __raw_writel(gpio_context[i].fallingdetect,
2120 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2121 __raw_writel(gpio_context[i].dataout,
2122 bank->base + OMAP24XX_GPIO_DATAOUT);
2123 __raw_writel(gpio_context[i].setwkuena,
2124 bank->base + OMAP24XX_GPIO_SETWKUENA);
2125 __raw_writel(gpio_context[i].setdataout,
2126 bank->base + OMAP24XX_GPIO_SETDATAOUT);
2127 }
2128}
2129#endif
2130
2039/* 2131/*
2040 * This may get called early from board specific init 2132 * This may get called early from board specific init
2041 * for boards that have interrupts routed via FPGA. 2133 * for boards that have interrupts routed via FPGA.
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
index 805819f3a868..8237cb9e74fd 100644
--- a/arch/arm/plat-omap/include/plat/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -112,6 +112,8 @@
112#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0) 112#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
113#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4) 113#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
114 114
115#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
116
115/* 34xx-only CONTROL_GENERAL register offsets */ 117/* 34xx-only CONTROL_GENERAL register offsets */
116#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000) 118#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000)
117#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008) 119#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008)
@@ -144,8 +146,51 @@
144#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) 146#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
145#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) 147#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
146#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) 148#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
147#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02b0) 149#define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \
148#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4) 150 + ((i) >> 1) * 4 + (!(i) & 1) * 2)
151#define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4)
152#define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8)
153#define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0)
154#define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4)
155#define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8)
156#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
157#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0)
158#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4)
159#define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8)
160#define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0)
161#define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4)
162
163
164/* 34xx PADCONF register offsets */
165#define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
166 (i)*2)
167#define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0)
168#define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1)
169#define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2)
170#define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3)
171#define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4)
172#define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5)
173#define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6)
174#define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7)
175#define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8)
176#define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9)
177#define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10)
178#define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11)
179#define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12)
180#define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13)
181#define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14)
182#define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15)
183#define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16)
184#define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17)
185
186/* 34xx GENERAL_WKUP regist offsets */
187#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
188 0x008 + (i))
189#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
190#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
191#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
192#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
193#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
149 194
150/* 34xx D2D idle-related pins, handled by PM core */ 195/* 34xx D2D idle-related pins, handled by PM core */
151#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 196#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
@@ -205,6 +250,10 @@
205#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15) 250#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15)
206#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14) 251#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
207 252
253#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860)
254#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910)
255#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
256
208#ifndef __ASSEMBLY__ 257#ifndef __ASSEMBLY__
209#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ 258#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
210 defined(CONFIG_ARCH_OMAP4) 259 defined(CONFIG_ARCH_OMAP4)
@@ -215,6 +264,15 @@ extern u32 omap_ctrl_readl(u16 offset);
215extern void omap_ctrl_writeb(u8 val, u16 offset); 264extern void omap_ctrl_writeb(u8 val, u16 offset);
216extern void omap_ctrl_writew(u16 val, u16 offset); 265extern void omap_ctrl_writew(u16 val, u16 offset);
217extern void omap_ctrl_writel(u32 val, u16 offset); 266extern void omap_ctrl_writel(u32 val, u16 offset);
267
268extern void omap3_save_scratchpad_contents(void);
269extern void omap3_clear_scratchpad_contents(void);
270extern u32 *get_restore_pointer(void);
271extern u32 *get_es3_restore_pointer(void);
272extern u32 omap3_arm_context[128];
273extern void omap3_control_save_context(void);
274extern void omap3_control_restore_context(void);
275
218#else 276#else
219#define omap_ctrl_base_get() 0 277#define omap_ctrl_base_get() 0
220#define omap_ctrl_readb(x) 0 278#define omap_ctrl_readb(x) 0
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index 72f680b7180d..1c017b29b7e9 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -633,6 +633,11 @@ extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
633extern void omap_set_dma_src_endian_type(int lch, enum end_type etype); 633extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
634extern int omap_get_dma_index(int lch, int *ei, int *fi); 634extern int omap_get_dma_index(int lch, int *ei, int *fi);
635 635
636void omap_dma_global_context_save(void);
637void omap_dma_global_context_restore(void);
638
639extern void omap_dma_disable_irq(int lch);
640
636/* Chaining APIs */ 641/* Chaining APIs */
637#ifndef CONFIG_ARCH_OMAP1 642#ifndef CONFIG_ARCH_OMAP1
638extern int omap_request_dma_chain(int dev_id, const char *dev_name, 643extern int omap_request_dma_chain(int dev_id, const char *dev_name,
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 633ff688b928..de7c54731cbe 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -76,7 +76,8 @@ extern void omap2_gpio_prepare_for_retention(void);
76extern void omap2_gpio_resume_after_retention(void); 76extern void omap2_gpio_resume_after_retention(void);
77extern void omap_set_gpio_debounce(int gpio, int enable); 77extern void omap_set_gpio_debounce(int gpio, int enable);
78extern void omap_set_gpio_debounce_time(int gpio, int enable); 78extern void omap_set_gpio_debounce_time(int gpio, int enable);
79 79extern void omap_gpio_save_context(void);
80extern void omap_gpio_restore_context(void);
80/*-------------------------------------------------------------------------*/ 81/*-------------------------------------------------------------------------*/
81 82
82/* Wrappers for "new style" GPIO calls, using the new infrastructure 83/* Wrappers for "new style" GPIO calls, using the new infrastructure
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 9c99cda77ba6..696e0ca051b7 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -52,6 +52,7 @@
52#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) 52#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
53#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2)) 53#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
54#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) 54#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
55#define GPMC_CONFIG7_CSVALID (1 << 6)
55 56
56/* 57/*
57 * Note that all values in this struct are in nanoseconds, while 58 * Note that all values in this struct are in nanoseconds, while
@@ -107,6 +108,8 @@ extern int gpmc_prefetch_enable(int cs, int dma_mode,
107 unsigned int u32_count, int is_write); 108 unsigned int u32_count, int is_write);
108extern void gpmc_prefetch_reset(void); 109extern void gpmc_prefetch_reset(void);
109extern int gpmc_prefetch_status(void); 110extern int gpmc_prefetch_status(void);
111extern void omap3_gpmc_save_context(void);
112extern void omap3_gpmc_restore_context(void);
110extern void __init gpmc_init(void); 113extern void __init gpmc_init(void);
111 114
112#endif 115#endif
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 6a6d0281e1d5..ce5dd2d1dc21 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -477,9 +477,14 @@
477 477
478#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) 478#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
479 479
480#define INTCPS_NR_MIR_REGS 3
481#define INTCPS_NR_IRQS 96
482
480#ifndef __ASSEMBLY__ 483#ifndef __ASSEMBLY__
481extern void omap_init_irq(void); 484extern void omap_init_irq(void);
482extern int omap_irq_pending(void); 485extern int omap_irq_pending(void);
486void omap_intc_save_context(void);
487void omap_intc_restore_context(void);
483#endif 488#endif
484 489
485#include <mach/hardware.h> 490#include <mach/hardware.h>
diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h
index cda2a70397b4..e63e94e18975 100644
--- a/arch/arm/plat-omap/include/plat/prcm.h
+++ b/arch/arm/plat-omap/include/plat/prcm.h
@@ -27,9 +27,13 @@ u32 omap_prcm_get_reset_sources(void);
27void omap_prcm_arch_reset(char mode); 27void omap_prcm_arch_reset(char mode);
28int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name); 28int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name);
29 29
30#endif 30#define START_PADCONF_SAVE 0x2
31#define PADCONF_SAVE_DONE 0x1
31 32
33void omap3_prcm_save_context(void);
34void omap3_prcm_restore_context(void);
32 35
36#endif
33 37
34 38
35 39
diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
index 7b58a5f78ce4..f704030d2a70 100644
--- a/arch/arm/plat-omap/include/plat/sdrc.h
+++ b/arch/arm/plat-omap/include/plat/sdrc.h
@@ -44,6 +44,12 @@
44#define SDRC_RFR_CTRL_1 0x0D4 44#define SDRC_RFR_CTRL_1 0x0D4
45#define SDRC_MANUAL_1 0x0D8 45#define SDRC_MANUAL_1 0x0D8
46 46
47#define SDRC_POWER_AUTOCOUNT_SHIFT 8
48#define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
49#define SDRC_POWER_CLKCTRL_SHIFT 4
50#define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
51#define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
52
47/* 53/*
48 * These values represent the number of memory clock cycles between 54 * These values represent the number of memory clock cycles between
49 * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192 55 * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192
@@ -120,6 +126,8 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
120int omap2_sdrc_get_params(unsigned long r, 126int omap2_sdrc_get_params(unsigned long r,
121 struct omap_sdrc_params **sdrc_cs0, 127 struct omap_sdrc_params **sdrc_cs0,
122 struct omap_sdrc_params **sdrc_cs1); 128 struct omap_sdrc_params **sdrc_cs1);
129void omap2_sms_save_context(void);
130void omap2_sms_restore_context(void);
123 131
124#ifdef CONFIG_ARCH_OMAP2 132#ifdef CONFIG_ARCH_OMAP2
125 133
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 8974e3fc2691..16a1b458d53c 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -27,6 +27,7 @@ extern u32 omap3_configure_core_dpll(
27 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0, 27 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
28 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1, 28 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
29 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1); 29 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
30extern void omap3_sram_restore_context(void);
30 31
31/* Do not use these */ 32/* Do not use these */
32extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); 33extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
@@ -68,4 +69,10 @@ extern u32 omap3_sram_configure_core_dpll(
68 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1); 69 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
69extern unsigned long omap3_sram_configure_core_dpll_sz; 70extern unsigned long omap3_sram_configure_core_dpll_sz;
70 71
72#ifdef CONFIG_PM
73extern void omap_push_sram_idle(void);
74#else
75static inline void omap_push_sram_idle(void) {}
76#endif /* CONFIG_PM */
77
71#endif 78#endif
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index a53aa8541730..3e923668778d 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -396,22 +396,24 @@ u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
396 sdrc_actim_ctrl_b_1, sdrc_mr_1); 396 sdrc_actim_ctrl_b_1, sdrc_mr_1);
397} 397}
398 398
399/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ 399#ifdef CONFIG_PM
400void restore_sram_functions(void) 400void omap3_sram_restore_context(void)
401{ 401{
402 omap_sram_ceil = omap_sram_base + omap_sram_size; 402 omap_sram_ceil = omap_sram_base + omap_sram_size;
403 403
404 _omap3_sram_configure_core_dpll = 404 _omap3_sram_configure_core_dpll =
405 omap_sram_push(omap3_sram_configure_core_dpll, 405 omap_sram_push(omap3_sram_configure_core_dpll,
406 omap3_sram_configure_core_dpll_sz); 406 omap3_sram_configure_core_dpll_sz);
407 omap_push_sram_idle();
407} 408}
409#endif /* CONFIG_PM */
408 410
409int __init omap34xx_sram_init(void) 411int __init omap34xx_sram_init(void)
410{ 412{
411 _omap3_sram_configure_core_dpll = 413 _omap3_sram_configure_core_dpll =
412 omap_sram_push(omap3_sram_configure_core_dpll, 414 omap_sram_push(omap3_sram_configure_core_dpll,
413 omap3_sram_configure_core_dpll_sz); 415 omap3_sram_configure_core_dpll_sz);
414 416 omap_push_sram_idle();
415 return 0; 417 return 0;
416} 418}
417#else 419#else
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-14 08:21:10 -0500