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authorBryan Wu <bryan.wu@analog.com>2007-07-12 05:26:31 -0400
committerBryan Wu <bryan.wu@analog.com>2007-07-12 05:26:31 -0400
commitc04d66bbbdbbc7b5d55c42795f29e494190f8fb3 (patch)
tree2622e8b87db8c42d2b613b3a48eaa3bec7fcc0fc
parent1d1894749cca89f4bb013364524199b3015d7b00 (diff)
Blackfin arch: clean up some coding style issues
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
-rw-r--r--arch/blackfin/mach-common/ints-priority-dc.c4
-rw-r--r--arch/blackfin/mach-common/ints-priority-sc.c13
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF54x_base.h1
-rw-r--r--include/asm-blackfin/mach-bf561/cdefBF561.h1
-rw-r--r--include/asm-blackfin/mman.h2
5 files changed, 8 insertions, 13 deletions
diff --git a/arch/blackfin/mach-common/ints-priority-dc.c b/arch/blackfin/mach-common/ints-priority-dc.c
index 7977c2c40867..6b9fd03ce835 100644
--- a/arch/blackfin/mach-common/ints-priority-dc.c
+++ b/arch/blackfin/mach-common/ints-priority-dc.c
@@ -371,8 +371,8 @@ int __init init_arch_irq(void)
371 bfin_write_SICA_IMASK1(SIC_UNMASK_ALL); 371 bfin_write_SICA_IMASK1(SIC_UNMASK_ALL);
372 SSYNC(); 372 SSYNC();
373 373
374 bfin_write_SICA_IWR0(IWR_ENABLE_ALL); 374 bfin_write_SICA_IWR0(IWR_ENABLE_ALL);
375 bfin_write_SICA_IWR1(IWR_ENABLE_ALL); 375 bfin_write_SICA_IWR1(IWR_ENABLE_ALL);
376 376
377 local_irq_disable(); 377 local_irq_disable();
378 378
diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c
index c3bb2fbd6428..28a878c3577a 100644
--- a/arch/blackfin/mach-common/ints-priority-sc.c
+++ b/arch/blackfin/mach-common/ints-priority-sc.c
@@ -147,8 +147,8 @@ static void bfin_internal_mask_irq(unsigned int irq)
147 unsigned mask_bank, mask_bit; 147 unsigned mask_bank, mask_bit;
148 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32; 148 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
149 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32; 149 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
150 bfin_write_SIC_IMASK( mask_bank, bfin_read_SIC_IMASK(mask_bank) & \ 150 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
151 ~(1 << mask_bit)); 151 ~(1 << mask_bit));
152#endif 152#endif
153 SSYNC(); 153 SSYNC();
154} 154}
@@ -161,9 +161,9 @@ static void bfin_internal_unmask_irq(unsigned int irq)
161#else 161#else
162 unsigned mask_bank, mask_bit; 162 unsigned mask_bank, mask_bit;
163 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32; 163 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
164 mask_bit = (irq - (IRQ_CORETMR + 1))%32; 164 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
165 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | \ 165 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
166 ( 1 << mask_bit)); 166 (1 << mask_bit));
167#endif 167#endif
168 SSYNC(); 168 SSYNC();
169} 169}
@@ -728,7 +728,7 @@ int __init init_arch_irq(void)
728 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); 728 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
729 bfin_write_SIC_IWR0(IWR_ENABLE_ALL); 729 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
730 bfin_write_SIC_IWR1(IWR_ENABLE_ALL); 730 bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
731 bfin_write_SIC_IWR2(IWR_ENABLE_ALL); 731 bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
732#else 732#else
733 bfin_write_SIC_IMASK(SIC_UNMASK_ALL); 733 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
734 bfin_write_SIC_IWR(IWR_ENABLE_ALL); 734 bfin_write_SIC_IWR(IWR_ENABLE_ALL);
@@ -878,7 +878,6 @@ void do_irq(int vec, struct pt_regs *fp)
878 sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0); 878 sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0);
879 sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1); 879 sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1);
880 sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2); 880 sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2);
881
882 881
883 for (;; ivg++) { 882 for (;; ivg++) {
884 if (ivg >= ivg_stop) { 883 if (ivg >= ivg_stop) {
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
index 87f2385ed971..98d35a929116 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
@@ -68,7 +68,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
68 bfin_write32(SIC_IWR0, iwr0); 68 bfin_write32(SIC_IWR0, iwr0);
69 bfin_write32(SIC_IWR1, iwr1); 69 bfin_write32(SIC_IWR1, iwr1);
70 bfin_write32(SIC_IWR2, iwr2); 70 bfin_write32(SIC_IWR2, iwr2);
71
72} 71}
73#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 72#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
74#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) 73#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h
index 6e8b8168a97a..1a8ec9e46922 100644
--- a/include/asm-blackfin/mach-bf561/cdefBF561.h
+++ b/include/asm-blackfin/mach-bf561/cdefBF561.h
@@ -74,7 +74,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
74 local_irq_restore(flags); 74 local_irq_restore(flags);
75 bfin_write32(SICA_IWR0, iwr0); 75 bfin_write32(SICA_IWR0, iwr0);
76 bfin_write32(SICA_IWR1, iwr1); 76 bfin_write32(SICA_IWR1, iwr1);
77
78} 77}
79#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 78#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
80#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) 79#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
diff --git a/include/asm-blackfin/mman.h b/include/asm-blackfin/mman.h
index 4d504f908c0c..b58f5ad3f024 100644
--- a/include/asm-blackfin/mman.h
+++ b/include/asm-blackfin/mman.h
@@ -22,8 +22,6 @@
22#define MAP_NORESERVE 0x4000 /* don't check for reservations */ 22#define MAP_NORESERVE 0x4000 /* don't check for reservations */
23#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ 23#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */
24#define MAP_NONBLOCK 0x10000 /* do not block on IO */ 24#define MAP_NONBLOCK 0x10000 /* do not block on IO */
25#define MAP_UNINITIALIZE 0x4000000 /* For anonymous mmap, memory could
26 be uninitialized. */
27 25
28#define MS_ASYNC 1 /* sync memory asynchronously */ 26#define MS_ASYNC 1 /* sync memory asynchronously */
29#define MS_INVALIDATE 2 /* invalidate the caches */ 27#define MS_INVALIDATE 2 /* invalidate the caches */