diff options
author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-23 01:47:06 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-23 01:47:06 -0400 |
commit | 8542e5893c2b10b4f6c80149e7dc3fdd2dc38bc6 (patch) | |
tree | a02ec337d6d6e4b30cd0b4d8968116a32c59357c | |
parent | 6f3cafce0ed24372084b5648c9e8a6aacbaf9900 (diff) | |
parent | b44fb7a09e6bb7d77c1b4b402591f6f953c1e51c (diff) |
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-mmc
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-mmc:
[ARM] 3565/1: AT91RM9200 MMC update
[MMC] Convert all hosts except mmci to use data->blksz
-rw-r--r-- | drivers/mmc/at91_mci.c | 141 | ||||
-rw-r--r-- | drivers/mmc/imxmmc.c | 2 | ||||
-rw-r--r-- | drivers/mmc/omap.c | 6 | ||||
-rw-r--r-- | drivers/mmc/sdhci.c | 8 |
4 files changed, 74 insertions, 83 deletions
diff --git a/drivers/mmc/at91_mci.c b/drivers/mmc/at91_mci.c index 88f0eef9cf33..3228516b7d19 100644 --- a/drivers/mmc/at91_mci.c +++ b/drivers/mmc/at91_mci.c | |||
@@ -81,13 +81,6 @@ | |||
81 | 81 | ||
82 | #undef SUPPORT_4WIRE | 82 | #undef SUPPORT_4WIRE |
83 | 83 | ||
84 | #ifdef CONFIG_MMC_DEBUG | ||
85 | #define DBG(fmt...) \ | ||
86 | printk(fmt) | ||
87 | #else | ||
88 | #define DBG(fmt...) do { } while (0) | ||
89 | #endif | ||
90 | |||
91 | static struct clk *mci_clk; | 84 | static struct clk *mci_clk; |
92 | 85 | ||
93 | #define FL_SENT_COMMAND (1 << 0) | 86 | #define FL_SENT_COMMAND (1 << 0) |
@@ -202,50 +195,50 @@ static void at91mci_pre_dma_read(struct at91mci_host *host) | |||
202 | struct mmc_command *cmd; | 195 | struct mmc_command *cmd; |
203 | struct mmc_data *data; | 196 | struct mmc_data *data; |
204 | 197 | ||
205 | DBG("pre dma read\n"); | 198 | pr_debug("pre dma read\n"); |
206 | 199 | ||
207 | cmd = host->cmd; | 200 | cmd = host->cmd; |
208 | if (!cmd) { | 201 | if (!cmd) { |
209 | DBG("no command\n"); | 202 | pr_debug("no command\n"); |
210 | return; | 203 | return; |
211 | } | 204 | } |
212 | 205 | ||
213 | data = cmd->data; | 206 | data = cmd->data; |
214 | if (!data) { | 207 | if (!data) { |
215 | DBG("no data\n"); | 208 | pr_debug("no data\n"); |
216 | return; | 209 | return; |
217 | } | 210 | } |
218 | 211 | ||
219 | for (i = 0; i < 2; i++) { | 212 | for (i = 0; i < 2; i++) { |
220 | /* nothing left to transfer */ | 213 | /* nothing left to transfer */ |
221 | if (host->transfer_index >= data->sg_len) { | 214 | if (host->transfer_index >= data->sg_len) { |
222 | DBG("Nothing left to transfer (index = %d)\n", host->transfer_index); | 215 | pr_debug("Nothing left to transfer (index = %d)\n", host->transfer_index); |
223 | break; | 216 | break; |
224 | } | 217 | } |
225 | 218 | ||
226 | /* Check to see if this needs filling */ | 219 | /* Check to see if this needs filling */ |
227 | if (i == 0) { | 220 | if (i == 0) { |
228 | if (at91_mci_read(AT91_PDC_RCR) != 0) { | 221 | if (at91_mci_read(AT91_PDC_RCR) != 0) { |
229 | DBG("Transfer active in current\n"); | 222 | pr_debug("Transfer active in current\n"); |
230 | continue; | 223 | continue; |
231 | } | 224 | } |
232 | } | 225 | } |
233 | else { | 226 | else { |
234 | if (at91_mci_read(AT91_PDC_RNCR) != 0) { | 227 | if (at91_mci_read(AT91_PDC_RNCR) != 0) { |
235 | DBG("Transfer active in next\n"); | 228 | pr_debug("Transfer active in next\n"); |
236 | continue; | 229 | continue; |
237 | } | 230 | } |
238 | } | 231 | } |
239 | 232 | ||
240 | /* Setup the next transfer */ | 233 | /* Setup the next transfer */ |
241 | DBG("Using transfer index %d\n", host->transfer_index); | 234 | pr_debug("Using transfer index %d\n", host->transfer_index); |
242 | 235 | ||
243 | sg = &data->sg[host->transfer_index++]; | 236 | sg = &data->sg[host->transfer_index++]; |
244 | DBG("sg = %p\n", sg); | 237 | pr_debug("sg = %p\n", sg); |
245 | 238 | ||
246 | sg->dma_address = dma_map_page(NULL, sg->page, sg->offset, sg->length, DMA_FROM_DEVICE); | 239 | sg->dma_address = dma_map_page(NULL, sg->page, sg->offset, sg->length, DMA_FROM_DEVICE); |
247 | 240 | ||
248 | DBG("dma address = %08X, length = %d\n", sg->dma_address, sg->length); | 241 | pr_debug("dma address = %08X, length = %d\n", sg->dma_address, sg->length); |
249 | 242 | ||
250 | if (i == 0) { | 243 | if (i == 0) { |
251 | at91_mci_write(AT91_PDC_RPR, sg->dma_address); | 244 | at91_mci_write(AT91_PDC_RPR, sg->dma_address); |
@@ -257,7 +250,7 @@ static void at91mci_pre_dma_read(struct at91mci_host *host) | |||
257 | } | 250 | } |
258 | } | 251 | } |
259 | 252 | ||
260 | DBG("pre dma read done\n"); | 253 | pr_debug("pre dma read done\n"); |
261 | } | 254 | } |
262 | 255 | ||
263 | /* | 256 | /* |
@@ -268,17 +261,17 @@ static void at91mci_post_dma_read(struct at91mci_host *host) | |||
268 | struct mmc_command *cmd; | 261 | struct mmc_command *cmd; |
269 | struct mmc_data *data; | 262 | struct mmc_data *data; |
270 | 263 | ||
271 | DBG("post dma read\n"); | 264 | pr_debug("post dma read\n"); |
272 | 265 | ||
273 | cmd = host->cmd; | 266 | cmd = host->cmd; |
274 | if (!cmd) { | 267 | if (!cmd) { |
275 | DBG("no command\n"); | 268 | pr_debug("no command\n"); |
276 | return; | 269 | return; |
277 | } | 270 | } |
278 | 271 | ||
279 | data = cmd->data; | 272 | data = cmd->data; |
280 | if (!data) { | 273 | if (!data) { |
281 | DBG("no data\n"); | 274 | pr_debug("no data\n"); |
282 | return; | 275 | return; |
283 | } | 276 | } |
284 | 277 | ||
@@ -289,17 +282,17 @@ static void at91mci_post_dma_read(struct at91mci_host *host) | |||
289 | 282 | ||
290 | struct scatterlist *sg; | 283 | struct scatterlist *sg; |
291 | 284 | ||
292 | DBG("finishing index %d\n", host->in_use_index); | 285 | pr_debug("finishing index %d\n", host->in_use_index); |
293 | 286 | ||
294 | sg = &data->sg[host->in_use_index++]; | 287 | sg = &data->sg[host->in_use_index++]; |
295 | 288 | ||
296 | DBG("Unmapping page %08X\n", sg->dma_address); | 289 | pr_debug("Unmapping page %08X\n", sg->dma_address); |
297 | 290 | ||
298 | dma_unmap_page(NULL, sg->dma_address, sg->length, DMA_FROM_DEVICE); | 291 | dma_unmap_page(NULL, sg->dma_address, sg->length, DMA_FROM_DEVICE); |
299 | 292 | ||
300 | /* Swap the contents of the buffer */ | 293 | /* Swap the contents of the buffer */ |
301 | buffer = kmap_atomic(sg->page, KM_BIO_SRC_IRQ) + sg->offset; | 294 | buffer = kmap_atomic(sg->page, KM_BIO_SRC_IRQ) + sg->offset; |
302 | DBG("buffer = %p, length = %d\n", buffer, sg->length); | 295 | pr_debug("buffer = %p, length = %d\n", buffer, sg->length); |
303 | 296 | ||
304 | data->bytes_xfered += sg->length; | 297 | data->bytes_xfered += sg->length; |
305 | 298 | ||
@@ -320,7 +313,7 @@ static void at91mci_post_dma_read(struct at91mci_host *host) | |||
320 | at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); | 313 | at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); |
321 | } | 314 | } |
322 | 315 | ||
323 | DBG("post dma read done\n"); | 316 | pr_debug("post dma read done\n"); |
324 | } | 317 | } |
325 | 318 | ||
326 | /* | 319 | /* |
@@ -331,7 +324,7 @@ static void at91_mci_handle_transmitted(struct at91mci_host *host) | |||
331 | struct mmc_command *cmd; | 324 | struct mmc_command *cmd; |
332 | struct mmc_data *data; | 325 | struct mmc_data *data; |
333 | 326 | ||
334 | DBG("Handling the transmit\n"); | 327 | pr_debug("Handling the transmit\n"); |
335 | 328 | ||
336 | /* Disable the transfer */ | 329 | /* Disable the transfer */ |
337 | at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); | 330 | at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); |
@@ -387,12 +380,12 @@ static unsigned int at91_mci_send_command(struct at91mci_host *host, struct mmc_ | |||
387 | /* Not sure if this is needed */ | 380 | /* Not sure if this is needed */ |
388 | #if 0 | 381 | #if 0 |
389 | if ((at91_mci_read(AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) { | 382 | if ((at91_mci_read(AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) { |
390 | DBG("Clearing timeout\n"); | 383 | pr_debug("Clearing timeout\n"); |
391 | at91_mci_write(AT91_MCI_ARGR, 0); | 384 | at91_mci_write(AT91_MCI_ARGR, 0); |
392 | at91_mci_write(AT91_MCI_CMDR, AT91_MCI_OPDCMD); | 385 | at91_mci_write(AT91_MCI_CMDR, AT91_MCI_OPDCMD); |
393 | while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) { | 386 | while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) { |
394 | /* spin */ | 387 | /* spin */ |
395 | DBG("Clearing: SR = %08X\n", at91_mci_read(AT91_MCI_SR)); | 388 | pr_debug("Clearing: SR = %08X\n", at91_mci_read(AT91_MCI_SR)); |
396 | } | 389 | } |
397 | } | 390 | } |
398 | #endif | 391 | #endif |
@@ -411,7 +404,7 @@ static unsigned int at91_mci_send_command(struct at91mci_host *host, struct mmc_ | |||
411 | } | 404 | } |
412 | 405 | ||
413 | if (data) { | 406 | if (data) { |
414 | block_length = 1 << data->blksz_bits; | 407 | block_length = data->blksz; |
415 | blocks = data->blocks; | 408 | blocks = data->blocks; |
416 | 409 | ||
417 | /* always set data start - also set direction flag for read */ | 410 | /* always set data start - also set direction flag for read */ |
@@ -439,7 +432,7 @@ static unsigned int at91_mci_send_command(struct at91mci_host *host, struct mmc_ | |||
439 | /* | 432 | /* |
440 | * Set the arguments and send the command | 433 | * Set the arguments and send the command |
441 | */ | 434 | */ |
442 | DBG("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08lX)\n", | 435 | pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08lX)\n", |
443 | cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91_MCI_MR)); | 436 | cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91_MCI_MR)); |
444 | 437 | ||
445 | if (!data) { | 438 | if (!data) { |
@@ -491,7 +484,7 @@ static unsigned int at91_mci_send_command(struct at91mci_host *host, struct mmc_ | |||
491 | 484 | ||
492 | at91mci_sg_to_dma(host, data); | 485 | at91mci_sg_to_dma(host, data); |
493 | 486 | ||
494 | DBG("Transmitting %d bytes\n", host->total_length); | 487 | pr_debug("Transmitting %d bytes\n", host->total_length); |
495 | 488 | ||
496 | at91_mci_write(AT91_PDC_TPR, host->physical_address); | 489 | at91_mci_write(AT91_PDC_TPR, host->physical_address); |
497 | at91_mci_write(AT91_PDC_TCR, host->total_length / 4); | 490 | at91_mci_write(AT91_PDC_TCR, host->total_length / 4); |
@@ -525,7 +518,7 @@ static void at91mci_process_command(struct at91mci_host *host, struct mmc_comman | |||
525 | 518 | ||
526 | ier = at91_mci_send_command(host, cmd); | 519 | ier = at91_mci_send_command(host, cmd); |
527 | 520 | ||
528 | DBG("setting ier to %08X\n", ier); | 521 | pr_debug("setting ier to %08X\n", ier); |
529 | 522 | ||
530 | /* Stop on errors or the required value */ | 523 | /* Stop on errors or the required value */ |
531 | at91_mci_write(AT91_MCI_IER, 0xffff0000 | ier); | 524 | at91_mci_write(AT91_MCI_IER, 0xffff0000 | ier); |
@@ -570,7 +563,7 @@ static void at91mci_completed_command(struct at91mci_host *host) | |||
570 | 563 | ||
571 | status = at91_mci_read(AT91_MCI_SR); | 564 | status = at91_mci_read(AT91_MCI_SR); |
572 | 565 | ||
573 | DBG("Status = %08X [%08X %08X %08X %08X]\n", | 566 | pr_debug("Status = %08X [%08X %08X %08X %08X]\n", |
574 | status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); | 567 | status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); |
575 | 568 | ||
576 | if (status & (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE | | 569 | if (status & (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE | |
@@ -590,7 +583,7 @@ static void at91mci_completed_command(struct at91mci_host *host) | |||
590 | else | 583 | else |
591 | cmd->error = MMC_ERR_FAILED; | 584 | cmd->error = MMC_ERR_FAILED; |
592 | 585 | ||
593 | DBG("Error detected and set to %d (cmd = %d, retries = %d)\n", | 586 | pr_debug("Error detected and set to %d (cmd = %d, retries = %d)\n", |
594 | cmd->error, cmd->opcode, cmd->retries); | 587 | cmd->error, cmd->opcode, cmd->retries); |
595 | } | 588 | } |
596 | } | 589 | } |
@@ -621,10 +614,7 @@ static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |||
621 | struct at91mci_host *host = mmc_priv(mmc); | 614 | struct at91mci_host *host = mmc_priv(mmc); |
622 | unsigned long at91_master_clock = clk_get_rate(mci_clk); | 615 | unsigned long at91_master_clock = clk_get_rate(mci_clk); |
623 | 616 | ||
624 | if (host) | 617 | host->bus_mode = ios->bus_mode; |
625 | host->bus_mode = ios->bus_mode; | ||
626 | else | ||
627 | printk("MMC: No host for bus_mode\n"); | ||
628 | 618 | ||
629 | if (ios->clock == 0) { | 619 | if (ios->clock == 0) { |
630 | /* Disable the MCI controller */ | 620 | /* Disable the MCI controller */ |
@@ -640,15 +630,15 @@ static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |||
640 | else | 630 | else |
641 | clkdiv = (at91_master_clock / ios->clock) / 2; | 631 | clkdiv = (at91_master_clock / ios->clock) / 2; |
642 | 632 | ||
643 | DBG("clkdiv = %d. mcck = %ld\n", clkdiv, | 633 | pr_debug("clkdiv = %d. mcck = %ld\n", clkdiv, |
644 | at91_master_clock / (2 * (clkdiv + 1))); | 634 | at91_master_clock / (2 * (clkdiv + 1))); |
645 | } | 635 | } |
646 | if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) { | 636 | if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) { |
647 | DBG("MMC: Setting controller bus width to 4\n"); | 637 | pr_debug("MMC: Setting controller bus width to 4\n"); |
648 | at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) | AT91_MCI_SDCBUS); | 638 | at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) | AT91_MCI_SDCBUS); |
649 | } | 639 | } |
650 | else { | 640 | else { |
651 | DBG("MMC: Setting controller bus width to 1\n"); | 641 | pr_debug("MMC: Setting controller bus width to 1\n"); |
652 | at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); | 642 | at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); |
653 | } | 643 | } |
654 | 644 | ||
@@ -656,7 +646,7 @@ static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |||
656 | at91_mci_write(AT91_MCI_MR, (at91_mci_read(AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv); | 646 | at91_mci_write(AT91_MCI_MR, (at91_mci_read(AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv); |
657 | 647 | ||
658 | /* maybe switch power to the card */ | 648 | /* maybe switch power to the card */ |
659 | if (host && host->board->vcc_pin) { | 649 | if (host->board->vcc_pin) { |
660 | switch (ios->power_mode) { | 650 | switch (ios->power_mode) { |
661 | case MMC_POWER_OFF: | 651 | case MMC_POWER_OFF: |
662 | at91_set_gpio_output(host->board->vcc_pin, 0); | 652 | at91_set_gpio_output(host->board->vcc_pin, 0); |
@@ -679,11 +669,8 @@ static irqreturn_t at91_mci_irq(int irq, void *devid, struct pt_regs *regs) | |||
679 | 669 | ||
680 | unsigned int int_status; | 670 | unsigned int int_status; |
681 | 671 | ||
682 | if (host == NULL) | ||
683 | return IRQ_HANDLED; | ||
684 | |||
685 | int_status = at91_mci_read(AT91_MCI_SR); | 672 | int_status = at91_mci_read(AT91_MCI_SR); |
686 | DBG("MCI irq: status = %08X, %08lX, %08lX\n", int_status, at91_mci_read(AT91_MCI_IMR), | 673 | pr_debug("MCI irq: status = %08X, %08lX, %08lX\n", int_status, at91_mci_read(AT91_MCI_IMR), |
687 | int_status & at91_mci_read(AT91_MCI_IMR)); | 674 | int_status & at91_mci_read(AT91_MCI_IMR)); |
688 | 675 | ||
689 | if ((int_status & at91_mci_read(AT91_MCI_IMR)) & 0xffff0000) | 676 | if ((int_status & at91_mci_read(AT91_MCI_IMR)) & 0xffff0000) |
@@ -692,75 +679,75 @@ static irqreturn_t at91_mci_irq(int irq, void *devid, struct pt_regs *regs) | |||
692 | int_status &= at91_mci_read(AT91_MCI_IMR); | 679 | int_status &= at91_mci_read(AT91_MCI_IMR); |
693 | 680 | ||
694 | if (int_status & AT91_MCI_UNRE) | 681 | if (int_status & AT91_MCI_UNRE) |
695 | DBG("MMC: Underrun error\n"); | 682 | pr_debug("MMC: Underrun error\n"); |
696 | if (int_status & AT91_MCI_OVRE) | 683 | if (int_status & AT91_MCI_OVRE) |
697 | DBG("MMC: Overrun error\n"); | 684 | pr_debug("MMC: Overrun error\n"); |
698 | if (int_status & AT91_MCI_DTOE) | 685 | if (int_status & AT91_MCI_DTOE) |
699 | DBG("MMC: Data timeout\n"); | 686 | pr_debug("MMC: Data timeout\n"); |
700 | if (int_status & AT91_MCI_DCRCE) | 687 | if (int_status & AT91_MCI_DCRCE) |
701 | DBG("MMC: CRC error in data\n"); | 688 | pr_debug("MMC: CRC error in data\n"); |
702 | if (int_status & AT91_MCI_RTOE) | 689 | if (int_status & AT91_MCI_RTOE) |
703 | DBG("MMC: Response timeout\n"); | 690 | pr_debug("MMC: Response timeout\n"); |
704 | if (int_status & AT91_MCI_RENDE) | 691 | if (int_status & AT91_MCI_RENDE) |
705 | DBG("MMC: Response end bit error\n"); | 692 | pr_debug("MMC: Response end bit error\n"); |
706 | if (int_status & AT91_MCI_RCRCE) | 693 | if (int_status & AT91_MCI_RCRCE) |
707 | DBG("MMC: Response CRC error\n"); | 694 | pr_debug("MMC: Response CRC error\n"); |
708 | if (int_status & AT91_MCI_RDIRE) | 695 | if (int_status & AT91_MCI_RDIRE) |
709 | DBG("MMC: Response direction error\n"); | 696 | pr_debug("MMC: Response direction error\n"); |
710 | if (int_status & AT91_MCI_RINDE) | 697 | if (int_status & AT91_MCI_RINDE) |
711 | DBG("MMC: Response index error\n"); | 698 | pr_debug("MMC: Response index error\n"); |
712 | 699 | ||
713 | /* Only continue processing if no errors */ | 700 | /* Only continue processing if no errors */ |
714 | if (!completed) { | 701 | if (!completed) { |
715 | if (int_status & AT91_MCI_TXBUFE) { | 702 | if (int_status & AT91_MCI_TXBUFE) { |
716 | DBG("TX buffer empty\n"); | 703 | pr_debug("TX buffer empty\n"); |
717 | at91_mci_handle_transmitted(host); | 704 | at91_mci_handle_transmitted(host); |
718 | } | 705 | } |
719 | 706 | ||
720 | if (int_status & AT91_MCI_RXBUFF) { | 707 | if (int_status & AT91_MCI_RXBUFF) { |
721 | DBG("RX buffer full\n"); | 708 | pr_debug("RX buffer full\n"); |
722 | at91_mci_write(AT91_MCI_IER, AT91_MCI_CMDRDY); | 709 | at91_mci_write(AT91_MCI_IER, AT91_MCI_CMDRDY); |
723 | } | 710 | } |
724 | 711 | ||
725 | if (int_status & AT91_MCI_ENDTX) { | 712 | if (int_status & AT91_MCI_ENDTX) { |
726 | DBG("Transmit has ended\n"); | 713 | pr_debug("Transmit has ended\n"); |
727 | } | 714 | } |
728 | 715 | ||
729 | if (int_status & AT91_MCI_ENDRX) { | 716 | if (int_status & AT91_MCI_ENDRX) { |
730 | DBG("Receive has ended\n"); | 717 | pr_debug("Receive has ended\n"); |
731 | at91mci_post_dma_read(host); | 718 | at91mci_post_dma_read(host); |
732 | } | 719 | } |
733 | 720 | ||
734 | if (int_status & AT91_MCI_NOTBUSY) { | 721 | if (int_status & AT91_MCI_NOTBUSY) { |
735 | DBG("Card is ready\n"); | 722 | pr_debug("Card is ready\n"); |
736 | at91_mci_write(AT91_MCI_IER, AT91_MCI_CMDRDY); | 723 | at91_mci_write(AT91_MCI_IER, AT91_MCI_CMDRDY); |
737 | } | 724 | } |
738 | 725 | ||
739 | if (int_status & AT91_MCI_DTIP) { | 726 | if (int_status & AT91_MCI_DTIP) { |
740 | DBG("Data transfer in progress\n"); | 727 | pr_debug("Data transfer in progress\n"); |
741 | } | 728 | } |
742 | 729 | ||
743 | if (int_status & AT91_MCI_BLKE) { | 730 | if (int_status & AT91_MCI_BLKE) { |
744 | DBG("Block transfer has ended\n"); | 731 | pr_debug("Block transfer has ended\n"); |
745 | } | 732 | } |
746 | 733 | ||
747 | if (int_status & AT91_MCI_TXRDY) { | 734 | if (int_status & AT91_MCI_TXRDY) { |
748 | DBG("Ready to transmit\n"); | 735 | pr_debug("Ready to transmit\n"); |
749 | } | 736 | } |
750 | 737 | ||
751 | if (int_status & AT91_MCI_RXRDY) { | 738 | if (int_status & AT91_MCI_RXRDY) { |
752 | DBG("Ready to receive\n"); | 739 | pr_debug("Ready to receive\n"); |
753 | } | 740 | } |
754 | 741 | ||
755 | if (int_status & AT91_MCI_CMDRDY) { | 742 | if (int_status & AT91_MCI_CMDRDY) { |
756 | DBG("Command ready\n"); | 743 | pr_debug("Command ready\n"); |
757 | completed = 1; | 744 | completed = 1; |
758 | } | 745 | } |
759 | } | 746 | } |
760 | at91_mci_write(AT91_MCI_IDR, int_status); | 747 | at91_mci_write(AT91_MCI_IDR, int_status); |
761 | 748 | ||
762 | if (completed) { | 749 | if (completed) { |
763 | DBG("Completed command\n"); | 750 | pr_debug("Completed command\n"); |
764 | at91_mci_write(AT91_MCI_IDR, 0xffffffff); | 751 | at91_mci_write(AT91_MCI_IDR, 0xffffffff); |
765 | at91mci_completed_command(host); | 752 | at91mci_completed_command(host); |
766 | } | 753 | } |
@@ -779,10 +766,10 @@ static irqreturn_t at91_mmc_det_irq(int irq, void *_host, struct pt_regs *regs) | |||
779 | */ | 766 | */ |
780 | if (present != host->present) { | 767 | if (present != host->present) { |
781 | host->present = present; | 768 | host->present = present; |
782 | DBG("%s: card %s\n", mmc_hostname(host->mmc), | 769 | pr_debug("%s: card %s\n", mmc_hostname(host->mmc), |
783 | present ? "insert" : "remove"); | 770 | present ? "insert" : "remove"); |
784 | if (!present) { | 771 | if (!present) { |
785 | DBG("****** Resetting SD-card bus width ******\n"); | 772 | pr_debug("****** Resetting SD-card bus width ******\n"); |
786 | at91_mci_write(AT91_MCI_SDCR, 0); | 773 | at91_mci_write(AT91_MCI_SDCR, 0); |
787 | } | 774 | } |
788 | mmc_detect_change(host->mmc, msecs_to_jiffies(100)); | 775 | mmc_detect_change(host->mmc, msecs_to_jiffies(100)); |
@@ -822,13 +809,13 @@ static int at91_mci_probe(struct platform_device *pdev) | |||
822 | struct at91mci_host *host; | 809 | struct at91mci_host *host; |
823 | int ret; | 810 | int ret; |
824 | 811 | ||
825 | DBG("Probe MCI devices\n"); | 812 | pr_debug("Probe MCI devices\n"); |
826 | at91_mci_disable(); | 813 | at91_mci_disable(); |
827 | at91_mci_enable(); | 814 | at91_mci_enable(); |
828 | 815 | ||
829 | mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev); | 816 | mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev); |
830 | if (!mmc) { | 817 | if (!mmc) { |
831 | DBG("Failed to allocate mmc host\n"); | 818 | pr_debug("Failed to allocate mmc host\n"); |
832 | return -ENOMEM; | 819 | return -ENOMEM; |
833 | } | 820 | } |
834 | 821 | ||
@@ -854,8 +841,9 @@ static int at91_mci_probe(struct platform_device *pdev) | |||
854 | * Get Clock | 841 | * Get Clock |
855 | */ | 842 | */ |
856 | mci_clk = clk_get(&pdev->dev, "mci_clk"); | 843 | mci_clk = clk_get(&pdev->dev, "mci_clk"); |
857 | if (!mci_clk) { | 844 | if (IS_ERR(mci_clk)) { |
858 | printk(KERN_ERR "AT91 MMC: no clock defined.\n"); | 845 | printk(KERN_ERR "AT91 MMC: no clock defined.\n"); |
846 | mmc_free_host(mmc); | ||
859 | return -ENODEV; | 847 | return -ENODEV; |
860 | } | 848 | } |
861 | clk_enable(mci_clk); /* Enable the peripheral clock */ | 849 | clk_enable(mci_clk); /* Enable the peripheral clock */ |
@@ -865,7 +853,10 @@ static int at91_mci_probe(struct platform_device *pdev) | |||
865 | */ | 853 | */ |
866 | ret = request_irq(AT91_ID_MCI, at91_mci_irq, SA_SHIRQ, DRIVER_NAME, host); | 854 | ret = request_irq(AT91_ID_MCI, at91_mci_irq, SA_SHIRQ, DRIVER_NAME, host); |
867 | if (ret) { | 855 | if (ret) { |
868 | DBG("Failed to request MCI interrupt\n"); | 856 | printk(KERN_ERR "Failed to request MCI interrupt\n"); |
857 | clk_disable(mci_clk); | ||
858 | clk_put(mci_clk); | ||
859 | mmc_free_host(mmc); | ||
869 | return ret; | 860 | return ret; |
870 | } | 861 | } |
871 | 862 | ||
@@ -886,12 +877,12 @@ static int at91_mci_probe(struct platform_device *pdev) | |||
886 | */ | 877 | */ |
887 | if (host->board->det_pin) { | 878 | if (host->board->det_pin) { |
888 | ret = request_irq(host->board->det_pin, at91_mmc_det_irq, | 879 | ret = request_irq(host->board->det_pin, at91_mmc_det_irq, |
889 | SA_SAMPLE_RANDOM, DRIVER_NAME, host); | 880 | 0, DRIVER_NAME, host); |
890 | if (ret) | 881 | if (ret) |
891 | DBG("couldn't allocate MMC detect irq\n"); | 882 | printk(KERN_ERR "couldn't allocate MMC detect irq\n"); |
892 | } | 883 | } |
893 | 884 | ||
894 | DBG(KERN_INFO "Added MCI driver\n"); | 885 | pr_debug(KERN_INFO "Added MCI driver\n"); |
895 | 886 | ||
896 | return 0; | 887 | return 0; |
897 | } | 888 | } |
@@ -924,7 +915,7 @@ static int at91_mci_remove(struct platform_device *pdev) | |||
924 | 915 | ||
925 | platform_set_drvdata(pdev, NULL); | 916 | platform_set_drvdata(pdev, NULL); |
926 | 917 | ||
927 | DBG("Removed\n"); | 918 | pr_debug("MCI Removed\n"); |
928 | 919 | ||
929 | return 0; | 920 | return 0; |
930 | } | 921 | } |
diff --git a/drivers/mmc/imxmmc.c b/drivers/mmc/imxmmc.c index a4eb1d0e7a71..5c62f4e6ad06 100644 --- a/drivers/mmc/imxmmc.c +++ b/drivers/mmc/imxmmc.c | |||
@@ -228,7 +228,7 @@ static int imxmci_busy_wait_for_status(struct imxmci_host *host, | |||
228 | static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data) | 228 | static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data) |
229 | { | 229 | { |
230 | unsigned int nob = data->blocks; | 230 | unsigned int nob = data->blocks; |
231 | unsigned int blksz = 1 << data->blksz_bits; | 231 | unsigned int blksz = data->blksz; |
232 | unsigned int datasz = nob * blksz; | 232 | unsigned int datasz = nob * blksz; |
233 | int i; | 233 | int i; |
234 | 234 | ||
diff --git a/drivers/mmc/omap.c b/drivers/mmc/omap.c index becb3c68c34d..c25244b3657b 100644 --- a/drivers/mmc/omap.c +++ b/drivers/mmc/omap.c | |||
@@ -584,10 +584,10 @@ mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data) | |||
584 | int sync_dev = 0; | 584 | int sync_dev = 0; |
585 | 585 | ||
586 | data_addr = io_v2p((u32) host->base) + OMAP_MMC_REG_DATA; | 586 | data_addr = io_v2p((u32) host->base) + OMAP_MMC_REG_DATA; |
587 | frame = 1 << data->blksz_bits; | 587 | frame = data->blksz; |
588 | count = sg_dma_len(sg); | 588 | count = sg_dma_len(sg); |
589 | 589 | ||
590 | if ((data->blocks == 1) && (count > (1 << data->blksz_bits))) | 590 | if ((data->blocks == 1) && (count > data->blksz)) |
591 | count = frame; | 591 | count = frame; |
592 | 592 | ||
593 | host->dma_len = count; | 593 | host->dma_len = count; |
@@ -776,7 +776,7 @@ mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req) | |||
776 | } | 776 | } |
777 | 777 | ||
778 | 778 | ||
779 | block_size = 1 << data->blksz_bits; | 779 | block_size = data->blksz; |
780 | 780 | ||
781 | OMAP_MMC_WRITE(host->base, NBLK, data->blocks - 1); | 781 | OMAP_MMC_WRITE(host->base, NBLK, data->blocks - 1); |
782 | OMAP_MMC_WRITE(host->base, BLEN, block_size - 1); | 782 | OMAP_MMC_WRITE(host->base, BLEN, block_size - 1); |
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 6bfcdbc7491e..8e9100bd57ef 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c | |||
@@ -268,7 +268,7 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data) | |||
268 | } | 268 | } |
269 | 269 | ||
270 | DBG("blksz %04x blks %04x flags %08x\n", | 270 | DBG("blksz %04x blks %04x flags %08x\n", |
271 | 1 << data->blksz_bits, data->blocks, data->flags); | 271 | data->blksz, data->blocks, data->flags); |
272 | DBG("tsac %d ms nsac %d clk\n", | 272 | DBG("tsac %d ms nsac %d clk\n", |
273 | data->timeout_ns / 1000000, data->timeout_clks); | 273 | data->timeout_ns / 1000000, data->timeout_clks); |
274 | 274 | ||
@@ -282,7 +282,7 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data) | |||
282 | 282 | ||
283 | writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE); | 283 | writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE); |
284 | 284 | ||
285 | writew(1 << data->blksz_bits, host->ioaddr + SDHCI_BLOCK_SIZE); | 285 | writew(data->blksz, host->ioaddr + SDHCI_BLOCK_SIZE); |
286 | writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT); | 286 | writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT); |
287 | 287 | ||
288 | if (host->flags & SDHCI_USE_DMA) { | 288 | if (host->flags & SDHCI_USE_DMA) { |
@@ -294,7 +294,7 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data) | |||
294 | 294 | ||
295 | writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS); | 295 | writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS); |
296 | } else { | 296 | } else { |
297 | host->size = (1 << data->blksz_bits) * data->blocks; | 297 | host->size = data->blksz * data->blocks; |
298 | 298 | ||
299 | host->cur_sg = data->sg; | 299 | host->cur_sg = data->sg; |
300 | host->num_sg = data->sg_len; | 300 | host->num_sg = data->sg_len; |
@@ -335,7 +335,7 @@ static void sdhci_finish_data(struct sdhci_host *host) | |||
335 | blocks = 0; | 335 | blocks = 0; |
336 | else | 336 | else |
337 | blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT); | 337 | blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT); |
338 | data->bytes_xfered = (1 << data->blksz_bits) * (data->blocks - blocks); | 338 | data->bytes_xfered = data->blksz * (data->blocks - blocks); |
339 | 339 | ||
340 | if ((data->error == MMC_ERR_NONE) && blocks) { | 340 | if ((data->error == MMC_ERR_NONE) && blocks) { |
341 | printk(KERN_ERR "%s: Controller signalled completion even " | 341 | printk(KERN_ERR "%s: Controller signalled completion even " |