aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-05-26 16:54:33 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-05-26 16:54:33 -0400
commit4ec5240ec367a592834385893200dd4fb369354c (patch)
tree3ac9a34948049bff79a2b2ce49c0a3c84e35a748
parentf49809fe9b39e22b0f6f75c86295ce216ce3e374 (diff)
parentb6016b767397258b58163494a869f8f1199e6897 (diff)
Automatic merge of rsync://rsync.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
Diffstat
-rw-r--r--drivers/net/Kconfig9
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/bnx2.c5530
-rw-r--r--drivers/net/bnx2.h4352
-rw-r--r--drivers/net/bnx2_fw.h2468
-rw-r--r--drivers/net/bonding/bond_main.c2
-rw-r--r--include/linux/if_tr.h6
-rw-r--r--include/linux/mii.h8
-rw-r--r--include/linux/pci_ids.h2
-rw-r--r--include/linux/pkt_sched.h9
-rw-r--r--include/net/xfrm.h2
-rw-r--r--net/802/tr.c26
-rw-r--r--net/ipv6/xfrm6_policy.c4
-rw-r--r--net/sched/sch_netem.c209
-rw-r--r--net/xfrm/xfrm_policy.c4
15 files changed, 12499 insertions, 133 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 7c5c1acd1474..f08e01b2fd19 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2032,6 +2032,15 @@ config TIGON3
2032 To compile this driver as a module, choose M here: the module 2032 To compile this driver as a module, choose M here: the module
2033 will be called tg3. This is recommended. 2033 will be called tg3. This is recommended.
2034 2034
2035config BNX2
2036 tristate "Broadcom NetXtremeII support"
2037 depends on PCI
2038 help
2039 This driver supports Broadcom NetXtremeII gigabit Ethernet cards.
2040
2041 To compile this driver as a module, choose M here: the module
2042 will be called bnx2. This is recommended.
2043
2035config GIANFAR 2044config GIANFAR
2036 tristate "Gianfar Ethernet" 2045 tristate "Gianfar Ethernet"
2037 depends on 85xx || 83xx 2046 depends on 85xx || 83xx
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index e038d55e4f6f..30c7567001fe 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_NS83820) += ns83820.o
51obj-$(CONFIG_STNIC) += stnic.o 8390.o 51obj-$(CONFIG_STNIC) += stnic.o 8390.o
52obj-$(CONFIG_FEALNX) += fealnx.o 52obj-$(CONFIG_FEALNX) += fealnx.o
53obj-$(CONFIG_TIGON3) += tg3.o 53obj-$(CONFIG_TIGON3) += tg3.o
54obj-$(CONFIG_BNX2) += bnx2.o
54obj-$(CONFIG_TC35815) += tc35815.o 55obj-$(CONFIG_TC35815) += tc35815.o
55obj-$(CONFIG_SK98LIN) += sk98lin/ 56obj-$(CONFIG_SK98LIN) += sk98lin/
56obj-$(CONFIG_SKFP) += skfp/ 57obj-$(CONFIG_SKFP) += skfp/
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
new file mode 100644
index 000000000000..8acc655ec1e8
--- /dev/null
+++ b/drivers/net/bnx2.c
@@ -0,0 +1,5530 @@
1/* bnx2.c: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004, 2005 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12#include "bnx2.h"
13#include "bnx2_fw.h"
14
15#define DRV_MODULE_NAME "bnx2"
16#define PFX DRV_MODULE_NAME ": "
17#define DRV_MODULE_VERSION "1.2.19"
18#define DRV_MODULE_RELDATE "May 23, 2005"
19
20#define RUN_AT(x) (jiffies + (x))
21
22/* Time in jiffies before concluding the transmitter is hung. */
23#define TX_TIMEOUT (5*HZ)
24
25static char version[] __devinitdata =
26 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
27
28MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
29MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706 Driver");
30MODULE_LICENSE("GPL");
31MODULE_VERSION(DRV_MODULE_VERSION);
32
33static int disable_msi = 0;
34
35module_param(disable_msi, int, 0);
36MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
37
38typedef enum {
39 BCM5706 = 0,
40 NC370T,
41 NC370I,
42 BCM5706S,
43 NC370F,
44} board_t;
45
46/* indexed by board_t, above */
47static struct {
48 char *name;
49} board_info[] __devinitdata = {
50 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
51 { "HP NC370T Multifunction Gigabit Server Adapter" },
52 { "HP NC370i Multifunction Gigabit Server Adapter" },
53 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
54 { "HP NC370F Multifunction Gigabit Server Adapter" },
55 { 0 },
56 };
57
58static struct pci_device_id bnx2_pci_tbl[] = {
59 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
60 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
61 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
62 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
63 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
64 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
65 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
66 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
67 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
68 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
69 { 0, }
70};
71
72static struct flash_spec flash_table[] =
73{
74 /* Slow EEPROM */
75 {0x00000000, 0x40030380, 0x009f0081, 0xa184a053, 0xaf000400,
76 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
77 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
78 "EEPROM - slow"},
79 /* Fast EEPROM */
80 {0x02000000, 0x62008380, 0x009f0081, 0xa184a053, 0xaf000400,
81 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
82 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
83 "EEPROM - fast"},
84 /* ATMEL AT45DB011B (buffered flash) */
85 {0x02000003, 0x6e008173, 0x00570081, 0x68848353, 0xaf000400,
86 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
87 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
88 "Buffered flash"},
89 /* Saifun SA25F005 (non-buffered flash) */
90 /* strap, cfg1, & write1 need updates */
91 {0x01000003, 0x5f008081, 0x00050081, 0x03840253, 0xaf020406,
92 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
93 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
94 "Non-buffered flash (64kB)"},
95 /* Saifun SA25F010 (non-buffered flash) */
96 /* strap, cfg1, & write1 need updates */
97 {0x00000001, 0x47008081, 0x00050081, 0x03840253, 0xaf020406,
98 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
99 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
100 "Non-buffered flash (128kB)"},
101 /* Saifun SA25F020 (non-buffered flash) */
102 /* strap, cfg1, & write1 need updates */
103 {0x00000003, 0x4f008081, 0x00050081, 0x03840253, 0xaf020406,
104 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
105 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
106 "Non-buffered flash (256kB)"},
107};
108
109MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
110
111static u32
112bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
113{
114 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
115 return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
116}
117
118static void
119bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
120{
121 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
122 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
123}
124
125static void
126bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
127{
128 offset += cid_addr;
129 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
130 REG_WR(bp, BNX2_CTX_DATA, val);
131}
132
133static int
134bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
135{
136 u32 val1;
137 int i, ret;
138
139 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
140 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
141 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
142
143 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
144 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
145
146 udelay(40);
147 }
148
149 val1 = (bp->phy_addr << 21) | (reg << 16) |
150 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
151 BNX2_EMAC_MDIO_COMM_START_BUSY;
152 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
153
154 for (i = 0; i < 50; i++) {
155 udelay(10);
156
157 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
158 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
159 udelay(5);
160
161 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
162 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
163
164 break;
165 }
166 }
167
168 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
169 *val = 0x0;
170 ret = -EBUSY;
171 }
172 else {
173 *val = val1;
174 ret = 0;
175 }
176
177 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
178 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
179 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
180
181 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
182 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
183
184 udelay(40);
185 }
186
187 return ret;
188}
189
190static int
191bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
192{
193 u32 val1;
194 int i, ret;
195
196 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
197 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
198 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
199
200 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
201 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
202
203 udelay(40);
204 }
205
206 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
207 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
208 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
209 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
210
211 for (i = 0; i < 50; i++) {
212 udelay(10);
213
214 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
215 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
216 udelay(5);
217 break;
218 }
219 }
220
221 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
222 ret = -EBUSY;
223 else
224 ret = 0;
225
226 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
227 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
228 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
229
230 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
231 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
232
233 udelay(40);
234 }
235
236 return ret;
237}
238
239static void
240bnx2_disable_int(struct bnx2 *bp)
241{
242 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
243 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
244 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
245}
246
247static void
248bnx2_enable_int(struct bnx2 *bp)
249{
250 u32 val;
251
252 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
253 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
254
255 val = REG_RD(bp, BNX2_HC_COMMAND);
256 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
257}
258
259static void
260bnx2_disable_int_sync(struct bnx2 *bp)
261{
262 atomic_inc(&bp->intr_sem);
263 bnx2_disable_int(bp);
264 synchronize_irq(bp->pdev->irq);
265}
266
267static void
268bnx2_netif_stop(struct bnx2 *bp)
269{
270 bnx2_disable_int_sync(bp);
271 if (netif_running(bp->dev)) {
272 netif_poll_disable(bp->dev);
273 netif_tx_disable(bp->dev);
274 bp->dev->trans_start = jiffies; /* prevent tx timeout */
275 }
276}
277
278static void
279bnx2_netif_start(struct bnx2 *bp)
280{
281 if (atomic_dec_and_test(&bp->intr_sem)) {
282 if (netif_running(bp->dev)) {
283 netif_wake_queue(bp->dev);
284 netif_poll_enable(bp->dev);
285 bnx2_enable_int(bp);
286 }
287 }
288}
289
290static void
291bnx2_free_mem(struct bnx2 *bp)
292{
293 if (bp->stats_blk) {
294 pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
295 bp->stats_blk, bp->stats_blk_mapping);
296 bp->stats_blk = NULL;
297 }
298 if (bp->status_blk) {
299 pci_free_consistent(bp->pdev, sizeof(struct status_block),
300 bp->status_blk, bp->status_blk_mapping);
301 bp->status_blk = NULL;
302 }
303 if (bp->tx_desc_ring) {
304 pci_free_consistent(bp->pdev,
305 sizeof(struct tx_bd) * TX_DESC_CNT,
306 bp->tx_desc_ring, bp->tx_desc_mapping);
307 bp->tx_desc_ring = NULL;
308 }
309 if (bp->tx_buf_ring) {
310 kfree(bp->tx_buf_ring);
311 bp->tx_buf_ring = NULL;
312 }
313 if (bp->rx_desc_ring) {
314 pci_free_consistent(bp->pdev,
315 sizeof(struct rx_bd) * RX_DESC_CNT,
316 bp->rx_desc_ring, bp->rx_desc_mapping);
317 bp->rx_desc_ring = NULL;
318 }
319 if (bp->rx_buf_ring) {
320 kfree(bp->rx_buf_ring);
321 bp->rx_buf_ring = NULL;
322 }
323}
324
325static int
326bnx2_alloc_mem(struct bnx2 *bp)
327{
328 bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
329 GFP_KERNEL);
330 if (bp->tx_buf_ring == NULL)
331 return -ENOMEM;
332
333 memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT);
334 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
335 sizeof(struct tx_bd) *
336 TX_DESC_CNT,
337 &bp->tx_desc_mapping);
338 if (bp->tx_desc_ring == NULL)
339 goto alloc_mem_err;
340
341 bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
342 GFP_KERNEL);
343 if (bp->rx_buf_ring == NULL)
344 goto alloc_mem_err;
345
346 memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
347 bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
348 sizeof(struct rx_bd) *
349 RX_DESC_CNT,
350 &bp->rx_desc_mapping);
351 if (bp->rx_desc_ring == NULL)
352 goto alloc_mem_err;
353
354 bp->status_blk = pci_alloc_consistent(bp->pdev,
355 sizeof(struct status_block),
356 &bp->status_blk_mapping);
357 if (bp->status_blk == NULL)
358 goto alloc_mem_err;
359
360 memset(bp->status_blk, 0, sizeof(struct status_block));
361
362 bp->stats_blk = pci_alloc_consistent(bp->pdev,
363 sizeof(struct statistics_block),
364 &bp->stats_blk_mapping);
365 if (bp->stats_blk == NULL)
366 goto alloc_mem_err;
367
368 memset(bp->stats_blk, 0, sizeof(struct statistics_block));
369
370 return 0;
371
372alloc_mem_err:
373 bnx2_free_mem(bp);
374 return -ENOMEM;
375}
376
377static void
378bnx2_report_link(struct bnx2 *bp)
379{
380 if (bp->link_up) {
381 netif_carrier_on(bp->dev);
382 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
383
384 printk("%d Mbps ", bp->line_speed);
385
386 if (bp->duplex == DUPLEX_FULL)
387 printk("full duplex");
388 else
389 printk("half duplex");
390
391 if (bp->flow_ctrl) {
392 if (bp->flow_ctrl & FLOW_CTRL_RX) {
393 printk(", receive ");
394 if (bp->flow_ctrl & FLOW_CTRL_TX)
395 printk("& transmit ");
396 }
397 else {
398 printk(", transmit ");
399 }
400 printk("flow control ON");
401 }
402 printk("\n");
403 }
404 else {
405 netif_carrier_off(bp->dev);
406 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
407 }
408}
409
410static void
411bnx2_resolve_flow_ctrl(struct bnx2 *bp)
412{
413 u32 local_adv, remote_adv;
414
415 bp->flow_ctrl = 0;
416 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
417 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
418
419 if (bp->duplex == DUPLEX_FULL) {
420 bp->flow_ctrl = bp->req_flow_ctrl;
421 }
422 return;
423 }
424
425 if (bp->duplex != DUPLEX_FULL) {
426 return;
427 }
428
429 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
430 bnx2_read_phy(bp, MII_LPA, &remote_adv);
431
432 if (bp->phy_flags & PHY_SERDES_FLAG) {
433 u32 new_local_adv = 0;
434 u32 new_remote_adv = 0;
435
436 if (local_adv & ADVERTISE_1000XPAUSE)
437 new_local_adv |= ADVERTISE_PAUSE_CAP;
438 if (local_adv & ADVERTISE_1000XPSE_ASYM)
439 new_local_adv |= ADVERTISE_PAUSE_ASYM;
440 if (remote_adv & ADVERTISE_1000XPAUSE)
441 new_remote_adv |= ADVERTISE_PAUSE_CAP;
442 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
443 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
444
445 local_adv = new_local_adv;
446 remote_adv = new_remote_adv;
447 }
448
449 /* See Table 28B-3 of 802.3ab-1999 spec. */
450 if (local_adv & ADVERTISE_PAUSE_CAP) {
451 if(local_adv & ADVERTISE_PAUSE_ASYM) {
452 if (remote_adv & ADVERTISE_PAUSE_CAP) {
453 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
454 }
455 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
456 bp->flow_ctrl = FLOW_CTRL_RX;
457 }
458 }
459 else {
460 if (remote_adv & ADVERTISE_PAUSE_CAP) {
461 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
462 }
463 }
464 }
465 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
466 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
467 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
468
469 bp->flow_ctrl = FLOW_CTRL_TX;
470 }
471 }
472}
473
474static int
475bnx2_serdes_linkup(struct bnx2 *bp)
476{
477 u32 bmcr, local_adv, remote_adv, common;
478
479 bp->link_up = 1;
480 bp->line_speed = SPEED_1000;
481
482 bnx2_read_phy(bp, MII_BMCR, &bmcr);
483 if (bmcr & BMCR_FULLDPLX) {
484 bp->duplex = DUPLEX_FULL;
485 }
486 else {
487 bp->duplex = DUPLEX_HALF;
488 }
489
490 if (!(bmcr & BMCR_ANENABLE)) {
491 return 0;
492 }
493
494 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
495 bnx2_read_phy(bp, MII_LPA, &remote_adv);
496
497 common = local_adv & remote_adv;
498 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
499
500 if (common & ADVERTISE_1000XFULL) {
501 bp->duplex = DUPLEX_FULL;
502 }
503 else {
504 bp->duplex = DUPLEX_HALF;
505 }
506 }
507
508 return 0;
509}
510
511static int
512bnx2_copper_linkup(struct bnx2 *bp)
513{
514 u32 bmcr;
515
516 bnx2_read_phy(bp, MII_BMCR, &bmcr);
517 if (bmcr & BMCR_ANENABLE) {
518 u32 local_adv, remote_adv, common;
519
520 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
521 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
522
523 common = local_adv & (remote_adv >> 2);
524 if (common & ADVERTISE_1000FULL) {
525 bp->line_speed = SPEED_1000;
526 bp->duplex = DUPLEX_FULL;
527 }
528 else if (common & ADVERTISE_1000HALF) {
529 bp->line_speed = SPEED_1000;
530 bp->duplex = DUPLEX_HALF;
531 }
532 else {
533 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
534 bnx2_read_phy(bp, MII_LPA, &remote_adv);
535
536 common = local_adv & remote_adv;
537 if (common & ADVERTISE_100FULL) {
538 bp->line_speed = SPEED_100;
539 bp->duplex = DUPLEX_FULL;
540 }
541 else if (common & ADVERTISE_100HALF) {
542 bp->line_speed = SPEED_100;
543 bp->duplex = DUPLEX_HALF;
544 }
545 else if (common & ADVERTISE_10FULL) {
546 bp->line_speed = SPEED_10;
547 bp->duplex = DUPLEX_FULL;
548 }
549 else if (common & ADVERTISE_10HALF) {
550 bp->line_speed = SPEED_10;
551 bp->duplex = DUPLEX_HALF;
552 }
553 else {
554 bp->line_speed = 0;
555 bp->link_up = 0;
556 }
557 }
558 }
559 else {
560 if (bmcr & BMCR_SPEED100) {
561 bp->line_speed = SPEED_100;
562 }
563 else {
564 bp->line_speed = SPEED_10;
565 }
566 if (bmcr & BMCR_FULLDPLX) {
567 bp->duplex = DUPLEX_FULL;
568 }
569 else {
570 bp->duplex = DUPLEX_HALF;
571 }
572 }
573
574 return 0;
575}
576
577static int
578bnx2_set_mac_link(struct bnx2 *bp)
579{
580 u32 val;
581
582 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
583 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
584 (bp->duplex == DUPLEX_HALF)) {
585 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
586 }
587
588 /* Configure the EMAC mode register. */
589 val = REG_RD(bp, BNX2_EMAC_MODE);
590
591 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
592 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK);
593
594 if (bp->link_up) {
595 if (bp->line_speed != SPEED_1000)
596 val |= BNX2_EMAC_MODE_PORT_MII;
597 else
598 val |= BNX2_EMAC_MODE_PORT_GMII;
599 }
600 else {
601 val |= BNX2_EMAC_MODE_PORT_GMII;
602 }
603
604 /* Set the MAC to operate in the appropriate duplex mode. */
605 if (bp->duplex == DUPLEX_HALF)
606 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
607 REG_WR(bp, BNX2_EMAC_MODE, val);
608
609 /* Enable/disable rx PAUSE. */
610 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
611
612 if (bp->flow_ctrl & FLOW_CTRL_RX)
613 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
614 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
615
616 /* Enable/disable tx PAUSE. */
617 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
618 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
619
620 if (bp->flow_ctrl & FLOW_CTRL_TX)
621 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
622 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
623
624 /* Acknowledge the interrupt. */
625 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
626
627 return 0;
628}
629
630static int
631bnx2_set_link(struct bnx2 *bp)
632{
633 u32 bmsr;
634 u8 link_up;
635
636 if (bp->loopback == MAC_LOOPBACK) {
637 bp->link_up = 1;
638 return 0;
639 }
640
641 link_up = bp->link_up;
642
643 bnx2_read_phy(bp, MII_BMSR, &bmsr);
644 bnx2_read_phy(bp, MII_BMSR, &bmsr);
645
646 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
647 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
648 u32 val;
649
650 val = REG_RD(bp, BNX2_EMAC_STATUS);
651 if (val & BNX2_EMAC_STATUS_LINK)
652 bmsr |= BMSR_LSTATUS;
653 else
654 bmsr &= ~BMSR_LSTATUS;
655 }
656
657 if (bmsr & BMSR_LSTATUS) {
658 bp->link_up = 1;
659
660 if (bp->phy_flags & PHY_SERDES_FLAG) {
661 bnx2_serdes_linkup(bp);
662 }
663 else {
664 bnx2_copper_linkup(bp);
665 }
666 bnx2_resolve_flow_ctrl(bp);
667 }
668 else {
669 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
670 (bp->autoneg & AUTONEG_SPEED)) {
671
672 u32 bmcr;
673
674 bnx2_read_phy(bp, MII_BMCR, &bmcr);
675 if (!(bmcr & BMCR_ANENABLE)) {
676 bnx2_write_phy(bp, MII_BMCR, bmcr |
677 BMCR_ANENABLE);
678 }
679 }
680 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
681 bp->link_up = 0;
682 }
683
684 if (bp->link_up != link_up) {
685 bnx2_report_link(bp);
686 }
687
688 bnx2_set_mac_link(bp);
689
690 return 0;
691}
692
693static int
694bnx2_reset_phy(struct bnx2 *bp)
695{
696 int i;
697 u32 reg;
698
699 bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
700
701#define PHY_RESET_MAX_WAIT 100
702 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
703 udelay(10);
704
705 bnx2_read_phy(bp, MII_BMCR, &reg);
706 if (!(reg & BMCR_RESET)) {
707 udelay(20);
708 break;
709 }
710 }
711 if (i == PHY_RESET_MAX_WAIT) {
712 return -EBUSY;
713 }
714 return 0;
715}
716
717static u32
718bnx2_phy_get_pause_adv(struct bnx2 *bp)
719{
720 u32 adv = 0;
721
722 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
723 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
724
725 if (bp->phy_flags & PHY_SERDES_FLAG) {
726 adv = ADVERTISE_1000XPAUSE;
727 }
728 else {
729 adv = ADVERTISE_PAUSE_CAP;
730 }
731 }
732 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
733 if (bp->phy_flags & PHY_SERDES_FLAG) {
734 adv = ADVERTISE_1000XPSE_ASYM;
735 }
736 else {
737 adv = ADVERTISE_PAUSE_ASYM;
738 }
739 }
740 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
741 if (bp->phy_flags & PHY_SERDES_FLAG) {
742 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
743 }
744 else {
745 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
746 }
747 }
748 return adv;
749}
750
751static int
752bnx2_setup_serdes_phy(struct bnx2 *bp)
753{
754 u32 adv, bmcr;
755 u32 new_adv = 0;
756
757 if (!(bp->autoneg & AUTONEG_SPEED)) {
758 u32 new_bmcr;
759
760 bnx2_read_phy(bp, MII_BMCR, &bmcr);
761 new_bmcr = bmcr & ~BMCR_ANENABLE;
762 new_bmcr |= BMCR_SPEED1000;
763 if (bp->req_duplex == DUPLEX_FULL) {
764 new_bmcr |= BMCR_FULLDPLX;
765 }
766 else {
767 new_bmcr &= ~BMCR_FULLDPLX;
768 }
769 if (new_bmcr != bmcr) {
770 /* Force a link down visible on the other side */
771 if (bp->link_up) {
772 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
773 adv &= ~(ADVERTISE_1000XFULL |
774 ADVERTISE_1000XHALF);
775 bnx2_write_phy(bp, MII_ADVERTISE, adv);
776 bnx2_write_phy(bp, MII_BMCR, bmcr |
777 BMCR_ANRESTART | BMCR_ANENABLE);
778
779 bp->link_up = 0;
780 netif_carrier_off(bp->dev);
781 }
782 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
783 }
784 return 0;
785 }
786
787 if (bp->advertising & ADVERTISED_1000baseT_Full)
788 new_adv |= ADVERTISE_1000XFULL;
789
790 new_adv |= bnx2_phy_get_pause_adv(bp);
791
792 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
793 bnx2_read_phy(bp, MII_BMCR, &bmcr);
794
795 bp->serdes_an_pending = 0;
796 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
797 /* Force a link down visible on the other side */
798 if (bp->link_up) {
799 int i;
800
801 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
802 for (i = 0; i < 110; i++) {
803 udelay(100);
804 }
805 }
806
807 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
808 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
809 BMCR_ANENABLE);
810 bp->serdes_an_pending = SERDES_AN_TIMEOUT / bp->timer_interval;
811 }
812
813 return 0;
814}
815
816#define ETHTOOL_ALL_FIBRE_SPEED \
817 (ADVERTISED_1000baseT_Full)
818
819#define ETHTOOL_ALL_COPPER_SPEED \
820 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
821 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
822 ADVERTISED_1000baseT_Full)
823
824#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
825 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
826
827#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
828
829static int
830bnx2_setup_copper_phy(struct bnx2 *bp)
831{
832 u32 bmcr;
833 u32 new_bmcr;
834
835 bnx2_read_phy(bp, MII_BMCR, &bmcr);
836
837 if (bp->autoneg & AUTONEG_SPEED) {
838 u32 adv_reg, adv1000_reg;
839 u32 new_adv_reg = 0;
840 u32 new_adv1000_reg = 0;
841
842 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
843 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
844 ADVERTISE_PAUSE_ASYM);
845
846 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
847 adv1000_reg &= PHY_ALL_1000_SPEED;
848
849 if (bp->advertising & ADVERTISED_10baseT_Half)
850 new_adv_reg |= ADVERTISE_10HALF;
851 if (bp->advertising & ADVERTISED_10baseT_Full)
852 new_adv_reg |= ADVERTISE_10FULL;
853 if (bp->advertising & ADVERTISED_100baseT_Half)
854 new_adv_reg |= ADVERTISE_100HALF;
855 if (bp->advertising & ADVERTISED_100baseT_Full)
856 new_adv_reg |= ADVERTISE_100FULL;
857 if (bp->advertising & ADVERTISED_1000baseT_Full)
858 new_adv1000_reg |= ADVERTISE_1000FULL;
859
860 new_adv_reg |= ADVERTISE_CSMA;
861
862 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
863
864 if ((adv1000_reg != new_adv1000_reg) ||
865 (adv_reg != new_adv_reg) ||
866 ((bmcr & BMCR_ANENABLE) == 0)) {
867
868 bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
869 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
870 bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
871 BMCR_ANENABLE);
872 }
873 else if (bp->link_up) {
874 /* Flow ctrl may have changed from auto to forced */
875 /* or vice-versa. */
876
877 bnx2_resolve_flow_ctrl(bp);
878 bnx2_set_mac_link(bp);
879 }
880 return 0;
881 }
882
883 new_bmcr = 0;
884 if (bp->req_line_speed == SPEED_100) {
885 new_bmcr |= BMCR_SPEED100;
886 }
887 if (bp->req_duplex == DUPLEX_FULL) {
888 new_bmcr |= BMCR_FULLDPLX;
889 }
890 if (new_bmcr != bmcr) {
891 u32 bmsr;
892 int i = 0;
893
894 bnx2_read_phy(bp, MII_BMSR, &bmsr);
895 bnx2_read_phy(bp, MII_BMSR, &bmsr);
896
897 if (bmsr & BMSR_LSTATUS) {
898 /* Force link down */
899 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
900 do {
901 udelay(100);
902 bnx2_read_phy(bp, MII_BMSR, &bmsr);
903 bnx2_read_phy(bp, MII_BMSR, &bmsr);
904 i++;
905 } while ((bmsr & BMSR_LSTATUS) && (i < 620));
906 }
907
908 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
909
910 /* Normally, the new speed is setup after the link has
911 * gone down and up again. In some cases, link will not go
912 * down so we need to set up the new speed here.
913 */
914 if (bmsr & BMSR_LSTATUS) {
915 bp->line_speed = bp->req_line_speed;
916 bp->duplex = bp->req_duplex;
917 bnx2_resolve_flow_ctrl(bp);
918 bnx2_set_mac_link(bp);
919 }
920 }
921 return 0;
922}
923
924static int
925bnx2_setup_phy(struct bnx2 *bp)
926{
927 if (bp->loopback == MAC_LOOPBACK)
928 return 0;
929
930 if (bp->phy_flags & PHY_SERDES_FLAG) {
931 return (bnx2_setup_serdes_phy(bp));
932 }
933 else {
934 return (bnx2_setup_copper_phy(bp));
935 }
936}
937
938static int
939bnx2_init_serdes_phy(struct bnx2 *bp)
940{
941 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
942
943 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
944 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
945 }
946
947 if (bp->dev->mtu > 1500) {
948 u32 val;
949
950 /* Set extended packet length bit */
951 bnx2_write_phy(bp, 0x18, 0x7);
952 bnx2_read_phy(bp, 0x18, &val);
953 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
954
955 bnx2_write_phy(bp, 0x1c, 0x6c00);
956 bnx2_read_phy(bp, 0x1c, &val);
957 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
958 }
959 else {
960 u32 val;
961
962 bnx2_write_phy(bp, 0x18, 0x7);
963 bnx2_read_phy(bp, 0x18, &val);
964 bnx2_write_phy(bp, 0x18, val & ~0x4007);
965
966 bnx2_write_phy(bp, 0x1c, 0x6c00);
967 bnx2_read_phy(bp, 0x1c, &val);
968 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
969 }
970
971 return 0;
972}
973
974static int
975bnx2_init_copper_phy(struct bnx2 *bp)
976{
977 bp->phy_flags |= PHY_CRC_FIX_FLAG;
978
979 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
980 bnx2_write_phy(bp, 0x18, 0x0c00);
981 bnx2_write_phy(bp, 0x17, 0x000a);
982 bnx2_write_phy(bp, 0x15, 0x310b);
983 bnx2_write_phy(bp, 0x17, 0x201f);
984 bnx2_write_phy(bp, 0x15, 0x9506);
985 bnx2_write_phy(bp, 0x17, 0x401f);
986 bnx2_write_phy(bp, 0x15, 0x14e2);
987 bnx2_write_phy(bp, 0x18, 0x0400);
988 }
989
990 if (bp->dev->mtu > 1500) {
991 u32 val;
992
993 /* Set extended packet length bit */
994 bnx2_write_phy(bp, 0x18, 0x7);
995 bnx2_read_phy(bp, 0x18, &val);
996 bnx2_write_phy(bp, 0x18, val | 0x4000);
997
998 bnx2_read_phy(bp, 0x10, &val);
999 bnx2_write_phy(bp, 0x10, val | 0x1);
1000 }
1001 else {
1002 u32 val;
1003
1004 bnx2_write_phy(bp, 0x18, 0x7);
1005 bnx2_read_phy(bp, 0x18, &val);
1006 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1007
1008 bnx2_read_phy(bp, 0x10, &val);
1009 bnx2_write_phy(bp, 0x10, val & ~0x1);
1010 }
1011
1012 return 0;
1013}
1014
1015
1016static int
1017bnx2_init_phy(struct bnx2 *bp)
1018{
1019 u32 val;
1020 int rc = 0;
1021
1022 bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1023 bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1024
1025 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1026
1027 bnx2_reset_phy(bp);
1028
1029 bnx2_read_phy(bp, MII_PHYSID1, &val);
1030 bp->phy_id = val << 16;
1031 bnx2_read_phy(bp, MII_PHYSID2, &val);
1032 bp->phy_id |= val & 0xffff;
1033
1034 if (bp->phy_flags & PHY_SERDES_FLAG) {
1035 rc = bnx2_init_serdes_phy(bp);
1036 }
1037 else {
1038 rc = bnx2_init_copper_phy(bp);
1039 }
1040
1041 bnx2_setup_phy(bp);
1042
1043 return rc;
1044}
1045
1046static int
1047bnx2_set_mac_loopback(struct bnx2 *bp)
1048{
1049 u32 mac_mode;
1050
1051 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1052 mac_mode &= ~BNX2_EMAC_MODE_PORT;
1053 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1054 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1055 bp->link_up = 1;
1056 return 0;
1057}
1058
1059static int
1060bnx2_fw_sync(struct bnx2 *bp, u32 msg_data)
1061{
1062 int i;
1063 u32 val;
1064
1065 if (bp->fw_timed_out)
1066 return -EBUSY;
1067
1068 bp->fw_wr_seq++;
1069 msg_data |= bp->fw_wr_seq;
1070
1071 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
1072
1073 /* wait for an acknowledgement. */
1074 for (i = 0; i < (FW_ACK_TIME_OUT_MS * 1000)/5; i++) {
1075 udelay(5);
1076
1077 val = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_FW_MB);
1078
1079 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1080 break;
1081 }
1082
1083 /* If we timed out, inform the firmware that this is the case. */
1084 if (((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) &&
1085 ((msg_data & BNX2_DRV_MSG_DATA) != BNX2_DRV_MSG_DATA_WAIT0)) {
1086
1087 msg_data &= ~BNX2_DRV_MSG_CODE;
1088 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1089
1090 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
1091
1092 bp->fw_timed_out = 1;
1093
1094 return -EBUSY;
1095 }
1096
1097 return 0;
1098}
1099
1100static void
1101bnx2_init_context(struct bnx2 *bp)
1102{
1103 u32 vcid;
1104
1105 vcid = 96;
1106 while (vcid) {
1107 u32 vcid_addr, pcid_addr, offset;
1108
1109 vcid--;
1110
1111 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1112 u32 new_vcid;
1113
1114 vcid_addr = GET_PCID_ADDR(vcid);
1115 if (vcid & 0x8) {
1116 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1117 }
1118 else {
1119 new_vcid = vcid;
1120 }
1121 pcid_addr = GET_PCID_ADDR(new_vcid);
1122 }
1123 else {
1124 vcid_addr = GET_CID_ADDR(vcid);
1125 pcid_addr = vcid_addr;
1126 }
1127
1128 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1129 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1130
1131 /* Zero out the context. */
1132 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1133 CTX_WR(bp, 0x00, offset, 0);
1134 }
1135
1136 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1137 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1138 }
1139}
1140
1141static int
1142bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1143{
1144 u16 *good_mbuf;
1145 u32 good_mbuf_cnt;
1146 u32 val;
1147
1148 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1149 if (good_mbuf == NULL) {
1150 printk(KERN_ERR PFX "Failed to allocate memory in "
1151 "bnx2_alloc_bad_rbuf\n");
1152 return -ENOMEM;
1153 }
1154
1155 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1156 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1157
1158 good_mbuf_cnt = 0;
1159
1160 /* Allocate a bunch of mbufs and save the good ones in an array. */
1161 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1162 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1163 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1164
1165 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1166
1167 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1168
1169 /* The addresses with Bit 9 set are bad memory blocks. */
1170 if (!(val & (1 << 9))) {
1171 good_mbuf[good_mbuf_cnt] = (u16) val;
1172 good_mbuf_cnt++;
1173 }
1174
1175 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1176 }
1177
1178 /* Free the good ones back to the mbuf pool thus discarding
1179 * all the bad ones. */
1180 while (good_mbuf_cnt) {
1181 good_mbuf_cnt--;
1182
1183 val = good_mbuf[good_mbuf_cnt];
1184 val = (val << 9) | val | 1;
1185
1186 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1187 }
1188 kfree(good_mbuf);
1189 return 0;
1190}
1191
1192static void
1193bnx2_set_mac_addr(struct bnx2 *bp)
1194{
1195 u32 val;
1196 u8 *mac_addr = bp->dev->dev_addr;
1197
1198 val = (mac_addr[0] << 8) | mac_addr[1];
1199
1200 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1201
1202 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1203 (mac_addr[4] << 8) | mac_addr[5];
1204
1205 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1206}
1207
1208static inline int
1209bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1210{
1211 struct sk_buff *skb;
1212 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1213 dma_addr_t mapping;
1214 struct rx_bd *rxbd = &bp->rx_desc_ring[index];
1215 unsigned long align;
1216
1217 skb = dev_alloc_skb(bp->rx_buf_size);
1218 if (skb == NULL) {
1219 return -ENOMEM;
1220 }
1221
1222 if (unlikely((align = (unsigned long) skb->data & 0x7))) {
1223 skb_reserve(skb, 8 - align);
1224 }
1225
1226 skb->dev = bp->dev;
1227 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1228 PCI_DMA_FROMDEVICE);
1229
1230 rx_buf->skb = skb;
1231 pci_unmap_addr_set(rx_buf, mapping, mapping);
1232
1233 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1234 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1235
1236 bp->rx_prod_bseq += bp->rx_buf_use_size;
1237
1238 return 0;
1239}
1240
1241static void
1242bnx2_phy_int(struct bnx2 *bp)
1243{
1244 u32 new_link_state, old_link_state;
1245
1246 new_link_state = bp->status_blk->status_attn_bits &
1247 STATUS_ATTN_BITS_LINK_STATE;
1248 old_link_state = bp->status_blk->status_attn_bits_ack &
1249 STATUS_ATTN_BITS_LINK_STATE;
1250 if (new_link_state != old_link_state) {
1251 if (new_link_state) {
1252 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
1253 STATUS_ATTN_BITS_LINK_STATE);
1254 }
1255 else {
1256 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
1257 STATUS_ATTN_BITS_LINK_STATE);
1258 }
1259 bnx2_set_link(bp);
1260 }
1261}
1262
1263static void
1264bnx2_tx_int(struct bnx2 *bp)
1265{
1266 u16 hw_cons, sw_cons, sw_ring_cons;
1267 int tx_free_bd = 0;
1268
1269 hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
1270 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1271 hw_cons++;
1272 }
1273 sw_cons = bp->tx_cons;
1274
1275 while (sw_cons != hw_cons) {
1276 struct sw_bd *tx_buf;
1277 struct sk_buff *skb;
1278 int i, last;
1279
1280 sw_ring_cons = TX_RING_IDX(sw_cons);
1281
1282 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
1283 skb = tx_buf->skb;
1284#ifdef BCM_TSO
1285 /* partial BD completions possible with TSO packets */
1286 if (skb_shinfo(skb)->tso_size) {
1287 u16 last_idx, last_ring_idx;
1288
1289 last_idx = sw_cons +
1290 skb_shinfo(skb)->nr_frags + 1;
1291 last_ring_idx = sw_ring_cons +
1292 skb_shinfo(skb)->nr_frags + 1;
1293 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
1294 last_idx++;
1295 }
1296 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
1297 break;
1298 }
1299 }
1300#endif
1301 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
1302 skb_headlen(skb), PCI_DMA_TODEVICE);
1303
1304 tx_buf->skb = NULL;
1305 last = skb_shinfo(skb)->nr_frags;
1306
1307 for (i = 0; i < last; i++) {
1308 sw_cons = NEXT_TX_BD(sw_cons);
1309
1310 pci_unmap_page(bp->pdev,
1311 pci_unmap_addr(
1312 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
1313 mapping),
1314 skb_shinfo(skb)->frags[i].size,
1315 PCI_DMA_TODEVICE);
1316 }
1317
1318 sw_cons = NEXT_TX_BD(sw_cons);
1319
1320 tx_free_bd += last + 1;
1321
1322 dev_kfree_skb_irq(skb);
1323
1324 hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
1325 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1326 hw_cons++;
1327 }
1328 }
1329
1330 atomic_add(tx_free_bd, &bp->tx_avail_bd);
1331
1332 if (unlikely(netif_queue_stopped(bp->dev))) {
1333 unsigned long flags;
1334
1335 spin_lock_irqsave(&bp->tx_lock, flags);
1336 if ((netif_queue_stopped(bp->dev)) &&
1337 (atomic_read(&bp->tx_avail_bd) > MAX_SKB_FRAGS)) {
1338
1339 netif_wake_queue(bp->dev);
1340 }
1341 spin_unlock_irqrestore(&bp->tx_lock, flags);
1342 }
1343
1344 bp->tx_cons = sw_cons;
1345
1346}
1347
1348static inline void
1349bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1350 u16 cons, u16 prod)
1351{
1352 struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons];
1353 struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod];
1354 struct rx_bd *cons_bd = &bp->rx_desc_ring[cons];
1355 struct rx_bd *prod_bd = &bp->rx_desc_ring[prod];
1356
1357 pci_dma_sync_single_for_device(bp->pdev,
1358 pci_unmap_addr(cons_rx_buf, mapping),
1359 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1360
1361 prod_rx_buf->skb = cons_rx_buf->skb;
1362 pci_unmap_addr_set(prod_rx_buf, mapping,
1363 pci_unmap_addr(cons_rx_buf, mapping));
1364
1365 memcpy(prod_bd, cons_bd, 8);
1366
1367 bp->rx_prod_bseq += bp->rx_buf_use_size;
1368
1369}
1370
1371static int
1372bnx2_rx_int(struct bnx2 *bp, int budget)
1373{
1374 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
1375 struct l2_fhdr *rx_hdr;
1376 int rx_pkt = 0;
1377
1378 hw_cons = bp->status_blk->status_rx_quick_consumer_index0;
1379 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
1380 hw_cons++;
1381 }
1382 sw_cons = bp->rx_cons;
1383 sw_prod = bp->rx_prod;
1384
1385 /* Memory barrier necessary as speculative reads of the rx
1386 * buffer can be ahead of the index in the status block
1387 */
1388 rmb();
1389 while (sw_cons != hw_cons) {
1390 unsigned int len;
1391 u16 status;
1392 struct sw_bd *rx_buf;
1393 struct sk_buff *skb;
1394
1395 sw_ring_cons = RX_RING_IDX(sw_cons);
1396 sw_ring_prod = RX_RING_IDX(sw_prod);
1397
1398 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1399 skb = rx_buf->skb;
1400 pci_dma_sync_single_for_cpu(bp->pdev,
1401 pci_unmap_addr(rx_buf, mapping),
1402 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1403
1404 rx_hdr = (struct l2_fhdr *) skb->data;
1405 len = rx_hdr->l2_fhdr_pkt_len - 4;
1406
1407 if (rx_hdr->l2_fhdr_errors &
1408 (L2_FHDR_ERRORS_BAD_CRC |
1409 L2_FHDR_ERRORS_PHY_DECODE |
1410 L2_FHDR_ERRORS_ALIGNMENT |
1411 L2_FHDR_ERRORS_TOO_SHORT |
1412 L2_FHDR_ERRORS_GIANT_FRAME)) {
1413
1414 goto reuse_rx;
1415 }
1416
1417 /* Since we don't have a jumbo ring, copy small packets
1418 * if mtu > 1500
1419 */
1420 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
1421 struct sk_buff *new_skb;
1422
1423 new_skb = dev_alloc_skb(len + 2);
1424 if (new_skb == NULL)
1425 goto reuse_rx;
1426
1427 /* aligned copy */
1428 memcpy(new_skb->data,
1429 skb->data + bp->rx_offset - 2,
1430 len + 2);
1431
1432 skb_reserve(new_skb, 2);
1433 skb_put(new_skb, len);
1434 new_skb->dev = bp->dev;
1435
1436 bnx2_reuse_rx_skb(bp, skb,
1437 sw_ring_cons, sw_ring_prod);
1438
1439 skb = new_skb;
1440 }
1441 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
1442 pci_unmap_single(bp->pdev,
1443 pci_unmap_addr(rx_buf, mapping),
1444 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1445
1446 skb_reserve(skb, bp->rx_offset);
1447 skb_put(skb, len);
1448 }
1449 else {
1450reuse_rx:
1451 bnx2_reuse_rx_skb(bp, skb,
1452 sw_ring_cons, sw_ring_prod);
1453 goto next_rx;
1454 }
1455
1456 skb->protocol = eth_type_trans(skb, bp->dev);
1457
1458 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
1459 (htons(skb->protocol) != 0x8100)) {
1460
1461 dev_kfree_skb_irq(skb);
1462 goto next_rx;
1463
1464 }
1465
1466 status = rx_hdr->l2_fhdr_status;
1467 skb->ip_summed = CHECKSUM_NONE;
1468 if (bp->rx_csum &&
1469 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1470 L2_FHDR_STATUS_UDP_DATAGRAM))) {
1471
1472 u16 cksum = rx_hdr->l2_fhdr_tcp_udp_xsum;
1473
1474 if (cksum == 0xffff)
1475 skb->ip_summed = CHECKSUM_UNNECESSARY;
1476 }
1477
1478#ifdef BCM_VLAN
1479 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
1480 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1481 rx_hdr->l2_fhdr_vlan_tag);
1482 }
1483 else
1484#endif
1485 netif_receive_skb(skb);
1486
1487 bp->dev->last_rx = jiffies;
1488 rx_pkt++;
1489
1490next_rx:
1491 rx_buf->skb = NULL;
1492
1493 sw_cons = NEXT_RX_BD(sw_cons);
1494 sw_prod = NEXT_RX_BD(sw_prod);
1495
1496 if ((rx_pkt == budget))
1497 break;
1498 }
1499 bp->rx_cons = sw_cons;
1500 bp->rx_prod = sw_prod;
1501
1502 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
1503
1504 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
1505
1506 mmiowb();
1507
1508 return rx_pkt;
1509
1510}
1511
1512/* MSI ISR - The only difference between this and the INTx ISR
1513 * is that the MSI interrupt is always serviced.
1514 */
1515static irqreturn_t
1516bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
1517{
1518 struct net_device *dev = dev_instance;
1519 struct bnx2 *bp = dev->priv;
1520
1521 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1522 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1523 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1524
1525 /* Return here if interrupt is disabled. */
1526 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1527 return IRQ_RETVAL(1);
1528 }
1529
1530 if (netif_rx_schedule_prep(dev)) {
1531 __netif_rx_schedule(dev);
1532 }
1533
1534 return IRQ_RETVAL(1);
1535}
1536
1537static irqreturn_t
1538bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1539{
1540 struct net_device *dev = dev_instance;
1541 struct bnx2 *bp = dev->priv;
1542
1543 /* When using INTx, it is possible for the interrupt to arrive
1544 * at the CPU before the status block posted prior to the
1545 * interrupt. Reading a register will flush the status block.
1546 * When using MSI, the MSI message will always complete after
1547 * the status block write.
1548 */
1549 if ((bp->status_blk->status_idx == bp->last_status_idx) ||
1550 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
1551 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
1552 return IRQ_RETVAL(0);
1553
1554 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1555 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1556 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1557
1558 /* Return here if interrupt is shared and is disabled. */
1559 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1560 return IRQ_RETVAL(1);
1561 }
1562
1563 if (netif_rx_schedule_prep(dev)) {
1564 __netif_rx_schedule(dev);
1565 }
1566
1567 return IRQ_RETVAL(1);
1568}
1569
1570static int
1571bnx2_poll(struct net_device *dev, int *budget)
1572{
1573 struct bnx2 *bp = dev->priv;
1574 int rx_done = 1;
1575
1576 bp->last_status_idx = bp->status_blk->status_idx;
1577
1578 rmb();
1579 if ((bp->status_blk->status_attn_bits &
1580 STATUS_ATTN_BITS_LINK_STATE) !=
1581 (bp->status_blk->status_attn_bits_ack &
1582 STATUS_ATTN_BITS_LINK_STATE)) {
1583
1584 unsigned long flags;
1585
1586 spin_lock_irqsave(&bp->phy_lock, flags);
1587 bnx2_phy_int(bp);
1588 spin_unlock_irqrestore(&bp->phy_lock, flags);
1589 }
1590
1591 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_cons) {
1592 bnx2_tx_int(bp);
1593 }
1594
1595 if (bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) {
1596 int orig_budget = *budget;
1597 int work_done;
1598
1599 if (orig_budget > dev->quota)
1600 orig_budget = dev->quota;
1601
1602 work_done = bnx2_rx_int(bp, orig_budget);
1603 *budget -= work_done;
1604 dev->quota -= work_done;
1605
1606 if (work_done >= orig_budget) {
1607 rx_done = 0;
1608 }
1609 }
1610
1611 if (rx_done) {
1612 netif_rx_complete(dev);
1613 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1614 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1615 bp->last_status_idx);
1616 return 0;
1617 }
1618
1619 return 1;
1620}
1621
1622/* Called with rtnl_lock from vlan functions and also dev->xmit_lock
1623 * from set_multicast.
1624 */
1625static void
1626bnx2_set_rx_mode(struct net_device *dev)
1627{
1628 struct bnx2 *bp = dev->priv;
1629 u32 rx_mode, sort_mode;
1630 int i;
1631 unsigned long flags;
1632
1633 spin_lock_irqsave(&bp->phy_lock, flags);
1634
1635 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
1636 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
1637 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
1638#ifdef BCM_VLAN
1639 if (!bp->vlgrp) {
1640 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1641 }
1642#else
1643 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1644#endif
1645 if (dev->flags & IFF_PROMISC) {
1646 /* Promiscuous mode. */
1647 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
1648 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
1649 }
1650 else if (dev->flags & IFF_ALLMULTI) {
1651 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1652 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1653 0xffffffff);
1654 }
1655 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
1656 }
1657 else {
1658 /* Accept one or more multicast(s). */
1659 struct dev_mc_list *mclist;
1660 u32 mc_filter[NUM_MC_HASH_REGISTERS];
1661 u32 regidx;
1662 u32 bit;
1663 u32 crc;
1664
1665 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
1666
1667 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1668 i++, mclist = mclist->next) {
1669
1670 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1671 bit = crc & 0xff;
1672 regidx = (bit & 0xe0) >> 5;
1673 bit &= 0x1f;
1674 mc_filter[regidx] |= (1 << bit);
1675 }
1676
1677 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1678 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1679 mc_filter[i]);
1680 }
1681
1682 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
1683 }
1684
1685 if (rx_mode != bp->rx_mode) {
1686 bp->rx_mode = rx_mode;
1687 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
1688 }
1689
1690 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
1691 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
1692 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
1693
1694 spin_unlock_irqrestore(&bp->phy_lock, flags);
1695}
1696
1697static void
1698load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
1699 u32 rv2p_proc)
1700{
1701 int i;
1702 u32 val;
1703
1704
1705 for (i = 0; i < rv2p_code_len; i += 8) {
1706 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
1707 rv2p_code++;
1708 REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
1709 rv2p_code++;
1710
1711 if (rv2p_proc == RV2P_PROC1) {
1712 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
1713 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
1714 }
1715 else {
1716 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
1717 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
1718 }
1719 }
1720
1721 /* Reset the processor, un-stall is done later. */
1722 if (rv2p_proc == RV2P_PROC1) {
1723 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
1724 }
1725 else {
1726 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
1727 }
1728}
1729
1730static void
1731load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
1732{
1733 u32 offset;
1734 u32 val;
1735
1736 /* Halt the CPU. */
1737 val = REG_RD_IND(bp, cpu_reg->mode);
1738 val |= cpu_reg->mode_value_halt;
1739 REG_WR_IND(bp, cpu_reg->mode, val);
1740 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1741
1742 /* Load the Text area. */
1743 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
1744 if (fw->text) {
1745 int j;
1746
1747 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
1748 REG_WR_IND(bp, offset, fw->text[j]);
1749 }
1750 }
1751
1752 /* Load the Data area. */
1753 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
1754 if (fw->data) {
1755 int j;
1756
1757 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
1758 REG_WR_IND(bp, offset, fw->data[j]);
1759 }
1760 }
1761
1762 /* Load the SBSS area. */
1763 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
1764 if (fw->sbss) {
1765 int j;
1766
1767 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
1768 REG_WR_IND(bp, offset, fw->sbss[j]);
1769 }
1770 }
1771
1772 /* Load the BSS area. */
1773 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
1774 if (fw->bss) {
1775 int j;
1776
1777 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
1778 REG_WR_IND(bp, offset, fw->bss[j]);
1779 }
1780 }
1781
1782 /* Load the Read-Only area. */
1783 offset = cpu_reg->spad_base +
1784 (fw->rodata_addr - cpu_reg->mips_view_base);
1785 if (fw->rodata) {
1786 int j;
1787
1788 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
1789 REG_WR_IND(bp, offset, fw->rodata[j]);
1790 }
1791 }
1792
1793 /* Clear the pre-fetch instruction. */
1794 REG_WR_IND(bp, cpu_reg->inst, 0);
1795 REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
1796
1797 /* Start the CPU. */
1798 val = REG_RD_IND(bp, cpu_reg->mode);
1799 val &= ~cpu_reg->mode_value_halt;
1800 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1801 REG_WR_IND(bp, cpu_reg->mode, val);
1802}
1803
1804static void
1805bnx2_init_cpus(struct bnx2 *bp)
1806{
1807 struct cpu_reg cpu_reg;
1808 struct fw_info fw;
1809
1810 /* Initialize the RV2P processor. */
1811 load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
1812 load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
1813
1814 /* Initialize the RX Processor. */
1815 cpu_reg.mode = BNX2_RXP_CPU_MODE;
1816 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
1817 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
1818 cpu_reg.state = BNX2_RXP_CPU_STATE;
1819 cpu_reg.state_value_clear = 0xffffff;
1820 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
1821 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
1822 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
1823 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
1824 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
1825 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
1826 cpu_reg.mips_view_base = 0x8000000;
1827
1828 fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
1829 fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
1830 fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
1831 fw.start_addr = bnx2_RXP_b06FwStartAddr;
1832
1833 fw.text_addr = bnx2_RXP_b06FwTextAddr;
1834 fw.text_len = bnx2_RXP_b06FwTextLen;
1835 fw.text_index = 0;
1836 fw.text = bnx2_RXP_b06FwText;
1837
1838 fw.data_addr = bnx2_RXP_b06FwDataAddr;
1839 fw.data_len = bnx2_RXP_b06FwDataLen;
1840 fw.data_index = 0;
1841 fw.data = bnx2_RXP_b06FwData;
1842
1843 fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
1844 fw.sbss_len = bnx2_RXP_b06FwSbssLen;
1845 fw.sbss_index = 0;
1846 fw.sbss = bnx2_RXP_b06FwSbss;
1847
1848 fw.bss_addr = bnx2_RXP_b06FwBssAddr;
1849 fw.bss_len = bnx2_RXP_b06FwBssLen;
1850 fw.bss_index = 0;
1851 fw.bss = bnx2_RXP_b06FwBss;
1852
1853 fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
1854 fw.rodata_len = bnx2_RXP_b06FwRodataLen;
1855 fw.rodata_index = 0;
1856 fw.rodata = bnx2_RXP_b06FwRodata;
1857
1858 load_cpu_fw(bp, &cpu_reg, &fw);
1859
1860 /* Initialize the TX Processor. */
1861 cpu_reg.mode = BNX2_TXP_CPU_MODE;
1862 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
1863 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
1864 cpu_reg.state = BNX2_TXP_CPU_STATE;
1865 cpu_reg.state_value_clear = 0xffffff;
1866 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
1867 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
1868 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
1869 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
1870 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
1871 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
1872 cpu_reg.mips_view_base = 0x8000000;
1873
1874 fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
1875 fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
1876 fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
1877 fw.start_addr = bnx2_TXP_b06FwStartAddr;
1878
1879 fw.text_addr = bnx2_TXP_b06FwTextAddr;
1880 fw.text_len = bnx2_TXP_b06FwTextLen;
1881 fw.text_index = 0;
1882 fw.text = bnx2_TXP_b06FwText;
1883
1884 fw.data_addr = bnx2_TXP_b06FwDataAddr;
1885 fw.data_len = bnx2_TXP_b06FwDataLen;
1886 fw.data_index = 0;
1887 fw.data = bnx2_TXP_b06FwData;
1888
1889 fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
1890 fw.sbss_len = bnx2_TXP_b06FwSbssLen;
1891 fw.sbss_index = 0;
1892 fw.sbss = bnx2_TXP_b06FwSbss;
1893
1894 fw.bss_addr = bnx2_TXP_b06FwBssAddr;
1895 fw.bss_len = bnx2_TXP_b06FwBssLen;
1896 fw.bss_index = 0;
1897 fw.bss = bnx2_TXP_b06FwBss;
1898
1899 fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
1900 fw.rodata_len = bnx2_TXP_b06FwRodataLen;
1901 fw.rodata_index = 0;
1902 fw.rodata = bnx2_TXP_b06FwRodata;
1903
1904 load_cpu_fw(bp, &cpu_reg, &fw);
1905
1906 /* Initialize the TX Patch-up Processor. */
1907 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
1908 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
1909 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
1910 cpu_reg.state = BNX2_TPAT_CPU_STATE;
1911 cpu_reg.state_value_clear = 0xffffff;
1912 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
1913 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
1914 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
1915 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
1916 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
1917 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
1918 cpu_reg.mips_view_base = 0x8000000;
1919
1920 fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
1921 fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
1922 fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
1923 fw.start_addr = bnx2_TPAT_b06FwStartAddr;
1924
1925 fw.text_addr = bnx2_TPAT_b06FwTextAddr;
1926 fw.text_len = bnx2_TPAT_b06FwTextLen;
1927 fw.text_index = 0;
1928 fw.text = bnx2_TPAT_b06FwText;
1929
1930 fw.data_addr = bnx2_TPAT_b06FwDataAddr;
1931 fw.data_len = bnx2_TPAT_b06FwDataLen;
1932 fw.data_index = 0;
1933 fw.data = bnx2_TPAT_b06FwData;
1934
1935 fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
1936 fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
1937 fw.sbss_index = 0;
1938 fw.sbss = bnx2_TPAT_b06FwSbss;
1939
1940 fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
1941 fw.bss_len = bnx2_TPAT_b06FwBssLen;
1942 fw.bss_index = 0;
1943 fw.bss = bnx2_TPAT_b06FwBss;
1944
1945 fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
1946 fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
1947 fw.rodata_index = 0;
1948 fw.rodata = bnx2_TPAT_b06FwRodata;
1949
1950 load_cpu_fw(bp, &cpu_reg, &fw);
1951
1952 /* Initialize the Completion Processor. */
1953 cpu_reg.mode = BNX2_COM_CPU_MODE;
1954 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
1955 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
1956 cpu_reg.state = BNX2_COM_CPU_STATE;
1957 cpu_reg.state_value_clear = 0xffffff;
1958 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
1959 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
1960 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
1961 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
1962 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
1963 cpu_reg.spad_base = BNX2_COM_SCRATCH;
1964 cpu_reg.mips_view_base = 0x8000000;
1965
1966 fw.ver_major = bnx2_COM_b06FwReleaseMajor;
1967 fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
1968 fw.ver_fix = bnx2_COM_b06FwReleaseFix;
1969 fw.start_addr = bnx2_COM_b06FwStartAddr;
1970
1971 fw.text_addr = bnx2_COM_b06FwTextAddr;
1972 fw.text_len = bnx2_COM_b06FwTextLen;
1973 fw.text_index = 0;
1974 fw.text = bnx2_COM_b06FwText;
1975
1976 fw.data_addr = bnx2_COM_b06FwDataAddr;
1977 fw.data_len = bnx2_COM_b06FwDataLen;
1978 fw.data_index = 0;
1979 fw.data = bnx2_COM_b06FwData;
1980
1981 fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
1982 fw.sbss_len = bnx2_COM_b06FwSbssLen;
1983 fw.sbss_index = 0;
1984 fw.sbss = bnx2_COM_b06FwSbss;
1985
1986 fw.bss_addr = bnx2_COM_b06FwBssAddr;
1987 fw.bss_len = bnx2_COM_b06FwBssLen;
1988 fw.bss_index = 0;
1989 fw.bss = bnx2_COM_b06FwBss;
1990
1991 fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
1992 fw.rodata_len = bnx2_COM_b06FwRodataLen;
1993 fw.rodata_index = 0;
1994 fw.rodata = bnx2_COM_b06FwRodata;
1995
1996 load_cpu_fw(bp, &cpu_reg, &fw);
1997
1998}
1999
2000static int
2001bnx2_set_power_state(struct bnx2 *bp, int state)
2002{
2003 u16 pmcsr;
2004
2005 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2006
2007 switch (state) {
2008 case 0: {
2009 u32 val;
2010
2011 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2012 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2013 PCI_PM_CTRL_PME_STATUS);
2014
2015 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2016 /* delay required during transition out of D3hot */
2017 msleep(20);
2018
2019 val = REG_RD(bp, BNX2_EMAC_MODE);
2020 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2021 val &= ~BNX2_EMAC_MODE_MPKT;
2022 REG_WR(bp, BNX2_EMAC_MODE, val);
2023
2024 val = REG_RD(bp, BNX2_RPM_CONFIG);
2025 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2026 REG_WR(bp, BNX2_RPM_CONFIG, val);
2027 break;
2028 }
2029 case 3: {
2030 int i;
2031 u32 val, wol_msg;
2032
2033 if (bp->wol) {
2034 u32 advertising;
2035 u8 autoneg;
2036
2037 autoneg = bp->autoneg;
2038 advertising = bp->advertising;
2039
2040 bp->autoneg = AUTONEG_SPEED;
2041 bp->advertising = ADVERTISED_10baseT_Half |
2042 ADVERTISED_10baseT_Full |
2043 ADVERTISED_100baseT_Half |
2044 ADVERTISED_100baseT_Full |
2045 ADVERTISED_Autoneg;
2046
2047 bnx2_setup_copper_phy(bp);
2048
2049 bp->autoneg = autoneg;
2050 bp->advertising = advertising;
2051
2052 bnx2_set_mac_addr(bp);
2053
2054 val = REG_RD(bp, BNX2_EMAC_MODE);
2055
2056 /* Enable port mode. */
2057 val &= ~BNX2_EMAC_MODE_PORT;
2058 val |= BNX2_EMAC_MODE_PORT_MII |
2059 BNX2_EMAC_MODE_MPKT_RCVD |
2060 BNX2_EMAC_MODE_ACPI_RCVD |
2061 BNX2_EMAC_MODE_FORCE_LINK |
2062 BNX2_EMAC_MODE_MPKT;
2063
2064 REG_WR(bp, BNX2_EMAC_MODE, val);
2065
2066 /* receive all multicast */
2067 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2068 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2069 0xffffffff);
2070 }
2071 REG_WR(bp, BNX2_EMAC_RX_MODE,
2072 BNX2_EMAC_RX_MODE_SORT_MODE);
2073
2074 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2075 BNX2_RPM_SORT_USER0_MC_EN;
2076 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2077 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2078 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2079 BNX2_RPM_SORT_USER0_ENA);
2080
2081 /* Need to enable EMAC and RPM for WOL. */
2082 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2083 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2084 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2085 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2086
2087 val = REG_RD(bp, BNX2_RPM_CONFIG);
2088 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2089 REG_WR(bp, BNX2_RPM_CONFIG, val);
2090
2091 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2092 }
2093 else {
2094 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2095 }
2096
2097 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg);
2098
2099 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2100 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2101 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2102
2103 if (bp->wol)
2104 pmcsr |= 3;
2105 }
2106 else {
2107 pmcsr |= 3;
2108 }
2109 if (bp->wol) {
2110 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2111 }
2112 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2113 pmcsr);
2114
2115 /* No more memory access after this point until
2116 * device is brought back to D0.
2117 */
2118 udelay(50);
2119 break;
2120 }
2121 default:
2122 return -EINVAL;
2123 }
2124 return 0;
2125}
2126
2127static int
2128bnx2_acquire_nvram_lock(struct bnx2 *bp)
2129{
2130 u32 val;
2131 int j;
2132
2133 /* Request access to the flash interface. */
2134 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2135 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2136 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2137 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2138 break;
2139
2140 udelay(5);
2141 }
2142
2143 if (j >= NVRAM_TIMEOUT_COUNT)
2144 return -EBUSY;
2145
2146 return 0;
2147}
2148
2149static int
2150bnx2_release_nvram_lock(struct bnx2 *bp)
2151{
2152 int j;
2153 u32 val;
2154
2155 /* Relinquish nvram interface. */
2156 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2157
2158 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2159 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2160 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2161 break;
2162
2163 udelay(5);
2164 }
2165
2166 if (j >= NVRAM_TIMEOUT_COUNT)
2167 return -EBUSY;
2168
2169 return 0;
2170}
2171
2172
2173static int
2174bnx2_enable_nvram_write(struct bnx2 *bp)
2175{
2176 u32 val;
2177
2178 val = REG_RD(bp, BNX2_MISC_CFG);
2179 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
2180
2181 if (!bp->flash_info->buffered) {
2182 int j;
2183
2184 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2185 REG_WR(bp, BNX2_NVM_COMMAND,
2186 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
2187
2188 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2189 udelay(5);
2190
2191 val = REG_RD(bp, BNX2_NVM_COMMAND);
2192 if (val & BNX2_NVM_COMMAND_DONE)
2193 break;
2194 }
2195
2196 if (j >= NVRAM_TIMEOUT_COUNT)
2197 return -EBUSY;
2198 }
2199 return 0;
2200}
2201
2202static void
2203bnx2_disable_nvram_write(struct bnx2 *bp)
2204{
2205 u32 val;
2206
2207 val = REG_RD(bp, BNX2_MISC_CFG);
2208 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
2209}
2210
2211
2212static void
2213bnx2_enable_nvram_access(struct bnx2 *bp)
2214{
2215 u32 val;
2216
2217 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2218 /* Enable both bits, even on read. */
2219 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2220 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
2221}
2222
2223static void
2224bnx2_disable_nvram_access(struct bnx2 *bp)
2225{
2226 u32 val;
2227
2228 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2229 /* Disable both bits, even after read. */
2230 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2231 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
2232 BNX2_NVM_ACCESS_ENABLE_WR_EN));
2233}
2234
2235static int
2236bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
2237{
2238 u32 cmd;
2239 int j;
2240
2241 if (bp->flash_info->buffered)
2242 /* Buffered flash, no erase needed */
2243 return 0;
2244
2245 /* Build an erase command */
2246 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
2247 BNX2_NVM_COMMAND_DOIT;
2248
2249 /* Need to clear DONE bit separately. */
2250 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2251
2252 /* Address of the NVRAM to read from. */
2253 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2254
2255 /* Issue an erase command. */
2256 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2257
2258 /* Wait for completion. */
2259 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2260 u32 val;
2261
2262 udelay(5);
2263
2264 val = REG_RD(bp, BNX2_NVM_COMMAND);
2265 if (val & BNX2_NVM_COMMAND_DONE)
2266 break;
2267 }
2268
2269 if (j >= NVRAM_TIMEOUT_COUNT)
2270 return -EBUSY;
2271
2272 return 0;
2273}
2274
2275static int
2276bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
2277{
2278 u32 cmd;
2279 int j;
2280
2281 /* Build the command word. */
2282 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
2283
2284 /* Calculate an offset of a buffered flash. */
2285 if (bp->flash_info->buffered) {
2286 offset = ((offset / bp->flash_info->page_size) <<
2287 bp->flash_info->page_bits) +
2288 (offset % bp->flash_info->page_size);
2289 }
2290
2291 /* Need to clear DONE bit separately. */
2292 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2293
2294 /* Address of the NVRAM to read from. */
2295 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2296
2297 /* Issue a read command. */
2298 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2299
2300 /* Wait for completion. */
2301 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2302 u32 val;
2303
2304 udelay(5);
2305
2306 val = REG_RD(bp, BNX2_NVM_COMMAND);
2307 if (val & BNX2_NVM_COMMAND_DONE) {
2308 val = REG_RD(bp, BNX2_NVM_READ);
2309
2310 val = be32_to_cpu(val);
2311 memcpy(ret_val, &val, 4);
2312 break;
2313 }
2314 }
2315 if (j >= NVRAM_TIMEOUT_COUNT)
2316 return -EBUSY;
2317
2318 return 0;
2319}
2320
2321
2322static int
2323bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
2324{
2325 u32 cmd, val32;
2326 int j;
2327
2328 /* Build the command word. */
2329 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
2330
2331 /* Calculate an offset of a buffered flash. */
2332 if (bp->flash_info->buffered) {
2333 offset = ((offset / bp->flash_info->page_size) <<
2334 bp->flash_info->page_bits) +
2335 (offset % bp->flash_info->page_size);
2336 }
2337
2338 /* Need to clear DONE bit separately. */
2339 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2340
2341 memcpy(&val32, val, 4);
2342 val32 = cpu_to_be32(val32);
2343
2344 /* Write the data. */
2345 REG_WR(bp, BNX2_NVM_WRITE, val32);
2346
2347 /* Address of the NVRAM to write to. */
2348 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2349
2350 /* Issue the write command. */
2351 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2352
2353 /* Wait for completion. */
2354 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2355 udelay(5);
2356
2357 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
2358 break;
2359 }
2360 if (j >= NVRAM_TIMEOUT_COUNT)
2361 return -EBUSY;
2362
2363 return 0;
2364}
2365
2366static int
2367bnx2_init_nvram(struct bnx2 *bp)
2368{
2369 u32 val;
2370 int j, entry_count, rc;
2371 struct flash_spec *flash;
2372
2373 /* Determine the selected interface. */
2374 val = REG_RD(bp, BNX2_NVM_CFG1);
2375
2376 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2377
2378 rc = 0;
2379 if (val & 0x40000000) {
2380
2381 /* Flash interface has been reconfigured */
2382 for (j = 0, flash = &flash_table[0]; j < entry_count;
2383 j++, flash++) {
2384
2385 if (val == flash->config1) {
2386 bp->flash_info = flash;
2387 break;
2388 }
2389 }
2390 }
2391 else {
2392 /* Not yet been reconfigured */
2393
2394 for (j = 0, flash = &flash_table[0]; j < entry_count;
2395 j++, flash++) {
2396
2397 if ((val & FLASH_STRAP_MASK) == flash->strapping) {
2398 bp->flash_info = flash;
2399
2400 /* Request access to the flash interface. */
2401 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2402 return rc;
2403
2404 /* Enable access to flash interface */
2405 bnx2_enable_nvram_access(bp);
2406
2407 /* Reconfigure the flash interface */
2408 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
2409 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
2410 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
2411 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
2412
2413 /* Disable access to flash interface */
2414 bnx2_disable_nvram_access(bp);
2415 bnx2_release_nvram_lock(bp);
2416
2417 break;
2418 }
2419 }
2420 } /* if (val & 0x40000000) */
2421
2422 if (j == entry_count) {
2423 bp->flash_info = NULL;
2424 printk(KERN_ALERT "Unknown flash/EEPROM type.\n");
2425 rc = -ENODEV;
2426 }
2427
2428 return rc;
2429}
2430
2431static int
2432bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
2433 int buf_size)
2434{
2435 int rc = 0;
2436 u32 cmd_flags, offset32, len32, extra;
2437
2438 if (buf_size == 0)
2439 return 0;
2440
2441 /* Request access to the flash interface. */
2442 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2443 return rc;
2444
2445 /* Enable access to flash interface */
2446 bnx2_enable_nvram_access(bp);
2447
2448 len32 = buf_size;
2449 offset32 = offset;
2450 extra = 0;
2451
2452 cmd_flags = 0;
2453
2454 if (offset32 & 3) {
2455 u8 buf[4];
2456 u32 pre_len;
2457
2458 offset32 &= ~3;
2459 pre_len = 4 - (offset & 3);
2460
2461 if (pre_len >= len32) {
2462 pre_len = len32;
2463 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2464 BNX2_NVM_COMMAND_LAST;
2465 }
2466 else {
2467 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2468 }
2469
2470 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2471
2472 if (rc)
2473 return rc;
2474
2475 memcpy(ret_buf, buf + (offset & 3), pre_len);
2476
2477 offset32 += 4;
2478 ret_buf += pre_len;
2479 len32 -= pre_len;
2480 }
2481 if (len32 & 3) {
2482 extra = 4 - (len32 & 3);
2483 len32 = (len32 + 4) & ~3;
2484 }
2485
2486 if (len32 == 4) {
2487 u8 buf[4];
2488
2489 if (cmd_flags)
2490 cmd_flags = BNX2_NVM_COMMAND_LAST;
2491 else
2492 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2493 BNX2_NVM_COMMAND_LAST;
2494
2495 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2496
2497 memcpy(ret_buf, buf, 4 - extra);
2498 }
2499 else if (len32 > 0) {
2500 u8 buf[4];
2501
2502 /* Read the first word. */
2503 if (cmd_flags)
2504 cmd_flags = 0;
2505 else
2506 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2507
2508 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
2509
2510 /* Advance to the next dword. */
2511 offset32 += 4;
2512 ret_buf += 4;
2513 len32 -= 4;
2514
2515 while (len32 > 4 && rc == 0) {
2516 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
2517
2518 /* Advance to the next dword. */
2519 offset32 += 4;
2520 ret_buf += 4;
2521 len32 -= 4;
2522 }
2523
2524 if (rc)
2525 return rc;
2526
2527 cmd_flags = BNX2_NVM_COMMAND_LAST;
2528 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2529
2530 memcpy(ret_buf, buf, 4 - extra);
2531 }
2532
2533 /* Disable access to flash interface */
2534 bnx2_disable_nvram_access(bp);
2535
2536 bnx2_release_nvram_lock(bp);
2537
2538 return rc;
2539}
2540
2541static int
2542bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
2543 int buf_size)
2544{
2545 u32 written, offset32, len32;
2546 u8 *buf, start[4], end[4];
2547 int rc = 0;
2548 int align_start, align_end;
2549
2550 buf = data_buf;
2551 offset32 = offset;
2552 len32 = buf_size;
2553 align_start = align_end = 0;
2554
2555 if ((align_start = (offset32 & 3))) {
2556 offset32 &= ~3;
2557 len32 += align_start;
2558 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
2559 return rc;
2560 }
2561
2562 if (len32 & 3) {
2563 if ((len32 > 4) || !align_start) {
2564 align_end = 4 - (len32 & 3);
2565 len32 += align_end;
2566 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
2567 end, 4))) {
2568 return rc;
2569 }
2570 }
2571 }
2572
2573 if (align_start || align_end) {
2574 buf = kmalloc(len32, GFP_KERNEL);
2575 if (buf == 0)
2576 return -ENOMEM;
2577 if (align_start) {
2578 memcpy(buf, start, 4);
2579 }
2580 if (align_end) {
2581 memcpy(buf + len32 - 4, end, 4);
2582 }
2583 memcpy(buf + align_start, data_buf, buf_size);
2584 }
2585
2586 written = 0;
2587 while ((written < len32) && (rc == 0)) {
2588 u32 page_start, page_end, data_start, data_end;
2589 u32 addr, cmd_flags;
2590 int i;
2591 u8 flash_buffer[264];
2592
2593 /* Find the page_start addr */
2594 page_start = offset32 + written;
2595 page_start -= (page_start % bp->flash_info->page_size);
2596 /* Find the page_end addr */
2597 page_end = page_start + bp->flash_info->page_size;
2598 /* Find the data_start addr */
2599 data_start = (written == 0) ? offset32 : page_start;
2600 /* Find the data_end addr */
2601 data_end = (page_end > offset32 + len32) ?
2602 (offset32 + len32) : page_end;
2603
2604 /* Request access to the flash interface. */
2605 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2606 goto nvram_write_end;
2607
2608 /* Enable access to flash interface */
2609 bnx2_enable_nvram_access(bp);
2610
2611 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2612 if (bp->flash_info->buffered == 0) {
2613 int j;
2614
2615 /* Read the whole page into the buffer
2616 * (non-buffer flash only) */
2617 for (j = 0; j < bp->flash_info->page_size; j += 4) {
2618 if (j == (bp->flash_info->page_size - 4)) {
2619 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2620 }
2621 rc = bnx2_nvram_read_dword(bp,
2622 page_start + j,
2623 &flash_buffer[j],
2624 cmd_flags);
2625
2626 if (rc)
2627 goto nvram_write_end;
2628
2629 cmd_flags = 0;
2630 }
2631 }
2632
2633 /* Enable writes to flash interface (unlock write-protect) */
2634 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
2635 goto nvram_write_end;
2636
2637 /* Erase the page */
2638 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
2639 goto nvram_write_end;
2640
2641 /* Re-enable the write again for the actual write */
2642 bnx2_enable_nvram_write(bp);
2643
2644 /* Loop to write back the buffer data from page_start to
2645 * data_start */
2646 i = 0;
2647 if (bp->flash_info->buffered == 0) {
2648 for (addr = page_start; addr < data_start;
2649 addr += 4, i += 4) {
2650
2651 rc = bnx2_nvram_write_dword(bp, addr,
2652 &flash_buffer[i], cmd_flags);
2653
2654 if (rc != 0)
2655 goto nvram_write_end;
2656
2657 cmd_flags = 0;
2658 }
2659 }
2660
2661 /* Loop to write the new data from data_start to data_end */
2662 for (addr = data_start; addr < data_end; addr += 4, i++) {
2663 if ((addr == page_end - 4) ||
2664 ((bp->flash_info->buffered) &&
2665 (addr == data_end - 4))) {
2666
2667 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2668 }
2669 rc = bnx2_nvram_write_dword(bp, addr, buf,
2670 cmd_flags);
2671
2672 if (rc != 0)
2673 goto nvram_write_end;
2674
2675 cmd_flags = 0;
2676 buf += 4;
2677 }
2678
2679 /* Loop to write back the buffer data from data_end
2680 * to page_end */
2681 if (bp->flash_info->buffered == 0) {
2682 for (addr = data_end; addr < page_end;
2683 addr += 4, i += 4) {
2684
2685 if (addr == page_end-4) {
2686 cmd_flags = BNX2_NVM_COMMAND_LAST;
2687 }
2688 rc = bnx2_nvram_write_dword(bp, addr,
2689 &flash_buffer[i], cmd_flags);
2690
2691 if (rc != 0)
2692 goto nvram_write_end;
2693
2694 cmd_flags = 0;
2695 }
2696 }
2697
2698 /* Disable writes to flash interface (lock write-protect) */
2699 bnx2_disable_nvram_write(bp);
2700
2701 /* Disable access to flash interface */
2702 bnx2_disable_nvram_access(bp);
2703 bnx2_release_nvram_lock(bp);
2704
2705 /* Increment written */
2706 written += data_end - data_start;
2707 }
2708
2709nvram_write_end:
2710 if (align_start || align_end)
2711 kfree(buf);
2712 return rc;
2713}
2714
2715static int
2716bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
2717{
2718 u32 val;
2719 int i, rc = 0;
2720
2721 /* Wait for the current PCI transaction to complete before
2722 * issuing a reset. */
2723 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
2724 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
2725 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
2726 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
2727 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
2728 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
2729 udelay(5);
2730
2731 /* Deposit a driver reset signature so the firmware knows that
2732 * this is a soft reset. */
2733 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_RESET_SIGNATURE,
2734 BNX2_DRV_RESET_SIGNATURE_MAGIC);
2735
2736 bp->fw_timed_out = 0;
2737
2738 /* Wait for the firmware to tell us it is ok to issue a reset. */
2739 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code);
2740
2741 /* Do a dummy read to force the chip to complete all current transaction
2742 * before we issue a reset. */
2743 val = REG_RD(bp, BNX2_MISC_ID);
2744
2745 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2746 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
2747 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
2748
2749 /* Chip reset. */
2750 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
2751
2752 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2753 (CHIP_ID(bp) == CHIP_ID_5706_A1))
2754 msleep(15);
2755
2756 /* Reset takes approximate 30 usec */
2757 for (i = 0; i < 10; i++) {
2758 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
2759 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2760 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
2761 break;
2762 }
2763 udelay(10);
2764 }
2765
2766 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2767 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
2768 printk(KERN_ERR PFX "Chip reset did not complete\n");
2769 return -EBUSY;
2770 }
2771
2772 /* Make sure byte swapping is properly configured. */
2773 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
2774 if (val != 0x01020304) {
2775 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
2776 return -ENODEV;
2777 }
2778
2779 bp->fw_timed_out = 0;
2780
2781 /* Wait for the firmware to finish its initialization. */
2782 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code);
2783
2784 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2785 /* Adjust the voltage regular to two steps lower. The default
2786 * of this register is 0x0000000e. */
2787 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
2788
2789 /* Remove bad rbuf memory from the free pool. */
2790 rc = bnx2_alloc_bad_rbuf(bp);
2791 }
2792
2793 return rc;
2794}
2795
2796static int
2797bnx2_init_chip(struct bnx2 *bp)
2798{
2799 u32 val;
2800
2801 /* Make sure the interrupt is not active. */
2802 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2803
2804 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
2805 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
2806#ifdef __BIG_ENDIAN
2807 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
2808#endif
2809 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
2810 DMA_READ_CHANS << 12 |
2811 DMA_WRITE_CHANS << 16;
2812
2813 val |= (0x2 << 20) | (1 << 11);
2814
2815 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz = 133))
2816 val |= (1 << 23);
2817
2818 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
2819 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
2820 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
2821
2822 REG_WR(bp, BNX2_DMA_CONFIG, val);
2823
2824 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2825 val = REG_RD(bp, BNX2_TDMA_CONFIG);
2826 val |= BNX2_TDMA_CONFIG_ONE_DMA;
2827 REG_WR(bp, BNX2_TDMA_CONFIG, val);
2828 }
2829
2830 if (bp->flags & PCIX_FLAG) {
2831 u16 val16;
2832
2833 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
2834 &val16);
2835 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
2836 val16 & ~PCI_X_CMD_ERO);
2837 }
2838
2839 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2840 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
2841 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
2842 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
2843
2844 /* Initialize context mapping and zero out the quick contexts. The
2845 * context block must have already been enabled. */
2846 bnx2_init_context(bp);
2847
2848 bnx2_init_cpus(bp);
2849 bnx2_init_nvram(bp);
2850
2851 bnx2_set_mac_addr(bp);
2852
2853 val = REG_RD(bp, BNX2_MQ_CONFIG);
2854 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
2855 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
2856 REG_WR(bp, BNX2_MQ_CONFIG, val);
2857
2858 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
2859 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
2860 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
2861
2862 val = (BCM_PAGE_BITS - 8) << 24;
2863 REG_WR(bp, BNX2_RV2P_CONFIG, val);
2864
2865 /* Configure page size. */
2866 val = REG_RD(bp, BNX2_TBDR_CONFIG);
2867 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
2868 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
2869 REG_WR(bp, BNX2_TBDR_CONFIG, val);
2870
2871 val = bp->mac_addr[0] +
2872 (bp->mac_addr[1] << 8) +
2873 (bp->mac_addr[2] << 16) +
2874 bp->mac_addr[3] +
2875 (bp->mac_addr[4] << 8) +
2876 (bp->mac_addr[5] << 16);
2877 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
2878
2879 /* Program the MTU. Also include 4 bytes for CRC32. */
2880 val = bp->dev->mtu + ETH_HLEN + 4;
2881 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
2882 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
2883 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
2884
2885 bp->last_status_idx = 0;
2886 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
2887
2888 /* Set up how to generate a link change interrupt. */
2889 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2890
2891 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
2892 (u64) bp->status_blk_mapping & 0xffffffff);
2893 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
2894
2895 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
2896 (u64) bp->stats_blk_mapping & 0xffffffff);
2897 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
2898 (u64) bp->stats_blk_mapping >> 32);
2899
2900 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
2901 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
2902
2903 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
2904 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
2905
2906 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
2907 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
2908
2909 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
2910
2911 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
2912
2913 REG_WR(bp, BNX2_HC_COM_TICKS,
2914 (bp->com_ticks_int << 16) | bp->com_ticks);
2915
2916 REG_WR(bp, BNX2_HC_CMD_TICKS,
2917 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
2918
2919 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
2920 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
2921
2922 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
2923 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
2924 else {
2925 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
2926 BNX2_HC_CONFIG_TX_TMR_MODE |
2927 BNX2_HC_CONFIG_COLLECT_STATS);
2928 }
2929
2930 /* Clear internal stats counters. */
2931 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
2932
2933 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
2934
2935 /* Initialize the receive filter. */
2936 bnx2_set_rx_mode(bp->dev);
2937
2938 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET);
2939
2940 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
2941 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
2942
2943 udelay(20);
2944
2945 return 0;
2946}
2947
2948
2949static void
2950bnx2_init_tx_ring(struct bnx2 *bp)
2951{
2952 struct tx_bd *txbd;
2953 u32 val;
2954
2955 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
2956
2957 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
2958 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
2959
2960 bp->tx_prod = 0;
2961 bp->tx_cons = 0;
2962 bp->tx_prod_bseq = 0;
2963 atomic_set(&bp->tx_avail_bd, bp->tx_ring_size);
2964
2965 val = BNX2_L2CTX_TYPE_TYPE_L2;
2966 val |= BNX2_L2CTX_TYPE_SIZE_L2;
2967 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
2968
2969 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
2970 val |= 8 << 16;
2971 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
2972
2973 val = (u64) bp->tx_desc_mapping >> 32;
2974 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
2975
2976 val = (u64) bp->tx_desc_mapping & 0xffffffff;
2977 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
2978}
2979
2980static void
2981bnx2_init_rx_ring(struct bnx2 *bp)
2982{
2983 struct rx_bd *rxbd;
2984 int i;
2985 u16 prod, ring_prod;
2986 u32 val;
2987
2988 /* 8 for CRC and VLAN */
2989 bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
2990 /* 8 for alignment */
2991 bp->rx_buf_size = bp->rx_buf_use_size + 8;
2992
2993 ring_prod = prod = bp->rx_prod = 0;
2994 bp->rx_cons = 0;
2995 bp->rx_prod_bseq = 0;
2996
2997 rxbd = &bp->rx_desc_ring[0];
2998 for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
2999 rxbd->rx_bd_len = bp->rx_buf_use_size;
3000 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3001 }
3002
3003 rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;
3004 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
3005
3006 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3007 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
3008 val |= 0x02 << 8;
3009 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
3010
3011 val = (u64) bp->rx_desc_mapping >> 32;
3012 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
3013
3014 val = (u64) bp->rx_desc_mapping & 0xffffffff;
3015 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
3016
3017 for ( ;ring_prod < bp->rx_ring_size; ) {
3018 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
3019 break;
3020 }
3021 prod = NEXT_RX_BD(prod);
3022 ring_prod = RX_RING_IDX(prod);
3023 }
3024 bp->rx_prod = prod;
3025
3026 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
3027
3028 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
3029}
3030
3031static void
3032bnx2_free_tx_skbs(struct bnx2 *bp)
3033{
3034 int i;
3035
3036 if (bp->tx_buf_ring == NULL)
3037 return;
3038
3039 for (i = 0; i < TX_DESC_CNT; ) {
3040 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
3041 struct sk_buff *skb = tx_buf->skb;
3042 int j, last;
3043
3044 if (skb == NULL) {
3045 i++;
3046 continue;
3047 }
3048
3049 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
3050 skb_headlen(skb), PCI_DMA_TODEVICE);
3051
3052 tx_buf->skb = NULL;
3053
3054 last = skb_shinfo(skb)->nr_frags;
3055 for (j = 0; j < last; j++) {
3056 tx_buf = &bp->tx_buf_ring[i + j + 1];
3057 pci_unmap_page(bp->pdev,
3058 pci_unmap_addr(tx_buf, mapping),
3059 skb_shinfo(skb)->frags[j].size,
3060 PCI_DMA_TODEVICE);
3061 }
3062 dev_kfree_skb_any(skb);
3063 i += j + 1;
3064 }
3065
3066}
3067
3068static void
3069bnx2_free_rx_skbs(struct bnx2 *bp)
3070{
3071 int i;
3072
3073 if (bp->rx_buf_ring == NULL)
3074 return;
3075
3076 for (i = 0; i < RX_DESC_CNT; i++) {
3077 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
3078 struct sk_buff *skb = rx_buf->skb;
3079
3080 if (skb == 0)
3081 continue;
3082
3083 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
3084 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
3085
3086 rx_buf->skb = NULL;
3087
3088 dev_kfree_skb_any(skb);
3089 }
3090}
3091
3092static void
3093bnx2_free_skbs(struct bnx2 *bp)
3094{
3095 bnx2_free_tx_skbs(bp);
3096 bnx2_free_rx_skbs(bp);
3097}
3098
3099static int
3100bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
3101{
3102 int rc;
3103
3104 rc = bnx2_reset_chip(bp, reset_code);
3105 bnx2_free_skbs(bp);
3106 if (rc)
3107 return rc;
3108
3109 bnx2_init_chip(bp);
3110 bnx2_init_tx_ring(bp);
3111 bnx2_init_rx_ring(bp);
3112 return 0;
3113}
3114
3115static int
3116bnx2_init_nic(struct bnx2 *bp)
3117{
3118 int rc;
3119
3120 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
3121 return rc;
3122
3123 bnx2_init_phy(bp);
3124 bnx2_set_link(bp);
3125 return 0;
3126}
3127
3128static int
3129bnx2_test_registers(struct bnx2 *bp)
3130{
3131 int ret;
3132 int i;
3133 static struct {
3134 u16 offset;
3135 u16 flags;
3136 u32 rw_mask;
3137 u32 ro_mask;
3138 } reg_tbl[] = {
3139 { 0x006c, 0, 0x00000000, 0x0000003f },
3140 { 0x0090, 0, 0xffffffff, 0x00000000 },
3141 { 0x0094, 0, 0x00000000, 0x00000000 },
3142
3143 { 0x0404, 0, 0x00003f00, 0x00000000 },
3144 { 0x0418, 0, 0x00000000, 0xffffffff },
3145 { 0x041c, 0, 0x00000000, 0xffffffff },
3146 { 0x0420, 0, 0x00000000, 0x80ffffff },
3147 { 0x0424, 0, 0x00000000, 0x00000000 },
3148 { 0x0428, 0, 0x00000000, 0x00000001 },
3149 { 0x0450, 0, 0x00000000, 0x0000ffff },
3150 { 0x0454, 0, 0x00000000, 0xffffffff },
3151 { 0x0458, 0, 0x00000000, 0xffffffff },
3152
3153 { 0x0808, 0, 0x00000000, 0xffffffff },
3154 { 0x0854, 0, 0x00000000, 0xffffffff },
3155 { 0x0868, 0, 0x00000000, 0x77777777 },
3156 { 0x086c, 0, 0x00000000, 0x77777777 },
3157 { 0x0870, 0, 0x00000000, 0x77777777 },
3158 { 0x0874, 0, 0x00000000, 0x77777777 },
3159
3160 { 0x0c00, 0, 0x00000000, 0x00000001 },
3161 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3162 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
3163 { 0x0c0c, 0, 0x00ffffff, 0x00000000 },
3164 { 0x0c30, 0, 0x00000000, 0xffffffff },
3165 { 0x0c34, 0, 0x00000000, 0xffffffff },
3166 { 0x0c38, 0, 0x00000000, 0xffffffff },
3167 { 0x0c3c, 0, 0x00000000, 0xffffffff },
3168 { 0x0c40, 0, 0x00000000, 0xffffffff },
3169 { 0x0c44, 0, 0x00000000, 0xffffffff },
3170 { 0x0c48, 0, 0x00000000, 0x0007ffff },
3171 { 0x0c4c, 0, 0x00000000, 0xffffffff },
3172 { 0x0c50, 0, 0x00000000, 0xffffffff },
3173 { 0x0c54, 0, 0x00000000, 0xffffffff },
3174 { 0x0c58, 0, 0x00000000, 0xffffffff },
3175 { 0x0c5c, 0, 0x00000000, 0xffffffff },
3176 { 0x0c60, 0, 0x00000000, 0xffffffff },
3177 { 0x0c64, 0, 0x00000000, 0xffffffff },
3178 { 0x0c68, 0, 0x00000000, 0xffffffff },
3179 { 0x0c6c, 0, 0x00000000, 0xffffffff },
3180 { 0x0c70, 0, 0x00000000, 0xffffffff },
3181 { 0x0c74, 0, 0x00000000, 0xffffffff },
3182 { 0x0c78, 0, 0x00000000, 0xffffffff },
3183 { 0x0c7c, 0, 0x00000000, 0xffffffff },
3184 { 0x0c80, 0, 0x00000000, 0xffffffff },
3185 { 0x0c84, 0, 0x00000000, 0xffffffff },
3186 { 0x0c88, 0, 0x00000000, 0xffffffff },
3187 { 0x0c8c, 0, 0x00000000, 0xffffffff },
3188 { 0x0c90, 0, 0x00000000, 0xffffffff },
3189 { 0x0c94, 0, 0x00000000, 0xffffffff },
3190 { 0x0c98, 0, 0x00000000, 0xffffffff },
3191 { 0x0c9c, 0, 0x00000000, 0xffffffff },
3192 { 0x0ca0, 0, 0x00000000, 0xffffffff },
3193 { 0x0ca4, 0, 0x00000000, 0xffffffff },
3194 { 0x0ca8, 0, 0x00000000, 0x0007ffff },
3195 { 0x0cac, 0, 0x00000000, 0xffffffff },
3196 { 0x0cb0, 0, 0x00000000, 0xffffffff },
3197 { 0x0cb4, 0, 0x00000000, 0xffffffff },
3198 { 0x0cb8, 0, 0x00000000, 0xffffffff },
3199 { 0x0cbc, 0, 0x00000000, 0xffffffff },
3200 { 0x0cc0, 0, 0x00000000, 0xffffffff },
3201 { 0x0cc4, 0, 0x00000000, 0xffffffff },
3202 { 0x0cc8, 0, 0x00000000, 0xffffffff },
3203 { 0x0ccc, 0, 0x00000000, 0xffffffff },
3204 { 0x0cd0, 0, 0x00000000, 0xffffffff },
3205 { 0x0cd4, 0, 0x00000000, 0xffffffff },
3206 { 0x0cd8, 0, 0x00000000, 0xffffffff },
3207 { 0x0cdc, 0, 0x00000000, 0xffffffff },
3208 { 0x0ce0, 0, 0x00000000, 0xffffffff },
3209 { 0x0ce4, 0, 0x00000000, 0xffffffff },
3210 { 0x0ce8, 0, 0x00000000, 0xffffffff },
3211 { 0x0cec, 0, 0x00000000, 0xffffffff },
3212 { 0x0cf0, 0, 0x00000000, 0xffffffff },
3213 { 0x0cf4, 0, 0x00000000, 0xffffffff },
3214 { 0x0cf8, 0, 0x00000000, 0xffffffff },
3215 { 0x0cfc, 0, 0x00000000, 0xffffffff },
3216 { 0x0d00, 0, 0x00000000, 0xffffffff },
3217 { 0x0d04, 0, 0x00000000, 0xffffffff },
3218
3219 { 0x1000, 0, 0x00000000, 0x00000001 },
3220 { 0x1004, 0, 0x00000000, 0x000f0001 },
3221 { 0x1044, 0, 0x00000000, 0xffc003ff },
3222 { 0x1080, 0, 0x00000000, 0x0001ffff },
3223 { 0x1084, 0, 0x00000000, 0xffffffff },
3224 { 0x1088, 0, 0x00000000, 0xffffffff },
3225 { 0x108c, 0, 0x00000000, 0xffffffff },
3226 { 0x1090, 0, 0x00000000, 0xffffffff },
3227 { 0x1094, 0, 0x00000000, 0xffffffff },
3228 { 0x1098, 0, 0x00000000, 0xffffffff },
3229 { 0x109c, 0, 0x00000000, 0xffffffff },
3230 { 0x10a0, 0, 0x00000000, 0xffffffff },
3231
3232 { 0x1408, 0, 0x01c00800, 0x00000000 },
3233 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3234 { 0x14a8, 0, 0x00000000, 0x000001ff },
3235 { 0x14ac, 0, 0x4fffffff, 0x10000000 },
3236 { 0x14b0, 0, 0x00000002, 0x00000001 },
3237 { 0x14b8, 0, 0x00000000, 0x00000000 },
3238 { 0x14c0, 0, 0x00000000, 0x00000009 },
3239 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3240 { 0x14cc, 0, 0x00000000, 0x00000001 },
3241 { 0x14d0, 0, 0xffffffff, 0x00000000 },
3242 { 0x1500, 0, 0x00000000, 0xffffffff },
3243 { 0x1504, 0, 0x00000000, 0xffffffff },
3244 { 0x1508, 0, 0x00000000, 0xffffffff },
3245 { 0x150c, 0, 0x00000000, 0xffffffff },
3246 { 0x1510, 0, 0x00000000, 0xffffffff },
3247 { 0x1514, 0, 0x00000000, 0xffffffff },
3248 { 0x1518, 0, 0x00000000, 0xffffffff },
3249 { 0x151c, 0, 0x00000000, 0xffffffff },
3250 { 0x1520, 0, 0x00000000, 0xffffffff },
3251 { 0x1524, 0, 0x00000000, 0xffffffff },
3252 { 0x1528, 0, 0x00000000, 0xffffffff },
3253 { 0x152c, 0, 0x00000000, 0xffffffff },
3254 { 0x1530, 0, 0x00000000, 0xffffffff },
3255 { 0x1534, 0, 0x00000000, 0xffffffff },
3256 { 0x1538, 0, 0x00000000, 0xffffffff },
3257 { 0x153c, 0, 0x00000000, 0xffffffff },
3258 { 0x1540, 0, 0x00000000, 0xffffffff },
3259 { 0x1544, 0, 0x00000000, 0xffffffff },
3260 { 0x1548, 0, 0x00000000, 0xffffffff },
3261 { 0x154c, 0, 0x00000000, 0xffffffff },
3262 { 0x1550, 0, 0x00000000, 0xffffffff },
3263 { 0x1554, 0, 0x00000000, 0xffffffff },
3264 { 0x1558, 0, 0x00000000, 0xffffffff },
3265 { 0x1600, 0, 0x00000000, 0xffffffff },
3266 { 0x1604, 0, 0x00000000, 0xffffffff },
3267 { 0x1608, 0, 0x00000000, 0xffffffff },
3268 { 0x160c, 0, 0x00000000, 0xffffffff },
3269 { 0x1610, 0, 0x00000000, 0xffffffff },
3270 { 0x1614, 0, 0x00000000, 0xffffffff },
3271 { 0x1618, 0, 0x00000000, 0xffffffff },
3272 { 0x161c, 0, 0x00000000, 0xffffffff },
3273 { 0x1620, 0, 0x00000000, 0xffffffff },
3274 { 0x1624, 0, 0x00000000, 0xffffffff },
3275 { 0x1628, 0, 0x00000000, 0xffffffff },
3276 { 0x162c, 0, 0x00000000, 0xffffffff },
3277 { 0x1630, 0, 0x00000000, 0xffffffff },
3278 { 0x1634, 0, 0x00000000, 0xffffffff },
3279 { 0x1638, 0, 0x00000000, 0xffffffff },
3280 { 0x163c, 0, 0x00000000, 0xffffffff },
3281 { 0x1640, 0, 0x00000000, 0xffffffff },
3282 { 0x1644, 0, 0x00000000, 0xffffffff },
3283 { 0x1648, 0, 0x00000000, 0xffffffff },
3284 { 0x164c, 0, 0x00000000, 0xffffffff },
3285 { 0x1650, 0, 0x00000000, 0xffffffff },
3286 { 0x1654, 0, 0x00000000, 0xffffffff },
3287
3288 { 0x1800, 0, 0x00000000, 0x00000001 },
3289 { 0x1804, 0, 0x00000000, 0x00000003 },
3290 { 0x1840, 0, 0x00000000, 0xffffffff },
3291 { 0x1844, 0, 0x00000000, 0xffffffff },
3292 { 0x1848, 0, 0x00000000, 0xffffffff },
3293 { 0x184c, 0, 0x00000000, 0xffffffff },
3294 { 0x1850, 0, 0x00000000, 0xffffffff },
3295 { 0x1900, 0, 0x7ffbffff, 0x00000000 },
3296 { 0x1904, 0, 0xffffffff, 0x00000000 },
3297 { 0x190c, 0, 0xffffffff, 0x00000000 },
3298 { 0x1914, 0, 0xffffffff, 0x00000000 },
3299 { 0x191c, 0, 0xffffffff, 0x00000000 },
3300 { 0x1924, 0, 0xffffffff, 0x00000000 },
3301 { 0x192c, 0, 0xffffffff, 0x00000000 },
3302 { 0x1934, 0, 0xffffffff, 0x00000000 },
3303 { 0x193c, 0, 0xffffffff, 0x00000000 },
3304 { 0x1944, 0, 0xffffffff, 0x00000000 },
3305 { 0x194c, 0, 0xffffffff, 0x00000000 },
3306 { 0x1954, 0, 0xffffffff, 0x00000000 },
3307 { 0x195c, 0, 0xffffffff, 0x00000000 },
3308 { 0x1964, 0, 0xffffffff, 0x00000000 },
3309 { 0x196c, 0, 0xffffffff, 0x00000000 },
3310 { 0x1974, 0, 0xffffffff, 0x00000000 },
3311 { 0x197c, 0, 0xffffffff, 0x00000000 },
3312 { 0x1980, 0, 0x0700ffff, 0x00000000 },
3313
3314 { 0x1c00, 0, 0x00000000, 0x00000001 },
3315 { 0x1c04, 0, 0x00000000, 0x00000003 },
3316 { 0x1c08, 0, 0x0000000f, 0x00000000 },
3317 { 0x1c40, 0, 0x00000000, 0xffffffff },
3318 { 0x1c44, 0, 0x00000000, 0xffffffff },
3319 { 0x1c48, 0, 0x00000000, 0xffffffff },
3320 { 0x1c4c, 0, 0x00000000, 0xffffffff },
3321 { 0x1c50, 0, 0x00000000, 0xffffffff },
3322 { 0x1d00, 0, 0x7ffbffff, 0x00000000 },
3323 { 0x1d04, 0, 0xffffffff, 0x00000000 },
3324 { 0x1d0c, 0, 0xffffffff, 0x00000000 },
3325 { 0x1d14, 0, 0xffffffff, 0x00000000 },
3326 { 0x1d1c, 0, 0xffffffff, 0x00000000 },
3327 { 0x1d24, 0, 0xffffffff, 0x00000000 },
3328 { 0x1d2c, 0, 0xffffffff, 0x00000000 },
3329 { 0x1d34, 0, 0xffffffff, 0x00000000 },
3330 { 0x1d3c, 0, 0xffffffff, 0x00000000 },
3331 { 0x1d44, 0, 0xffffffff, 0x00000000 },
3332 { 0x1d4c, 0, 0xffffffff, 0x00000000 },
3333 { 0x1d54, 0, 0xffffffff, 0x00000000 },
3334 { 0x1d5c, 0, 0xffffffff, 0x00000000 },
3335 { 0x1d64, 0, 0xffffffff, 0x00000000 },
3336 { 0x1d6c, 0, 0xffffffff, 0x00000000 },
3337 { 0x1d74, 0, 0xffffffff, 0x00000000 },
3338 { 0x1d7c, 0, 0xffffffff, 0x00000000 },
3339 { 0x1d80, 0, 0x0700ffff, 0x00000000 },
3340
3341 { 0x2004, 0, 0x00000000, 0x0337000f },
3342 { 0x2008, 0, 0xffffffff, 0x00000000 },
3343 { 0x200c, 0, 0xffffffff, 0x00000000 },
3344 { 0x2010, 0, 0xffffffff, 0x00000000 },
3345 { 0x2014, 0, 0x801fff80, 0x00000000 },
3346 { 0x2018, 0, 0x000003ff, 0x00000000 },
3347
3348 { 0x2800, 0, 0x00000000, 0x00000001 },
3349 { 0x2804, 0, 0x00000000, 0x00003f01 },
3350 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
3351 { 0x2810, 0, 0xffff0000, 0x00000000 },
3352 { 0x2814, 0, 0xffff0000, 0x00000000 },
3353 { 0x2818, 0, 0xffff0000, 0x00000000 },
3354 { 0x281c, 0, 0xffff0000, 0x00000000 },
3355 { 0x2834, 0, 0xffffffff, 0x00000000 },
3356 { 0x2840, 0, 0x00000000, 0xffffffff },
3357 { 0x2844, 0, 0x00000000, 0xffffffff },
3358 { 0x2848, 0, 0xffffffff, 0x00000000 },
3359 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
3360
3361 { 0x2c00, 0, 0x00000000, 0x00000011 },
3362 { 0x2c04, 0, 0x00000000, 0x00030007 },
3363
3364 { 0x3000, 0, 0x00000000, 0x00000001 },
3365 { 0x3004, 0, 0x00000000, 0x007007ff },
3366 { 0x3008, 0, 0x00000003, 0x00000000 },
3367 { 0x300c, 0, 0xffffffff, 0x00000000 },
3368 { 0x3010, 0, 0xffffffff, 0x00000000 },
3369 { 0x3014, 0, 0xffffffff, 0x00000000 },
3370 { 0x3034, 0, 0xffffffff, 0x00000000 },
3371 { 0x3038, 0, 0xffffffff, 0x00000000 },
3372 { 0x3050, 0, 0x00000001, 0x00000000 },
3373
3374 { 0x3c00, 0, 0x00000000, 0x00000001 },
3375 { 0x3c04, 0, 0x00000000, 0x00070000 },
3376 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
3377 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
3378 { 0x3c10, 0, 0xffffffff, 0x00000000 },
3379 { 0x3c14, 0, 0x00000000, 0xffffffff },
3380 { 0x3c18, 0, 0x00000000, 0xffffffff },
3381 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3382 { 0x3c20, 0, 0xffffff00, 0x00000000 },
3383 { 0x3c24, 0, 0xffffffff, 0x00000000 },
3384 { 0x3c28, 0, 0xffffffff, 0x00000000 },
3385 { 0x3c2c, 0, 0xffffffff, 0x00000000 },
3386 { 0x3c30, 0, 0xffffffff, 0x00000000 },
3387 { 0x3c34, 0, 0xffffffff, 0x00000000 },
3388 { 0x3c38, 0, 0xffffffff, 0x00000000 },
3389 { 0x3c3c, 0, 0xffffffff, 0x00000000 },
3390 { 0x3c40, 0, 0xffffffff, 0x00000000 },
3391 { 0x3c44, 0, 0xffffffff, 0x00000000 },
3392 { 0x3c48, 0, 0xffffffff, 0x00000000 },
3393 { 0x3c4c, 0, 0xffffffff, 0x00000000 },
3394 { 0x3c50, 0, 0xffffffff, 0x00000000 },
3395 { 0x3c54, 0, 0xffffffff, 0x00000000 },
3396 { 0x3c58, 0, 0xffffffff, 0x00000000 },
3397 { 0x3c5c, 0, 0xffffffff, 0x00000000 },
3398 { 0x3c60, 0, 0xffffffff, 0x00000000 },
3399 { 0x3c64, 0, 0xffffffff, 0x00000000 },
3400 { 0x3c68, 0, 0xffffffff, 0x00000000 },
3401 { 0x3c6c, 0, 0xffffffff, 0x00000000 },
3402 { 0x3c70, 0, 0xffffffff, 0x00000000 },
3403 { 0x3c74, 0, 0x0000003f, 0x00000000 },
3404 { 0x3c78, 0, 0x00000000, 0x00000000 },
3405 { 0x3c7c, 0, 0x00000000, 0x00000000 },
3406 { 0x3c80, 0, 0x3fffffff, 0x00000000 },
3407 { 0x3c84, 0, 0x0000003f, 0x00000000 },
3408 { 0x3c88, 0, 0x00000000, 0xffffffff },
3409 { 0x3c8c, 0, 0x00000000, 0xffffffff },
3410
3411 { 0x4000, 0, 0x00000000, 0x00000001 },
3412 { 0x4004, 0, 0x00000000, 0x00030000 },
3413 { 0x4008, 0, 0x00000ff0, 0x00000000 },
3414 { 0x400c, 0, 0xffffffff, 0x00000000 },
3415 { 0x4088, 0, 0x00000000, 0x00070303 },
3416
3417 { 0x4400, 0, 0x00000000, 0x00000001 },
3418 { 0x4404, 0, 0x00000000, 0x00003f01 },
3419 { 0x4408, 0, 0x7fff00ff, 0x00000000 },
3420 { 0x440c, 0, 0xffffffff, 0x00000000 },
3421 { 0x4410, 0, 0xffff, 0x0000 },
3422 { 0x4414, 0, 0xffff, 0x0000 },
3423 { 0x4418, 0, 0xffff, 0x0000 },
3424 { 0x441c, 0, 0xffff, 0x0000 },
3425 { 0x4428, 0, 0xffffffff, 0x00000000 },
3426 { 0x442c, 0, 0xffffffff, 0x00000000 },
3427 { 0x4430, 0, 0xffffffff, 0x00000000 },
3428 { 0x4434, 0, 0xffffffff, 0x00000000 },
3429 { 0x4438, 0, 0xffffffff, 0x00000000 },
3430 { 0x443c, 0, 0xffffffff, 0x00000000 },
3431 { 0x4440, 0, 0xffffffff, 0x00000000 },
3432 { 0x4444, 0, 0xffffffff, 0x00000000 },
3433
3434 { 0x4c00, 0, 0x00000000, 0x00000001 },
3435 { 0x4c04, 0, 0x00000000, 0x0000003f },
3436 { 0x4c08, 0, 0xffffffff, 0x00000000 },
3437 { 0x4c0c, 0, 0x0007fc00, 0x00000000 },
3438 { 0x4c10, 0, 0x80003fe0, 0x00000000 },
3439 { 0x4c14, 0, 0xffffffff, 0x00000000 },
3440 { 0x4c44, 0, 0x00000000, 0x9fff9fff },
3441 { 0x4c48, 0, 0x00000000, 0xb3009fff },
3442 { 0x4c4c, 0, 0x00000000, 0x77f33b30 },
3443 { 0x4c50, 0, 0x00000000, 0xffffffff },
3444
3445 { 0x5004, 0, 0x00000000, 0x0000007f },
3446 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3447 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3448
3449 { 0x5400, 0, 0x00000008, 0x00000001 },
3450 { 0x5404, 0, 0x00000000, 0x0000003f },
3451 { 0x5408, 0, 0x0000001f, 0x00000000 },
3452 { 0x540c, 0, 0xffffffff, 0x00000000 },
3453 { 0x5410, 0, 0xffffffff, 0x00000000 },
3454 { 0x5414, 0, 0x0000ffff, 0x00000000 },
3455 { 0x5418, 0, 0x0000ffff, 0x00000000 },
3456 { 0x541c, 0, 0x0000ffff, 0x00000000 },
3457 { 0x5420, 0, 0x0000ffff, 0x00000000 },
3458 { 0x5428, 0, 0x000000ff, 0x00000000 },
3459 { 0x542c, 0, 0xff00ffff, 0x00000000 },
3460 { 0x5430, 0, 0x001fff80, 0x00000000 },
3461 { 0x5438, 0, 0xffffffff, 0x00000000 },
3462 { 0x543c, 0, 0xffffffff, 0x00000000 },
3463 { 0x5440, 0, 0xf800f800, 0x07ff07ff },
3464
3465 { 0x5c00, 0, 0x00000000, 0x00000001 },
3466 { 0x5c04, 0, 0x00000000, 0x0003000f },
3467 { 0x5c08, 0, 0x00000003, 0x00000000 },
3468 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
3469 { 0x5c10, 0, 0x00000000, 0xffffffff },
3470 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
3471 { 0x5c84, 0, 0x00000000, 0x0000f333 },
3472 { 0x5c88, 0, 0x00000000, 0x00077373 },
3473 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
3474
3475 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
3476 { 0x680c, 0, 0xffffffff, 0x00000000 },
3477 { 0x6810, 0, 0xffffffff, 0x00000000 },
3478 { 0x6814, 0, 0xffffffff, 0x00000000 },
3479 { 0x6818, 0, 0xffffffff, 0x00000000 },
3480 { 0x681c, 0, 0xffffffff, 0x00000000 },
3481 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
3482 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
3483 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
3484 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
3485 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
3486 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
3487 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
3488 { 0x683c, 0, 0x0000ffff, 0x00000000 },
3489 { 0x6840, 0, 0x00000ff0, 0x00000000 },
3490 { 0x6844, 0, 0x00ffff00, 0x00000000 },
3491 { 0x684c, 0, 0xffffffff, 0x00000000 },
3492 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
3493 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
3494 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
3495 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
3496 { 0x6908, 0, 0x00000000, 0x0001ff0f },
3497 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
3498
3499 { 0xffff, 0, 0x00000000, 0x00000000 },
3500 };
3501
3502 ret = 0;
3503 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
3504 u32 offset, rw_mask, ro_mask, save_val, val;
3505
3506 offset = (u32) reg_tbl[i].offset;
3507 rw_mask = reg_tbl[i].rw_mask;
3508 ro_mask = reg_tbl[i].ro_mask;
3509
3510 save_val = readl((u8 *) bp->regview + offset);
3511
3512 writel(0, (u8 *) bp->regview + offset);
3513
3514 val = readl((u8 *) bp->regview + offset);
3515 if ((val & rw_mask) != 0) {
3516 goto reg_test_err;
3517 }
3518
3519 if ((val & ro_mask) != (save_val & ro_mask)) {
3520 goto reg_test_err;
3521 }
3522
3523 writel(0xffffffff, (u8 *) bp->regview + offset);
3524
3525 val = readl((u8 *) bp->regview + offset);
3526 if ((val & rw_mask) != rw_mask) {
3527 goto reg_test_err;
3528 }
3529
3530 if ((val & ro_mask) != (save_val & ro_mask)) {
3531 goto reg_test_err;
3532 }
3533
3534 writel(save_val, (u8 *) bp->regview + offset);
3535 continue;
3536
3537reg_test_err:
3538 writel(save_val, (u8 *) bp->regview + offset);
3539 ret = -ENODEV;
3540 break;
3541 }
3542 return ret;
3543}
3544
3545static int
3546bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
3547{
3548 static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
3549 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
3550 int i;
3551
3552 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
3553 u32 offset;
3554
3555 for (offset = 0; offset < size; offset += 4) {
3556
3557 REG_WR_IND(bp, start + offset, test_pattern[i]);
3558
3559 if (REG_RD_IND(bp, start + offset) !=
3560 test_pattern[i]) {
3561 return -ENODEV;
3562 }
3563 }
3564 }
3565 return 0;
3566}
3567
3568static int
3569bnx2_test_memory(struct bnx2 *bp)
3570{
3571 int ret = 0;
3572 int i;
3573 static struct {
3574 u32 offset;
3575 u32 len;
3576 } mem_tbl[] = {
3577 { 0x60000, 0x4000 },
3578 { 0xa0000, 0x4000 },
3579 { 0xe0000, 0x4000 },
3580 { 0x120000, 0x4000 },
3581 { 0x1a0000, 0x4000 },
3582 { 0x160000, 0x4000 },
3583 { 0xffffffff, 0 },
3584 };
3585
3586 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
3587 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
3588 mem_tbl[i].len)) != 0) {
3589 return ret;
3590 }
3591 }
3592
3593 return ret;
3594}
3595
3596static int
3597bnx2_test_loopback(struct bnx2 *bp)
3598{
3599 unsigned int pkt_size, num_pkts, i;
3600 struct sk_buff *skb, *rx_skb;
3601 unsigned char *packet;
3602 u16 rx_start_idx, rx_idx, send_idx;
3603 u32 send_bseq, val;
3604 dma_addr_t map;
3605 struct tx_bd *txbd;
3606 struct sw_bd *rx_buf;
3607 struct l2_fhdr *rx_hdr;
3608 int ret = -ENODEV;
3609
3610 if (!netif_running(bp->dev))
3611 return -ENODEV;
3612
3613 bp->loopback = MAC_LOOPBACK;
3614 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_DIAG);
3615 bnx2_set_mac_loopback(bp);
3616
3617 pkt_size = 1514;
3618 skb = dev_alloc_skb(pkt_size);
3619 packet = skb_put(skb, pkt_size);
3620 memcpy(packet, bp->mac_addr, 6);
3621 memset(packet + 6, 0x0, 8);
3622 for (i = 14; i < pkt_size; i++)
3623 packet[i] = (unsigned char) (i & 0xff);
3624
3625 map = pci_map_single(bp->pdev, skb->data, pkt_size,
3626 PCI_DMA_TODEVICE);
3627
3628 val = REG_RD(bp, BNX2_HC_COMMAND);
3629 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3630 REG_RD(bp, BNX2_HC_COMMAND);
3631
3632 udelay(5);
3633 rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
3634
3635 send_idx = 0;
3636 send_bseq = 0;
3637 num_pkts = 0;
3638
3639 txbd = &bp->tx_desc_ring[send_idx];
3640
3641 txbd->tx_bd_haddr_hi = (u64) map >> 32;
3642 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
3643 txbd->tx_bd_mss_nbytes = pkt_size;
3644 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
3645
3646 num_pkts++;
3647 send_idx = NEXT_TX_BD(send_idx);
3648
3649 send_bseq += pkt_size;
3650
3651 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, send_idx);
3652 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, send_bseq);
3653
3654
3655 udelay(100);
3656
3657 val = REG_RD(bp, BNX2_HC_COMMAND);
3658 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3659 REG_RD(bp, BNX2_HC_COMMAND);
3660
3661 udelay(5);
3662
3663 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
3664 dev_kfree_skb_irq(skb);
3665
3666 if (bp->status_blk->status_tx_quick_consumer_index0 != send_idx) {
3667 goto loopback_test_done;
3668 }
3669
3670 rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
3671 if (rx_idx != rx_start_idx + num_pkts) {
3672 goto loopback_test_done;
3673 }
3674
3675 rx_buf = &bp->rx_buf_ring[rx_start_idx];
3676 rx_skb = rx_buf->skb;
3677
3678 rx_hdr = (struct l2_fhdr *) rx_skb->data;
3679 skb_reserve(rx_skb, bp->rx_offset);
3680
3681 pci_dma_sync_single_for_cpu(bp->pdev,
3682 pci_unmap_addr(rx_buf, mapping),
3683 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
3684
3685 if (rx_hdr->l2_fhdr_errors &
3686 (L2_FHDR_ERRORS_BAD_CRC |
3687 L2_FHDR_ERRORS_PHY_DECODE |
3688 L2_FHDR_ERRORS_ALIGNMENT |
3689 L2_FHDR_ERRORS_TOO_SHORT |
3690 L2_FHDR_ERRORS_GIANT_FRAME)) {
3691
3692 goto loopback_test_done;
3693 }
3694
3695 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
3696 goto loopback_test_done;
3697 }
3698
3699 for (i = 14; i < pkt_size; i++) {
3700 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
3701 goto loopback_test_done;
3702 }
3703 }
3704
3705 ret = 0;
3706
3707loopback_test_done:
3708 bp->loopback = 0;
3709 return ret;
3710}
3711
3712#define NVRAM_SIZE 0x200
3713#define CRC32_RESIDUAL 0xdebb20e3
3714
3715static int
3716bnx2_test_nvram(struct bnx2 *bp)
3717{
3718 u32 buf[NVRAM_SIZE / 4];
3719 u8 *data = (u8 *) buf;
3720 int rc = 0;
3721 u32 magic, csum;
3722
3723 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
3724 goto test_nvram_done;
3725
3726 magic = be32_to_cpu(buf[0]);
3727 if (magic != 0x669955aa) {
3728 rc = -ENODEV;
3729 goto test_nvram_done;
3730 }
3731
3732 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
3733 goto test_nvram_done;
3734
3735 csum = ether_crc_le(0x100, data);
3736 if (csum != CRC32_RESIDUAL) {
3737 rc = -ENODEV;
3738 goto test_nvram_done;
3739 }
3740
3741 csum = ether_crc_le(0x100, data + 0x100);
3742 if (csum != CRC32_RESIDUAL) {
3743 rc = -ENODEV;
3744 }
3745
3746test_nvram_done:
3747 return rc;
3748}
3749
3750static int
3751bnx2_test_link(struct bnx2 *bp)
3752{
3753 u32 bmsr;
3754
3755 spin_lock_irq(&bp->phy_lock);
3756 bnx2_read_phy(bp, MII_BMSR, &bmsr);
3757 bnx2_read_phy(bp, MII_BMSR, &bmsr);
3758 spin_unlock_irq(&bp->phy_lock);
3759
3760 if (bmsr & BMSR_LSTATUS) {
3761 return 0;
3762 }
3763 return -ENODEV;
3764}
3765
3766static int
3767bnx2_test_intr(struct bnx2 *bp)
3768{
3769 int i;
3770 u32 val;
3771 u16 status_idx;
3772
3773 if (!netif_running(bp->dev))
3774 return -ENODEV;
3775
3776 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
3777
3778 /* This register is not touched during run-time. */
3779 val = REG_RD(bp, BNX2_HC_COMMAND);
3780 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
3781 REG_RD(bp, BNX2_HC_COMMAND);
3782
3783 for (i = 0; i < 10; i++) {
3784 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
3785 status_idx) {
3786
3787 break;
3788 }
3789
3790 msleep_interruptible(10);
3791 }
3792 if (i < 10)
3793 return 0;
3794
3795 return -ENODEV;
3796}
3797
3798static void
3799bnx2_timer(unsigned long data)
3800{
3801 struct bnx2 *bp = (struct bnx2 *) data;
3802 u32 msg;
3803
3804 if (atomic_read(&bp->intr_sem) != 0)
3805 goto bnx2_restart_timer;
3806
3807 msg = (u32) ++bp->fw_drv_pulse_wr_seq;
3808 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_PULSE_MB, msg);
3809
3810 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
3811 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
3812 unsigned long flags;
3813
3814 spin_lock_irqsave(&bp->phy_lock, flags);
3815 if (bp->serdes_an_pending) {
3816 bp->serdes_an_pending--;
3817 }
3818 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
3819 u32 bmcr;
3820
3821 bnx2_read_phy(bp, MII_BMCR, &bmcr);
3822
3823 if (bmcr & BMCR_ANENABLE) {
3824 u32 phy1, phy2;
3825
3826 bnx2_write_phy(bp, 0x1c, 0x7c00);
3827 bnx2_read_phy(bp, 0x1c, &phy1);
3828
3829 bnx2_write_phy(bp, 0x17, 0x0f01);
3830 bnx2_read_phy(bp, 0x15, &phy2);
3831 bnx2_write_phy(bp, 0x17, 0x0f01);
3832 bnx2_read_phy(bp, 0x15, &phy2);
3833
3834 if ((phy1 & 0x10) && /* SIGNAL DETECT */
3835 !(phy2 & 0x20)) { /* no CONFIG */
3836
3837 bmcr &= ~BMCR_ANENABLE;
3838 bmcr |= BMCR_SPEED1000 |
3839 BMCR_FULLDPLX;
3840 bnx2_write_phy(bp, MII_BMCR, bmcr);
3841 bp->phy_flags |=
3842 PHY_PARALLEL_DETECT_FLAG;
3843 }
3844 }
3845 }
3846 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
3847 (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
3848 u32 phy2;
3849
3850 bnx2_write_phy(bp, 0x17, 0x0f01);
3851 bnx2_read_phy(bp, 0x15, &phy2);
3852 if (phy2 & 0x20) {
3853 u32 bmcr;
3854
3855 bnx2_read_phy(bp, MII_BMCR, &bmcr);
3856 bmcr |= BMCR_ANENABLE;
3857 bnx2_write_phy(bp, MII_BMCR, bmcr);
3858
3859 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
3860
3861 }
3862 }
3863
3864 spin_unlock_irqrestore(&bp->phy_lock, flags);
3865 }
3866
3867bnx2_restart_timer:
3868 bp->timer.expires = RUN_AT(bp->timer_interval);
3869
3870 add_timer(&bp->timer);
3871}
3872
3873/* Called with rtnl_lock */
3874static int
3875bnx2_open(struct net_device *dev)
3876{
3877 struct bnx2 *bp = dev->priv;
3878 int rc;
3879
3880 bnx2_set_power_state(bp, 0);
3881 bnx2_disable_int(bp);
3882
3883 rc = bnx2_alloc_mem(bp);
3884 if (rc)
3885 return rc;
3886
3887 if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
3888 (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
3889 !disable_msi) {
3890
3891 if (pci_enable_msi(bp->pdev) == 0) {
3892 bp->flags |= USING_MSI_FLAG;
3893 rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
3894 dev);
3895 }
3896 else {
3897 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
3898 SA_SHIRQ, dev->name, dev);
3899 }
3900 }
3901 else {
3902 rc = request_irq(bp->pdev->irq, bnx2_interrupt, SA_SHIRQ,
3903 dev->name, dev);
3904 }
3905 if (rc) {
3906 bnx2_free_mem(bp);
3907 return rc;
3908 }
3909
3910 rc = bnx2_init_nic(bp);
3911
3912 if (rc) {
3913 free_irq(bp->pdev->irq, dev);
3914 if (bp->flags & USING_MSI_FLAG) {
3915 pci_disable_msi(bp->pdev);
3916 bp->flags &= ~USING_MSI_FLAG;
3917 }
3918 bnx2_free_skbs(bp);
3919 bnx2_free_mem(bp);
3920 return rc;
3921 }
3922
3923 init_timer(&bp->timer);
3924
3925 bp->timer.expires = RUN_AT(bp->timer_interval);
3926 bp->timer.data = (unsigned long) bp;
3927 bp->timer.function = bnx2_timer;
3928 add_timer(&bp->timer);
3929
3930 atomic_set(&bp->intr_sem, 0);
3931
3932 bnx2_enable_int(bp);
3933
3934 if (bp->flags & USING_MSI_FLAG) {
3935 /* Test MSI to make sure it is working
3936 * If MSI test fails, go back to INTx mode
3937 */
3938 if (bnx2_test_intr(bp) != 0) {
3939 printk(KERN_WARNING PFX "%s: No interrupt was generated"
3940 " using MSI, switching to INTx mode. Please"
3941 " report this failure to the PCI maintainer"
3942 " and include system chipset information.\n",
3943 bp->dev->name);
3944
3945 bnx2_disable_int(bp);
3946 free_irq(bp->pdev->irq, dev);
3947 pci_disable_msi(bp->pdev);
3948 bp->flags &= ~USING_MSI_FLAG;
3949
3950 rc = bnx2_init_nic(bp);
3951
3952 if (!rc) {
3953 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
3954 SA_SHIRQ, dev->name, dev);
3955 }
3956 if (rc) {
3957 bnx2_free_skbs(bp);
3958 bnx2_free_mem(bp);
3959 del_timer_sync(&bp->timer);
3960 return rc;
3961 }
3962 bnx2_enable_int(bp);
3963 }
3964 }
3965 if (bp->flags & USING_MSI_FLAG) {
3966 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
3967 }
3968
3969 netif_start_queue(dev);
3970
3971 return 0;
3972}
3973
3974static void
3975bnx2_reset_task(void *data)
3976{
3977 struct bnx2 *bp = data;
3978
3979 bnx2_netif_stop(bp);
3980
3981 bnx2_init_nic(bp);
3982
3983 atomic_set(&bp->intr_sem, 1);
3984 bnx2_netif_start(bp);
3985}
3986
3987static void
3988bnx2_tx_timeout(struct net_device *dev)
3989{
3990 struct bnx2 *bp = dev->priv;
3991
3992 /* This allows the netif to be shutdown gracefully before resetting */
3993 schedule_work(&bp->reset_task);
3994}
3995
3996#ifdef BCM_VLAN
3997/* Called with rtnl_lock */
3998static void
3999bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4000{
4001 struct bnx2 *bp = dev->priv;
4002
4003 bnx2_netif_stop(bp);
4004
4005 bp->vlgrp = vlgrp;
4006 bnx2_set_rx_mode(dev);
4007
4008 bnx2_netif_start(bp);
4009}
4010
4011/* Called with rtnl_lock */
4012static void
4013bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4014{
4015 struct bnx2 *bp = dev->priv;
4016
4017 bnx2_netif_stop(bp);
4018
4019 if (bp->vlgrp)
4020 bp->vlgrp->vlan_devices[vid] = NULL;
4021 bnx2_set_rx_mode(dev);
4022
4023 bnx2_netif_start(bp);
4024}
4025#endif
4026
4027/* Called with dev->xmit_lock.
4028 * hard_start_xmit is pseudo-lockless - a lock is only required when
4029 * the tx queue is full. This way, we get the benefit of lockless
4030 * operations most of the time without the complexities to handle
4031 * netif_stop_queue/wake_queue race conditions.
4032 */
4033static int
4034bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4035{
4036 struct bnx2 *bp = dev->priv;
4037 dma_addr_t mapping;
4038 struct tx_bd *txbd;
4039 struct sw_bd *tx_buf;
4040 u32 len, vlan_tag_flags, last_frag, mss;
4041 u16 prod, ring_prod;
4042 int i;
4043
4044 if (unlikely(atomic_read(&bp->tx_avail_bd) <
4045 (skb_shinfo(skb)->nr_frags + 1))) {
4046
4047 netif_stop_queue(dev);
4048 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
4049 dev->name);
4050
4051 return NETDEV_TX_BUSY;
4052 }
4053 len = skb_headlen(skb);
4054 prod = bp->tx_prod;
4055 ring_prod = TX_RING_IDX(prod);
4056
4057 vlan_tag_flags = 0;
4058 if (skb->ip_summed == CHECKSUM_HW) {
4059 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4060 }
4061
4062 if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
4063 vlan_tag_flags |=
4064 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
4065 }
4066#ifdef BCM_TSO
4067 if ((mss = skb_shinfo(skb)->tso_size) &&
4068 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
4069 u32 tcp_opt_len, ip_tcp_len;
4070
4071 if (skb_header_cloned(skb) &&
4072 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4073 dev_kfree_skb(skb);
4074 return NETDEV_TX_OK;
4075 }
4076
4077 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4078 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
4079
4080 tcp_opt_len = 0;
4081 if (skb->h.th->doff > 5) {
4082 tcp_opt_len = (skb->h.th->doff - 5) << 2;
4083 }
4084 ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
4085
4086 skb->nh.iph->check = 0;
4087 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
4088 skb->h.th->check =
4089 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4090 skb->nh.iph->daddr,
4091 0, IPPROTO_TCP, 0);
4092
4093 if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
4094 vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
4095 (tcp_opt_len >> 2)) << 8;
4096 }
4097 }
4098 else
4099#endif
4100 {
4101 mss = 0;
4102 }
4103
4104 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4105
4106 tx_buf = &bp->tx_buf_ring[ring_prod];
4107 tx_buf->skb = skb;
4108 pci_unmap_addr_set(tx_buf, mapping, mapping);
4109
4110 txbd = &bp->tx_desc_ring[ring_prod];
4111
4112 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4113 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4114 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4115 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
4116
4117 last_frag = skb_shinfo(skb)->nr_frags;
4118
4119 for (i = 0; i < last_frag; i++) {
4120 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4121
4122 prod = NEXT_TX_BD(prod);
4123 ring_prod = TX_RING_IDX(prod);
4124 txbd = &bp->tx_desc_ring[ring_prod];
4125
4126 len = frag->size;
4127 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
4128 len, PCI_DMA_TODEVICE);
4129 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
4130 mapping, mapping);
4131
4132 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4133 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4134 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4135 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
4136
4137 }
4138 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
4139
4140 prod = NEXT_TX_BD(prod);
4141 bp->tx_prod_bseq += skb->len;
4142
4143 atomic_sub(last_frag + 1, &bp->tx_avail_bd);
4144
4145 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
4146 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
4147
4148 mmiowb();
4149
4150 bp->tx_prod = prod;
4151 dev->trans_start = jiffies;
4152
4153 if (unlikely(atomic_read(&bp->tx_avail_bd) <= MAX_SKB_FRAGS)) {
4154 unsigned long flags;
4155
4156 spin_lock_irqsave(&bp->tx_lock, flags);
4157 if (atomic_read(&bp->tx_avail_bd) <= MAX_SKB_FRAGS) {
4158 netif_stop_queue(dev);
4159
4160 if (atomic_read(&bp->tx_avail_bd) > MAX_SKB_FRAGS)
4161 netif_wake_queue(dev);
4162 }
4163 spin_unlock_irqrestore(&bp->tx_lock, flags);
4164 }
4165
4166 return NETDEV_TX_OK;
4167}
4168
4169/* Called with rtnl_lock */
4170static int
4171bnx2_close(struct net_device *dev)
4172{
4173 struct bnx2 *bp = dev->priv;
4174 u32 reset_code;
4175
4176 flush_scheduled_work();
4177 bnx2_netif_stop(bp);
4178 del_timer_sync(&bp->timer);
4179 if (bp->wol)
4180 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4181 else
4182 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4183 bnx2_reset_chip(bp, reset_code);
4184 free_irq(bp->pdev->irq, dev);
4185 if (bp->flags & USING_MSI_FLAG) {
4186 pci_disable_msi(bp->pdev);
4187 bp->flags &= ~USING_MSI_FLAG;
4188 }
4189 bnx2_free_skbs(bp);
4190 bnx2_free_mem(bp);
4191 bp->link_up = 0;
4192 netif_carrier_off(bp->dev);
4193 bnx2_set_power_state(bp, 3);
4194 return 0;
4195}
4196
4197#define GET_NET_STATS64(ctr) \
4198 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
4199 (unsigned long) (ctr##_lo)
4200
4201#define GET_NET_STATS32(ctr) \
4202 (ctr##_lo)
4203
4204#if (BITS_PER_LONG == 64)
4205#define GET_NET_STATS GET_NET_STATS64
4206#else
4207#define GET_NET_STATS GET_NET_STATS32
4208#endif
4209
4210static struct net_device_stats *
4211bnx2_get_stats(struct net_device *dev)
4212{
4213 struct bnx2 *bp = dev->priv;
4214 struct statistics_block *stats_blk = bp->stats_blk;
4215 struct net_device_stats *net_stats = &bp->net_stats;
4216
4217 if (bp->stats_blk == NULL) {
4218 return net_stats;
4219 }
4220 net_stats->rx_packets =
4221 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
4222 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
4223 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
4224
4225 net_stats->tx_packets =
4226 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
4227 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
4228 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
4229
4230 net_stats->rx_bytes =
4231 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
4232
4233 net_stats->tx_bytes =
4234 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
4235
4236 net_stats->multicast =
4237 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
4238
4239 net_stats->collisions =
4240 (unsigned long) stats_blk->stat_EtherStatsCollisions;
4241
4242 net_stats->rx_length_errors =
4243 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
4244 stats_blk->stat_EtherStatsOverrsizePkts);
4245
4246 net_stats->rx_over_errors =
4247 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
4248
4249 net_stats->rx_frame_errors =
4250 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
4251
4252 net_stats->rx_crc_errors =
4253 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
4254
4255 net_stats->rx_errors = net_stats->rx_length_errors +
4256 net_stats->rx_over_errors + net_stats->rx_frame_errors +
4257 net_stats->rx_crc_errors;
4258
4259 net_stats->tx_aborted_errors =
4260 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
4261 stats_blk->stat_Dot3StatsLateCollisions);
4262
4263 if (CHIP_NUM(bp) == CHIP_NUM_5706)
4264 net_stats->tx_carrier_errors = 0;
4265 else {
4266 net_stats->tx_carrier_errors =
4267 (unsigned long)
4268 stats_blk->stat_Dot3StatsCarrierSenseErrors;
4269 }
4270
4271 net_stats->tx_errors =
4272 (unsigned long)
4273 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
4274 +
4275 net_stats->tx_aborted_errors +
4276 net_stats->tx_carrier_errors;
4277
4278 return net_stats;
4279}
4280
4281/* All ethtool functions called with rtnl_lock */
4282
4283static int
4284bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4285{
4286 struct bnx2 *bp = dev->priv;
4287
4288 cmd->supported = SUPPORTED_Autoneg;
4289 if (bp->phy_flags & PHY_SERDES_FLAG) {
4290 cmd->supported |= SUPPORTED_1000baseT_Full |
4291 SUPPORTED_FIBRE;
4292
4293 cmd->port = PORT_FIBRE;
4294 }
4295 else {
4296 cmd->supported |= SUPPORTED_10baseT_Half |
4297 SUPPORTED_10baseT_Full |
4298 SUPPORTED_100baseT_Half |
4299 SUPPORTED_100baseT_Full |
4300 SUPPORTED_1000baseT_Full |
4301 SUPPORTED_TP;
4302
4303 cmd->port = PORT_TP;
4304 }
4305
4306 cmd->advertising = bp->advertising;
4307
4308 if (bp->autoneg & AUTONEG_SPEED) {
4309 cmd->autoneg = AUTONEG_ENABLE;
4310 }
4311 else {
4312 cmd->autoneg = AUTONEG_DISABLE;
4313 }
4314
4315 if (netif_carrier_ok(dev)) {
4316 cmd->speed = bp->line_speed;
4317 cmd->duplex = bp->duplex;
4318 }
4319 else {
4320 cmd->speed = -1;
4321 cmd->duplex = -1;
4322 }
4323
4324 cmd->transceiver = XCVR_INTERNAL;
4325 cmd->phy_address = bp->phy_addr;
4326
4327 return 0;
4328}
4329
4330static int
4331bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4332{
4333 struct bnx2 *bp = dev->priv;
4334 u8 autoneg = bp->autoneg;
4335 u8 req_duplex = bp->req_duplex;
4336 u16 req_line_speed = bp->req_line_speed;
4337 u32 advertising = bp->advertising;
4338
4339 if (cmd->autoneg == AUTONEG_ENABLE) {
4340 autoneg |= AUTONEG_SPEED;
4341
4342 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
4343
4344 /* allow advertising 1 speed */
4345 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
4346 (cmd->advertising == ADVERTISED_10baseT_Full) ||
4347 (cmd->advertising == ADVERTISED_100baseT_Half) ||
4348 (cmd->advertising == ADVERTISED_100baseT_Full)) {
4349
4350 if (bp->phy_flags & PHY_SERDES_FLAG)
4351 return -EINVAL;
4352
4353 advertising = cmd->advertising;
4354
4355 }
4356 else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
4357 advertising = cmd->advertising;
4358 }
4359 else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
4360 return -EINVAL;
4361 }
4362 else {
4363 if (bp->phy_flags & PHY_SERDES_FLAG) {
4364 advertising = ETHTOOL_ALL_FIBRE_SPEED;
4365 }
4366 else {
4367 advertising = ETHTOOL_ALL_COPPER_SPEED;
4368 }
4369 }
4370 advertising |= ADVERTISED_Autoneg;
4371 }
4372 else {
4373 if (bp->phy_flags & PHY_SERDES_FLAG) {
4374 if ((cmd->speed != SPEED_1000) ||
4375 (cmd->duplex != DUPLEX_FULL)) {
4376 return -EINVAL;
4377 }
4378 }
4379 else if (cmd->speed == SPEED_1000) {
4380 return -EINVAL;
4381 }
4382 autoneg &= ~AUTONEG_SPEED;
4383 req_line_speed = cmd->speed;
4384 req_duplex = cmd->duplex;
4385 advertising = 0;
4386 }
4387
4388 bp->autoneg = autoneg;
4389 bp->advertising = advertising;
4390 bp->req_line_speed = req_line_speed;
4391 bp->req_duplex = req_duplex;
4392
4393 spin_lock_irq(&bp->phy_lock);
4394
4395 bnx2_setup_phy(bp);
4396
4397 spin_unlock_irq(&bp->phy_lock);
4398
4399 return 0;
4400}
4401
4402static void
4403bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4404{
4405 struct bnx2 *bp = dev->priv;
4406
4407 strcpy(info->driver, DRV_MODULE_NAME);
4408 strcpy(info->version, DRV_MODULE_VERSION);
4409 strcpy(info->bus_info, pci_name(bp->pdev));
4410 info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
4411 info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
4412 info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
4413 info->fw_version[6] = (bp->fw_ver & 0xff) + '0';
4414 info->fw_version[1] = info->fw_version[3] = info->fw_version[5] = '.';
4415 info->fw_version[7] = 0;
4416}
4417
4418static void
4419bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4420{
4421 struct bnx2 *bp = dev->priv;
4422
4423 if (bp->flags & NO_WOL_FLAG) {
4424 wol->supported = 0;
4425 wol->wolopts = 0;
4426 }
4427 else {
4428 wol->supported = WAKE_MAGIC;
4429 if (bp->wol)
4430 wol->wolopts = WAKE_MAGIC;
4431 else
4432 wol->wolopts = 0;
4433 }
4434 memset(&wol->sopass, 0, sizeof(wol->sopass));
4435}
4436
4437static int
4438bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4439{
4440 struct bnx2 *bp = dev->priv;
4441
4442 if (wol->wolopts & ~WAKE_MAGIC)
4443 return -EINVAL;
4444
4445 if (wol->wolopts & WAKE_MAGIC) {
4446 if (bp->flags & NO_WOL_FLAG)
4447 return -EINVAL;
4448
4449 bp->wol = 1;
4450 }
4451 else {
4452 bp->wol = 0;
4453 }
4454 return 0;
4455}
4456
4457static int
4458bnx2_nway_reset(struct net_device *dev)
4459{
4460 struct bnx2 *bp = dev->priv;
4461 u32 bmcr;
4462
4463 if (!(bp->autoneg & AUTONEG_SPEED)) {
4464 return -EINVAL;
4465 }
4466
4467 spin_lock_irq(&bp->phy_lock);
4468
4469 /* Force a link down visible on the other side */
4470 if (bp->phy_flags & PHY_SERDES_FLAG) {
4471 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
4472 spin_unlock_irq(&bp->phy_lock);
4473
4474 msleep(20);
4475
4476 spin_lock_irq(&bp->phy_lock);
4477 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
4478 bp->serdes_an_pending = SERDES_AN_TIMEOUT /
4479 bp->timer_interval;
4480 }
4481 }
4482
4483 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4484 bmcr &= ~BMCR_LOOPBACK;
4485 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
4486
4487 spin_unlock_irq(&bp->phy_lock);
4488
4489 return 0;
4490}
4491
4492static int
4493bnx2_get_eeprom_len(struct net_device *dev)
4494{
4495 struct bnx2 *bp = dev->priv;
4496
4497 if (bp->flash_info == 0)
4498 return 0;
4499
4500 return (int) bp->flash_info->total_size;
4501}
4502
4503static int
4504bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4505 u8 *eebuf)
4506{
4507 struct bnx2 *bp = dev->priv;
4508 int rc;
4509
4510 if (eeprom->offset > bp->flash_info->total_size)
4511 return -EINVAL;
4512
4513 if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
4514 eeprom->len = bp->flash_info->total_size - eeprom->offset;
4515
4516 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
4517
4518 return rc;
4519}
4520
4521static int
4522bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4523 u8 *eebuf)
4524{
4525 struct bnx2 *bp = dev->priv;
4526 int rc;
4527
4528 if (eeprom->offset > bp->flash_info->total_size)
4529 return -EINVAL;
4530
4531 if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
4532 eeprom->len = bp->flash_info->total_size - eeprom->offset;
4533
4534 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
4535
4536 return rc;
4537}
4538
4539static int
4540bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4541{
4542 struct bnx2 *bp = dev->priv;
4543
4544 memset(coal, 0, sizeof(struct ethtool_coalesce));
4545
4546 coal->rx_coalesce_usecs = bp->rx_ticks;
4547 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
4548 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
4549 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
4550
4551 coal->tx_coalesce_usecs = bp->tx_ticks;
4552 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
4553 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
4554 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
4555
4556 coal->stats_block_coalesce_usecs = bp->stats_ticks;
4557
4558 return 0;
4559}
4560
4561static int
4562bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4563{
4564 struct bnx2 *bp = dev->priv;
4565
4566 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
4567 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
4568
4569 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
4570 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
4571
4572 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
4573 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
4574
4575 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
4576 if (bp->rx_quick_cons_trip_int > 0xff)
4577 bp->rx_quick_cons_trip_int = 0xff;
4578
4579 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
4580 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
4581
4582 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
4583 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
4584
4585 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
4586 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
4587
4588 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
4589 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
4590 0xff;
4591
4592 bp->stats_ticks = coal->stats_block_coalesce_usecs;
4593 if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
4594 bp->stats_ticks &= 0xffff00;
4595
4596 if (netif_running(bp->dev)) {
4597 bnx2_netif_stop(bp);
4598 bnx2_init_nic(bp);
4599 bnx2_netif_start(bp);
4600 }
4601
4602 return 0;
4603}
4604
4605static void
4606bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4607{
4608 struct bnx2 *bp = dev->priv;
4609
4610 ering->rx_max_pending = MAX_RX_DESC_CNT;
4611 ering->rx_mini_max_pending = 0;
4612 ering->rx_jumbo_max_pending = 0;
4613
4614 ering->rx_pending = bp->rx_ring_size;
4615 ering->rx_mini_pending = 0;
4616 ering->rx_jumbo_pending = 0;
4617
4618 ering->tx_max_pending = MAX_TX_DESC_CNT;
4619 ering->tx_pending = bp->tx_ring_size;
4620}
4621
4622static int
4623bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4624{
4625 struct bnx2 *bp = dev->priv;
4626
4627 if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
4628 (ering->tx_pending > MAX_TX_DESC_CNT) ||
4629 (ering->tx_pending <= MAX_SKB_FRAGS)) {
4630
4631 return -EINVAL;
4632 }
4633 bp->rx_ring_size = ering->rx_pending;
4634 bp->tx_ring_size = ering->tx_pending;
4635
4636 if (netif_running(bp->dev)) {
4637 bnx2_netif_stop(bp);
4638 bnx2_init_nic(bp);
4639 bnx2_netif_start(bp);
4640 }
4641
4642 return 0;
4643}
4644
4645static void
4646bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4647{
4648 struct bnx2 *bp = dev->priv;
4649
4650 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
4651 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
4652 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
4653}
4654
4655static int
4656bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4657{
4658 struct bnx2 *bp = dev->priv;
4659
4660 bp->req_flow_ctrl = 0;
4661 if (epause->rx_pause)
4662 bp->req_flow_ctrl |= FLOW_CTRL_RX;
4663 if (epause->tx_pause)
4664 bp->req_flow_ctrl |= FLOW_CTRL_TX;
4665
4666 if (epause->autoneg) {
4667 bp->autoneg |= AUTONEG_FLOW_CTRL;
4668 }
4669 else {
4670 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
4671 }
4672
4673 spin_lock_irq(&bp->phy_lock);
4674
4675 bnx2_setup_phy(bp);
4676
4677 spin_unlock_irq(&bp->phy_lock);
4678
4679 return 0;
4680}
4681
4682static u32
4683bnx2_get_rx_csum(struct net_device *dev)
4684{
4685 struct bnx2 *bp = dev->priv;
4686
4687 return bp->rx_csum;
4688}
4689
4690static int
4691bnx2_set_rx_csum(struct net_device *dev, u32 data)
4692{
4693 struct bnx2 *bp = dev->priv;
4694
4695 bp->rx_csum = data;
4696 return 0;
4697}
4698
4699#define BNX2_NUM_STATS 45
4700
4701struct {
4702 char string[ETH_GSTRING_LEN];
4703} bnx2_stats_str_arr[BNX2_NUM_STATS] = {
4704 { "rx_bytes" },
4705 { "rx_error_bytes" },
4706 { "tx_bytes" },
4707 { "tx_error_bytes" },
4708 { "rx_ucast_packets" },
4709 { "rx_mcast_packets" },
4710 { "rx_bcast_packets" },
4711 { "tx_ucast_packets" },
4712 { "tx_mcast_packets" },
4713 { "tx_bcast_packets" },
4714 { "tx_mac_errors" },
4715 { "tx_carrier_errors" },
4716 { "rx_crc_errors" },
4717 { "rx_align_errors" },
4718 { "tx_single_collisions" },
4719 { "tx_multi_collisions" },
4720 { "tx_deferred" },
4721 { "tx_excess_collisions" },
4722 { "tx_late_collisions" },
4723 { "tx_total_collisions" },
4724 { "rx_fragments" },
4725 { "rx_jabbers" },
4726 { "rx_undersize_packets" },
4727 { "rx_oversize_packets" },
4728 { "rx_64_byte_packets" },
4729 { "rx_65_to_127_byte_packets" },
4730 { "rx_128_to_255_byte_packets" },
4731 { "rx_256_to_511_byte_packets" },
4732 { "rx_512_to_1023_byte_packets" },
4733 { "rx_1024_to_1522_byte_packets" },
4734 { "rx_1523_to_9022_byte_packets" },
4735 { "tx_64_byte_packets" },
4736 { "tx_65_to_127_byte_packets" },
4737 { "tx_128_to_255_byte_packets" },
4738 { "tx_256_to_511_byte_packets" },
4739 { "tx_512_to_1023_byte_packets" },
4740 { "tx_1024_to_1522_byte_packets" },
4741 { "tx_1523_to_9022_byte_packets" },
4742 { "rx_xon_frames" },
4743 { "rx_xoff_frames" },
4744 { "tx_xon_frames" },
4745 { "tx_xoff_frames" },
4746 { "rx_mac_ctrl_frames" },
4747 { "rx_filtered_packets" },
4748 { "rx_discards" },
4749};
4750
4751#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
4752
4753unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
4754 STATS_OFFSET32(stat_IfHCInOctets_hi),
4755 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
4756 STATS_OFFSET32(stat_IfHCOutOctets_hi),
4757 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
4758 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
4759 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
4760 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
4761 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
4762 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
4763 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
4764 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
4765 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
4766 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
4767 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
4768 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
4769 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
4770 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
4771 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
4772 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
4773 STATS_OFFSET32(stat_EtherStatsCollisions),
4774 STATS_OFFSET32(stat_EtherStatsFragments),
4775 STATS_OFFSET32(stat_EtherStatsJabbers),
4776 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
4777 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
4778 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
4779 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
4780 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
4781 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
4782 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
4783 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
4784 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
4785 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
4786 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
4787 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
4788 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
4789 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
4790 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
4791 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
4792 STATS_OFFSET32(stat_XonPauseFramesReceived),
4793 STATS_OFFSET32(stat_XoffPauseFramesReceived),
4794 STATS_OFFSET32(stat_OutXonSent),
4795 STATS_OFFSET32(stat_OutXoffSent),
4796 STATS_OFFSET32(stat_MacControlFramesReceived),
4797 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
4798 STATS_OFFSET32(stat_IfInMBUFDiscards),
4799};
4800
4801/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
4802 * skipped because of errata.
4803 */
4804u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
4805 8,0,8,8,8,8,8,8,8,8,
4806 4,0,4,4,4,4,4,4,4,4,
4807 4,4,4,4,4,4,4,4,4,4,
4808 4,4,4,4,4,4,4,4,4,4,
4809 4,4,4,4,4,
4810};
4811
4812#define BNX2_NUM_TESTS 6
4813
4814struct {
4815 char string[ETH_GSTRING_LEN];
4816} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
4817 { "register_test (offline)" },
4818 { "memory_test (offline)" },
4819 { "loopback_test (offline)" },
4820 { "nvram_test (online)" },
4821 { "interrupt_test (online)" },
4822 { "link_test (online)" },
4823};
4824
4825static int
4826bnx2_self_test_count(struct net_device *dev)
4827{
4828 return BNX2_NUM_TESTS;
4829}
4830
4831static void
4832bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
4833{
4834 struct bnx2 *bp = dev->priv;
4835
4836 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
4837 if (etest->flags & ETH_TEST_FL_OFFLINE) {
4838 bnx2_netif_stop(bp);
4839 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
4840 bnx2_free_skbs(bp);
4841
4842 if (bnx2_test_registers(bp) != 0) {
4843 buf[0] = 1;
4844 etest->flags |= ETH_TEST_FL_FAILED;
4845 }
4846 if (bnx2_test_memory(bp) != 0) {
4847 buf[1] = 1;
4848 etest->flags |= ETH_TEST_FL_FAILED;
4849 }
4850 if (bnx2_test_loopback(bp) != 0) {
4851 buf[2] = 1;
4852 etest->flags |= ETH_TEST_FL_FAILED;
4853 }
4854
4855 if (!netif_running(bp->dev)) {
4856 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
4857 }
4858 else {
4859 bnx2_init_nic(bp);
4860 bnx2_netif_start(bp);
4861 }
4862
4863 /* wait for link up */
4864 msleep_interruptible(3000);
4865 if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
4866 msleep_interruptible(4000);
4867 }
4868
4869 if (bnx2_test_nvram(bp) != 0) {
4870 buf[3] = 1;
4871 etest->flags |= ETH_TEST_FL_FAILED;
4872 }
4873 if (bnx2_test_intr(bp) != 0) {
4874 buf[4] = 1;
4875 etest->flags |= ETH_TEST_FL_FAILED;
4876 }
4877
4878 if (bnx2_test_link(bp) != 0) {
4879 buf[5] = 1;
4880 etest->flags |= ETH_TEST_FL_FAILED;
4881
4882 }
4883}
4884
4885static void
4886bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
4887{
4888 switch (stringset) {
4889 case ETH_SS_STATS:
4890 memcpy(buf, bnx2_stats_str_arr,
4891 sizeof(bnx2_stats_str_arr));
4892 break;
4893 case ETH_SS_TEST:
4894 memcpy(buf, bnx2_tests_str_arr,
4895 sizeof(bnx2_tests_str_arr));
4896 break;
4897 }
4898}
4899
4900static int
4901bnx2_get_stats_count(struct net_device *dev)
4902{
4903 return BNX2_NUM_STATS;
4904}
4905
4906static void
4907bnx2_get_ethtool_stats(struct net_device *dev,
4908 struct ethtool_stats *stats, u64 *buf)
4909{
4910 struct bnx2 *bp = dev->priv;
4911 int i;
4912 u32 *hw_stats = (u32 *) bp->stats_blk;
4913 u8 *stats_len_arr = 0;
4914
4915 if (hw_stats == NULL) {
4916 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
4917 return;
4918 }
4919
4920 if (CHIP_NUM(bp) == CHIP_NUM_5706)
4921 stats_len_arr = bnx2_5706_stats_len_arr;
4922
4923 for (i = 0; i < BNX2_NUM_STATS; i++) {
4924 if (stats_len_arr[i] == 0) {
4925 /* skip this counter */
4926 buf[i] = 0;
4927 continue;
4928 }
4929 if (stats_len_arr[i] == 4) {
4930 /* 4-byte counter */
4931 buf[i] = (u64)
4932 *(hw_stats + bnx2_stats_offset_arr[i]);
4933 continue;
4934 }
4935 /* 8-byte counter */
4936 buf[i] = (((u64) *(hw_stats +
4937 bnx2_stats_offset_arr[i])) << 32) +
4938 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
4939 }
4940}
4941
4942static int
4943bnx2_phys_id(struct net_device *dev, u32 data)
4944{
4945 struct bnx2 *bp = dev->priv;
4946 int i;
4947 u32 save;
4948
4949 if (data == 0)
4950 data = 2;
4951
4952 save = REG_RD(bp, BNX2_MISC_CFG);
4953 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
4954
4955 for (i = 0; i < (data * 2); i++) {
4956 if ((i % 2) == 0) {
4957 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
4958 }
4959 else {
4960 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
4961 BNX2_EMAC_LED_1000MB_OVERRIDE |
4962 BNX2_EMAC_LED_100MB_OVERRIDE |
4963 BNX2_EMAC_LED_10MB_OVERRIDE |
4964 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
4965 BNX2_EMAC_LED_TRAFFIC);
4966 }
4967 msleep_interruptible(500);
4968 if (signal_pending(current))
4969 break;
4970 }
4971 REG_WR(bp, BNX2_EMAC_LED, 0);
4972 REG_WR(bp, BNX2_MISC_CFG, save);
4973 return 0;
4974}
4975
4976static struct ethtool_ops bnx2_ethtool_ops = {
4977 .get_settings = bnx2_get_settings,
4978 .set_settings = bnx2_set_settings,
4979 .get_drvinfo = bnx2_get_drvinfo,
4980 .get_wol = bnx2_get_wol,
4981 .set_wol = bnx2_set_wol,
4982 .nway_reset = bnx2_nway_reset,
4983 .get_link = ethtool_op_get_link,
4984 .get_eeprom_len = bnx2_get_eeprom_len,
4985 .get_eeprom = bnx2_get_eeprom,
4986 .set_eeprom = bnx2_set_eeprom,
4987 .get_coalesce = bnx2_get_coalesce,
4988 .set_coalesce = bnx2_set_coalesce,
4989 .get_ringparam = bnx2_get_ringparam,
4990 .set_ringparam = bnx2_set_ringparam,
4991 .get_pauseparam = bnx2_get_pauseparam,
4992 .set_pauseparam = bnx2_set_pauseparam,
4993 .get_rx_csum = bnx2_get_rx_csum,
4994 .set_rx_csum = bnx2_set_rx_csum,
4995 .get_tx_csum = ethtool_op_get_tx_csum,
4996 .set_tx_csum = ethtool_op_set_tx_csum,
4997 .get_sg = ethtool_op_get_sg,
4998 .set_sg = ethtool_op_set_sg,
4999#ifdef BCM_TSO
5000 .get_tso = ethtool_op_get_tso,
5001 .set_tso = ethtool_op_set_tso,
5002#endif
5003 .self_test_count = bnx2_self_test_count,
5004 .self_test = bnx2_self_test,
5005 .get_strings = bnx2_get_strings,
5006 .phys_id = bnx2_phys_id,
5007 .get_stats_count = bnx2_get_stats_count,
5008 .get_ethtool_stats = bnx2_get_ethtool_stats,
5009};
5010
5011/* Called with rtnl_lock */
5012static int
5013bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5014{
5015 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&ifr->ifr_data;
5016 struct bnx2 *bp = dev->priv;
5017 int err;
5018
5019 switch(cmd) {
5020 case SIOCGMIIPHY:
5021 data->phy_id = bp->phy_addr;
5022
5023 /* fallthru */
5024 case SIOCGMIIREG: {
5025 u32 mii_regval;
5026
5027 spin_lock_irq(&bp->phy_lock);
5028 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
5029 spin_unlock_irq(&bp->phy_lock);
5030
5031 data->val_out = mii_regval;
5032
5033 return err;
5034 }
5035
5036 case SIOCSMIIREG:
5037 if (!capable(CAP_NET_ADMIN))
5038 return -EPERM;
5039
5040 spin_lock_irq(&bp->phy_lock);
5041 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
5042 spin_unlock_irq(&bp->phy_lock);
5043
5044 return err;
5045
5046 default:
5047 /* do nothing */
5048 break;
5049 }
5050 return -EOPNOTSUPP;
5051}
5052
5053/* Called with rtnl_lock */
5054static int
5055bnx2_change_mac_addr(struct net_device *dev, void *p)
5056{
5057 struct sockaddr *addr = p;
5058 struct bnx2 *bp = dev->priv;
5059
5060 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5061 if (netif_running(dev))
5062 bnx2_set_mac_addr(bp);
5063
5064 return 0;
5065}
5066
5067/* Called with rtnl_lock */
5068static int
5069bnx2_change_mtu(struct net_device *dev, int new_mtu)
5070{
5071 struct bnx2 *bp = dev->priv;
5072
5073 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
5074 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
5075 return -EINVAL;
5076
5077 dev->mtu = new_mtu;
5078 if (netif_running(dev)) {
5079 bnx2_netif_stop(bp);
5080
5081 bnx2_init_nic(bp);
5082
5083 bnx2_netif_start(bp);
5084 }
5085 return 0;
5086}
5087
5088#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5089static void
5090poll_bnx2(struct net_device *dev)
5091{
5092 struct bnx2 *bp = dev->priv;
5093
5094 disable_irq(bp->pdev->irq);
5095 bnx2_interrupt(bp->pdev->irq, dev, NULL);
5096 enable_irq(bp->pdev->irq);
5097}
5098#endif
5099
5100static int __devinit
5101bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5102{
5103 struct bnx2 *bp;
5104 unsigned long mem_len;
5105 int rc;
5106 u32 reg;
5107
5108 SET_MODULE_OWNER(dev);
5109 SET_NETDEV_DEV(dev, &pdev->dev);
5110 bp = dev->priv;
5111
5112 bp->flags = 0;
5113 bp->phy_flags = 0;
5114
5115 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5116 rc = pci_enable_device(pdev);
5117 if (rc) {
5118 printk(KERN_ERR PFX "Cannot enable PCI device, aborting.");
5119 goto err_out;
5120 }
5121
5122 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5123 printk(KERN_ERR PFX "Cannot find PCI device base address, "
5124 "aborting.\n");
5125 rc = -ENODEV;
5126 goto err_out_disable;
5127 }
5128
5129 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5130 if (rc) {
5131 printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n");
5132 goto err_out_disable;
5133 }
5134
5135 pci_set_master(pdev);
5136
5137 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
5138 if (bp->pm_cap == 0) {
5139 printk(KERN_ERR PFX "Cannot find power management capability, "
5140 "aborting.\n");
5141 rc = -EIO;
5142 goto err_out_release;
5143 }
5144
5145 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5146 if (bp->pcix_cap == 0) {
5147 printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n");
5148 rc = -EIO;
5149 goto err_out_release;
5150 }
5151
5152 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5153 bp->flags |= USING_DAC_FLAG;
5154 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
5155 printk(KERN_ERR PFX "pci_set_consistent_dma_mask "
5156 "failed, aborting.\n");
5157 rc = -EIO;
5158 goto err_out_release;
5159 }
5160 }
5161 else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
5162 printk(KERN_ERR PFX "System does not support DMA, aborting.\n");
5163 rc = -EIO;
5164 goto err_out_release;
5165 }
5166
5167 bp->dev = dev;
5168 bp->pdev = pdev;
5169
5170 spin_lock_init(&bp->phy_lock);
5171 spin_lock_init(&bp->tx_lock);
5172 INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
5173
5174 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
5175 mem_len = MB_GET_CID_ADDR(17);
5176 dev->mem_end = dev->mem_start + mem_len;
5177 dev->irq = pdev->irq;
5178
5179 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
5180
5181 if (!bp->regview) {
5182 printk(KERN_ERR PFX "Cannot map register space, aborting.\n");
5183 rc = -ENOMEM;
5184 goto err_out_release;
5185 }
5186
5187 /* Configure byte swap and enable write to the reg_window registers.
5188 * Rely on CPU to do target byte swapping on big endian systems
5189 * The chip's target access swapping will not swap all accesses
5190 */
5191 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
5192 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5193 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
5194
5195 bnx2_set_power_state(bp, 0);
5196
5197 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5198
5199 bp->phy_addr = 1;
5200
5201 /* Get bus information. */
5202 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5203 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
5204 u32 clkreg;
5205
5206 bp->flags |= PCIX_FLAG;
5207
5208 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
5209
5210 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
5211 switch (clkreg) {
5212 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
5213 bp->bus_speed_mhz = 133;
5214 break;
5215
5216 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
5217 bp->bus_speed_mhz = 100;
5218 break;
5219
5220 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
5221 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
5222 bp->bus_speed_mhz = 66;
5223 break;
5224
5225 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
5226 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
5227 bp->bus_speed_mhz = 50;
5228 break;
5229
5230 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
5231 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
5232 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
5233 bp->bus_speed_mhz = 33;
5234 break;
5235 }
5236 }
5237 else {
5238 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
5239 bp->bus_speed_mhz = 66;
5240 else
5241 bp->bus_speed_mhz = 33;
5242 }
5243
5244 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
5245 bp->flags |= PCI_32BIT_FLAG;
5246
5247 /* 5706A0 may falsely detect SERR and PERR. */
5248 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5249 reg = REG_RD(bp, PCI_COMMAND);
5250 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
5251 REG_WR(bp, PCI_COMMAND, reg);
5252 }
5253 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
5254 !(bp->flags & PCIX_FLAG)) {
5255
5256 printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, "
5257 "aborting.\n");
5258 goto err_out_unmap;
5259 }
5260
5261 bnx2_init_nvram(bp);
5262
5263 /* Get the permanent MAC address. First we need to make sure the
5264 * firmware is actually running.
5265 */
5266 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DEV_INFO_SIGNATURE);
5267
5268 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5269 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
5270 printk(KERN_ERR PFX "Firmware not running, aborting.\n");
5271 rc = -ENODEV;
5272 goto err_out_unmap;
5273 }
5274
5275 bp->fw_ver = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
5276 BNX2_DEV_INFO_BC_REV);
5277
5278 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_UPPER);
5279 bp->mac_addr[0] = (u8) (reg >> 8);
5280 bp->mac_addr[1] = (u8) reg;
5281
5282 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_LOWER);
5283 bp->mac_addr[2] = (u8) (reg >> 24);
5284 bp->mac_addr[3] = (u8) (reg >> 16);
5285 bp->mac_addr[4] = (u8) (reg >> 8);
5286 bp->mac_addr[5] = (u8) reg;
5287
5288 bp->tx_ring_size = MAX_TX_DESC_CNT;
5289 bp->rx_ring_size = 100;
5290
5291 bp->rx_csum = 1;
5292
5293 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
5294
5295 bp->tx_quick_cons_trip_int = 20;
5296 bp->tx_quick_cons_trip = 20;
5297 bp->tx_ticks_int = 80;
5298 bp->tx_ticks = 80;
5299
5300 bp->rx_quick_cons_trip_int = 6;
5301 bp->rx_quick_cons_trip = 6;
5302 bp->rx_ticks_int = 18;
5303 bp->rx_ticks = 18;
5304
5305 bp->stats_ticks = 1000000 & 0xffff00;
5306
5307 bp->timer_interval = HZ;
5308
5309 /* Disable WOL support if we are running on a SERDES chip. */
5310 if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
5311 bp->phy_flags |= PHY_SERDES_FLAG;
5312 bp->flags |= NO_WOL_FLAG;
5313 }
5314
5315 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5316 bp->tx_quick_cons_trip_int =
5317 bp->tx_quick_cons_trip;
5318 bp->tx_ticks_int = bp->tx_ticks;
5319 bp->rx_quick_cons_trip_int =
5320 bp->rx_quick_cons_trip;
5321 bp->rx_ticks_int = bp->rx_ticks;
5322 bp->comp_prod_trip_int = bp->comp_prod_trip;
5323 bp->com_ticks_int = bp->com_ticks;
5324 bp->cmd_ticks_int = bp->cmd_ticks;
5325 }
5326
5327 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
5328 bp->req_line_speed = 0;
5329 if (bp->phy_flags & PHY_SERDES_FLAG) {
5330 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
5331 }
5332 else {
5333 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
5334 }
5335
5336 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
5337
5338 return 0;
5339
5340err_out_unmap:
5341 if (bp->regview) {
5342 iounmap(bp->regview);
5343 }
5344
5345err_out_release:
5346 pci_release_regions(pdev);
5347
5348err_out_disable:
5349 pci_disable_device(pdev);
5350 pci_set_drvdata(pdev, NULL);
5351
5352err_out:
5353 return rc;
5354}
5355
5356static int __devinit
5357bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5358{
5359 static int version_printed = 0;
5360 struct net_device *dev = NULL;
5361 struct bnx2 *bp;
5362 int rc, i;
5363
5364 if (version_printed++ == 0)
5365 printk(KERN_INFO "%s", version);
5366
5367 /* dev zeroed in init_etherdev */
5368 dev = alloc_etherdev(sizeof(*bp));
5369
5370 if (!dev)
5371 return -ENOMEM;
5372
5373 rc = bnx2_init_board(pdev, dev);
5374 if (rc < 0) {
5375 free_netdev(dev);
5376 return rc;
5377 }
5378
5379 dev->open = bnx2_open;
5380 dev->hard_start_xmit = bnx2_start_xmit;
5381 dev->stop = bnx2_close;
5382 dev->get_stats = bnx2_get_stats;
5383 dev->set_multicast_list = bnx2_set_rx_mode;
5384 dev->do_ioctl = bnx2_ioctl;
5385 dev->set_mac_address = bnx2_change_mac_addr;
5386 dev->change_mtu = bnx2_change_mtu;
5387 dev->tx_timeout = bnx2_tx_timeout;
5388 dev->watchdog_timeo = TX_TIMEOUT;
5389#ifdef BCM_VLAN
5390 dev->vlan_rx_register = bnx2_vlan_rx_register;
5391 dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
5392#endif
5393 dev->poll = bnx2_poll;
5394 dev->ethtool_ops = &bnx2_ethtool_ops;
5395 dev->weight = 64;
5396
5397 bp = dev->priv;
5398
5399#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5400 dev->poll_controller = poll_bnx2;
5401#endif
5402
5403 if ((rc = register_netdev(dev))) {
5404 printk(KERN_ERR PFX "Cannot register net device\n");
5405 if (bp->regview)
5406 iounmap(bp->regview);
5407 pci_release_regions(pdev);
5408 pci_disable_device(pdev);
5409 pci_set_drvdata(pdev, NULL);
5410 free_netdev(dev);
5411 return rc;
5412 }
5413
5414 pci_set_drvdata(pdev, dev);
5415
5416 memcpy(dev->dev_addr, bp->mac_addr, 6);
5417 bp->name = board_info[ent->driver_data].name,
5418 printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
5419 "IRQ %d, ",
5420 dev->name,
5421 bp->name,
5422 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
5423 ((CHIP_ID(bp) & 0x0ff0) >> 4),
5424 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
5425 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
5426 bp->bus_speed_mhz,
5427 dev->base_addr,
5428 bp->pdev->irq);
5429
5430 printk("node addr ");
5431 for (i = 0; i < 6; i++)
5432 printk("%2.2x", dev->dev_addr[i]);
5433 printk("\n");
5434
5435 dev->features |= NETIF_F_SG;
5436 if (bp->flags & USING_DAC_FLAG)
5437 dev->features |= NETIF_F_HIGHDMA;
5438 dev->features |= NETIF_F_IP_CSUM;
5439#ifdef BCM_VLAN
5440 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
5441#endif
5442#ifdef BCM_TSO
5443 dev->features |= NETIF_F_TSO;
5444#endif
5445
5446 netif_carrier_off(bp->dev);
5447
5448 return 0;
5449}
5450
5451static void __devexit
5452bnx2_remove_one(struct pci_dev *pdev)
5453{
5454 struct net_device *dev = pci_get_drvdata(pdev);
5455 struct bnx2 *bp = dev->priv;
5456
5457 unregister_netdev(dev);
5458
5459 if (bp->regview)
5460 iounmap(bp->regview);
5461
5462 free_netdev(dev);
5463 pci_release_regions(pdev);
5464 pci_disable_device(pdev);
5465 pci_set_drvdata(pdev, NULL);
5466}
5467
5468static int
5469bnx2_suspend(struct pci_dev *pdev, u32 state)
5470{
5471 struct net_device *dev = pci_get_drvdata(pdev);
5472 struct bnx2 *bp = dev->priv;
5473 u32 reset_code;
5474
5475 if (!netif_running(dev))
5476 return 0;
5477
5478 bnx2_netif_stop(bp);
5479 netif_device_detach(dev);
5480 del_timer_sync(&bp->timer);
5481 if (bp->wol)
5482 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5483 else
5484 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5485 bnx2_reset_chip(bp, reset_code);
5486 bnx2_free_skbs(bp);
5487 bnx2_set_power_state(bp, state);
5488 return 0;
5489}
5490
5491static int
5492bnx2_resume(struct pci_dev *pdev)
5493{
5494 struct net_device *dev = pci_get_drvdata(pdev);
5495 struct bnx2 *bp = dev->priv;
5496
5497 if (!netif_running(dev))
5498 return 0;
5499
5500 bnx2_set_power_state(bp, 0);
5501 netif_device_attach(dev);
5502 bnx2_init_nic(bp);
5503 bnx2_netif_start(bp);
5504 return 0;
5505}
5506
5507static struct pci_driver bnx2_pci_driver = {
5508 name: DRV_MODULE_NAME,
5509 id_table: bnx2_pci_tbl,
5510 probe: bnx2_init_one,
5511 remove: __devexit_p(bnx2_remove_one),
5512 suspend: bnx2_suspend,
5513 resume: bnx2_resume,
5514};
5515
5516static int __init bnx2_init(void)
5517{
5518 return pci_module_init(&bnx2_pci_driver);
5519}
5520
5521static void __exit bnx2_cleanup(void)
5522{
5523 pci_unregister_driver(&bnx2_pci_driver);
5524}
5525
5526module_init(bnx2_init);
5527module_exit(bnx2_cleanup);
5528
5529
5530
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
new file mode 100644
index 000000000000..8214a2853d0d
--- /dev/null
+++ b/drivers/net/bnx2.h
@@ -0,0 +1,4352 @@
1/* bnx2.h: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004, 2005 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12
13#ifndef BNX2_H
14#define BNX2_H
15
16#include <linux/config.h>
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20
21#include <linux/kernel.h>
22#include <linux/timer.h>
23#include <linux/errno.h>
24#include <linux/ioport.h>
25#include <linux/slab.h>
26#include <linux/interrupt.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
31#include <linux/skbuff.h>
32#include <linux/dma-mapping.h>
33#include <asm/bitops.h>
34#include <asm/io.h>
35#include <asm/irq.h>
36#include <linux/delay.h>
37#include <asm/byteorder.h>
38#include <linux/time.h>
39#include <linux/ethtool.h>
40#include <linux/mii.h>
41#ifdef NETIF_F_HW_VLAN_TX
42#include <linux/if_vlan.h>
43#define BCM_VLAN 1
44#endif
45#ifdef NETIF_F_TSO
46#include <net/ip.h>
47#include <net/tcp.h>
48#include <net/checksum.h>
49#define BCM_TSO 1
50#endif
51#include <linux/workqueue.h>
52#include <linux/crc32.h>
53
54/* Hardware data structures and register definitions automatically
55 * generated from RTL code. Do not modify.
56 */
57
58/*
59 * tx_bd definition
60 */
61struct tx_bd {
62 u32 tx_bd_haddr_hi;
63 u32 tx_bd_haddr_lo;
64 u32 tx_bd_mss_nbytes;
65 u32 tx_bd_vlan_tag_flags;
66 #define TX_BD_FLAGS_CONN_FAULT (1<<0)
67 #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1)
68 #define TX_BD_FLAGS_IP_CKSUM (1<<2)
69 #define TX_BD_FLAGS_VLAN_TAG (1<<3)
70 #define TX_BD_FLAGS_COAL_NOW (1<<4)
71 #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5)
72 #define TX_BD_FLAGS_END (1<<6)
73 #define TX_BD_FLAGS_START (1<<7)
74 #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8)
75 #define TX_BD_FLAGS_SW_FLAGS (1<<13)
76 #define TX_BD_FLAGS_SW_SNAP (1<<14)
77 #define TX_BD_FLAGS_SW_LSO (1<<15)
78
79};
80
81
82/*
83 * rx_bd definition
84 */
85struct rx_bd {
86 u32 rx_bd_haddr_hi;
87 u32 rx_bd_haddr_lo;
88 u32 rx_bd_len;
89 u32 rx_bd_flags;
90 #define RX_BD_FLAGS_NOPUSH (1<<0)
91 #define RX_BD_FLAGS_DUMMY (1<<1)
92 #define RX_BD_FLAGS_END (1<<2)
93 #define RX_BD_FLAGS_START (1<<3)
94
95};
96
97
98/*
99 * status_block definition
100 */
101struct status_block {
102 u32 status_attn_bits;
103 #define STATUS_ATTN_BITS_LINK_STATE (1L<<0)
104 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1)
105 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2)
106 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3)
107 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4)
108 #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5)
109 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6)
110 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7)
111 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8)
112 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9)
113 #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10)
114 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11)
115 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12)
116 #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13)
117 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14)
118 #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15)
119 #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16)
120 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17)
121 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18)
122 #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19)
123 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20)
124 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21)
125 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22)
126 #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23)
127 #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24)
128 #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25)
129 #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26)
130 #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27)
131 #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31)
132
133 u32 status_attn_bits_ack;
134#if defined(__BIG_ENDIAN)
135 u16 status_tx_quick_consumer_index0;
136 u16 status_tx_quick_consumer_index1;
137 u16 status_tx_quick_consumer_index2;
138 u16 status_tx_quick_consumer_index3;
139 u16 status_rx_quick_consumer_index0;
140 u16 status_rx_quick_consumer_index1;
141 u16 status_rx_quick_consumer_index2;
142 u16 status_rx_quick_consumer_index3;
143 u16 status_rx_quick_consumer_index4;
144 u16 status_rx_quick_consumer_index5;
145 u16 status_rx_quick_consumer_index6;
146 u16 status_rx_quick_consumer_index7;
147 u16 status_rx_quick_consumer_index8;
148 u16 status_rx_quick_consumer_index9;
149 u16 status_rx_quick_consumer_index10;
150 u16 status_rx_quick_consumer_index11;
151 u16 status_rx_quick_consumer_index12;
152 u16 status_rx_quick_consumer_index13;
153 u16 status_rx_quick_consumer_index14;
154 u16 status_rx_quick_consumer_index15;
155 u16 status_completion_producer_index;
156 u16 status_cmd_consumer_index;
157 u16 status_idx;
158 u16 status_unused;
159#elif defined(__LITTLE_ENDIAN)
160 u16 status_tx_quick_consumer_index1;
161 u16 status_tx_quick_consumer_index0;
162 u16 status_tx_quick_consumer_index3;
163 u16 status_tx_quick_consumer_index2;
164 u16 status_rx_quick_consumer_index1;
165 u16 status_rx_quick_consumer_index0;
166 u16 status_rx_quick_consumer_index3;
167 u16 status_rx_quick_consumer_index2;
168 u16 status_rx_quick_consumer_index5;
169 u16 status_rx_quick_consumer_index4;
170 u16 status_rx_quick_consumer_index7;
171 u16 status_rx_quick_consumer_index6;
172 u16 status_rx_quick_consumer_index9;
173 u16 status_rx_quick_consumer_index8;
174 u16 status_rx_quick_consumer_index11;
175 u16 status_rx_quick_consumer_index10;
176 u16 status_rx_quick_consumer_index13;
177 u16 status_rx_quick_consumer_index12;
178 u16 status_rx_quick_consumer_index15;
179 u16 status_rx_quick_consumer_index14;
180 u16 status_cmd_consumer_index;
181 u16 status_completion_producer_index;
182 u16 status_unused;
183 u16 status_idx;
184#endif
185};
186
187
188/*
189 * statistics_block definition
190 */
191struct statistics_block {
192 u32 stat_IfHCInOctets_hi;
193 u32 stat_IfHCInOctets_lo;
194 u32 stat_IfHCInBadOctets_hi;
195 u32 stat_IfHCInBadOctets_lo;
196 u32 stat_IfHCOutOctets_hi;
197 u32 stat_IfHCOutOctets_lo;
198 u32 stat_IfHCOutBadOctets_hi;
199 u32 stat_IfHCOutBadOctets_lo;
200 u32 stat_IfHCInUcastPkts_hi;
201 u32 stat_IfHCInUcastPkts_lo;
202 u32 stat_IfHCInMulticastPkts_hi;
203 u32 stat_IfHCInMulticastPkts_lo;
204 u32 stat_IfHCInBroadcastPkts_hi;
205 u32 stat_IfHCInBroadcastPkts_lo;
206 u32 stat_IfHCOutUcastPkts_hi;
207 u32 stat_IfHCOutUcastPkts_lo;
208 u32 stat_IfHCOutMulticastPkts_hi;
209 u32 stat_IfHCOutMulticastPkts_lo;
210 u32 stat_IfHCOutBroadcastPkts_hi;
211 u32 stat_IfHCOutBroadcastPkts_lo;
212 u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
213 u32 stat_Dot3StatsCarrierSenseErrors;
214 u32 stat_Dot3StatsFCSErrors;
215 u32 stat_Dot3StatsAlignmentErrors;
216 u32 stat_Dot3StatsSingleCollisionFrames;
217 u32 stat_Dot3StatsMultipleCollisionFrames;
218 u32 stat_Dot3StatsDeferredTransmissions;
219 u32 stat_Dot3StatsExcessiveCollisions;
220 u32 stat_Dot3StatsLateCollisions;
221 u32 stat_EtherStatsCollisions;
222 u32 stat_EtherStatsFragments;
223 u32 stat_EtherStatsJabbers;
224 u32 stat_EtherStatsUndersizePkts;
225 u32 stat_EtherStatsOverrsizePkts;
226 u32 stat_EtherStatsPktsRx64Octets;
227 u32 stat_EtherStatsPktsRx65Octetsto127Octets;
228 u32 stat_EtherStatsPktsRx128Octetsto255Octets;
229 u32 stat_EtherStatsPktsRx256Octetsto511Octets;
230 u32 stat_EtherStatsPktsRx512Octetsto1023Octets;
231 u32 stat_EtherStatsPktsRx1024Octetsto1522Octets;
232 u32 stat_EtherStatsPktsRx1523Octetsto9022Octets;
233 u32 stat_EtherStatsPktsTx64Octets;
234 u32 stat_EtherStatsPktsTx65Octetsto127Octets;
235 u32 stat_EtherStatsPktsTx128Octetsto255Octets;
236 u32 stat_EtherStatsPktsTx256Octetsto511Octets;
237 u32 stat_EtherStatsPktsTx512Octetsto1023Octets;
238 u32 stat_EtherStatsPktsTx1024Octetsto1522Octets;
239 u32 stat_EtherStatsPktsTx1523Octetsto9022Octets;
240 u32 stat_XonPauseFramesReceived;
241 u32 stat_XoffPauseFramesReceived;
242 u32 stat_OutXonSent;
243 u32 stat_OutXoffSent;
244 u32 stat_FlowControlDone;
245 u32 stat_MacControlFramesReceived;
246 u32 stat_XoffStateEntered;
247 u32 stat_IfInFramesL2FilterDiscards;
248 u32 stat_IfInRuleCheckerDiscards;
249 u32 stat_IfInFTQDiscards;
250 u32 stat_IfInMBUFDiscards;
251 u32 stat_IfInRuleCheckerP4Hit;
252 u32 stat_CatchupInRuleCheckerDiscards;
253 u32 stat_CatchupInFTQDiscards;
254 u32 stat_CatchupInMBUFDiscards;
255 u32 stat_CatchupInRuleCheckerP4Hit;
256 u32 stat_GenStat00;
257 u32 stat_GenStat01;
258 u32 stat_GenStat02;
259 u32 stat_GenStat03;
260 u32 stat_GenStat04;
261 u32 stat_GenStat05;
262 u32 stat_GenStat06;
263 u32 stat_GenStat07;
264 u32 stat_GenStat08;
265 u32 stat_GenStat09;
266 u32 stat_GenStat10;
267 u32 stat_GenStat11;
268 u32 stat_GenStat12;
269 u32 stat_GenStat13;
270 u32 stat_GenStat14;
271 u32 stat_GenStat15;
272};
273
274
275/*
276 * l2_fhdr definition
277 */
278struct l2_fhdr {
279#if defined(__BIG_ENDIAN)
280 u16 l2_fhdr_errors;
281 u16 l2_fhdr_status;
282#elif defined(__LITTLE_ENDIAN)
283 u16 l2_fhdr_status;
284 u16 l2_fhdr_errors;
285#endif
286 #define L2_FHDR_ERRORS_BAD_CRC (1<<1)
287 #define L2_FHDR_ERRORS_PHY_DECODE (1<<2)
288 #define L2_FHDR_ERRORS_ALIGNMENT (1<<3)
289 #define L2_FHDR_ERRORS_TOO_SHORT (1<<4)
290 #define L2_FHDR_ERRORS_GIANT_FRAME (1<<5)
291
292 #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0)
293 #define L2_FHDR_STATUS_RULE_P2 (1<<3)
294 #define L2_FHDR_STATUS_RULE_P3 (1<<4)
295 #define L2_FHDR_STATUS_RULE_P4 (1<<5)
296 #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6)
297 #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7)
298 #define L2_FHDR_STATUS_RSS_HASH (1<<8)
299 #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13)
300 #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14)
301 #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15)
302
303 u32 l2_fhdr_hash;
304#if defined(__BIG_ENDIAN)
305 u16 l2_fhdr_pkt_len;
306 u16 l2_fhdr_vlan_tag;
307 u16 l2_fhdr_ip_xsum;
308 u16 l2_fhdr_tcp_udp_xsum;
309#elif defined(__LITTLE_ENDIAN)
310 u16 l2_fhdr_vlan_tag;
311 u16 l2_fhdr_pkt_len;
312 u16 l2_fhdr_tcp_udp_xsum;
313 u16 l2_fhdr_ip_xsum;
314#endif
315};
316
317
318/*
319 * l2_context definition
320 */
321#define BNX2_L2CTX_TYPE 0x00000000
322#define BNX2_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16)
323#define BNX2_L2CTX_TYPE_TYPE (0xf<<28)
324#define BNX2_L2CTX_TYPE_TYPE_EMPTY (0<<28)
325#define BNX2_L2CTX_TYPE_TYPE_L2 (1<<28)
326
327#define BNX2_L2CTX_TX_HOST_BIDX 0x00000088
328#define BNX2_L2CTX_EST_NBD 0x00000088
329#define BNX2_L2CTX_CMD_TYPE 0x00000088
330#define BNX2_L2CTX_CMD_TYPE_TYPE (0xf<<24)
331#define BNX2_L2CTX_CMD_TYPE_TYPE_L2 (0<<24)
332#define BNX2_L2CTX_CMD_TYPE_TYPE_TCP (1<<24)
333
334#define BNX2_L2CTX_TX_HOST_BSEQ 0x00000090
335#define BNX2_L2CTX_TSCH_BSEQ 0x00000094
336#define BNX2_L2CTX_TBDR_BSEQ 0x00000098
337#define BNX2_L2CTX_TBDR_BOFF 0x0000009c
338#define BNX2_L2CTX_TBDR_BIDX 0x0000009c
339#define BNX2_L2CTX_TBDR_BHADDR_HI 0x000000a0
340#define BNX2_L2CTX_TBDR_BHADDR_LO 0x000000a4
341#define BNX2_L2CTX_TXP_BOFF 0x000000a8
342#define BNX2_L2CTX_TXP_BIDX 0x000000a8
343#define BNX2_L2CTX_TXP_BSEQ 0x000000ac
344
345
346/*
347 * l2_bd_chain_context definition
348 */
349#define BNX2_L2CTX_BD_PRE_READ 0x00000000
350#define BNX2_L2CTX_CTX_SIZE 0x00000000
351#define BNX2_L2CTX_CTX_TYPE 0x00000000
352#define BNX2_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16)
353#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28)
354#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28)
355#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28)
356
357#define BNX2_L2CTX_HOST_BDIDX 0x00000004
358#define BNX2_L2CTX_HOST_BSEQ 0x00000008
359#define BNX2_L2CTX_NX_BSEQ 0x0000000c
360#define BNX2_L2CTX_NX_BDHADDR_HI 0x00000010
361#define BNX2_L2CTX_NX_BDHADDR_LO 0x00000014
362#define BNX2_L2CTX_NX_BDIDX 0x00000018
363
364
365/*
366 * pci_config_l definition
367 * offset: 0000
368 */
369#define BNX2_PCICFG_MISC_CONFIG 0x00000068
370#define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2)
371#define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3)
372#define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5)
373#define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6)
374#define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7)
375#define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8)
376#define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9)
377#define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16)
378#define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24)
379#define BNX2_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28)
380
381#define BNX2_PCICFG_MISC_STATUS 0x0000006c
382#define BNX2_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0)
383#define BNX2_PCICFG_MISC_STATUS_32BIT_DET (1L<<1)
384#define BNX2_PCICFG_MISC_STATUS_M66EN (1L<<2)
385#define BNX2_PCICFG_MISC_STATUS_PCIX_DET (1L<<3)
386#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4)
387#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4)
388#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4)
389#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4)
390#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4)
391
392#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070
393#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
394#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
395#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
396#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
397#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
398#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
399#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
400#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
401#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
402#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
403#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
404#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
405#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
406#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
407#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
408#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
409#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
410#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11)
411#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
412#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
413#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
414#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
415#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
416#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
417#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
418#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17)
419#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
420#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19)
421#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
422
423#define BNX2_PCICFG_REG_WINDOW_ADDRESS 0x00000078
424#define BNX2_PCICFG_REG_WINDOW 0x00000080
425#define BNX2_PCICFG_INT_ACK_CMD 0x00000084
426#define BNX2_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0)
427#define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16)
428#define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17)
429#define BNX2_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18)
430
431#define BNX2_PCICFG_STATUS_BIT_SET_CMD 0x00000088
432#define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c
433#define BNX2_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090
434#define BNX2_PCICFG_MAILBOX_QUEUE_DATA 0x00000094
435
436
437/*
438 * pci_reg definition
439 * offset: 0x400
440 */
441#define BNX2_PCI_GRC_WINDOW_ADDR 0x00000400
442#define BNX2_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8)
443
444#define BNX2_PCI_CONFIG_1 0x00000404
445#define BNX2_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8)
446#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8)
447#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8)
448#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8)
449#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8)
450#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8)
451#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8)
452#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8)
453#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8)
454#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11)
455#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11)
456#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11)
457#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11)
458#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11)
459#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11)
460#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11)
461#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11)
462#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11)
463
464#define BNX2_PCI_CONFIG_2 0x00000408
465#define BNX2_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
466#define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
467#define BNX2_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
468#define BNX2_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
469#define BNX2_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
470#define BNX2_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
471#define BNX2_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
472#define BNX2_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
473#define BNX2_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
474#define BNX2_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
475#define BNX2_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
476#define BNX2_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
477#define BNX2_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
478#define BNX2_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
479#define BNX2_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
480#define BNX2_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
481#define BNX2_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
482#define BNX2_PCI_CONFIG_2_BAR1_64ENA (1L<<4)
483#define BNX2_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
484#define BNX2_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
485#define BNX2_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
486#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
487#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
488#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8)
489#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8)
490#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8)
491#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8)
492#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8)
493#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8)
494#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8)
495#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8)
496#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8)
497#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8)
498#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8)
499#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8)
500#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8)
501#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8)
502#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8)
503#define BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16)
504#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21)
505#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21)
506#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21)
507#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21)
508#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21)
509#define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23)
510#define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24)
511#define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25)
512
513#define BNX2_PCI_CONFIG_3 0x0000040c
514#define BNX2_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
515#define BNX2_PCI_CONFIG_3_FORCE_PME (1L<<24)
516#define BNX2_PCI_CONFIG_3_PME_STATUS (1L<<25)
517#define BNX2_PCI_CONFIG_3_PME_ENABLE (1L<<26)
518#define BNX2_PCI_CONFIG_3_PM_STATE (0x3L<<27)
519#define BNX2_PCI_CONFIG_3_VAUX_PRESET (1L<<30)
520#define BNX2_PCI_CONFIG_3_PCI_POWER (1L<<31)
521
522#define BNX2_PCI_PM_DATA_A 0x00000410
523#define BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0)
524#define BNX2_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8)
525#define BNX2_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16)
526#define BNX2_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24)
527
528#define BNX2_PCI_PM_DATA_B 0x00000414
529#define BNX2_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0)
530#define BNX2_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8)
531#define BNX2_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16)
532#define BNX2_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24)
533
534#define BNX2_PCI_SWAP_DIAG0 0x00000418
535#define BNX2_PCI_SWAP_DIAG1 0x0000041c
536#define BNX2_PCI_EXP_ROM_ADDR 0x00000420
537#define BNX2_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2)
538#define BNX2_PCI_EXP_ROM_ADDR_REQ (1L<<31)
539
540#define BNX2_PCI_EXP_ROM_DATA 0x00000424
541#define BNX2_PCI_VPD_INTF 0x00000428
542#define BNX2_PCI_VPD_INTF_INTF_REQ (1L<<0)
543
544#define BNX2_PCI_VPD_ADDR_FLAG 0x0000042c
545#define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2)
546#define BNX2_PCI_VPD_ADDR_FLAG_WR (1<<15)
547
548#define BNX2_PCI_VPD_DATA 0x00000430
549#define BNX2_PCI_ID_VAL1 0x00000434
550#define BNX2_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0)
551#define BNX2_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16)
552
553#define BNX2_PCI_ID_VAL2 0x00000438
554#define BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0)
555#define BNX2_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16)
556
557#define BNX2_PCI_ID_VAL3 0x0000043c
558#define BNX2_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0)
559#define BNX2_PCI_ID_VAL3_REVISION_ID (0xffL<<24)
560
561#define BNX2_PCI_ID_VAL4 0x00000440
562#define BNX2_PCI_ID_VAL4_CAP_ENA (0xfL<<0)
563#define BNX2_PCI_ID_VAL4_CAP_ENA_0 (0L<<0)
564#define BNX2_PCI_ID_VAL4_CAP_ENA_1 (1L<<0)
565#define BNX2_PCI_ID_VAL4_CAP_ENA_2 (2L<<0)
566#define BNX2_PCI_ID_VAL4_CAP_ENA_3 (3L<<0)
567#define BNX2_PCI_ID_VAL4_CAP_ENA_4 (4L<<0)
568#define BNX2_PCI_ID_VAL4_CAP_ENA_5 (5L<<0)
569#define BNX2_PCI_ID_VAL4_CAP_ENA_6 (6L<<0)
570#define BNX2_PCI_ID_VAL4_CAP_ENA_7 (7L<<0)
571#define BNX2_PCI_ID_VAL4_CAP_ENA_8 (8L<<0)
572#define BNX2_PCI_ID_VAL4_CAP_ENA_9 (9L<<0)
573#define BNX2_PCI_ID_VAL4_CAP_ENA_10 (10L<<0)
574#define BNX2_PCI_ID_VAL4_CAP_ENA_11 (11L<<0)
575#define BNX2_PCI_ID_VAL4_CAP_ENA_12 (12L<<0)
576#define BNX2_PCI_ID_VAL4_CAP_ENA_13 (13L<<0)
577#define BNX2_PCI_ID_VAL4_CAP_ENA_14 (14L<<0)
578#define BNX2_PCI_ID_VAL4_CAP_ENA_15 (15L<<0)
579#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6)
580#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6)
581#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6)
582#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6)
583#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6)
584#define BNX2_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9)
585#define BNX2_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12)
586#define BNX2_PCI_ID_VAL4_MSI_ENABLE (1L<<15)
587#define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16)
588#define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17)
589#define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21)
590#define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23)
591#define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26)
592
593#define BNX2_PCI_ID_VAL5 0x00000444
594#define BNX2_PCI_ID_VAL5_D1_SUPPORT (1L<<0)
595#define BNX2_PCI_ID_VAL5_D2_SUPPORT (1L<<1)
596#define BNX2_PCI_ID_VAL5_PME_IN_D0 (1L<<2)
597#define BNX2_PCI_ID_VAL5_PME_IN_D1 (1L<<3)
598#define BNX2_PCI_ID_VAL5_PME_IN_D2 (1L<<4)
599#define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5)
600
601#define BNX2_PCI_PCIX_EXTENDED_STATUS 0x00000448
602#define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8)
603#define BNX2_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9)
604#define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16)
605#define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24)
606
607#define BNX2_PCI_ID_VAL6 0x0000044c
608#define BNX2_PCI_ID_VAL6_MAX_LAT (0xffL<<0)
609#define BNX2_PCI_ID_VAL6_MIN_GNT (0xffL<<8)
610#define BNX2_PCI_ID_VAL6_BIST (0xffL<<16)
611
612#define BNX2_PCI_MSI_DATA 0x00000450
613#define BNX2_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0)
614
615#define BNX2_PCI_MSI_ADDR_H 0x00000454
616#define BNX2_PCI_MSI_ADDR_L 0x00000458
617
618
619/*
620 * misc_reg definition
621 * offset: 0x800
622 */
623#define BNX2_MISC_COMMAND 0x00000800
624#define BNX2_MISC_COMMAND_ENABLE_ALL (1L<<0)
625#define BNX2_MISC_COMMAND_DISABLE_ALL (1L<<1)
626#define BNX2_MISC_COMMAND_CORE_RESET (1L<<4)
627#define BNX2_MISC_COMMAND_HARD_RESET (1L<<5)
628#define BNX2_MISC_COMMAND_PAR_ERROR (1L<<8)
629#define BNX2_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16)
630
631#define BNX2_MISC_CFG 0x00000804
632#define BNX2_MISC_CFG_PCI_GRC_TMOUT (1L<<0)
633#define BNX2_MISC_CFG_NVM_WR_EN (0x3L<<1)
634#define BNX2_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1)
635#define BNX2_MISC_CFG_NVM_WR_EN_PCI (1L<<1)
636#define BNX2_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1)
637#define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1)
638#define BNX2_MISC_CFG_BIST_EN (1L<<3)
639#define BNX2_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4)
640#define BNX2_MISC_CFG_BYPASS_BSCAN (1L<<5)
641#define BNX2_MISC_CFG_BYPASS_EJTAG (1L<<6)
642#define BNX2_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7)
643#define BNX2_MISC_CFG_LEDMODE (0x3L<<8)
644#define BNX2_MISC_CFG_LEDMODE_MAC (0L<<8)
645#define BNX2_MISC_CFG_LEDMODE_GPHY1 (1L<<8)
646#define BNX2_MISC_CFG_LEDMODE_GPHY2 (2L<<8)
647
648#define BNX2_MISC_ID 0x00000808
649#define BNX2_MISC_ID_BOND_ID (0xfL<<0)
650#define BNX2_MISC_ID_CHIP_METAL (0xffL<<4)
651#define BNX2_MISC_ID_CHIP_REV (0xfL<<12)
652#define BNX2_MISC_ID_CHIP_NUM (0xffffL<<16)
653
654#define BNX2_MISC_ENABLE_STATUS_BITS 0x0000080c
655#define BNX2_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0)
656#define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1)
657#define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2)
658#define BNX2_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3)
659#define BNX2_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4)
660#define BNX2_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5)
661#define BNX2_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
662#define BNX2_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7)
663#define BNX2_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
664#define BNX2_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9)
665#define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
666#define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
667#define BNX2_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12)
668#define BNX2_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13)
669#define BNX2_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14)
670#define BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15)
671#define BNX2_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16)
672#define BNX2_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17)
673#define BNX2_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18)
674#define BNX2_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19)
675#define BNX2_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
676#define BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21)
677#define BNX2_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
678#define BNX2_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
679#define BNX2_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
680#define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25)
681#define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26)
682#define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27)
683
684#define BNX2_MISC_ENABLE_SET_BITS 0x00000810
685#define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0)
686#define BNX2_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1)
687#define BNX2_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2)
688#define BNX2_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3)
689#define BNX2_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4)
690#define BNX2_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5)
691#define BNX2_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
692#define BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7)
693#define BNX2_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
694#define BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9)
695#define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
696#define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
697#define BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12)
698#define BNX2_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13)
699#define BNX2_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14)
700#define BNX2_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15)
701#define BNX2_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16)
702#define BNX2_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17)
703#define BNX2_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18)
704#define BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19)
705#define BNX2_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
706#define BNX2_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21)
707#define BNX2_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
708#define BNX2_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
709#define BNX2_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
710#define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25)
711#define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26)
712#define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27)
713
714#define BNX2_MISC_ENABLE_CLR_BITS 0x00000814
715#define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0)
716#define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1)
717#define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2)
718#define BNX2_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3)
719#define BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4)
720#define BNX2_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5)
721#define BNX2_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
722#define BNX2_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7)
723#define BNX2_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
724#define BNX2_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9)
725#define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
726#define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
727#define BNX2_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12)
728#define BNX2_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13)
729#define BNX2_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14)
730#define BNX2_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15)
731#define BNX2_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16)
732#define BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17)
733#define BNX2_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18)
734#define BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19)
735#define BNX2_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
736#define BNX2_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21)
737#define BNX2_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
738#define BNX2_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
739#define BNX2_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
740#define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25)
741#define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26)
742#define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27)
743
744#define BNX2_MISC_CLOCK_CONTROL_BITS 0x00000818
745#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
746#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
747#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
748#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
749#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
750#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
751#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
752#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
753#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
754#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
755#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
756#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
757#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
758#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
759#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
760#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
761#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
762#define BNX2_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11)
763#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
764#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
765#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
766#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
767#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
768#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
769#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
770#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17)
771#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
772#define BNX2_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19)
773#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
774
775#define BNX2_MISC_GPIO 0x0000081c
776#define BNX2_MISC_GPIO_VALUE (0xffL<<0)
777#define BNX2_MISC_GPIO_SET (0xffL<<8)
778#define BNX2_MISC_GPIO_CLR (0xffL<<16)
779#define BNX2_MISC_GPIO_FLOAT (0xffL<<24)
780
781#define BNX2_MISC_GPIO_INT 0x00000820
782#define BNX2_MISC_GPIO_INT_INT_STATE (0xfL<<0)
783#define BNX2_MISC_GPIO_INT_OLD_VALUE (0xfL<<8)
784#define BNX2_MISC_GPIO_INT_OLD_SET (0xfL<<16)
785#define BNX2_MISC_GPIO_INT_OLD_CLR (0xfL<<24)
786
787#define BNX2_MISC_CONFIG_LFSR 0x00000824
788#define BNX2_MISC_CONFIG_LFSR_DIV (0xffffL<<0)
789
790#define BNX2_MISC_LFSR_MASK_BITS 0x00000828
791#define BNX2_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0)
792#define BNX2_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1)
793#define BNX2_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2)
794#define BNX2_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3)
795#define BNX2_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4)
796#define BNX2_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5)
797#define BNX2_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
798#define BNX2_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7)
799#define BNX2_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
800#define BNX2_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9)
801#define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
802#define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
803#define BNX2_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12)
804#define BNX2_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13)
805#define BNX2_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14)
806#define BNX2_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15)
807#define BNX2_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16)
808#define BNX2_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17)
809#define BNX2_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18)
810#define BNX2_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19)
811#define BNX2_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
812#define BNX2_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21)
813#define BNX2_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
814#define BNX2_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
815#define BNX2_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
816#define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25)
817#define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26)
818#define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27)
819
820#define BNX2_MISC_ARB_REQ0 0x0000082c
821#define BNX2_MISC_ARB_REQ1 0x00000830
822#define BNX2_MISC_ARB_REQ2 0x00000834
823#define BNX2_MISC_ARB_REQ3 0x00000838
824#define BNX2_MISC_ARB_REQ4 0x0000083c
825#define BNX2_MISC_ARB_FREE0 0x00000840
826#define BNX2_MISC_ARB_FREE1 0x00000844
827#define BNX2_MISC_ARB_FREE2 0x00000848
828#define BNX2_MISC_ARB_FREE3 0x0000084c
829#define BNX2_MISC_ARB_FREE4 0x00000850
830#define BNX2_MISC_ARB_REQ_STATUS0 0x00000854
831#define BNX2_MISC_ARB_REQ_STATUS1 0x00000858
832#define BNX2_MISC_ARB_REQ_STATUS2 0x0000085c
833#define BNX2_MISC_ARB_REQ_STATUS3 0x00000860
834#define BNX2_MISC_ARB_REQ_STATUS4 0x00000864
835#define BNX2_MISC_ARB_GNT0 0x00000868
836#define BNX2_MISC_ARB_GNT0_0 (0x7L<<0)
837#define BNX2_MISC_ARB_GNT0_1 (0x7L<<4)
838#define BNX2_MISC_ARB_GNT0_2 (0x7L<<8)
839#define BNX2_MISC_ARB_GNT0_3 (0x7L<<12)
840#define BNX2_MISC_ARB_GNT0_4 (0x7L<<16)
841#define BNX2_MISC_ARB_GNT0_5 (0x7L<<20)
842#define BNX2_MISC_ARB_GNT0_6 (0x7L<<24)
843#define BNX2_MISC_ARB_GNT0_7 (0x7L<<28)
844
845#define BNX2_MISC_ARB_GNT1 0x0000086c
846#define BNX2_MISC_ARB_GNT1_8 (0x7L<<0)
847#define BNX2_MISC_ARB_GNT1_9 (0x7L<<4)
848#define BNX2_MISC_ARB_GNT1_10 (0x7L<<8)
849#define BNX2_MISC_ARB_GNT1_11 (0x7L<<12)
850#define BNX2_MISC_ARB_GNT1_12 (0x7L<<16)
851#define BNX2_MISC_ARB_GNT1_13 (0x7L<<20)
852#define BNX2_MISC_ARB_GNT1_14 (0x7L<<24)
853#define BNX2_MISC_ARB_GNT1_15 (0x7L<<28)
854
855#define BNX2_MISC_ARB_GNT2 0x00000870
856#define BNX2_MISC_ARB_GNT2_16 (0x7L<<0)
857#define BNX2_MISC_ARB_GNT2_17 (0x7L<<4)
858#define BNX2_MISC_ARB_GNT2_18 (0x7L<<8)
859#define BNX2_MISC_ARB_GNT2_19 (0x7L<<12)
860#define BNX2_MISC_ARB_GNT2_20 (0x7L<<16)
861#define BNX2_MISC_ARB_GNT2_21 (0x7L<<20)
862#define BNX2_MISC_ARB_GNT2_22 (0x7L<<24)
863#define BNX2_MISC_ARB_GNT2_23 (0x7L<<28)
864
865#define BNX2_MISC_ARB_GNT3 0x00000874
866#define BNX2_MISC_ARB_GNT3_24 (0x7L<<0)
867#define BNX2_MISC_ARB_GNT3_25 (0x7L<<4)
868#define BNX2_MISC_ARB_GNT3_26 (0x7L<<8)
869#define BNX2_MISC_ARB_GNT3_27 (0x7L<<12)
870#define BNX2_MISC_ARB_GNT3_28 (0x7L<<16)
871#define BNX2_MISC_ARB_GNT3_29 (0x7L<<20)
872#define BNX2_MISC_ARB_GNT3_30 (0x7L<<24)
873#define BNX2_MISC_ARB_GNT3_31 (0x7L<<28)
874
875#define BNX2_MISC_PRBS_CONTROL 0x00000878
876#define BNX2_MISC_PRBS_CONTROL_EN (1L<<0)
877#define BNX2_MISC_PRBS_CONTROL_RSTB (1L<<1)
878#define BNX2_MISC_PRBS_CONTROL_INV (1L<<2)
879#define BNX2_MISC_PRBS_CONTROL_ERR_CLR (1L<<3)
880#define BNX2_MISC_PRBS_CONTROL_ORDER (0x3L<<4)
881#define BNX2_MISC_PRBS_CONTROL_ORDER_7TH (0L<<4)
882#define BNX2_MISC_PRBS_CONTROL_ORDER_15TH (1L<<4)
883#define BNX2_MISC_PRBS_CONTROL_ORDER_23RD (2L<<4)
884#define BNX2_MISC_PRBS_CONTROL_ORDER_31ST (3L<<4)
885
886#define BNX2_MISC_PRBS_STATUS 0x0000087c
887#define BNX2_MISC_PRBS_STATUS_LOCK (1L<<0)
888#define BNX2_MISC_PRBS_STATUS_STKY (1L<<1)
889#define BNX2_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2)
890#define BNX2_MISC_PRBS_STATUS_STATE (0xfL<<16)
891
892#define BNX2_MISC_SM_ASF_CONTROL 0x00000880
893#define BNX2_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0)
894#define BNX2_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1)
895#define BNX2_MISC_SM_ASF_CONTROL_WG_TO (1L<<2)
896#define BNX2_MISC_SM_ASF_CONTROL_HB_TO (1L<<3)
897#define BNX2_MISC_SM_ASF_CONTROL_PA_TO (1L<<4)
898#define BNX2_MISC_SM_ASF_CONTROL_PL_TO (1L<<5)
899#define BNX2_MISC_SM_ASF_CONTROL_RT_TO (1L<<6)
900#define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7)
901#define BNX2_MISC_SM_ASF_CONTROL_RES (0xfL<<8)
902#define BNX2_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12)
903#define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13)
904#define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14)
905#define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15)
906#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16)
907#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24)
908#define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30)
909#define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31)
910
911#define BNX2_MISC_SMB_IN 0x00000884
912#define BNX2_MISC_SMB_IN_DAT_IN (0xffL<<0)
913#define BNX2_MISC_SMB_IN_RDY (1L<<8)
914#define BNX2_MISC_SMB_IN_DONE (1L<<9)
915#define BNX2_MISC_SMB_IN_FIRSTBYTE (1L<<10)
916#define BNX2_MISC_SMB_IN_STATUS (0x7L<<11)
917#define BNX2_MISC_SMB_IN_STATUS_OK (0x0L<<11)
918#define BNX2_MISC_SMB_IN_STATUS_PEC (0x1L<<11)
919#define BNX2_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11)
920#define BNX2_MISC_SMB_IN_STATUS_STOP (0x3L<<11)
921#define BNX2_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11)
922
923#define BNX2_MISC_SMB_OUT 0x00000888
924#define BNX2_MISC_SMB_OUT_DAT_OUT (0xffL<<0)
925#define BNX2_MISC_SMB_OUT_RDY (1L<<8)
926#define BNX2_MISC_SMB_OUT_START (1L<<9)
927#define BNX2_MISC_SMB_OUT_LAST (1L<<10)
928#define BNX2_MISC_SMB_OUT_ACC_TYPE (1L<<11)
929#define BNX2_MISC_SMB_OUT_ENB_PEC (1L<<12)
930#define BNX2_MISC_SMB_OUT_GET_RX_LEN (1L<<13)
931#define BNX2_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14)
932#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20)
933#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20)
934#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20)
935#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20)
936#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20)
937#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20)
938#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20)
939#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20)
940#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20)
941#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (0x6L<<20)
942#define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24)
943#define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25)
944#define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26)
945#define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27)
946#define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28)
947
948#define BNX2_MISC_SMB_WATCHDOG 0x0000088c
949#define BNX2_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0)
950
951#define BNX2_MISC_SMB_HEARTBEAT 0x00000890
952#define BNX2_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0)
953
954#define BNX2_MISC_SMB_POLL_ASF 0x00000894
955#define BNX2_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0)
956
957#define BNX2_MISC_SMB_POLL_LEGACY 0x00000898
958#define BNX2_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0)
959
960#define BNX2_MISC_SMB_RETRAN 0x0000089c
961#define BNX2_MISC_SMB_RETRAN_RETRAN (0xffL<<0)
962
963#define BNX2_MISC_SMB_TIMESTAMP 0x000008a0
964#define BNX2_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0)
965
966#define BNX2_MISC_PERR_ENA0 0x000008a4
967#define BNX2_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0)
968#define BNX2_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1)
969#define BNX2_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2)
970#define BNX2_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3)
971#define BNX2_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4)
972#define BNX2_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5)
973#define BNX2_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6)
974#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7)
975#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8)
976#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9)
977#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10)
978#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11)
979#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12)
980#define BNX2_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13)
981#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14)
982#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15)
983#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16)
984#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17)
985#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18)
986#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19)
987#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20)
988#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21)
989#define BNX2_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22)
990#define BNX2_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23)
991#define BNX2_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24)
992#define BNX2_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25)
993#define BNX2_MISC_PERR_ENA0_RBDC_MISC (1L<<26)
994#define BNX2_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27)
995#define BNX2_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28)
996#define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29)
997#define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30)
998#define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31)
999
1000#define BNX2_MISC_PERR_ENA1 0x000008a8
1001#define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0)
1002#define BNX2_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1)
1003#define BNX2_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2)
1004#define BNX2_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3)
1005#define BNX2_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4)
1006#define BNX2_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5)
1007#define BNX2_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6)
1008#define BNX2_MISC_PERR_ENA1_TBDC_MISC (1L<<7)
1009#define BNX2_MISC_PERR_ENA1_TDMA_MISC (1L<<8)
1010#define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9)
1011#define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10)
1012#define BNX2_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11)
1013#define BNX2_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12)
1014#define BNX2_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13)
1015#define BNX2_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14)
1016#define BNX2_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15)
1017#define BNX2_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16)
1018#define BNX2_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17)
1019#define BNX2_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18)
1020#define BNX2_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19)
1021#define BNX2_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20)
1022#define BNX2_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21)
1023#define BNX2_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22)
1024#define BNX2_MISC_PERR_ENA1_CSQ_MISC (1L<<23)
1025#define BNX2_MISC_PERR_ENA1_CPQ_MISC (1L<<24)
1026#define BNX2_MISC_PERR_ENA1_MCPQ_MISC (1L<<25)
1027#define BNX2_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26)
1028#define BNX2_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27)
1029#define BNX2_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28)
1030#define BNX2_MISC_PERR_ENA1_RXPQ_MISC (1L<<29)
1031#define BNX2_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30)
1032#define BNX2_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31)
1033
1034#define BNX2_MISC_PERR_ENA2 0x000008ac
1035#define BNX2_MISC_PERR_ENA2_COMQ_MISC (1L<<0)
1036#define BNX2_MISC_PERR_ENA2_COMXQ_MISC (1L<<1)
1037#define BNX2_MISC_PERR_ENA2_COMTQ_MISC (1L<<2)
1038#define BNX2_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3)
1039#define BNX2_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4)
1040#define BNX2_MISC_PERR_ENA2_TXPQ_MISC (1L<<5)
1041#define BNX2_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6)
1042#define BNX2_MISC_PERR_ENA2_TPATQ_MISC (1L<<7)
1043#define BNX2_MISC_PERR_ENA2_TASQ_MISC (1L<<8)
1044
1045#define BNX2_MISC_DEBUG_VECTOR_SEL 0x000008b0
1046#define BNX2_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0)
1047#define BNX2_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12)
1048
1049#define BNX2_MISC_VREG_CONTROL 0x000008b4
1050#define BNX2_MISC_VREG_CONTROL_1_2 (0xfL<<0)
1051#define BNX2_MISC_VREG_CONTROL_2_5 (0xfL<<4)
1052
1053#define BNX2_MISC_FINAL_CLK_CTL_VAL 0x000008b8
1054#define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6)
1055
1056#define BNX2_MISC_UNUSED0 0x000008bc
1057
1058
1059/*
1060 * nvm_reg definition
1061 * offset: 0x6400
1062 */
1063#define BNX2_NVM_COMMAND 0x00006400
1064#define BNX2_NVM_COMMAND_RST (1L<<0)
1065#define BNX2_NVM_COMMAND_DONE (1L<<3)
1066#define BNX2_NVM_COMMAND_DOIT (1L<<4)
1067#define BNX2_NVM_COMMAND_WR (1L<<5)
1068#define BNX2_NVM_COMMAND_ERASE (1L<<6)
1069#define BNX2_NVM_COMMAND_FIRST (1L<<7)
1070#define BNX2_NVM_COMMAND_LAST (1L<<8)
1071#define BNX2_NVM_COMMAND_WREN (1L<<16)
1072#define BNX2_NVM_COMMAND_WRDI (1L<<17)
1073#define BNX2_NVM_COMMAND_EWSR (1L<<18)
1074#define BNX2_NVM_COMMAND_WRSR (1L<<19)
1075
1076#define BNX2_NVM_STATUS 0x00006404
1077#define BNX2_NVM_STATUS_PI_FSM_STATE (0xfL<<0)
1078#define BNX2_NVM_STATUS_EE_FSM_STATE (0xfL<<4)
1079#define BNX2_NVM_STATUS_EQ_FSM_STATE (0xfL<<8)
1080
1081#define BNX2_NVM_WRITE 0x00006408
1082#define BNX2_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0)
1083#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0)
1084#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0)
1085#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0)
1086#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0)
1087#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0)
1088#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0)
1089#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0)
1090
1091#define BNX2_NVM_ADDR 0x0000640c
1092#define BNX2_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
1093#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0)
1094#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0)
1095#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0)
1096#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0)
1097#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0)
1098#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0)
1099#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0)
1100
1101#define BNX2_NVM_READ 0x00006410
1102#define BNX2_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0)
1103#define BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0)
1104#define BNX2_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0)
1105#define BNX2_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0)
1106#define BNX2_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0)
1107#define BNX2_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0)
1108#define BNX2_NVM_READ_NVM_READ_VALUE_SO (16L<<0)
1109#define BNX2_NVM_READ_NVM_READ_VALUE_SI (32L<<0)
1110
1111#define BNX2_NVM_CFG1 0x00006414
1112#define BNX2_NVM_CFG1_FLASH_MODE (1L<<0)
1113#define BNX2_NVM_CFG1_BUFFER_MODE (1L<<1)
1114#define BNX2_NVM_CFG1_PASS_MODE (1L<<2)
1115#define BNX2_NVM_CFG1_BITBANG_MODE (1L<<3)
1116#define BNX2_NVM_CFG1_STATUS_BIT (0x7L<<4)
1117#define BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4)
1118#define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4)
1119#define BNX2_NVM_CFG1_SPI_CLK_DIV (0xfL<<7)
1120#define BNX2_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11)
1121#define BNX2_NVM_CFG1_PROTECT_MODE (1L<<24)
1122#define BNX2_NVM_CFG1_FLASH_SIZE (1L<<25)
1123#define BNX2_NVM_CFG1_COMPAT_BYPASSS (1L<<31)
1124
1125#define BNX2_NVM_CFG2 0x00006418
1126#define BNX2_NVM_CFG2_ERASE_CMD (0xffL<<0)
1127#define BNX2_NVM_CFG2_DUMMY (0xffL<<8)
1128#define BNX2_NVM_CFG2_STATUS_CMD (0xffL<<16)
1129
1130#define BNX2_NVM_CFG3 0x0000641c
1131#define BNX2_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0)
1132#define BNX2_NVM_CFG3_WRITE_CMD (0xffL<<8)
1133#define BNX2_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16)
1134#define BNX2_NVM_CFG3_READ_CMD (0xffL<<24)
1135
1136#define BNX2_NVM_SW_ARB 0x00006420
1137#define BNX2_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0)
1138#define BNX2_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
1139#define BNX2_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2)
1140#define BNX2_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3)
1141#define BNX2_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4)
1142#define BNX2_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
1143#define BNX2_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6)
1144#define BNX2_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7)
1145#define BNX2_NVM_SW_ARB_ARB_ARB0 (1L<<8)
1146#define BNX2_NVM_SW_ARB_ARB_ARB1 (1L<<9)
1147#define BNX2_NVM_SW_ARB_ARB_ARB2 (1L<<10)
1148#define BNX2_NVM_SW_ARB_ARB_ARB3 (1L<<11)
1149#define BNX2_NVM_SW_ARB_REQ0 (1L<<12)
1150#define BNX2_NVM_SW_ARB_REQ1 (1L<<13)
1151#define BNX2_NVM_SW_ARB_REQ2 (1L<<14)
1152#define BNX2_NVM_SW_ARB_REQ3 (1L<<15)
1153
1154#define BNX2_NVM_ACCESS_ENABLE 0x00006424
1155#define BNX2_NVM_ACCESS_ENABLE_EN (1L<<0)
1156#define BNX2_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
1157
1158#define BNX2_NVM_WRITE1 0x00006428
1159#define BNX2_NVM_WRITE1_WREN_CMD (0xffL<<0)
1160#define BNX2_NVM_WRITE1_WRDI_CMD (0xffL<<8)
1161#define BNX2_NVM_WRITE1_SR_DATA (0xffL<<16)
1162
1163
1164
1165/*
1166 * dma_reg definition
1167 * offset: 0xc00
1168 */
1169#define BNX2_DMA_COMMAND 0x00000c00
1170#define BNX2_DMA_COMMAND_ENABLE (1L<<0)
1171
1172#define BNX2_DMA_STATUS 0x00000c04
1173#define BNX2_DMA_STATUS_PAR_ERROR_STATE (1L<<0)
1174#define BNX2_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16)
1175#define BNX2_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17)
1176#define BNX2_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18)
1177#define BNX2_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19)
1178#define BNX2_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20)
1179#define BNX2_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21)
1180#define BNX2_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22)
1181#define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23)
1182#define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24)
1183#define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25)
1184
1185#define BNX2_DMA_CONFIG 0x00000c08
1186#define BNX2_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0)
1187#define BNX2_DMA_CONFIG_DATA_WORD_SWAP (1L<<1)
1188#define BNX2_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4)
1189#define BNX2_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5)
1190#define BNX2_DMA_CONFIG_ONE_DMA (1L<<6)
1191#define BNX2_DMA_CONFIG_CNTL_TWO_DMA (1L<<7)
1192#define BNX2_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8)
1193#define BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10)
1194#define BNX2_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11)
1195#define BNX2_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12)
1196#define BNX2_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16)
1197#define BNX2_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20)
1198#define BNX2_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23)
1199#define BNX2_DMA_CONFIG_BIG_SIZE (0xfL<<24)
1200#define BNX2_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24)
1201#define BNX2_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24)
1202#define BNX2_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24)
1203#define BNX2_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24)
1204#define BNX2_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24)
1205
1206#define BNX2_DMA_BLACKOUT 0x00000c0c
1207#define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0)
1208#define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8)
1209#define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16)
1210
1211#define BNX2_DMA_RCHAN_STAT 0x00000c30
1212#define BNX2_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0)
1213#define BNX2_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3)
1214#define BNX2_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4)
1215#define BNX2_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7)
1216#define BNX2_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8)
1217#define BNX2_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11)
1218#define BNX2_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12)
1219#define BNX2_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15)
1220#define BNX2_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16)
1221#define BNX2_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19)
1222#define BNX2_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20)
1223#define BNX2_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23)
1224#define BNX2_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24)
1225#define BNX2_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27)
1226#define BNX2_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28)
1227#define BNX2_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31)
1228
1229#define BNX2_DMA_WCHAN_STAT 0x00000c34
1230#define BNX2_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0)
1231#define BNX2_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3)
1232#define BNX2_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4)
1233#define BNX2_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7)
1234#define BNX2_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8)
1235#define BNX2_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11)
1236#define BNX2_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12)
1237#define BNX2_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15)
1238#define BNX2_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16)
1239#define BNX2_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19)
1240#define BNX2_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20)
1241#define BNX2_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23)
1242#define BNX2_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24)
1243#define BNX2_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27)
1244#define BNX2_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28)
1245#define BNX2_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31)
1246
1247#define BNX2_DMA_RCHAN_ASSIGNMENT 0x00000c38
1248#define BNX2_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0)
1249#define BNX2_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4)
1250#define BNX2_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8)
1251#define BNX2_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12)
1252#define BNX2_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16)
1253#define BNX2_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20)
1254#define BNX2_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24)
1255#define BNX2_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28)
1256
1257#define BNX2_DMA_WCHAN_ASSIGNMENT 0x00000c3c
1258#define BNX2_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0)
1259#define BNX2_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4)
1260#define BNX2_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8)
1261#define BNX2_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12)
1262#define BNX2_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16)
1263#define BNX2_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20)
1264#define BNX2_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24)
1265#define BNX2_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28)
1266
1267#define BNX2_DMA_RCHAN_STAT_00 0x00000c40
1268#define BNX2_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0)
1269
1270#define BNX2_DMA_RCHAN_STAT_01 0x00000c44
1271#define BNX2_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0)
1272
1273#define BNX2_DMA_RCHAN_STAT_02 0x00000c48
1274#define BNX2_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0)
1275#define BNX2_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16)
1276#define BNX2_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17)
1277#define BNX2_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18)
1278
1279#define BNX2_DMA_RCHAN_STAT_10 0x00000c4c
1280#define BNX2_DMA_RCHAN_STAT_11 0x00000c50
1281#define BNX2_DMA_RCHAN_STAT_12 0x00000c54
1282#define BNX2_DMA_RCHAN_STAT_20 0x00000c58
1283#define BNX2_DMA_RCHAN_STAT_21 0x00000c5c
1284#define BNX2_DMA_RCHAN_STAT_22 0x00000c60
1285#define BNX2_DMA_RCHAN_STAT_30 0x00000c64
1286#define BNX2_DMA_RCHAN_STAT_31 0x00000c68
1287#define BNX2_DMA_RCHAN_STAT_32 0x00000c6c
1288#define BNX2_DMA_RCHAN_STAT_40 0x00000c70
1289#define BNX2_DMA_RCHAN_STAT_41 0x00000c74
1290#define BNX2_DMA_RCHAN_STAT_42 0x00000c78
1291#define BNX2_DMA_RCHAN_STAT_50 0x00000c7c
1292#define BNX2_DMA_RCHAN_STAT_51 0x00000c80
1293#define BNX2_DMA_RCHAN_STAT_52 0x00000c84
1294#define BNX2_DMA_RCHAN_STAT_60 0x00000c88
1295#define BNX2_DMA_RCHAN_STAT_61 0x00000c8c
1296#define BNX2_DMA_RCHAN_STAT_62 0x00000c90
1297#define BNX2_DMA_RCHAN_STAT_70 0x00000c94
1298#define BNX2_DMA_RCHAN_STAT_71 0x00000c98
1299#define BNX2_DMA_RCHAN_STAT_72 0x00000c9c
1300#define BNX2_DMA_WCHAN_STAT_00 0x00000ca0
1301#define BNX2_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0)
1302
1303#define BNX2_DMA_WCHAN_STAT_01 0x00000ca4
1304#define BNX2_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0)
1305
1306#define BNX2_DMA_WCHAN_STAT_02 0x00000ca8
1307#define BNX2_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0)
1308#define BNX2_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16)
1309#define BNX2_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17)
1310#define BNX2_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18)
1311
1312#define BNX2_DMA_WCHAN_STAT_10 0x00000cac
1313#define BNX2_DMA_WCHAN_STAT_11 0x00000cb0
1314#define BNX2_DMA_WCHAN_STAT_12 0x00000cb4
1315#define BNX2_DMA_WCHAN_STAT_20 0x00000cb8
1316#define BNX2_DMA_WCHAN_STAT_21 0x00000cbc
1317#define BNX2_DMA_WCHAN_STAT_22 0x00000cc0
1318#define BNX2_DMA_WCHAN_STAT_30 0x00000cc4
1319#define BNX2_DMA_WCHAN_STAT_31 0x00000cc8
1320#define BNX2_DMA_WCHAN_STAT_32 0x00000ccc
1321#define BNX2_DMA_WCHAN_STAT_40 0x00000cd0
1322#define BNX2_DMA_WCHAN_STAT_41 0x00000cd4
1323#define BNX2_DMA_WCHAN_STAT_42 0x00000cd8
1324#define BNX2_DMA_WCHAN_STAT_50 0x00000cdc
1325#define BNX2_DMA_WCHAN_STAT_51 0x00000ce0
1326#define BNX2_DMA_WCHAN_STAT_52 0x00000ce4
1327#define BNX2_DMA_WCHAN_STAT_60 0x00000ce8
1328#define BNX2_DMA_WCHAN_STAT_61 0x00000cec
1329#define BNX2_DMA_WCHAN_STAT_62 0x00000cf0
1330#define BNX2_DMA_WCHAN_STAT_70 0x00000cf4
1331#define BNX2_DMA_WCHAN_STAT_71 0x00000cf8
1332#define BNX2_DMA_WCHAN_STAT_72 0x00000cfc
1333#define BNX2_DMA_ARB_STAT_00 0x00000d00
1334#define BNX2_DMA_ARB_STAT_00_MASTER (0xffffL<<0)
1335#define BNX2_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16)
1336#define BNX2_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24)
1337
1338#define BNX2_DMA_ARB_STAT_01 0x00000d04
1339#define BNX2_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0)
1340#define BNX2_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4)
1341#define BNX2_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8)
1342#define BNX2_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12)
1343#define BNX2_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16)
1344#define BNX2_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20)
1345#define BNX2_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24)
1346#define BNX2_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28)
1347
1348#define BNX2_DMA_FUSE_CTRL0_CMD 0x00000f00
1349#define BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0)
1350#define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1)
1351#define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2)
1352#define BNX2_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3)
1353#define BNX2_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8)
1354
1355#define BNX2_DMA_FUSE_CTRL0_DATA 0x00000f04
1356#define BNX2_DMA_FUSE_CTRL1_CMD 0x00000f08
1357#define BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0)
1358#define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1)
1359#define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2)
1360#define BNX2_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3)
1361#define BNX2_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8)
1362
1363#define BNX2_DMA_FUSE_CTRL1_DATA 0x00000f0c
1364#define BNX2_DMA_FUSE_CTRL2_CMD 0x00000f10
1365#define BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0)
1366#define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1)
1367#define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2)
1368#define BNX2_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3)
1369#define BNX2_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8)
1370
1371#define BNX2_DMA_FUSE_CTRL2_DATA 0x00000f14
1372
1373
1374/*
1375 * context_reg definition
1376 * offset: 0x1000
1377 */
1378#define BNX2_CTX_COMMAND 0x00001000
1379#define BNX2_CTX_COMMAND_ENABLED (1L<<0)
1380
1381#define BNX2_CTX_STATUS 0x00001004
1382#define BNX2_CTX_STATUS_LOCK_WAIT (1L<<0)
1383#define BNX2_CTX_STATUS_READ_STAT (1L<<16)
1384#define BNX2_CTX_STATUS_WRITE_STAT (1L<<17)
1385#define BNX2_CTX_STATUS_ACC_STALL_STAT (1L<<18)
1386#define BNX2_CTX_STATUS_LOCK_STALL_STAT (1L<<19)
1387
1388#define BNX2_CTX_VIRT_ADDR 0x00001008
1389#define BNX2_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6)
1390
1391#define BNX2_CTX_PAGE_TBL 0x0000100c
1392#define BNX2_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6)
1393
1394#define BNX2_CTX_DATA_ADR 0x00001010
1395#define BNX2_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2)
1396
1397#define BNX2_CTX_DATA 0x00001014
1398#define BNX2_CTX_LOCK 0x00001018
1399#define BNX2_CTX_LOCK_TYPE (0x7L<<0)
1400#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0)
1401#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0)
1402#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0)
1403#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0)
1404#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0)
1405#define BNX2_CTX_LOCK_CID_VALUE (0x3fffL<<7)
1406#define BNX2_CTX_LOCK_GRANTED (1L<<26)
1407#define BNX2_CTX_LOCK_MODE (0x7L<<27)
1408#define BNX2_CTX_LOCK_MODE_UNLOCK (0x0L<<27)
1409#define BNX2_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27)
1410#define BNX2_CTX_LOCK_MODE_SURE (0x2L<<27)
1411#define BNX2_CTX_LOCK_STATUS (1L<<30)
1412#define BNX2_CTX_LOCK_REQ (1L<<31)
1413
1414#define BNX2_CTX_ACCESS_STATUS 0x00001040
1415#define BNX2_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0)
1416#define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10)
1417#define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12)
1418#define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14)
1419#define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17)
1420
1421#define BNX2_CTX_DBG_LOCK_STATUS 0x00001044
1422#define BNX2_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0)
1423#define BNX2_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22)
1424
1425#define BNX2_CTX_CHNL_LOCK_STATUS_0 0x00001080
1426#define BNX2_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0)
1427#define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14)
1428#define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16)
1429
1430#define BNX2_CTX_CHNL_LOCK_STATUS_1 0x00001084
1431#define BNX2_CTX_CHNL_LOCK_STATUS_2 0x00001088
1432#define BNX2_CTX_CHNL_LOCK_STATUS_3 0x0000108c
1433#define BNX2_CTX_CHNL_LOCK_STATUS_4 0x00001090
1434#define BNX2_CTX_CHNL_LOCK_STATUS_5 0x00001094
1435#define BNX2_CTX_CHNL_LOCK_STATUS_6 0x00001098
1436#define BNX2_CTX_CHNL_LOCK_STATUS_7 0x0000109c
1437#define BNX2_CTX_CHNL_LOCK_STATUS_8 0x000010a0
1438
1439
1440/*
1441 * emac_reg definition
1442 * offset: 0x1400
1443 */
1444#define BNX2_EMAC_MODE 0x00001400
1445#define BNX2_EMAC_MODE_RESET (1L<<0)
1446#define BNX2_EMAC_MODE_HALF_DUPLEX (1L<<1)
1447#define BNX2_EMAC_MODE_PORT (0x3L<<2)
1448#define BNX2_EMAC_MODE_PORT_NONE (0L<<2)
1449#define BNX2_EMAC_MODE_PORT_MII (1L<<2)
1450#define BNX2_EMAC_MODE_PORT_GMII (2L<<2)
1451#define BNX2_EMAC_MODE_PORT_UNDEF (3L<<2)
1452#define BNX2_EMAC_MODE_MAC_LOOP (1L<<4)
1453#define BNX2_EMAC_MODE_TAGGED_MAC_CTL (1L<<7)
1454#define BNX2_EMAC_MODE_TX_BURST (1L<<8)
1455#define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9)
1456#define BNX2_EMAC_MODE_EXT_LINK_POL (1L<<10)
1457#define BNX2_EMAC_MODE_FORCE_LINK (1L<<11)
1458#define BNX2_EMAC_MODE_MPKT (1L<<18)
1459#define BNX2_EMAC_MODE_MPKT_RCVD (1L<<19)
1460#define BNX2_EMAC_MODE_ACPI_RCVD (1L<<20)
1461
1462#define BNX2_EMAC_STATUS 0x00001404
1463#define BNX2_EMAC_STATUS_LINK (1L<<11)
1464#define BNX2_EMAC_STATUS_LINK_CHANGE (1L<<12)
1465#define BNX2_EMAC_STATUS_MI_COMPLETE (1L<<22)
1466#define BNX2_EMAC_STATUS_MI_INT (1L<<23)
1467#define BNX2_EMAC_STATUS_AP_ERROR (1L<<24)
1468#define BNX2_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31)
1469
1470#define BNX2_EMAC_ATTENTION_ENA 0x00001408
1471#define BNX2_EMAC_ATTENTION_ENA_LINK (1L<<11)
1472#define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22)
1473#define BNX2_EMAC_ATTENTION_ENA_MI_INT (1L<<23)
1474#define BNX2_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24)
1475
1476#define BNX2_EMAC_LED 0x0000140c
1477#define BNX2_EMAC_LED_OVERRIDE (1L<<0)
1478#define BNX2_EMAC_LED_1000MB_OVERRIDE (1L<<1)
1479#define BNX2_EMAC_LED_100MB_OVERRIDE (1L<<2)
1480#define BNX2_EMAC_LED_10MB_OVERRIDE (1L<<3)
1481#define BNX2_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4)
1482#define BNX2_EMAC_LED_BLNK_TRAFFIC (1L<<5)
1483#define BNX2_EMAC_LED_TRAFFIC (1L<<6)
1484#define BNX2_EMAC_LED_1000MB (1L<<7)
1485#define BNX2_EMAC_LED_100MB (1L<<8)
1486#define BNX2_EMAC_LED_10MB (1L<<9)
1487#define BNX2_EMAC_LED_TRAFFIC_STAT (1L<<10)
1488#define BNX2_EMAC_LED_BLNK_RATE (0xfffL<<19)
1489#define BNX2_EMAC_LED_BLNK_RATE_ENA (1L<<31)
1490
1491#define BNX2_EMAC_MAC_MATCH0 0x00001410
1492#define BNX2_EMAC_MAC_MATCH1 0x00001414
1493#define BNX2_EMAC_MAC_MATCH2 0x00001418
1494#define BNX2_EMAC_MAC_MATCH3 0x0000141c
1495#define BNX2_EMAC_MAC_MATCH4 0x00001420
1496#define BNX2_EMAC_MAC_MATCH5 0x00001424
1497#define BNX2_EMAC_MAC_MATCH6 0x00001428
1498#define BNX2_EMAC_MAC_MATCH7 0x0000142c
1499#define BNX2_EMAC_MAC_MATCH8 0x00001430
1500#define BNX2_EMAC_MAC_MATCH9 0x00001434
1501#define BNX2_EMAC_MAC_MATCH10 0x00001438
1502#define BNX2_EMAC_MAC_MATCH11 0x0000143c
1503#define BNX2_EMAC_MAC_MATCH12 0x00001440
1504#define BNX2_EMAC_MAC_MATCH13 0x00001444
1505#define BNX2_EMAC_MAC_MATCH14 0x00001448
1506#define BNX2_EMAC_MAC_MATCH15 0x0000144c
1507#define BNX2_EMAC_MAC_MATCH16 0x00001450
1508#define BNX2_EMAC_MAC_MATCH17 0x00001454
1509#define BNX2_EMAC_MAC_MATCH18 0x00001458
1510#define BNX2_EMAC_MAC_MATCH19 0x0000145c
1511#define BNX2_EMAC_MAC_MATCH20 0x00001460
1512#define BNX2_EMAC_MAC_MATCH21 0x00001464
1513#define BNX2_EMAC_MAC_MATCH22 0x00001468
1514#define BNX2_EMAC_MAC_MATCH23 0x0000146c
1515#define BNX2_EMAC_MAC_MATCH24 0x00001470
1516#define BNX2_EMAC_MAC_MATCH25 0x00001474
1517#define BNX2_EMAC_MAC_MATCH26 0x00001478
1518#define BNX2_EMAC_MAC_MATCH27 0x0000147c
1519#define BNX2_EMAC_MAC_MATCH28 0x00001480
1520#define BNX2_EMAC_MAC_MATCH29 0x00001484
1521#define BNX2_EMAC_MAC_MATCH30 0x00001488
1522#define BNX2_EMAC_MAC_MATCH31 0x0000148c
1523#define BNX2_EMAC_BACKOFF_SEED 0x00001498
1524#define BNX2_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0)
1525
1526#define BNX2_EMAC_RX_MTU_SIZE 0x0000149c
1527#define BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0)
1528#define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
1529
1530#define BNX2_EMAC_SERDES_CNTL 0x000014a4
1531#define BNX2_EMAC_SERDES_CNTL_RXR (0x7L<<0)
1532#define BNX2_EMAC_SERDES_CNTL_RXG (0x3L<<3)
1533#define BNX2_EMAC_SERDES_CNTL_RXCKSEL (1L<<6)
1534#define BNX2_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7)
1535#define BNX2_EMAC_SERDES_CNTL_BGMAX (1L<<10)
1536#define BNX2_EMAC_SERDES_CNTL_BGMIN (1L<<11)
1537#define BNX2_EMAC_SERDES_CNTL_TXMODE (1L<<12)
1538#define BNX2_EMAC_SERDES_CNTL_TXEDGE (1L<<13)
1539#define BNX2_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14)
1540#define BNX2_EMAC_SERDES_CNTL_PLLTEST (1L<<15)
1541#define BNX2_EMAC_SERDES_CNTL_CDET_EN (1L<<16)
1542#define BNX2_EMAC_SERDES_CNTL_TBI_LBK (1L<<17)
1543#define BNX2_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18)
1544#define BNX2_EMAC_SERDES_CNTL_REV_PHASE (1L<<19)
1545#define BNX2_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20)
1546#define BNX2_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22)
1547
1548#define BNX2_EMAC_SERDES_STATUS 0x000014a8
1549#define BNX2_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0)
1550#define BNX2_EMAC_SERDES_STATUS_COMMA_DET (1L<<8)
1551
1552#define BNX2_EMAC_MDIO_COMM 0x000014ac
1553#define BNX2_EMAC_MDIO_COMM_DATA (0xffffL<<0)
1554#define BNX2_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16)
1555#define BNX2_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21)
1556#define BNX2_EMAC_MDIO_COMM_COMMAND (0x3L<<26)
1557#define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26)
1558#define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26)
1559#define BNX2_EMAC_MDIO_COMM_COMMAND_READ (2L<<26)
1560#define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26)
1561#define BNX2_EMAC_MDIO_COMM_FAIL (1L<<28)
1562#define BNX2_EMAC_MDIO_COMM_START_BUSY (1L<<29)
1563#define BNX2_EMAC_MDIO_COMM_DISEXT (1L<<30)
1564
1565#define BNX2_EMAC_MDIO_STATUS 0x000014b0
1566#define BNX2_EMAC_MDIO_STATUS_LINK (1L<<0)
1567#define BNX2_EMAC_MDIO_STATUS_10MB (1L<<1)
1568
1569#define BNX2_EMAC_MDIO_MODE 0x000014b4
1570#define BNX2_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1)
1571#define BNX2_EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
1572#define BNX2_EMAC_MDIO_MODE_BIT_BANG (1L<<8)
1573#define BNX2_EMAC_MDIO_MODE_MDIO (1L<<9)
1574#define BNX2_EMAC_MDIO_MODE_MDIO_OE (1L<<10)
1575#define BNX2_EMAC_MDIO_MODE_MDC (1L<<11)
1576#define BNX2_EMAC_MDIO_MODE_MDINT (1L<<12)
1577#define BNX2_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16)
1578
1579#define BNX2_EMAC_MDIO_AUTO_STATUS 0x000014b8
1580#define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0)
1581
1582#define BNX2_EMAC_TX_MODE 0x000014bc
1583#define BNX2_EMAC_TX_MODE_RESET (1L<<0)
1584#define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
1585#define BNX2_EMAC_TX_MODE_FLOW_EN (1L<<4)
1586#define BNX2_EMAC_TX_MODE_BIG_BACKOFF (1L<<5)
1587#define BNX2_EMAC_TX_MODE_LONG_PAUSE (1L<<6)
1588#define BNX2_EMAC_TX_MODE_LINK_AWARE (1L<<7)
1589
1590#define BNX2_EMAC_TX_STATUS 0x000014c0
1591#define BNX2_EMAC_TX_STATUS_XOFFED (1L<<0)
1592#define BNX2_EMAC_TX_STATUS_XOFF_SENT (1L<<1)
1593#define BNX2_EMAC_TX_STATUS_XON_SENT (1L<<2)
1594#define BNX2_EMAC_TX_STATUS_LINK_UP (1L<<3)
1595#define BNX2_EMAC_TX_STATUS_UNDERRUN (1L<<4)
1596
1597#define BNX2_EMAC_TX_LENGTHS 0x000014c4
1598#define BNX2_EMAC_TX_LENGTHS_SLOT (0xffL<<0)
1599#define BNX2_EMAC_TX_LENGTHS_IPG (0xfL<<8)
1600#define BNX2_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12)
1601
1602#define BNX2_EMAC_RX_MODE 0x000014c8
1603#define BNX2_EMAC_RX_MODE_RESET (1L<<0)
1604#define BNX2_EMAC_RX_MODE_FLOW_EN (1L<<2)
1605#define BNX2_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
1606#define BNX2_EMAC_RX_MODE_KEEP_PAUSE (1L<<4)
1607#define BNX2_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5)
1608#define BNX2_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6)
1609#define BNX2_EMAC_RX_MODE_LLC_CHK (1L<<7)
1610#define BNX2_EMAC_RX_MODE_PROMISCUOUS (1L<<8)
1611#define BNX2_EMAC_RX_MODE_NO_CRC_CHK (1L<<9)
1612#define BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
1613#define BNX2_EMAC_RX_MODE_FILT_BROADCAST (1L<<11)
1614#define BNX2_EMAC_RX_MODE_SORT_MODE (1L<<12)
1615
1616#define BNX2_EMAC_RX_STATUS 0x000014cc
1617#define BNX2_EMAC_RX_STATUS_FFED (1L<<0)
1618#define BNX2_EMAC_RX_STATUS_FF_RECEIVED (1L<<1)
1619#define BNX2_EMAC_RX_STATUS_N_RECEIVED (1L<<2)
1620
1621#define BNX2_EMAC_MULTICAST_HASH0 0x000014d0
1622#define BNX2_EMAC_MULTICAST_HASH1 0x000014d4
1623#define BNX2_EMAC_MULTICAST_HASH2 0x000014d8
1624#define BNX2_EMAC_MULTICAST_HASH3 0x000014dc
1625#define BNX2_EMAC_MULTICAST_HASH4 0x000014e0
1626#define BNX2_EMAC_MULTICAST_HASH5 0x000014e4
1627#define BNX2_EMAC_MULTICAST_HASH6 0x000014e8
1628#define BNX2_EMAC_MULTICAST_HASH7 0x000014ec
1629#define BNX2_EMAC_RX_STAT_IFHCINOCTETS 0x00001500
1630#define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504
1631#define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508
1632#define BNX2_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c
1633#define BNX2_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510
1634#define BNX2_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514
1635#define BNX2_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518
1636#define BNX2_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c
1637#define BNX2_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520
1638#define BNX2_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524
1639#define BNX2_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528
1640#define BNX2_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c
1641#define BNX2_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530
1642#define BNX2_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534
1643#define BNX2_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538
1644#define BNX2_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c
1645#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540
1646#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544
1647#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548
1648#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c
1649#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550
1650#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554
1651#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558
1652#define BNX2_EMAC_RXMAC_DEBUG0 0x0000155c
1653#define BNX2_EMAC_RXMAC_DEBUG1 0x00001560
1654#define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0)
1655#define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1)
1656#define BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2)
1657#define BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3)
1658#define BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4)
1659#define BNX2_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5)
1660#define BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6)
1661#define BNX2_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7)
1662#define BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23)
1663
1664#define BNX2_EMAC_RXMAC_DEBUG2 0x00001564
1665#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0)
1666#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0)
1667#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0)
1668#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0)
1669#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0)
1670#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0)
1671#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0)
1672#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0)
1673#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0)
1674#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3)
1675#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3)
1676#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3)
1677#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3)
1678#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3)
1679#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3)
1680#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3)
1681#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3)
1682#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3)
1683#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3)
1684#define BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7)
1685#define BNX2_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15)
1686#define BNX2_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16)
1687#define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18)
1688#define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18)
1689#define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18)
1690#define BNX2_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19)
1691#define BNX2_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23)
1692
1693#define BNX2_EMAC_RXMAC_DEBUG3 0x00001568
1694#define BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0)
1695#define BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16)
1696
1697#define BNX2_EMAC_RXMAC_DEBUG4 0x0000156c
1698#define BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0)
1699#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16)
1700#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16)
1701#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16)
1702#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16)
1703#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16)
1704#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16)
1705#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16)
1706#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16)
1707#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16)
1708#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16)
1709#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16)
1710#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16)
1711#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16)
1712#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16)
1713#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16)
1714#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16)
1715#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16)
1716#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16)
1717#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16)
1718#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16)
1719#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16)
1720#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16)
1721#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16)
1722#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16)
1723#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16)
1724#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16)
1725#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16)
1726#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16)
1727#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16)
1728#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16)
1729#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16)
1730#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16)
1731#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16)
1732#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16)
1733#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16)
1734#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16)
1735#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16)
1736#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16)
1737#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16)
1738#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16)
1739#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16)
1740#define BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22)
1741#define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23)
1742#define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24)
1743#define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25)
1744#define BNX2_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26)
1745#define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27)
1746#define BNX2_EMAC_RXMAC_DEBUG4_START (1L<<28)
1747
1748#define BNX2_EMAC_RXMAC_DEBUG5 0x00001570
1749#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0)
1750#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0)
1751#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0)
1752#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0)
1753#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0)
1754#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0)
1755#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0)
1756#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0)
1757#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4)
1758#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4)
1759#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4)
1760#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4)
1761#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4)
1762#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4)
1763#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4)
1764#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4)
1765#define BNX2_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7)
1766#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8)
1767#define BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11)
1768#define BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12)
1769#define BNX2_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13)
1770#define BNX2_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14)
1771#define BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15)
1772#define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16)
1773#define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19)
1774#define BNX2_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20)
1775
1776#define BNX2_EMAC_RX_STAT_AC0 0x00001580
1777#define BNX2_EMAC_RX_STAT_AC1 0x00001584
1778#define BNX2_EMAC_RX_STAT_AC2 0x00001588
1779#define BNX2_EMAC_RX_STAT_AC3 0x0000158c
1780#define BNX2_EMAC_RX_STAT_AC4 0x00001590
1781#define BNX2_EMAC_RX_STAT_AC5 0x00001594
1782#define BNX2_EMAC_RX_STAT_AC6 0x00001598
1783#define BNX2_EMAC_RX_STAT_AC7 0x0000159c
1784#define BNX2_EMAC_RX_STAT_AC8 0x000015a0
1785#define BNX2_EMAC_RX_STAT_AC9 0x000015a4
1786#define BNX2_EMAC_RX_STAT_AC10 0x000015a8
1787#define BNX2_EMAC_RX_STAT_AC11 0x000015ac
1788#define BNX2_EMAC_RX_STAT_AC12 0x000015b0
1789#define BNX2_EMAC_RX_STAT_AC13 0x000015b4
1790#define BNX2_EMAC_RX_STAT_AC14 0x000015b8
1791#define BNX2_EMAC_RX_STAT_AC15 0x000015bc
1792#define BNX2_EMAC_RX_STAT_AC16 0x000015c0
1793#define BNX2_EMAC_RX_STAT_AC17 0x000015c4
1794#define BNX2_EMAC_RX_STAT_AC18 0x000015c8
1795#define BNX2_EMAC_RX_STAT_AC19 0x000015cc
1796#define BNX2_EMAC_RX_STAT_AC20 0x000015d0
1797#define BNX2_EMAC_RX_STAT_AC21 0x000015d4
1798#define BNX2_EMAC_RX_STAT_AC22 0x000015d8
1799#define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc
1800#define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600
1801#define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604
1802#define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608
1803#define BNX2_EMAC_TX_STAT_OUTXONSENT 0x0000160c
1804#define BNX2_EMAC_TX_STAT_OUTXOFFSENT 0x00001610
1805#define BNX2_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614
1806#define BNX2_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618
1807#define BNX2_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c
1808#define BNX2_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620
1809#define BNX2_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624
1810#define BNX2_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628
1811#define BNX2_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c
1812#define BNX2_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630
1813#define BNX2_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634
1814#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638
1815#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c
1816#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640
1817#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644
1818#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648
1819#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c
1820#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650
1821#define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654
1822#define BNX2_EMAC_TXMAC_DEBUG0 0x00001658
1823#define BNX2_EMAC_TXMAC_DEBUG1 0x0000165c
1824#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0)
1825#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0)
1826#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0)
1827#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0)
1828#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0)
1829#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0)
1830#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0)
1831#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0)
1832#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0)
1833#define BNX2_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4)
1834#define BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5)
1835#define BNX2_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6)
1836#define BNX2_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10)
1837#define BNX2_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11)
1838#define BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12)
1839#define BNX2_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13)
1840#define BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14)
1841#define BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15)
1842#define BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19)
1843
1844#define BNX2_EMAC_TXMAC_DEBUG2 0x00001660
1845#define BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0)
1846#define BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10)
1847#define BNX2_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26)
1848#define BNX2_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31)
1849
1850#define BNX2_EMAC_TXMAC_DEBUG3 0x00001664
1851#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0)
1852#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0)
1853#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0)
1854#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0)
1855#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0)
1856#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0)
1857#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0)
1858#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0)
1859#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0)
1860#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0)
1861#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0)
1862#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0)
1863#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0)
1864#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0)
1865#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0)
1866#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0)
1867#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4)
1868#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4)
1869#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4)
1870#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4)
1871#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4)
1872#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4)
1873#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4)
1874#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4)
1875#define BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7)
1876#define BNX2_EMAC_TXMAC_DEBUG3_XOFF (1L<<8)
1877#define BNX2_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9)
1878#define BNX2_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13)
1879
1880#define BNX2_EMAC_TXMAC_DEBUG4 0x00001668
1881#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0)
1882#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16)
1883#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16)
1884#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16)
1885#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16)
1886#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16)
1887#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16)
1888#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16)
1889#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16)
1890#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16)
1891#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16)
1892#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16)
1893#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16)
1894#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16)
1895#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16)
1896#define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20)
1897#define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21)
1898#define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22)
1899#define BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23)
1900#define BNX2_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24)
1901#define BNX2_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25)
1902#define BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26)
1903#define BNX2_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27)
1904#define BNX2_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28)
1905#define BNX2_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29)
1906#define BNX2_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30)
1907#define BNX2_EMAC_TXMAC_DEBUG4_GO (1L<<31)
1908
1909#define BNX2_EMAC_TX_STAT_AC0 0x00001680
1910#define BNX2_EMAC_TX_STAT_AC1 0x00001684
1911#define BNX2_EMAC_TX_STAT_AC2 0x00001688
1912#define BNX2_EMAC_TX_STAT_AC3 0x0000168c
1913#define BNX2_EMAC_TX_STAT_AC4 0x00001690
1914#define BNX2_EMAC_TX_STAT_AC5 0x00001694
1915#define BNX2_EMAC_TX_STAT_AC6 0x00001698
1916#define BNX2_EMAC_TX_STAT_AC7 0x0000169c
1917#define BNX2_EMAC_TX_STAT_AC8 0x000016a0
1918#define BNX2_EMAC_TX_STAT_AC9 0x000016a4
1919#define BNX2_EMAC_TX_STAT_AC10 0x000016a8
1920#define BNX2_EMAC_TX_STAT_AC11 0x000016ac
1921#define BNX2_EMAC_TX_STAT_AC12 0x000016b0
1922#define BNX2_EMAC_TX_STAT_AC13 0x000016b4
1923#define BNX2_EMAC_TX_STAT_AC14 0x000016b8
1924#define BNX2_EMAC_TX_STAT_AC15 0x000016bc
1925#define BNX2_EMAC_TX_STAT_AC16 0x000016c0
1926#define BNX2_EMAC_TX_STAT_AC17 0x000016c4
1927#define BNX2_EMAC_TX_STAT_AC18 0x000016c8
1928#define BNX2_EMAC_TX_STAT_AC19 0x000016cc
1929#define BNX2_EMAC_TX_STAT_AC20 0x000016d0
1930#define BNX2_EMAC_TX_STAT_AC21 0x000016d4
1931#define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8
1932
1933
1934/*
1935 * rpm_reg definition
1936 * offset: 0x1800
1937 */
1938#define BNX2_RPM_COMMAND 0x00001800
1939#define BNX2_RPM_COMMAND_ENABLED (1L<<0)
1940#define BNX2_RPM_COMMAND_OVERRUN_ABORT (1L<<4)
1941
1942#define BNX2_RPM_STATUS 0x00001804
1943#define BNX2_RPM_STATUS_MBUF_WAIT (1L<<0)
1944#define BNX2_RPM_STATUS_FREE_WAIT (1L<<1)
1945
1946#define BNX2_RPM_CONFIG 0x00001808
1947#define BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0)
1948#define BNX2_RPM_CONFIG_ACPI_ENA (1L<<1)
1949#define BNX2_RPM_CONFIG_ACPI_KEEP (1L<<2)
1950#define BNX2_RPM_CONFIG_MP_KEEP (1L<<3)
1951#define BNX2_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4)
1952#define BNX2_RPM_CONFIG_IGNORE_VLAN (1L<<31)
1953
1954#define BNX2_RPM_VLAN_MATCH0 0x00001810
1955#define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0)
1956
1957#define BNX2_RPM_VLAN_MATCH1 0x00001814
1958#define BNX2_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0)
1959
1960#define BNX2_RPM_VLAN_MATCH2 0x00001818
1961#define BNX2_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0)
1962
1963#define BNX2_RPM_VLAN_MATCH3 0x0000181c
1964#define BNX2_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0)
1965
1966#define BNX2_RPM_SORT_USER0 0x00001820
1967#define BNX2_RPM_SORT_USER0_PM_EN (0xffffL<<0)
1968#define BNX2_RPM_SORT_USER0_BC_EN (1L<<16)
1969#define BNX2_RPM_SORT_USER0_MC_EN (1L<<17)
1970#define BNX2_RPM_SORT_USER0_MC_HSH_EN (1L<<18)
1971#define BNX2_RPM_SORT_USER0_PROM_EN (1L<<19)
1972#define BNX2_RPM_SORT_USER0_VLAN_EN (0xfL<<20)
1973#define BNX2_RPM_SORT_USER0_PROM_VLAN (1L<<24)
1974#define BNX2_RPM_SORT_USER0_ENA (1L<<31)
1975
1976#define BNX2_RPM_SORT_USER1 0x00001824
1977#define BNX2_RPM_SORT_USER1_PM_EN (0xffffL<<0)
1978#define BNX2_RPM_SORT_USER1_BC_EN (1L<<16)
1979#define BNX2_RPM_SORT_USER1_MC_EN (1L<<17)
1980#define BNX2_RPM_SORT_USER1_MC_HSH_EN (1L<<18)
1981#define BNX2_RPM_SORT_USER1_PROM_EN (1L<<19)
1982#define BNX2_RPM_SORT_USER1_VLAN_EN (0xfL<<20)
1983#define BNX2_RPM_SORT_USER1_PROM_VLAN (1L<<24)
1984#define BNX2_RPM_SORT_USER1_ENA (1L<<31)
1985
1986#define BNX2_RPM_SORT_USER2 0x00001828
1987#define BNX2_RPM_SORT_USER2_PM_EN (0xffffL<<0)
1988#define BNX2_RPM_SORT_USER2_BC_EN (1L<<16)
1989#define BNX2_RPM_SORT_USER2_MC_EN (1L<<17)
1990#define BNX2_RPM_SORT_USER2_MC_HSH_EN (1L<<18)
1991#define BNX2_RPM_SORT_USER2_PROM_EN (1L<<19)
1992#define BNX2_RPM_SORT_USER2_VLAN_EN (0xfL<<20)
1993#define BNX2_RPM_SORT_USER2_PROM_VLAN (1L<<24)
1994#define BNX2_RPM_SORT_USER2_ENA (1L<<31)
1995
1996#define BNX2_RPM_SORT_USER3 0x0000182c
1997#define BNX2_RPM_SORT_USER3_PM_EN (0xffffL<<0)
1998#define BNX2_RPM_SORT_USER3_BC_EN (1L<<16)
1999#define BNX2_RPM_SORT_USER3_MC_EN (1L<<17)
2000#define BNX2_RPM_SORT_USER3_MC_HSH_EN (1L<<18)
2001#define BNX2_RPM_SORT_USER3_PROM_EN (1L<<19)
2002#define BNX2_RPM_SORT_USER3_VLAN_EN (0xfL<<20)
2003#define BNX2_RPM_SORT_USER3_PROM_VLAN (1L<<24)
2004#define BNX2_RPM_SORT_USER3_ENA (1L<<31)
2005
2006#define BNX2_RPM_STAT_L2_FILTER_DISCARDS 0x00001840
2007#define BNX2_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844
2008#define BNX2_RPM_STAT_IFINFTQDISCARDS 0x00001848
2009#define BNX2_RPM_STAT_IFINMBUFDISCARD 0x0000184c
2010#define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850
2011#define BNX2_RPM_STAT_AC0 0x00001880
2012#define BNX2_RPM_STAT_AC1 0x00001884
2013#define BNX2_RPM_STAT_AC2 0x00001888
2014#define BNX2_RPM_STAT_AC3 0x0000188c
2015#define BNX2_RPM_STAT_AC4 0x00001890
2016#define BNX2_RPM_RC_CNTL_0 0x00001900
2017#define BNX2_RPM_RC_CNTL_0_OFFSET (0xffL<<0)
2018#define BNX2_RPM_RC_CNTL_0_CLASS (0x7L<<8)
2019#define BNX2_RPM_RC_CNTL_0_PRIORITY (1L<<11)
2020#define BNX2_RPM_RC_CNTL_0_P4 (1L<<12)
2021#define BNX2_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13)
2022#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13)
2023#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13)
2024#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13)
2025#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13)
2026#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13)
2027#define BNX2_RPM_RC_CNTL_0_COMP (0x3L<<16)
2028#define BNX2_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16)
2029#define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16)
2030#define BNX2_RPM_RC_CNTL_0_COMP_GREATER (2L<<16)
2031#define BNX2_RPM_RC_CNTL_0_COMP_LESS (3L<<16)
2032#define BNX2_RPM_RC_CNTL_0_SBIT (1L<<19)
2033#define BNX2_RPM_RC_CNTL_0_CMDSEL (0xfL<<20)
2034#define BNX2_RPM_RC_CNTL_0_MAP (1L<<24)
2035#define BNX2_RPM_RC_CNTL_0_DISCARD (1L<<25)
2036#define BNX2_RPM_RC_CNTL_0_MASK (1L<<26)
2037#define BNX2_RPM_RC_CNTL_0_P1 (1L<<27)
2038#define BNX2_RPM_RC_CNTL_0_P2 (1L<<28)
2039#define BNX2_RPM_RC_CNTL_0_P3 (1L<<29)
2040#define BNX2_RPM_RC_CNTL_0_NBIT (1L<<30)
2041
2042#define BNX2_RPM_RC_VALUE_MASK_0 0x00001904
2043#define BNX2_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0)
2044#define BNX2_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16)
2045
2046#define BNX2_RPM_RC_CNTL_1 0x00001908
2047#define BNX2_RPM_RC_CNTL_1_A (0x3ffffL<<0)
2048#define BNX2_RPM_RC_CNTL_1_B (0xfffL<<19)
2049
2050#define BNX2_RPM_RC_VALUE_MASK_1 0x0000190c
2051#define BNX2_RPM_RC_CNTL_2 0x00001910
2052#define BNX2_RPM_RC_CNTL_2_A (0x3ffffL<<0)
2053#define BNX2_RPM_RC_CNTL_2_B (0xfffL<<19)
2054
2055#define BNX2_RPM_RC_VALUE_MASK_2 0x00001914
2056#define BNX2_RPM_RC_CNTL_3 0x00001918
2057#define BNX2_RPM_RC_CNTL_3_A (0x3ffffL<<0)
2058#define BNX2_RPM_RC_CNTL_3_B (0xfffL<<19)
2059
2060#define BNX2_RPM_RC_VALUE_MASK_3 0x0000191c
2061#define BNX2_RPM_RC_CNTL_4 0x00001920
2062#define BNX2_RPM_RC_CNTL_4_A (0x3ffffL<<0)
2063#define BNX2_RPM_RC_CNTL_4_B (0xfffL<<19)
2064
2065#define BNX2_RPM_RC_VALUE_MASK_4 0x00001924
2066#define BNX2_RPM_RC_CNTL_5 0x00001928
2067#define BNX2_RPM_RC_CNTL_5_A (0x3ffffL<<0)
2068#define BNX2_RPM_RC_CNTL_5_B (0xfffL<<19)
2069
2070#define BNX2_RPM_RC_VALUE_MASK_5 0x0000192c
2071#define BNX2_RPM_RC_CNTL_6 0x00001930
2072#define BNX2_RPM_RC_CNTL_6_A (0x3ffffL<<0)
2073#define BNX2_RPM_RC_CNTL_6_B (0xfffL<<19)
2074
2075#define BNX2_RPM_RC_VALUE_MASK_6 0x00001934
2076#define BNX2_RPM_RC_CNTL_7 0x00001938
2077#define BNX2_RPM_RC_CNTL_7_A (0x3ffffL<<0)
2078#define BNX2_RPM_RC_CNTL_7_B (0xfffL<<19)
2079
2080#define BNX2_RPM_RC_VALUE_MASK_7 0x0000193c
2081#define BNX2_RPM_RC_CNTL_8 0x00001940
2082#define BNX2_RPM_RC_CNTL_8_A (0x3ffffL<<0)
2083#define BNX2_RPM_RC_CNTL_8_B (0xfffL<<19)
2084
2085#define BNX2_RPM_RC_VALUE_MASK_8 0x00001944
2086#define BNX2_RPM_RC_CNTL_9 0x00001948
2087#define BNX2_RPM_RC_CNTL_9_A (0x3ffffL<<0)
2088#define BNX2_RPM_RC_CNTL_9_B (0xfffL<<19)
2089
2090#define BNX2_RPM_RC_VALUE_MASK_9 0x0000194c
2091#define BNX2_RPM_RC_CNTL_10 0x00001950
2092#define BNX2_RPM_RC_CNTL_10_A (0x3ffffL<<0)
2093#define BNX2_RPM_RC_CNTL_10_B (0xfffL<<19)
2094
2095#define BNX2_RPM_RC_VALUE_MASK_10 0x00001954
2096#define BNX2_RPM_RC_CNTL_11 0x00001958
2097#define BNX2_RPM_RC_CNTL_11_A (0x3ffffL<<0)
2098#define BNX2_RPM_RC_CNTL_11_B (0xfffL<<19)
2099
2100#define BNX2_RPM_RC_VALUE_MASK_11 0x0000195c
2101#define BNX2_RPM_RC_CNTL_12 0x00001960
2102#define BNX2_RPM_RC_CNTL_12_A (0x3ffffL<<0)
2103#define BNX2_RPM_RC_CNTL_12_B (0xfffL<<19)
2104
2105#define BNX2_RPM_RC_VALUE_MASK_12 0x00001964
2106#define BNX2_RPM_RC_CNTL_13 0x00001968
2107#define BNX2_RPM_RC_CNTL_13_A (0x3ffffL<<0)
2108#define BNX2_RPM_RC_CNTL_13_B (0xfffL<<19)
2109
2110#define BNX2_RPM_RC_VALUE_MASK_13 0x0000196c
2111#define BNX2_RPM_RC_CNTL_14 0x00001970
2112#define BNX2_RPM_RC_CNTL_14_A (0x3ffffL<<0)
2113#define BNX2_RPM_RC_CNTL_14_B (0xfffL<<19)
2114
2115#define BNX2_RPM_RC_VALUE_MASK_14 0x00001974
2116#define BNX2_RPM_RC_CNTL_15 0x00001978
2117#define BNX2_RPM_RC_CNTL_15_A (0x3ffffL<<0)
2118#define BNX2_RPM_RC_CNTL_15_B (0xfffL<<19)
2119
2120#define BNX2_RPM_RC_VALUE_MASK_15 0x0000197c
2121#define BNX2_RPM_RC_CONFIG 0x00001980
2122#define BNX2_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0)
2123#define BNX2_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24)
2124
2125#define BNX2_RPM_DEBUG0 0x00001984
2126#define BNX2_RPM_DEBUG0_FM_BCNT (0xffffL<<0)
2127#define BNX2_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16)
2128#define BNX2_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17)
2129#define BNX2_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18)
2130#define BNX2_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19)
2131#define BNX2_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20)
2132#define BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21)
2133#define BNX2_RPM_DEBUG0_LLC_SNAP (1L<<22)
2134#define BNX2_RPM_DEBUG0_FM_STARTED (1L<<23)
2135#define BNX2_RPM_DEBUG0_DONE (1L<<24)
2136#define BNX2_RPM_DEBUG0_WAIT_4_DONE (1L<<25)
2137#define BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26)
2138#define BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27)
2139#define BNX2_RPM_DEBUG0_IGNORE_VLAN (1L<<28)
2140#define BNX2_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31)
2141
2142#define BNX2_RPM_DEBUG1 0x00001988
2143#define BNX2_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0)
2144#define BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0)
2145#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0)
2146#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0)
2147#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0)
2148#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0)
2149#define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0)
2150#define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0)
2151#define BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0)
2152#define BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0)
2153#define BNX2_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0)
2154#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0)
2155#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0)
2156#define BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0)
2157#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0)
2158#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0)
2159#define BNX2_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0)
2160#define BNX2_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16)
2161#define BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28)
2162#define BNX2_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29)
2163#define BNX2_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30)
2164#define BNX2_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31)
2165
2166#define BNX2_RPM_DEBUG2 0x0000198c
2167#define BNX2_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0)
2168#define BNX2_RPM_DEBUG2_IP_BCNT (0xffL<<16)
2169#define BNX2_RPM_DEBUG2_THIS_CMD_M4 (1L<<24)
2170#define BNX2_RPM_DEBUG2_THIS_CMD_M3 (1L<<25)
2171#define BNX2_RPM_DEBUG2_THIS_CMD_M2 (1L<<26)
2172#define BNX2_RPM_DEBUG2_THIS_CMD_M1 (1L<<27)
2173#define BNX2_RPM_DEBUG2_IPIPE_EMPTY (1L<<28)
2174#define BNX2_RPM_DEBUG2_FM_DISCARD (1L<<29)
2175#define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30)
2176#define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31)
2177
2178#define BNX2_RPM_DEBUG3 0x00001990
2179#define BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0)
2180#define BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9)
2181#define BNX2_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10)
2182#define BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11)
2183#define BNX2_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12)
2184#define BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13)
2185#define BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14)
2186#define BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15)
2187#define BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16)
2188#define BNX2_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21)
2189#define BNX2_RPM_DEBUG3_DROP_NXT_VLD (1L<<22)
2190#define BNX2_RPM_DEBUG3_DROP_NXT (1L<<23)
2191#define BNX2_RPM_DEBUG3_FTQ_FSM (0x3L<<24)
2192#define BNX2_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24)
2193#define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24)
2194#define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24)
2195#define BNX2_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26)
2196#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26)
2197#define BNX2_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26)
2198#define BNX2_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26)
2199#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26)
2200#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26)
2201#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26)
2202#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26)
2203#define BNX2_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26)
2204#define BNX2_RPM_DEBUG3_MBFREE_FSM (1L<<29)
2205#define BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29)
2206#define BNX2_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29)
2207#define BNX2_RPM_DEBUG3_MBALLOC_FSM (1L<<30)
2208#define BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30)
2209#define BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30)
2210#define BNX2_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31)
2211
2212#define BNX2_RPM_DEBUG4 0x00001994
2213#define BNX2_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0)
2214#define BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25)
2215#define BNX2_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28)
2216#define BNX2_RPM_DEBUG4_DFIFO_EMPTY (1L<<31)
2217
2218#define BNX2_RPM_DEBUG5 0x00001998
2219#define BNX2_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0)
2220#define BNX2_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5)
2221#define BNX2_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10)
2222#define BNX2_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15)
2223#define BNX2_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20)
2224#define BNX2_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21)
2225#define BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22)
2226#define BNX2_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23)
2227#define BNX2_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24)
2228#define BNX2_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25)
2229#define BNX2_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26)
2230#define BNX2_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27)
2231#define BNX2_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28)
2232#define BNX2_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29)
2233#define BNX2_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30)
2234#define BNX2_RPM_DEBUG5_HOLDREG_RD (1L<<31)
2235
2236#define BNX2_RPM_DEBUG6 0x0000199c
2237#define BNX2_RPM_DEBUG6_ACPI_VEC (0xffffL<<0)
2238#define BNX2_RPM_DEBUG6_VEC (0xffffL<<16)
2239
2240#define BNX2_RPM_DEBUG7 0x000019a0
2241#define BNX2_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0)
2242
2243#define BNX2_RPM_DEBUG8 0x000019a4
2244#define BNX2_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0)
2245#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0)
2246#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0)
2247#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0)
2248#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0)
2249#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0)
2250#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0)
2251#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0)
2252#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0)
2253#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0)
2254#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0)
2255#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0)
2256#define BNX2_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4)
2257#define BNX2_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5)
2258#define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6)
2259#define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7)
2260#define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8)
2261#define BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9)
2262#define BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10)
2263#define BNX2_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11)
2264#define BNX2_RPM_DEBUG8_EOF_DET (1L<<12)
2265#define BNX2_RPM_DEBUG8_SOF_DET (1L<<13)
2266#define BNX2_RPM_DEBUG8_WAIT_4_SOF (1L<<14)
2267#define BNX2_RPM_DEBUG8_ALL_DONE (1L<<15)
2268#define BNX2_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16)
2269#define BNX2_RPM_DEBUG8_BYTE_CTR (0xffL<<24)
2270
2271#define BNX2_RPM_DEBUG9 0x000019a8
2272#define BNX2_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0)
2273#define BNX2_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3)
2274#define BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4)
2275#define BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28)
2276#define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29)
2277#define BNX2_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30)
2278#define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31)
2279
2280#define BNX2_RPM_ACPI_DBG_BUF_W00 0x000019c0
2281#define BNX2_RPM_ACPI_DBG_BUF_W01 0x000019c4
2282#define BNX2_RPM_ACPI_DBG_BUF_W02 0x000019c8
2283#define BNX2_RPM_ACPI_DBG_BUF_W03 0x000019cc
2284#define BNX2_RPM_ACPI_DBG_BUF_W10 0x000019d0
2285#define BNX2_RPM_ACPI_DBG_BUF_W11 0x000019d4
2286#define BNX2_RPM_ACPI_DBG_BUF_W12 0x000019d8
2287#define BNX2_RPM_ACPI_DBG_BUF_W13 0x000019dc
2288#define BNX2_RPM_ACPI_DBG_BUF_W20 0x000019e0
2289#define BNX2_RPM_ACPI_DBG_BUF_W21 0x000019e4
2290#define BNX2_RPM_ACPI_DBG_BUF_W22 0x000019e8
2291#define BNX2_RPM_ACPI_DBG_BUF_W23 0x000019ec
2292#define BNX2_RPM_ACPI_DBG_BUF_W30 0x000019f0
2293#define BNX2_RPM_ACPI_DBG_BUF_W31 0x000019f4
2294#define BNX2_RPM_ACPI_DBG_BUF_W32 0x000019f8
2295#define BNX2_RPM_ACPI_DBG_BUF_W33 0x000019fc
2296
2297
2298/*
2299 * rbuf_reg definition
2300 * offset: 0x200000
2301 */
2302#define BNX2_RBUF_COMMAND 0x00200000
2303#define BNX2_RBUF_COMMAND_ENABLED (1L<<0)
2304#define BNX2_RBUF_COMMAND_FREE_INIT (1L<<1)
2305#define BNX2_RBUF_COMMAND_RAM_INIT (1L<<2)
2306#define BNX2_RBUF_COMMAND_OVER_FREE (1L<<4)
2307#define BNX2_RBUF_COMMAND_ALLOC_REQ (1L<<5)
2308
2309#define BNX2_RBUF_STATUS1 0x00200004
2310#define BNX2_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0)
2311
2312#define BNX2_RBUF_STATUS2 0x00200008
2313#define BNX2_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0)
2314#define BNX2_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16)
2315
2316#define BNX2_RBUF_CONFIG 0x0020000c
2317#define BNX2_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0)
2318#define BNX2_RBUF_CONFIG_XON_TRIP (0x3ffL<<16)
2319
2320#define BNX2_RBUF_FW_BUF_ALLOC 0x00200010
2321#define BNX2_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7)
2322
2323#define BNX2_RBUF_FW_BUF_FREE 0x00200014
2324#define BNX2_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0)
2325#define BNX2_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7)
2326#define BNX2_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16)
2327
2328#define BNX2_RBUF_FW_BUF_SEL 0x00200018
2329#define BNX2_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0)
2330#define BNX2_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7)
2331#define BNX2_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16)
2332
2333#define BNX2_RBUF_CONFIG2 0x0020001c
2334#define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0)
2335#define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16)
2336
2337#define BNX2_RBUF_CONFIG3 0x00200020
2338#define BNX2_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0)
2339#define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16)
2340
2341#define BNX2_RBUF_PKT_DATA 0x00208000
2342#define BNX2_RBUF_CLIST_DATA 0x00210000
2343#define BNX2_RBUF_BUF_DATA 0x00220000
2344
2345
2346/*
2347 * rv2p_reg definition
2348 * offset: 0x2800
2349 */
2350#define BNX2_RV2P_COMMAND 0x00002800
2351#define BNX2_RV2P_COMMAND_ENABLED (1L<<0)
2352#define BNX2_RV2P_COMMAND_PROC1_INTRPT (1L<<1)
2353#define BNX2_RV2P_COMMAND_PROC2_INTRPT (1L<<2)
2354#define BNX2_RV2P_COMMAND_ABORT0 (1L<<4)
2355#define BNX2_RV2P_COMMAND_ABORT1 (1L<<5)
2356#define BNX2_RV2P_COMMAND_ABORT2 (1L<<6)
2357#define BNX2_RV2P_COMMAND_ABORT3 (1L<<7)
2358#define BNX2_RV2P_COMMAND_ABORT4 (1L<<8)
2359#define BNX2_RV2P_COMMAND_ABORT5 (1L<<9)
2360#define BNX2_RV2P_COMMAND_PROC1_RESET (1L<<16)
2361#define BNX2_RV2P_COMMAND_PROC2_RESET (1L<<17)
2362#define BNX2_RV2P_COMMAND_CTXIF_RESET (1L<<18)
2363
2364#define BNX2_RV2P_STATUS 0x00002804
2365#define BNX2_RV2P_STATUS_ALWAYS_0 (1L<<0)
2366#define BNX2_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8)
2367#define BNX2_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9)
2368#define BNX2_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10)
2369#define BNX2_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11)
2370#define BNX2_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12)
2371#define BNX2_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13)
2372
2373#define BNX2_RV2P_CONFIG 0x00002808
2374#define BNX2_RV2P_CONFIG_STALL_PROC1 (1L<<0)
2375#define BNX2_RV2P_CONFIG_STALL_PROC2 (1L<<1)
2376#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8)
2377#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9)
2378#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10)
2379#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11)
2380#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12)
2381#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13)
2382#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16)
2383#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17)
2384#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18)
2385#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19)
2386#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20)
2387#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21)
2388#define BNX2_RV2P_CONFIG_PAGE_SIZE (0xfL<<24)
2389#define BNX2_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24)
2390#define BNX2_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24)
2391#define BNX2_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24)
2392#define BNX2_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24)
2393#define BNX2_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24)
2394#define BNX2_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24)
2395#define BNX2_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24)
2396#define BNX2_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24)
2397#define BNX2_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24)
2398#define BNX2_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24)
2399#define BNX2_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24)
2400#define BNX2_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24)
2401#define BNX2_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24)
2402
2403#define BNX2_RV2P_GEN_BFR_ADDR_0 0x00002810
2404#define BNX2_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16)
2405
2406#define BNX2_RV2P_GEN_BFR_ADDR_1 0x00002814
2407#define BNX2_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16)
2408
2409#define BNX2_RV2P_GEN_BFR_ADDR_2 0x00002818
2410#define BNX2_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16)
2411
2412#define BNX2_RV2P_GEN_BFR_ADDR_3 0x0000281c
2413#define BNX2_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16)
2414
2415#define BNX2_RV2P_INSTR_HIGH 0x00002830
2416#define BNX2_RV2P_INSTR_HIGH_HIGH (0x1fL<<0)
2417
2418#define BNX2_RV2P_INSTR_LOW 0x00002834
2419#define BNX2_RV2P_PROC1_ADDR_CMD 0x00002838
2420#define BNX2_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0)
2421#define BNX2_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31)
2422
2423#define BNX2_RV2P_PROC2_ADDR_CMD 0x0000283c
2424#define BNX2_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0)
2425#define BNX2_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31)
2426
2427#define BNX2_RV2P_PROC1_GRC_DEBUG 0x00002840
2428#define BNX2_RV2P_PROC2_GRC_DEBUG 0x00002844
2429#define BNX2_RV2P_GRC_PROC_DEBUG 0x00002848
2430#define BNX2_RV2P_DEBUG_VECT_PEEK 0x0000284c
2431#define BNX2_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
2432#define BNX2_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
2433#define BNX2_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
2434#define BNX2_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
2435#define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
2436#define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
2437
2438#define BNX2_RV2P_PFTQ_DATA 0x00002b40
2439#define BNX2_RV2P_PFTQ_CMD 0x00002b78
2440#define BNX2_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0)
2441#define BNX2_RV2P_PFTQ_CMD_WR_TOP (1L<<10)
2442#define BNX2_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10)
2443#define BNX2_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10)
2444#define BNX2_RV2P_PFTQ_CMD_SFT_RESET (1L<<25)
2445#define BNX2_RV2P_PFTQ_CMD_RD_DATA (1L<<26)
2446#define BNX2_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27)
2447#define BNX2_RV2P_PFTQ_CMD_ADD_DATA (1L<<28)
2448#define BNX2_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29)
2449#define BNX2_RV2P_PFTQ_CMD_POP (1L<<30)
2450#define BNX2_RV2P_PFTQ_CMD_BUSY (1L<<31)
2451
2452#define BNX2_RV2P_PFTQ_CTL 0x00002b7c
2453#define BNX2_RV2P_PFTQ_CTL_INTERVENE (1L<<0)
2454#define BNX2_RV2P_PFTQ_CTL_OVERFLOW (1L<<1)
2455#define BNX2_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2)
2456#define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
2457#define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
2458
2459#define BNX2_RV2P_TFTQ_DATA 0x00002b80
2460#define BNX2_RV2P_TFTQ_CMD 0x00002bb8
2461#define BNX2_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0)
2462#define BNX2_RV2P_TFTQ_CMD_WR_TOP (1L<<10)
2463#define BNX2_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10)
2464#define BNX2_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10)
2465#define BNX2_RV2P_TFTQ_CMD_SFT_RESET (1L<<25)
2466#define BNX2_RV2P_TFTQ_CMD_RD_DATA (1L<<26)
2467#define BNX2_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27)
2468#define BNX2_RV2P_TFTQ_CMD_ADD_DATA (1L<<28)
2469#define BNX2_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29)
2470#define BNX2_RV2P_TFTQ_CMD_POP (1L<<30)
2471#define BNX2_RV2P_TFTQ_CMD_BUSY (1L<<31)
2472
2473#define BNX2_RV2P_TFTQ_CTL 0x00002bbc
2474#define BNX2_RV2P_TFTQ_CTL_INTERVENE (1L<<0)
2475#define BNX2_RV2P_TFTQ_CTL_OVERFLOW (1L<<1)
2476#define BNX2_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2)
2477#define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
2478#define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
2479
2480#define BNX2_RV2P_MFTQ_DATA 0x00002bc0
2481#define BNX2_RV2P_MFTQ_CMD 0x00002bf8
2482#define BNX2_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0)
2483#define BNX2_RV2P_MFTQ_CMD_WR_TOP (1L<<10)
2484#define BNX2_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10)
2485#define BNX2_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10)
2486#define BNX2_RV2P_MFTQ_CMD_SFT_RESET (1L<<25)
2487#define BNX2_RV2P_MFTQ_CMD_RD_DATA (1L<<26)
2488#define BNX2_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27)
2489#define BNX2_RV2P_MFTQ_CMD_ADD_DATA (1L<<28)
2490#define BNX2_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29)
2491#define BNX2_RV2P_MFTQ_CMD_POP (1L<<30)
2492#define BNX2_RV2P_MFTQ_CMD_BUSY (1L<<31)
2493
2494#define BNX2_RV2P_MFTQ_CTL 0x00002bfc
2495#define BNX2_RV2P_MFTQ_CTL_INTERVENE (1L<<0)
2496#define BNX2_RV2P_MFTQ_CTL_OVERFLOW (1L<<1)
2497#define BNX2_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2)
2498#define BNX2_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
2499#define BNX2_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
2500
2501
2502
2503/*
2504 * mq_reg definition
2505 * offset: 0x3c00
2506 */
2507#define BNX2_MQ_COMMAND 0x00003c00
2508#define BNX2_MQ_COMMAND_ENABLED (1L<<0)
2509#define BNX2_MQ_COMMAND_OVERFLOW (1L<<4)
2510#define BNX2_MQ_COMMAND_WR_ERROR (1L<<5)
2511#define BNX2_MQ_COMMAND_RD_ERROR (1L<<6)
2512
2513#define BNX2_MQ_STATUS 0x00003c04
2514#define BNX2_MQ_STATUS_CTX_ACCESS_STAT (1L<<16)
2515#define BNX2_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17)
2516#define BNX2_MQ_STATUS_PCI_STALL_STAT (1L<<18)
2517
2518#define BNX2_MQ_CONFIG 0x00003c08
2519#define BNX2_MQ_CONFIG_TX_HIGH_PRI (1L<<0)
2520#define BNX2_MQ_CONFIG_HALT_DIS (1L<<1)
2521#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4)
2522#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4)
2523#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4)
2524#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4)
2525#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4)
2526#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4)
2527#define BNX2_MQ_CONFIG_MAX_DEPTH (0x7fL<<8)
2528#define BNX2_MQ_CONFIG_CUR_DEPTH (0x7fL<<20)
2529
2530#define BNX2_MQ_ENQUEUE1 0x00003c0c
2531#define BNX2_MQ_ENQUEUE1_OFFSET (0x3fL<<2)
2532#define BNX2_MQ_ENQUEUE1_CID (0x3fffL<<8)
2533#define BNX2_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24)
2534#define BNX2_MQ_ENQUEUE1_KNL_MODE (1L<<28)
2535
2536#define BNX2_MQ_ENQUEUE2 0x00003c10
2537#define BNX2_MQ_BAD_WR_ADDR 0x00003c14
2538#define BNX2_MQ_BAD_RD_ADDR 0x00003c18
2539#define BNX2_MQ_KNL_BYP_WIND_START 0x00003c1c
2540#define BNX2_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12)
2541
2542#define BNX2_MQ_KNL_WIND_END 0x00003c20
2543#define BNX2_MQ_KNL_WIND_END_VALUE (0xffffffL<<8)
2544
2545#define BNX2_MQ_KNL_WRITE_MASK1 0x00003c24
2546#define BNX2_MQ_KNL_TX_MASK1 0x00003c28
2547#define BNX2_MQ_KNL_CMD_MASK1 0x00003c2c
2548#define BNX2_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30
2549#define BNX2_MQ_KNL_RX_V2P_MASK1 0x00003c34
2550#define BNX2_MQ_KNL_WRITE_MASK2 0x00003c38
2551#define BNX2_MQ_KNL_TX_MASK2 0x00003c3c
2552#define BNX2_MQ_KNL_CMD_MASK2 0x00003c40
2553#define BNX2_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44
2554#define BNX2_MQ_KNL_RX_V2P_MASK2 0x00003c48
2555#define BNX2_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c
2556#define BNX2_MQ_KNL_BYP_TX_MASK1 0x00003c50
2557#define BNX2_MQ_KNL_BYP_CMD_MASK1 0x00003c54
2558#define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58
2559#define BNX2_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c
2560#define BNX2_MQ_KNL_BYP_WRITE_MASK2 0x00003c60
2561#define BNX2_MQ_KNL_BYP_TX_MASK2 0x00003c64
2562#define BNX2_MQ_KNL_BYP_CMD_MASK2 0x00003c68
2563#define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c
2564#define BNX2_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70
2565#define BNX2_MQ_MEM_WR_ADDR 0x00003c74
2566#define BNX2_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0)
2567
2568#define BNX2_MQ_MEM_WR_DATA0 0x00003c78
2569#define BNX2_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0)
2570
2571#define BNX2_MQ_MEM_WR_DATA1 0x00003c7c
2572#define BNX2_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0)
2573
2574#define BNX2_MQ_MEM_WR_DATA2 0x00003c80
2575#define BNX2_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0)
2576
2577#define BNX2_MQ_MEM_RD_ADDR 0x00003c84
2578#define BNX2_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0)
2579
2580#define BNX2_MQ_MEM_RD_DATA0 0x00003c88
2581#define BNX2_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0)
2582
2583#define BNX2_MQ_MEM_RD_DATA1 0x00003c8c
2584#define BNX2_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0)
2585
2586#define BNX2_MQ_MEM_RD_DATA2 0x00003c90
2587#define BNX2_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0)
2588
2589
2590
2591/*
2592 * tbdr_reg definition
2593 * offset: 0x5000
2594 */
2595#define BNX2_TBDR_COMMAND 0x00005000
2596#define BNX2_TBDR_COMMAND_ENABLE (1L<<0)
2597#define BNX2_TBDR_COMMAND_SOFT_RST (1L<<1)
2598#define BNX2_TBDR_COMMAND_MSTR_ABORT (1L<<4)
2599
2600#define BNX2_TBDR_STATUS 0x00005004
2601#define BNX2_TBDR_STATUS_DMA_WAIT (1L<<0)
2602#define BNX2_TBDR_STATUS_FTQ_WAIT (1L<<1)
2603#define BNX2_TBDR_STATUS_FIFO_OVERFLOW (1L<<2)
2604#define BNX2_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3)
2605#define BNX2_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4)
2606#define BNX2_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5)
2607#define BNX2_TBDR_STATUS_BURST_CNT (1L<<6)
2608
2609#define BNX2_TBDR_CONFIG 0x00005008
2610#define BNX2_TBDR_CONFIG_MAX_BDS (0xffL<<0)
2611#define BNX2_TBDR_CONFIG_SWAP_MODE (1L<<8)
2612#define BNX2_TBDR_CONFIG_PRIORITY (1L<<9)
2613#define BNX2_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10)
2614#define BNX2_TBDR_CONFIG_PAGE_SIZE (0xfL<<24)
2615#define BNX2_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24)
2616#define BNX2_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24)
2617#define BNX2_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24)
2618#define BNX2_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24)
2619#define BNX2_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24)
2620#define BNX2_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24)
2621#define BNX2_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24)
2622#define BNX2_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24)
2623#define BNX2_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24)
2624#define BNX2_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24)
2625#define BNX2_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24)
2626#define BNX2_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24)
2627#define BNX2_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24)
2628
2629#define BNX2_TBDR_DEBUG_VECT_PEEK 0x0000500c
2630#define BNX2_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
2631#define BNX2_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
2632#define BNX2_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
2633#define BNX2_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
2634#define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
2635#define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
2636
2637#define BNX2_TBDR_FTQ_DATA 0x000053c0
2638#define BNX2_TBDR_FTQ_CMD 0x000053f8
2639#define BNX2_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0)
2640#define BNX2_TBDR_FTQ_CMD_WR_TOP (1L<<10)
2641#define BNX2_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10)
2642#define BNX2_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10)
2643#define BNX2_TBDR_FTQ_CMD_SFT_RESET (1L<<25)
2644#define BNX2_TBDR_FTQ_CMD_RD_DATA (1L<<26)
2645#define BNX2_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27)
2646#define BNX2_TBDR_FTQ_CMD_ADD_DATA (1L<<28)
2647#define BNX2_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29)
2648#define BNX2_TBDR_FTQ_CMD_POP (1L<<30)
2649#define BNX2_TBDR_FTQ_CMD_BUSY (1L<<31)
2650
2651#define BNX2_TBDR_FTQ_CTL 0x000053fc
2652#define BNX2_TBDR_FTQ_CTL_INTERVENE (1L<<0)
2653#define BNX2_TBDR_FTQ_CTL_OVERFLOW (1L<<1)
2654#define BNX2_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2)
2655#define BNX2_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
2656#define BNX2_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
2657
2658
2659
2660/*
2661 * tdma_reg definition
2662 * offset: 0x5c00
2663 */
2664#define BNX2_TDMA_COMMAND 0x00005c00
2665#define BNX2_TDMA_COMMAND_ENABLED (1L<<0)
2666#define BNX2_TDMA_COMMAND_MASTER_ABORT (1L<<4)
2667#define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7)
2668
2669#define BNX2_TDMA_STATUS 0x00005c04
2670#define BNX2_TDMA_STATUS_DMA_WAIT (1L<<0)
2671#define BNX2_TDMA_STATUS_PAYLOAD_WAIT (1L<<1)
2672#define BNX2_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2)
2673#define BNX2_TDMA_STATUS_LOCK_WAIT (1L<<3)
2674#define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16)
2675#define BNX2_TDMA_STATUS_BURST_CNT (1L<<17)
2676
2677#define BNX2_TDMA_CONFIG 0x00005c08
2678#define BNX2_TDMA_CONFIG_ONE_DMA (1L<<0)
2679#define BNX2_TDMA_CONFIG_ONE_RECORD (1L<<1)
2680#define BNX2_TDMA_CONFIG_LIMIT_SZ (0xfL<<4)
2681#define BNX2_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4)
2682#define BNX2_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4)
2683#define BNX2_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4)
2684#define BNX2_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4)
2685#define BNX2_TDMA_CONFIG_LINE_SZ (0xfL<<8)
2686#define BNX2_TDMA_CONFIG_LINE_SZ_64 (0L<<8)
2687#define BNX2_TDMA_CONFIG_LINE_SZ_128 (4L<<8)
2688#define BNX2_TDMA_CONFIG_LINE_SZ_256 (6L<<8)
2689#define BNX2_TDMA_CONFIG_LINE_SZ_512 (8L<<8)
2690#define BNX2_TDMA_CONFIG_ALIGN_ENA (1L<<15)
2691#define BNX2_TDMA_CONFIG_CHK_L2_BD (1L<<16)
2692#define BNX2_TDMA_CONFIG_FIFO_CMP (0xfL<<20)
2693
2694#define BNX2_TDMA_PAYLOAD_PROD 0x00005c0c
2695#define BNX2_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3)
2696
2697#define BNX2_TDMA_DBG_WATCHDOG 0x00005c10
2698#define BNX2_TDMA_DBG_TRIGGER 0x00005c14
2699#define BNX2_TDMA_DMAD_FSM 0x00005c80
2700#define BNX2_TDMA_DMAD_FSM_BD_INVLD (1L<<0)
2701#define BNX2_TDMA_DMAD_FSM_PUSH (0xfL<<4)
2702#define BNX2_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8)
2703#define BNX2_TDMA_DMAD_FSM_ARB_CTX (1L<<12)
2704#define BNX2_TDMA_DMAD_FSM_DR_INTF (1L<<16)
2705#define BNX2_TDMA_DMAD_FSM_DMAD (0x7L<<20)
2706#define BNX2_TDMA_DMAD_FSM_BD (0xfL<<24)
2707
2708#define BNX2_TDMA_DMAD_STATUS 0x00005c84
2709#define BNX2_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0)
2710#define BNX2_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4)
2711#define BNX2_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8)
2712#define BNX2_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12)
2713
2714#define BNX2_TDMA_DR_INTF_FSM 0x00005c88
2715#define BNX2_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0)
2716#define BNX2_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4)
2717#define BNX2_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8)
2718#define BNX2_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12)
2719#define BNX2_TDMA_DR_INTF_FSM_DMAD (0x7L<<16)
2720
2721#define BNX2_TDMA_DR_INTF_STATUS 0x00005c8c
2722#define BNX2_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0)
2723#define BNX2_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4)
2724#define BNX2_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8)
2725#define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12)
2726#define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16)
2727
2728#define BNX2_TDMA_FTQ_DATA 0x00005fc0
2729#define BNX2_TDMA_FTQ_CMD 0x00005ff8
2730#define BNX2_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0)
2731#define BNX2_TDMA_FTQ_CMD_WR_TOP (1L<<10)
2732#define BNX2_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10)
2733#define BNX2_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10)
2734#define BNX2_TDMA_FTQ_CMD_SFT_RESET (1L<<25)
2735#define BNX2_TDMA_FTQ_CMD_RD_DATA (1L<<26)
2736#define BNX2_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27)
2737#define BNX2_TDMA_FTQ_CMD_ADD_DATA (1L<<28)
2738#define BNX2_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29)
2739#define BNX2_TDMA_FTQ_CMD_POP (1L<<30)
2740#define BNX2_TDMA_FTQ_CMD_BUSY (1L<<31)
2741
2742#define BNX2_TDMA_FTQ_CTL 0x00005ffc
2743#define BNX2_TDMA_FTQ_CTL_INTERVENE (1L<<0)
2744#define BNX2_TDMA_FTQ_CTL_OVERFLOW (1L<<1)
2745#define BNX2_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2)
2746#define BNX2_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
2747#define BNX2_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
2748
2749
2750
2751/*
2752 * hc_reg definition
2753 * offset: 0x6800
2754 */
2755#define BNX2_HC_COMMAND 0x00006800
2756#define BNX2_HC_COMMAND_ENABLE (1L<<0)
2757#define BNX2_HC_COMMAND_SKIP_ABORT (1L<<4)
2758#define BNX2_HC_COMMAND_COAL_NOW (1L<<16)
2759#define BNX2_HC_COMMAND_COAL_NOW_WO_INT (1L<<17)
2760#define BNX2_HC_COMMAND_STATS_NOW (1L<<18)
2761#define BNX2_HC_COMMAND_FORCE_INT (0x3L<<19)
2762#define BNX2_HC_COMMAND_FORCE_INT_NULL (0L<<19)
2763#define BNX2_HC_COMMAND_FORCE_INT_HIGH (1L<<19)
2764#define BNX2_HC_COMMAND_FORCE_INT_LOW (2L<<19)
2765#define BNX2_HC_COMMAND_FORCE_INT_FREE (3L<<19)
2766#define BNX2_HC_COMMAND_CLR_STAT_NOW (1L<<21)
2767
2768#define BNX2_HC_STATUS 0x00006804
2769#define BNX2_HC_STATUS_MASTER_ABORT (1L<<0)
2770#define BNX2_HC_STATUS_PARITY_ERROR_STATE (1L<<1)
2771#define BNX2_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16)
2772#define BNX2_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17)
2773#define BNX2_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18)
2774#define BNX2_HC_STATUS_NUM_INT_GEN_STAT (1L<<19)
2775#define BNX2_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20)
2776#define BNX2_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23)
2777#define BNX2_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24)
2778#define BNX2_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25)
2779
2780#define BNX2_HC_CONFIG 0x00006808
2781#define BNX2_HC_CONFIG_COLLECT_STATS (1L<<0)
2782#define BNX2_HC_CONFIG_RX_TMR_MODE (1L<<1)
2783#define BNX2_HC_CONFIG_TX_TMR_MODE (1L<<2)
2784#define BNX2_HC_CONFIG_COM_TMR_MODE (1L<<3)
2785#define BNX2_HC_CONFIG_CMD_TMR_MODE (1L<<4)
2786#define BNX2_HC_CONFIG_STATISTIC_PRIORITY (1L<<5)
2787#define BNX2_HC_CONFIG_STATUS_PRIORITY (1L<<6)
2788#define BNX2_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8)
2789
2790#define BNX2_HC_ATTN_BITS_ENABLE 0x0000680c
2791#define BNX2_HC_STATUS_ADDR_L 0x00006810
2792#define BNX2_HC_STATUS_ADDR_H 0x00006814
2793#define BNX2_HC_STATISTICS_ADDR_L 0x00006818
2794#define BNX2_HC_STATISTICS_ADDR_H 0x0000681c
2795#define BNX2_HC_TX_QUICK_CONS_TRIP 0x00006820
2796#define BNX2_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
2797#define BNX2_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16)
2798
2799#define BNX2_HC_COMP_PROD_TRIP 0x00006824
2800#define BNX2_HC_COMP_PROD_TRIP_VALUE (0xffL<<0)
2801#define BNX2_HC_COMP_PROD_TRIP_INT (0xffL<<16)
2802
2803#define BNX2_HC_RX_QUICK_CONS_TRIP 0x00006828
2804#define BNX2_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
2805#define BNX2_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16)
2806
2807#define BNX2_HC_RX_TICKS 0x0000682c
2808#define BNX2_HC_RX_TICKS_VALUE (0x3ffL<<0)
2809#define BNX2_HC_RX_TICKS_INT (0x3ffL<<16)
2810
2811#define BNX2_HC_TX_TICKS 0x00006830
2812#define BNX2_HC_TX_TICKS_VALUE (0x3ffL<<0)
2813#define BNX2_HC_TX_TICKS_INT (0x3ffL<<16)
2814
2815#define BNX2_HC_COM_TICKS 0x00006834
2816#define BNX2_HC_COM_TICKS_VALUE (0x3ffL<<0)
2817#define BNX2_HC_COM_TICKS_INT (0x3ffL<<16)
2818
2819#define BNX2_HC_CMD_TICKS 0x00006838
2820#define BNX2_HC_CMD_TICKS_VALUE (0x3ffL<<0)
2821#define BNX2_HC_CMD_TICKS_INT (0x3ffL<<16)
2822
2823#define BNX2_HC_PERIODIC_TICKS 0x0000683c
2824#define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0)
2825
2826#define BNX2_HC_STAT_COLLECT_TICKS 0x00006840
2827#define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4)
2828
2829#define BNX2_HC_STATS_TICKS 0x00006844
2830#define BNX2_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8)
2831
2832#define BNX2_HC_STAT_MEM_DATA 0x0000684c
2833#define BNX2_HC_STAT_GEN_SEL_0 0x00006850
2834#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0)
2835#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0)
2836#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0)
2837#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0)
2838#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0)
2839#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0)
2840#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0)
2841#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0)
2842#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0)
2843#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0)
2844#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0)
2845#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0)
2846#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0)
2847#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0)
2848#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0)
2849#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0)
2850#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0)
2851#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0)
2852#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0)
2853#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0)
2854#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0)
2855#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0)
2856#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0)
2857#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0)
2858#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0)
2859#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0)
2860#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0)
2861#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0)
2862#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0)
2863#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0)
2864#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0)
2865#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0)
2866#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0)
2867#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0)
2868#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0)
2869#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0)
2870#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0)
2871#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0)
2872#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0)
2873#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0)
2874#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0)
2875#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0)
2876#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0)
2877#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0)
2878#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0)
2879#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0)
2880#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0)
2881#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0)
2882#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0)
2883#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0)
2884#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0)
2885#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0)
2886#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0)
2887#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0)
2888#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0)
2889#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0)
2890#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0)
2891#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0)
2892#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0)
2893#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0)
2894#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0)
2895#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0)
2896#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0)
2897#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0)
2898#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0)
2899#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0)
2900#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0)
2901#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0)
2902#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0)
2903#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0)
2904#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0)
2905#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0)
2906#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0)
2907#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0)
2908#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0)
2909#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0)
2910#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0)
2911#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0)
2912#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0)
2913#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0)
2914#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0)
2915#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0)
2916#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0)
2917#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0)
2918#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0)
2919#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0)
2920#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0)
2921#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0)
2922#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0)
2923#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0)
2924#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0)
2925#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0)
2926#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0)
2927#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0)
2928#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0)
2929#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0)
2930#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0)
2931#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0)
2932#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0)
2933#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0)
2934#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0)
2935#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0)
2936#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0)
2937#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0)
2938#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0)
2939#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0)
2940#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0)
2941#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0)
2942#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0)
2943#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0)
2944#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0)
2945#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0)
2946#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0)
2947#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0)
2948#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0)
2949#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0)
2950#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0)
2951#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0)
2952#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0)
2953#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0)
2954#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0)
2955#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0)
2956#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0)
2957#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8)
2958#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16)
2959#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24)
2960
2961#define BNX2_HC_STAT_GEN_SEL_1 0x00006854
2962#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0)
2963#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8)
2964#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16)
2965#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24)
2966
2967#define BNX2_HC_STAT_GEN_SEL_2 0x00006858
2968#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0)
2969#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8)
2970#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16)
2971#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24)
2972
2973#define BNX2_HC_STAT_GEN_SEL_3 0x0000685c
2974#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0)
2975#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8)
2976#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16)
2977#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24)
2978
2979#define BNX2_HC_STAT_GEN_STAT0 0x00006888
2980#define BNX2_HC_STAT_GEN_STAT1 0x0000688c
2981#define BNX2_HC_STAT_GEN_STAT2 0x00006890
2982#define BNX2_HC_STAT_GEN_STAT3 0x00006894
2983#define BNX2_HC_STAT_GEN_STAT4 0x00006898
2984#define BNX2_HC_STAT_GEN_STAT5 0x0000689c
2985#define BNX2_HC_STAT_GEN_STAT6 0x000068a0
2986#define BNX2_HC_STAT_GEN_STAT7 0x000068a4
2987#define BNX2_HC_STAT_GEN_STAT8 0x000068a8
2988#define BNX2_HC_STAT_GEN_STAT9 0x000068ac
2989#define BNX2_HC_STAT_GEN_STAT10 0x000068b0
2990#define BNX2_HC_STAT_GEN_STAT11 0x000068b4
2991#define BNX2_HC_STAT_GEN_STAT12 0x000068b8
2992#define BNX2_HC_STAT_GEN_STAT13 0x000068bc
2993#define BNX2_HC_STAT_GEN_STAT14 0x000068c0
2994#define BNX2_HC_STAT_GEN_STAT15 0x000068c4
2995#define BNX2_HC_STAT_GEN_STAT_AC0 0x000068c8
2996#define BNX2_HC_STAT_GEN_STAT_AC1 0x000068cc
2997#define BNX2_HC_STAT_GEN_STAT_AC2 0x000068d0
2998#define BNX2_HC_STAT_GEN_STAT_AC3 0x000068d4
2999#define BNX2_HC_STAT_GEN_STAT_AC4 0x000068d8
3000#define BNX2_HC_STAT_GEN_STAT_AC5 0x000068dc
3001#define BNX2_HC_STAT_GEN_STAT_AC6 0x000068e0
3002#define BNX2_HC_STAT_GEN_STAT_AC7 0x000068e4
3003#define BNX2_HC_STAT_GEN_STAT_AC8 0x000068e8
3004#define BNX2_HC_STAT_GEN_STAT_AC9 0x000068ec
3005#define BNX2_HC_STAT_GEN_STAT_AC10 0x000068f0
3006#define BNX2_HC_STAT_GEN_STAT_AC11 0x000068f4
3007#define BNX2_HC_STAT_GEN_STAT_AC12 0x000068f8
3008#define BNX2_HC_STAT_GEN_STAT_AC13 0x000068fc
3009#define BNX2_HC_STAT_GEN_STAT_AC14 0x00006900
3010#define BNX2_HC_STAT_GEN_STAT_AC15 0x00006904
3011#define BNX2_HC_VIS 0x00006908
3012#define BNX2_HC_VIS_STAT_BUILD_STATE (0xfL<<0)
3013#define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0)
3014#define BNX2_HC_VIS_STAT_BUILD_STATE_START (1L<<0)
3015#define BNX2_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0)
3016#define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0)
3017#define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0)
3018#define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0)
3019#define BNX2_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0)
3020#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0)
3021#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0)
3022#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0)
3023#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0)
3024#define BNX2_HC_VIS_DMA_STAT_STATE (0xfL<<8)
3025#define BNX2_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8)
3026#define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8)
3027#define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8)
3028#define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8)
3029#define BNX2_HC_VIS_DMA_STAT_STATE_COMP (4L<<8)
3030#define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8)
3031#define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8)
3032#define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8)
3033#define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8)
3034#define BNX2_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8)
3035#define BNX2_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8)
3036#define BNX2_HC_VIS_DMA_MSI_STATE (0x7L<<12)
3037#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15)
3038#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15)
3039#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15)
3040#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15)
3041
3042#define BNX2_HC_VIS_1 0x0000690c
3043#define BNX2_HC_VIS_1_HW_INTACK_STATE (1L<<4)
3044#define BNX2_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4)
3045#define BNX2_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4)
3046#define BNX2_HC_VIS_1_SW_INTACK_STATE (1L<<5)
3047#define BNX2_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5)
3048#define BNX2_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5)
3049#define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6)
3050#define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6)
3051#define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6)
3052#define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7)
3053#define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7)
3054#define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7)
3055#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17)
3056#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17)
3057#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17)
3058#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17)
3059#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17)
3060#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17)
3061#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17)
3062#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17)
3063#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17)
3064#define BNX2_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21)
3065#define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21)
3066#define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21)
3067#define BNX2_HC_VIS_1_INT_GEN_STATE (1L<<23)
3068#define BNX2_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23)
3069#define BNX2_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23)
3070#define BNX2_HC_VIS_1_STAT_CHAN_ID (0x7L<<24)
3071#define BNX2_HC_VIS_1_INT_B (1L<<27)
3072
3073#define BNX2_HC_DEBUG_VECT_PEEK 0x00006910
3074#define BNX2_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3075#define BNX2_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3076#define BNX2_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3077#define BNX2_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3078#define BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3079#define BNX2_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3080
3081
3082
3083/*
3084 * txp_reg definition
3085 * offset: 0x40000
3086 */
3087#define BNX2_TXP_CPU_MODE 0x00045000
3088#define BNX2_TXP_CPU_MODE_LOCAL_RST (1L<<0)
3089#define BNX2_TXP_CPU_MODE_STEP_ENA (1L<<1)
3090#define BNX2_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3091#define BNX2_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3092#define BNX2_TXP_CPU_MODE_MSG_BIT1 (1L<<6)
3093#define BNX2_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
3094#define BNX2_TXP_CPU_MODE_SOFT_HALT (1L<<10)
3095#define BNX2_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3096#define BNX2_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3097#define BNX2_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3098#define BNX2_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3099
3100#define BNX2_TXP_CPU_STATE 0x00045004
3101#define BNX2_TXP_CPU_STATE_BREAKPOINT (1L<<0)
3102#define BNX2_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
3103#define BNX2_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3104#define BNX2_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3105#define BNX2_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3106#define BNX2_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6)
3107#define BNX2_TXP_CPU_STATE_ALIGN_HALTED (1L<<7)
3108#define BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3109#define BNX2_TXP_CPU_STATE_SOFT_HALTED (1L<<10)
3110#define BNX2_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3111#define BNX2_TXP_CPU_STATE_INTERRRUPT (1L<<12)
3112#define BNX2_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3113#define BNX2_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
3114#define BNX2_TXP_CPU_STATE_BLOCKED_READ (1L<<31)
3115
3116#define BNX2_TXP_CPU_EVENT_MASK 0x00045008
3117#define BNX2_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3118#define BNX2_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3119#define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3120#define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3121#define BNX2_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3122#define BNX2_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3123#define BNX2_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3124#define BNX2_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3125#define BNX2_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3126#define BNX2_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3127#define BNX2_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3128
3129#define BNX2_TXP_CPU_PROGRAM_COUNTER 0x0004501c
3130#define BNX2_TXP_CPU_INSTRUCTION 0x00045020
3131#define BNX2_TXP_CPU_DATA_ACCESS 0x00045024
3132#define BNX2_TXP_CPU_INTERRUPT_ENABLE 0x00045028
3133#define BNX2_TXP_CPU_INTERRUPT_VECTOR 0x0004502c
3134#define BNX2_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030
3135#define BNX2_TXP_CPU_HW_BREAKPOINT 0x00045034
3136#define BNX2_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3137#define BNX2_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3138
3139#define BNX2_TXP_CPU_DEBUG_VECT_PEEK 0x00045038
3140#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3141#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3142#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3143#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3144#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3145#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3146
3147#define BNX2_TXP_CPU_LAST_BRANCH_ADDR 0x00045048
3148#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3149#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3150#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3151#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3152
3153#define BNX2_TXP_CPU_REG_FILE 0x00045200
3154#define BNX2_TXP_FTQ_DATA 0x000453c0
3155#define BNX2_TXP_FTQ_CMD 0x000453f8
3156#define BNX2_TXP_FTQ_CMD_OFFSET (0x3ffL<<0)
3157#define BNX2_TXP_FTQ_CMD_WR_TOP (1L<<10)
3158#define BNX2_TXP_FTQ_CMD_WR_TOP_0 (0L<<10)
3159#define BNX2_TXP_FTQ_CMD_WR_TOP_1 (1L<<10)
3160#define BNX2_TXP_FTQ_CMD_SFT_RESET (1L<<25)
3161#define BNX2_TXP_FTQ_CMD_RD_DATA (1L<<26)
3162#define BNX2_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
3163#define BNX2_TXP_FTQ_CMD_ADD_DATA (1L<<28)
3164#define BNX2_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
3165#define BNX2_TXP_FTQ_CMD_POP (1L<<30)
3166#define BNX2_TXP_FTQ_CMD_BUSY (1L<<31)
3167
3168#define BNX2_TXP_FTQ_CTL 0x000453fc
3169#define BNX2_TXP_FTQ_CTL_INTERVENE (1L<<0)
3170#define BNX2_TXP_FTQ_CTL_OVERFLOW (1L<<1)
3171#define BNX2_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3172#define BNX2_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3173#define BNX2_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3174
3175#define BNX2_TXP_SCRATCH 0x00060000
3176
3177
3178/*
3179 * tpat_reg definition
3180 * offset: 0x80000
3181 */
3182#define BNX2_TPAT_CPU_MODE 0x00085000
3183#define BNX2_TPAT_CPU_MODE_LOCAL_RST (1L<<0)
3184#define BNX2_TPAT_CPU_MODE_STEP_ENA (1L<<1)
3185#define BNX2_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3186#define BNX2_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3187#define BNX2_TPAT_CPU_MODE_MSG_BIT1 (1L<<6)
3188#define BNX2_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7)
3189#define BNX2_TPAT_CPU_MODE_SOFT_HALT (1L<<10)
3190#define BNX2_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3191#define BNX2_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3192#define BNX2_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3193#define BNX2_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3194
3195#define BNX2_TPAT_CPU_STATE 0x00085004
3196#define BNX2_TPAT_CPU_STATE_BREAKPOINT (1L<<0)
3197#define BNX2_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2)
3198#define BNX2_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3199#define BNX2_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3200#define BNX2_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3201#define BNX2_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6)
3202#define BNX2_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7)
3203#define BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3204#define BNX2_TPAT_CPU_STATE_SOFT_HALTED (1L<<10)
3205#define BNX2_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3206#define BNX2_TPAT_CPU_STATE_INTERRRUPT (1L<<12)
3207#define BNX2_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3208#define BNX2_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15)
3209#define BNX2_TPAT_CPU_STATE_BLOCKED_READ (1L<<31)
3210
3211#define BNX2_TPAT_CPU_EVENT_MASK 0x00085008
3212#define BNX2_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3213#define BNX2_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3214#define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3215#define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3216#define BNX2_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3217#define BNX2_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3218#define BNX2_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3219#define BNX2_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3220#define BNX2_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3221#define BNX2_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3222#define BNX2_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3223
3224#define BNX2_TPAT_CPU_PROGRAM_COUNTER 0x0008501c
3225#define BNX2_TPAT_CPU_INSTRUCTION 0x00085020
3226#define BNX2_TPAT_CPU_DATA_ACCESS 0x00085024
3227#define BNX2_TPAT_CPU_INTERRUPT_ENABLE 0x00085028
3228#define BNX2_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c
3229#define BNX2_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030
3230#define BNX2_TPAT_CPU_HW_BREAKPOINT 0x00085034
3231#define BNX2_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3232#define BNX2_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3233
3234#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038
3235#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3236#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3237#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3238#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3239#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3240#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3241
3242#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048
3243#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3244#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3245#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3246#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3247
3248#define BNX2_TPAT_CPU_REG_FILE 0x00085200
3249#define BNX2_TPAT_FTQ_DATA 0x000853c0
3250#define BNX2_TPAT_FTQ_CMD 0x000853f8
3251#define BNX2_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0)
3252#define BNX2_TPAT_FTQ_CMD_WR_TOP (1L<<10)
3253#define BNX2_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10)
3254#define BNX2_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10)
3255#define BNX2_TPAT_FTQ_CMD_SFT_RESET (1L<<25)
3256#define BNX2_TPAT_FTQ_CMD_RD_DATA (1L<<26)
3257#define BNX2_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27)
3258#define BNX2_TPAT_FTQ_CMD_ADD_DATA (1L<<28)
3259#define BNX2_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29)
3260#define BNX2_TPAT_FTQ_CMD_POP (1L<<30)
3261#define BNX2_TPAT_FTQ_CMD_BUSY (1L<<31)
3262
3263#define BNX2_TPAT_FTQ_CTL 0x000853fc
3264#define BNX2_TPAT_FTQ_CTL_INTERVENE (1L<<0)
3265#define BNX2_TPAT_FTQ_CTL_OVERFLOW (1L<<1)
3266#define BNX2_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3267#define BNX2_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3268#define BNX2_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3269
3270#define BNX2_TPAT_SCRATCH 0x000a0000
3271
3272
3273/*
3274 * rxp_reg definition
3275 * offset: 0xc0000
3276 */
3277#define BNX2_RXP_CPU_MODE 0x000c5000
3278#define BNX2_RXP_CPU_MODE_LOCAL_RST (1L<<0)
3279#define BNX2_RXP_CPU_MODE_STEP_ENA (1L<<1)
3280#define BNX2_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3281#define BNX2_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3282#define BNX2_RXP_CPU_MODE_MSG_BIT1 (1L<<6)
3283#define BNX2_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
3284#define BNX2_RXP_CPU_MODE_SOFT_HALT (1L<<10)
3285#define BNX2_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3286#define BNX2_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3287#define BNX2_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3288#define BNX2_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3289
3290#define BNX2_RXP_CPU_STATE 0x000c5004
3291#define BNX2_RXP_CPU_STATE_BREAKPOINT (1L<<0)
3292#define BNX2_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
3293#define BNX2_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3294#define BNX2_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3295#define BNX2_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3296#define BNX2_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6)
3297#define BNX2_RXP_CPU_STATE_ALIGN_HALTED (1L<<7)
3298#define BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3299#define BNX2_RXP_CPU_STATE_SOFT_HALTED (1L<<10)
3300#define BNX2_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3301#define BNX2_RXP_CPU_STATE_INTERRRUPT (1L<<12)
3302#define BNX2_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3303#define BNX2_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
3304#define BNX2_RXP_CPU_STATE_BLOCKED_READ (1L<<31)
3305
3306#define BNX2_RXP_CPU_EVENT_MASK 0x000c5008
3307#define BNX2_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3308#define BNX2_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3309#define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3310#define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3311#define BNX2_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3312#define BNX2_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3313#define BNX2_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3314#define BNX2_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3315#define BNX2_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3316#define BNX2_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3317#define BNX2_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3318
3319#define BNX2_RXP_CPU_PROGRAM_COUNTER 0x000c501c
3320#define BNX2_RXP_CPU_INSTRUCTION 0x000c5020
3321#define BNX2_RXP_CPU_DATA_ACCESS 0x000c5024
3322#define BNX2_RXP_CPU_INTERRUPT_ENABLE 0x000c5028
3323#define BNX2_RXP_CPU_INTERRUPT_VECTOR 0x000c502c
3324#define BNX2_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030
3325#define BNX2_RXP_CPU_HW_BREAKPOINT 0x000c5034
3326#define BNX2_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3327#define BNX2_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3328
3329#define BNX2_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038
3330#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3331#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3332#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3333#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3334#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3335#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3336
3337#define BNX2_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048
3338#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3339#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3340#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3341#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3342
3343#define BNX2_RXP_CPU_REG_FILE 0x000c5200
3344#define BNX2_RXP_CFTQ_DATA 0x000c5380
3345#define BNX2_RXP_CFTQ_CMD 0x000c53b8
3346#define BNX2_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0)
3347#define BNX2_RXP_CFTQ_CMD_WR_TOP (1L<<10)
3348#define BNX2_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10)
3349#define BNX2_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10)
3350#define BNX2_RXP_CFTQ_CMD_SFT_RESET (1L<<25)
3351#define BNX2_RXP_CFTQ_CMD_RD_DATA (1L<<26)
3352#define BNX2_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27)
3353#define BNX2_RXP_CFTQ_CMD_ADD_DATA (1L<<28)
3354#define BNX2_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29)
3355#define BNX2_RXP_CFTQ_CMD_POP (1L<<30)
3356#define BNX2_RXP_CFTQ_CMD_BUSY (1L<<31)
3357
3358#define BNX2_RXP_CFTQ_CTL 0x000c53bc
3359#define BNX2_RXP_CFTQ_CTL_INTERVENE (1L<<0)
3360#define BNX2_RXP_CFTQ_CTL_OVERFLOW (1L<<1)
3361#define BNX2_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2)
3362#define BNX2_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3363#define BNX2_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3364
3365#define BNX2_RXP_FTQ_DATA 0x000c53c0
3366#define BNX2_RXP_FTQ_CMD 0x000c53f8
3367#define BNX2_RXP_FTQ_CMD_OFFSET (0x3ffL<<0)
3368#define BNX2_RXP_FTQ_CMD_WR_TOP (1L<<10)
3369#define BNX2_RXP_FTQ_CMD_WR_TOP_0 (0L<<10)
3370#define BNX2_RXP_FTQ_CMD_WR_TOP_1 (1L<<10)
3371#define BNX2_RXP_FTQ_CMD_SFT_RESET (1L<<25)
3372#define BNX2_RXP_FTQ_CMD_RD_DATA (1L<<26)
3373#define BNX2_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
3374#define BNX2_RXP_FTQ_CMD_ADD_DATA (1L<<28)
3375#define BNX2_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
3376#define BNX2_RXP_FTQ_CMD_POP (1L<<30)
3377#define BNX2_RXP_FTQ_CMD_BUSY (1L<<31)
3378
3379#define BNX2_RXP_FTQ_CTL 0x000c53fc
3380#define BNX2_RXP_FTQ_CTL_INTERVENE (1L<<0)
3381#define BNX2_RXP_FTQ_CTL_OVERFLOW (1L<<1)
3382#define BNX2_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3383#define BNX2_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3384#define BNX2_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3385
3386#define BNX2_RXP_SCRATCH 0x000e0000
3387
3388
3389/*
3390 * com_reg definition
3391 * offset: 0x100000
3392 */
3393#define BNX2_COM_CPU_MODE 0x00105000
3394#define BNX2_COM_CPU_MODE_LOCAL_RST (1L<<0)
3395#define BNX2_COM_CPU_MODE_STEP_ENA (1L<<1)
3396#define BNX2_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3397#define BNX2_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3398#define BNX2_COM_CPU_MODE_MSG_BIT1 (1L<<6)
3399#define BNX2_COM_CPU_MODE_INTERRUPT_ENA (1L<<7)
3400#define BNX2_COM_CPU_MODE_SOFT_HALT (1L<<10)
3401#define BNX2_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3402#define BNX2_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3403#define BNX2_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3404#define BNX2_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3405
3406#define BNX2_COM_CPU_STATE 0x00105004
3407#define BNX2_COM_CPU_STATE_BREAKPOINT (1L<<0)
3408#define BNX2_COM_CPU_STATE_BAD_INST_HALTED (1L<<2)
3409#define BNX2_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3410#define BNX2_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3411#define BNX2_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3412#define BNX2_COM_CPU_STATE_BAD_pc_HALTED (1L<<6)
3413#define BNX2_COM_CPU_STATE_ALIGN_HALTED (1L<<7)
3414#define BNX2_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3415#define BNX2_COM_CPU_STATE_SOFT_HALTED (1L<<10)
3416#define BNX2_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3417#define BNX2_COM_CPU_STATE_INTERRRUPT (1L<<12)
3418#define BNX2_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3419#define BNX2_COM_CPU_STATE_INST_FETCH_STALL (1L<<15)
3420#define BNX2_COM_CPU_STATE_BLOCKED_READ (1L<<31)
3421
3422#define BNX2_COM_CPU_EVENT_MASK 0x00105008
3423#define BNX2_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3424#define BNX2_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3425#define BNX2_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3426#define BNX2_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3427#define BNX2_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3428#define BNX2_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3429#define BNX2_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3430#define BNX2_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3431#define BNX2_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3432#define BNX2_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3433#define BNX2_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3434
3435#define BNX2_COM_CPU_PROGRAM_COUNTER 0x0010501c
3436#define BNX2_COM_CPU_INSTRUCTION 0x00105020
3437#define BNX2_COM_CPU_DATA_ACCESS 0x00105024
3438#define BNX2_COM_CPU_INTERRUPT_ENABLE 0x00105028
3439#define BNX2_COM_CPU_INTERRUPT_VECTOR 0x0010502c
3440#define BNX2_COM_CPU_INTERRUPT_SAVED_PC 0x00105030
3441#define BNX2_COM_CPU_HW_BREAKPOINT 0x00105034
3442#define BNX2_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3443#define BNX2_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3444
3445#define BNX2_COM_CPU_DEBUG_VECT_PEEK 0x00105038
3446#define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3447#define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3448#define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3449#define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3450#define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3451#define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3452
3453#define BNX2_COM_CPU_LAST_BRANCH_ADDR 0x00105048
3454#define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3455#define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3456#define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3457#define BNX2_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3458
3459#define BNX2_COM_CPU_REG_FILE 0x00105200
3460#define BNX2_COM_COMXQ_FTQ_DATA 0x00105340
3461#define BNX2_COM_COMXQ_FTQ_CMD 0x00105378
3462#define BNX2_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3463#define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10)
3464#define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10)
3465#define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10)
3466#define BNX2_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25)
3467#define BNX2_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26)
3468#define BNX2_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
3469#define BNX2_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28)
3470#define BNX2_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
3471#define BNX2_COM_COMXQ_FTQ_CMD_POP (1L<<30)
3472#define BNX2_COM_COMXQ_FTQ_CMD_BUSY (1L<<31)
3473
3474#define BNX2_COM_COMXQ_FTQ_CTL 0x0010537c
3475#define BNX2_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0)
3476#define BNX2_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1)
3477#define BNX2_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3478#define BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3479#define BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3480
3481#define BNX2_COM_COMTQ_FTQ_DATA 0x00105380
3482#define BNX2_COM_COMTQ_FTQ_CMD 0x001053b8
3483#define BNX2_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3484#define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10)
3485#define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10)
3486#define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10)
3487#define BNX2_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25)
3488#define BNX2_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26)
3489#define BNX2_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
3490#define BNX2_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28)
3491#define BNX2_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
3492#define BNX2_COM_COMTQ_FTQ_CMD_POP (1L<<30)
3493#define BNX2_COM_COMTQ_FTQ_CMD_BUSY (1L<<31)
3494
3495#define BNX2_COM_COMTQ_FTQ_CTL 0x001053bc
3496#define BNX2_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0)
3497#define BNX2_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1)
3498#define BNX2_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3499#define BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3500#define BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3501
3502#define BNX2_COM_COMQ_FTQ_DATA 0x001053c0
3503#define BNX2_COM_COMQ_FTQ_CMD 0x001053f8
3504#define BNX2_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3505#define BNX2_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10)
3506#define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10)
3507#define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10)
3508#define BNX2_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25)
3509#define BNX2_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26)
3510#define BNX2_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
3511#define BNX2_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28)
3512#define BNX2_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
3513#define BNX2_COM_COMQ_FTQ_CMD_POP (1L<<30)
3514#define BNX2_COM_COMQ_FTQ_CMD_BUSY (1L<<31)
3515
3516#define BNX2_COM_COMQ_FTQ_CTL 0x001053fc
3517#define BNX2_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0)
3518#define BNX2_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1)
3519#define BNX2_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3520#define BNX2_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3521#define BNX2_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3522
3523#define BNX2_COM_SCRATCH 0x00120000
3524
3525
3526/*
3527 * cp_reg definition
3528 * offset: 0x180000
3529 */
3530#define BNX2_CP_CPU_MODE 0x00185000
3531#define BNX2_CP_CPU_MODE_LOCAL_RST (1L<<0)
3532#define BNX2_CP_CPU_MODE_STEP_ENA (1L<<1)
3533#define BNX2_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3534#define BNX2_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3535#define BNX2_CP_CPU_MODE_MSG_BIT1 (1L<<6)
3536#define BNX2_CP_CPU_MODE_INTERRUPT_ENA (1L<<7)
3537#define BNX2_CP_CPU_MODE_SOFT_HALT (1L<<10)
3538#define BNX2_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3539#define BNX2_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3540#define BNX2_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3541#define BNX2_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3542
3543#define BNX2_CP_CPU_STATE 0x00185004
3544#define BNX2_CP_CPU_STATE_BREAKPOINT (1L<<0)
3545#define BNX2_CP_CPU_STATE_BAD_INST_HALTED (1L<<2)
3546#define BNX2_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3547#define BNX2_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3548#define BNX2_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3549#define BNX2_CP_CPU_STATE_BAD_pc_HALTED (1L<<6)
3550#define BNX2_CP_CPU_STATE_ALIGN_HALTED (1L<<7)
3551#define BNX2_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3552#define BNX2_CP_CPU_STATE_SOFT_HALTED (1L<<10)
3553#define BNX2_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3554#define BNX2_CP_CPU_STATE_INTERRRUPT (1L<<12)
3555#define BNX2_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3556#define BNX2_CP_CPU_STATE_INST_FETCH_STALL (1L<<15)
3557#define BNX2_CP_CPU_STATE_BLOCKED_READ (1L<<31)
3558
3559#define BNX2_CP_CPU_EVENT_MASK 0x00185008
3560#define BNX2_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3561#define BNX2_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3562#define BNX2_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3563#define BNX2_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3564#define BNX2_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3565#define BNX2_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3566#define BNX2_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3567#define BNX2_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3568#define BNX2_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3569#define BNX2_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3570#define BNX2_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3571
3572#define BNX2_CP_CPU_PROGRAM_COUNTER 0x0018501c
3573#define BNX2_CP_CPU_INSTRUCTION 0x00185020
3574#define BNX2_CP_CPU_DATA_ACCESS 0x00185024
3575#define BNX2_CP_CPU_INTERRUPT_ENABLE 0x00185028
3576#define BNX2_CP_CPU_INTERRUPT_VECTOR 0x0018502c
3577#define BNX2_CP_CPU_INTERRUPT_SAVED_PC 0x00185030
3578#define BNX2_CP_CPU_HW_BREAKPOINT 0x00185034
3579#define BNX2_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3580#define BNX2_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3581
3582#define BNX2_CP_CPU_DEBUG_VECT_PEEK 0x00185038
3583#define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3584#define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3585#define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3586#define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3587#define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3588#define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3589
3590#define BNX2_CP_CPU_LAST_BRANCH_ADDR 0x00185048
3591#define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3592#define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3593#define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3594#define BNX2_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3595
3596#define BNX2_CP_CPU_REG_FILE 0x00185200
3597#define BNX2_CP_CPQ_FTQ_DATA 0x001853c0
3598#define BNX2_CP_CPQ_FTQ_CMD 0x001853f8
3599#define BNX2_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3600#define BNX2_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10)
3601#define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
3602#define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
3603#define BNX2_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25)
3604#define BNX2_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26)
3605#define BNX2_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
3606#define BNX2_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28)
3607#define BNX2_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
3608#define BNX2_CP_CPQ_FTQ_CMD_POP (1L<<30)
3609#define BNX2_CP_CPQ_FTQ_CMD_BUSY (1L<<31)
3610
3611#define BNX2_CP_CPQ_FTQ_CTL 0x001853fc
3612#define BNX2_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0)
3613#define BNX2_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1)
3614#define BNX2_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3615#define BNX2_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3616#define BNX2_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3617
3618#define BNX2_CP_SCRATCH 0x001a0000
3619
3620
3621/*
3622 * mcp_reg definition
3623 * offset: 0x140000
3624 */
3625#define BNX2_MCP_CPU_MODE 0x00145000
3626#define BNX2_MCP_CPU_MODE_LOCAL_RST (1L<<0)
3627#define BNX2_MCP_CPU_MODE_STEP_ENA (1L<<1)
3628#define BNX2_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3629#define BNX2_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3630#define BNX2_MCP_CPU_MODE_MSG_BIT1 (1L<<6)
3631#define BNX2_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7)
3632#define BNX2_MCP_CPU_MODE_SOFT_HALT (1L<<10)
3633#define BNX2_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3634#define BNX2_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3635#define BNX2_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3636#define BNX2_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3637
3638#define BNX2_MCP_CPU_STATE 0x00145004
3639#define BNX2_MCP_CPU_STATE_BREAKPOINT (1L<<0)
3640#define BNX2_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2)
3641#define BNX2_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3642#define BNX2_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3643#define BNX2_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3644#define BNX2_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6)
3645#define BNX2_MCP_CPU_STATE_ALIGN_HALTED (1L<<7)
3646#define BNX2_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3647#define BNX2_MCP_CPU_STATE_SOFT_HALTED (1L<<10)
3648#define BNX2_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3649#define BNX2_MCP_CPU_STATE_INTERRRUPT (1L<<12)
3650#define BNX2_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3651#define BNX2_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15)
3652#define BNX2_MCP_CPU_STATE_BLOCKED_READ (1L<<31)
3653
3654#define BNX2_MCP_CPU_EVENT_MASK 0x00145008
3655#define BNX2_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3656#define BNX2_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3657#define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3658#define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3659#define BNX2_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3660#define BNX2_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3661#define BNX2_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3662#define BNX2_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3663#define BNX2_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3664#define BNX2_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3665#define BNX2_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3666
3667#define BNX2_MCP_CPU_PROGRAM_COUNTER 0x0014501c
3668#define BNX2_MCP_CPU_INSTRUCTION 0x00145020
3669#define BNX2_MCP_CPU_DATA_ACCESS 0x00145024
3670#define BNX2_MCP_CPU_INTERRUPT_ENABLE 0x00145028
3671#define BNX2_MCP_CPU_INTERRUPT_VECTOR 0x0014502c
3672#define BNX2_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030
3673#define BNX2_MCP_CPU_HW_BREAKPOINT 0x00145034
3674#define BNX2_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3675#define BNX2_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3676
3677#define BNX2_MCP_CPU_DEBUG_VECT_PEEK 0x00145038
3678#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3679#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3680#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3681#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3682#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3683#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3684
3685#define BNX2_MCP_CPU_LAST_BRANCH_ADDR 0x00145048
3686#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3687#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3688#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3689#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3690
3691#define BNX2_MCP_CPU_REG_FILE 0x00145200
3692#define BNX2_MCP_MCPQ_FTQ_DATA 0x001453c0
3693#define BNX2_MCP_MCPQ_FTQ_CMD 0x001453f8
3694#define BNX2_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3695#define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10)
3696#define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
3697#define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
3698#define BNX2_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25)
3699#define BNX2_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26)
3700#define BNX2_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
3701#define BNX2_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28)
3702#define BNX2_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
3703#define BNX2_MCP_MCPQ_FTQ_CMD_POP (1L<<30)
3704#define BNX2_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31)
3705
3706#define BNX2_MCP_MCPQ_FTQ_CTL 0x001453fc
3707#define BNX2_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0)
3708#define BNX2_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1)
3709#define BNX2_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3710#define BNX2_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3711#define BNX2_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3712
3713#define BNX2_MCP_ROM 0x00150000
3714#define BNX2_MCP_SCRATCH 0x00160000
3715
3716
3717#define NUM_MC_HASH_REGISTERS 8
3718
3719
3720/* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */
3721#define PHY_BCM5706_PHY_ID 0x00206160
3722
3723#define PHY_ID(id) ((id) & 0xfffffff0)
3724#define PHY_REV_ID(id) ((id) & 0xf)
3725
3726#define MIN_ETHERNET_PACKET_SIZE 60
3727#define MAX_ETHERNET_PACKET_SIZE 1514
3728#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9014
3729
3730#define RX_COPY_THRESH 92
3731
3732#define DMA_READ_CHANS 5
3733#define DMA_WRITE_CHANS 3
3734
3735#define BCM_PAGE_BITS 12
3736#define BCM_PAGE_SIZE (1 << BCM_PAGE_BITS)
3737
3738#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct tx_bd))
3739#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
3740
3741#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct rx_bd))
3742#define MAX_RX_DESC_CNT (RX_DESC_CNT - 1)
3743
3744#define NEXT_TX_BD(x) (((x) & (MAX_TX_DESC_CNT - 1)) == \
3745 (MAX_TX_DESC_CNT - 1)) ? \
3746 (x) + 2 : (x) + 1
3747
3748#define TX_RING_IDX(x) ((x) & MAX_TX_DESC_CNT)
3749
3750#define NEXT_RX_BD(x) (((x) & (MAX_RX_DESC_CNT - 1)) == \
3751 (MAX_RX_DESC_CNT - 1)) ? \
3752 (x) + 2 : (x) + 1
3753
3754#define RX_RING_IDX(x) ((x) & MAX_RX_DESC_CNT)
3755
3756
3757/* Context size. */
3758#define CTX_SHIFT 7
3759#define CTX_SIZE (1 << CTX_SHIFT)
3760#define CTX_MASK (CTX_SIZE - 1)
3761#define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT)
3762#define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT)
3763
3764#define PHY_CTX_SHIFT 6
3765#define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT)
3766#define PHY_CTX_MASK (PHY_CTX_SIZE - 1)
3767#define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT)
3768#define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT)
3769
3770#define MB_KERNEL_CTX_SHIFT 8
3771#define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT)
3772#define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1)
3773#define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT))
3774
3775#define MAX_CID_CNT 0x4000
3776#define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT))
3777#define INVALID_CID_ADDR 0xffffffff
3778
3779#define TX_CID 16
3780#define RX_CID 0
3781
3782#define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID)
3783#define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID)
3784
3785struct sw_bd {
3786 struct sk_buff *skb;
3787 DECLARE_PCI_UNMAP_ADDR(mapping)
3788};
3789
3790/* Buffered flash (Atmel: AT45DB011B) specific information */
3791#define SEEPROM_PAGE_BITS 2
3792#define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS)
3793#define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1)
3794#define SEEPROM_PAGE_SIZE 4
3795#define SEEPROM_TOTAL_SIZE 65536
3796
3797#define BUFFERED_FLASH_PAGE_BITS 9
3798#define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS)
3799#define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1)
3800#define BUFFERED_FLASH_PAGE_SIZE 264
3801#define BUFFERED_FLASH_TOTAL_SIZE 131072
3802
3803#define SAIFUN_FLASH_PAGE_BITS 8
3804#define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS)
3805#define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1)
3806#define SAIFUN_FLASH_PAGE_SIZE 256
3807#define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536
3808
3809#define NVRAM_TIMEOUT_COUNT 30000
3810
3811
3812#define FLASH_STRAP_MASK (BNX2_NVM_CFG1_FLASH_MODE | \
3813 BNX2_NVM_CFG1_BUFFER_MODE | \
3814 BNX2_NVM_CFG1_PROTECT_MODE | \
3815 BNX2_NVM_CFG1_FLASH_SIZE)
3816
3817struct flash_spec {
3818 u32 strapping;
3819 u32 config1;
3820 u32 config2;
3821 u32 config3;
3822 u32 write1;
3823 u32 buffered;
3824 u32 page_bits;
3825 u32 page_size;
3826 u32 addr_mask;
3827 u32 total_size;
3828 u8 *name;
3829};
3830
3831struct bnx2 {
3832 /* Fields used in the tx and intr/napi performance paths are grouped */
3833 /* together in the beginning of the structure. */
3834 void __iomem *regview;
3835
3836 struct net_device *dev;
3837 struct pci_dev *pdev;
3838
3839 atomic_t intr_sem;
3840
3841 struct status_block *status_blk;
3842 u32 last_status_idx;
3843
3844 atomic_t tx_avail_bd;
3845 struct tx_bd *tx_desc_ring;
3846 struct sw_bd *tx_buf_ring;
3847 u32 tx_prod_bseq;
3848 u16 tx_prod;
3849 u16 tx_cons;
3850
3851#ifdef BCM_VLAN
3852 struct vlan_group *vlgrp;
3853#endif
3854
3855 u32 rx_offset;
3856 u32 rx_buf_use_size; /* useable size */
3857 u32 rx_buf_size; /* with alignment */
3858 struct rx_bd *rx_desc_ring;
3859 struct sw_bd *rx_buf_ring;
3860 u32 rx_prod_bseq;
3861 u16 rx_prod;
3862 u16 rx_cons;
3863
3864 u32 rx_csum;
3865
3866 /* Only used to synchronize netif_stop_queue/wake_queue when tx */
3867 /* ring is full */
3868 spinlock_t tx_lock;
3869
3870 /* End of fileds used in the performance code paths. */
3871
3872 char *name;
3873
3874 int timer_interval;
3875 struct timer_list timer;
3876 struct work_struct reset_task;
3877
3878 /* Used to synchronize phy accesses. */
3879 spinlock_t phy_lock;
3880
3881 u32 flags;
3882#define PCIX_FLAG 1
3883#define PCI_32BIT_FLAG 2
3884#define ONE_TDMA_FLAG 4 /* no longer used */
3885#define NO_WOL_FLAG 8
3886#define USING_DAC_FLAG 0x10
3887#define USING_MSI_FLAG 0x20
3888
3889 u32 phy_flags;
3890#define PHY_SERDES_FLAG 1
3891#define PHY_CRC_FIX_FLAG 2
3892#define PHY_PARALLEL_DETECT_FLAG 4
3893#define PHY_INT_MODE_MASK_FLAG 0x300
3894#define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100
3895#define PHY_INT_MODE_LINK_READY_FLAG 0x200
3896
3897 u32 chip_id;
3898 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
3899#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000)
3900#define CHIP_NUM_5706 0x57060000
3901
3902#define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000)
3903#define CHIP_REV_Ax 0x00000000
3904#define CHIP_REV_Bx 0x00001000
3905#define CHIP_REV_Cx 0x00002000
3906
3907#define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0)
3908#define CHIP_BONDING(bp) (((bp)->chip_id) & 0x0000000f)
3909
3910#define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0)
3911#define CHIP_ID_5706_A0 0x57060000
3912#define CHIP_ID_5706_A1 0x57060010
3913
3914#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0xf)
3915
3916/* A serdes chip will have the first bit of the bond id set. */
3917#define CHIP_BOND_ID_SERDES_BIT 0x01
3918
3919 u32 phy_addr;
3920 u32 phy_id;
3921
3922 u16 bus_speed_mhz;
3923 u8 wol;
3924
3925 u8 fw_timed_out;
3926
3927 u16 fw_wr_seq;
3928 u16 fw_drv_pulse_wr_seq;
3929
3930 int tx_ring_size;
3931 dma_addr_t tx_desc_mapping;
3932
3933
3934 int rx_ring_size;
3935 dma_addr_t rx_desc_mapping;
3936
3937 u16 tx_quick_cons_trip;
3938 u16 tx_quick_cons_trip_int;
3939 u16 rx_quick_cons_trip;
3940 u16 rx_quick_cons_trip_int;
3941 u16 comp_prod_trip;
3942 u16 comp_prod_trip_int;
3943 u16 tx_ticks;
3944 u16 tx_ticks_int;
3945 u16 com_ticks;
3946 u16 com_ticks_int;
3947 u16 cmd_ticks;
3948 u16 cmd_ticks_int;
3949 u16 rx_ticks;
3950 u16 rx_ticks_int;
3951
3952 u32 stats_ticks;
3953
3954 dma_addr_t status_blk_mapping;
3955
3956 struct statistics_block *stats_blk;
3957 dma_addr_t stats_blk_mapping;
3958
3959 u32 rx_mode;
3960
3961 u16 req_line_speed;
3962 u8 req_duplex;
3963
3964 u8 link_up;
3965
3966 u16 line_speed;
3967 u8 duplex;
3968 u8 flow_ctrl; /* actual flow ctrl settings */
3969 /* may be different from */
3970 /* req_flow_ctrl if autoneg */
3971#define FLOW_CTRL_TX 1
3972#define FLOW_CTRL_RX 2
3973
3974 u32 advertising;
3975
3976 u8 req_flow_ctrl; /* flow ctrl advertisement */
3977 /* settings or forced */
3978 /* settings */
3979 u8 autoneg;
3980#define AUTONEG_SPEED 1
3981#define AUTONEG_FLOW_CTRL 2
3982
3983 u8 loopback;
3984#define MAC_LOOPBACK 1
3985#define PHY_LOOPBACK 2
3986
3987 u8 serdes_an_pending;
3988#define SERDES_AN_TIMEOUT (2 * HZ)
3989
3990 u8 mac_addr[8];
3991
3992 u32 fw_ver;
3993
3994 int pm_cap;
3995 int pcix_cap;
3996
3997 struct net_device_stats net_stats;
3998
3999 struct flash_spec *flash_info;
4000};
4001
4002static u32 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset);
4003static void bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val);
4004
4005#define REG_RD(bp, offset) \
4006 readl(bp->regview + offset)
4007
4008#define REG_WR(bp, offset, val) \
4009 writel(val, bp->regview + offset)
4010
4011#define REG_WR16(bp, offset, val) \
4012 writew(val, bp->regview + offset)
4013
4014#define REG_RD_IND(bp, offset) \
4015 bnx2_reg_rd_ind(bp, offset)
4016
4017#define REG_WR_IND(bp, offset, val) \
4018 bnx2_reg_wr_ind(bp, offset, val)
4019
4020/* Indirect context access. Unlike the MBQ_WR, these macros will not
4021 * trigger a chip event. */
4022static void bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val);
4023
4024#define CTX_WR(bp, cid_addr, offset, val) \
4025 bnx2_ctx_wr(bp, cid_addr, offset, val)
4026
4027struct cpu_reg {
4028 u32 mode;
4029 u32 mode_value_halt;
4030 u32 mode_value_sstep;
4031
4032 u32 state;
4033 u32 state_value_clear;
4034
4035 u32 gpr0;
4036 u32 evmask;
4037 u32 pc;
4038 u32 inst;
4039 u32 bp;
4040
4041 u32 spad_base;
4042
4043 u32 mips_view_base;
4044};
4045
4046struct fw_info {
4047 u32 ver_major;
4048 u32 ver_minor;
4049 u32 ver_fix;
4050
4051 u32 start_addr;
4052
4053 /* Text section. */
4054 u32 text_addr;
4055 u32 text_len;
4056 u32 text_index;
4057 u32 *text;
4058
4059 /* Data section. */
4060 u32 data_addr;
4061 u32 data_len;
4062 u32 data_index;
4063 u32 *data;
4064
4065 /* SBSS section. */
4066 u32 sbss_addr;
4067 u32 sbss_len;
4068 u32 sbss_index;
4069 u32 *sbss;
4070
4071 /* BSS section. */
4072 u32 bss_addr;
4073 u32 bss_len;
4074 u32 bss_index;
4075 u32 *bss;
4076
4077 /* Read-only section. */
4078 u32 rodata_addr;
4079 u32 rodata_len;
4080 u32 rodata_index;
4081 u32 *rodata;
4082};
4083
4084#define RV2P_PROC1 0
4085#define RV2P_PROC2 1
4086
4087
4088/* This value (in milliseconds) determines the frequency of the driver
4089 * issuing the PULSE message code. The firmware monitors this periodic
4090 * pulse to determine when to switch to an OS-absent mode. */
4091#define DRV_PULSE_PERIOD_MS 250
4092
4093/* This value (in milliseconds) determines how long the driver should
4094 * wait for an acknowledgement from the firmware before timing out. Once
4095 * the firmware has timed out, the driver will assume there is no firmware
4096 * running and there won't be any firmware-driver synchronization during a
4097 * driver reset. */
4098#define FW_ACK_TIME_OUT_MS 50
4099
4100
4101#define BNX2_DRV_RESET_SIGNATURE 0x00000000
4102#define BNX2_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */
4103//#define DRV_RESET_SIGNATURE_MAGIC 0x47495352 /* RSIG */
4104
4105#define BNX2_DRV_MB 0x00000004
4106#define BNX2_DRV_MSG_CODE 0xff000000
4107#define BNX2_DRV_MSG_CODE_RESET 0x01000000
4108#define BNX2_DRV_MSG_CODE_UNLOAD 0x02000000
4109#define BNX2_DRV_MSG_CODE_SHUTDOWN 0x03000000
4110#define BNX2_DRV_MSG_CODE_SUSPEND_WOL 0x04000000
4111#define BNX2_DRV_MSG_CODE_FW_TIMEOUT 0x05000000
4112#define BNX2_DRV_MSG_CODE_PULSE 0x06000000
4113#define BNX2_DRV_MSG_CODE_DIAG 0x07000000
4114#define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000
4115
4116#define BNX2_DRV_MSG_DATA 0x00ff0000
4117#define BNX2_DRV_MSG_DATA_WAIT0 0x00010000
4118#define BNX2_DRV_MSG_DATA_WAIT1 0x00020000
4119#define BNX2_DRV_MSG_DATA_WAIT2 0x00030000
4120#define BNX2_DRV_MSG_DATA_WAIT3 0x00040000
4121
4122#define BNX2_DRV_MSG_SEQ 0x0000ffff
4123
4124#define BNX2_FW_MB 0x00000008
4125#define BNX2_FW_MSG_ACK 0x0000ffff
4126#define BNX2_FW_MSG_STATUS_MASK 0x00ff0000
4127#define BNX2_FW_MSG_STATUS_OK 0x00000000
4128#define BNX2_FW_MSG_STATUS_FAILURE 0x00ff0000
4129
4130#define BNX2_LINK_STATUS 0x0000000c
4131
4132#define BNX2_DRV_PULSE_MB 0x00000010
4133#define BNX2_DRV_PULSE_SEQ_MASK 0x0000ffff
4134
4135/* Indicate to the firmware not to go into the
4136 * OS absent when it is not getting driver pulse.
4137 * This is used for debugging. */
4138#define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00010000
4139
4140#define BNX2_DEV_INFO_SIGNATURE 0x00000020
4141#define BNX2_DEV_INFO_SIGNATURE_MAGIC 0x44564900
4142#define BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00
4143#define BNX2_DEV_INFO_FEATURE_CFG_VALID 0x01
4144#define BNX2_DEV_INFO_SECONDARY_PORT 0x80
4145#define BNX2_DEV_INFO_DRV_ALWAYS_ALIVE 0x40
4146
4147#define BNX2_SHARED_HW_CFG_PART_NUM 0x00000024
4148
4149#define BNX2_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034
4150#define BNX2_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000
4151#define BNX2_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000
4152#define BNX2_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00
4153#define BNX2_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff
4154
4155#define BNX2_SHARED_HW_CFG POWER_CONSUMED 0x00000038
4156#define BNX2_SHARED_HW_CFG_CONFIG 0x0000003c
4157#define BNX2_SHARED_HW_CFG_DESIGN_NIC 0
4158#define BNX2_SHARED_HW_CFG_DESIGN_LOM 0x1
4159#define BNX2_SHARED_HW_CFG_PHY_COPPER 0
4160#define BNX2_SHARED_HW_CFG_PHY_FIBER 0x2
4161#define BNX2_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8
4162#define BNX2_SHARED_HW_CFG_LED_MODE_MASK 0x300
4163#define BNX2_SHARED_HW_CFG_LED_MODE_MAC 0
4164#define BNX2_SHARED_HW_CFG_LED_MODE_GPHY1 0x100
4165#define BNX2_SHARED_HW_CFG_LED_MODE_GPHY2 0x200
4166
4167#define BNX2_DEV_INFO_BC_REV 0x0000004c
4168
4169#define BNX2_PORT_HW_CFG_MAC_UPPER 0x00000050
4170#define BNX2_PORT_HW_CFG_UPPERMAC_MASK 0xffff
4171
4172#define BNX2_PORT_HW_CFG_MAC_LOWER 0x00000054
4173#define BNX2_PORT_HW_CFG_CONFIG 0x00000058
4174
4175#define BNX2_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068
4176#define BNX2_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c
4177#define BNX2_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070
4178#define BNX2_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074
4179#define BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078
4180#define BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c
4181
4182#define BNX2_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4
4183
4184#define BNX2_DEV_INFO_FORMAT_REV 0x000000c4
4185#define BNX2_DEV_INFO_FORMAT_REV_MASK 0xff000000
4186#define BNX2_DEV_INFO_FORMAT_REV_ID ('A' << 24)
4187
4188#define BNX2_SHARED_FEATURE 0x000000c8
4189#define BNX2_SHARED_FEATURE_MASK 0xffffffff
4190
4191#define BNX2_PORT_FEATURE 0x000000d8
4192#define BNX2_PORT2_FEATURE 0x00000014c
4193#define BNX2_PORT_FEATURE_WOL_ENABLED 0x01000000
4194#define BNX2_PORT_FEATURE_MBA_ENABLED 0x02000000
4195#define BNX2_PORT_FEATURE_ASF_ENABLED 0x04000000
4196#define BNX2_PORT_FEATURE_IMD_ENABLED 0x08000000
4197#define BNX2_PORT_FEATURE_BAR1_SIZE_MASK 0xf
4198#define BNX2_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0
4199#define BNX2_PORT_FEATURE_BAR1_SIZE_64K 0x1
4200#define BNX2_PORT_FEATURE_BAR1_SIZE_128K 0x2
4201#define BNX2_PORT_FEATURE_BAR1_SIZE_256K 0x3
4202#define BNX2_PORT_FEATURE_BAR1_SIZE_512K 0x4
4203#define BNX2_PORT_FEATURE_BAR1_SIZE_1M 0x5
4204#define BNX2_PORT_FEATURE_BAR1_SIZE_2M 0x6
4205#define BNX2_PORT_FEATURE_BAR1_SIZE_4M 0x7
4206#define BNX2_PORT_FEATURE_BAR1_SIZE_8M 0x8
4207#define BNX2_PORT_FEATURE_BAR1_SIZE_16M 0x9
4208#define BNX2_PORT_FEATURE_BAR1_SIZE_32M 0xa
4209#define BNX2_PORT_FEATURE_BAR1_SIZE_64M 0xb
4210#define BNX2_PORT_FEATURE_BAR1_SIZE_128M 0xc
4211#define BNX2_PORT_FEATURE_BAR1_SIZE_256M 0xd
4212#define BNX2_PORT_FEATURE_BAR1_SIZE_512M 0xe
4213#define BNX2_PORT_FEATURE_BAR1_SIZE_1G 0xf
4214
4215#define BNX2_PORT_FEATURE_WOL 0xdc
4216#define BNX2_PORT2_FEATURE_WOL 0x150
4217#define BNX2_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4
4218#define BNX2_PORT_FEATURE_WOL_DEFAULT_MASK 0x30
4219#define BNX2_PORT_FEATURE_WOL_DEFAULT_DISABLE 0
4220#define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10
4221#define BNX2_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20
4222#define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30
4223#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf
4224#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0
4225#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1
4226#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2
4227#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3
4228#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4
4229#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5
4230#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6
4231#define BNX2_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40
4232#define BNX2_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400
4233#define BNX2_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800
4234
4235#define BNX2_PORT_FEATURE_MBA 0xe0
4236#define BNX2_PORT2_FEATURE_MBA 0x154
4237#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0
4238#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3
4239#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0
4240#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1
4241#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2
4242#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2
4243#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c
4244#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0
4245#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4
4246#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8
4247#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc
4248#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10
4249#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14
4250#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18
4251#define BNX2_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40
4252#define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0
4253#define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80
4254#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8
4255#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00
4256#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0
4257#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100
4258#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200
4259#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300
4260#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400
4261#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500
4262#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600
4263#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700
4264#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800
4265#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900
4266#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00
4267#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00
4268#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00
4269#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00
4270#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00
4271#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00
4272#define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16
4273#define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000
4274#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20
4275#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000
4276#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0
4277#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000
4278#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000
4279#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000
4280
4281#define BNX2_PORT_FEATURE_IMD 0xe4
4282#define BNX2_PORT2_FEATURE_IMD 0x158
4283#define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0
4284#define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1
4285
4286#define BNX2_PORT_FEATURE_VLAN 0xe8
4287#define BNX2_PORT2_FEATURE_VLAN 0x15c
4288#define BNX2_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff
4289#define BNX2_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000
4290
4291#define BNX2_BC_STATE_RESET_TYPE 0x000001c0
4292#define BNX2_BC_STATE_RESET_TYPE_SIG 0x00005254
4293#define BNX2_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff
4294#define BNX2_BC_STATE_RESET_TYPE_NONE (BNX2_BC_STATE_RESET_TYPE_SIG | \
4295 0x00010000)
4296#define BNX2_BC_STATE_RESET_TYPE_PCI (BNX2_BC_STATE_RESET_TYPE_SIG | \
4297 0x00020000)
4298#define BNX2_BC_STATE_RESET_TYPE_VAUX (BNX2_BC_STATE_RESET_TYPE_SIG | \
4299 0x00030000)
4300#define BNX2_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE
4301#define BNX2_BC_STATE_RESET_TYPE_DRV_RESET (BNX2_BC_STATE_RESET_TYPE_SIG | \
4302 DRV_MSG_CODE_RESET)
4303#define BNX2_BC_STATE_RESET_TYPE_DRV_UNLOAD (BNX2_BC_STATE_RESET_TYPE_SIG | \
4304 DRV_MSG_CODE_UNLOAD)
4305#define BNX2_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BNX2_BC_STATE_RESET_TYPE_SIG | \
4306 DRV_MSG_CODE_SHUTDOWN)
4307#define BNX2_BC_STATE_RESET_TYPE_DRV_WOL (BNX2_BC_STATE_RESET_TYPE_SIG | \
4308 DRV_MSG_CODE_WOL)
4309#define BNX2_BC_STATE_RESET_TYPE_DRV_DIAG (BNX2_BC_STATE_RESET_TYPE_SIG | \
4310 DRV_MSG_CODE_DIAG)
4311#define BNX2_BC_STATE_RESET_TYPE_VALUE(msg) (BNX2_BC_STATE_RESET_TYPE_SIG | \
4312 (msg))
4313
4314#define BNX2_BC_STATE 0x000001c4
4315#define BNX2_BC_STATE_ERR_MASK 0x0000ff00
4316#define BNX2_BC_STATE_SIGN 0x42530000
4317#define BNX2_BC_STATE_SIGN_MASK 0xffff0000
4318#define BNX2_BC_STATE_BC1_START (BNX2_BC_STATE_SIGN | 0x1)
4319#define BNX2_BC_STATE_GET_NVM_CFG1 (BNX2_BC_STATE_SIGN | 0x2)
4320#define BNX2_BC_STATE_PROG_BAR (BNX2_BC_STATE_SIGN | 0x3)
4321#define BNX2_BC_STATE_INIT_VID (BNX2_BC_STATE_SIGN | 0x4)
4322#define BNX2_BC_STATE_GET_NVM_CFG2 (BNX2_BC_STATE_SIGN | 0x5)
4323#define BNX2_BC_STATE_APPLY_WKARND (BNX2_BC_STATE_SIGN | 0x6)
4324#define BNX2_BC_STATE_LOAD_BC2 (BNX2_BC_STATE_SIGN | 0x7)
4325#define BNX2_BC_STATE_GOING_BC2 (BNX2_BC_STATE_SIGN | 0x8)
4326#define BNX2_BC_STATE_GOING_DIAG (BNX2_BC_STATE_SIGN | 0x9)
4327#define BNX2_BC_STATE_RT_FINAL_INIT (BNX2_BC_STATE_SIGN | 0x81)
4328#define BNX2_BC_STATE_RT_WKARND (BNX2_BC_STATE_SIGN | 0x82)
4329#define BNX2_BC_STATE_RT_DRV_PULSE (BNX2_BC_STATE_SIGN | 0x83)
4330#define BNX2_BC_STATE_RT_FIOEVTS (BNX2_BC_STATE_SIGN | 0x84)
4331#define BNX2_BC_STATE_RT_DRV_CMD (BNX2_BC_STATE_SIGN | 0x85)
4332#define BNX2_BC_STATE_RT_LOW_POWER (BNX2_BC_STATE_SIGN | 0x86)
4333#define BNX2_BC_STATE_RT_SET_WOL (BNX2_BC_STATE_SIGN | 0x87)
4334#define BNX2_BC_STATE_RT_OTHER_FW (BNX2_BC_STATE_SIGN | 0x88)
4335#define BNX2_BC_STATE_RT_GOING_D3 (BNX2_BC_STATE_SIGN | 0x89)
4336#define BNX2_BC_STATE_ERR_BAD_VERSION (BNX2_BC_STATE_SIGN | 0x0100)
4337#define BNX2_BC_STATE_ERR_BAD_BC2_CRC (BNX2_BC_STATE_SIGN | 0x0200)
4338#define BNX2_BC_STATE_ERR_BC1_LOOP (BNX2_BC_STATE_SIGN | 0x0300)
4339#define BNX2_BC_STATE_ERR_UNKNOWN_CMD (BNX2_BC_STATE_SIGN | 0x0400)
4340#define BNX2_BC_STATE_ERR_DRV_DEAD (BNX2_BC_STATE_SIGN | 0x0500)
4341#define BNX2_BC_STATE_ERR_NO_RXP (BNX2_BC_STATE_SIGN | 0x0600)
4342#define BNX2_BC_STATE_ERR_TOO_MANY_RBUF (BNX2_BC_STATE_SIGN | 0x0700)
4343
4344#define BNX2_BC_STATE_DEBUG_CMD 0x1dc
4345#define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000
4346#define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000
4347#define BNX2_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff
4348#define BNX2_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff
4349
4350#define HOST_VIEW_SHMEM_BASE 0x167c00
4351
4352#endif
diff --git a/drivers/net/bnx2_fw.h b/drivers/net/bnx2_fw.h
new file mode 100644
index 000000000000..35f3a2ae5ef1
--- /dev/null
+++ b/drivers/net/bnx2_fw.h
@@ -0,0 +1,2468 @@
1/* bnx2_fw.h: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004, 2005 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, except as noted below.
8 *
9 * This file contains firmware data derived from proprietary unpublished
10 * source code, Copyright (c) 2004, 2005 Broadcom Corporation.
11 *
12 * Permission is hereby granted for the distribution of this firmware data
13 * in hexadecimal or equivalent format, provided this copyright notice is
14 * accompanying it.
15 */
16
17
18static int bnx2_COM_b06FwReleaseMajor = 0x0;
19static int bnx2_COM_b06FwReleaseMinor = 0x0;
20static int bnx2_COM_b06FwReleaseFix = 0x0;
21static u32 bnx2_COM_b06FwStartAddr = 0x080004a0;
22static u32 bnx2_COM_b06FwTextAddr = 0x08000000;
23static int bnx2_COM_b06FwTextLen = 0x4594;
24static u32 bnx2_COM_b06FwDataAddr = 0x080045e0;
25static int bnx2_COM_b06FwDataLen = 0x0;
26static u32 bnx2_COM_b06FwRodataAddr = 0x08004598;
27static int bnx2_COM_b06FwRodataLen = 0x18;
28static u32 bnx2_COM_b06FwBssAddr = 0x08004600;
29static int bnx2_COM_b06FwBssLen = 0x88;
30static u32 bnx2_COM_b06FwSbssAddr = 0x080045e0;
31static int bnx2_COM_b06FwSbssLen = 0x1c;
32static u32 bnx2_COM_b06FwText[(0x4594/4) + 1] = {
33 0x0a000128, 0x00000000, 0x00000000, 0x0000000d, 0x636f6d20, 0x302e362e,
34 0x39000000, 0x00060902, 0x00000000, 0x00000003, 0x00000014, 0x00000032,
35 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
36 0x00000010, 0x000003e8, 0x0000ea60, 0x00000001, 0x00000000, 0x00000000,
37 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
38 0x0000ffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
39 0x00000000, 0x00000000, 0x00000002, 0x00000020, 0x00000000, 0x00000000,
40 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
41 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
42 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
43 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
44 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
45 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
46 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
47 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
48 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
49 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
50 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
51 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
52 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
53 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
54 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
55 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
56 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
57 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
58 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
59 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
60 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
61 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
62 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
63 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
64 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
65 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
66 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
67 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
68 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
69 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
70 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
71 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
72 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
73 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
74 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
75 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
76 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
77 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
78 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
79 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
80 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
81 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
82 0x00000000, 0x00000000, 0x00000000, 0x10000003, 0x00000000, 0x0000000d,
83 0x0000000d, 0x3c020800, 0x244245e0, 0x3c030800, 0x24634688, 0xac400000,
84 0x0043202b, 0x1480fffd, 0x24420004, 0x3c1d0800, 0x37bd7ffc, 0x03a0f021,
85 0x3c100800, 0x261004a0, 0x3c1c0800, 0x279c45e0, 0x0e0001f2, 0x00000000,
86 0x0000000d, 0x27bdffe8, 0x3c1a8000, 0x3c020008, 0x0342d825, 0x3c036010,
87 0xafbf0010, 0x8c655000, 0x3c020800, 0x24470ac8, 0x3c040800, 0x24864600,
88 0x2402ff7f, 0x00a22824, 0x34a5380c, 0xac655000, 0x00002821, 0x24020037,
89 0x24030c80, 0xaf420008, 0xaf430024, 0xacc70000, 0x24a50001, 0x2ca20016,
90 0x1440fffc, 0x24c60004, 0x24844600, 0x3c020800, 0x24420ad4, 0x3c030800,
91 0x246309d4, 0xac820004, 0x3c020800, 0x24420618, 0x3c050800, 0x24a50ca0,
92 0xac82000c, 0x3c020800, 0x24423100, 0xac830008, 0x3c030800, 0x246325c8,
93 0xac820014, 0x3c020800, 0x24422b0c, 0xac830018, 0xac83001c, 0x3c030800,
94 0x24630adc, 0xac820024, 0x3c020800, 0x24423040, 0xac83002c, 0x3c030800,
95 0x24633060, 0xac820030, 0x3c020800, 0x24422f6c, 0xac830034, 0x3c030800,
96 0x24632c60, 0xac82003c, 0x3c020800, 0x24420b6c, 0xac850010, 0xac850020,
97 0xac830040, 0x0e000bd6, 0xac820050, 0x8fbf0010, 0x03e00008, 0x27bd0018,
98 0x27bdffe0, 0xafb00010, 0x27500100, 0xafbf0018, 0xafb10014, 0x9203000b,
99 0x24020003, 0x1462005b, 0x96110008, 0x32220001, 0x10400009, 0x27430080,
100 0x8e020000, 0x96040014, 0x000211c2, 0x00021040, 0x00621821, 0xa4640000,
101 0x0a0001cb, 0x3c020800, 0x3c020800, 0x8c430020, 0x1060002a, 0x3c030800,
102 0x0e001006, 0x00000000, 0x97420108, 0x8f850018, 0x9743010c, 0x3042003e,
103 0x00021400, 0x00621825, 0xaca30000, 0x8f840018, 0x8f420100, 0xac820004,
104 0x97430116, 0x9742010e, 0x8f840018, 0x00031c00, 0x00431025, 0xac820008,
105 0x97430110, 0x97440112, 0x8f850018, 0x00031c00, 0x00832025, 0xaca4000c,
106 0x97420114, 0x8f840018, 0x3042ffff, 0xac820010, 0x8f830018, 0xac600014,
107 0x8f820018, 0x3c030800, 0xac400018, 0x9462466e, 0x8f840018, 0x3c032000,
108 0x00431025, 0xac82001c, 0x0e001044, 0x24040001, 0x3c030800, 0x8c620040,
109 0x24420001, 0xac620040, 0x3c020800, 0x8c430044, 0x32240004, 0x24630001,
110 0x10800017, 0xac430044, 0x8f4202b8, 0x04430007, 0x8e020020, 0x3c040800,
111 0x8c830060, 0x24020001, 0x24630001, 0x0a0001ed, 0xac830060, 0x3c060800,
112 0x8cc4005c, 0xaf420280, 0x96030016, 0x00001021, 0xa7430284, 0x8e050004,
113 0x24840001, 0x3c031000, 0xaf450288, 0xaf4302b8, 0x0a0001ed, 0xacc4005c,
114 0x32220002, 0x0a0001ed, 0x0002102b, 0x3c026000, 0xac400808, 0x0000000d,
115 0x00001021, 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
116 0x27bdffc8, 0xafbf0034, 0xafbe0030, 0xafb7002c, 0xafb60028, 0xafb50024,
117 0xafb40020, 0xafb3001c, 0xafb20018, 0xafb10014, 0x0e00013f, 0xafb00010,
118 0x24110020, 0x24150030, 0x2794000c, 0x27930008, 0x3c124000, 0x3c1e0800,
119 0x3c170800, 0x3c160800, 0x8f820004, 0x3c040800, 0x8c830020, 0x10430004,
120 0x00000000, 0xaf830004, 0x0e00110b, 0x00000000, 0x8f500000, 0x32020007,
121 0x1040fff5, 0x32020001, 0x1040002b, 0x32020002, 0x8f420100, 0xaf420020,
122 0x8f430104, 0xaf4300a8, 0x9342010b, 0x93630000, 0x306300ff, 0x10710005,
123 0x304400ff, 0x10750006, 0x2c820016, 0x0a000227, 0x00000000, 0xaf940000,
124 0x0a000228, 0x2c820016, 0xaf930000, 0x0a000228, 0x00000000, 0xaf800000,
125 0x14400005, 0x00041880, 0x0e0002b2, 0x00000000, 0x0a000234, 0x00000000,
126 0x3c020800, 0x24424600, 0x00621821, 0x8c620000, 0x0040f809, 0x00000000,
127 0x10400005, 0x8fc20034, 0x8f420104, 0x3c016020, 0xac220014, 0x8fc20034,
128 0xaf520138, 0x24420001, 0xafc20034, 0x32020002, 0x10400019, 0x32020004,
129 0x8f420140, 0xaf420020, 0x93630000, 0x306300ff, 0x10710005, 0x00000000,
130 0x10750006, 0x00000000, 0x0a000250, 0x00000000, 0xaf940000, 0x0a000251,
131 0x00000000, 0xaf930000, 0x0a000251, 0x00000000, 0xaf800000, 0x0e0008b9,
132 0x00000000, 0x8ee20038, 0xaf520178, 0x24420001, 0xaee20038, 0x32020004,
133 0x1040ffad, 0x00000000, 0x8f420180, 0xaf420020, 0x93630000, 0x306300ff,
134 0x10710005, 0x00000000, 0x10750006, 0x00000000, 0x0a00026a, 0x00000000,
135 0xaf940000, 0x0a00026b, 0x00000000, 0xaf930000, 0x0a00026b, 0x00000000,
136 0xaf800000, 0x93620000, 0x14510004, 0x8ec2003c, 0x0e000835, 0x00000000,
137 0x8ec2003c, 0xaf5201b8, 0x24420001, 0x0a000206, 0xaec2003c, 0x27bdffe8,
138 0xafbf0010, 0x97420108, 0x24033000, 0x30447000, 0x10830012, 0x28823001,
139 0x10400007, 0x24024000, 0x1080000b, 0x24022000, 0x1082001a, 0x24020001,
140 0x0a000299, 0x00000000, 0x1082000c, 0x24025000, 0x1082000e, 0x00000000,
141 0x0a000299, 0x00000000, 0x0000000d, 0x0a00029b, 0x00001021, 0x0e000300,
142 0x00000000, 0x0a00029b, 0x00001021, 0x0e00048f, 0x00000000, 0x0a00029b,
143 0x00001021, 0x0e000fdf, 0x00000000, 0x0a00029b, 0x00001021, 0x0000000d,
144 0x00001021, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x93620000, 0x24030020,
145 0x304400ff, 0x10830005, 0x24020030, 0x10820007, 0x00000000, 0x0a0002af,
146 0x00000000, 0x2782000c, 0xaf820000, 0x03e00008, 0x00000000, 0x27820008,
147 0xaf820000, 0x03e00008, 0x00000000, 0xaf800000, 0x03e00008, 0x00000000,
148 0x0000000d, 0x03e00008, 0x00001021, 0x03e00008, 0x00001021, 0x27440100,
149 0x94830008, 0x30620004, 0x10400017, 0x30620002, 0x8f4202b8, 0x04430007,
150 0x8c820020, 0x3c040800, 0x8c830060, 0x24020001, 0x24630001, 0x03e00008,
151 0xac830060, 0xaf420280, 0x94830016, 0x3c060800, 0xa7430284, 0x8c850004,
152 0x8cc4005c, 0x00001021, 0x3c031000, 0x24840001, 0xaf450288, 0xaf4302b8,
153 0x03e00008, 0xacc4005c, 0x14400003, 0x3c040800, 0x03e00008, 0x00001021,
154 0x8c830084, 0x24020001, 0x24630001, 0x03e00008, 0xac830084, 0x27450100,
155 0x3c040800, 0x8c820088, 0x94a3000c, 0x24420001, 0x007a1821, 0xac820088,
156 0x8ca40018, 0x90664000, 0xaf440038, 0x8ca2001c, 0x2403fff8, 0x00063600,
157 0x00431024, 0x34420004, 0x3c030005, 0xaf42003c, 0xaf430030, 0x00000000,
158 0x00000000, 0x00000000, 0xaf460404, 0x00000000, 0x00000000, 0x00000000,
159 0x3c020006, 0x34420001, 0xaf420030, 0x00000000, 0x00000000, 0x00000000,
160 0x8f420000, 0x30420010, 0x1040fffd, 0x00001021, 0x03e00008, 0x00000000,
161 0x3c020800, 0x8c430020, 0x27bdffe8, 0xafb00010, 0x27500100, 0x1060001e,
162 0xafbf0014, 0x0e001006, 0x00000000, 0x8f830018, 0x8e020018, 0xac620000,
163 0x8f840018, 0x9602000c, 0xac820004, 0x8f830018, 0xac600008, 0x8f820018,
164 0xac40000c, 0x8f830018, 0xac600010, 0x8f820018, 0xac400014, 0x8f840018,
165 0x3c026000, 0x8c434448, 0xac830018, 0x96020008, 0x3c030800, 0x9464466e,
166 0x8f850018, 0x00021400, 0x00441025, 0x24040001, 0x0e001044, 0xaca2001c,
167 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdffc8, 0xafb3001c,
168 0x00009821, 0xafb7002c, 0x0000b821, 0xafbe0030, 0x0000f021, 0xafb50024,
169 0x27550100, 0xafbf0034, 0xafb60028, 0xafb40020, 0xafb20018, 0xafb10014,
170 0xafb00010, 0x96a20008, 0x8f540100, 0x8eb20018, 0x30420001, 0x10400037,
171 0x02a0b021, 0x8f630054, 0x2642ffff, 0x00431023, 0x18400006, 0x00000000,
172 0x0000000d, 0x00000000, 0x24000128, 0x0a000372, 0x00002021, 0x8f62004c,
173 0x02421023, 0x18400028, 0x00002021, 0x93650120, 0x93640121, 0x3c030800,
174 0x8c62008c, 0x308400ff, 0x24420001, 0x30a500ff, 0x00803821, 0x1485000b,
175 0xac62008c, 0x3c040800, 0x8c830090, 0x24630001, 0xac830090, 0x93620122,
176 0x30420001, 0x00021023, 0x30420005, 0x0a000372, 0x34440004, 0x27660100,
177 0x00041080, 0x00c21021, 0x8c430000, 0x02431823, 0x04600004, 0x24820001,
178 0x30440007, 0x1485fff9, 0x00041080, 0x10870007, 0x3c030800, 0xa3640121,
179 0x8c620094, 0x24040005, 0x24420001, 0x0a000372, 0xac620094, 0x24040004,
180 0x00809821, 0x9362003f, 0x304400ff, 0x38830016, 0x2c630001, 0x38820010,
181 0x2c420001, 0x00621825, 0x1460000c, 0x24020001, 0x38830008, 0x2c630001,
182 0x38820014, 0x2c420001, 0x00621825, 0x14600005, 0x24020001, 0x24020012,
183 0x14820002, 0x00001021, 0x24020001, 0x50400007, 0x8eb10020, 0x8ea20020,
184 0x8f630040, 0x00408821, 0x00431023, 0x5c400001, 0x8f710040, 0x9343010b,
185 0x24020004, 0x54620005, 0x36730080, 0x96a20008, 0x36730002, 0x24170001,
186 0x305e0020, 0x2402fffb, 0x02628024, 0x1200002a, 0x3c030800, 0x8c620030,
187 0x02021024, 0x10400026, 0x3c020800, 0x8c430020, 0x10600024, 0x32620004,
188 0x0e001006, 0x00000000, 0x8f830018, 0x8f420100, 0xac620000, 0x8f840018,
189 0x02201821, 0x32620002, 0xac900004, 0x8f840018, 0x50400001, 0x8ec30014,
190 0xac830008, 0x8f830018, 0x8ec20020, 0xac62000c, 0x8f840018, 0x8f620040,
191 0xac820010, 0x8f830018, 0x8ec20018, 0xac620014, 0x8f840018, 0x3c026000,
192 0x8c434448, 0x3c020800, 0xac830018, 0x9443466e, 0x8f840018, 0x3c024010,
193 0x00621825, 0xac83001c, 0x0e001044, 0x24040001, 0x32620004, 0x10400076,
194 0x00003821, 0x3c029000, 0x34420001, 0x3c038000, 0x02821025, 0xa360007c,
195 0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620023,
196 0x30420080, 0x10400011, 0x00000000, 0x8f65005c, 0x8f63004c, 0x9764003c,
197 0x8f620064, 0x00a32823, 0x00852821, 0x00a2102b, 0x54400006, 0x3c023fff,
198 0x93620023, 0x3042007f, 0xa3620023, 0xaf720064, 0x3c023fff, 0x0a0003f1,
199 0x3442ffff, 0x8f62005c, 0x02421023, 0x04400011, 0x00000000, 0x8f65005c,
200 0x8f630064, 0x9764003c, 0x3c023fff, 0x3442ffff, 0xaf720064, 0x00a32823,
201 0x00852821, 0x0045102b, 0x10400004, 0x02451021, 0x3c053fff, 0x34a5ffff,
202 0x02451021, 0xaf62005c, 0x24070001, 0xaf72004c, 0x8f620054, 0x16420005,
203 0x00000000, 0x93620023, 0x30420040, 0x10400017, 0x24020001, 0x9762006a,
204 0x00022880, 0x50a00001, 0x24050001, 0x97630068, 0x93640081, 0x3c020800,
205 0x8c46004c, 0x00652821, 0x00852804, 0x00c5102b, 0x54400001, 0x00a03021,
206 0x3c020800, 0x8c440050, 0x00c4182b, 0x54600001, 0x00c02021, 0x8f420074,
207 0x2403fffe, 0x00832824, 0x00a21021, 0xaf62000c, 0x3c028000, 0x34420001,
208 0x02821025, 0xa3600081, 0xaf420020, 0x9363007e, 0x9362007a, 0x10620004,
209 0x00000000, 0x0e000f2a, 0x00000000, 0x00403821, 0x10e00017, 0x3c029000,
210 0x34420001, 0x02821025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024,
211 0x1440fffd, 0x3c028000, 0x9363007d, 0x34420001, 0x3c048000, 0x02821025,
212 0xa363007d, 0xaf420020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002,
213 0x3c031000, 0xaf5401c0, 0xa34201c4, 0xaf4301f8, 0x8ea30014, 0x8f620040,
214 0x14430003, 0x00431023, 0x0a000443, 0x00001021, 0x28420001, 0x10400034,
215 0x00000000, 0x8f620040, 0xaf630040, 0x9362003e, 0x30420001, 0x1440000b,
216 0x3c029000, 0x93620022, 0x24420001, 0xa3620022, 0x93630022, 0x3c020800,
217 0x8c440098, 0x0064182b, 0x1460001e, 0x3c020800, 0x3c029000, 0x34420001,
218 0x02821025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd,
219 0x00000000, 0x3c038000, 0x9362007d, 0x34630001, 0x3c048000, 0x02831825,
220 0x34420001, 0xa362007d, 0xaf430020, 0x8f4201f8, 0x00441024, 0x1440fffd,
221 0x24020002, 0x3c031000, 0xaf5401c0, 0xa34201c4, 0x24020001, 0xaf4301f8,
222 0xa7620012, 0x0a000476, 0xa3600022, 0x9743007a, 0x9444002a, 0x00641821,
223 0x3063fffe, 0xa7630012, 0x0e000b68, 0x00000000, 0x12e00003, 0x00000000,
224 0x0e000f27, 0x00000000, 0x53c00004, 0x96a20008, 0x0e000c10, 0x00000000,
225 0x96a20008, 0x8fbf0034, 0x8fbe0030, 0x8fb7002c, 0x8fb60028, 0x8fb50024,
226 0x8fb40020, 0x8fb3001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x00021042,
227 0x30420001, 0x03e00008, 0x27bd0038, 0x27bdffe8, 0xafbf0010, 0x97420108,
228 0x2403000b, 0x304400ff, 0x1083004e, 0x2882000c, 0x10400011, 0x24020006,
229 0x1082003e, 0x28820007, 0x10400007, 0x28820008, 0x1080002b, 0x24020001,
230 0x1082002e, 0x3c026000, 0x0a000504, 0x00000000, 0x14400061, 0x2882000a,
231 0x1440002b, 0x00000000, 0x0a0004ec, 0x00000000, 0x2402001c, 0x1082004e,
232 0x2882001d, 0x1040000e, 0x24020019, 0x10820041, 0x2882001a, 0x10400005,
233 0x2402000e, 0x10820036, 0x00000000, 0x0a000504, 0x00000000, 0x2402001b,
234 0x1082003c, 0x00000000, 0x0a000504, 0x00000000, 0x240200c1, 0x10820040,
235 0x288200c2, 0x10400005, 0x24020080, 0x1082001f, 0x00000000, 0x0a000504,
236 0x00000000, 0x240200c2, 0x1082003b, 0x00000000, 0x0a000504, 0x00000000,
237 0x3c026000, 0x0e000c7d, 0xac400808, 0x0a000506, 0x8fbf0010, 0x8c444448,
238 0x3c030800, 0xac640064, 0x0e000c7d, 0x00000000, 0x3c026000, 0x8c444448,
239 0x3c030800, 0x0a000505, 0xac640068, 0x8f440100, 0x0e000508, 0x00000000,
240 0x3c026000, 0x8c444448, 0x3c030800, 0x0a000505, 0xac64006c, 0x0e000cab,
241 0x00000000, 0x0a000506, 0x8fbf0010, 0x8f440100, 0x0e000cd5, 0x00000000,
242 0x0a000506, 0x8fbf0010, 0x0e000d1c, 0x00000000, 0x0a000506, 0x8fbf0010,
243 0x0000000d, 0x0a000506, 0x8fbf0010, 0x0e0005d7, 0x00000000, 0x0a000506,
244 0x8fbf0010, 0x8f440100, 0x0e000d7e, 0x00000000, 0x0a000506, 0x8fbf0010,
245 0x0e000e95, 0x00000000, 0x0a000506, 0x8fbf0010, 0x0e000626, 0x00000000,
246 0x0a000506, 0x8fbf0010, 0x0e000b68, 0x00000000, 0x0a000506, 0x8fbf0010,
247 0x0000000d, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x27bdffe8, 0x3c029000,
248 0x34420001, 0xafb00010, 0x00808021, 0x02021025, 0x3c038000, 0xafbf0014,
249 0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620005,
250 0x34420001, 0xa3620005, 0x8f63004c, 0x8f620054, 0x10620019, 0x3c028000,
251 0x9762006a, 0x00022880, 0x50a00001, 0x24050001, 0x97630068, 0x93640081,
252 0x3c020800, 0x8c46004c, 0x00652821, 0x00852804, 0x00c5102b, 0x54400001,
253 0x00a03021, 0x3c020800, 0x8c440050, 0x00c4182b, 0x54600001, 0x00c02021,
254 0x8f420074, 0x2403fffe, 0x00832824, 0x00a21021, 0xaf62000c, 0x3c028000,
255 0x34420001, 0x02021025, 0x0e000c7d, 0xaf420020, 0x3c029000, 0x34420001,
256 0x3c038000, 0x02021025, 0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd,
257 0x3c028000, 0x9363007d, 0x34420001, 0x3c048000, 0x02021025, 0xa363007d,
258 0xaf420020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x8fbf0014, 0xaf5001c0,
259 0x8fb00010, 0x24020002, 0x3c031000, 0xa34201c4, 0xaf4301f8, 0x03e00008,
260 0x27bd0018, 0x27bdffd8, 0xafbf0020, 0xafb3001c, 0xafb20018, 0xafb10014,
261 0xafb00010, 0x93630005, 0x00809021, 0x24020030, 0x30630030, 0x14620072,
262 0x00a09821, 0x3c020800, 0x8c430020, 0x1060006c, 0x00000000, 0x0e001006,
263 0x00000000, 0x8f820018, 0xac520000, 0x9363003e, 0x9362003f, 0x8f840018,
264 0x00031a00, 0x00431025, 0xac820004, 0x93630081, 0x93620082, 0x8f850018,
265 0x00031e00, 0x00021400, 0x00621825, 0xaca30008, 0x8f840018, 0x8f620040,
266 0xac82000c, 0x8f830018, 0x8f620048, 0xac620010, 0x8f840018, 0x8f62004c,
267 0x3c110800, 0xac820014, 0x8f830018, 0x8f620050, 0x26304660, 0x00002021,
268 0xac620018, 0x9602000e, 0x8f850018, 0x3c03c00b, 0x00431025, 0x0e001044,
269 0xaca2001c, 0x8f830018, 0x8f620054, 0xac620000, 0x8f840018, 0x8f620058,
270 0xac820004, 0x8f830018, 0x8f62005c, 0xac620008, 0x8f840018, 0x8f620060,
271 0xac82000c, 0x8f850018, 0x8f620064, 0xaca20010, 0x97630068, 0x9762006a,
272 0x8f840018, 0x00031c00, 0x00431025, 0xac820014, 0x8f830018, 0x00002021,
273 0xac600018, 0x9602000e, 0x8f850018, 0x3c03c00c, 0x00431025, 0x0e001044,
274 0xaca2001c, 0x8f840018, 0x8f630018, 0xac830000, 0x936200c4, 0x30420002,
275 0x10400006, 0x00000000, 0x976200c8, 0x8f830018, 0x3042ffff, 0x0a0005b5,
276 0xac620004, 0x8f820018, 0xac400004, 0x8f830018, 0x8f62006c, 0xac620008,
277 0x8f840018, 0x8f6200dc, 0xac82000c, 0x8f830018, 0xac600010, 0x93620005,
278 0x8f830018, 0x00021600, 0x00531025, 0xac620014, 0x8f850018, 0x3c026000,
279 0x8c434448, 0x24040001, 0x26224660, 0xaca30018, 0x9443000e, 0x8f850018,
280 0x3c02400d, 0x00621825, 0x0e001044, 0xaca3001c, 0x0e000d48, 0x02402021,
281 0x8fbf0020, 0x8fb3001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
282 0x27bd0028, 0x27bdffe0, 0xafb00010, 0x27500100, 0xafbf0018, 0xafb10014,
283 0x9603000c, 0x240200c1, 0x5462001d, 0x8e040000, 0x3c029000, 0x8f440100,
284 0x34420001, 0x3c038000, 0x00821025, 0xaf420020, 0x8f420020, 0x00431024,
285 0x1440fffd, 0x00000000, 0x3c038000, 0x9362007d, 0x34630001, 0x3c058000,
286 0x00831825, 0x34420004, 0xa362007d, 0xaf430020, 0x8f4201f8, 0x00451024,
287 0x1440fffd, 0x24020002, 0x3c031000, 0xaf4401c0, 0xa34201c4, 0xaf4301f8,
288 0x0a000622, 0x8fbf0018, 0x8f65004c, 0x24060001, 0x0e000db5, 0x2407049f,
289 0x3c020800, 0x8c430020, 0x9611000c, 0x1060001d, 0x8e100000, 0x0e001006,
290 0x00000000, 0x8f820018, 0xac500000, 0x8f840018, 0x00111400, 0xac820004,
291 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010,
292 0x8f840018, 0x240204a2, 0xac820014, 0x8f850018, 0x3c026000, 0x8c434448,
293 0x24040001, 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018, 0x3c024019,
294 0x00621825, 0x0e001044, 0xaca3001c, 0x8fbf0018, 0x8fb10014, 0x8fb00010,
295 0x03e00008, 0x27bd0020, 0x27bdffb0, 0xafb1002c, 0x27510100, 0xafbf004c,
296 0xafbe0048, 0xafb70044, 0xafb60040, 0xafb5003c, 0xafb40038, 0xafb30034,
297 0xafb20030, 0xafb00028, 0x8e350000, 0x9634000c, 0x3c026000, 0x8c434448,
298 0x0000f021, 0xaf630170, 0x8f620040, 0x8e230014, 0x0000b821, 0x00431023,
299 0x044001ec, 0x0000b021, 0x32820010, 0x1040002e, 0x3c026000, 0x9363003f,
300 0x9222000e, 0x10430006, 0x2402000c, 0x9223000f, 0x10620003, 0x24020014,
301 0x14620025, 0x3c026000, 0x32820004, 0x10400007, 0x241e0001, 0x8f620050,
302 0x24420001, 0xaf620050, 0x8f630054, 0x24630001, 0xaf630054, 0x32830102,
303 0x24020002, 0x5462000d, 0x9222000f, 0x8f620040, 0x24420001, 0xaf620040,
304 0x8f630048, 0x8f620040, 0x24630001, 0x54620005, 0x9222000f, 0x8f620048,
305 0x24420001, 0xaf620048, 0x9222000f, 0xa362003f, 0x9223000f, 0x24020012,
306 0x14620007, 0x3c026000, 0x3c030800, 0x8c620074, 0x24420001, 0x0e000f6e,
307 0xac620074, 0x3c026000, 0x8c434448, 0x32820040, 0xaf630174, 0x32830020,
308 0xafa30010, 0x32830080, 0xafa30014, 0x32830001, 0xafa3001c, 0x32830008,
309 0xafa30020, 0x32830100, 0x104000bb, 0xafa30018, 0x8e260010, 0x8f630054,
310 0x24c2ffff, 0x00431023, 0x18400006, 0x00000000, 0x0000000d, 0x00000000,
311 0x24000128, 0x0a0006b2, 0x00009021, 0x8f62004c, 0x00c21023, 0x18400028,
312 0x00009021, 0x93650120, 0x93640121, 0x3c030800, 0x8c62008c, 0x308400ff,
313 0x24420001, 0x30a500ff, 0x00804021, 0x1485000b, 0xac62008c, 0x3c040800,
314 0x8c830090, 0x24630001, 0xac830090, 0x93620122, 0x30420001, 0x00021023,
315 0x30420005, 0x0a0006b2, 0x34520004, 0x27670100, 0x00041080, 0x00e21021,
316 0x8c430000, 0x00c31823, 0x04600004, 0x24820001, 0x30440007, 0x1485fff9,
317 0x00041080, 0x10880007, 0x3c030800, 0xa3640121, 0x8c620094, 0x24120005,
318 0x24420001, 0x0a0006b2, 0xac620094, 0x24120004, 0x32420001, 0x10400020,
319 0x3c020800, 0x8c430020, 0x8e300000, 0x1060001c, 0x8e330010, 0x0e001006,
320 0x00000000, 0x8f820018, 0xac500000, 0x8f840018, 0x24020001, 0xac820004,
321 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010,
322 0x8f820018, 0xac530014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001,
323 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018, 0x3c024010, 0x00621825,
324 0x0e001044, 0xaca3001c, 0x32420004, 0x10400060, 0x00003821, 0x3c029000,
325 0x8e260010, 0x34420001, 0x3c038000, 0x02a21025, 0xa360007c, 0xaf420020,
326 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620023, 0x30420080,
327 0x10400011, 0x00000000, 0x8f65005c, 0x8f63004c, 0x9764003c, 0x8f620064,
328 0x00a32823, 0x00852821, 0x00a2102b, 0x54400006, 0x3c023fff, 0x93620023,
329 0x3042007f, 0xa3620023, 0xaf660064, 0x3c023fff, 0x0a000702, 0x3442ffff,
330 0x8f62005c, 0x00c21023, 0x04400011, 0x00000000, 0x8f65005c, 0x8f630064,
331 0x9764003c, 0x3c023fff, 0x3442ffff, 0xaf660064, 0x00a32823, 0x00852821,
332 0x0045102b, 0x10400004, 0x00c51021, 0x3c053fff, 0x34a5ffff, 0x00c51021,
333 0xaf62005c, 0x24070001, 0xaf66004c, 0x8f620054, 0x14c20005, 0x00000000,
334 0x93620023, 0x30420040, 0x10400017, 0x24020001, 0x9762006a, 0x00022880,
335 0x50a00001, 0x24050001, 0x97630068, 0x93640081, 0x3c020800, 0x8c46004c,
336 0x00652821, 0x00852804, 0x00c5102b, 0x54400001, 0x00a03021, 0x3c020800,
337 0x8c440050, 0x00c4182b, 0x54600001, 0x00c02021, 0x8f420074, 0x2403fffe,
338 0x00832824, 0x00a21021, 0xaf62000c, 0x3c028000, 0x34420001, 0x02a21025,
339 0xa3600081, 0xaf420020, 0x9363007e, 0x9362007a, 0x10620005, 0x00e0b021,
340 0x0e000f2a, 0x00000000, 0x00403821, 0x00e0b021, 0x8fa20010, 0x10400008,
341 0x00000000, 0x8e220018, 0xaf620018, 0x8e23001c, 0xaf63001c, 0x8e220020,
342 0x24160001, 0xaf620058, 0x13c00036, 0x32820004, 0x10400035, 0x8fa30014,
343 0x93620023, 0x30420040, 0x10400031, 0x3c020800, 0x8c430020, 0x1060001c,
344 0x8e300000, 0x0e001006, 0x00000000, 0x8f820018, 0xac500000, 0x8f830018,
345 0xac600004, 0x8f820018, 0xac400008, 0x8f830018, 0xac60000c, 0x8f820018,
346 0xac400010, 0x8f830018, 0x24020587, 0xac620014, 0x8f850018, 0x3c026000,
347 0x8c434448, 0x24040001, 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018,
348 0x3c024019, 0x00621825, 0x0e001044, 0xaca3001c, 0x3c029000, 0x34420001,
349 0x02a21025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd,
350 0x24020001, 0xaf62000c, 0x93630023, 0x3c028000, 0x34420001, 0x02a21025,
351 0x306300bf, 0xa3630023, 0xaf420020, 0x8fa30014, 0x10600012, 0x8fa3001c,
352 0x9362007c, 0x24420001, 0xa362007c, 0x9363007e, 0x9362007a, 0x1462000b,
353 0x8fa3001c, 0x9362007c, 0x3c030800, 0x8c640024, 0x0044102b, 0x14400005,
354 0x8fa3001c, 0x0e000f2a, 0x00000000, 0x02c2b025, 0x8fa3001c, 0x3062ffff,
355 0x10400003, 0x32820200, 0x0a000793, 0x24170004, 0x10400003, 0x00000000,
356 0x24170040, 0x24160001, 0x13c0005d, 0x32820002, 0x1040005c, 0x8fa20020,
357 0x9222000a, 0x30420020, 0x10400033, 0x3c100800, 0x93620023, 0x30420040,
358 0x1040002f, 0x8e020020, 0x1040001e, 0x3c029000, 0x0e001006, 0x00000000,
359 0x8f820018, 0xac550000, 0x8f840018, 0x3c02008d, 0xac820004, 0x8f830018,
360 0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010, 0x8f840018,
361 0x240205bf, 0xac820014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001,
362 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018, 0x3c024019, 0x00621825,
363 0x0e001044, 0xaca3001c, 0x3c029000, 0x34420001, 0x02a21025, 0xaf420020,
364 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93630023,
365 0x3c028000, 0x34420001, 0x02a21025, 0x306300bf, 0xa3630023, 0xaf420020,
366 0x8e020020, 0x10400023, 0x8fa20020, 0x0e001006, 0x00000000, 0x8f840018,
367 0x8e230000, 0xac830000, 0x9222000a, 0x8f830018, 0x00021600, 0xac620004,
368 0x8f840018, 0x8f620040, 0xac820008, 0x8f850018, 0x8f63004c, 0xaca3000c,
369 0x9362003f, 0x8f840018, 0x304200ff, 0xac820010, 0x8f830018, 0x3c026000,
370 0xac600014, 0x8f850018, 0x8c434448, 0x24040001, 0x3c020800, 0xaca30018,
371 0x9443466e, 0x8f850018, 0x3c02401a, 0x00621825, 0x0e001044, 0xaca3001c,
372 0x8fa20020, 0x1040000e, 0x8fa20018, 0x9222000a, 0xa3620082, 0x56e00005,
373 0x36f70008, 0x8fa30018, 0x10600004, 0x00000000, 0x36f70008, 0x0a000801,
374 0x24160001, 0x0e000de1, 0x02a02021, 0x8fa20018, 0x10400003, 0x00000000,
375 0x36f70010, 0x24160001, 0x12c00019, 0x3c029000, 0x34420001, 0x02a21025,
376 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000,
377 0x3c038000, 0x9362007d, 0x34630001, 0x3c048000, 0x02a31825, 0x02e21025,
378 0xa362007d, 0xaf430020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002,
379 0x3c031000, 0xaf5501c0, 0xa34201c4, 0xaf4301f8, 0x9363003f, 0x24020012,
380 0x14620004, 0x3c026000, 0x0e000f6e, 0x00000000, 0x3c026000, 0x8c434448,
381 0xaf630178, 0x8fbf004c, 0x8fbe0048, 0x8fb70044, 0x8fb60040, 0x8fb5003c,
382 0x8fb40038, 0x8fb30034, 0x8fb20030, 0x8fb1002c, 0x8fb00028, 0x03e00008,
383 0x27bd0050, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f500180, 0x97420184,
384 0x30420200, 0x14400015, 0x00000000, 0x8f430188, 0x3c02ff00, 0x00621824,
385 0x3c020200, 0x10620031, 0x0043102b, 0x14400007, 0x3c020300, 0x1060000b,
386 0x3c020100, 0x1062000d, 0x00000000, 0x0a0008b4, 0x00000000, 0x10620027,
387 0x3c020400, 0x1062003e, 0x02002021, 0x0a0008b4, 0x00000000, 0x0e000e1e,
388 0x02002021, 0x0a0008b6, 0x8fbf0014, 0x93620005, 0x30420020, 0x1440005e,
389 0x8fbf0014, 0x3c029000, 0x34420001, 0x02021025, 0xaf420020, 0x3c038000,
390 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620005, 0x3c038000,
391 0x34630001, 0x02031825, 0x34420020, 0xa3620005, 0xaf430020, 0x93620005,
392 0x30420020, 0x14400003, 0x02002021, 0x0000000d, 0x02002021, 0x0e000553,
393 0x24055854, 0x0a0008b6, 0x8fbf0014, 0x93620005, 0x30420001, 0x1040003f,
394 0x3c029000, 0x34420001, 0x02021025, 0xaf420020, 0x3c038000, 0x8f420020,
395 0x00431024, 0x1440fffd, 0x00000000, 0x93620005, 0x3c048000, 0x3c030800,
396 0x304200fe, 0xa3620005, 0x8c620020, 0x34840001, 0x02042025, 0xaf440020,
397 0x1040002d, 0x8fbf0014, 0x0a000894, 0x00000000, 0x00002821, 0x00003021,
398 0x0e000f78, 0x240706a4, 0x3c020800, 0x8c430020, 0x10600023, 0x8fbf0014,
399 0x0e001006, 0x00000000, 0x8f820018, 0xac500000, 0x93630082, 0x9362003f,
400 0x8f840018, 0x00031a00, 0x00431025, 0xac820004, 0x8f830018, 0xac600008,
401 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010, 0x8f820018, 0xac400014,
402 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001, 0x3c020800, 0xaca30018,
403 0x9443466e, 0x8f850018, 0x3c02400a, 0x00621825, 0x0e001044, 0xaca3001c,
404 0x0a0008b6, 0x8fbf0014, 0x0000000d, 0x8fbf0014, 0x8fb00010, 0x03e00008,
405 0x27bd0018, 0x27bdffe8, 0xafbf0010, 0x93420148, 0x2444ffff, 0x2c830005,
406 0x10600047, 0x3c020800, 0x24424598, 0x00041880, 0x00621821, 0x8c640000,
407 0x00800008, 0x00000000, 0x8f430144, 0x8f62000c, 0x14620006, 0x24020001,
408 0xaf62000c, 0x0e000909, 0x00000000, 0x0a000907, 0x8fbf0010, 0x8f62000c,
409 0x0a000900, 0x00000000, 0x97630010, 0x8f420144, 0x14430006, 0x24020001,
410 0xa7620010, 0x0e000eeb, 0x00000000, 0x0a000907, 0x8fbf0010, 0x97620010,
411 0x0a000900, 0x00000000, 0x97630012, 0x8f420144, 0x14430006, 0x24020001,
412 0xa7620012, 0x0e000f06, 0x00000000, 0x0a000907, 0x8fbf0010, 0x97620012,
413 0x0a000900, 0x00000000, 0x97630014, 0x8f420144, 0x14430006, 0x24020001,
414 0xa7620014, 0x0e000f21, 0x00000000, 0x0a000907, 0x8fbf0010, 0x97620014,
415 0x0a000900, 0x00000000, 0x97630016, 0x8f420144, 0x14430006, 0x24020001,
416 0xa7620016, 0x0e000f24, 0x00000000, 0x0a000907, 0x8fbf0010, 0x97620016,
417 0x14400006, 0x8fbf0010, 0x3c030800, 0x8c620070, 0x24420001, 0xac620070,
418 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x27bdffe8, 0xafbf0010, 0x93620081,
419 0x3c030800, 0x8c640048, 0x0044102b, 0x14400028, 0x3c029000, 0x8f460140,
420 0x34420001, 0x3c038000, 0x00c21025, 0xaf420020, 0x8f420020, 0x00431024,
421 0x1440fffd, 0x3c048000, 0x34840001, 0x3c059000, 0x34a50001, 0x3c078000,
422 0x24020012, 0x24030080, 0x00c42025, 0x00c52825, 0xa362003f, 0xa3630082,
423 0xaf440020, 0xaf450020, 0x8f420020, 0x00471024, 0x1440fffd, 0x3c038000,
424 0x9362007d, 0x34630001, 0x3c048000, 0x00c31825, 0x34420020, 0xa362007d,
425 0xaf430020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002, 0x3c031000,
426 0x0a00096d, 0xaf4601c0, 0x93620081, 0x24420001, 0x0e000f2a, 0xa3620081,
427 0x9763006a, 0x00032880, 0x14a00002, 0x00403821, 0x24050001, 0x97630068,
428 0x93640081, 0x3c020800, 0x8c46004c, 0x00652821, 0x00852804, 0x00c5102b,
429 0x54400001, 0x00a03021, 0x3c020800, 0x8c440050, 0x00c4182b, 0x54600001,
430 0x00c02021, 0x8f420074, 0x2403fffe, 0x00832824, 0x00a21021, 0xaf62000c,
431 0x10e0001a, 0x3c029000, 0x8f440140, 0x34420001, 0x3c038000, 0x00821025,
432 0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x3c038000,
433 0x9362007d, 0x34630001, 0x3c058000, 0x00831825, 0x34420004, 0xa362007d,
434 0xaf430020, 0x8f4201f8, 0x00451024, 0x1440fffd, 0x24020002, 0x3c031000,
435 0xaf4401c0, 0xa34201c4, 0xaf4301f8, 0x8fbf0010, 0x03e00008, 0x27bd0018,
436 0x27bdffd8, 0xafb3001c, 0x27530100, 0xafbf0024, 0xafb40020, 0xafb20018,
437 0xafb10014, 0xafb00010, 0x96620008, 0x3c140800, 0x8f520100, 0x30420001,
438 0x104000cf, 0x00000000, 0x8e700018, 0x8f630054, 0x2602ffff, 0x00431023,
439 0x18400006, 0x00000000, 0x0000000d, 0x00000000, 0x24000128, 0x0a0009b6,
440 0x00008821, 0x8f62004c, 0x02021023, 0x18400028, 0x00008821, 0x93650120,
441 0x93640121, 0x3c030800, 0x8c62008c, 0x308400ff, 0x24420001, 0x30a500ff,
442 0x00803821, 0x1485000b, 0xac62008c, 0x3c040800, 0x8c830090, 0x24630001,
443 0xac830090, 0x93620122, 0x30420001, 0x00021023, 0x30420005, 0x0a0009b6,
444 0x34510004, 0x27660100, 0x00041080, 0x00c21021, 0x8c430000, 0x02031823,
445 0x04600004, 0x24820001, 0x30440007, 0x1485fff9, 0x00041080, 0x10870007,
446 0x3c030800, 0xa3640121, 0x8c620094, 0x24110005, 0x24420001, 0x0a0009b6,
447 0xac620094, 0x24110004, 0x32220001, 0x1040001e, 0x8e820020, 0x1040001d,
448 0x32220004, 0x0e001006, 0x00000000, 0x8f820018, 0xac520000, 0x8f840018,
449 0x24020001, 0xac820004, 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c,
450 0x8f830018, 0xac600010, 0x8f820018, 0xac500014, 0x8f850018, 0x3c026000,
451 0x8c434448, 0x24040001, 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018,
452 0x3c024010, 0x00621825, 0x0e001044, 0xaca3001c, 0x32220004, 0x10400076,
453 0x00003821, 0x3c029000, 0x34420001, 0x3c038000, 0x02421025, 0xa360007c,
454 0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620023,
455 0x30420080, 0x10400011, 0x00000000, 0x8f65005c, 0x8f63004c, 0x9764003c,
456 0x8f620064, 0x00a32823, 0x00852821, 0x00a2102b, 0x54400006, 0x3c023fff,
457 0x93620023, 0x3042007f, 0xa3620023, 0xaf700064, 0x3c023fff, 0x0a000a03,
458 0x3442ffff, 0x8f62005c, 0x02021023, 0x04400011, 0x00000000, 0x8f65005c,
459 0x8f630064, 0x9764003c, 0x3c023fff, 0x3442ffff, 0xaf700064, 0x00a32823,
460 0x00852821, 0x0045102b, 0x10400004, 0x02051021, 0x3c053fff, 0x34a5ffff,
461 0x02051021, 0xaf62005c, 0x24070001, 0xaf70004c, 0x8f620054, 0x16020005,
462 0x00000000, 0x93620023, 0x30420040, 0x10400017, 0x24020001, 0x9762006a,
463 0x00022880, 0x50a00001, 0x24050001, 0x97630068, 0x93640081, 0x3c020800,
464 0x8c46004c, 0x00652821, 0x00852804, 0x00c5102b, 0x54400001, 0x00a03021,
465 0x3c020800, 0x8c440050, 0x00c4182b, 0x54600001, 0x00c02021, 0x8f420074,
466 0x2403fffe, 0x00832824, 0x00a21021, 0xaf62000c, 0x3c028000, 0x34420001,
467 0x02421025, 0xa3600081, 0xaf420020, 0x9363007e, 0x9362007a, 0x10620004,
468 0x00000000, 0x0e000f2a, 0x00000000, 0x00403821, 0x10e00017, 0x3c029000,
469 0x34420001, 0x02421025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024,
470 0x1440fffd, 0x3c028000, 0x9363007d, 0x34420001, 0x3c048000, 0x02421025,
471 0xa363007d, 0xaf420020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002,
472 0x3c031000, 0xaf5201c0, 0xa34201c4, 0xaf4301f8, 0x9342010b, 0x8e830020,
473 0x27500100, 0x38420006, 0x10600029, 0x2c510001, 0x0e001006, 0x00000000,
474 0x8f830018, 0x8e020000, 0xac620000, 0x8f840018, 0x96020008, 0xac820004,
475 0x8f830018, 0x8e020014, 0xac620008, 0x8f850018, 0x3c026000, 0x8c434448,
476 0xaca3000c, 0x8f840018, 0x96020012, 0xac820010, 0x8f850018, 0x8e030020,
477 0xaca30014, 0x9602000c, 0x9603000e, 0x8f840018, 0x00021400, 0x00431025,
478 0xac820018, 0x12200005, 0x3c020800, 0x9443466e, 0x8f840018, 0x0a000a78,
479 0x3c024013, 0x9443466e, 0x8f840018, 0x3c024014, 0x00621825, 0xac83001c,
480 0x0e001044, 0x24040001, 0x8e630014, 0x8f620040, 0x14430003, 0x00431023,
481 0x0a000a83, 0x00001021, 0x28420001, 0x10400034, 0x00000000, 0x8f620040,
482 0xaf630040, 0x9362003e, 0x30420001, 0x1440000b, 0x3c029000, 0x93620022,
483 0x24420001, 0xa3620022, 0x93630022, 0x3c020800, 0x8c440098, 0x0064182b,
484 0x1460001e, 0x3c020800, 0x3c029000, 0x34420001, 0x02421025, 0xaf420020,
485 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x3c038000,
486 0x9362007d, 0x34630001, 0x3c048000, 0x02431825, 0x34420001, 0xa362007d,
487 0xaf430020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002, 0x3c031000,
488 0xaf5201c0, 0xa34201c4, 0x24020001, 0xaf4301f8, 0xa7620012, 0x0a000ab6,
489 0xa3600022, 0x9743007a, 0x9444002a, 0x00641821, 0x3063fffe, 0xa7630012,
490 0x0e000b68, 0x00000000, 0x97420108, 0x8fbf0024, 0x8fb40020, 0x8fb3001c,
491 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x00021042, 0x30420001, 0x03e00008,
492 0x27bd0028, 0x27bdffe0, 0xafb20018, 0x3c120800, 0x8e420020, 0xafb00010,
493 0x27500100, 0xafbf001c, 0x10400046, 0xafb10014, 0x0e001006, 0x00000000,
494 0x8f840018, 0x8e020000, 0xac820000, 0x936300b1, 0x936200c5, 0x8f850018,
495 0x00031e00, 0x00021400, 0x34420100, 0x00621825, 0xaca30004, 0x8f840018,
496 0x8e02001c, 0xac820008, 0x8f830018, 0x8f620048, 0xac62000c, 0x8f840018,
497 0x96020012, 0xac820010, 0x8f830018, 0x8f620040, 0x24040001, 0xac620014,
498 0x8f850018, 0x3c026000, 0x8c434448, 0x3c020800, 0x24514660, 0xaca30018,
499 0x9623000e, 0x8f850018, 0x3c024016, 0x00621825, 0x0e001044, 0xaca3001c,
500 0x96030008, 0x30630010, 0x1060001c, 0x8e420020, 0x1040001a, 0x8e100000,
501 0x0e001006, 0x00000000, 0x8f820018, 0xac500000, 0x8f830018, 0xac600004,
502 0x8f820018, 0xac400008, 0x8f830018, 0xac60000c, 0x8f820018, 0xac400010,
503 0x8f830018, 0xac600014, 0x8f850018, 0x3c036000, 0x8c634448, 0x24040001,
504 0xaca30018, 0x9622000e, 0x8f850018, 0x3c034015, 0x00431025, 0x0e001044,
505 0xaca2001c, 0x00001021, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010,
506 0x03e00008, 0x27bd0020, 0x27bdffe0, 0xafb20018, 0x3c120800, 0x8e420020,
507 0xafb00010, 0x27500100, 0xafbf001c, 0x10400041, 0xafb10014, 0x0e001006,
508 0x00000000, 0x8f830018, 0x8e020000, 0xac620000, 0x8f840018, 0x24020100,
509 0xac820004, 0x8f830018, 0x8e02001c, 0xac620008, 0x8f840018, 0x8e020018,
510 0xac82000c, 0x8f830018, 0x96020012, 0xac620010, 0x8f840018, 0x96020008,
511 0xac820014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001, 0x3c020800,
512 0x24514660, 0xaca30018, 0x9623000e, 0x8f850018, 0x3c024017, 0x00621825,
513 0x0e001044, 0xaca3001c, 0x96030008, 0x30630010, 0x1060001c, 0x8e420020,
514 0x1040001a, 0x8e100000, 0x0e001006, 0x00000000, 0x8f820018, 0xac500000,
515 0x8f830018, 0xac600004, 0x8f820018, 0xac400008, 0x8f830018, 0xac60000c,
516 0x8f820018, 0xac400010, 0x8f830018, 0xac600014, 0x8f850018, 0x3c036000,
517 0x8c634448, 0x24040001, 0xaca30018, 0x9622000e, 0x8f850018, 0x3c034015,
518 0x00431025, 0x0e001044, 0xaca2001c, 0x00001021, 0x8fbf001c, 0x8fb20018,
519 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x27bdffe8, 0xafbf0010,
520 0x936200c4, 0x30420002, 0x10400019, 0x00000000, 0x936200c5, 0x936300b1,
521 0x00431023, 0x304400ff, 0x30830080, 0x10600004, 0x00000000, 0x0000000d,
522 0x00000000, 0x24000a6a, 0x93620004, 0x00441023, 0x304400ff, 0x30830080,
523 0x10600004, 0x2482ffff, 0x8f650024, 0x0a000b82, 0x00000000, 0x00022b00,
524 0x8f620024, 0x0045102b, 0x10400002, 0x00000000, 0x8f650024, 0x8f620048,
525 0x8f630040, 0x00431823, 0x0065202b, 0x10800004, 0x00000000, 0x8f620040,
526 0x00451021, 0xaf620048, 0x9762003c, 0x0062102b, 0x10400041, 0x8fbf0010,
527 0x10a0003f, 0x3c029000, 0x34420001, 0x3c040800, 0x8c830080, 0x8f450100,
528 0x3c068000, 0x24630001, 0x00a21025, 0xac830080, 0xaf420020, 0x8f420020,
529 0x00461024, 0x1440fffd, 0x3c038000, 0x9362007d, 0x34630001, 0x3c048000,
530 0x00a31825, 0x34420004, 0xa362007d, 0xaf430020, 0x8f4201f8, 0x00441024,
531 0x1440fffd, 0x24020002, 0x3c030800, 0xaf4501c0, 0xa34201c4, 0x8c640020,
532 0x3c021000, 0xaf4201f8, 0x1080001f, 0x8fbf0010, 0x0e001006, 0x00000000,
533 0x8f830018, 0x8f420100, 0xac620000, 0x8f840018, 0x8f620040, 0xac820004,
534 0x8f850018, 0x8f620048, 0xaca20008, 0x8f830018, 0xac60000c, 0x8f820018,
535 0xac400010, 0x8f830018, 0x3c026000, 0xac600014, 0x8f840018, 0x8c434448,
536 0x3c020800, 0xac830018, 0x9443466e, 0x8f840018, 0x3c0240c2, 0x00621825,
537 0xac83001c, 0x0e001044, 0x24040001, 0x8fbf0010, 0x03e00008, 0x27bd0018,
538 0x3c020800, 0x24423958, 0xaf82000c, 0x03e00008, 0x00000000, 0x27bdffe8,
539 0xafb00010, 0x27500100, 0xafbf0014, 0x8e02001c, 0x14400003, 0x3c020800,
540 0x0000000d, 0x3c020800, 0x8c430020, 0x10600026, 0x00001021, 0x0e001006,
541 0x00000000, 0x8f830018, 0x8e020000, 0xac620000, 0x8f840018, 0x8e02001c,
542 0xac820004, 0x8f830018, 0xac600008, 0x8f840018, 0x8e020018, 0xac82000c,
543 0x8f850018, 0x96020012, 0xaca20010, 0x8f830018, 0x3c106000, 0xac600014,
544 0x8f840018, 0x8e024448, 0x3c030800, 0xac820018, 0x9462466e, 0x8f840018,
545 0x3c034012, 0x00431025, 0xac82001c, 0x0e001044, 0x24040001, 0x8e036800,
546 0x00001021, 0x3c040001, 0x00641825, 0xae036800, 0x0a000c0d, 0x8fbf0014,
547 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c020800, 0x97430078,
548 0x9444002e, 0x00001021, 0x00641821, 0x3063fffe, 0x03e00008, 0xa7630010,
549 0x27450100, 0x8f640048, 0x8ca30018, 0x00641023, 0x18400021, 0x00000000,
550 0xaf630048, 0x8f620040, 0x9763003c, 0x00821023, 0x0043102a, 0x1040001a,
551 0x3c029000, 0x8ca40000, 0x34420001, 0x3c038000, 0x00821025, 0xaf420020,
552 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x3c038000, 0x9362007d,
553 0x34630001, 0x3c058000, 0x00831825, 0x34420004, 0xa362007d, 0xaf430020,
554 0x8f4201f8, 0x00451024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf4401c0,
555 0xa34201c4, 0xaf4301f8, 0x03e00008, 0x00001021, 0x8f420100, 0x34420001,
556 0xaf4200a4, 0x03e00008, 0x00001021, 0x27bdffe0, 0xafbf0018, 0xafb10014,
557 0xafb00010, 0x9362007e, 0x30d000ff, 0x16020029, 0x00808821, 0x93620080,
558 0x16020026, 0x00000000, 0x9362007f, 0x16020023, 0x00000000, 0x9362007a,
559 0x16020004, 0x00000000, 0x0000000d, 0x00000000, 0x24000771, 0x0e000f49,
560 0x00000000, 0x3c039000, 0x34630001, 0x3c048000, 0x02231825, 0xa370007a,
561 0xaf430020, 0x8f420020, 0x00441024, 0x1440fffd, 0x3c028000, 0x9363007d,
562 0x34420001, 0x3c048000, 0x02221025, 0xa363007d, 0xaf420020, 0x8f4201f8,
563 0x00441024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf5101c0, 0xa34201c4,
564 0xaf4301f8, 0x0a000c79, 0x8fbf0018, 0x0000000d, 0x00000000, 0x24000781,
565 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c020800,
566 0x8c430020, 0x27bdffe8, 0xafb00010, 0x27500100, 0x10600024, 0xafbf0014,
567 0x0e001006, 0x00000000, 0x8f830018, 0x8e020000, 0xac620000, 0x8f840018,
568 0x8e020004, 0xac820004, 0x8f830018, 0x8e020018, 0xac620008, 0x8f840018,
569 0x8e03001c, 0xac83000c, 0x9602000c, 0x9203000a, 0x8f840018, 0x00021400,
570 0x00431025, 0xac820010, 0x8f830018, 0x3c026000, 0xac600014, 0x8f840018,
571 0x8c434448, 0xac830018, 0x96020008, 0x3c030800, 0x9464466e, 0x8f850018,
572 0x00021400, 0x00441025, 0x24040001, 0x0e001044, 0xaca2001c, 0x8fbf0014,
573 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c020800, 0x8c430020, 0x27bdffe8,
574 0xafb00010, 0x27500100, 0x10600020, 0xafbf0014, 0x0e001006, 0x00000000,
575 0x8f820018, 0xac400000, 0x8f830018, 0xac600004, 0x8f820018, 0xac400008,
576 0x8f830018, 0xac60000c, 0x9602000c, 0x9603000e, 0x8f840018, 0x00021400,
577 0x00431025, 0xac820010, 0x8f830018, 0x3c026000, 0xac600014, 0x8f840018,
578 0x8c434448, 0xac830018, 0x96020008, 0x3c030800, 0x9464466e, 0x8f850018,
579 0x00021400, 0x00441025, 0x24040001, 0x0e001044, 0xaca2001c, 0x8fbf0014,
580 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdffe8, 0xafb00010, 0x27500100,
581 0xafbf0014, 0x9602000c, 0x10400024, 0x00802821, 0x3c020800, 0x8c430020,
582 0x1060003a, 0x8fbf0014, 0x0e001006, 0x00000000, 0x8f840018, 0x8e030000,
583 0xac830000, 0x9602000c, 0x8f840018, 0x00021400, 0xac820004, 0x8f830018,
584 0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010, 0x8f820018,
585 0xac400014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001, 0x3c020800,
586 0xaca30018, 0x9443466e, 0x8f850018, 0x3c02400b, 0x00621825, 0x0e001044,
587 0xaca3001c, 0x0a000d19, 0x8fbf0014, 0x93620005, 0x30420010, 0x14400015,
588 0x3c029000, 0x34420001, 0x00a21025, 0xaf420020, 0x3c038000, 0x8f420020,
589 0x00431024, 0x1440fffd, 0x00000000, 0x3c038000, 0x93620005, 0x34630001,
590 0x00a02021, 0x00a31825, 0x24055852, 0x34420010, 0xa3620005, 0x0e000553,
591 0xaf430020, 0x0a000d19, 0x8fbf0014, 0x0000000d, 0x8fbf0014, 0x8fb00010,
592 0x03e00008, 0x27bd0018, 0x3c020800, 0x8c430020, 0x27bdffe8, 0xafb00010,
593 0x27500100, 0x10600022, 0xafbf0014, 0x0e001006, 0x00000000, 0x8f840018,
594 0x8e020004, 0xac820000, 0x9603000c, 0x9762002c, 0x8f840018, 0x00031c00,
595 0x00431025, 0xac820004, 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c,
596 0x8f830018, 0xac600010, 0x8f820018, 0xac400014, 0x8f850018, 0x3c026000,
597 0x8c434448, 0x24040001, 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018,
598 0x3c02400e, 0x00621825, 0x0e001044, 0xaca3001c, 0x0e000d48, 0x8e040000,
599 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c038000, 0x8f420278,
600 0x00431024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf440240, 0xa3420244,
601 0x03e00008, 0xaf430278, 0x3c020800, 0x8c430020, 0x27bdffe0, 0xafb10014,
602 0x00808821, 0xafb20018, 0x00c09021, 0xafb00010, 0x30b0ffff, 0x1060001c,
603 0xafbf001c, 0x0e001006, 0x00000000, 0x8f820018, 0xac510000, 0x8f840018,
604 0x00101400, 0xac820004, 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c,
605 0x8f830018, 0xac600010, 0x8f820018, 0xac520014, 0x8f840018, 0x3c026000,
606 0x8c434448, 0x3c020800, 0xac830018, 0x9443466e, 0x8f840018, 0x3c024019,
607 0x00621825, 0xac83001c, 0x0e001044, 0x24040001, 0x8fbf001c, 0x8fb20018,
608 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x27bdffe8, 0x27450100,
609 0xafbf0010, 0x94a3000c, 0x240200c1, 0x14620029, 0x00803021, 0x3c029000,
610 0x34420001, 0x00c21025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024,
611 0x1440fffd, 0x3c028000, 0x34420001, 0x3c049000, 0x34840001, 0x3c058000,
612 0x24030012, 0x00c21025, 0x00c42025, 0xa363003f, 0xaf420020, 0xaf440020,
613 0x8f420020, 0x00451024, 0x1440fffd, 0x3c038000, 0x9362007d, 0x34630001,
614 0x3c048000, 0x00c31825, 0x34420020, 0xa362007d, 0xaf430020, 0x8f4201f8,
615 0x00441024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf4601c0, 0xa34201c4,
616 0xaf4301f8, 0x0a000db3, 0x8fbf0010, 0x00c02021, 0x94a5000c, 0x24060001,
617 0x0e000f78, 0x240706d8, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x3c020800,
618 0x8c430020, 0x27bdffe0, 0xafb00010, 0x00808021, 0xafb20018, 0x00a09021,
619 0xafb10014, 0x30d100ff, 0x1060001c, 0xafbf001c, 0x0e001006, 0x00000000,
620 0x8f820018, 0xac500000, 0x8f840018, 0x24020001, 0xac820004, 0x8f830018,
621 0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010, 0x8f820018,
622 0xac520014, 0x8f840018, 0x3c026000, 0x8c434448, 0x3c020800, 0xac830018,
623 0x9443466e, 0x8f840018, 0x3c024010, 0x00621825, 0xac83001c, 0x0e001044,
624 0x02202021, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
625 0x27bd0020, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x93620005, 0x30420001,
626 0x10400033, 0x00808021, 0x3c029000, 0x34420001, 0x02021025, 0xaf420020,
627 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620005,
628 0x3c048000, 0x3c030800, 0x304200fe, 0xa3620005, 0x8c620020, 0x34840001,
629 0x02042025, 0xaf440020, 0x10400020, 0x8fbf0014, 0x0e001006, 0x00000000,
630 0x8f820018, 0xac500000, 0x93630082, 0x9362003f, 0x8f840018, 0x00031a00,
631 0x00431025, 0xac820004, 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c,
632 0x8f830018, 0xac600010, 0x8f820018, 0xac400014, 0x8f840018, 0x3c026000,
633 0x8c434448, 0x3c020800, 0xac830018, 0x9443466e, 0x8f840018, 0x3c02400a,
634 0x00621825, 0xac83001c, 0x0e001044, 0x24040001, 0x8fbf0014, 0x8fb00010,
635 0x03e00008, 0x27bd0018, 0x27bdffe8, 0xafbf0010, 0x8f420188, 0x00803021,
636 0x9364003f, 0x24030012, 0x00021402, 0x1483001c, 0x304500ff, 0x3c029000,
637 0x34420001, 0x3c038000, 0x00c21025, 0xa3650080, 0xa365007a, 0xaf420020,
638 0x8f420020, 0x00431024, 0x1440fffd, 0x3c028000, 0x9363007d, 0x34420001,
639 0x3c048000, 0x00c21025, 0xa363007d, 0xaf420020, 0x8f4201f8, 0x00441024,
640 0x1440fffd, 0x24020002, 0x3c031000, 0xaf4601c0, 0xa34201c4, 0xaf4301f8,
641 0x0a000e54, 0x8fbf0010, 0x9362007e, 0x1445000e, 0x00000000, 0x93620080,
642 0x1045000b, 0x00000000, 0xa3650080, 0x8f820000, 0x93660080, 0x8f440180,
643 0x8f65004c, 0x8c430000, 0x0060f809, 0x00000000, 0x0a000e54, 0x8fbf0010,
644 0xa3650080, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x3c020800, 0x8c430020,
645 0x27bdffe0, 0xafb10014, 0x00808821, 0xafb20018, 0x00a09021, 0xafb00010,
646 0x30d000ff, 0x1060002f, 0xafbf001c, 0x0e001006, 0x00000000, 0x8f820018,
647 0xac510000, 0x8f830018, 0xac700004, 0x8f820018, 0xac520008, 0x8f830018,
648 0xac60000c, 0x8f820018, 0xac400010, 0x9763006a, 0x00032880, 0x50a00001,
649 0x24050001, 0x97630068, 0x93640081, 0x3c020800, 0x8c46004c, 0x00652821,
650 0x00852804, 0x00c5102b, 0x54400001, 0x00a03021, 0x3c020800, 0x8c440050,
651 0x00c4182b, 0x54600001, 0x00c02021, 0x8f830018, 0x2402fffe, 0x00822824,
652 0x3c026000, 0xac650014, 0x8f840018, 0x8c434448, 0x3c020800, 0xac830018,
653 0x9443466e, 0x8f840018, 0x3c024011, 0x00621825, 0xac83001c, 0x0e001044,
654 0x24040001, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
655 0x27bd0020, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f440100, 0x27500100,
656 0x8f650050, 0x0e000c45, 0x9206001b, 0x3c020800, 0x8c430020, 0x1060001d,
657 0x8e100018, 0x0e001006, 0x00000000, 0x8f840018, 0x8f420100, 0xac820000,
658 0x8f830018, 0xac700004, 0x8f840018, 0x8f620050, 0xac820008, 0x8f830018,
659 0xac60000c, 0x8f820018, 0xac400010, 0x8f830018, 0x3c026000, 0xac600014,
660 0x8f850018, 0x8c434448, 0x24040001, 0x3c020800, 0xaca30018, 0x9443466e,
661 0x8f850018, 0x3c02401c, 0x00621825, 0x0e001044, 0xaca3001c, 0x8fbf0014,
662 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c029000, 0x8f460140, 0x34420001,
663 0x3c038000, 0x00c21025, 0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd,
664 0x3c048000, 0x34840001, 0x3c059000, 0x34a50001, 0x3c078000, 0x24020012,
665 0x24030080, 0x00c42025, 0x00c52825, 0xa362003f, 0xa3630082, 0xaf440020,
666 0xaf450020, 0x8f420020, 0x00471024, 0x1440fffd, 0x3c038000, 0x9362007d,
667 0x34630001, 0x3c048000, 0x00c31825, 0x34420020, 0xa362007d, 0xaf430020,
668 0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf4601c0,
669 0xa34201c4, 0x03e00008, 0xaf4301f8, 0x8f430238, 0x3c020800, 0x04610013,
670 0x8c44009c, 0x2406fffe, 0x3c050800, 0x3c038000, 0x2484ffff, 0x14800009,
671 0x00000000, 0x97420078, 0x8ca3007c, 0x24420001, 0x00461024, 0x24630001,
672 0xa7620010, 0x03e00008, 0xaca3007c, 0x8f420238, 0x00431024, 0x1440fff3,
673 0x2484ffff, 0x8f420140, 0x3c031000, 0xaf420200, 0x03e00008, 0xaf430238,
674 0x3c029000, 0x8f440140, 0x34420001, 0x3c038000, 0x00821025, 0xaf420020,
675 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x3c038000, 0x9362007d,
676 0x34630001, 0x3c058000, 0x00831825, 0x34420001, 0xa362007d, 0xaf430020,
677 0x8f4201f8, 0x00451024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf4401c0,
678 0xa34201c4, 0x03e00008, 0xaf4301f8, 0x0000000d, 0x03e00008, 0x00000000,
679 0x0000000d, 0x03e00008, 0x00000000, 0x24020001, 0x03e00008, 0xa7620010,
680 0x9362003f, 0x304400ff, 0x3883000e, 0x2c630001, 0x38820010, 0x2c420001,
681 0x00621825, 0x14600003, 0x24020012, 0x14820003, 0x00000000, 0x03e00008,
682 0x00001021, 0x9363007e, 0x9362007a, 0x14620006, 0x00000000, 0x9363007e,
683 0x24020001, 0x24630001, 0x03e00008, 0xa363007e, 0x9363007e, 0x93620080,
684 0x14620004, 0x24020001, 0xa362000b, 0x03e00008, 0x24020001, 0x03e00008,
685 0x00001021, 0x9362000b, 0x10400021, 0x00001021, 0xa360000b, 0x9362003f,
686 0x304400ff, 0x3883000e, 0x2c630001, 0x38820010, 0x2c420001, 0x00621825,
687 0x14600015, 0x00001821, 0x24020012, 0x10820012, 0x00000000, 0x9363007e,
688 0x9362007a, 0x14620007, 0x00000000, 0x9362007e, 0x24030001, 0x24420001,
689 0xa362007e, 0x03e00008, 0x00601021, 0x9363007e, 0x93620080, 0x14620004,
690 0x00001821, 0x24020001, 0xa362000b, 0x24030001, 0x03e00008, 0x00601021,
691 0x03e00008, 0x00000000, 0x24040001, 0xaf64000c, 0x8f6300dc, 0x8f6200cc,
692 0x50620001, 0xa7640010, 0xa7640012, 0xa7640014, 0x03e00008, 0xa7640016,
693 0x27bdffd8, 0xafb00010, 0x00808021, 0xafb3001c, 0x00c09821, 0xafbf0020,
694 0xafb20018, 0xafb10014, 0x93620023, 0x00e09021, 0x30420040, 0x10400020,
695 0x30b1ffff, 0x3c020800, 0x8c430020, 0x1060001c, 0x00000000, 0x0e001006,
696 0x00000000, 0x8f820018, 0xac500000, 0x8f840018, 0x3c02008d, 0xac820004,
697 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010,
698 0x8f820018, 0xac520014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001,
699 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018, 0x3c024019, 0x00621825,
700 0x0e001044, 0xaca3001c, 0x93620023, 0x30420020, 0x14400003, 0x3c020800,
701 0x52600020, 0x3c029000, 0x8c430020, 0x1060001d, 0x3c029000, 0x0e001006,
702 0x00000000, 0x8f820018, 0xac500000, 0x8f840018, 0x00111400, 0xac820004,
703 0x8f830018, 0xac720008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010,
704 0x8f820018, 0xac400014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001,
705 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018, 0x3c02401b, 0x00621825,
706 0x0e001044, 0xaca3001c, 0x3c029000, 0x34420001, 0x02021025, 0xaf420020,
707 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93630023,
708 0x3c028000, 0x34420001, 0x02021025, 0x8fbf0020, 0x8fb3001c, 0x8fb20018,
709 0x8fb10014, 0x8fb00010, 0x3063009f, 0xa3630023, 0xaf420020, 0x03e00008,
710 0x27bd0028, 0x3c020800, 0x8c430020, 0x27bdffe8, 0xafb00010, 0x27500100,
711 0x1060001d, 0xafbf0014, 0x0e001006, 0x00000000, 0x8f830018, 0x8e020004,
712 0xac620000, 0x8f840018, 0x8e020018, 0xac820004, 0x8f850018, 0x8e020000,
713 0xaca20008, 0x8f830018, 0xac60000c, 0x8f820018, 0xac400010, 0x8f830018,
714 0xac600014, 0x8f820018, 0xac400018, 0x96030008, 0x3c020800, 0x9444466e,
715 0x8f850018, 0x00031c00, 0x00641825, 0x24040001, 0x0e001044, 0xaca3001c,
716 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c060800, 0x24c54660,
717 0x3c02000a, 0x03421821, 0x94640006, 0x94a2000a, 0x00441023, 0x00021400,
718 0x00021c03, 0x04610006, 0xa4a40006, 0x0000000d, 0x00000000, 0x2400005a,
719 0x0a00101b, 0x24020001, 0x8f820014, 0x0062102b, 0x14400002, 0x00001021,
720 0x24020001, 0x304200ff, 0x1040001c, 0x274a0400, 0x3c07000a, 0x3c020800,
721 0x24454660, 0x94a9000a, 0x8f880014, 0x03471021, 0x94430006, 0x00402021,
722 0xa4a30006, 0x94820006, 0xa4a20006, 0x01221023, 0x00021400, 0x00021403,
723 0x04410006, 0x0048102b, 0x0000000d, 0x00000000, 0x2400005a, 0x0a001036,
724 0x24020001, 0x14400002, 0x00001021, 0x24020001, 0x304200ff, 0x1440ffec,
725 0x03471021, 0x24c44660, 0x8c820010, 0xaf420038, 0x8c830014, 0x3c020005,
726 0xaf43003c, 0xaf420030, 0xaf800010, 0xaf8a0018, 0x03e00008, 0x00000000,
727 0x27bdffe0, 0x8f820010, 0x8f850018, 0x3c070800, 0x24e84660, 0xafbf001c,
728 0xafb20018, 0xafb10014, 0xafb00010, 0x9503000a, 0x8d060014, 0x00009021,
729 0x309000ff, 0x00e08821, 0x24420001, 0x24a50020, 0x24630001, 0xaf820010,
730 0xaf850018, 0xa503000a, 0x24c30020, 0x3c028000, 0x04c10007, 0xad030014,
731 0x00621024, 0x14400005, 0x26224660, 0x8d020010, 0x24420001, 0xad020010,
732 0x26224660, 0x9444000a, 0x94450018, 0x0010102b, 0x00a41826, 0x2c630001,
733 0x00621825, 0x1060001c, 0x3c030006, 0x8f820010, 0x24120001, 0x00021140,
734 0x00431025, 0xaf420030, 0x00000000, 0x00000000, 0x00000000, 0x27450400,
735 0x8f420000, 0x30420010, 0x1040fffd, 0x26224660, 0x9444000a, 0x94430018,
736 0xaf800010, 0xaf850018, 0x14830012, 0x26274660, 0x0e0010d2, 0x00000000,
737 0x1600000e, 0x26274660, 0x0e001006, 0x00000000, 0x0a00108f, 0x26274660,
738 0x00041c00, 0x00031c03, 0x00051400, 0x00021403, 0x00621823, 0x18600002,
739 0x3c026000, 0xac400808, 0x26274660, 0x94e2000e, 0x94e3000c, 0x24420001,
740 0xa4e2000e, 0x3042ffff, 0x50430001, 0xa4e0000e, 0x12000005, 0x3c02000a,
741 0x94e2000a, 0xa74200a2, 0x0a0010cc, 0x02401021, 0x03421821, 0x94640006,
742 0x94e2000a, 0x00441023, 0x00021400, 0x00021c03, 0x04610006, 0xa4e40006,
743 0x0000000d, 0x00000000, 0x2400005a, 0x0a0010ae, 0x24020001, 0x8f820014,
744 0x0062102b, 0x14400002, 0x00001021, 0x24020001, 0x304200ff, 0x1040001b,
745 0x3c020800, 0x3c06000a, 0x24454660, 0x94a8000a, 0x8f870014, 0x03461021,
746 0x94430006, 0x00402021, 0xa4a30006, 0x94820006, 0xa4a20006, 0x01021023,
747 0x00021400, 0x00021403, 0x04410006, 0x0047102b, 0x0000000d, 0x00000000,
748 0x2400005a, 0x0a0010c8, 0x24020001, 0x14400002, 0x00001021, 0x24020001,
749 0x304200ff, 0x1440ffec, 0x03461021, 0x02401021, 0x8fbf001c, 0x8fb20018,
750 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c020800, 0x24454660,
751 0x94a3001a, 0x8ca40024, 0x00403021, 0x000318c0, 0x00832021, 0xaf44003c,
752 0x8ca20020, 0xaf420038, 0x3c020050, 0x34420008, 0xaf420030, 0x00000000,
753 0x00000000, 0x00000000, 0x8f420000, 0x30420020, 0x1040fffd, 0x00000000,
754 0x8f430400, 0x24c64660, 0xacc30010, 0x8f420404, 0x3c030020, 0xacc20014,
755 0xaf430030, 0x94c40018, 0x94c3001c, 0x94c2001a, 0x94c5001e, 0x00832021,
756 0x24420001, 0xa4c2001a, 0x3042ffff, 0x14450002, 0xa4c40018, 0xa4c0001a,
757 0x03e00008, 0x00000000, 0x8f820010, 0x3c030006, 0x00021140, 0x00431025,
758 0xaf420030, 0x00000000, 0x00000000, 0x00000000, 0x27430400, 0x8f420000,
759 0x30420010, 0x1040fffd, 0x00000000, 0xaf800010, 0xaf830018, 0x03e00008,
760 0x00000000, 0x27bdffe8, 0xafb00010, 0x3c100800, 0x26104660, 0x3c05000a,
761 0x02002021, 0x03452821, 0xafbf0014, 0x0e001128, 0x2406000a, 0x96020002,
762 0x9603001e, 0x3042000f, 0x24420003, 0x00431804, 0x24027fff, 0x0043102b,
763 0xaf830014, 0x10400004, 0x00000000, 0x0000000d, 0x00000000, 0x24000043,
764 0x0e0010d2, 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018,
765 0x10c00007, 0x00000000, 0x8ca20000, 0x24c6ffff, 0x24a50004, 0xac820000,
766 0x14c0fffb, 0x24840004, 0x03e00008, 0x00000000, 0x0a001137, 0x00a01021,
767 0xac860000, 0x24840004, 0x00a01021, 0x1440fffc, 0x24a5ffff, 0x03e00008,
768 0x00000000, 0x3c036000, 0x8c642b7c, 0x3c036010, 0x8c6553fc, 0x00041582,
769 0x00042302, 0x308403ff, 0x00052d82, 0x00441026, 0x0002102b, 0x0005282b,
770 0x00451025, 0x1440000d, 0x3c020050, 0x34420004, 0xaf400038, 0xaf40003c,
771 0xaf420030, 0x00000000, 0x00000000, 0x8f420000, 0x30420020, 0x1040fffd,
772 0x3c020020, 0xaf420030, 0x0000000d, 0x03e00008, 0x00000000, 0x3c020050,
773 0x34420004, 0xaf440038, 0xaf45003c, 0xaf420030, 0x00000000, 0x00000000,
774 0x8f420000, 0x30420020, 0x1040fffd, 0x3c020020, 0xaf420030, 0x03e00008,
775 0x00000000, 0x00000000 };
776
777static u32 bnx2_COM_b06FwData[(0x0/4) + 1] = { 0x00000000 };
778static u32 bnx2_COM_b06FwRodata[(0x18/4) + 1] = {
779 0x08002318, 0x08002348, 0x08002378, 0x080023a8, 0x080023d8, 0x00000000,
780 0x00000000 };
781
782static u32 bnx2_COM_b06FwBss[(0x88/4) + 1] = { 0x00000000 };
783static u32 bnx2_COM_b06FwSbss[(0x1c/4) + 1] = { 0x00000000 };
784
785static int bnx2_RXP_b06FwReleaseMajor = 0x0;
786static int bnx2_RXP_b06FwReleaseMinor = 0x0;
787static int bnx2_RXP_b06FwReleaseFix = 0x0;
788static u32 bnx2_RXP_b06FwStartAddr = 0x08000060;
789static u32 bnx2_RXP_b06FwTextAddr = 0x08000000;
790static int bnx2_RXP_b06FwTextLen = 0x20b8;
791static u32 bnx2_RXP_b06FwDataAddr = 0x080020e0;
792static int bnx2_RXP_b06FwDataLen = 0x0;
793static u32 bnx2_RXP_b06FwRodataAddr = 0x00000000;
794static int bnx2_RXP_b06FwRodataLen = 0x0;
795static u32 bnx2_RXP_b06FwBssAddr = 0x08002100;
796static int bnx2_RXP_b06FwBssLen = 0x239c;
797static u32 bnx2_RXP_b06FwSbssAddr = 0x080020e0;
798static int bnx2_RXP_b06FwSbssLen = 0x14;
799
800static u32 bnx2_RXP_b06FwText[(0x20b8/4) + 1] = {
801 0x0a000018, 0x00000000, 0x00000000, 0x0000000d, 0x72787020, 0x302e362e,
802 0x39000000, 0x00060903, 0x00000000, 0x0000000d, 0x00000000, 0x00000000,
803 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
804 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
805 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c020800,
806 0x244220e0, 0x3c030800, 0x2463449c, 0xac400000, 0x0043202b, 0x1480fffd,
807 0x24420004, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100060,
808 0x3c1c0800, 0x279c20e0, 0x0e000329, 0x00000000, 0x0000000d, 0x8f870008,
809 0x2ce20080, 0x10400018, 0x3c030800, 0x24633490, 0x8f460100, 0x00072140,
810 0x00831021, 0xac460000, 0x8f450104, 0x00641021, 0xac450004, 0x8f460108,
811 0xac460008, 0x8f45010c, 0xac45000c, 0x8f460114, 0xac460010, 0x8f450118,
812 0xac450014, 0x8f460124, 0xac460018, 0x8f450128, 0x00641821, 0x24e20001,
813 0xaf820008, 0xac65001c, 0x03e00008, 0x00000000, 0x00804021, 0x8f830000,
814 0x24070001, 0x3c020001, 0x00621024, 0x10400037, 0x00603021, 0x9742010e,
815 0x3c038000, 0x3045ffff, 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003,
816 0xa342018b, 0x8f840004, 0x24020080, 0x24030002, 0xaf420180, 0xa743018c,
817 0x10800005, 0xa745018e, 0x9743011c, 0x9742011e, 0x0a000069, 0x00021400,
818 0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c,
819 0x24020003, 0x30838000, 0x1060000d, 0xa7420188, 0x93420116, 0x304200fc,
820 0x005a1021, 0x24424004, 0x8c430000, 0x3063ffff, 0x14600005, 0x00000000,
821 0x3c02ffff, 0x34427fff, 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c,
822 0x8f440104, 0x3042bfff, 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6,
823 0xaf4301ac, 0x3c021000, 0xaf4201b8, 0x03e00008, 0x00001021, 0x30c21000,
824 0x1040000f, 0x00000000, 0x9742010c, 0x3042fc00, 0x5440000b, 0x24070005,
825 0x3c021000, 0x00c21024, 0x10400007, 0x3c030dff, 0x3463ffff, 0x3c020e00,
826 0x00c21024, 0x0062182b, 0x54600001, 0x24070005, 0x8f82000c, 0x30434000,
827 0x10600016, 0x00404821, 0x3c020f00, 0x00c21024, 0x14400012, 0x00000000,
828 0x93420116, 0x34424000, 0x03421821, 0x94650002, 0x2ca21389, 0x1040000b,
829 0x3c020800, 0x24422100, 0x00051942, 0x00031880, 0x00621821, 0x30a5001f,
830 0x8c640000, 0x24020001, 0x00a21004, 0x00822024, 0x01044025, 0x11000037,
831 0x3c021000, 0x9742010e, 0x34e60002, 0x3c038000, 0x24420004, 0x3045ffff,
832 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003, 0xa342018b, 0x8f840004,
833 0x24020180, 0x24030002, 0xaf420180, 0xa743018c, 0x10800005, 0xa745018e,
834 0x9743011c, 0x9742011e, 0x0a0000cd, 0x00021400, 0x9743011e, 0x9742011c,
835 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c, 0x30828000, 0x1040000c,
836 0xa7460188, 0x93420116, 0x304200fc, 0x005a1021, 0x24424004, 0x8c430000,
837 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff, 0x00821024, 0xaf82000c,
838 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff, 0x00031c00, 0x3084ffff,
839 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000, 0xaf4201b8, 0x03e00008,
840 0x00001021, 0x00c21024, 0x104000ba, 0x3c020800, 0x8c430030, 0x1060003e,
841 0x31224000, 0x1040003c, 0x3c030f00, 0x00c31824, 0x3c020100, 0x0043102b,
842 0x14400038, 0x3c030800, 0x9742010e, 0x34e60002, 0x3c038000, 0x24420004,
843 0x3045ffff, 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003, 0xa342018b,
844 0x8f840004, 0x24020080, 0x24030002, 0xaf420180, 0xa743018c, 0x10800005,
845 0xa745018e, 0x9743011c, 0x9742011e, 0x0a000110, 0x00021400, 0x9743011e,
846 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c, 0x30828000,
847 0x1040000c, 0xa7460188, 0x93420116, 0x304200fc, 0x005a1021, 0x24424004,
848 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff, 0x00821024,
849 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff, 0x00031c00,
850 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000, 0xaf4201b8,
851 0x03e00008, 0x00001021, 0x3c030800, 0x8c620024, 0x30420008, 0x1040003d,
852 0x34e80002, 0x3c020f00, 0x00c21024, 0x5440003a, 0x3107ffff, 0x9742010c,
853 0x30420200, 0x50400036, 0x3107ffff, 0x9742010e, 0x30e6fffb, 0x3c038000,
854 0x24420004, 0x3045ffff, 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003,
855 0xa342018b, 0x8f840004, 0x24020180, 0x24030002, 0xaf420180, 0xa743018c,
856 0x10800005, 0xa745018e, 0x9743011c, 0x9742011e, 0x0a000153, 0x00021400,
857 0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c,
858 0x30828000, 0x1040000c, 0xa7460188, 0x93420116, 0x304200fc, 0x005a1021,
859 0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff,
860 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff,
861 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000,
862 0xaf4201b8, 0x3107ffff, 0x8f820000, 0x3c068000, 0x9743010e, 0x00021442,
863 0x30440780, 0x24630004, 0x3065ffff, 0x8f4201b8, 0x00461024, 0x1440fffd,
864 0x24020003, 0xa342018b, 0x8f830004, 0x24020002, 0xaf440180, 0xa742018c,
865 0x10600005, 0xa745018e, 0x9743011c, 0x9742011e, 0x0a000189, 0x00021400,
866 0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c,
867 0x30828000, 0x1040000c, 0xa7470188, 0x93420116, 0x304200fc, 0x005a1021,
868 0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff,
869 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff,
870 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000,
871 0xaf4201b8, 0x03e00008, 0x00001021, 0x8f424000, 0x30420100, 0x104000ef,
872 0x3c020800, 0x8c440024, 0x24030001, 0x14830036, 0x00404021, 0x9742010e,
873 0x34e50002, 0x3c038000, 0x24420004, 0x3044ffff, 0x8f4201b8, 0x00431024,
874 0x1440fffd, 0x24020003, 0xa342018b, 0x8f830004, 0x24020002, 0xaf400180,
875 0xa742018c, 0x10600005, 0xa744018e, 0x9743011c, 0x9742011e, 0x0a0001c6,
876 0x00021400, 0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8,
877 0x8f84000c, 0x30828000, 0x1040000c, 0xa7450188, 0x93420116, 0x304200fc,
878 0x005a1021, 0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff,
879 0x34427fff, 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104,
880 0x3042bfff, 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac,
881 0x3c021000, 0xaf4201b8, 0x03e00008, 0x00001021, 0x30820001, 0x10400035,
882 0x30e90004, 0x9742010e, 0x30e6fffb, 0x3c038000, 0x24420004, 0x3044ffff,
883 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003, 0xa342018b, 0x8f830004,
884 0x24020002, 0xaf400180, 0xa742018c, 0x10600005, 0xa744018e, 0x9743011c,
885 0x9742011e, 0x0a0001fe, 0x00021400, 0x9743011e, 0x9742011c, 0x00021400,
886 0x00621825, 0xaf4301a8, 0x8f84000c, 0x30828000, 0x1040000c, 0xa7470188,
887 0x93420116, 0x304200fc, 0x005a1021, 0x24424004, 0x8c430000, 0x3063ffff,
888 0x14600004, 0x3c02ffff, 0x34427fff, 0x00821024, 0xaf82000c, 0x9782000e,
889 0x9743010c, 0x8f440104, 0x3042bfff, 0x00031c00, 0x3084ffff, 0x00641825,
890 0xa74201a6, 0xaf4301ac, 0x3c021000, 0xaf4201b8, 0x30c7ffff, 0x8d020024,
891 0x30420004, 0x10400037, 0x8d020024, 0x9742010e, 0x30e6fffb, 0x3c038000,
892 0x24420004, 0x3045ffff, 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003,
893 0xa342018b, 0x8f840004, 0x24020100, 0x24030002, 0xaf420180, 0xa743018c,
894 0x10800005, 0xa745018e, 0x9743011c, 0x9742011e, 0x0a000237, 0x00021400,
895 0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c,
896 0x30828000, 0x1040000c, 0xa7470188, 0x93420116, 0x304200fc, 0x005a1021,
897 0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff,
898 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff,
899 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000,
900 0xaf4201b8, 0x30c7ffff, 0x8d020024, 0x30420008, 0x10400034, 0x00000000,
901 0x9742010e, 0x3c038000, 0x24420004, 0x3045ffff, 0x8f4201b8, 0x00431024,
902 0x1440fffd, 0x24020003, 0xa342018b, 0x8f840004, 0x24020180, 0x24030002,
903 0xaf420180, 0xa743018c, 0x10800005, 0xa745018e, 0x9743011c, 0x9742011e,
904 0x0a00026f, 0x00021400, 0x9743011e, 0x9742011c, 0x00021400, 0x00621825,
905 0xaf4301a8, 0x8f84000c, 0x30828000, 0x1040000c, 0xa7470188, 0x93420116,
906 0x304200fc, 0x005a1021, 0x24424004, 0x8c430000, 0x3063ffff, 0x14600004,
907 0x3c02ffff, 0x34427fff, 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c,
908 0x8f440104, 0x3042bfff, 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6,
909 0xaf4301ac, 0x3c021000, 0xaf4201b8, 0x15200046, 0x00001021, 0x3c038000,
910 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020002, 0x24032000, 0xa342018b,
911 0xa7430188, 0x3c021000, 0xaf4201b8, 0x03e00008, 0x00001021, 0x3c030800,
912 0x8c620024, 0x30420001, 0x10400035, 0x00001021, 0x9742010e, 0x34e50002,
913 0x3c038000, 0x24420004, 0x3044ffff, 0x8f4201b8, 0x00431024, 0x1440fffd,
914 0x24020003, 0xa342018b, 0x8f830004, 0x24020002, 0xaf400180, 0xa742018c,
915 0x10600005, 0xa744018e, 0x9743011c, 0x9742011e, 0x0a0002b5, 0x00021400,
916 0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c,
917 0x30828000, 0x1040000c, 0xa7450188, 0x93420116, 0x304200fc, 0x005a1021,
918 0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff,
919 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff,
920 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000,
921 0xaf4201b8, 0x00001021, 0x03e00008, 0x00000000, 0x27bdffe0, 0xafbf0018,
922 0xafb10014, 0xafb00010, 0x8f420140, 0xaf420020, 0x8f430148, 0x3c027000,
923 0x00621824, 0x3c024000, 0x1062000c, 0x0043102b, 0x14400006, 0x3c025000,
924 0x3c023000, 0x1062000b, 0x3c024000, 0x0a00031f, 0x00000000, 0x10620034,
925 0x3c024000, 0x0a00031f, 0x00000000, 0x0e00067c, 0x00000000, 0x0a00031f,
926 0x3c024000, 0x8f420148, 0x24030002, 0x3044ffff, 0x00021402, 0x305000ff,
927 0x1203000c, 0x27510180, 0x2a020003, 0x10400005, 0x24020003, 0x0600001d,
928 0x36053000, 0x0a00030a, 0x3c038000, 0x12020007, 0x00000000, 0x0a000317,
929 0x00000000, 0x0e000423, 0x00000000, 0x0a000308, 0x00402021, 0x0e000435,
930 0x00000000, 0x00402021, 0x36053000, 0x3c038000, 0x8f4201b8, 0x00431024,
931 0x1440fffd, 0x24020002, 0xa6250008, 0xa222000b, 0xa6240010, 0x8f420144,
932 0x3c031000, 0xae220024, 0xaf4301b8, 0x0a00031f, 0x3c024000, 0x0000000d,
933 0x00000000, 0x240001c3, 0x0a00031f, 0x3c024000, 0x0e0007f7, 0x00000000,
934 0x3c024000, 0xaf420178, 0x00000000, 0x8fbf0018, 0x8fb10014, 0x8fb00010,
935 0x03e00008, 0x27bd0020, 0x24020800, 0x03e00008, 0xaf4201b8, 0x27bdffe8,
936 0x3c04600c, 0xafbf0014, 0xafb00010, 0x8c825000, 0x3c1a8000, 0x2403ff7f,
937 0x3c106000, 0x00431024, 0x3442380c, 0x24030003, 0xac825000, 0x3c040008,
938 0xaf430008, 0x8e020808, 0x3c030800, 0xac600020, 0x3042fff0, 0x2c420001,
939 0xaf820004, 0x0e000819, 0x0344d825, 0x0e000781, 0x00000000, 0x3c020400,
940 0x3442000c, 0x3c03ffff, 0x34630806, 0xae021948, 0xae03194c, 0x8e021980,
941 0x34420200, 0xae021980, 0x8f500000, 0x32020003, 0x1040fffd, 0x32020001,
942 0x10400004, 0x32020002, 0x0e0003bd, 0x00000000, 0x32020002, 0x1040fff6,
943 0x00000000, 0x0e0002d4, 0x00000000, 0x0a00034a, 0x00000000, 0x27bdffe8,
944 0x3c04600c, 0xafbf0014, 0xafb00010, 0x8c825000, 0x3c1a8000, 0x2403ff7f,
945 0x3c106000, 0x00431024, 0x3442380c, 0x24030003, 0xac825000, 0x3c040008,
946 0xaf430008, 0x8e020808, 0x3c030800, 0xac600020, 0x3042fff0, 0x2c420001,
947 0xaf820004, 0x0e000819, 0x0344d825, 0x0e000781, 0x00000000, 0x3c020400,
948 0x3442000c, 0x3c03ffff, 0x34630806, 0xae021948, 0xae03194c, 0x8e021980,
949 0x8fbf0014, 0x34420200, 0xae021980, 0x8fb00010, 0x03e00008, 0x27bd0018,
950 0x30a5ffff, 0x30c6ffff, 0x30e7ffff, 0x3c038000, 0x8f4201b8, 0x00431024,
951 0x1440fffd, 0x24020003, 0xa342018b, 0x8f830004, 0xaf440180, 0xa745018c,
952 0x10600005, 0xa746018e, 0x9743011c, 0x9742011e, 0x0a000393, 0x00021400,
953 0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c,
954 0x30828000, 0x1040000c, 0xa7470188, 0x93420116, 0x304200fc, 0x005a1021,
955 0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff,
956 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff,
957 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000,
958 0xaf4201b8, 0x03e00008, 0x00000000, 0x3c038000, 0x8f4201b8, 0x00431024,
959 0x1440fffd, 0x24020002, 0x24032000, 0xa342018b, 0xa7430188, 0x3c021000,
960 0xaf4201b8, 0x03e00008, 0x00000000, 0x27bdffe8, 0xafbf0010, 0x8f460128,
961 0xaf460020, 0x8f420104, 0x8f450100, 0x24030800, 0x3c040010, 0xaf820000,
962 0x00441024, 0xaf85000c, 0xaf4301b8, 0x14400005, 0x3c02001f, 0x3c030800,
963 0x8c620020, 0x0a0003d5, 0x00002021, 0x3442ff00, 0x14c20009, 0x2402bfff,
964 0x3c030800, 0x8c620020, 0x24040001, 0x24420001, 0x0e00004c, 0xac620020,
965 0x0a0003e4, 0x00000000, 0x00a21024, 0x14400006, 0x00000000, 0xaf400048,
966 0x0e000448, 0xaf400040, 0x0a0003e4, 0x00000000, 0x0e000783, 0x00000000,
967 0x10400005, 0x3c024000, 0x8f430124, 0x3c026020, 0xac430014, 0x3c024000,
968 0xaf420138, 0x00000000, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x27bdffe0,
969 0xafbf0018, 0xafb10014, 0xafb00010, 0x8f420148, 0x24030002, 0x3044ffff,
970 0x00021402, 0x305000ff, 0x1203000c, 0x27510180, 0x2a020003, 0x10400005,
971 0x24020003, 0x0600001d, 0x36053000, 0x0a00040e, 0x3c038000, 0x12020007,
972 0x00000000, 0x0a00041b, 0x00000000, 0x0e000423, 0x00000000, 0x0a00040c,
973 0x00402021, 0x0e000435, 0x00000000, 0x00402021, 0x36053000, 0x3c038000,
974 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020002, 0xa6250008, 0xa222000b,
975 0xa6240010, 0x8f420144, 0x3c031000, 0xae220024, 0xaf4301b8, 0x0a00041f,
976 0x8fbf0018, 0x0000000d, 0x00000000, 0x240001c3, 0x8fbf0018, 0x8fb10014,
977 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3084ffff, 0x2c821389, 0x1040000d,
978 0x00001021, 0x3c030800, 0x24632100, 0x00042942, 0x00052880, 0x00a32821,
979 0x3086001f, 0x8ca40000, 0x24030001, 0x00c31804, 0x00832025, 0x03e00008,
980 0xaca40000, 0x03e00008, 0x24020091, 0x3084ffff, 0x2c821389, 0x1040000e,
981 0x00001021, 0x3c030800, 0x24632100, 0x00042942, 0x00052880, 0x00a32821,
982 0x3086001f, 0x24030001, 0x8ca40000, 0x00c31804, 0x00031827, 0x00832024,
983 0x03e00008, 0xaca40000, 0x03e00008, 0x24020091, 0x27bdffb0, 0x3c026000,
984 0xafbf0048, 0x8c434448, 0xaf630140, 0x93620005, 0x30420001, 0x14400005,
985 0x00000000, 0x0e0007ed, 0x00000000, 0x0a00067a, 0x8fbf0048, 0x93420116,
986 0x93430112, 0x8f430104, 0x3c040020, 0x34424000, 0x00641824, 0x1060000d,
987 0x03426021, 0x8f430128, 0x27420180, 0xac430000, 0x8f650040, 0x24040008,
988 0x240340c1, 0xa4430008, 0x24030002, 0xa043000b, 0x3c031000, 0x0a000563,
989 0xa044000a, 0x8f420104, 0x3c030040, 0x00431024, 0x10400007, 0x00000000,
990 0x8f430128, 0x27420180, 0xac430000, 0x8f650040, 0x0a00055c, 0x24040010,
991 0xaf400048, 0xaf400054, 0xaf400040, 0x8f630048, 0x8f620040, 0x00624823,
992 0x05210004, 0x00000000, 0x0000000d, 0x00000000, 0x24000132, 0x9742011a,
993 0x3046ffff, 0x10c00004, 0x8d880004, 0x01061021, 0x0a000487, 0x2445ffff,
994 0x01002821, 0x918a000d, 0xa7a00020, 0xafa00028, 0x9364003f, 0x3c026000,
995 0x8c434448, 0x308700ff, 0x31420004, 0x10400033, 0xaf630144, 0x24090012,
996 0x14e90006, 0x3c040800, 0x8c830028, 0x24020001, 0x24630001, 0x0a00054e,
997 0xac830028, 0x8f620044, 0x15020012, 0x97a20020, 0x27a60010, 0x27450180,
998 0x3442001a, 0xa7a20020, 0x8f630040, 0x3c048000, 0x24020020, 0xa3a70022,
999 0xa3a90023, 0xa3a2001a, 0xafa30028, 0x8f4201b8, 0x00441024, 0x1440fffd,
1000 0x00000000, 0x0a000533, 0x00000000, 0x8f620044, 0x01021023, 0x0440009e,
1001 0x24020001, 0x8f620048, 0x01021023, 0x0441009a, 0x24020001, 0x97a20020,
1002 0x27a60010, 0x34420001, 0xa7a20020, 0x8f630040, 0x27450180, 0x3c048000,
1003 0xafa30028, 0x8f4201b8, 0x00441024, 0x1440fffd, 0x00000000, 0x0a000533,
1004 0x00000000, 0x3c026000, 0x8c424448, 0xaf620148, 0x8f630040, 0x00685823,
1005 0x19600013, 0x00cb102a, 0x54400007, 0x314a00fe, 0x5566000c, 0x010b4021,
1006 0x31420001, 0x54400009, 0x010b4021, 0x314a00fe, 0x24020001, 0xa7a20020,
1007 0x8f630040, 0x00c05821, 0x00003021, 0x0a0004dd, 0xafa30028, 0x00cb1023,
1008 0x0a0004dd, 0x3046ffff, 0x00005821, 0x8f620048, 0x2442ffff, 0x00a21823,
1009 0x18600019, 0x0066102a, 0x14400013, 0x24020001, 0xa7a20020, 0x8f630040,
1010 0xafa30028, 0x8f620040, 0x55020005, 0x27a60010, 0x55200003, 0x27a60010,
1011 0x0a0004f6, 0x00c01821, 0x27450180, 0x3c038000, 0x8f4201b8, 0x00431024,
1012 0x1440fffd, 0x00000000, 0x0a000533, 0x00000000, 0x8f650048, 0x00c31023,
1013 0x3046ffff, 0x314a00f6, 0x3c046000, 0x8c824448, 0x31430002, 0x1060001e,
1014 0xaf62014c, 0x8f620044, 0x1502000e, 0x97a20020, 0x27a60010, 0x34420200,
1015 0xa7a20020, 0x8f630040, 0x27450180, 0x3c048000, 0xafa30028, 0x8f4201b8,
1016 0x00441024, 0x1440fffd, 0x00000000, 0x0a000533, 0x00000000, 0x27a60010,
1017 0x34420001, 0xa7a20020, 0x8f630040, 0x27450180, 0x3c048000, 0xafa30028,
1018 0x8f4201b8, 0x00441024, 0x1440fffd, 0x00000000, 0x0a000533, 0x00000000,
1019 0x3c026000, 0x8c424448, 0x31430010, 0xaf620150, 0x54600003, 0x8d890008,
1020 0x0a00054e, 0x24020001, 0x8f630054, 0x2522ffff, 0x00431023, 0x1840002a,
1021 0x24020001, 0x27a60010, 0xa7a20020, 0x8f630040, 0x27450180, 0x3c048000,
1022 0xafa30028, 0x8f4201b8, 0x00441024, 0x1440fffd, 0x00000000, 0x8f420128,
1023 0xaca20000, 0x8cc30018, 0x240240c1, 0xa4a20008, 0xaca30018, 0x90c4000a,
1024 0x24020002, 0xa0a2000b, 0xa0a4000a, 0x94c20010, 0xa4a20010, 0x90c30012,
1025 0xa0a30012, 0x90c20013, 0xa0a20013, 0x8cc30014, 0xaca30014, 0x8cc20024,
1026 0xaca20024, 0x8cc30028, 0xaca30028, 0x8cc4002c, 0x24020001, 0x3c031000,
1027 0xaca4002c, 0xaf4301b8, 0xaf400044, 0xaf400050, 0x0a00067a, 0x8fbf0048,
1028 0x3c026000, 0x8c424448, 0x31430020, 0x10600019, 0xaf620154, 0x8f430128,
1029 0x27420180, 0xac430000, 0x8f650040, 0x24040004, 0x240340c1, 0xa4430008,
1030 0x24030002, 0xa044000a, 0x24040008, 0xa043000b, 0x3c031000, 0xa4440010,
1031 0xa0400012, 0xa0400013, 0xac400014, 0xac400024, 0xac400028, 0xac40002c,
1032 0xac450018, 0x0e0007ed, 0xaf4301b8, 0x0a00067a, 0x8fbf0048, 0x8f430104,
1033 0x8c824448, 0x38e3000a, 0x2c630001, 0xaf620158, 0x38e2000c, 0x2c420001,
1034 0x00621825, 0x14600003, 0x2402000e, 0x14e2002a, 0x00000000, 0x50c00008,
1035 0x9584000e, 0x10c00004, 0xa7a60040, 0x01061021, 0x0a000583, 0x2445ffff,
1036 0x01002821, 0x9584000e, 0x93630035, 0x8f62004c, 0x00642004, 0x00892021,
1037 0x00821023, 0x1840001f, 0x3c026000, 0x8f620018, 0x01021023, 0x1c40000f,
1038 0x97a20020, 0x8f620018, 0x15020018, 0x3c026000, 0x8f62001c, 0x01221023,
1039 0x1c400008, 0x97a20020, 0x8f62001c, 0x15220011, 0x3c026000, 0x8f620058,
1040 0x00821023, 0x1840000c, 0x97a20020, 0xafa50028, 0xafa80034, 0xafa90038,
1041 0xafa4003c, 0x34420020, 0x0a0005a8, 0xa7a20020, 0x8f680040, 0x00003021,
1042 0x8f640058, 0x01002821, 0x3c026000, 0x8c434448, 0xaf63015c, 0x8f62004c,
1043 0x01221023, 0x18400009, 0x00000000, 0x8f620054, 0x01221023, 0x1c400005,
1044 0x97a20020, 0xafa50028, 0xafa90024, 0x0a0005c3, 0x34420040, 0x9742011a,
1045 0x1440000c, 0x24020014, 0x8f620058, 0x14820009, 0x24020014, 0x8f63004c,
1046 0x8f620054, 0x10620004, 0x97a20020, 0xafa50028, 0x34420080, 0xa7a20020,
1047 0x24020014, 0x10e2000a, 0x28e20015, 0x10400005, 0x2402000c, 0x10e20006,
1048 0x3c026000, 0x0a000600, 0x00000000, 0x24020016, 0x14e20031, 0x3c026000,
1049 0x8f620054, 0x24420001, 0x1522002d, 0x3c026000, 0x24020014, 0x10e2001e,
1050 0x28e20015, 0x10400005, 0x2402000c, 0x10e20008, 0x3c026000, 0x0a000600,
1051 0x00000000, 0x24020016, 0x10e2000c, 0x97a20020, 0x0a000600, 0x3c026000,
1052 0x97a30020, 0x2402000e, 0xafa50028, 0xa3a70022, 0xa3a20023, 0xafa90024,
1053 0x34630054, 0x0a0005ff, 0xa7a30020, 0x24030010, 0x24040002, 0xafa50028,
1054 0xa3a70022, 0xa3a30023, 0xa3a4001a, 0xafa90024, 0x0a0005fe, 0x3442005d,
1055 0x97a20020, 0x24030012, 0x24040002, 0xafa50028, 0xa3a70022, 0xa3a30023,
1056 0xa3a4001a, 0xafa90024, 0x3042fffe, 0x3442005c, 0xa7a20020, 0x3c026000,
1057 0x8c434448, 0x31420001, 0xaf630160, 0x1040002c, 0x2402000c, 0x10e20014,
1058 0x28e2000d, 0x10400005, 0x2402000a, 0x10e20008, 0x97a20020, 0x0a000631,
1059 0x3c026000, 0x2402000e, 0x10e20018, 0x3c026000, 0x0a000631, 0x00000000,
1060 0x24030008, 0x24040002, 0xafa50028, 0xa3a70022, 0xa3a30023, 0xa3a4001a,
1061 0x0a00062f, 0x34420013, 0x97a30020, 0x30620004, 0x1440000b, 0x97a20020,
1062 0x3462001b, 0xa7a20020, 0x24020016, 0x24030002, 0xafa50028, 0xa3a70022,
1063 0xa3a20023, 0x0a000630, 0xa3a3001a, 0x97a20020, 0x24030010, 0x24040002,
1064 0xafa50028, 0xa3a70022, 0xa3a30023, 0xa3a4001a, 0x3442001b, 0xa7a20020,
1065 0x3c026000, 0x8c434448, 0x31420009, 0x0002102b, 0x00021023, 0x30420007,
1066 0x34440003, 0xaf630164, 0x10c00016, 0x24030800, 0x8f820010, 0x27450180,
1067 0x24420001, 0xaf820010, 0x24020004, 0xaf4301b8, 0xa4a40008, 0xa0a2000b,
1068 0x93440120, 0x3c031000, 0xa4a6000e, 0xaca90024, 0xaca80028, 0x008b2021,
1069 0xa4a4000c, 0xaf4301b8, 0x97a20020, 0x00003021, 0x3042ffbf, 0x0a000650,
1070 0xa7a20020, 0x24060001, 0x3c026000, 0x8c434448, 0xaf630168, 0x97a20020,
1071 0x10400020, 0x27450180, 0x3c038000, 0x8f4201b8, 0x00431024, 0x1440fffd,
1072 0x00000000, 0x8f420128, 0xaca20000, 0x8fa30028, 0x240240c1, 0xa4a20008,
1073 0xaca30018, 0x93a4001a, 0x24020002, 0xa0a2000b, 0xa0a4000a, 0x97a20020,
1074 0xa4a20010, 0x93a30022, 0xa0a30012, 0x93a20023, 0xa0a20013, 0x8fa30024,
1075 0xaca30014, 0x8fa20034, 0xaca20024, 0x8fa30038, 0xaca30028, 0x8fa2003c,
1076 0x3c031000, 0xaca2002c, 0xaf4301b8, 0x3c026000, 0x8c434448, 0x00c01021,
1077 0xaf63016c, 0x8fbf0048, 0x03e00008, 0x27bd0050, 0x8f460140, 0x8f470148,
1078 0x3c028000, 0x00e24024, 0x00072c02, 0x30a300ff, 0x2402000b, 0x1062008f,
1079 0x27440180, 0x2862000c, 0x10400011, 0x24020006, 0x1062005a, 0x28620007,
1080 0x10400007, 0x24020008, 0x10600024, 0x24020001, 0x10620037, 0x00000000,
1081 0x0a00077e, 0x00000000, 0x106200a9, 0x24020009, 0x106200bb, 0x00071c02,
1082 0x0a00077e, 0x00000000, 0x2402001b, 0x106200c7, 0x2862001c, 0x10400007,
1083 0x2402000e, 0x106200b1, 0x24020019, 0x106200c2, 0x00071c02, 0x0a00077e,
1084 0x00000000, 0x24020080, 0x10620060, 0x28620081, 0x10400005, 0x2402001c,
1085 0x10620094, 0x00071c02, 0x0a00077e, 0x00000000, 0x240200c2, 0x106200c5,
1086 0x00a01821, 0x0a00077e, 0x00000000, 0x00a01821, 0x3c058000, 0x8f4201b8,
1087 0x00451024, 0x1440fffd, 0x24020001, 0xa4830008, 0x24030002, 0xac860000,
1088 0xac800004, 0xa082000a, 0xa083000b, 0xa4870010, 0x8f430144, 0x3c021000,
1089 0xac800028, 0xac830024, 0x3c036000, 0xaf4201b8, 0x03e00008, 0xac600808,
1090 0x11000009, 0x00a01821, 0x3c020800, 0x24030002, 0xa0434490, 0x24424490,
1091 0xac460008, 0x8f430144, 0x03e00008, 0xac430004, 0x3c058000, 0x8f4201b8,
1092 0x00451024, 0x1440fffd, 0x24020002, 0xac800000, 0xac860004, 0xa4830008,
1093 0xa082000a, 0xa082000b, 0xa4870010, 0xac800024, 0x8f420144, 0x3c031000,
1094 0xac820028, 0x3c026000, 0xaf4301b8, 0x03e00008, 0xac400808, 0x00a01821,
1095 0x3c080800, 0x3c058000, 0x8f4201b8, 0x00451024, 0x1440fffd, 0x00000000,
1096 0xac860000, 0x91024490, 0x00002821, 0x10400002, 0x25064490, 0x8cc50008,
1097 0xac850004, 0xa4830008, 0x91034490, 0x24020002, 0xa082000b, 0xa4870010,
1098 0x34630001, 0xa083000a, 0x8f420144, 0xac820024, 0x91034490, 0x10600002,
1099 0x00001021, 0x8cc20004, 0xac820028, 0x3c021000, 0xaf4201b8, 0x3c026000,
1100 0xa1004490, 0x03e00008, 0xac400808, 0x00a01821, 0x3c058000, 0x8f4201b8,
1101 0x00451024, 0x1440fffd, 0x24020002, 0xa082000b, 0xa4830008, 0xa4870010,
1102 0x8f420144, 0x3c031000, 0xa4820012, 0x03e00008, 0xaf4301b8, 0x30e2ffff,
1103 0x14400028, 0x00071c02, 0x93620005, 0x30420004, 0x14400020, 0x3c029000,
1104 0x34420001, 0x00c21025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024,
1105 0x1440fffd, 0x00000000, 0x93620005, 0x3c038000, 0x34630001, 0x00c31825,
1106 0x34420004, 0xa3620005, 0xaf430020, 0x93620005, 0x30420004, 0x14400003,
1107 0x3c038000, 0x0000000d, 0x3c038000, 0x8f4201b8, 0x00431024, 0x1440fffd,
1108 0x24020005, 0x3c031000, 0xac860000, 0xa082000b, 0xaf4301b8, 0x0a00073d,
1109 0x00071c02, 0x0000000d, 0x03e00008, 0x00000000, 0x00071c02, 0x3c058000,
1110 0x8f4201b8, 0x00451024, 0x1440fffd, 0x24020001, 0xa4830008, 0x24030002,
1111 0xac860000, 0xac800004, 0xa082000a, 0xa083000b, 0xa4870010, 0x8f430144,
1112 0x3c021000, 0xac800028, 0xac830024, 0x03e00008, 0xaf4201b8, 0x00071c02,
1113 0x3c058000, 0x8f4201b8, 0x00451024, 0x1440fffd, 0x24020002, 0xac800000,
1114 0xac860004, 0xa4830008, 0xa082000a, 0xa082000b, 0xa4870010, 0xac800024,
1115 0x8f420144, 0x3c031000, 0xac820028, 0x03e00008, 0xaf4301b8, 0x00071c02,
1116 0x3c058000, 0x8f4201b8, 0x00451024, 0x1440fffd, 0x24020001, 0xa4830008,
1117 0x24030002, 0xa082000a, 0x3c021000, 0xac860000, 0xac800004, 0xa083000b,
1118 0xa4870010, 0xac800024, 0xac800028, 0x03e00008, 0xaf4201b8, 0x3c058000,
1119 0x8f4201b8, 0x00451024, 0x1440fffd, 0x24020002, 0xac860000, 0xac800004,
1120 0xa4830008, 0xa080000a, 0x0a000748, 0xa082000b, 0x0000000d, 0x03e00008,
1121 0x00000000, 0x03e00008, 0x00000000, 0x8f420100, 0x3042003e, 0x14400011,
1122 0x24020001, 0xaf400048, 0x8f420100, 0x304207c0, 0x10400005, 0x00000000,
1123 0xaf40004c, 0xaf400050, 0x03e00008, 0x24020001, 0xaf400054, 0xaf400040,
1124 0x8f420100, 0x30423800, 0x54400001, 0xaf400044, 0x24020001, 0x03e00008,
1125 0x00000000, 0x3c029000, 0x34420001, 0x00822025, 0xaf440020, 0x3c038000,
1126 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x03e00008, 0x00000000,
1127 0x3c028000, 0x34420001, 0x00822025, 0x03e00008, 0xaf440020, 0x8f430128,
1128 0x27420180, 0xac430000, 0x8f650040, 0x240340c1, 0xa4430008, 0x24030002,
1129 0xa044000a, 0x24040008, 0xa043000b, 0x3c031000, 0xa4440010, 0xa0400012,
1130 0xa0400013, 0xac400014, 0xac400024, 0xac400028, 0xac40002c, 0xac450018,
1131 0x03e00008, 0xaf4301b8, 0x24020001, 0xacc40000, 0x03e00008, 0xa4e50000,
1132 0x03e00008, 0x24020001, 0x24020001, 0xaf400044, 0x03e00008, 0xaf400050,
1133 0x00803021, 0x27450180, 0x3c038000, 0x8f4201b8, 0x00431024, 0x1440fffd,
1134 0x00000000, 0x8f420128, 0xaca20000, 0x8cc30018, 0x240240c1, 0xa4a20008,
1135 0xaca30018, 0x90c4000a, 0x24020002, 0xa0a2000b, 0xa0a4000a, 0x94c20010,
1136 0xa4a20010, 0x90c30012, 0xa0a30012, 0x90c20013, 0xa0a20013, 0x8cc30014,
1137 0xaca30014, 0x8cc20024, 0xaca20024, 0x8cc30028, 0xaca30028, 0x8cc2002c,
1138 0x3c031000, 0xaca2002c, 0x24020001, 0xaf4301b8, 0xaf400044, 0x03e00008,
1139 0xaf400050, 0x27bdffe8, 0xafbf0010, 0x0e000326, 0x00000000, 0x00002021,
1140 0x0e00004c, 0xaf400180, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x8f460148,
1141 0x27450180, 0x3c038000, 0x00061402, 0x304700ff, 0x8f4201b8, 0x00431024,
1142 0x1440fffd, 0x00000000, 0x8f440140, 0x00061202, 0x304200ff, 0x00061c02,
1143 0xaca20004, 0x24020002, 0xa4a30008, 0x30c300ff, 0xa0a2000b, 0xaca30024,
1144 0x10e0000a, 0xaca40000, 0x28e20004, 0x14400005, 0x24020001, 0x24020005,
1145 0x54e20005, 0xa0a0000a, 0x24020001, 0x0a000816, 0xa0a2000a, 0xa0a0000a,
1146 0x3c021000, 0x03e00008, 0xaf4201b8, 0x03e00008, 0x00001021, 0x10c00007,
1147 0x00000000, 0x8ca20000, 0x24c6ffff, 0x24a50004, 0xac820000, 0x14c0fffb,
1148 0x24840004, 0x03e00008, 0x00000000, 0x0a00082a, 0x00a01021, 0xac860000,
1149 0x24840004, 0x00a01021, 0x1440fffc, 0x24a5ffff, 0x03e00008, 0x00000000,
1150 0x00000000 };
1151
1152static u32 bnx2_RXP_b06FwData[(0x0/4) + 1] = { 0x00000000 };
1153static u32 bnx2_RXP_b06FwRodata[(0x0/4) + 1] = { 0x00000000 };
1154static u32 bnx2_RXP_b06FwBss[(0x239c/4) + 1] = { 0x00000000 };
1155static u32 bnx2_RXP_b06FwSbss[(0x14/4) + 1] = { 0x00000000 };
1156
1157static u32 bnx2_rv2p_proc1[] = {
1158 0x00000008, 0xac000001, 0x0000000c, 0x2f800001, 0x00000010, 0x213f0004,
1159 0x00000010, 0x20bf002c, 0x00000010, 0x203f0143, 0x00000018, 0x8000fffd,
1160 0x00000010, 0xb1b8b017, 0x0000000b, 0x2fdf0002, 0x00000000, 0x03d80000,
1161 0x00000000, 0x2c380000, 0x00000008, 0x2c800000, 0x00000008, 0x2d000000,
1162 0x00000010, 0x91d40000, 0x00000008, 0x2d800108, 0x00000008, 0x02000002,
1163 0x00000010, 0x91de0000, 0x0000000f, 0x42e0001c, 0x00000010, 0x91840a08,
1164 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008, 0x00000008, 0x2d800150,
1165 0x00000000, 0x00000000, 0x00000010, 0x91de0000, 0x00000010, 0x2c620002,
1166 0x00000018, 0x80000012, 0x0000000b, 0x2fdf0002, 0x0000000c, 0x1f800002,
1167 0x00000000, 0x2c070000, 0x00000018, 0x8000ffe6, 0x00000008, 0x02000002,
1168 0x0000000f, 0x42e0001c, 0x00000010, 0x91840a08, 0x00000008, 0x2c8000b0,
1169 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, 0x00000008, 0x2d800108,
1170 0x00000000, 0x00000000, 0x00000010, 0x91de0000, 0x00000018, 0x80000004,
1171 0x0000000c, 0x1f800002, 0x00000000, 0x00000000, 0x00000018, 0x8000ffd9,
1172 0x0000000c, 0x29800002, 0x0000000c, 0x1f800002, 0x00000000, 0x2adf0000,
1173 0x00000008, 0x2a000005, 0x00000018, 0x8000ffd4, 0x00000008, 0x02240030,
1174 0x00000018, 0x00040000, 0x00000018, 0x80000015, 0x00000018, 0x80000017,
1175 0x00000018, 0x8000001b, 0x00000018, 0x8000004c, 0x00000018, 0x8000008c,
1176 0x00000018, 0x8000000f, 0x00000018, 0x8000000e, 0x00000018, 0x8000000d,
1177 0x00000018, 0x8000000c, 0x00000018, 0x800000c2, 0x00000018, 0x8000000a,
1178 0x00000018, 0x80000009, 0x00000018, 0x80000008, 0x00000018, 0x800000fd,
1179 0x00000018, 0x80000006, 0x00000018, 0x80000005, 0x00000018, 0x800000ff,
1180 0x00000018, 0x80000104, 0x00000018, 0x80000002, 0x00000018, 0x80000098,
1181 0x00000018, 0x80000000, 0x0000000c, 0x1f800001, 0x00000000, 0x00000000,
1182 0x00000018, 0x8000ffba, 0x00000010, 0x91d40000, 0x0000000c, 0x29800001,
1183 0x0000000c, 0x1f800001, 0x00000008, 0x2a000002, 0x00000018, 0x8000ffb5,
1184 0x00000010, 0xb1a0b012, 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c200000,
1185 0x00000008, 0x2c800000, 0x00000008, 0x2d000000, 0x00000010, 0x91d40000,
1186 0x00000008, 0x2d80011c, 0x00000000, 0x00000000, 0x00000010, 0x91de0000,
1187 0x0000000f, 0x47600008, 0x0000000f, 0x060e0001, 0x00000010, 0x001f0000,
1188 0x00000000, 0x0f580000, 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000,
1189 0x00000000, 0x0b660000, 0x00000000, 0x0d610000, 0x00000018, 0x80000013,
1190 0x0000000f, 0x47600008, 0x0000000b, 0x2fdf0002, 0x00000008, 0x2c800000,
1191 0x00000008, 0x2d000000, 0x00000010, 0x91d40000, 0x00000008, 0x2d80011c,
1192 0x0000000f, 0x060e0001, 0x00000010, 0x001f0000, 0x00000000, 0x0f580000,
1193 0x00000010, 0x91de0000, 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000,
1194 0x00000000, 0x0b660000, 0x00000000, 0x0d610000, 0x00000000, 0x02620000,
1195 0x0000000b, 0x2fdf0002, 0x00000000, 0x309a0000, 0x00000000, 0x31040000,
1196 0x00000000, 0x0c961800, 0x00000009, 0x0c99ffff, 0x00000004, 0xcc993400,
1197 0x00000010, 0xb1963202, 0x00000008, 0x0f800000, 0x0000000c, 0x29800001,
1198 0x00000010, 0x00220002, 0x0000000c, 0x29520001, 0x0000000c, 0x29520000,
1199 0x00000008, 0x22000001, 0x0000000c, 0x1f800001, 0x00000000, 0x2adf0000,
1200 0x00000008, 0x2a000003, 0x00000018, 0x8000ff83, 0x00000010, 0xb1a0b01d,
1201 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c200000, 0x00000008, 0x2c8000b0,
1202 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, 0x00000008, 0x2d800150,
1203 0x00000000, 0x00000000, 0x00000010, 0x205f0000, 0x00000008, 0x2c800000,
1204 0x00000008, 0x2d000000, 0x00000008, 0x2d800108, 0x00000000, 0x00000000,
1205 0x00000010, 0x91de0000, 0x0000000f, 0x47600008, 0x00000000, 0x060e0000,
1206 0x00000010, 0x001f0000, 0x00000000, 0x0f580000, 0x00000010, 0x91de0000,
1207 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000, 0x00000000, 0x0b670000,
1208 0x00000000, 0x0d620000, 0x00000000, 0x0ce71800, 0x00000009, 0x0c99ffff,
1209 0x00000004, 0xcc993400, 0x00000010, 0xb1963220, 0x00000008, 0x0f800000,
1210 0x00000018, 0x8000001e, 0x0000000f, 0x47600008, 0x0000000b, 0x2fdf0002,
1211 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008, 0x00000010, 0x91d40000,
1212 0x00000008, 0x2d80012c, 0x0000000f, 0x060e0001, 0x00000010, 0x001f0000,
1213 0x00000000, 0x0f580000, 0x00000010, 0x91de0000, 0x00000000, 0x0a640000,
1214 0x00000000, 0x0ae50000, 0x00000000, 0x0b670000, 0x00000000, 0x0d620000,
1215 0x00000000, 0x02630000, 0x0000000f, 0x47620010, 0x00000000, 0x0ce71800,
1216 0x0000000b, 0x2fdf0002, 0x00000000, 0x311a0000, 0x00000000, 0x31840000,
1217 0x0000000b, 0xc20000ff, 0x00000002, 0x42040000, 0x00000001, 0x31620800,
1218 0x0000000f, 0x020e0010, 0x00000002, 0x31620800, 0x00000009, 0x0c99ffff,
1219 0x00000004, 0xcc993400, 0x00000010, 0xb1963202, 0x00000008, 0x0f800000,
1220 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, 0x0000000c, 0x61420006,
1221 0x00000008, 0x22000008, 0x00000000, 0x2adf0000, 0x00000008, 0x2a000004,
1222 0x00000018, 0x8000ff42, 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008,
1223 0x00000010, 0x91a0b008, 0x00000010, 0x91d40000, 0x0000000c, 0x31620018,
1224 0x00000008, 0x2d800001, 0x00000000, 0x00000000, 0x00000010, 0x91de0000,
1225 0x00000008, 0xac000001, 0x00000018, 0x8000000e, 0x00000000, 0x0380b000,
1226 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c004000, 0x00000010, 0x91d40000,
1227 0x00000008, 0x2d800101, 0x00000000, 0x00000000, 0x00000010, 0x91de0000,
1228 0x0000000c, 0x31620018, 0x00000008, 0x2d800001, 0x00000000, 0x00000000,
1229 0x00000010, 0x91de0000, 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c000e00,
1230 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, 0x00000008, 0x2a000007,
1231 0x00000018, 0x8000ff27, 0x00000010, 0xb1a0b016, 0x0000000b, 0x2fdf0002,
1232 0x00000000, 0x03d80000, 0x00000000, 0x2c200000, 0x00000008, 0x2c8000b0,
1233 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, 0x00000008, 0x2d800150,
1234 0x00000000, 0x00000000, 0x00000010, 0x205f0000, 0x00000008, 0x2c800000,
1235 0x00000008, 0x2d000000, 0x00000008, 0x2d800108, 0x00000008, 0x07000001,
1236 0x00000010, 0xb5de1c00, 0x00000010, 0x2c620002, 0x00000018, 0x8000000a,
1237 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c070000, 0x0000000c, 0x1f800001,
1238 0x00000010, 0x91de0000, 0x00000018, 0x8000ff11, 0x00000008, 0x2c8000b0,
1239 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, 0x00000008, 0x2d800108,
1240 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, 0x00000010, 0x91de0000,
1241 0x00000000, 0x2adf0000, 0x00000008, 0x2a00000a, 0x00000018, 0x8000ff07,
1242 0x00000000, 0x82265600, 0x0000000f, 0x47220008, 0x00000009, 0x070e000f,
1243 0x00000008, 0x070e0008, 0x00000008, 0x02800001, 0x00000007, 0x02851c00,
1244 0x00000008, 0x82850001, 0x00000000, 0x02840a00, 0x00000007, 0x42851c00,
1245 0x00000003, 0xc3aa5200, 0x00000000, 0x03b10e00, 0x00000010, 0x001f0000,
1246 0x0000000f, 0x0f280007, 0x00000007, 0x4b071c00, 0x00000000, 0x00000000,
1247 0x0000000f, 0x0a960003, 0x00000000, 0x0a955c00, 0x00000000, 0x4a005a00,
1248 0x00000000, 0x0c960a00, 0x00000009, 0x0c99ffff, 0x00000008, 0x0d00ffff,
1249 0x00000010, 0xb1963202, 0x00000008, 0x0f800005, 0x00000010, 0x00220020,
1250 0x00000000, 0x02a70000, 0x00000010, 0xb1850002, 0x00000008, 0x82850200,
1251 0x00000000, 0x02000000, 0x00000000, 0x03a60000, 0x00000018, 0x8000004e,
1252 0x00000000, 0x072b0000, 0x00000001, 0x878c1c00, 0x00000000, 0x870e1e00,
1253 0x00000000, 0x860c1e00, 0x00000000, 0x03061e00, 0x00000010, 0xb18e0003,
1254 0x00000018, 0x80000047, 0x00000018, 0x8000fffa, 0x00000010, 0x918c0003,
1255 0x00000010, 0xb1870002, 0x00000018, 0x80000043, 0x00000010, 0x91d40000,
1256 0x0000000c, 0x29800001, 0x00000000, 0x2a860000, 0x00000000, 0x230c0000,
1257 0x00000000, 0x2b070000, 0x00000010, 0xb187000e, 0x00000008, 0x2a000008,
1258 0x00000018, 0x8000003b, 0x00000010, 0x91d40000, 0x00000000, 0x28d18c00,
1259 0x00000000, 0x2a860000, 0x00000000, 0x230c0000, 0x00000000, 0x2b070000,
1260 0x00000018, 0x8000fff8, 0x00000010, 0x91d40000, 0x0000000c, 0x29800001,
1261 0x00000000, 0x2aab0000, 0x00000000, 0xa3265600, 0x00000000, 0x2b000000,
1262 0x0000000c, 0x1f800001, 0x00000008, 0x2a000008, 0x00000018, 0x8000fec8,
1263 0x00000010, 0x91d40000, 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001,
1264 0x00000008, 0x2a000009, 0x00000018, 0x8000fec3, 0x00000010, 0x91d40000,
1265 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, 0x00000000, 0x29420000,
1266 0x00000008, 0x2a000002, 0x00000018, 0x8000febd, 0x00000018, 0x8000febc,
1267 0x00000010, 0xb1bcb016, 0x0000000b, 0x2fdf0002, 0x00000000, 0x03d80000,
1268 0x00000000, 0x2c3c0000, 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008,
1269 0x00000010, 0x91d40000, 0x00000008, 0x2d800150, 0x00000000, 0x00000000,
1270 0x00000010, 0x205f0000, 0x00000008, 0x2c800000, 0x00000008, 0x2d000000,
1271 0x00000008, 0x2d800108, 0x00000008, 0x07000001, 0x00000010, 0xb5de1c00,
1272 0x00000010, 0x2c620002, 0x00000018, 0x8000000a, 0x0000000b, 0x2fdf0002,
1273 0x00000000, 0x2c070000, 0x0000000c, 0x1f800000, 0x00000010, 0x91de0000,
1274 0x00000018, 0x8000fea6, 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008,
1275 0x00000010, 0x91d40000, 0x00000008, 0x2d800108, 0x0000000c, 0x29800000,
1276 0x0000000c, 0x1f800000, 0x00000010, 0x91de0000, 0x00000000, 0x2adf0000,
1277 0x00000008, 0x2a000006, 0x00000018, 0x8000fe9c, 0x00000008, 0x03050004,
1278 0x00000006, 0x83040c00, 0x00000008, 0x02850200, 0x00000000, 0x86050c00,
1279 0x00000001, 0x860c0e00, 0x00000008, 0x02040004, 0x00000000, 0x02041800,
1280 0x00000000, 0x83871800, 0x00000018, 0x00020000 };
1281
1282static u32 bnx2_rv2p_proc2[] = {
1283 0x00000000, 0x2a000000, 0x00000010, 0xb1d40000, 0x00000008, 0x02540003,
1284 0x00000018, 0x00040000, 0x00000018, 0x8000000a, 0x00000018, 0x8000000a,
1285 0x00000018, 0x8000000e, 0x00000018, 0x80000056, 0x00000018, 0x800001b9,
1286 0x00000018, 0x800001e1, 0x00000018, 0x8000019b, 0x00000018, 0x800001f9,
1287 0x00000018, 0x8000019f, 0x00000018, 0x800001a6, 0x00000018, 0x80000000,
1288 0x0000000c, 0x29800001, 0x00000000, 0x2a000000, 0x0000000c, 0x29800000,
1289 0x00000010, 0x20530000, 0x00000018, 0x8000ffee, 0x0000000c, 0x29800001,
1290 0x00000010, 0x91de0000, 0x00000010, 0x001f0000, 0x00000000, 0x2f80aa00,
1291 0x00000000, 0x2a000000, 0x00000000, 0x0d610000, 0x00000000, 0x03620000,
1292 0x00000000, 0x2c400000, 0x00000000, 0x02638c00, 0x00000000, 0x26460000,
1293 0x00000010, 0x00420002, 0x00000008, 0x02040012, 0x00000010, 0xb9060836,
1294 0x00000000, 0x0f580000, 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000,
1295 0x00000000, 0x0b660000, 0x00000000, 0x0c000000, 0x00000000, 0x0b800000,
1296 0x00000010, 0x00420009, 0x00000008, 0x0cc60012, 0x00000008, 0x0f800003,
1297 0x00000000, 0x00000000, 0x00000010, 0x009f0000, 0x00000008, 0x27110012,
1298 0x00000000, 0x66900000, 0x00000008, 0xa31b0012, 0x00000018, 0x80000008,
1299 0x00000000, 0x0cc60000, 0x00000008, 0x0f800003, 0x00000000, 0x00000000,
1300 0x00000010, 0x009f0000, 0x00000000, 0x27110000, 0x00000000, 0x66900000,
1301 0x00000000, 0x231b0000, 0x00000010, 0xb197320e, 0x00000000, 0x25960000,
1302 0x00000000, 0x021b0000, 0x00000010, 0x001f0000, 0x00000008, 0x0f800003,
1303 0x0000000c, 0x29800000, 0x00000010, 0x20530000, 0x00000000, 0x22c50800,
1304 0x00000010, 0x009f0000, 0x00000000, 0x27002200, 0x00000000, 0x26802000,
1305 0x00000000, 0x231b0000, 0x0000000c, 0x69520001, 0x00000018, 0x8000fff3,
1306 0x00000010, 0x01130002, 0x00000010, 0xb1980003, 0x00000010, 0x001f0000,
1307 0x00000008, 0x0f800004, 0x00000008, 0x22000003, 0x00000008, 0x2c80000c,
1308 0x00000008, 0x2d00000c, 0x00000010, 0x009f0000, 0x00000000, 0x25960000,
1309 0x0000000c, 0x29800000, 0x00000000, 0x32140000, 0x00000000, 0x32950000,
1310 0x00000000, 0x33160000, 0x00000000, 0x31e32e00, 0x00000008, 0x2d800010,
1311 0x00000010, 0x20530000, 0x00000018, 0x8000ffac, 0x00000000, 0x23000000,
1312 0x00000000, 0x25e60000, 0x00000008, 0x2200000b, 0x0000000c, 0x69520000,
1313 0x0000000c, 0x29800000, 0x00000010, 0x20530000, 0x00000018, 0x8000ffa5,
1314 0x0000000c, 0x29800001, 0x00000010, 0x91de0000, 0x00000000, 0x2fd50000,
1315 0x00000010, 0x001f0000, 0x00000000, 0x02700000, 0x00000000, 0x0d620000,
1316 0x00000000, 0xbb630800, 0x00000000, 0x2a000000, 0x00000009, 0x076000ff,
1317 0x0000000f, 0x2c0e0007, 0x00000008, 0x2c800000, 0x00000008, 0x2d000064,
1318 0x00000008, 0x2d80011c, 0x00000009, 0x06420002, 0x0000000c, 0x61420001,
1319 0x00000000, 0x0f400000, 0x00000000, 0x02d08c00, 0x00000000, 0x23000000,
1320 0x00000004, 0x826da000, 0x00000000, 0x8304a000, 0x00000000, 0x22c50c00,
1321 0x00000000, 0x03760000, 0x00000004, 0x83860a00, 0x00000000, 0x83870c00,
1322 0x00000010, 0x91de0000, 0x00000000, 0x037c0000, 0x00000000, 0x837b0c00,
1323 0x00000001, 0x83060e00, 0x00000000, 0x83870c00, 0x00000000, 0x82850e00,
1324 0x00000010, 0xb1860016, 0x0000000f, 0x47610018, 0x00000000, 0x068e0000,
1325 0x0000000f, 0x47670010, 0x0000000f, 0x47e20010, 0x00000000, 0x870e1e00,
1326 0x00000010, 0xb70e1a10, 0x00000010, 0x0ce7000e, 0x00000008, 0x22000009,
1327 0x00000000, 0x286d0000, 0x0000000f, 0x65680010, 0x00000003, 0xf66c9400,
1328 0x00000010, 0xb972a003, 0x0000000c, 0x73e70019, 0x0000000c, 0x21420004,
1329 0x00000018, 0x8000023f, 0x00000000, 0x37ed0000, 0x0000000c, 0x73e7001a,
1330 0x00000010, 0x20530000, 0x00000008, 0x22000008, 0x0000000c, 0x61420004,
1331 0x00000000, 0x02f60000, 0x00000004, 0x82840a00, 0x00000010, 0xb1840a2b,
1332 0x00000010, 0x2d67000a, 0x00000010, 0xb96d0804, 0x00000004, 0xb6ed0a00,
1333 0x00000000, 0x37ed0000, 0x00000018, 0x80000029, 0x0000000c, 0x61420000,
1334 0x00000000, 0x37040000, 0x00000000, 0x37850000, 0x0000000c, 0x33e7001a,
1335 0x00000018, 0x80000024, 0x00000010, 0xb96d0809, 0x00000004, 0xb6ed0a00,
1336 0x00000000, 0x036d0000, 0x00000004, 0xb76e0c00, 0x00000010, 0x91ee0c1f,
1337 0x0000000c, 0x73e7001a, 0x00000004, 0xb6ef0c00, 0x00000000, 0x37ed0000,
1338 0x00000018, 0x8000001b, 0x0000000c, 0x61420000, 0x00000010, 0xb7ee0a05,
1339 0x00000010, 0xb96f0815, 0x00000003, 0xb76e0800, 0x00000004, 0xb7ef0a00,
1340 0x00000018, 0x80000015, 0x00000010, 0x0ce7000c, 0x00000008, 0x22000009,
1341 0x00000000, 0x286d0000, 0x0000000f, 0x65680010, 0x00000003, 0xf66c9400,
1342 0x00000010, 0xb972a003, 0x0000000c, 0x73e70019, 0x0000000c, 0x21420004,
1343 0x00000018, 0x80000215, 0x00000010, 0x20530000, 0x00000008, 0x22000008,
1344 0x0000000c, 0x61420004, 0x00000000, 0x37040000, 0x00000000, 0x37850000,
1345 0x00000000, 0x036d0000, 0x00000003, 0xb8f10c00, 0x00000018, 0x80000004,
1346 0x00000000, 0x02840000, 0x00000002, 0x21421800, 0x0000000c, 0x61420000,
1347 0x00000000, 0x286d0000, 0x0000000f, 0x65ed0010, 0x00000009, 0x266dffff,
1348 0x00000000, 0x23000000, 0x00000010, 0xb1840a3d, 0x00000010, 0x01420002,
1349 0x00000004, 0xb8f10a00, 0x00000003, 0x83760a00, 0x00000010, 0xb8040c39,
1350 0x00000010, 0xb7e6080a, 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000,
1351 0x00000009, 0x0c68ffff, 0x00000009, 0x0b67ffff, 0x00000000, 0x0be60000,
1352 0x00000000, 0x0c840000, 0x00000010, 0xb197320c, 0x00000008, 0x0f800002,
1353 0x00000018, 0x8000000a, 0x00000000, 0x0a6a0000, 0x00000000, 0x0aeb0000,
1354 0x00000000, 0x0c000000, 0x00000009, 0x0b6cffff, 0x00000000, 0x0be90000,
1355 0x00000000, 0x0c840000, 0x00000010, 0xb1973203, 0x00000008, 0x0f800002,
1356 0x00000018, 0x80000001, 0x00000010, 0x001f0000, 0x00000000, 0x0c860000,
1357 0x00000000, 0x06980000, 0x00000008, 0x0f800003, 0x00000000, 0x00000000,
1358 0x00000010, 0x009f0000, 0x00000010, 0xb1973210, 0x00000000, 0x231b0000,
1359 0x00000000, 0x02043600, 0x00000003, 0x8384a000, 0x0000000f, 0x65870010,
1360 0x00000009, 0x2607ffff, 0x00000000, 0x27111a00, 0x00000000, 0x66900000,
1361 0x0000000c, 0x29000000, 0x00000018, 0x800001de, 0x00000000, 0x06980000,
1362 0x00000010, 0x20530000, 0x00000000, 0x22c58c00, 0x00000010, 0x001f0000,
1363 0x00000008, 0x0f800003, 0x00000018, 0x8000fff0, 0x00000000, 0x02043600,
1364 0x00000000, 0x231b0000, 0x00000003, 0x8384a000, 0x0000000f, 0x65870010,
1365 0x00000009, 0x2607ffff, 0x00000000, 0x27111a00, 0x00000000, 0x66900000,
1366 0x0000000c, 0x29000000, 0x00000010, 0x91840a02, 0x00000002, 0x21421800,
1367 0x00000000, 0x32140000, 0x00000000, 0x32950000, 0x00000005, 0x73e72c00,
1368 0x00000005, 0x74683000, 0x00000000, 0x33170000, 0x00000018, 0x80000138,
1369 0x00000010, 0x91c60004, 0x00000008, 0x07000004, 0x00000010, 0xb1c41c02,
1370 0x00000010, 0x91840a04, 0x00000018, 0x800001c3, 0x00000010, 0x20530000,
1371 0x00000000, 0x22c58c00, 0x00000010, 0xb1840a8e, 0x0000000c, 0x21420006,
1372 0x00000010, 0x0ce7001a, 0x0000000f, 0x43680010, 0x00000000, 0x03f30c00,
1373 0x00000010, 0x91870850, 0x0000000f, 0x46ec0010, 0x00000010, 0xb68d0c4e,
1374 0x00000000, 0x838d0c00, 0x00000000, 0xa3050800, 0x00000001, 0xa3460e00,
1375 0x00000000, 0x02048c00, 0x00000010, 0x91840a02, 0x00000002, 0x21421800,
1376 0x00000010, 0x001f0000, 0x00000008, 0x22000008, 0x00000003, 0x8384a000,
1377 0x0000000f, 0x65870010, 0x00000009, 0x2607ffff, 0x00000000, 0x27750c00,
1378 0x00000000, 0x66f40000, 0x0000000c, 0x29000000, 0x00000018, 0x800001aa,
1379 0x00000000, 0x03068c00, 0x00000003, 0xf4680c00, 0x00000010, 0x20530000,
1380 0x00000000, 0x22c58c00, 0x00000018, 0x8000ffe5, 0x00000000, 0x39760000,
1381 0x00000000, 0x39840000, 0x0000000c, 0x33e70019, 0x00000010, 0x001f0000,
1382 0x00000000, 0x031e0000, 0x00000000, 0x0760fe00, 0x0000000f, 0x0f0e0007,
1383 0x00000000, 0x83850800, 0x00000000, 0x0a7d0000, 0x00000000, 0x0afe0000,
1384 0x00000000, 0x0b7f0000, 0x00000000, 0x0d7a0000, 0x00000000, 0x0c000000,
1385 0x00000000, 0x0bfc0000, 0x00000000, 0x0c970e00, 0x00000008, 0x0f800003,
1386 0x0000000f, 0x47670010, 0x00000008, 0x070e0001, 0x0000000b, 0xc38000ff,
1387 0x00000002, 0x43870000, 0x00000001, 0x33e70e00, 0x0000000f, 0x038e0010,
1388 0x00000002, 0x33e70e00, 0x00000000, 0x28f30000, 0x00000010, 0x009f0000,
1389 0x00000000, 0x02043600, 0x00000010, 0x91840a02, 0x00000002, 0x21421800,
1390 0x00000008, 0x22000006, 0x00000000, 0x231b0000, 0x00000000, 0x23ff0000,
1391 0x00000000, 0x241b0000, 0x00000003, 0x8384a000, 0x0000000f, 0x65870010,
1392 0x00000009, 0x2607ffff, 0x00000000, 0x27110000, 0x00000000, 0x26900000,
1393 0x0000000c, 0x29000000, 0x00000018, 0x8000017e, 0x00000003, 0xf4683600,
1394 0x00000000, 0x3a100000, 0x00000000, 0x3a910000, 0x00000003, 0xf66c2400,
1395 0x00000010, 0x001f0000, 0x00000010, 0xb1923604, 0x00000008, 0x0f800004,
1396 0x00000000, 0x00000000, 0x00000010, 0x009f0000, 0x00000000, 0x3e170000,
1397 0x00000000, 0x3e940000, 0x00000000, 0x3f150000, 0x00000000, 0x3f960000,
1398 0x00000010, 0x001f0000, 0x00000000, 0x0f060000, 0x00000010, 0x20530000,
1399 0x00000000, 0x22c53600, 0x00000018, 0x8000ffac, 0x00000010, 0x001f0000,
1400 0x00000000, 0x031e0000, 0x00000000, 0x83850800, 0x00000009, 0x076000ff,
1401 0x0000000f, 0x0f0e0007, 0x00000000, 0x0c000000, 0x00000000, 0x0a7d0000,
1402 0x00000000, 0x0afe0000, 0x00000000, 0x0b7f0000, 0x00000000, 0x0d7a0000,
1403 0x00000000, 0x0bfc0000, 0x00000000, 0x0c970e00, 0x00000008, 0x0f800003,
1404 0x0000000f, 0x47670010, 0x00000008, 0x070e0001, 0x0000000b, 0xc38000ff,
1405 0x00000002, 0x43870000, 0x00000001, 0x33e70e00, 0x0000000f, 0x038e0010,
1406 0x00000002, 0x33e70e00, 0x00000000, 0x39840000, 0x00000003, 0xb9720800,
1407 0x00000000, 0x28f30000, 0x0000000f, 0x65680010, 0x00000010, 0x009f0000,
1408 0x00000000, 0x02043600, 0x00000010, 0x91840a02, 0x00000002, 0x21421800,
1409 0x00000008, 0x22000007, 0x00000000, 0x231b0000, 0x00000000, 0x23ff0000,
1410 0x00000000, 0x241b0000, 0x00000003, 0x8384a000, 0x0000000f, 0x65870010,
1411 0x00000009, 0x2607ffff, 0x00000000, 0x27110000, 0x00000000, 0x26900000,
1412 0x0000000c, 0x29000000, 0x00000018, 0x80000145, 0x00000003, 0xf4683600,
1413 0x00000000, 0x3a100000, 0x00000000, 0x3a910000, 0x00000003, 0xf66c2400,
1414 0x00000010, 0x001f0000, 0x00000010, 0xb1923604, 0x00000008, 0x0f800004,
1415 0x00000000, 0x00000000, 0x00000010, 0x009f0000, 0x00000000, 0x3e170000,
1416 0x00000000, 0x3e940000, 0x00000000, 0x3f150000, 0x00000000, 0x3f960000,
1417 0x00000010, 0x001f0000, 0x00000000, 0x0f060000, 0x00000010, 0x20530000,
1418 0x00000000, 0x22c53600, 0x00000018, 0x8000ff73, 0x00000010, 0x0ce70005,
1419 0x00000008, 0x2c80000c, 0x00000008, 0x2d000070, 0x00000008, 0x2d800010,
1420 0x00000000, 0x00000000, 0x00000010, 0x205f0000, 0x00000018, 0x8000011d,
1421 0x00000000, 0x2c1e0000, 0x00000008, 0x2c8000b8, 0x00000008, 0x2d000010,
1422 0x00000008, 0x2d800048, 0x00000000, 0x00000000, 0x00000010, 0x91de0000,
1423 0x00000018, 0x8000fe5d, 0x0000000c, 0x29800001, 0x00000000, 0x2a000000,
1424 0x00000010, 0x001f0000, 0x00000000, 0x0f008000, 0x00000008, 0x0f800007,
1425 0x00000018, 0x80000006, 0x0000000c, 0x29800001, 0x00000000, 0x2a000000,
1426 0x00000010, 0x001f0000, 0x0000000f, 0x0f470007, 0x00000008, 0x0f800008,
1427 0x00000018, 0x80000119, 0x00000010, 0x20530000, 0x00000018, 0x8000fe4f,
1428 0x0000000c, 0x29800001, 0x00000010, 0x91de0000, 0x00000000, 0x2fd50000,
1429 0x00000000, 0x2a000000, 0x00000009, 0x0261ffff, 0x0000000d, 0x70e10001,
1430 0x00000018, 0x80000101, 0x00000000, 0x2c400000, 0x00000008, 0x2c8000c4,
1431 0x00000008, 0x2d00001c, 0x00000008, 0x2d800001, 0x00000005, 0x70e10800,
1432 0x00000010, 0x91de0000, 0x00000018, 0x8000fe41, 0x0000000c, 0x29800001,
1433 0x00000010, 0x91de0000, 0x00000000, 0x2fd50000, 0x00000010, 0x001f0000,
1434 0x00000000, 0x02700000, 0x00000000, 0x0d620000, 0x00000000, 0xbb630800,
1435 0x00000000, 0x2a000000, 0x00000000, 0x0f400000, 0x00000000, 0x2c400000,
1436 0x0000000c, 0x73e7001b, 0x00000010, 0x0ce7000e, 0x00000000, 0x286d0000,
1437 0x0000000f, 0x65ed0010, 0x00000009, 0x266dffff, 0x00000018, 0x80000069,
1438 0x00000008, 0x02000004, 0x00000010, 0x91c40803, 0x00000018, 0x800000f6,
1439 0x00000010, 0x20530000, 0x00000018, 0x800000e5, 0x00000008, 0x2c8000b8,
1440 0x00000008, 0x2d000010, 0x00000008, 0x2d800048, 0x00000018, 0x80000005,
1441 0x00000008, 0x2c8000c4, 0x00000008, 0x2d00001c, 0x00000008, 0x2d800001,
1442 0x00000000, 0x00000000, 0x00000010, 0x205f0000, 0x00000008, 0x2c800048,
1443 0x00000008, 0x2d000068, 0x00000008, 0x2d800104, 0x00000000, 0x00000000,
1444 0x00000010, 0x91de0000, 0x00000000, 0x27f60000, 0x00000010, 0xb87a9e04,
1445 0x00000008, 0x2200000d, 0x00000018, 0x800000e2, 0x00000010, 0x20530000,
1446 0x00000018, 0x8000fe18, 0x0000000c, 0x29800001, 0x00000010, 0x91de0000,
1447 0x00000000, 0x2fd50000, 0x00000010, 0x001f0000, 0x00000000, 0x02700000,
1448 0x00000000, 0x0d620000, 0x00000000, 0xbb630800, 0x00000000, 0x2a000000,
1449 0x00000010, 0x0e670011, 0x00000000, 0x286d0000, 0x0000000f, 0x65ed0010,
1450 0x00000009, 0x266dffff, 0x00000004, 0xb8f1a000, 0x00000000, 0x0f400000,
1451 0x0000000c, 0x73e7001c, 0x00000018, 0x80000040, 0x00000008, 0x02000004,
1452 0x00000010, 0x91c40802, 0x00000018, 0x800000cd, 0x00000000, 0x2c1e0000,
1453 0x00000008, 0x2c8000b8, 0x00000008, 0x2d000010, 0x00000008, 0x2d800048,
1454 0x00000010, 0x20530000, 0x00000010, 0x91de0000, 0x00000018, 0x8000fdfe,
1455 0x0000000c, 0x29800001, 0x00000000, 0x03550000, 0x00000000, 0x06460000,
1456 0x00000000, 0x03d60000, 0x00000000, 0x2a000000, 0x0000000f, 0x0f480007,
1457 0x00000010, 0xb18c0027, 0x0000000f, 0x47420008, 0x00000009, 0x070e000f,
1458 0x00000008, 0x070e0008, 0x00000010, 0x001f0000, 0x00000008, 0x09000001,
1459 0x00000007, 0x09121c00, 0x00000003, 0xcbca9200, 0x00000000, 0x0b97a200,
1460 0x00000007, 0x4b171c00, 0x0000000f, 0x0a960003, 0x00000000, 0x0a959c00,
1461 0x00000000, 0x4a009a00, 0x00000008, 0x82120001, 0x00000001, 0x0c170800,
1462 0x00000000, 0x02180000, 0x00000000, 0x0c971800, 0x00000008, 0x0d00ffff,
1463 0x00000008, 0x0f800006, 0x0000000c, 0x29000000, 0x00000008, 0x22000001,
1464 0x00000000, 0x22c50c00, 0x00000010, 0x009f0000, 0x00000010, 0xb197320b,
1465 0x00000000, 0x231b0000, 0x00000000, 0x27110800, 0x00000000, 0x66900000,
1466 0x00000018, 0x800000a4, 0x00000000, 0x02180000, 0x00000010, 0x20530000,
1467 0x00000000, 0x22c53600, 0x00000010, 0x001f0000, 0x00000008, 0x0f800006,
1468 0x00000018, 0x8000fff5, 0x00000010, 0x91870002, 0x00000008, 0x2200000a,
1469 0x00000000, 0x231b0000, 0x00000000, 0x27110800, 0x00000000, 0x66900000,
1470 0x00000018, 0x80000098, 0x00000008, 0x0200000a, 0x00000010, 0x91c40804,
1471 0x00000010, 0x02c20003, 0x00000010, 0x001f0000, 0x00000008, 0x0f800008,
1472 0x00000010, 0x20530000, 0x00000018, 0x8000fdc9, 0x00000000, 0x06820000,
1473 0x00000010, 0x001f0000, 0x00000010, 0x0ce70028, 0x00000000, 0x03720000,
1474 0x00000000, 0xa8760c00, 0x00000000, 0x0cf60000, 0x00000010, 0xb8723224,
1475 0x00000000, 0x03440000, 0x00000008, 0x22000010, 0x00000000, 0x03ca0000,
1476 0x0000000f, 0x65680010, 0x00000000, 0x0bcf0000, 0x00000000, 0x27f20000,
1477 0x00000010, 0xb7ef3203, 0x0000000c, 0x21420004, 0x0000000c, 0x73e70019,
1478 0x00000000, 0x07520000, 0x00000000, 0x29000000, 0x00000018, 0x8000007e,
1479 0x00000004, 0xb9723200, 0x00000010, 0x20530000, 0x00000000, 0x22060000,
1480 0x0000000c, 0x61420004, 0x00000000, 0x25070000, 0x00000000, 0x27970000,
1481 0x00000000, 0x290e0000, 0x00000010, 0x0ce70010, 0x00000010, 0xb873320f,
1482 0x0000000f, 0x436c0010, 0x00000000, 0x03f30c00, 0x00000000, 0x03f30000,
1483 0x00000000, 0x83990e00, 0x00000001, 0x83860e00, 0x00000000, 0x83060e00,
1484 0x00000003, 0xf66c0c00, 0x00000000, 0x39f30e00, 0x00000000, 0x3af50e00,
1485 0x00000000, 0x7a740000, 0x0000000f, 0x43680010, 0x00000001, 0x83860e00,
1486 0x00000000, 0x83060e00, 0x00000003, 0xf4680c00, 0x00000000, 0x286d0000,
1487 0x00000000, 0x03690000, 0x00000010, 0xb1f60c54, 0x00000000, 0x0a6a0000,
1488 0x00000000, 0x0aeb0000, 0x00000009, 0x0b6cffff, 0x00000000, 0x0c000000,
1489 0x00000000, 0x0be90000, 0x00000003, 0x8cf6a000, 0x0000000c, 0x09800002,
1490 0x00000010, 0x009f0000, 0x00000010, 0xb8173209, 0x00000000, 0x35140000,
1491 0x00000000, 0x35950000, 0x00000005, 0x766c2c00, 0x00000000, 0x34970000,
1492 0x00000004, 0xb8f12e00, 0x00000010, 0x001f0000, 0x00000008, 0x0f800004,
1493 0x00000018, 0x8000fff7, 0x00000000, 0x03e90000, 0x00000010, 0xb8f6a01a,
1494 0x00000010, 0x20130019, 0x00000010, 0xb1f10e18, 0x00000000, 0x83973200,
1495 0x00000000, 0x38700e00, 0x00000000, 0xbb760e00, 0x00000000, 0x37d00000,
1496 0x0000000c, 0x73e7001a, 0x00000003, 0xb8f1a000, 0x00000000, 0x32140000,
1497 0x00000000, 0x32950000, 0x00000005, 0x73e72c00, 0x00000000, 0x33190000,
1498 0x00000005, 0x74680000, 0x00000010, 0x0ce7000d, 0x00000008, 0x22000009,
1499 0x00000000, 0x07520000, 0x00000000, 0x29000000, 0x0000000c, 0x73e70019,
1500 0x0000000f, 0x65680010, 0x0000000c, 0x21420004, 0x00000018, 0x8000003c,
1501 0x00000010, 0x20530000, 0x0000000c, 0x61420004, 0x00000000, 0x290e0000,
1502 0x00000018, 0x80000002, 0x00000010, 0x91973206, 0x00000000, 0x35140000,
1503 0x00000000, 0x35950000, 0x00000005, 0x766c2c00, 0x00000000, 0x34990000,
1504 0x00000004, 0xb8f13200, 0x00000000, 0x83690c00, 0x00000010, 0xb1860013,
1505 0x00000000, 0x28e90000, 0x00000008, 0x22000004, 0x00000000, 0x23ec0000,
1506 0x00000000, 0x03690000, 0x00000010, 0xb8660c07, 0x00000009, 0x036cffff,
1507 0x00000000, 0x326a0000, 0x00000000, 0x32eb0000, 0x00000005, 0x73e70c00,
1508 0x00000000, 0x33690000, 0x00000005, 0x74680000, 0x0000000c, 0x73e7001c,
1509 0x00000000, 0x03690000, 0x00000010, 0xb1f60c12, 0x00000010, 0xb1d00c11,
1510 0x0000000c, 0x21420005, 0x0000000c, 0x33e7001c, 0x00000018, 0x8000000e,
1511 0x00000010, 0x2e67000d, 0x00000000, 0x03690000, 0x00000010, 0xb1f60c0b,
1512 0x00000010, 0xb1d00c0a, 0x00000000, 0x03440000, 0x00000008, 0x2200000c,
1513 0x00000000, 0x07520000, 0x00000000, 0x29000000, 0x00000018, 0x80000015,
1514 0x0000000c, 0x33e7001c, 0x00000010, 0x20530000, 0x00000000, 0x22060000,
1515 0x00000000, 0x290e0000, 0x00000018, 0x000d0000, 0x00000000, 0x06820000,
1516 0x00000010, 0x2de7000d, 0x00000010, 0x0ce7000c, 0x00000000, 0x27f20000,
1517 0x00000010, 0xb96d9e0a, 0x00000000, 0xa86d9e00, 0x00000009, 0x0361ffff,
1518 0x00000010, 0xb7500c07, 0x00000008, 0x2200000f, 0x0000000f, 0x65680010,
1519 0x00000000, 0x29000000, 0x00000018, 0x80000004, 0x0000000c, 0x33e7001b,
1520 0x00000010, 0x20530000, 0x00000018, 0x000d0000, 0x00000000, 0x2b820000,
1521 0x00000010, 0x20d2002f, 0x00000010, 0x0052002e, 0x00000009, 0x054e0007,
1522 0x00000010, 0xb18a002c, 0x00000000, 0x050a8c00, 0x00000008, 0x850a0008,
1523 0x00000010, 0x918a0029, 0x00000003, 0xc5008800, 0x00000008, 0xa3460001,
1524 0x00000010, 0xb1c60007, 0x00000008, 0x22000001, 0x0000000c, 0x29800000,
1525 0x00000010, 0x20530000, 0x00000000, 0x274e8c00, 0x00000000, 0x66cd0000,
1526 0x00000000, 0x22c58c00, 0x00000008, 0x22000014, 0x00000003, 0x22c58e00,
1527 0x00000003, 0x23c58e00, 0x00000003, 0x22c58e00, 0x00000003, 0x26cd9e00,
1528 0x00000003, 0x27cd9e00, 0x00000003, 0x26cd9e00, 0x00000003, 0x274ea000,
1529 0x00000003, 0x284ea000, 0x00000003, 0x274ea000, 0x0000000c, 0x69520000,
1530 0x0000000c, 0x29800000, 0x00000010, 0x20530000, 0x00000003, 0x22c58e00,
1531 0x00000003, 0x23c58e00, 0x00000003, 0x22c58e00, 0x00000003, 0x26cd9e00,
1532 0x00000003, 0x27cd9e00, 0x00000003, 0x26cd9e00, 0x00000003, 0x274ea000,
1533 0x00000003, 0x284ea000, 0x00000003, 0x274ea000, 0x00000000, 0xa2c58c00,
1534 0x00000000, 0xa74e8c00, 0x00000000, 0xe6cd0000, 0x0000000f, 0x620a0010,
1535 0x00000008, 0x23460001, 0x0000000c, 0x29800000, 0x00000010, 0x20530000,
1536 0x0000000c, 0x29520000, 0x00000018, 0x80000002, 0x0000000c, 0x29800000,
1537 0x00000018, 0x00570000 };
1538
1539static int bnx2_TPAT_b06FwReleaseMajor = 0x0;
1540static int bnx2_TPAT_b06FwReleaseMinor = 0x0;
1541static int bnx2_TPAT_b06FwReleaseFix = 0x0;
1542static u32 bnx2_TPAT_b06FwStartAddr = 0x08000858;
1543static u32 bnx2_TPAT_b06FwTextAddr = 0x08000800;
1544static int bnx2_TPAT_b06FwTextLen = 0x1314;
1545static u32 bnx2_TPAT_b06FwDataAddr = 0x08001b40;
1546static int bnx2_TPAT_b06FwDataLen = 0x0;
1547static u32 bnx2_TPAT_b06FwRodataAddr = 0x00000000;
1548static int bnx2_TPAT_b06FwRodataLen = 0x0;
1549static u32 bnx2_TPAT_b06FwBssAddr = 0x08001b90;
1550static int bnx2_TPAT_b06FwBssLen = 0x80;
1551static u32 bnx2_TPAT_b06FwSbssAddr = 0x08001b40;
1552static int bnx2_TPAT_b06FwSbssLen = 0x48;
1553
1554static u32 bnx2_TPAT_b06FwText[(0x1314/4) + 1] = {
1555 0x0a000216, 0x00000000, 0x00000000, 0x0000000d, 0x74706174, 0x20302e36,
1556 0x2e390000, 0x00060901, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1557 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1558 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x10000003,
1559 0x00000000, 0x0000000d, 0x0000000d, 0x3c020800, 0x24421b40, 0x3c030800,
1560 0x24631c10, 0xac400000, 0x0043202b, 0x1480fffd, 0x24420004, 0x3c1d0800,
1561 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100858, 0x3c1c0800, 0x279c1b40,
1562 0x0e00051f, 0x00000000, 0x0000000d, 0x8f820024, 0x27bdffe8, 0xafbf0014,
1563 0x10400004, 0xafb00010, 0x0000000d, 0x00000000, 0x2400015f, 0x8f82001c,
1564 0x8c450008, 0x24030800, 0xaf430178, 0x97430104, 0x3c020008, 0xaf420140,
1565 0x8f820034, 0x30420001, 0x10400006, 0x3070ffff, 0x24020002, 0x2603fffe,
1566 0xa7420146, 0x0a000246, 0xa7430148, 0xa7400146, 0x8f850034, 0x30a20020,
1567 0x0002102b, 0x00021023, 0x30460009, 0x30a30c00, 0x24020400, 0x14620002,
1568 0x34c40001, 0x34c40005, 0xa744014a, 0x3c020800, 0x8c440820, 0x3c030048,
1569 0x24020002, 0x00832025, 0x30a30006, 0x1062000d, 0x2c620003, 0x50400005,
1570 0x24020004, 0x10600012, 0x3c020001, 0x0a000271, 0x00000000, 0x10620007,
1571 0x24020006, 0x1462000f, 0x3c020111, 0x0a000269, 0x00821025, 0x0a000268,
1572 0x3c020101, 0x3c020011, 0x00821025, 0x24030001, 0xaf421000, 0xaf830030,
1573 0x0a000271, 0x00000000, 0x00821025, 0xaf421000, 0xaf800030, 0x00000000,
1574 0x00000000, 0x00000000, 0x00000000, 0x8f830030, 0x1060003f, 0x3c048000,
1575 0x8f421000, 0x00441024, 0x1040fffd, 0x00000000, 0x10600039, 0x00000000,
1576 0x8f421000, 0x3c030020, 0x00431024, 0x10400034, 0x00000000, 0x97421014,
1577 0x14400031, 0x00000000, 0x97421008, 0x8f84001c, 0x24420006, 0x00024082,
1578 0x00081880, 0x00643821, 0x8ce50000, 0x30430003, 0x30420001, 0x10400004,
1579 0x00000000, 0x0000000d, 0x0a0002b0, 0x00081080, 0x5460000f, 0x30a5ffff,
1580 0x3c06ffff, 0x00a62824, 0x0005182b, 0x00a61026, 0x0002102b, 0x00621824,
1581 0x10600004, 0x00000000, 0x0000000d, 0x00000000, 0x240001fc, 0x8ce20000,
1582 0x0a0002af, 0x00462825, 0x0005182b, 0x38a2ffff, 0x0002102b, 0x00621824,
1583 0x10600004, 0x00000000, 0x0000000d, 0x00000000, 0x24000206, 0x8ce20000,
1584 0x3445ffff, 0x00081080, 0x00441021, 0x3c030800, 0xac450000, 0x8c620840,
1585 0x24420001, 0xac620840, 0x8f820008, 0x10400003, 0x00000000, 0x0e000660,
1586 0x00000000, 0x8f840028, 0x02002821, 0x24820008, 0x30421fff, 0x24434000,
1587 0x0343d821, 0x30a30007, 0xaf840018, 0xaf820028, 0xaf420084, 0x10600002,
1588 0x24a20007, 0x3045fff8, 0x8f820044, 0x8f840004, 0x00451821, 0xaf82002c,
1589 0x0064102b, 0xaf830044, 0x14400002, 0x00641023, 0xaf820044, 0x8f840044,
1590 0x34028000, 0x8fbf0014, 0x8fb00010, 0x00821021, 0x03421821, 0x3c021000,
1591 0xaf83001c, 0xaf440080, 0xaf420178, 0x03e00008, 0x27bd0018, 0x8f820024,
1592 0x27bdffe8, 0xafbf0014, 0x10400004, 0xafb00010, 0x0000000d, 0x00000000,
1593 0x24000249, 0x8f85001c, 0x24020001, 0xaf820024, 0x8ca70008, 0xa3800023,
1594 0x8f620004, 0x3c100800, 0x26041b90, 0x00021402, 0xa3820010, 0x304600ff,
1595 0x24c60005, 0x0e00064a, 0x00063082, 0x8f640004, 0x8f430108, 0x3c021000,
1596 0x00621824, 0xa7840020, 0x10600008, 0x00000000, 0x97420104, 0x93830023,
1597 0x2442ffec, 0x34630002, 0xa3830023, 0x0a000304, 0x3045ffff, 0x97420104,
1598 0x2442fff0, 0x3045ffff, 0x8f620004, 0x3042ffff, 0x2c420013, 0x14400004,
1599 0x00000000, 0x93820023, 0x34420001, 0xa3820023, 0x93830023, 0x24020001,
1600 0x10620009, 0x28620002, 0x14400014, 0x24020002, 0x10620012, 0x24020003,
1601 0x1062000a, 0x00000000, 0x0a000325, 0x00000000, 0x8f82001c, 0x8c43000c,
1602 0x3c04ffff, 0x00641824, 0x00651825, 0x0a000325, 0xac43000c, 0x8f82001c,
1603 0x8c430010, 0x3c04ffff, 0x00641824, 0x00651825, 0xac430010, 0x8f620004,
1604 0x3042ffff, 0x24420002, 0x00021083, 0xa3820038, 0x304500ff, 0x8f82001c,
1605 0x3c04ffff, 0x00052880, 0x00a22821, 0x8ca70000, 0x97820020, 0x97430104,
1606 0x00e42024, 0x24420002, 0x00621823, 0x00833825, 0xaca70000, 0x93840038,
1607 0x26061b90, 0x00041080, 0x00461021, 0x90430000, 0x3063000f, 0x00832021,
1608 0xa3840022, 0x308200ff, 0x3c04fff6, 0x24420003, 0x00021080, 0x00461021,
1609 0x8c450000, 0x93830022, 0x8f82001c, 0x3484ffff, 0x00a43824, 0x00031880,
1610 0x00621821, 0xaf850000, 0xac67000c, 0x93820022, 0x93830022, 0x8f84001c,
1611 0x24420003, 0x00021080, 0x00461021, 0x24630004, 0x00031880, 0xac470000,
1612 0x93820022, 0x00661821, 0x94670002, 0x00021080, 0x00441021, 0xac670000,
1613 0x24030010, 0xac470010, 0xa7430140, 0x24030002, 0xa7400142, 0xa7400144,
1614 0xa7430146, 0x97420104, 0x8f840034, 0x24030001, 0x2442fffe, 0x30840006,
1615 0xa7420148, 0x24020002, 0xa743014a, 0x1082000d, 0x2c820003, 0x10400005,
1616 0x24020004, 0x10800011, 0x3c020009, 0x0a000383, 0x00000000, 0x10820007,
1617 0x24020006, 0x1482000d, 0x3c020119, 0x0a00037d, 0x24030001, 0x0a00037c,
1618 0x3c020109, 0x3c020019, 0x24030001, 0xaf421000, 0xaf830030, 0x0a000383,
1619 0x00000000, 0xaf421000, 0xaf800030, 0x00000000, 0x00000000, 0x00000000,
1620 0x00000000, 0x93820010, 0x24030008, 0x8f840030, 0x24420002, 0x30420007,
1621 0x00621823, 0x30630007, 0xaf83000c, 0x10800005, 0x3c038000, 0x8f421000,
1622 0x00431024, 0x1040fffd, 0x00000000, 0x8f820028, 0xaf820018, 0x24420010,
1623 0x30421fff, 0xaf820028, 0xaf420084, 0x97430104, 0x24424000, 0x0342d821,
1624 0x3063ffff, 0x30620007, 0x10400002, 0x24620007, 0x3043fff8, 0x8f820044,
1625 0x8f840004, 0x00431821, 0xaf82002c, 0x0064102b, 0xaf830044, 0x14400002,
1626 0x00641023, 0xaf820044, 0x8f840044, 0x34028000, 0x8fbf0014, 0x8fb00010,
1627 0x00821021, 0x03421821, 0x3c021000, 0xaf83001c, 0xaf440080, 0xaf420178,
1628 0x03e00008, 0x27bd0018, 0x8f820024, 0x27bdffe8, 0xafbf0014, 0x14400004,
1629 0xafb00010, 0x0000000d, 0x00000000, 0x240002db, 0x8f620004, 0x04410009,
1630 0x3c050800, 0x93820022, 0x8f830000, 0x24a41b90, 0xaf800024, 0x24420003,
1631 0x00021080, 0x00441021, 0xac430000, 0x93820038, 0x24a51b90, 0x93860010,
1632 0x3c040001, 0x27700008, 0x24420001, 0x00021080, 0x00451021, 0x8c430000,
1633 0x24c60005, 0x00063082, 0x00641821, 0x02002021, 0x0e00064a, 0xac430000,
1634 0x93840022, 0x3c057fff, 0x8f620004, 0x00042080, 0x00902021, 0x8c830004,
1635 0x34a5ffff, 0x00451024, 0x00621821, 0xac830004, 0x93850038, 0x3c07ffff,
1636 0x93840010, 0x00052880, 0x00b02821, 0x8ca30000, 0x97420104, 0x97860020,
1637 0x00671824, 0x00441021, 0x00461023, 0x3042ffff, 0x00621825, 0xaca30000,
1638 0x93830023, 0x24020001, 0x10620009, 0x28620002, 0x1440001a, 0x24020002,
1639 0x10620018, 0x24020003, 0x1062000d, 0x00000000, 0x0a000411, 0x00000000,
1640 0x93820010, 0x97430104, 0x8e04000c, 0x00621821, 0x2463fff2, 0x3063ffff,
1641 0x00872024, 0x00832025, 0x0a000411, 0xae04000c, 0x93820010, 0x97430104,
1642 0x8e040010, 0x00621821, 0x2463ffee, 0x3063ffff, 0x00872024, 0x00832025,
1643 0xae040010, 0x9783000e, 0x8f840034, 0x2402000a, 0xa7420140, 0xa7430142,
1644 0x93820010, 0xa7420144, 0xa7400146, 0x97430104, 0x30840006, 0x24020001,
1645 0xa7430148, 0xa742014a, 0x24020002, 0x1082000d, 0x2c820003, 0x10400005,
1646 0x24020004, 0x10800011, 0x3c020041, 0x0a000437, 0x00000000, 0x10820007,
1647 0x24020006, 0x1482000d, 0x3c020151, 0x0a000431, 0x24030001, 0x0a000430,
1648 0x3c020141, 0x3c020051, 0x24030001, 0xaf421000, 0xaf830030, 0x0a000437,
1649 0x00000000, 0xaf421000, 0xaf800030, 0x00000000, 0x00000000, 0x00000000,
1650 0x00000000, 0x8f820030, 0x93840010, 0x8f850028, 0x10400005, 0x3c038000,
1651 0x8f421000, 0x00431024, 0x1040fffd, 0x00000000, 0x2483000a, 0x30620007,
1652 0x10400002, 0x24620007, 0x304303f8, 0x00a31021, 0x30421fff, 0xaf850018,
1653 0xaf820028, 0xaf420084, 0x97430104, 0x24424000, 0x0342d821, 0x3063ffff,
1654 0x30620007, 0x10400002, 0x24620007, 0x3043fff8, 0x8f820044, 0x8f840004,
1655 0x00431821, 0xaf82002c, 0x0064102b, 0xaf830044, 0x14400002, 0x00641023,
1656 0xaf820044, 0x8f840044, 0x34028000, 0x8fbf0014, 0x8fb00010, 0x00821021,
1657 0x03421821, 0x3c021000, 0xaf83001c, 0xaf440080, 0xaf420178, 0x03e00008,
1658 0x27bd0018, 0x3c026000, 0x8c444448, 0x3c030800, 0xac64082c, 0x8f620000,
1659 0x97430104, 0x3c048000, 0x3046ffff, 0x3067ffff, 0x8f420178, 0x00441024,
1660 0x1440fffd, 0x2402000a, 0x30c30007, 0xa7420140, 0x24020008, 0x00431023,
1661 0x30420007, 0x24c3fffe, 0xa7420142, 0xa7430144, 0xa7400146, 0xa7470148,
1662 0x8f420108, 0x3c036000, 0x8f850034, 0x30420020, 0x0002102b, 0x00021023,
1663 0x30420009, 0x34420001, 0xa742014a, 0x8c644448, 0x3c020800, 0x30a50006,
1664 0xac440830, 0x24020002, 0x10a2000d, 0x2ca20003, 0x10400005, 0x24020004,
1665 0x10a00011, 0x3c020041, 0x0a0004a8, 0x00000000, 0x10a20007, 0x24020006,
1666 0x14a2000d, 0x3c020151, 0x0a0004a2, 0x24030001, 0x0a0004a1, 0x3c020141,
1667 0x3c020051, 0x24030001, 0xaf421000, 0xaf830030, 0x0a0004a8, 0x00000000,
1668 0xaf421000, 0xaf800030, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1669 0x8f820030, 0x24c30008, 0x10400006, 0x30e6ffff, 0x3c048000, 0x8f421000,
1670 0x00441024, 0x1040fffd, 0x00000000, 0x3c026000, 0x8c444448, 0x3065ffff,
1671 0x3c020800, 0x30a30007, 0x10600003, 0xac440834, 0x24a20007, 0x3045fff8,
1672 0x8f840028, 0x00851021, 0x30421fff, 0x24434000, 0x0343d821, 0x30c30007,
1673 0xaf840018, 0xaf820028, 0xaf420084, 0x10600002, 0x24c20007, 0x3046fff8,
1674 0x8f820044, 0x8f840004, 0x00461821, 0xaf82002c, 0x0064102b, 0xaf830044,
1675 0x14400002, 0x00641023, 0xaf820044, 0x8f840044, 0x34028000, 0x3c030800,
1676 0x8c650844, 0x00821021, 0x03421821, 0xaf83001c, 0xaf440080, 0x10a00006,
1677 0x2402000e, 0x93830043, 0x14620004, 0x3c021000, 0x2402043f, 0xa7420148,
1678 0x3c021000, 0x3c036000, 0xaf420178, 0x8c644448, 0x3c020800, 0x03e00008,
1679 0xac440838, 0x8f820034, 0x30424000, 0x10400005, 0x24020800, 0x0000000d,
1680 0x00000000, 0x24000405, 0x24020800, 0xaf420178, 0x97440104, 0x3c030008,
1681 0xaf430140, 0x8f820034, 0x30420001, 0x10400006, 0x3085ffff, 0x24020002,
1682 0x24a3fffe, 0xa7420146, 0x0a0004ff, 0xa7430148, 0xa7400146, 0x8f840028,
1683 0x2402000d, 0xa742014a, 0x24830008, 0x30631fff, 0x24624000, 0x0342d821,
1684 0x30a20007, 0xaf840018, 0xaf830028, 0xaf430084, 0x10400002, 0x24a20007,
1685 0x3045fff8, 0x8f820044, 0x8f840004, 0x00451821, 0xaf82002c, 0x0064102b,
1686 0xaf830044, 0x14400002, 0x00641023, 0xaf820044, 0x8f840044, 0x34028000,
1687 0x00821021, 0x03421821, 0x3c021000, 0xaf83001c, 0xaf440080, 0x03e00008,
1688 0xaf420178, 0x27bdffe8, 0x3c046008, 0xafbf0014, 0xafb00010, 0x8c825000,
1689 0x3c1a8000, 0x2403ff7f, 0x375b4000, 0x00431024, 0x3442380c, 0xac825000,
1690 0x8f430008, 0x3c100800, 0x37428000, 0x34630001, 0xaf430008, 0xaf82001c,
1691 0x3c02601c, 0xaf800028, 0xaf400080, 0xaf400084, 0x8c450008, 0x3c036000,
1692 0x8c620808, 0x3c040800, 0x3c030080, 0xac830820, 0x3042fff0, 0x38420010,
1693 0x2c420001, 0xaf850004, 0xaf820008, 0x0e00062f, 0x00000000, 0x8f420000,
1694 0x30420001, 0x1040fffb, 0x00000000, 0x8f440108, 0x30822000, 0xaf840034,
1695 0x10400004, 0x8e02083c, 0x24420001, 0x0a00059d, 0xae02083c, 0x30820200,
1696 0x10400027, 0x00000000, 0x97420104, 0x1040001c, 0x30824000, 0x14400005,
1697 0x00000000, 0x0e00022d, 0x00000000, 0x0a000592, 0x00000000, 0x8f620008,
1698 0x8f630000, 0x24020030, 0x00031e02, 0x306300f0, 0x10620007, 0x28620031,
1699 0x14400031, 0x24020040, 0x10620007, 0x00000000, 0x0a000592, 0x00000000,
1700 0x0e0002dd, 0x00000000, 0x0a000592, 0x00000000, 0x0e0003b8, 0x00000000,
1701 0x0a000592, 0x00000000, 0x30820040, 0x1440002d, 0x00000000, 0x0000000d,
1702 0x00000000, 0x240004a6, 0x0a00059d, 0x00000000, 0x8f430100, 0x24020d00,
1703 0x1462000f, 0x30820006, 0x97420104, 0x10400005, 0x30820040, 0x0e0004e9,
1704 0x00000000, 0x0a000592, 0x00000000, 0x1440001b, 0x00000000, 0x0000000d,
1705 0x00000000, 0x240004b8, 0x0a00059d, 0x00000000, 0x1040000e, 0x30821000,
1706 0x10400005, 0x00000000, 0x0e00065d, 0x00000000, 0x0a000592, 0x00000000,
1707 0x0e00046b, 0x00000000, 0x8f820040, 0x24420001, 0xaf820040, 0x0a00059d,
1708 0x00000000, 0x30820040, 0x14400004, 0x00000000, 0x0000000d, 0x00000000,
1709 0x240004cf, 0x8f420138, 0x3c034000, 0x00431025, 0xaf420138, 0x0a00053f,
1710 0x00000000, 0x3c046008, 0x8c835000, 0x3c1a8000, 0x2402ff7f, 0x375b4000,
1711 0x00621824, 0x3463380c, 0xac835000, 0x8f420008, 0x3c056000, 0x3c03601c,
1712 0x34420001, 0xaf420008, 0x37428000, 0xaf800028, 0xaf82001c, 0xaf400080,
1713 0xaf400084, 0x8c660008, 0x8ca20808, 0x3c040800, 0x3c030080, 0xac830820,
1714 0x3042fff0, 0x38420010, 0x2c420001, 0xaf860004, 0xaf820008, 0x03e00008,
1715 0x00000000, 0x3084ffff, 0x30820007, 0x10400002, 0x24820007, 0x3044fff8,
1716 0x8f820028, 0x00441821, 0x30631fff, 0x24644000, 0x0344d821, 0xaf820018,
1717 0xaf830028, 0x03e00008, 0xaf430084, 0x3084ffff, 0x30820007, 0x10400002,
1718 0x24820007, 0x3044fff8, 0x8f820044, 0x8f830004, 0x00442021, 0xaf82002c,
1719 0x0083102b, 0xaf840044, 0x14400002, 0x00831023, 0xaf820044, 0x8f820044,
1720 0x34038000, 0x00431821, 0x03432021, 0xaf84001c, 0x03e00008, 0xaf420080,
1721 0x8f830034, 0x24020002, 0x30630006, 0x1062000d, 0x2c620003, 0x50400005,
1722 0x24020004, 0x10600012, 0x3c020001, 0x0a000601, 0x00000000, 0x10620007,
1723 0x24020006, 0x1462000f, 0x3c020111, 0x0a0005f9, 0x00821025, 0x0a0005f8,
1724 0x3c020101, 0x3c020011, 0x00821025, 0x24030001, 0xaf421000, 0xaf830030,
1725 0x0a000601, 0x00000000, 0x00821025, 0xaf421000, 0xaf800030, 0x00000000,
1726 0x00000000, 0x00000000, 0x03e00008, 0x00000000, 0x8f820030, 0x10400005,
1727 0x3c038000, 0x8f421000, 0x00431024, 0x1040fffd, 0x00000000, 0x03e00008,
1728 0x00000000, 0x8f820034, 0x27bdffe8, 0x30424000, 0x14400005, 0xafbf0010,
1729 0x0e00022d, 0x00000000, 0x0a00062d, 0x8fbf0010, 0x8f620008, 0x8f630000,
1730 0x24020030, 0x00031e02, 0x306300f0, 0x10620008, 0x28620031, 0x1440000d,
1731 0x8fbf0010, 0x24020040, 0x10620007, 0x00000000, 0x0a00062d, 0x00000000,
1732 0x0e0002dd, 0x00000000, 0x0a00062d, 0x8fbf0010, 0x0e0003b8, 0x00000000,
1733 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x8f84003c, 0x1080000f, 0x3c026000,
1734 0x8c430c3c, 0x30630fff, 0xaf830014, 0x14600011, 0x3082000f, 0x10400005,
1735 0x308200f0, 0x10400003, 0x30820f00, 0x14400006, 0x00000000, 0x0000000d,
1736 0x00000000, 0x2400050e, 0x03e00008, 0x00000000, 0x0000000d, 0x00000000,
1737 0x24000513, 0x03e00008, 0x00000000, 0xaf83003c, 0x03e00008, 0x00000000,
1738 0x10c00007, 0x00000000, 0x8ca20000, 0x24c6ffff, 0x24a50004, 0xac820000,
1739 0x14c0fffb, 0x24840004, 0x03e00008, 0x00000000, 0x0a000659, 0x00a01021,
1740 0xac860000, 0x24840004, 0x00a01021, 0x1440fffc, 0x24a5ffff, 0x03e00008,
1741 0x00000000, 0x0000000d, 0x03e00008, 0x00000000, 0x3c040800, 0x8c82084c,
1742 0x54400007, 0xac80084c, 0x8f820034, 0x24030400, 0x30420c00, 0x1443005b,
1743 0x00000000, 0xac80084c, 0x0000000d, 0x00000000, 0x2400003c, 0x3c026000,
1744 0x8c444448, 0x3c030800, 0xac640850, 0x24000043, 0x97420104, 0x3045ffff,
1745 0x000530c2, 0x24a2007f, 0x000239c2, 0x2400004e, 0x3c046020, 0x24030020,
1746 0xac830000, 0x8c820000, 0x30420020, 0x10400005, 0x3c036020, 0x8c620000,
1747 0x30420020, 0x1440fffd, 0x00000000, 0x3c026020, 0x8c430010, 0x24040001,
1748 0x0087102b, 0x30ea007f, 0x24abfffe, 0x10400010, 0x00034240, 0x3c056020,
1749 0x24090020, 0xaca90000, 0x8ca20000, 0x30420020, 0x10400006, 0x24840001,
1750 0x3c036020, 0x8c620000, 0x30420020, 0x1440fffd, 0x00000000, 0x0087102b,
1751 0x1440fff4, 0x00000000, 0x8f85001c, 0x3c026020, 0x8c430010, 0x3c046020,
1752 0x34848000, 0x006a1825, 0x01034025, 0x2400006b, 0x10c0000b, 0x00000000,
1753 0x8ca30000, 0x24a50004, 0x8ca20000, 0x24a50004, 0x24c6ffff, 0xac820000,
1754 0x24840004, 0xac830000, 0x14c0fff7, 0x24840004, 0x24000077, 0x3c020007,
1755 0x34427700, 0x3c036000, 0xac6223c8, 0xac6b23cc, 0xac6823e4, 0x24000086,
1756 0x3c046000, 0x3c038000, 0x8c8223f8, 0x00431024, 0x1440fffd, 0x3c021000,
1757 0x3c056000, 0x24030019, 0xaca223f8, 0xa743014a, 0x8ca44448, 0x3c020800,
1758 0xac440854, 0x03e00008, 0x00000000, 0x00000000 };
1759
1760static u32 bnx2_TPAT_b06FwData[(0x0/4) + 1] = { 0x00000000 };
1761static u32 bnx2_TPAT_b06FwRodata[(0x0/4) + 1] = { 0x00000000 };
1762static u32 bnx2_TPAT_b06FwBss[(0x80/4) + 1] = { 0x00000000 };
1763static u32 bnx2_TPAT_b06FwSbss[(0x48/4) + 1] = { 0x00000000 };
1764
1765static int bnx2_TXP_b06FwReleaseMajor = 0x0;
1766static int bnx2_TXP_b06FwReleaseMinor = 0x0;
1767static int bnx2_TXP_b06FwReleaseFix = 0x0;
1768static u32 bnx2_TXP_b06FwStartAddr = 0x08002090;
1769static u32 bnx2_TXP_b06FwTextAddr = 0x08000000;
1770static int bnx2_TXP_b06FwTextLen = 0x3ffc;
1771static u32 bnx2_TXP_b06FwDataAddr = 0x08004020;
1772static int bnx2_TXP_b06FwDataLen = 0x0;
1773static u32 bnx2_TXP_b06FwRodataAddr = 0x00000000;
1774static int bnx2_TXP_b06FwRodataLen = 0x0;
1775static u32 bnx2_TXP_b06FwBssAddr = 0x08004060;
1776static int bnx2_TXP_b06FwBssLen = 0x194;
1777static u32 bnx2_TXP_b06FwSbssAddr = 0x08004020;
1778static int bnx2_TXP_b06FwSbssLen = 0x34;
1779static u32 bnx2_TXP_b06FwText[(0x3ffc/4) + 1] = {
1780 0x0a000824, 0x00000000, 0x00000000, 0x0000000d, 0x74787020, 0x302e362e,
1781 0x39000000, 0x00060900, 0x0000000a, 0x000003e8, 0x0000ea60, 0x00000000,
1782 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1783 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1784 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1785 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1786 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1787 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1788 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1789 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1790 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1791 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1792 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1793 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1794 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1795 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1796 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1797 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1798 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1799 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1800 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1801 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1802 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1803 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1804 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1805 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1806 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1807 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1808 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1809 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1810 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1811 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1812 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1813 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1814 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1815 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1816 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1817 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1818 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1819 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1820 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1821 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1822 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1823 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1824 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1825 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1826 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1827 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1828 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1829 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1830 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1831 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1832 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1833 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1834 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1835 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1836 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1837 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1838 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1839 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1840 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1841 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1842 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1843 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1844 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1845 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1846 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1847 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1848 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1849 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1850 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1851 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1852 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1853 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1854 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1855 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1856 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1857 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1858 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1859 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1860 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1861 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1862 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1863 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1864 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1865 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1866 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1867 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1868 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1869 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1870 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1871 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1872 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1873 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1874 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1875 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1876 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1877 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1878 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1879 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1880 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1881 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1882 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1883 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1884 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1885 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1886 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1887 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1888 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1889 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1890 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1891 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1892 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1893 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1894 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1895 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1896 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1897 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1898 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1899 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1900 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1901 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1902 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1903 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1904 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1905 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1906 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1907 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1908 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1909 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1910 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1911 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1912 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1913 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1914 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1915 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1916 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1917 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1918 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1919 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1920 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1921 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1922 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1923 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1924 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1925 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1926 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1927 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1928 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1929 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1930 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1931 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1932 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1933 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1934 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1935 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1936 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1937 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1938 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1939 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1940 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1941 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1942 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1943 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1944 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1945 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1946 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1947 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1948 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1949 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1950 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1951 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1952 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1953 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1954 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1955 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1956 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1957 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1958 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1959 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1960 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1961 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1962 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1963 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1964 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1965 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1966 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1967 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1968 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1969 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1970 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1971 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1972 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1973 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1974 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1975 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1976 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1977 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1978 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1979 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1980 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1981 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1982 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1983 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1984 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1985 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1986 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1987 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1988 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1989 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1990 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1991 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1992 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1993 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1994 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1995 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1996 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1997 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1998 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1999 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2000 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2001 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2002 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2003 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2004 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2005 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2006 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2007 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2008 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2009 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2010 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2011 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2012 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2013 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2014 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2015 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2016 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2017 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2018 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2019 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2020 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2021 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2022 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2023 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2024 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2025 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2026 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2027 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2028 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2029 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2030 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2031 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2032 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2033 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2034 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2035 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2036 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2037 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2038 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2039 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2040 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2041 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2042 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2043 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2044 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2045 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2046 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2047 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2048 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2049 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2050 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2051 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2052 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2053 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2054 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2055 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2056 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2057 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2058 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2059 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2060 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2061 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2062 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2063 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2064 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2065 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2066 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2067 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2068 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2069 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2070 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2071 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2072 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2073 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2074 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2075 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2076 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2077 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2078 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2079 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2080 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2081 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2082 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2083 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2084 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2085 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2086 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2087 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2088 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2089 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2090 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2091 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2092 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2093 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2094 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2095 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2096 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2097 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2098 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2099 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2100 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2101 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2102 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2103 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2104 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2105 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2106 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2107 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2108 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2109 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2110 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2111 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2112 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2113 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2114 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2115 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2116 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2117 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2118 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2119 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2120 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2121 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2122 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2123 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2124 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2125 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2126 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2127 0x00000000, 0x00000000, 0x00000000, 0x10000003, 0x00000000, 0x0000000d,
2128 0x0000000d, 0x3c020800, 0x24424020, 0x3c030800, 0x246341f4, 0xac400000,
2129 0x0043202b, 0x1480fffd, 0x24420004, 0x3c1d0800, 0x37bd7ffc, 0x03a0f021,
2130 0x3c100800, 0x26102090, 0x3c1c0800, 0x279c4020, 0x0e000a0e, 0x00000000,
2131 0x0000000d, 0x8f840014, 0x27bdffe8, 0xafb00010, 0x8f460104, 0x8f830008,
2132 0x8c8500ac, 0xaf430080, 0x948200a8, 0xa7420e10, 0x948300aa, 0xa7430e12,
2133 0x8c8200ac, 0xaf420e18, 0x97430e10, 0xa7430e14, 0x97420e12, 0xa7420e16,
2134 0x8f430e18, 0x00005021, 0x00c53023, 0x10c001a3, 0xaf430e1c, 0x240f0800,
2135 0x3c0e1000, 0x2419fff8, 0x24100010, 0x3c188100, 0x93620008, 0x10400009,
2136 0x00000000, 0x97620010, 0x00c2102b, 0x14400005, 0x00000000, 0x97620010,
2137 0x3042ffff, 0x0a000862, 0xaf420e00, 0xaf460e00, 0x8f420000, 0x30420008,
2138 0x1040fffd, 0x00000000, 0x97420e08, 0x8f450e04, 0x3044ffff, 0x30820001,
2139 0x14400005, 0x00000000, 0x14a00005, 0x3083a040, 0x0a0009e6, 0x00000000,
2140 0x0000000d, 0x3083a040, 0x24020040, 0x14620049, 0x3082a000, 0x8f87000c,
2141 0x30880036, 0x30890008, 0xaf4f0178, 0x00e01821, 0x9742008a, 0x00431023,
2142 0x2442ffff, 0x30421fff, 0x2c420008, 0x1440fffa, 0x00000000, 0x8f830018,
2143 0x00a05021, 0x00c53023, 0x24e24000, 0x03422821, 0x306b00ff, 0x24630001,
2144 0xaf830018, 0x93840012, 0x000b1400, 0x3c030100, 0x00431025, 0xaca20000,
2145 0x8f820018, 0x30840007, 0x00042240, 0x34870001, 0x00e83825, 0x1120000f,
2146 0xaca20004, 0x97430e0a, 0x8f84000c, 0x00ee3825, 0x2402000e, 0x00781825,
2147 0xaf430160, 0x25430006, 0x24840008, 0x30841fff, 0xa742015a, 0xa7430158,
2148 0xaf84000c, 0x0a0008a9, 0x00000000, 0x8f83000c, 0x25420002, 0xa7420158,
2149 0x24630008, 0x30631fff, 0xaf83000c, 0x54c0000c, 0x8f420e14, 0x97420e10,
2150 0x97430e12, 0x8f840014, 0x00021400, 0x00621825, 0xac8300a8, 0x8f850014,
2151 0x8f420e18, 0x34e70040, 0xaca200ac, 0x8f420e14, 0x8f430e1c, 0xaf420144,
2152 0xaf430148, 0xa34b0152, 0xaf470154, 0x0a0009f1, 0xaf4e0178, 0x10400128,
2153 0x00000000, 0x97620010, 0x00a2102b, 0x10400003, 0x30820040, 0x10400122,
2154 0x00000000, 0xafa60008, 0xa7840010, 0xaf850004, 0x93620008, 0x1440005e,
2155 0x27ac0008, 0xaf60000c, 0x97820010, 0x30424000, 0x10400002, 0x2403000e,
2156 0x24030016, 0xa363000a, 0x24034007, 0xaf630014, 0x93820012, 0x8f630014,
2157 0x30420007, 0x00021240, 0x00621825, 0xaf630014, 0x97820010, 0x8f630014,
2158 0x30420010, 0x00621825, 0xaf630014, 0x97820010, 0x30420008, 0x5040000e,
2159 0x00002821, 0x8f620014, 0x004e1025, 0xaf620014, 0x97430e0a, 0x2402000e,
2160 0x00781825, 0xaf630004, 0xa3620002, 0x9363000a, 0x3405fffc, 0x24630004,
2161 0x0a0008f2, 0xa363000a, 0xaf600004, 0xa3600002, 0x97820010, 0x9363000a,
2162 0x30421f00, 0x00021182, 0x24420028, 0x00621821, 0xa3630009, 0x97420e0c,
2163 0xa7620010, 0x93630009, 0x24020008, 0x24630002, 0x30630007, 0x00431023,
2164 0x30420007, 0xa362000b, 0x93640009, 0x97620010, 0x8f890004, 0x97830010,
2165 0x00441021, 0x00a21021, 0x30630040, 0x10600006, 0x3045ffff, 0x15250005,
2166 0x0125102b, 0x3c068000, 0x0a000925, 0x00005821, 0x0125102b, 0x144000c8,
2167 0x00005021, 0x97420e14, 0xa7420e10, 0x97430e16, 0xa7430e12, 0x8f420e1c,
2168 0xaf420e18, 0xaf450e00, 0x8f420000, 0x30420008, 0x1040fffd, 0x00000000,
2169 0x97420e08, 0x00a04821, 0xa7820010, 0x8f430e04, 0x00003021, 0x240b0001,
2170 0xaf830004, 0x97620010, 0x0a000936, 0x304dffff, 0x8f890004, 0x97820010,
2171 0x30420040, 0x10400004, 0x01206821, 0x3c068000, 0x0a000936, 0x00005821,
2172 0x97630010, 0x8f820004, 0x144300a7, 0x00005021, 0x00003021, 0x240b0001,
2173 0x8d820000, 0x00491023, 0x1440000d, 0xad820000, 0x8f620014, 0x34420040,
2174 0xaf620014, 0x97430e10, 0x97420e12, 0x8f840014, 0x00031c00, 0x00431025,
2175 0xac8200a8, 0x8f830014, 0x8f420e18, 0xac6200ac, 0x93620008, 0x1440003f,
2176 0x00000000, 0x25260002, 0x8f84000c, 0x9743008a, 0x3063ffff, 0xafa30000,
2177 0x8fa20000, 0x00441023, 0x2442ffff, 0x30421fff, 0x2c420010, 0x1440fff7,
2178 0x00000000, 0x8f82000c, 0x8f830018, 0x00021082, 0x00021080, 0x24424000,
2179 0x03422821, 0x00605021, 0x24630001, 0x314200ff, 0x00021400, 0xaf830018,
2180 0x3c033200, 0x00431025, 0xaca20000, 0x93630009, 0x9362000a, 0x00031c00,
2181 0x00431025, 0xaca20004, 0x8f830018, 0xaca30008, 0x97820010, 0x30420008,
2182 0x10400002, 0x00c04021, 0x25280006, 0x97430e14, 0x93640002, 0x8f450e1c,
2183 0x8f660004, 0x8f670014, 0xaf4f0178, 0x3063ffff, 0xa7430144, 0x97420e16,
2184 0xa7420146, 0xaf450148, 0xa34a0152, 0x8f82000c, 0x308400ff, 0xa744015a,
2185 0xaf460160, 0xa7480158, 0xaf470154, 0xaf4e0178, 0x00501021, 0x30421fff,
2186 0xaf82000c, 0x0a0009c5, 0x8d820000, 0x93620009, 0x9363000b, 0x8f85000c,
2187 0x2463000a, 0x00435021, 0x25440007, 0x00992024, 0x9743008a, 0x3063ffff,
2188 0xafa30000, 0x8fa20000, 0x00451023, 0x2442ffff, 0x30421fff, 0x0044102b,
2189 0x1440fff7, 0x00000000, 0x8f82000c, 0x8f840018, 0x00021082, 0x00021080,
2190 0x24424000, 0x03422821, 0x00804021, 0x24840001, 0xaf840018, 0x93630009,
2191 0x310200ff, 0x00022400, 0x3c024100, 0x24630002, 0x00621825, 0x00832025,
2192 0xaca40000, 0x8f62000c, 0x00461025, 0xaca20004, 0x97430e14, 0x93640002,
2193 0x8f450e1c, 0x8f660004, 0x8f670014, 0xaf4f0178, 0x3063ffff, 0xa7430144,
2194 0x97420e16, 0x308400ff, 0xa7420146, 0xaf450148, 0xa3480152, 0x8f83000c,
2195 0x25420007, 0x00591024, 0xa744015a, 0xaf460160, 0xa7490158, 0xaf470154,
2196 0xaf4e0178, 0x00621821, 0x30631fff, 0xaf83000c, 0x8d820000, 0x14400005,
2197 0x00000000, 0x8f620014, 0x2403ffbf, 0x00431024, 0xaf620014, 0x8f62000c,
2198 0x004d1021, 0xaf62000c, 0x93630008, 0x14600008, 0x00000000, 0x11600006,
2199 0x00000000, 0x8f630014, 0x3c02efff, 0x3442fffe, 0x00621824, 0xaf630014,
2200 0xa36b0008, 0x01205021, 0x15400016, 0x8fa60008, 0x97420e14, 0x97430e16,
2201 0x8f850014, 0x00021400, 0x00621825, 0xaca300a8, 0x8f840014, 0x8f420e1c,
2202 0x0a0009f3, 0xac8200ac, 0x97420e14, 0x97430e16, 0x8f840014, 0x00021400,
2203 0x00621825, 0xac8300a8, 0x8f850014, 0x8f420e1c, 0x00005021, 0x0a0009f3,
2204 0xaca200ac, 0x14c0fe64, 0x00000000, 0x55400018, 0x8fb00010, 0x3c038000,
2205 0x8f420178, 0x00431024, 0x1440fffd, 0x00000000, 0x97430e14, 0x8f440e1c,
2206 0x24020800, 0xaf420178, 0x3063ffff, 0xa7430144, 0x97420e16, 0x3c031000,
2207 0xa7420146, 0x24020240, 0xaf440148, 0xa3400152, 0xa740015a, 0xaf400160,
2208 0xa7400158, 0xaf420154, 0xaf430178, 0x8fb00010, 0x03e00008, 0x27bd0018,
2209 0x27bdffd8, 0x3c1a8000, 0x3c0420ff, 0x3484fffd, 0x3c020008, 0x03421821,
2210 0xafbf0020, 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0xaf830014,
2211 0xaf440e00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2212 0x3c0200ff, 0x3442fffd, 0x3c046004, 0xaf420e00, 0x8c835000, 0x24130d00,
2213 0x3c120800, 0x3c114000, 0x2402ff7f, 0x00621824, 0x3463380c, 0x24020009,
2214 0xac835000, 0xaf420008, 0xaf800018, 0xaf80000c, 0x0e000fa1, 0x00000000,
2215 0x0e000a96, 0x00000000, 0x3c020800, 0x24504080, 0x8f420000, 0x30420001,
2216 0x1040fffd, 0x00000000, 0x8f440100, 0xaf840008, 0xaf440020, 0x93430108,
2217 0xa3830012, 0x93820012, 0x30420001, 0x10400008, 0x00000000, 0x93820012,
2218 0x30420006, 0x00021100, 0x0e00083b, 0x0050d821, 0x0a000a52, 0x00000000,
2219 0x14930005, 0x00000000, 0x0e00083b, 0x265b4100, 0x0a000a52, 0x00000000,
2220 0x0e000ba3, 0x00000000, 0xaf510138, 0x0a000a36, 0x00000000, 0x27bdfff8,
2221 0x3084ffff, 0x24820007, 0x3044fff8, 0x8f85000c, 0x9743008a, 0x3063ffff,
2222 0xafa30000, 0x8fa20000, 0x00451023, 0x2442ffff, 0x30421fff, 0x0044102b,
2223 0x1440fff7, 0x00000000, 0x8f82000c, 0x00021082, 0x00021080, 0x24424000,
2224 0x03421021, 0x03e00008, 0x27bd0008, 0x3084ffff, 0x8f82000c, 0x24840007,
2225 0x3084fff8, 0x00441021, 0x30421fff, 0xaf82000c, 0x03e00008, 0x00000000,
2226 0x27bdffe8, 0x3c1a8000, 0x3c0420ff, 0x3484fffd, 0x3c020008, 0x03421821,
2227 0xafbf0010, 0xaf830014, 0xaf440e00, 0x00000000, 0x00000000, 0x00000000,
2228 0x00000000, 0x00000000, 0x3c0200ff, 0x3442fffd, 0x3c046004, 0xaf420e00,
2229 0x8c825000, 0x2403ff7f, 0x00431024, 0x3442380c, 0x24030009, 0xac825000,
2230 0xaf430008, 0xaf800018, 0xaf80000c, 0x0e000fa1, 0x00000000, 0x0e000a96,
2231 0x00000000, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x27bdffe8, 0x3c02000a,
2232 0x03421821, 0x3c040800, 0x24844120, 0x24050018, 0xafbf0010, 0xaf830024,
2233 0x0e000fad, 0x00003021, 0x3c050800, 0x3c020800, 0x24423d60, 0xaca24180,
2234 0x24a54180, 0x3c020800, 0x24423e18, 0x3c030800, 0x24633e2c, 0x3c040800,
2235 0xaca20004, 0x3c020800, 0x24423d68, 0xaca30008, 0xac824190, 0x24844190,
2236 0x3c020800, 0x24423da4, 0x3c070800, 0x24e73de4, 0x3c060800, 0x24c63e40,
2237 0x3c050800, 0x24a52b28, 0x3c030800, 0xac820004, 0x3c020800, 0x24423e48,
2238 0xac870008, 0xac86000c, 0xac850010, 0xac6241b0, 0x246341b0, 0x8fbf0010,
2239 0x3c020800, 0x24423e60, 0xac620004, 0xac670008, 0xac66000c, 0xac650010,
2240 0x03e00008, 0x27bd0018, 0x27bdffc8, 0x3c020800, 0x24424120, 0xafbf0030,
2241 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x90470021, 0x8c510008,
2242 0x8c45001c, 0x8f900020, 0x3c060800, 0x3c038000, 0x8f420178, 0x00431024,
2243 0x1440fffd, 0x8cc2414c, 0x24c3414c, 0x2473ffd4, 0xaf420144, 0x8e620030,
2244 0x30b22000, 0xaf420148, 0x3c021000, 0xaf50014c, 0xa3470152, 0xa7510158,
2245 0xaf450154, 0xaf420178, 0x12400004, 0x3c030800, 0x8c620030, 0x24420001,
2246 0xac620030, 0x93420109, 0x9344010a, 0x00111c00, 0xafa30018, 0x00071a00,
2247 0xafa50014, 0x8cc5414c, 0x00021600, 0x00042400, 0x00441025, 0x00431025,
2248 0xafa20010, 0x8f440100, 0x8e660030, 0x0e000fe1, 0x02003821, 0x1640000e,
2249 0x8fbf0030, 0x8f820000, 0x8e630030, 0x8c44017c, 0x02031823, 0x00711823,
2250 0x00641823, 0x2c630002, 0x14600006, 0x8fb3002c, 0x0000000d, 0x00000000,
2251 0x240000ca, 0x8fbf0030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
2252 0x03e00008, 0x27bd0038, 0x974309da, 0x00804021, 0xad030000, 0x8f4209dc,
2253 0xad020004, 0x8f4309e0, 0xad030008, 0x934409d9, 0x24020001, 0x30840003,
2254 0x1082001f, 0x30a900ff, 0x28820002, 0x10400005, 0x24020002, 0x10800009,
2255 0x3c0a0800, 0x0a000b64, 0x93420934, 0x1082000b, 0x24020003, 0x10820026,
2256 0x3c0a0800, 0x0a000b64, 0x93420934, 0x974209e4, 0x00021400, 0x34420800,
2257 0xad02000c, 0x0a000b63, 0x25080010, 0x974209e4, 0x00021400, 0x34428100,
2258 0xad02000c, 0x974309e8, 0x3c0a0800, 0x00031c00, 0x34630800, 0xad030010,
2259 0x0a000b63, 0x25080014, 0x974409e4, 0x3c050800, 0x24a24120, 0x94430018,
2260 0x94460010, 0x9447000c, 0x00a05021, 0x24020800, 0xad000010, 0xad020014,
2261 0x00042400, 0x00661821, 0x00671823, 0x2463fff2, 0x00832025, 0xad04000c,
2262 0x0a000b63, 0x25080018, 0x974209e4, 0x3c050800, 0x00021400, 0x34428100,
2263 0xad02000c, 0x974409e8, 0x24a24120, 0x94430018, 0x94460010, 0x9447000c,
2264 0x00a05021, 0x24020800, 0xad000014, 0xad020018, 0x00042400, 0x00661821,
2265 0x00671823, 0x2463ffee, 0x00832025, 0xad040010, 0x2508001c, 0x93420934,
2266 0x93450921, 0x3c074000, 0x25444120, 0x94830014, 0x94860010, 0x00021082,
2267 0x00021600, 0x00052c00, 0x00a72825, 0x00451025, 0x00661821, 0x00431025,
2268 0xad020000, 0x97830028, 0x974209ea, 0x00621821, 0x00031c00, 0xad030004,
2269 0x97820028, 0x24420001, 0x30427fff, 0xa7820028, 0x93430920, 0x3c020006,
2270 0x00031e00, 0x00621825, 0xad030008, 0x8f42092c, 0xad02000c, 0x8f430930,
2271 0xad030010, 0x8f440938, 0x25080014, 0xad040000, 0x8f820020, 0x11200004,
2272 0xad020004, 0x8f420940, 0x0a000b8d, 0x2442ffff, 0x8f420940, 0xad020008,
2273 0x8f440948, 0x8f420940, 0x93430936, 0x00822823, 0x00652806, 0x3402ffff,
2274 0x0045102b, 0x54400001, 0x3405ffff, 0x93420937, 0x25444120, 0x90830020,
2275 0xad000010, 0x00021700, 0x34630010, 0x00031c00, 0x00431025, 0x00451025,
2276 0xad02000c, 0x03e00008, 0x25020014, 0x27bdffb0, 0x3c020008, 0x03421821,
2277 0xafbf004c, 0xafbe0048, 0xafb70044, 0xafb60040, 0xafb5003c, 0xafb40038,
2278 0xafb30034, 0xafb20030, 0xafb1002c, 0xafb00028, 0xaf830000, 0x24020040,
2279 0xaf420814, 0xaf400810, 0x8f420944, 0x8f430950, 0x8f440954, 0x8f45095c,
2280 0xaf820030, 0xaf830020, 0xaf84001c, 0xaf85002c, 0x93430900, 0x24020020,
2281 0x10620005, 0x24020030, 0x10620022, 0x3c030800, 0x0a000bf1, 0x8c62002c,
2282 0x24020088, 0xaf420818, 0x3c020800, 0x24424180, 0xafa20020, 0x93430109,
2283 0x3c020800, 0x10600009, 0x24574190, 0x3c026000, 0x24030100, 0xac43081c,
2284 0x3c030001, 0xac43081c, 0x0000000d, 0x00000000, 0x2400031d, 0x9342010a,
2285 0x30420080, 0x1440001c, 0x00000000, 0x3c026000, 0x24030100, 0xac43081c,
2286 0x3c030001, 0xac43081c, 0x0000000d, 0x00000000, 0x24000324, 0x0a000bf4,
2287 0x00000000, 0x93430109, 0x3063007f, 0x00031140, 0x000318c0, 0x00431021,
2288 0x24430088, 0xaf430818, 0x0000000d, 0x3c020800, 0x244241d0, 0x3c030800,
2289 0x247741e0, 0x0a000bf4, 0xafa20020, 0x24420001, 0x0a000f4c, 0xac62002c,
2290 0x8f840000, 0x8f850020, 0x24020800, 0xaf420178, 0x8f4209a4, 0x8c83017c,
2291 0x00a21023, 0x00431023, 0x2c420002, 0x14400004, 0x00000000, 0x0000000d,
2292 0x00000000, 0x24000349, 0x8f420104, 0x8f430988, 0x00431023, 0x58400005,
2293 0x8f4209a0, 0x0000000d, 0x00000000, 0x2400034d, 0x8f4209a0, 0x3c100800,
2294 0xae02414c, 0x8f4309a4, 0x2604414c, 0x2491ffd4, 0xae230030, 0x8f420104,
2295 0xae250024, 0x00431023, 0xac82ffd4, 0x8fa30020, 0x8c620000, 0x0040f809,
2296 0x0200b021, 0x00409021, 0x32440010, 0x32420002, 0x10400007, 0xafa40024,
2297 0x8e22001c, 0x32500040, 0x2403ffbf, 0x00431024, 0x0a000f13, 0xae22001c,
2298 0x32420020, 0x10400002, 0x3c020800, 0x245741b0, 0x32420001, 0x14400007,
2299 0x00000000, 0x8f820008, 0xaf420080, 0x8ec3414c, 0xaf430e10, 0x8e220030,
2300 0xaf420e18, 0x9343010b, 0x93420905, 0x30420008, 0x1040003c, 0x307400ff,
2301 0x8f820000, 0x8c430074, 0x0460000a, 0x00000000, 0x3c026000, 0x24030100,
2302 0xac43081c, 0x3c030001, 0xac43081c, 0x0000000d, 0x00000000, 0x24000384,
2303 0x8f820000, 0x9044007b, 0x9343010a, 0x14830027, 0x32500040, 0x24072000,
2304 0x3c090800, 0x3c038000, 0x8f420178, 0x00431024, 0x1440fffd, 0x8ec2414c,
2305 0x26c4414c, 0x2484ffd4, 0xaf420144, 0x8c820030, 0x3c030100, 0xaf420148,
2306 0x24020047, 0xaf43014c, 0x00001821, 0xa3420152, 0x3c021000, 0xa7430158,
2307 0xaf470154, 0xaf420178, 0x8ec5414c, 0x8d230030, 0x8c860030, 0x24630001,
2308 0xad230030, 0x93420109, 0x9343010a, 0xafa70014, 0xafa00018, 0x00021600,
2309 0x00031c00, 0x00431025, 0x34424700, 0xafa20010, 0x8f440100, 0x0e000fe1,
2310 0x3c070100, 0x3c030800, 0x24624120, 0x0a000d01, 0x8c43001c, 0x32820002,
2311 0x10400047, 0x3c039000, 0x34630001, 0x8f820008, 0x32500040, 0x3c048000,
2312 0x00431025, 0xaf420020, 0x8f420020, 0x00441024, 0x1440fffd, 0x00000000,
2313 0x8f830000, 0x90620005, 0x3c058000, 0x34420008, 0xa0620005, 0x8f860000,
2314 0x34a50001, 0x8f840008, 0x8cc20074, 0x3c038000, 0x00852025, 0x00431025,
2315 0xacc20074, 0xaf440020, 0x90c3007b, 0x9342010a, 0x14620028, 0x3c040800,
2316 0x24072000, 0x3c090800, 0x3c038000, 0x8f420178, 0x00431024, 0x1440fffd,
2317 0x8ec2414c, 0x26c4414c, 0x2484ffd4, 0xaf420144, 0x8c820030, 0x3c030100,
2318 0xaf420148, 0x24020046, 0xaf43014c, 0x00001821, 0xa3420152, 0x3c021000,
2319 0xa7430158, 0xaf470154, 0xaf420178, 0x8ec5414c, 0x8d230030, 0x8c860030,
2320 0x24630001, 0xad230030, 0x93420109, 0x9343010a, 0xafa70014, 0xafa00018,
2321 0x00021600, 0x00031c00, 0x00431025, 0x34424600, 0xafa20010, 0x8f440100,
2322 0x0e000fe1, 0x3c070100, 0x3c040800, 0x24824120, 0x0a000d01, 0x8c43001c,
2323 0x93420108, 0x30420010, 0x50400050, 0x9343093f, 0x8f860000, 0x90c3007f,
2324 0x90c2007e, 0x90c40080, 0x306800ff, 0x00021600, 0x00081c00, 0x00431025,
2325 0x00042200, 0x90c3007a, 0x90c5000a, 0x00441025, 0x11050028, 0x00623825,
2326 0xa0c8000a, 0x24086000, 0x3c090800, 0x3c038000, 0x8f420178, 0x00431024,
2327 0x1440fffd, 0x8ec2414c, 0x26c4414c, 0x2484ffd4, 0xaf420144, 0x8c820030,
2328 0x00001821, 0xaf420148, 0x24020052, 0xaf47014c, 0xa3420152, 0x3c021000,
2329 0xa7430158, 0xaf480154, 0xaf420178, 0x8ec5414c, 0x8d230030, 0x8c860030,
2330 0x24630001, 0xad230030, 0x93420109, 0x9343010a, 0xafa80014, 0xafa00018,
2331 0x00021600, 0x00031c00, 0x00431025, 0x34425200, 0xafa20010, 0x0e000fe1,
2332 0x8f440100, 0x0a000cfb, 0x00000000, 0x3c026000, 0x24030100, 0xac43081c,
2333 0x3c030001, 0xac43081c, 0x0000000d, 0x00000000, 0x240003cd, 0x16800009,
2334 0x3c040800, 0x3c030800, 0x24624120, 0x8c43001c, 0x32500040, 0x2404ffbf,
2335 0x00641824, 0x0a000f13, 0xac43001c, 0x8c824120, 0x10400005, 0x3c030800,
2336 0x8c620034, 0xac804120, 0x24420001, 0xac620034, 0x9343093f, 0x24020012,
2337 0x1462000f, 0x329e0038, 0x17c0000c, 0x3c030800, 0x8f830000, 0x8c62004c,
2338 0xac62005c, 0x3c020800, 0x24444120, 0x8c82001c, 0x32500040, 0x2403ffbf,
2339 0x00431024, 0x0a000f13, 0xac82001c, 0xac604120, 0x97420908, 0x000211c0,
2340 0xaf420024, 0x97420908, 0x3c030080, 0x34630003, 0x000211c0, 0xaf42080c,
2341 0xaf43081c, 0x974209ec, 0x8f4309a4, 0xa7820028, 0x3c020800, 0x24444120,
2342 0xac830028, 0x93420937, 0x93430934, 0x00021080, 0x00621821, 0xa4830014,
2343 0x934209d8, 0x00621821, 0xa4830016, 0x934209d8, 0x93430934, 0x00809821,
2344 0x00431021, 0x24420010, 0xa4820012, 0x0000a821, 0x24020006, 0x13c00003,
2345 0xae62001c, 0x0a000d82, 0x24120008, 0x8f420958, 0x8f830020, 0x8f84002c,
2346 0x00431023, 0x00832023, 0x04800003, 0xae620004, 0x04410003, 0x0082102b,
2347 0x0a000d4e, 0xae600004, 0x54400001, 0xae640004, 0x8ee20000, 0x0040f809,
2348 0x00000000, 0x00409021, 0x32420001, 0x5440001e, 0x8ee20004, 0x8e630008,
2349 0x1060002b, 0x3c02c000, 0x00621025, 0xaf420e00, 0x8f420000, 0x30420008,
2350 0x1040fffd, 0x00000000, 0x97420e08, 0xa7820010, 0x8f430e04, 0x8e620008,
2351 0xaf830004, 0x8f840004, 0x0044102b, 0x1040000b, 0x24150001, 0x24020100,
2352 0x3c016000, 0xac22081c, 0x3c020001, 0x3c016000, 0xac22081c, 0x0000000d,
2353 0x00000000, 0x24000449, 0x24150001, 0x8ee20004, 0x0040f809, 0x00000000,
2354 0x02429025, 0x32420002, 0x5040001d, 0x8f470940, 0x12a00006, 0x8ec2414c,
2355 0x8f830000, 0xac6200a8, 0x8f840000, 0x8e620030, 0xac8200ac, 0x32420004,
2356 0x50400013, 0x8f470940, 0x3c020800, 0x3283007d, 0x106000fe, 0x245741b0,
2357 0x32820001, 0x50400006, 0x36520002, 0x8f830030, 0x8f420940, 0x106200f7,
2358 0x00000000, 0x36520002, 0x24020008, 0xa660000c, 0xa662000e, 0xae600008,
2359 0xa2600020, 0x8f470940, 0x3c030800, 0x24684120, 0x8d020028, 0x8d050008,
2360 0x9504000c, 0x9506000a, 0x95030022, 0x00451021, 0x00862021, 0x00641821,
2361 0xaf870030, 0xad020028, 0x32820030, 0x10400006, 0xa5030010, 0x91020020,
2362 0x32910040, 0x34420004, 0x0a000dd4, 0xa1020020, 0x93420923, 0x30420040,
2363 0x10400029, 0x32910040, 0x8f830000, 0x8f840020, 0x8c620084, 0x00441023,
2364 0x0442000a, 0x3c039000, 0x95020010, 0x8c630084, 0x00821021, 0x00621823,
2365 0x1c600004, 0x3c039000, 0x91020020, 0x34420001, 0xa1020020, 0x34630001,
2366 0x8f820008, 0x32910040, 0x3c048000, 0x00431025, 0xaf420020, 0x8f420020,
2367 0x00441024, 0x1440fffd, 0x00000000, 0x8f840000, 0x9083003f, 0x2402000a,
2368 0x10620005, 0x2402000c, 0x9083003f, 0x24020008, 0x14620002, 0x24020014,
2369 0xa082003f, 0x8f830008, 0x3c028000, 0x34420001, 0x00621825, 0xaf430020,
2370 0x3c040800, 0x24904120, 0x9602000c, 0x96030016, 0x9604000e, 0x00431021,
2371 0x00442021, 0x24840002, 0x3084ffff, 0x0e000a55, 0xa6020018, 0x8f850018,
2372 0x00a01821, 0xa2030021, 0x8ee60008, 0x00402021, 0x24a50001, 0xaf850018,
2373 0x00c0f809, 0x00000000, 0x00402021, 0x0e000b12, 0x02202821, 0x8ee3000c,
2374 0x0060f809, 0x00402021, 0x96040018, 0x9602000e, 0x00822021, 0x24840002,
2375 0x0e000a6b, 0x3084ffff, 0x3c030800, 0x8c624120, 0x8e030008, 0x3c040800,
2376 0x00431023, 0x14400012, 0xac824120, 0x54600006, 0x8e02001c, 0x3243004a,
2377 0x24020002, 0x14620005, 0x00000000, 0x8e02001c, 0x34420040, 0x0a000e0b,
2378 0xae02001c, 0x52a00006, 0x36520002, 0x8e02002c, 0xaf420e10, 0x8e030030,
2379 0xaf430e18, 0x36520002, 0x52a00008, 0x96670010, 0x8f830000, 0x8f420e10,
2380 0xac6200a8, 0x8f840000, 0x8f420e18, 0xac8200ac, 0x96670010, 0x92680020,
2381 0x24020040, 0xaf420814, 0x8f830020, 0x8f82001c, 0x00671821, 0x00621023,
2382 0xaf830020, 0x58400005, 0x8f42095c, 0x8f820000, 0xaf83001c, 0xac430054,
2383 0x8f42095c, 0x31030008, 0xaf82002c, 0x1060001a, 0x00000000, 0x8f840000,
2384 0x90820120, 0x90830121, 0x304600ff, 0x00c31823, 0x30630007, 0x24020007,
2385 0x1062000e, 0x00000000, 0x90820122, 0x304200fe, 0xa0820122, 0x8f850000,
2386 0x00061880, 0x8f840020, 0x24a20100, 0x00431021, 0x24c30001, 0x30630007,
2387 0xac440000, 0x0a000e40, 0xa0a30120, 0x90820122, 0x34420001, 0xa0820122,
2388 0x14e00003, 0x31020001, 0x10400031, 0x32510002, 0x8f820000, 0x8c43000c,
2389 0x30630001, 0x1060002c, 0x32510002, 0x3c029000, 0x8f830008, 0x34420001,
2390 0x3c048000, 0x00621825, 0xaf430020, 0x8f420020, 0x00441024, 0x1440fffd,
2391 0x00000000, 0x8f870000, 0x8ce2000c, 0x30420001, 0x10400018, 0x00000000,
2392 0x94e2006a, 0x00022880, 0x50a00001, 0x24050001, 0x94e30068, 0x90e40081,
2393 0x3c020800, 0x8c460024, 0x00652821, 0x00852804, 0x00c5102b, 0x54400001,
2394 0x00a03021, 0x3c020800, 0x8c440028, 0x00c4182b, 0x54600001, 0x00c02021,
2395 0x8f430074, 0x2402fffe, 0x00822824, 0x00a31821, 0xace3000c, 0x8f830008,
2396 0x3c028000, 0x34420001, 0x00621825, 0xaf430020, 0x8f830020, 0x3c020800,
2397 0x24504120, 0xae030024, 0x8ee20010, 0x0040f809, 0x00000000, 0x12a00005,
2398 0x00000000, 0x8f420e10, 0xae02002c, 0x8f430e18, 0xae030030, 0x1220feba,
2399 0x0000a821, 0x8f870024, 0x97860028, 0x8f830000, 0x8f820030, 0x8f840020,
2400 0x8f85001c, 0x32500040, 0xa4e6002c, 0xac620044, 0x32420008, 0xac640050,
2401 0xac650054, 0x1040007a, 0x32820020, 0x10400027, 0x32910010, 0x24072000,
2402 0x3c090800, 0x3c038000, 0x8f420178, 0x00431024, 0x1440fffd, 0x8ec2414c,
2403 0x26c4414c, 0x2484ffd4, 0xaf420144, 0x8c820030, 0x3c030400, 0xaf420148,
2404 0x24020041, 0xaf43014c, 0x00001821, 0xa3420152, 0x3c021000, 0xa7430158,
2405 0xaf470154, 0xaf420178, 0x8ec5414c, 0x8d230030, 0x8c860030, 0x24630001,
2406 0xad230030, 0x93420109, 0x9343010a, 0xafa70014, 0xafa00018, 0x00021600,
2407 0x00031c00, 0x00431025, 0x34424100, 0xafa20010, 0x8f440100, 0x0e000fe1,
2408 0x3c070400, 0x12200028, 0x24072000, 0x3c090800, 0x3c038000, 0x8f420178,
2409 0x00431024, 0x1440fffd, 0x8ec2414c, 0x26c4414c, 0x2484ffd4, 0xaf420144,
2410 0x8c820030, 0x3c030300, 0xaf420148, 0x2402004e, 0xaf43014c, 0x00001821,
2411 0xa3420152, 0x3c021000, 0xa7430158, 0xaf470154, 0xaf420178, 0x8ec5414c,
2412 0x8d230030, 0x8c860030, 0x24630001, 0xad230030, 0x93420109, 0x9343010a,
2413 0xafa70014, 0xafa00018, 0x00021600, 0x00031c00, 0x00431025, 0x34424e00,
2414 0xafa20010, 0x8f440100, 0x0e000fe1, 0x3c070300, 0x0a000f0b, 0x8fa30024,
2415 0x32820008, 0x10400026, 0x3c090800, 0x24072000, 0x3c038000, 0x8f420178,
2416 0x00431024, 0x1440fffd, 0x8ec2414c, 0x26c4414c, 0x2484ffd4, 0xaf420144,
2417 0x8c820030, 0x3c030200, 0xaf420148, 0x2402004b, 0xaf43014c, 0x00001821,
2418 0xa3420152, 0x3c021000, 0xa7430158, 0xaf470154, 0xaf420178, 0x8ec5414c,
2419 0x8d230030, 0x8c860030, 0x24630001, 0xad230030, 0x93420109, 0x9343010a,
2420 0xafa70014, 0xafa00018, 0x00021600, 0x00031c00, 0x00431025, 0x34424b00,
2421 0xafa20010, 0x8f440100, 0x0e000fe1, 0x3c070200, 0x8fa30024, 0x14600004,
2422 0x8fa40020, 0x32420010, 0x10400004, 0x00000000, 0x8c820004, 0x0040f809,
2423 0x00000000, 0x12000006, 0x8fa30020, 0x8c620008, 0x0040f809, 0x00000000,
2424 0x0a000f4d, 0x8fbf004c, 0x3c030800, 0x8c62413c, 0x30420040, 0x1440002f,
2425 0x8fbf004c, 0x24040040, 0x8f910020, 0x3c038000, 0x8f420178, 0x00431024,
2426 0x1440fffd, 0x8ec2414c, 0x26d0414c, 0x2610ffd4, 0xaf420144, 0x8e020030,
2427 0x00001821, 0xaf420148, 0x24020049, 0xaf51014c, 0xa3420152, 0x3c021000,
2428 0xa7430158, 0xaf440154, 0xaf420178, 0x8ec5414c, 0x8e060030, 0x93420109,
2429 0x9343010a, 0xafa40014, 0xafa00018, 0x00021600, 0x00031c00, 0x00431025,
2430 0x34424900, 0xafa20010, 0x8f440100, 0x0e000fe1, 0x02203821, 0x8f830000,
2431 0x8e020030, 0x8c64017c, 0x02221023, 0x00441023, 0x2c420002, 0x14400005,
2432 0x8fbf004c, 0x0000000d, 0x00000000, 0x240000ca, 0x8fbf004c, 0x8fbe0048,
2433 0x8fb70044, 0x8fb60040, 0x8fb5003c, 0x8fb40038, 0x8fb30034, 0x8fb20030,
2434 0x8fb1002c, 0x8fb00028, 0x03e00008, 0x27bd0050, 0x03e00008, 0x00001021,
2435 0x3c030800, 0x24654120, 0x8ca40004, 0x8c634120, 0x0064102b, 0x54400001,
2436 0x00602021, 0x9743093c, 0x0083102b, 0x54400001, 0x00801821, 0x00001021,
2437 0xaca30008, 0x03e00008, 0xa4a00022, 0x8f850004, 0x97840010, 0x3c030800,
2438 0x24634120, 0x24020008, 0xa462000e, 0x8f820004, 0xa460000c, 0x000420c2,
2439 0x30840008, 0x2c420001, 0x00021023, 0x30420006, 0xac650008, 0x03e00008,
2440 0xa0640020, 0x3c020800, 0x24424120, 0x90450021, 0x94430018, 0x3c021100,
2441 0xac800004, 0x00052c00, 0x24630002, 0x00621825, 0x00a32825, 0x24820008,
2442 0x03e00008, 0xac850000, 0x0000000d, 0x00000000, 0x2400016f, 0x03e00008,
2443 0x00000000, 0x0000000d, 0x00000000, 0x2400017b, 0x03e00008, 0x00000000,
2444 0x03e00008, 0x00000000, 0x3c020800, 0x24424120, 0xac400008, 0xa4400022,
2445 0x03e00008, 0x24020001, 0x3c020800, 0x24424120, 0x24030008, 0xac400008,
2446 0xa440000c, 0xa443000e, 0xa0400020, 0x03e00008, 0x24020004, 0x03e00008,
2447 0x00001021, 0x10c00007, 0x00000000, 0x8ca20000, 0x24c6ffff, 0x24a50004,
2448 0xac820000, 0x14c0fffb, 0x24840004, 0x03e00008, 0x00000000, 0x0a000fb2,
2449 0x00a01021, 0xac860000, 0x24840004, 0x00a01021, 0x1440fffc, 0x24a5ffff,
2450 0x03e00008, 0x00000000, 0x3c0a0800, 0x8d490068, 0x3c050800, 0x24a51090,
2451 0x00093140, 0x00c51021, 0xac440000, 0x8f440e04, 0x00a61021, 0xac440004,
2452 0x97430e08, 0x97420e0c, 0x00a62021, 0x00031c00, 0x00431025, 0xac820008,
2453 0x8f430e10, 0x00801021, 0xac43000c, 0x8f440e14, 0xac440010, 0x8f430e18,
2454 0x3c0800ff, 0xac430014, 0x8f470e1c, 0x3508ffff, 0x25290001, 0xac470018,
2455 0x3c070800, 0x8ce3006c, 0x9344010a, 0x3c026000, 0x24630001, 0xace3006c,
2456 0x8c434448, 0x3129007f, 0x00a62821, 0xad490068, 0x00042600, 0x00681824,
2457 0x00832025, 0x03e00008, 0xaca4001c, 0x8fac0010, 0x8fad0014, 0x8fae0018,
2458 0x3c0b0800, 0x8d6a0060, 0x3c080800, 0x25080078, 0x000a4940, 0x01281021,
2459 0x01091821, 0xac440000, 0x00601021, 0xac650004, 0xac460008, 0xac67000c,
2460 0xac4c0010, 0xac6d0014, 0x3c036000, 0xac4e0018, 0x8c654448, 0x3c040800,
2461 0x8c820064, 0x254a0001, 0x314a007f, 0x01094021, 0xad6a0060, 0x24420001,
2462 0xac820064, 0x03e00008, 0xad05001c, 0x00000000 };
2463
2464static u32 bnx2_TXP_b06FwData[(0x0/4) + 1] = { 0x00000000 };
2465static u32 bnx2_TXP_b06FwRodata[(0x0/4) + 1] = { 0x00000000 };
2466static u32 bnx2_TXP_b06FwBss[(0x194/4) + 1] = { 0x00000000 };
2467static u32 bnx2_TXP_b06FwSbss[(0x34/4) + 1] = { 0x00000000 };
2468
diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c
index 770e28f98fd5..269a5e407349 100644
--- a/drivers/net/bonding/bond_main.c
+++ b/drivers/net/bonding/bond_main.c
@@ -3037,7 +3037,7 @@ static void bond_activebackup_arp_mon(struct net_device *bond_dev)
3037 bond_set_slave_inactive_flags(bond->current_arp_slave); 3037 bond_set_slave_inactive_flags(bond->current_arp_slave);
3038 3038
3039 /* search for next candidate */ 3039 /* search for next candidate */
3040 bond_for_each_slave_from(bond, slave, i, bond->current_arp_slave) { 3040 bond_for_each_slave_from(bond, slave, i, bond->current_arp_slave->next) {
3041 if (IS_UP(slave->dev)) { 3041 if (IS_UP(slave->dev)) {
3042 slave->link = BOND_LINK_BACK; 3042 slave->link = BOND_LINK_BACK;
3043 bond_set_slave_active_flags(slave); 3043 bond_set_slave_active_flags(slave);
diff --git a/include/linux/if_tr.h b/include/linux/if_tr.h
index a2b01e1e72f2..6688b414c529 100644
--- a/include/linux/if_tr.h
+++ b/include/linux/if_tr.h
@@ -36,8 +36,8 @@ struct trh_hdr {
36 __u8 fc; /* frame control field */ 36 __u8 fc; /* frame control field */
37 __u8 daddr[TR_ALEN]; /* destination address */ 37 __u8 daddr[TR_ALEN]; /* destination address */
38 __u8 saddr[TR_ALEN]; /* source address */ 38 __u8 saddr[TR_ALEN]; /* source address */
39 __u16 rcf; /* route control field */ 39 __be16 rcf; /* route control field */
40 __u16 rseg[8]; /* routing registers */ 40 __be16 rseg[8]; /* routing registers */
41}; 41};
42 42
43#ifdef __KERNEL__ 43#ifdef __KERNEL__
@@ -55,7 +55,7 @@ struct trllc {
55 __u8 ssap; /* source SAP */ 55 __u8 ssap; /* source SAP */
56 __u8 llc; /* LLC control field */ 56 __u8 llc; /* LLC control field */
57 __u8 protid[3]; /* protocol id */ 57 __u8 protid[3]; /* protocol id */
58 __u16 ethertype; /* ether type field */ 58 __be16 ethertype; /* ether type field */
59}; 59};
60 60
61/* Token-Ring statistics collection data. */ 61/* Token-Ring statistics collection data. */
diff --git a/include/linux/mii.h b/include/linux/mii.h
index 20971fe78a8d..374b615ea9ea 100644
--- a/include/linux/mii.h
+++ b/include/linux/mii.h
@@ -65,9 +65,13 @@
65#define ADVERTISE_SLCT 0x001f /* Selector bits */ 65#define ADVERTISE_SLCT 0x001f /* Selector bits */
66#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ 66#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
67#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ 67#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
68#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
68#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 69#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
70#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
69#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 71#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
72#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
70#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 73#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
74#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
71#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ 75#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
72#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ 76#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
73#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */ 77#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
@@ -84,9 +88,13 @@
84/* Link partner ability register. */ 88/* Link partner ability register. */
85#define LPA_SLCT 0x001f /* Same as advertise selector */ 89#define LPA_SLCT 0x001f /* Same as advertise selector */
86#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ 90#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
91#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
87#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ 92#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
93#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
88#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ 94#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
95#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
89#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ 96#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
97#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
90#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ 98#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
91#define LPA_PAUSE_CAP 0x0400 /* Can pause */ 99#define LPA_PAUSE_CAP 0x0400 /* Can pause */
92#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */ 100#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 7b9720e35361..7ccbc2e4272c 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2071,6 +2071,7 @@
2071#define PCI_DEVICE_ID_TIGON3_5703 0x1647 2071#define PCI_DEVICE_ID_TIGON3_5703 0x1647
2072#define PCI_DEVICE_ID_TIGON3_5704 0x1648 2072#define PCI_DEVICE_ID_TIGON3_5704 0x1648
2073#define PCI_DEVICE_ID_TIGON3_5704S_2 0x1649 2073#define PCI_DEVICE_ID_TIGON3_5704S_2 0x1649
2074#define PCI_DEVICE_ID_NX2_5706 0x164a
2074#define PCI_DEVICE_ID_TIGON3_5702FE 0x164d 2075#define PCI_DEVICE_ID_TIGON3_5702FE 0x164d
2075#define PCI_DEVICE_ID_TIGON3_5705 0x1653 2076#define PCI_DEVICE_ID_TIGON3_5705 0x1653
2076#define PCI_DEVICE_ID_TIGON3_5705_2 0x1654 2077#define PCI_DEVICE_ID_TIGON3_5705_2 0x1654
@@ -2090,6 +2091,7 @@
2090#define PCI_DEVICE_ID_TIGON3_5702X 0x16a6 2091#define PCI_DEVICE_ID_TIGON3_5702X 0x16a6
2091#define PCI_DEVICE_ID_TIGON3_5703X 0x16a7 2092#define PCI_DEVICE_ID_TIGON3_5703X 0x16a7
2092#define PCI_DEVICE_ID_TIGON3_5704S 0x16a8 2093#define PCI_DEVICE_ID_TIGON3_5704S 0x16a8
2094#define PCI_DEVICE_ID_NX2_5706S 0x16aa
2093#define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6 2095#define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6
2094#define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7 2096#define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7
2095#define PCI_DEVICE_ID_TIGON3_5781 0x16dd 2097#define PCI_DEVICE_ID_TIGON3_5781 0x16dd
diff --git a/include/linux/pkt_sched.h b/include/linux/pkt_sched.h
index 73d84c071cb1..1d9da36eb9db 100644
--- a/include/linux/pkt_sched.h
+++ b/include/linux/pkt_sched.h
@@ -427,6 +427,7 @@ enum
427 TCA_NETEM_UNSPEC, 427 TCA_NETEM_UNSPEC,
428 TCA_NETEM_CORR, 428 TCA_NETEM_CORR,
429 TCA_NETEM_DELAY_DIST, 429 TCA_NETEM_DELAY_DIST,
430 TCA_NETEM_REORDER,
430 __TCA_NETEM_MAX, 431 __TCA_NETEM_MAX,
431}; 432};
432 433
@@ -437,7 +438,7 @@ struct tc_netem_qopt
437 __u32 latency; /* added delay (us) */ 438 __u32 latency; /* added delay (us) */
438 __u32 limit; /* fifo limit (packets) */ 439 __u32 limit; /* fifo limit (packets) */
439 __u32 loss; /* random packet loss (0=none ~0=100%) */ 440 __u32 loss; /* random packet loss (0=none ~0=100%) */
440 __u32 gap; /* re-ordering gap (0 for delay all) */ 441 __u32 gap; /* re-ordering gap (0 for none) */
441 __u32 duplicate; /* random packet dup (0=none ~0=100%) */ 442 __u32 duplicate; /* random packet dup (0=none ~0=100%) */
442 __u32 jitter; /* random jitter in latency (us) */ 443 __u32 jitter; /* random jitter in latency (us) */
443}; 444};
@@ -449,6 +450,12 @@ struct tc_netem_corr
449 __u32 dup_corr; /* duplicate correlation */ 450 __u32 dup_corr; /* duplicate correlation */
450}; 451};
451 452
453struct tc_netem_reorder
454{
455 __u32 probability;
456 __u32 correlation;
457};
458
452#define NETEM_DIST_SCALE 8192 459#define NETEM_DIST_SCALE 8192
453 460
454#endif 461#endif
diff --git a/include/net/xfrm.h b/include/net/xfrm.h
index e142a256d5dc..d675836ba6c3 100644
--- a/include/net/xfrm.h
+++ b/include/net/xfrm.h
@@ -515,6 +515,8 @@ struct xfrm_dst
515 struct dst_entry *route; 515 struct dst_entry *route;
516 u32 route_mtu_cached; 516 u32 route_mtu_cached;
517 u32 child_mtu_cached; 517 u32 child_mtu_cached;
518 u32 route_cookie;
519 u32 path_cookie;
518}; 520};
519 521
520static inline void xfrm_dst_destroy(struct xfrm_dst *xdst) 522static inline void xfrm_dst_destroy(struct xfrm_dst *xdst)
diff --git a/net/802/tr.c b/net/802/tr.c
index 85293ccf7efc..a755e880f4ba 100644
--- a/net/802/tr.c
+++ b/net/802/tr.c
@@ -47,12 +47,12 @@ static void rif_check_expire(unsigned long dummy);
47 * Each RIF entry we learn is kept this way 47 * Each RIF entry we learn is kept this way
48 */ 48 */
49 49
50struct rif_cache_s { 50struct rif_cache {
51 unsigned char addr[TR_ALEN]; 51 unsigned char addr[TR_ALEN];
52 int iface; 52 int iface;
53 __u16 rcf; 53 __be16 rcf;
54 __u16 rseg[8]; 54 __be16 rseg[8];
55 struct rif_cache_s *next; 55 struct rif_cache *next;
56 unsigned long last_used; 56 unsigned long last_used;
57 unsigned char local_ring; 57 unsigned char local_ring;
58}; 58};
@@ -64,7 +64,7 @@ struct rif_cache_s {
64 * up a lot. 64 * up a lot.
65 */ 65 */
66 66
67static struct rif_cache_s *rif_table[RIF_TABLE_SIZE]; 67static struct rif_cache *rif_table[RIF_TABLE_SIZE];
68 68
69static DEFINE_SPINLOCK(rif_lock); 69static DEFINE_SPINLOCK(rif_lock);
70 70
@@ -249,7 +249,7 @@ void tr_source_route(struct sk_buff *skb,struct trh_hdr *trh,struct net_device *
249{ 249{
250 int slack; 250 int slack;
251 unsigned int hash; 251 unsigned int hash;
252 struct rif_cache_s *entry; 252 struct rif_cache *entry;
253 unsigned char *olddata; 253 unsigned char *olddata;
254 static const unsigned char mcast_func_addr[] 254 static const unsigned char mcast_func_addr[]
255 = {0xC0,0x00,0x00,0x04,0x00,0x00}; 255 = {0xC0,0x00,0x00,0x04,0x00,0x00};
@@ -337,7 +337,7 @@ printk("source routing for %02X:%02X:%02X:%02X:%02X:%02X\n",trh->daddr[0],
337static void tr_add_rif_info(struct trh_hdr *trh, struct net_device *dev) 337static void tr_add_rif_info(struct trh_hdr *trh, struct net_device *dev)
338{ 338{
339 unsigned int hash, rii_p = 0; 339 unsigned int hash, rii_p = 0;
340 struct rif_cache_s *entry; 340 struct rif_cache *entry;
341 341
342 342
343 spin_lock_bh(&rif_lock); 343 spin_lock_bh(&rif_lock);
@@ -373,7 +373,7 @@ printk("adding rif_entry: addr:%02X:%02X:%02X:%02X:%02X:%02X rcf:%04X\n",
373 * FIXME: We ought to keep some kind of cache size 373 * FIXME: We ought to keep some kind of cache size
374 * limiting and adjust the timers to suit. 374 * limiting and adjust the timers to suit.
375 */ 375 */
376 entry=kmalloc(sizeof(struct rif_cache_s),GFP_ATOMIC); 376 entry=kmalloc(sizeof(struct rif_cache),GFP_ATOMIC);
377 377
378 if(!entry) 378 if(!entry)
379 { 379 {
@@ -435,7 +435,7 @@ static void rif_check_expire(unsigned long dummy)
435 spin_lock_bh(&rif_lock); 435 spin_lock_bh(&rif_lock);
436 436
437 for(i =0; i < RIF_TABLE_SIZE; i++) { 437 for(i =0; i < RIF_TABLE_SIZE; i++) {
438 struct rif_cache_s *entry, **pentry; 438 struct rif_cache *entry, **pentry;
439 439
440 pentry = rif_table+i; 440 pentry = rif_table+i;
441 while((entry=*pentry) != NULL) { 441 while((entry=*pentry) != NULL) {
@@ -467,10 +467,10 @@ static void rif_check_expire(unsigned long dummy)
467 467
468#ifdef CONFIG_PROC_FS 468#ifdef CONFIG_PROC_FS
469 469
470static struct rif_cache_s *rif_get_idx(loff_t pos) 470static struct rif_cache *rif_get_idx(loff_t pos)
471{ 471{
472 int i; 472 int i;
473 struct rif_cache_s *entry; 473 struct rif_cache *entry;
474 loff_t off = 0; 474 loff_t off = 0;
475 475
476 for(i = 0; i < RIF_TABLE_SIZE; i++) 476 for(i = 0; i < RIF_TABLE_SIZE; i++)
@@ -493,7 +493,7 @@ static void *rif_seq_start(struct seq_file *seq, loff_t *pos)
493static void *rif_seq_next(struct seq_file *seq, void *v, loff_t *pos) 493static void *rif_seq_next(struct seq_file *seq, void *v, loff_t *pos)
494{ 494{
495 int i; 495 int i;
496 struct rif_cache_s *ent = v; 496 struct rif_cache *ent = v;
497 497
498 ++*pos; 498 ++*pos;
499 499
@@ -522,7 +522,7 @@ static void rif_seq_stop(struct seq_file *seq, void *v)
522static int rif_seq_show(struct seq_file *seq, void *v) 522static int rif_seq_show(struct seq_file *seq, void *v)
523{ 523{
524 int j, rcf_len, segment, brdgnmb; 524 int j, rcf_len, segment, brdgnmb;
525 struct rif_cache_s *entry = v; 525 struct rif_cache *entry = v;
526 526
527 if (v == SEQ_START_TOKEN) 527 if (v == SEQ_START_TOKEN)
528 seq_puts(seq, 528 seq_puts(seq,
diff --git a/net/ipv6/xfrm6_policy.c b/net/ipv6/xfrm6_policy.c
index 4429b1a1fe5f..cf1d91e74c82 100644
--- a/net/ipv6/xfrm6_policy.c
+++ b/net/ipv6/xfrm6_policy.c
@@ -113,6 +113,8 @@ __xfrm6_bundle_create(struct xfrm_policy *policy, struct xfrm_state **xfrm, int
113 113
114 xdst = (struct xfrm_dst *)dst1; 114 xdst = (struct xfrm_dst *)dst1;
115 xdst->route = &rt->u.dst; 115 xdst->route = &rt->u.dst;
116 if (rt->rt6i_node)
117 xdst->route_cookie = rt->rt6i_node->fn_sernum;
116 118
117 dst1->next = dst_prev; 119 dst1->next = dst_prev;
118 dst_prev = dst1; 120 dst_prev = dst1;
@@ -137,6 +139,8 @@ __xfrm6_bundle_create(struct xfrm_policy *policy, struct xfrm_state **xfrm, int
137 139
138 dst_prev->child = &rt->u.dst; 140 dst_prev->child = &rt->u.dst;
139 dst->path = &rt->u.dst; 141 dst->path = &rt->u.dst;
142 if (rt->rt6i_node)
143 ((struct xfrm_dst *)dst)->path_cookie = rt->rt6i_node->fn_sernum;
140 144
141 *dst_p = dst; 145 *dst_p = dst;
142 dst = dst_prev; 146 dst = dst_prev;
diff --git a/net/sched/sch_netem.c b/net/sched/sch_netem.c
index e0c9fbe73b15..bb9bf8d5003c 100644
--- a/net/sched/sch_netem.c
+++ b/net/sched/sch_netem.c
@@ -53,7 +53,6 @@
53 53
54struct netem_sched_data { 54struct netem_sched_data {
55 struct Qdisc *qdisc; 55 struct Qdisc *qdisc;
56 struct sk_buff_head delayed;
57 struct timer_list timer; 56 struct timer_list timer;
58 57
59 u32 latency; 58 u32 latency;
@@ -63,11 +62,12 @@ struct netem_sched_data {
63 u32 gap; 62 u32 gap;
64 u32 jitter; 63 u32 jitter;
65 u32 duplicate; 64 u32 duplicate;
65 u32 reorder;
66 66
67 struct crndstate { 67 struct crndstate {
68 unsigned long last; 68 unsigned long last;
69 unsigned long rho; 69 unsigned long rho;
70 } delay_cor, loss_cor, dup_cor; 70 } delay_cor, loss_cor, dup_cor, reorder_cor;
71 71
72 struct disttable { 72 struct disttable {
73 u32 size; 73 u32 size;
@@ -137,122 +137,68 @@ static long tabledist(unsigned long mu, long sigma,
137 return x / NETEM_DIST_SCALE + (sigma / NETEM_DIST_SCALE) * t + mu; 137 return x / NETEM_DIST_SCALE + (sigma / NETEM_DIST_SCALE) * t + mu;
138} 138}
139 139
140/* Put skb in the private delayed queue. */
141static int netem_delay(struct Qdisc *sch, struct sk_buff *skb)
142{
143 struct netem_sched_data *q = qdisc_priv(sch);
144 psched_tdiff_t td;
145 psched_time_t now;
146
147 PSCHED_GET_TIME(now);
148 td = tabledist(q->latency, q->jitter, &q->delay_cor, q->delay_dist);
149
150 /* Always queue at tail to keep packets in order */
151 if (likely(q->delayed.qlen < q->limit)) {
152 struct netem_skb_cb *cb = (struct netem_skb_cb *)skb->cb;
153
154 PSCHED_TADD2(now, td, cb->time_to_send);
155
156 pr_debug("netem_delay: skb=%p now=%llu tosend=%llu\n", skb,
157 now, cb->time_to_send);
158
159 __skb_queue_tail(&q->delayed, skb);
160 return NET_XMIT_SUCCESS;
161 }
162
163 pr_debug("netem_delay: queue over limit %d\n", q->limit);
164 sch->qstats.overlimits++;
165 kfree_skb(skb);
166 return NET_XMIT_DROP;
167}
168
169/* 140/*
170 * Move a packet that is ready to send from the delay holding 141 * Insert one skb into qdisc.
171 * list to the underlying qdisc. 142 * Note: parent depends on return value to account for queue length.
143 * NET_XMIT_DROP: queue length didn't change.
144 * NET_XMIT_SUCCESS: one skb was queued.
172 */ 145 */
173static int netem_run(struct Qdisc *sch)
174{
175 struct netem_sched_data *q = qdisc_priv(sch);
176 struct sk_buff *skb;
177 psched_time_t now;
178
179 PSCHED_GET_TIME(now);
180
181 skb = skb_peek(&q->delayed);
182 if (skb) {
183 const struct netem_skb_cb *cb
184 = (const struct netem_skb_cb *)skb->cb;
185 long delay
186 = PSCHED_US2JIFFIE(PSCHED_TDIFF(cb->time_to_send, now));
187 pr_debug("netem_run: skb=%p delay=%ld\n", skb, delay);
188
189 /* if more time remaining? */
190 if (delay > 0) {
191 mod_timer(&q->timer, jiffies + delay);
192 return 1;
193 }
194
195 __skb_unlink(skb, &q->delayed);
196
197 if (q->qdisc->enqueue(skb, q->qdisc)) {
198 sch->q.qlen--;
199 sch->qstats.drops++;
200 }
201 }
202
203 return 0;
204}
205
206static int netem_enqueue(struct sk_buff *skb, struct Qdisc *sch) 146static int netem_enqueue(struct sk_buff *skb, struct Qdisc *sch)
207{ 147{
208 struct netem_sched_data *q = qdisc_priv(sch); 148 struct netem_sched_data *q = qdisc_priv(sch);
149 struct netem_skb_cb *cb = (struct netem_skb_cb *)skb->cb;
150 struct sk_buff *skb2;
209 int ret; 151 int ret;
152 int count = 1;
210 153
211 pr_debug("netem_enqueue skb=%p\n", skb); 154 pr_debug("netem_enqueue skb=%p\n", skb);
212 155
156 /* Random duplication */
157 if (q->duplicate && q->duplicate >= get_crandom(&q->dup_cor))
158 ++count;
159
213 /* Random packet drop 0 => none, ~0 => all */ 160 /* Random packet drop 0 => none, ~0 => all */
214 if (q->loss && q->loss >= get_crandom(&q->loss_cor)) { 161 if (q->loss && q->loss >= get_crandom(&q->loss_cor))
215 pr_debug("netem_enqueue: random loss\n"); 162 --count;
163
164 if (count == 0) {
216 sch->qstats.drops++; 165 sch->qstats.drops++;
217 kfree_skb(skb); 166 kfree_skb(skb);
218 return 0; /* lie about loss so TCP doesn't know */ 167 return NET_XMIT_DROP;
219 } 168 }
220 169
221 /* Random duplication */ 170 /*
222 if (q->duplicate && q->duplicate >= get_crandom(&q->dup_cor)) { 171 * If we need to duplicate packet, then re-insert at top of the
223 struct sk_buff *skb2; 172 * qdisc tree, since parent queuer expects that only one
224 173 * skb will be queued.
225 skb2 = skb_clone(skb, GFP_ATOMIC); 174 */
226 if (skb2 && netem_delay(sch, skb2) == NET_XMIT_SUCCESS) { 175 if (count > 1 && (skb2 = skb_clone(skb, GFP_ATOMIC)) != NULL) {
227 struct Qdisc *qp; 176 struct Qdisc *rootq = sch->dev->qdisc;
228 177 u32 dupsave = q->duplicate; /* prevent duplicating a dup... */
229 /* Since one packet can generate two packets in the 178 q->duplicate = 0;
230 * queue, the parent's qlen accounting gets confused, 179
231 * so fix it. 180 rootq->enqueue(skb2, rootq);
232 */ 181 q->duplicate = dupsave;
233 qp = qdisc_lookup(sch->dev, TC_H_MAJ(sch->parent));
234 if (qp)
235 qp->q.qlen++;
236
237 sch->q.qlen++;
238 sch->bstats.bytes += skb2->len;
239 sch->bstats.packets++;
240 } else
241 sch->qstats.drops++;
242 } 182 }
243 183
244 /* If doing simple delay then gap == 0 so all packets 184 if (q->gap == 0 /* not doing reordering */
245 * go into the delayed holding queue 185 || q->counter < q->gap /* inside last reordering gap */
246 * otherwise if doing out of order only "1 out of gap" 186 || q->reorder < get_crandom(&q->reorder_cor)) {
247 * packets will be delayed. 187 psched_time_t now;
248 */ 188 PSCHED_GET_TIME(now);
249 if (q->counter < q->gap) { 189 PSCHED_TADD2(now, tabledist(q->latency, q->jitter,
190 &q->delay_cor, q->delay_dist),
191 cb->time_to_send);
250 ++q->counter; 192 ++q->counter;
251 ret = q->qdisc->enqueue(skb, q->qdisc); 193 ret = q->qdisc->enqueue(skb, q->qdisc);
252 } else { 194 } else {
195 /*
196 * Do re-ordering by putting one out of N packets at the front
197 * of the queue.
198 */
199 PSCHED_GET_TIME(cb->time_to_send);
253 q->counter = 0; 200 q->counter = 0;
254 ret = netem_delay(sch, skb); 201 ret = q->qdisc->ops->requeue(skb, q->qdisc);
255 netem_run(sch);
256 } 202 }
257 203
258 if (likely(ret == NET_XMIT_SUCCESS)) { 204 if (likely(ret == NET_XMIT_SUCCESS)) {
@@ -296,22 +242,33 @@ static struct sk_buff *netem_dequeue(struct Qdisc *sch)
296{ 242{
297 struct netem_sched_data *q = qdisc_priv(sch); 243 struct netem_sched_data *q = qdisc_priv(sch);
298 struct sk_buff *skb; 244 struct sk_buff *skb;
299 int pending;
300
301 pending = netem_run(sch);
302 245
303 skb = q->qdisc->dequeue(q->qdisc); 246 skb = q->qdisc->dequeue(q->qdisc);
304 if (skb) { 247 if (skb) {
305 pr_debug("netem_dequeue: return skb=%p\n", skb); 248 const struct netem_skb_cb *cb
306 sch->q.qlen--; 249 = (const struct netem_skb_cb *)skb->cb;
307 sch->flags &= ~TCQ_F_THROTTLED; 250 psched_time_t now;
308 } 251 long delay;
309 else if (pending) { 252
310 pr_debug("netem_dequeue: throttling\n"); 253 /* if more time remaining? */
254 PSCHED_GET_TIME(now);
255 delay = PSCHED_US2JIFFIE(PSCHED_TDIFF(cb->time_to_send, now));
256 pr_debug("netem_run: skb=%p delay=%ld\n", skb, delay);
257 if (delay <= 0) {
258 pr_debug("netem_dequeue: return skb=%p\n", skb);
259 sch->q.qlen--;
260 sch->flags &= ~TCQ_F_THROTTLED;
261 return skb;
262 }
263
264 mod_timer(&q->timer, jiffies + delay);
311 sch->flags |= TCQ_F_THROTTLED; 265 sch->flags |= TCQ_F_THROTTLED;
312 }
313 266
314 return skb; 267 if (q->qdisc->ops->requeue(skb, q->qdisc) != 0)
268 sch->qstats.drops++;
269 }
270
271 return NULL;
315} 272}
316 273
317static void netem_watchdog(unsigned long arg) 274static void netem_watchdog(unsigned long arg)
@@ -328,8 +285,6 @@ static void netem_reset(struct Qdisc *sch)
328 struct netem_sched_data *q = qdisc_priv(sch); 285 struct netem_sched_data *q = qdisc_priv(sch);
329 286
330 qdisc_reset(q->qdisc); 287 qdisc_reset(q->qdisc);
331 skb_queue_purge(&q->delayed);
332
333 sch->q.qlen = 0; 288 sch->q.qlen = 0;
334 sch->flags &= ~TCQ_F_THROTTLED; 289 sch->flags &= ~TCQ_F_THROTTLED;
335 del_timer_sync(&q->timer); 290 del_timer_sync(&q->timer);
@@ -397,6 +352,19 @@ static int get_correlation(struct Qdisc *sch, const struct rtattr *attr)
397 return 0; 352 return 0;
398} 353}
399 354
355static int get_reorder(struct Qdisc *sch, const struct rtattr *attr)
356{
357 struct netem_sched_data *q = qdisc_priv(sch);
358 const struct tc_netem_reorder *r = RTA_DATA(attr);
359
360 if (RTA_PAYLOAD(attr) != sizeof(*r))
361 return -EINVAL;
362
363 q->reorder = r->probability;
364 init_crandom(&q->reorder_cor, r->correlation);
365 return 0;
366}
367
400static int netem_change(struct Qdisc *sch, struct rtattr *opt) 368static int netem_change(struct Qdisc *sch, struct rtattr *opt)
401{ 369{
402 struct netem_sched_data *q = qdisc_priv(sch); 370 struct netem_sched_data *q = qdisc_priv(sch);
@@ -417,9 +385,15 @@ static int netem_change(struct Qdisc *sch, struct rtattr *opt)
417 q->jitter = qopt->jitter; 385 q->jitter = qopt->jitter;
418 q->limit = qopt->limit; 386 q->limit = qopt->limit;
419 q->gap = qopt->gap; 387 q->gap = qopt->gap;
388 q->counter = 0;
420 q->loss = qopt->loss; 389 q->loss = qopt->loss;
421 q->duplicate = qopt->duplicate; 390 q->duplicate = qopt->duplicate;
422 391
392 /* for compatiablity with earlier versions.
393 * if gap is set, need to assume 100% probablity
394 */
395 q->reorder = ~0;
396
423 /* Handle nested options after initial queue options. 397 /* Handle nested options after initial queue options.
424 * Should have put all options in nested format but too late now. 398 * Should have put all options in nested format but too late now.
425 */ 399 */
@@ -441,6 +415,11 @@ static int netem_change(struct Qdisc *sch, struct rtattr *opt)
441 if (ret) 415 if (ret)
442 return ret; 416 return ret;
443 } 417 }
418 if (tb[TCA_NETEM_REORDER-1]) {
419 ret = get_reorder(sch, tb[TCA_NETEM_REORDER-1]);
420 if (ret)
421 return ret;
422 }
444 } 423 }
445 424
446 425
@@ -455,11 +434,9 @@ static int netem_init(struct Qdisc *sch, struct rtattr *opt)
455 if (!opt) 434 if (!opt)
456 return -EINVAL; 435 return -EINVAL;
457 436
458 skb_queue_head_init(&q->delayed);
459 init_timer(&q->timer); 437 init_timer(&q->timer);
460 q->timer.function = netem_watchdog; 438 q->timer.function = netem_watchdog;
461 q->timer.data = (unsigned long) sch; 439 q->timer.data = (unsigned long) sch;
462 q->counter = 0;
463 440
464 q->qdisc = qdisc_create_dflt(sch->dev, &pfifo_qdisc_ops); 441 q->qdisc = qdisc_create_dflt(sch->dev, &pfifo_qdisc_ops);
465 if (!q->qdisc) { 442 if (!q->qdisc) {
@@ -491,6 +468,7 @@ static int netem_dump(struct Qdisc *sch, struct sk_buff *skb)
491 struct rtattr *rta = (struct rtattr *) b; 468 struct rtattr *rta = (struct rtattr *) b;
492 struct tc_netem_qopt qopt; 469 struct tc_netem_qopt qopt;
493 struct tc_netem_corr cor; 470 struct tc_netem_corr cor;
471 struct tc_netem_reorder reorder;
494 472
495 qopt.latency = q->latency; 473 qopt.latency = q->latency;
496 qopt.jitter = q->jitter; 474 qopt.jitter = q->jitter;
@@ -504,6 +482,11 @@ static int netem_dump(struct Qdisc *sch, struct sk_buff *skb)
504 cor.loss_corr = q->loss_cor.rho; 482 cor.loss_corr = q->loss_cor.rho;
505 cor.dup_corr = q->dup_cor.rho; 483 cor.dup_corr = q->dup_cor.rho;
506 RTA_PUT(skb, TCA_NETEM_CORR, sizeof(cor), &cor); 484 RTA_PUT(skb, TCA_NETEM_CORR, sizeof(cor), &cor);
485
486 reorder.probability = q->reorder;
487 reorder.correlation = q->reorder_cor.rho;
488 RTA_PUT(skb, TCA_NETEM_REORDER, sizeof(reorder), &reorder);
489
507 rta->rta_len = skb->tail - b; 490 rta->rta_len = skb->tail - b;
508 491
509 return skb->len; 492 return skb->len;
diff --git a/net/xfrm/xfrm_policy.c b/net/xfrm/xfrm_policy.c
index 55ed979db144..d07f5ce31824 100644
--- a/net/xfrm/xfrm_policy.c
+++ b/net/xfrm/xfrm_policy.c
@@ -1136,7 +1136,7 @@ int xfrm_bundle_ok(struct xfrm_dst *first, struct flowi *fl, int family)
1136 struct xfrm_dst *last; 1136 struct xfrm_dst *last;
1137 u32 mtu; 1137 u32 mtu;
1138 1138
1139 if (!dst_check(dst->path, 0) || 1139 if (!dst_check(dst->path, ((struct xfrm_dst *)dst)->path_cookie) ||
1140 (dst->dev && !netif_running(dst->dev))) 1140 (dst->dev && !netif_running(dst->dev)))
1141 return 0; 1141 return 0;
1142 1142
@@ -1156,7 +1156,7 @@ int xfrm_bundle_ok(struct xfrm_dst *first, struct flowi *fl, int family)
1156 xdst->child_mtu_cached = mtu; 1156 xdst->child_mtu_cached = mtu;
1157 } 1157 }
1158 1158
1159 if (!dst_check(xdst->route, 0)) 1159 if (!dst_check(xdst->route, xdst->route_cookie))
1160 return 0; 1160 return 0;
1161 mtu = dst_mtu(xdst->route); 1161 mtu = dst_mtu(xdst->route);
1162 if (xdst->route_mtu_cached != mtu) { 1162 if (xdst->route_mtu_cached != mtu) {
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 18:28:11 -0500