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authorSrinidhi Kasagar <srinidhi.kasagar@stericsson.com>2009-11-28 02:10:40 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-11-28 05:22:51 -0500
commitffae4e014a4bff7b904e4b5ace2ae453b9d93519 (patch)
treec0af42f9aa7bfeeaa746c51c19d8d668c669650e
parent59b559d7a39b590aecef583af58d123ff5876570 (diff)
ARM: 5829/1: ARM: U8500 register definitions
Adds register definitions, shared peripheral interrupt numbers (SHPI) and IO mappings for the U8500 core support. SHPI are assigned to [160:32] where first 32 interrupts are reserved. Reviewed-by: Alessandro Rubin <rubini@unipv.it> Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com> Acked-by: Andrea Gallo <andrea.gallo@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat
-rw-r--r--arch/arm/mach-ux500/include/mach/hardware.h131
-rw-r--r--arch/arm/mach-ux500/include/mach/io.h22
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs.h71
3 files changed, 224 insertions, 0 deletions
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
new file mode 100644
index 000000000000..6da650202dc7
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -0,0 +1,131 @@
1/*
2 * Copyright (C) 2009 ST-Ericsson.
3 *
4 * U8500 hardware definitions
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10#ifndef __MACH_HARDWARE_H
11#define __MACH_HARDWARE_H
12
13/* macros to get at IO space when running virtually
14 * We dont map all the peripherals, let ioremap do
15 * this for us. We map only very basic peripherals here.
16 */
17#define U8500_IO_VIRTUAL 0xf0000000
18#define U8500_IO_PHYSICAL 0xa0000000
19
20/* this macro is used in assembly, so no cast */
21#define IO_ADDRESS(x) \
22 (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
23
24/* typesafe io address */
25#define __io_address(n) __io(IO_ADDRESS(n))
26
27/*
28 * Base address definitions for U8500 Onchip IPs. All the
29 * peripherals are contained in a single 1 Mbyte region, with
30 * AHB peripherals at the bottom and APB peripherals at the
31 * top of the region. PER stands for PERIPHERAL region which
32 * itself divided into sub regions.
33 */
34#define U8500_PER3_BASE 0x80000000
35#define U8500_PER2_BASE 0x80110000
36#define U8500_PER1_BASE 0x80120000
37#define U8500_PER4_BASE 0x80150000
38
39#define U8500_PER6_BASE 0xa03c0000
40#define U8500_PER5_BASE 0xa03e0000
41#define U8500_PER7_BASE 0xa03d0000
42
43#define U8500_SVA_BASE 0xa0100000
44#define U8500_SIA_BASE 0xa0200000
45
46#define U8500_SGA_BASE 0xa0300000
47#define U8500_MCDE_BASE 0xa0350000
48#define U8500_DMA_BASE 0xa0362000
49
50#define U8500_SCU_BASE 0xa0410000
51#define U8500_GIC_CPU_BASE 0xa0410100
52#define U8500_TWD_BASE 0xa0410600
53#define U8500_GIC_DIST_BASE 0xa0411000
54#define U8500_L2CC_BASE 0xa0412000
55
56#define U8500_TWD_SIZE 0x100
57
58/* per7 base addressess */
59#define U8500_CR_BASE (U8500_PER7_BASE + 0x8000)
60#define U8500_MTU0_BASE (U8500_PER7_BASE + 0xa000)
61#define U8500_MTU1_BASE (U8500_PER7_BASE + 0xb000)
62#define U8500_TZPC0_BASE (U8500_PER7_BASE + 0xc000)
63#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000)
64
65/* per6 base addressess */
66#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
67#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000)
68#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000)
69#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000)
70#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000)
71#define U8500_CLKRST6_BASE (U8500_PER7_BASE + 0xf000)
72
73/* per5 base addressess */
74#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000)
75#define U8500_GPIO5_BASE (U8500_PER5_BASE + 0x1e000)
76#define U8500_CLKRST5_BASE (U8500_PER7_BASE + 0x1f000)
77
78/* per4 base addressess */
79#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x0000)
80#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x1000)
81#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x2000)
82#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x3000)
83#define U8500_RTC_BASE (U8500_PER4_BASE + 0x4000)
84#define U8500_SCR_BASE (U8500_PER4_BASE + 0x5000)
85#define U8500_DMC_BASE (U8500_PER4_BASE + 0x6000)
86#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x7000)
87
88/* per3 base addressess */
89#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
90#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000)
91#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000)
92#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000)
93#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000)
94#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000)
95#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
96#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000)
97#define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xe000)
98#define U8500_CLKRST3_BASE (U8500_PER7_BASE + 0xf000)
99
100/* per2 base addressess */
101#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000)
102#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000)
103#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000)
104#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000)
105#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000)
106#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000)
107#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000)
108#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000)
109#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000)
110#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000)
111#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000)
112#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xe000)
113#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
114
115/* per1 base addresses */
116#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
117#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
118#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
119#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
120#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
121#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
122#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
123#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
124#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xa000)
125#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xe000)
126#define U8500_CLKRST1_BASE (U8500_PER2_BASE + 0xf000)
127
128/* ST-Ericsson modified pl022 id */
129#define SSP_PER_ID 0x01080022
130
131#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-ux500/include/mach/io.h b/arch/arm/mach-ux500/include/mach/io.h
new file mode 100644
index 000000000000..1cf3f44ce5b2
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/io.h
@@ -0,0 +1,22 @@
1/*
2 * arch/arm/mach-u8500/include/mach/io.h
3 *
4 * Copyright (C) 1997-1999 Russell King
5 *
6 * Modifications:
7 * 06-12-1997 RMK Created.
8 * 07-04-1999 RMK Major cleanup
9 */
10#ifndef __ASM_ARM_ARCH_IO_H
11#define __ASM_ARM_ARCH_IO_H
12
13#define IO_SPACE_LIMIT 0xffffffff
14
15/*
16 * We don't actually have real ISA nor PCI buses, but there is so many
17 * drivers out there that might just work if we fake them...
18 */
19#define __io(a) __typesafe_io(a)
20#define __mem_pci(a) (a)
21
22#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
new file mode 100644
index 000000000000..394b5dd2200f
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -0,0 +1,71 @@
1/*
2 * Copyright (C) 2008 STMicroelectronics
3 * Copyright (C) 2009 ST-Ericsson.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10#ifndef ASM_ARCH_IRQS_H
11#define ASM_ARCH_IRQS_H
12
13#include <mach/hardware.h>
14
15#define IRQ_LOCALTIMER 29
16#define IRQ_LOCALWDOG 30
17
18/* Shared Peripheral Interrupt (SHPI) */
19#define IRQ_SHPI_START 32
20
21/* Interrupt numbers generic for shared peripheral */
22#define IRQ_MTU0 (IRQ_SHPI_START + 4)
23#define IRQ_SPI2 (IRQ_SHPI_START + 6)
24#define IRQ_SPI0 (IRQ_SHPI_START + 8)
25#define IRQ_UART0 (IRQ_SHPI_START + 11)
26#define IRQ_I2C3 (IRQ_SHPI_START + 12)
27#define IRQ_SSP0 (IRQ_SHPI_START + 14)
28#define IRQ_MTU1 (IRQ_SHPI_START + 17)
29#define IRQ_RTC_RTT (IRQ_SHPI_START + 18)
30#define IRQ_UART1 (IRQ_SHPI_START + 19)
31#define IRQ_I2C0 (IRQ_SHPI_START + 21)
32#define IRQ_I2C1 (IRQ_SHPI_START + 22)
33#define IRQ_USBOTG (IRQ_SHPI_START + 23)
34#define IRQ_DMA (IRQ_SHPI_START + 25)
35#define IRQ_UART2 (IRQ_SHPI_START + 26)
36#define IRQ_HSIR_EXCEP (IRQ_SHPI_START + 29)
37#define IRQ_MSP0 (IRQ_SHPI_START + 31)
38#define IRQ_HSIR_CH0_OVRRUN (IRQ_SHPI_START + 32)
39#define IRQ_HSIR_CH1_OVRRUN (IRQ_SHPI_START + 33)
40#define IRQ_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34)
41#define IRQ_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35)
42#define IRQ_AB4500 (IRQ_SHPI_START + 40)
43#define IRQ_DISP (IRQ_SHPI_START + 48)
44#define IRQ_SiPI3 (IRQ_SHPI_START + 49)
45#define IRQ_SSP1 (IRQ_SHPI_START + 52)
46#define IRQ_I2C2 (IRQ_SHPI_START + 55)
47#define IRQ_SDMMC0 (IRQ_SHPI_START + 60)
48#define IRQ_MSP1 (IRQ_SHPI_START + 62)
49#define IRQ_SPI1 (IRQ_SHPI_START + 96)
50#define IRQ_MSP2 (IRQ_SHPI_START + 98)
51#define IRQ_SDMMC4 (IRQ_SHPI_START + 99)
52#define IRQ_HSIRD0 (IRQ_SHPI_START + 104)
53#define IRQ_HSIRD1 (IRQ_SHPI_START + 105)
54#define IRQ_HSITD0 (IRQ_SHPI_START + 106)
55#define IRQ_HSITD1 (IRQ_SHPI_START + 107)
56#define IRQ_GPIO0 (IRQ_SHPI_START + 119)
57#define IRQ_GPIO1 (IRQ_SHPI_START + 120)
58#define IRQ_GPIO2 (IRQ_SHPI_START + 121)
59#define IRQ_GPIO3 (IRQ_SHPI_START + 122)
60#define IRQ_GPIO4 (IRQ_SHPI_START + 123)
61#define IRQ_GPIO5 (IRQ_SHPI_START + 124)
62#define IRQ_GPIO6 (IRQ_SHPI_START + 125)
63#define IRQ_GPIO7 (IRQ_SHPI_START + 126)
64#define IRQ_GPIO8 (IRQ_SHPI_START + 127)
65
66/* There are 128 shared peripheral interrupts assigned to
67 * INTID[160:32]. The first 32 interrupts are reserved.
68 */
69#define NR_IRQS 161
70
71#endif /*ASM_ARCH_IRQS_H*/
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-01 18:16:33 -0500