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authorHaiying Wang <Haiying.Wang@freescale.com>2009-04-29 14:14:33 -0400
committerKumar Gala <galak@kernel.crashing.org>2009-05-19 01:50:21 -0400
commitea5130dcb438840d64a168b67dd221e4d46246b8 (patch)
treeb39cb68104dc68e05501962d40ec3e56a6581c33
parent1e76dff22ce45bc8b869a9956b24a77877915364 (diff)
powerpc/85xx: clean up for mpc8568_mds name
Keep an unique machine def for the MPC8568 MDS board to handle some subtle differences between the future MDS board. Also set the bcsrs in setup_arch() only for mpc8568_mds because other mds has different bcsr settings. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_mds.c29
1 files changed, 15 insertions, 14 deletions
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 7dd029034aec..d34d29acbd3d 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -206,23 +206,24 @@ static void __init mpc85xx_mds_setup_arch(void)
206 } 206 }
207 207
208 if (bcsr_regs) { 208 if (bcsr_regs) {
209 if (machine_is(mpc8568_mds)) {
209#define BCSR_UCC1_GETH_EN (0x1 << 7) 210#define BCSR_UCC1_GETH_EN (0x1 << 7)
210#define BCSR_UCC2_GETH_EN (0x1 << 7) 211#define BCSR_UCC2_GETH_EN (0x1 << 7)
211#define BCSR_UCC1_MODE_MSK (0x3 << 4) 212#define BCSR_UCC1_MODE_MSK (0x3 << 4)
212#define BCSR_UCC2_MODE_MSK (0x3 << 0) 213#define BCSR_UCC2_MODE_MSK (0x3 << 0)
213 214
214 /* Turn off UCC1 & UCC2 */ 215 /* Turn off UCC1 & UCC2 */
215 clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); 216 clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
216 clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); 217 clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
217 218
218 /* Mode is RGMII, all bits clear */ 219 /* Mode is RGMII, all bits clear */
219 clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK | 220 clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
220 BCSR_UCC2_MODE_MSK); 221 BCSR_UCC2_MODE_MSK);
221
222 /* Turn UCC1 & UCC2 on */
223 setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
224 setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
225 222
223 /* Turn UCC1 & UCC2 on */
224 setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
225 setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
226 }
226 iounmap(bcsr_regs); 227 iounmap(bcsr_regs);
227 } 228 }
228#endif /* CONFIG_QUICC_ENGINE */ 229#endif /* CONFIG_QUICC_ENGINE */
@@ -257,7 +258,7 @@ static int __init board_fixups(void)
257 258
258 return 0; 259 return 0;
259} 260}
260machine_arch_initcall(mpc85xx_mds, board_fixups); 261machine_arch_initcall(mpc8568_mds, board_fixups);
261 262
262static struct of_device_id mpc85xx_ids[] = { 263static struct of_device_id mpc85xx_ids[] = {
263 { .type = "soc", }, 264 { .type = "soc", },
@@ -276,7 +277,7 @@ static int __init mpc85xx_publish_devices(void)
276 277
277 return 0; 278 return 0;
278} 279}
279machine_device_initcall(mpc85xx_mds, mpc85xx_publish_devices); 280machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
280 281
281static void __init mpc85xx_mds_pic_init(void) 282static void __init mpc85xx_mds_pic_init(void)
282{ 283{
@@ -321,8 +322,8 @@ static int __init mpc85xx_mds_probe(void)
321 return of_flat_dt_is_compatible(root, "MPC85xxMDS"); 322 return of_flat_dt_is_compatible(root, "MPC85xxMDS");
322} 323}
323 324
324define_machine(mpc85xx_mds) { 325define_machine(mpc8568_mds) {
325 .name = "MPC85xx MDS", 326 .name = "MPC8568 MDS",
326 .probe = mpc85xx_mds_probe, 327 .probe = mpc85xx_mds_probe,
327 .setup_arch = mpc85xx_mds_setup_arch, 328 .setup_arch = mpc85xx_mds_setup_arch,
328 .init_IRQ = mpc85xx_mds_pic_init, 329 .init_IRQ = mpc85xx_mds_pic_init,