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authorMatt Carlson <mcarlson@broadcom.com>2007-07-11 22:47:55 -0400
committerDavid S. Miller <davem@davemloft.net>2007-07-11 22:47:55 -0400
commite8f3f6cad7e423253090887bc4afe7bc844162da (patch)
tree78ffc0e193200e90685bf0137bc97153651e2009
parent469665459d26da8d0b46c70d070da1e192e48e46 (diff)
[TG3]: Fix the polarity bit.
For most pre-5705 devices, multiple link interrupts were being generated for a single physical link change. The source of the interrupts was determined to be unnecessary toggling of the MAC link polarity bit. This patch changes the way the link polarity bit gets configured. Where possible, code that dynamically configures the bit in response to link changes has been replaced by code that configures the bit once during initialization time and then leaves the bit alone. For correctness, this patch also limits the use of the bit to those devices where it is defined, namely devices before the 5705. This patch also corrects the link polarity configurations for 5700 devices when paired against a bcm5411 phy. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/tg3.c63
1 files changed, 44 insertions, 19 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 314f5cfe7246..1df129aa3299 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -1162,6 +1162,19 @@ static void tg3_frob_aux_power(struct tg3 *tp)
1162 } 1162 }
1163} 1163}
1164 1164
1165static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1166{
1167 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1168 return 1;
1169 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1170 if (speed != SPEED_10)
1171 return 1;
1172 } else if (speed == SPEED_10)
1173 return 1;
1174
1175 return 0;
1176}
1177
1165static int tg3_setup_phy(struct tg3 *, int); 1178static int tg3_setup_phy(struct tg3 *, int);
1166 1179
1167#define RESET_KIND_SHUTDOWN 0 1180#define RESET_KIND_SHUTDOWN 0
@@ -1320,9 +1333,17 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1320 else 1333 else
1321 mac_mode = MAC_MODE_PORT_MODE_MII; 1334 mac_mode = MAC_MODE_PORT_MODE_MII;
1322 1335
1323 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 || 1336 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
1324 !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)) 1337 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1325 mac_mode |= MAC_MODE_LINK_POLARITY; 1338 ASIC_REV_5700) {
1339 u32 speed = (tp->tg3_flags &
1340 TG3_FLAG_WOL_SPEED_100MB) ?
1341 SPEED_100 : SPEED_10;
1342 if (tg3_5700_link_polarity(tp, speed))
1343 mac_mode |= MAC_MODE_LINK_POLARITY;
1344 else
1345 mac_mode &= ~MAC_MODE_LINK_POLARITY;
1346 }
1326 } else { 1347 } else {
1327 mac_mode = MAC_MODE_PORT_MODE_TBI; 1348 mac_mode = MAC_MODE_PORT_MODE_TBI;
1328 } 1349 }
@@ -1990,15 +2011,12 @@ relink:
1990 if (tp->link_config.active_duplex == DUPLEX_HALF) 2011 if (tp->link_config.active_duplex == DUPLEX_HALF)
1991 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; 2012 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1992 2013
1993 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1994 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { 2014 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1995 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) || 2015 if (current_link_up == 1 &&
1996 (current_link_up == 1 && 2016 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1997 tp->link_config.active_speed == SPEED_10))
1998 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1999 } else {
2000 if (current_link_up == 1)
2001 tp->mac_mode |= MAC_MODE_LINK_POLARITY; 2017 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2018 else
2019 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2002 } 2020 }
2003 2021
2004 /* ??? Without this setting Netgear GA302T PHY does not 2022 /* ??? Without this setting Netgear GA302T PHY does not
@@ -2639,6 +2657,9 @@ static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2639 2657
2640 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); 2658 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2641 udelay(40); 2659 udelay(40);
2660
2661 tw32_f(MAC_MODE, tp->mac_mode);
2662 udelay(40);
2642 } 2663 }
2643 2664
2644out: 2665out:
@@ -2698,10 +2719,6 @@ static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2698 else 2719 else
2699 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); 2720 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2700 2721
2701 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2702 tw32_f(MAC_MODE, tp->mac_mode);
2703 udelay(40);
2704
2705 tp->hw_status->status = 2722 tp->hw_status->status =
2706 (SD_STATUS_UPDATED | 2723 (SD_STATUS_UPDATED |
2707 (tp->hw_status->status & ~SD_STATUS_LINK_CHG)); 2724 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
@@ -6444,6 +6461,10 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6444 6461
6445 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | 6462 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6446 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE; 6463 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6464 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6465 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6466 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
6467 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
6447 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); 6468 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6448 udelay(40); 6469 udelay(40);
6449 6470
@@ -8805,7 +8826,9 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8805 return 0; 8826 return 0;
8806 8827
8807 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) | 8828 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8808 MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY; 8829 MAC_MODE_PORT_INT_LPBACK;
8830 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8831 mac_mode |= MAC_MODE_LINK_POLARITY;
8809 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) 8832 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8810 mac_mode |= MAC_MODE_PORT_MODE_MII; 8833 mac_mode |= MAC_MODE_PORT_MODE_MII;
8811 else 8834 else
@@ -8835,8 +8858,7 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8835 tg3_writephy(tp, MII_BMCR, val); 8858 tg3_writephy(tp, MII_BMCR, val);
8836 udelay(40); 8859 udelay(40);
8837 8860
8838 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) | 8861 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
8839 MAC_MODE_LINK_POLARITY;
8840 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { 8862 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8841 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800); 8863 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8842 mac_mode |= MAC_MODE_PORT_MODE_MII; 8864 mac_mode |= MAC_MODE_PORT_MODE_MII;
@@ -8849,8 +8871,11 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8849 udelay(10); 8871 udelay(10);
8850 tw32_f(MAC_RX_MODE, tp->rx_mode); 8872 tw32_f(MAC_RX_MODE, tp->rx_mode);
8851 } 8873 }
8852 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { 8874 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
8853 mac_mode &= ~MAC_MODE_LINK_POLARITY; 8875 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
8876 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8877 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
8878 mac_mode |= MAC_MODE_LINK_POLARITY;
8854 tg3_writephy(tp, MII_TG3_EXT_CTRL, 8879 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8855 MII_TG3_EXT_CTRL_LNK3_LED_MODE); 8880 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8856 } 8881 }