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authorLennert Buytenhek <buytenh@wantstofly.org>2008-04-26 14:48:11 -0400
committerNicolas Pitre <nico@cam.org>2008-05-09 10:39:34 -0400
commitd236f5a5f77183c270223e8816804e7763463282 (patch)
treefccb0ca71b01aa6877a7f98290f7e1e203b4b333
parent28a4acb48586dc21d2d14a75a7aab7be78b7c83b (diff)
[ARM] Orion: use mv643xx_eth driver mbus window handling
Make the Orion 5x platform code use the mbus window handling code that's in the mv643xx_eth driver, instead of programming the GigE block's mbus window registers by hand. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Reviewed-by: Tzachi Perelstein <tzachi@marvell.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Nicolas Pitre <nico@marvell.com>
-rw-r--r--arch/arm/mach-orion5x/addr-map.c47
-rw-r--r--arch/arm/mach-orion5x/common.c8
-rw-r--r--arch/arm/mach-orion5x/common.h1
3 files changed, 7 insertions, 49 deletions
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index 9608503d67f5..186f51ce7c11 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -81,17 +81,6 @@
81#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4)) 81#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4))
82#define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4)) 82#define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4))
83 83
84/*
85 * Gigabit Ethernet Address Decode Windows registers
86 */
87#define ETH_WIN_BASE(win) ORION5X_ETH_REG(0x200 + ((win) * 8))
88#define ETH_WIN_SIZE(win) ORION5X_ETH_REG(0x204 + ((win) * 8))
89#define ETH_WIN_REMAP(win) ORION5X_ETH_REG(0x280 + ((win) * 4))
90#define ETH_WIN_EN ORION5X_ETH_REG(0x290)
91#define ETH_WIN_PROT ORION5X_ETH_REG(0x294)
92#define ETH_MAX_WIN 6
93#define ETH_MAX_REMAP_WIN 4
94
95 84
96struct mbus_dram_target_info orion5x_mbus_dram_info; 85struct mbus_dram_target_info orion5x_mbus_dram_info;
97 86
@@ -202,39 +191,3 @@ void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
202{ 191{
203 setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); 192 setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1);
204} 193}
205
206void __init orion5x_setup_eth_wins(void)
207{
208 int i;
209
210 /*
211 * First, disable and clear windows
212 */
213 for (i = 0; i < ETH_MAX_WIN; i++) {
214 orion5x_write(ETH_WIN_BASE(i), 0);
215 orion5x_write(ETH_WIN_SIZE(i), 0);
216 orion5x_setbits(ETH_WIN_EN, 1 << i);
217 orion5x_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
218 if (i < ETH_MAX_REMAP_WIN)
219 orion5x_write(ETH_WIN_REMAP(i), 0);
220 }
221
222 /*
223 * Setup windows for DDR banks.
224 */
225 for (i = 0; i < DDR_MAX_CS; i++) {
226 u32 base, size;
227 size = orion5x_read(DDR_SIZE_CS(i));
228 base = orion5x_read(DDR_BASE_CS(i));
229 if (size & DDR_BANK_EN) {
230 base = DDR_REG_TO_BASE(base);
231 size = DDR_REG_TO_SIZE(size);
232 orion5x_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
233 orion5x_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
234 (ATTR_DDR_CS(i) << 8) |
235 TARGET_DDR);
236 orion5x_clrbits(ETH_WIN_EN, 1 << i);
237 orion5x_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
238 }
239 }
240}
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 0ecff5a61972..da6e5deab073 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -190,6 +190,10 @@ static struct platform_device orion5x_ehci1 = {
190 * (The Orion and Discovery (MV643xx) families use the same Ethernet driver) 190 * (The Orion and Discovery (MV643xx) families use the same Ethernet driver)
191 ****************************************************************************/ 191 ****************************************************************************/
192 192
193struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
194 .dram = &orion5x_mbus_dram_info,
195};
196
193static struct resource orion5x_eth_shared_resources[] = { 197static struct resource orion5x_eth_shared_resources[] = {
194 { 198 {
195 .start = ORION5X_ETH_PHYS_BASE + 0x2000, 199 .start = ORION5X_ETH_PHYS_BASE + 0x2000,
@@ -201,6 +205,9 @@ static struct resource orion5x_eth_shared_resources[] = {
201static struct platform_device orion5x_eth_shared = { 205static struct platform_device orion5x_eth_shared = {
202 .name = MV643XX_ETH_SHARED_NAME, 206 .name = MV643XX_ETH_SHARED_NAME,
203 .id = 0, 207 .id = 0,
208 .dev = {
209 .platform_data = &orion5x_eth_shared_data,
210 },
204 .num_resources = 1, 211 .num_resources = 1,
205 .resource = orion5x_eth_shared_resources, 212 .resource = orion5x_eth_shared_resources,
206}; 213};
@@ -362,7 +369,6 @@ void __init orion5x_init(void)
362 * Setup Orion address map 369 * Setup Orion address map
363 */ 370 */
364 orion5x_setup_cpu_mbus_bridge(); 371 orion5x_setup_cpu_mbus_bridge();
365 orion5x_setup_eth_wins();
366 372
367 /* 373 /*
368 * Register devices. 374 * Register devices.
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index 14adf8d1a54a..bd0f05de6e18 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -22,7 +22,6 @@ void orion5x_setup_dev0_win(u32 base, u32 size);
22void orion5x_setup_dev1_win(u32 base, u32 size); 22void orion5x_setup_dev1_win(u32 base, u32 size);
23void orion5x_setup_dev2_win(u32 base, u32 size); 23void orion5x_setup_dev2_win(u32 base, u32 size);
24void orion5x_setup_pcie_wa_win(u32 base, u32 size); 24void orion5x_setup_pcie_wa_win(u32 base, u32 size);
25void orion5x_setup_eth_wins(void);
26 25
27/* 26/*
28 * Shared code used internally by other Orion core functions. 27 * Shared code used internally by other Orion core functions.