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authorMark Maule <maule@sgi.com>2005-08-03 17:07:00 -0400
committerTony Luck <tony.luck@intel.com>2005-08-11 18:56:31 -0400
commitc9221da9f2796f082642c3498edb2c8783ad4774 (patch)
tree1603dbace88f4790b6b0138f6e0b43a8958dd656
parent5b53ed1f2ed6c85e2b1c39d97cc112ea32004609 (diff)
[IA64-SGI] sn pci provider for TIOCE (pci
Altix patch to add an SN pci provider for TIOCE, which is SGI's PCI Express implementation. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat
-rw-r--r--arch/ia64/sn/kernel/io_init.c2
-rw-r--r--arch/ia64/sn/pci/Makefile2
-rw-r--r--arch/ia64/sn/pci/tioce_provider.c733
-rw-r--r--include/asm-ia64/sn/pcibus_provider_defs.h3
-rw-r--r--include/asm-ia64/sn/tioce.h740
-rw-r--r--include/asm-ia64/sn/tioce_provider.h66
6 files changed, 1544 insertions, 2 deletions
diff --git a/arch/ia64/sn/kernel/io_init.c b/arch/ia64/sn/kernel/io_init.c
index 829ea7985017..d1fc09b1d518 100644
--- a/arch/ia64/sn/kernel/io_init.c
+++ b/arch/ia64/sn/kernel/io_init.c
@@ -18,6 +18,7 @@
18#include <asm/sn/simulator.h> 18#include <asm/sn/simulator.h>
19#include <asm/sn/sn_sal.h> 19#include <asm/sn/sn_sal.h>
20#include <asm/sn/tioca_provider.h> 20#include <asm/sn/tioca_provider.h>
21#include <asm/sn/tioce_provider.h>
21#include "xtalk/hubdev.h" 22#include "xtalk/hubdev.h"
22#include "xtalk/xwidgetdev.h" 23#include "xtalk/xwidgetdev.h"
23 24
@@ -481,6 +482,7 @@ static int __init sn_pci_init(void)
481 482
482 pcibr_init_provider(); 483 pcibr_init_provider();
483 tioca_init_provider(); 484 tioca_init_provider();
485 tioce_init_provider();
484 486
485 /* 487 /*
486 * This is needed to avoid bounce limit checks in the blk layer 488 * This is needed to avoid bounce limit checks in the blk layer
diff --git a/arch/ia64/sn/pci/Makefile b/arch/ia64/sn/pci/Makefile
index 2f915bce25f9..321576b1b425 100644
--- a/arch/ia64/sn/pci/Makefile
+++ b/arch/ia64/sn/pci/Makefile
@@ -7,4 +7,4 @@
7# 7#
8# Makefile for the sn pci general routines. 8# Makefile for the sn pci general routines.
9 9
10obj-y := pci_dma.o tioca_provider.o pcibr/ 10obj-y := pci_dma.o tioca_provider.o tioce_provider.o pcibr/
diff --git a/arch/ia64/sn/pci/tioce_provider.c b/arch/ia64/sn/pci/tioce_provider.c
new file mode 100644
index 000000000000..d9081369cf96
--- /dev/null
+++ b/arch/ia64/sn/pci/tioce_provider.c
@@ -0,0 +1,733 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003-2005 Silicon Graphics, Inc. All Rights Reserved.
7 */
8
9#include <linux/types.h>
10#include <linux/interrupt.h>
11#include <linux/pci.h>
12#include <asm/sn/sn_sal.h>
13#include <asm/sn/addrs.h>
14#include <asm/sn/pcidev.h>
15#include <asm/sn/pcibus_provider_defs.h>
16#include <asm/sn/tioce_provider.h>
17
18/**
19 * Bus address ranges for the 5 flavors of TIOCE DMA
20 */
21
22#define TIOCE_D64_MIN 0x8000000000000000UL
23#define TIOCE_D64_MAX 0xffffffffffffffffUL
24#define TIOCE_D64_ADDR(a) ((a) >= TIOCE_D64_MIN)
25
26#define TIOCE_D32_MIN 0x0000000080000000UL
27#define TIOCE_D32_MAX 0x00000000ffffffffUL
28#define TIOCE_D32_ADDR(a) ((a) >= TIOCE_D32_MIN && (a) <= TIOCE_D32_MAX)
29
30#define TIOCE_M32_MIN 0x0000000000000000UL
31#define TIOCE_M32_MAX 0x000000007fffffffUL
32#define TIOCE_M32_ADDR(a) ((a) >= TIOCE_M32_MIN && (a) <= TIOCE_M32_MAX)
33
34#define TIOCE_M40_MIN 0x0000004000000000UL
35#define TIOCE_M40_MAX 0x0000007fffffffffUL
36#define TIOCE_M40_ADDR(a) ((a) >= TIOCE_M40_MIN && (a) <= TIOCE_M40_MAX)
37
38#define TIOCE_M40S_MIN 0x0000008000000000UL
39#define TIOCE_M40S_MAX 0x000000ffffffffffUL
40#define TIOCE_M40S_ADDR(a) ((a) >= TIOCE_M40S_MIN && (a) <= TIOCE_M40S_MAX)
41
42/*
43 * ATE manipulation macros.
44 */
45
46#define ATE_PAGESHIFT(ps) (__ffs(ps))
47#define ATE_PAGEMASK(ps) ((ps)-1)
48
49#define ATE_PAGE(x, ps) ((x) >> ATE_PAGESHIFT(ps))
50#define ATE_NPAGES(start, len, pagesize) \
51 (ATE_PAGE((start)+(len)-1, pagesize) - ATE_PAGE(start, pagesize) + 1)
52
53#define ATE_VALID(ate) ((ate) & (1UL << 63))
54#define ATE_MAKE(addr, ps) (((addr) & ~ATE_PAGEMASK(ps)) | (1UL << 63))
55
56/*
57 * Flavors of ate-based mapping supported by tioce_alloc_map()
58 */
59
60#define TIOCE_ATE_M32 1
61#define TIOCE_ATE_M40 2
62#define TIOCE_ATE_M40S 3
63
64#define KB(x) ((x) << 10)
65#define MB(x) ((x) << 20)
66#define GB(x) ((x) << 30)
67
68/**
69 * tioce_dma_d64 - create a DMA mapping using 64-bit direct mode
70 * @ct_addr: system coretalk address
71 *
72 * Map @ct_addr into 64-bit CE bus space. No device context is necessary
73 * and no CE mapping are consumed.
74 *
75 * Bits 53:0 come from the coretalk address. The remaining bits are set as
76 * follows:
77 *
78 * 63 - must be 1 to indicate d64 mode to CE hardware
79 * 62 - barrier bit ... controlled with tioce_dma_barrier()
80 * 61 - 0 since this is not an MSI transaction
81 * 60:54 - reserved, MBZ
82 */
83static uint64_t
84tioce_dma_d64(unsigned long ct_addr)
85{
86 uint64_t bus_addr;
87
88 bus_addr = ct_addr | (1UL << 63);
89
90 return bus_addr;
91}
92
93/**
94 * pcidev_to_tioce - return misc ce related pointers given a pci_dev
95 * @pci_dev: pci device context
96 * @base: ptr to store struct tioce_mmr * for the CE holding this device
97 * @kernel: ptr to store struct tioce_kernel * for the CE holding this device
98 * @port: ptr to store the CE port number that this device is on
99 *
100 * Return pointers to various CE-related structures for the CE upstream of
101 * @pci_dev.
102 */
103static inline void
104pcidev_to_tioce(struct pci_dev *pdev, struct tioce **base,
105 struct tioce_kernel **kernel, int *port)
106{
107 struct pcidev_info *pcidev_info;
108 struct tioce_common *ce_common;
109 struct tioce_kernel *ce_kernel;
110
111 pcidev_info = SN_PCIDEV_INFO(pdev);
112 ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
113 ce_kernel = (struct tioce_kernel *)ce_common->ce_kernel_private;
114
115 if (base)
116 *base = (struct tioce *)ce_common->ce_pcibus.bs_base;
117 if (kernel)
118 *kernel = ce_kernel;
119
120 /*
121 * we use port as a zero-based value internally, even though the
122 * documentation is 1-based.
123 */
124 if (port)
125 *port =
126 (pdev->bus->number < ce_kernel->ce_port1_secondary) ? 0 : 1;
127}
128
129/**
130 * tioce_alloc_map - Given a coretalk address, map it to pcie bus address
131 * space using one of the various ATE-based address modes.
132 * @ce_kern: tioce context
133 * @type: map mode to use
134 * @port: 0-based port that the requesting device is downstream of
135 * @ct_addr: the coretalk address to map
136 * @len: number of bytes to map
137 *
138 * Given the addressing type, set up various paramaters that define the
139 * ATE pool to use. Search for a contiguous block of entries to cover the
140 * length, and if enough resources exist, fill in the ATE's and construct a
141 * tioce_dmamap struct to track the mapping.
142 */
143static uint64_t
144tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port,
145 uint64_t ct_addr, int len)
146{
147 int i;
148 int j;
149 int first;
150 int last;
151 int entries;
152 int nates;
153 int pagesize;
154 uint64_t *ate_shadow;
155 uint64_t *ate_reg;
156 uint64_t addr;
157 struct tioce *ce_mmr;
158 uint64_t bus_base;
159 struct tioce_dmamap *map;
160
161 ce_mmr = (struct tioce *)ce_kern->ce_common->ce_pcibus.bs_base;
162
163 switch (type) {
164 case TIOCE_ATE_M32:
165 /*
166 * The first 64 entries of the ate3240 pool are dedicated to
167 * super-page (TIOCE_ATE_M40S) mode.
168 */
169 first = 64;
170 entries = TIOCE_NUM_M3240_ATES - 64;
171 ate_shadow = ce_kern->ce_ate3240_shadow;
172 ate_reg = ce_mmr->ce_ure_ate3240;
173 pagesize = ce_kern->ce_ate3240_pagesize;
174 bus_base = TIOCE_M32_MIN;
175 break;
176 case TIOCE_ATE_M40:
177 first = 0;
178 entries = TIOCE_NUM_M40_ATES;
179 ate_shadow = ce_kern->ce_ate40_shadow;
180 ate_reg = ce_mmr->ce_ure_ate40;
181 pagesize = MB(64);
182 bus_base = TIOCE_M40_MIN;
183 break;
184 case TIOCE_ATE_M40S:
185 /*
186 * ate3240 entries 0-31 are dedicated to port1 super-page
187 * mappings. ate3240 entries 32-63 are dedicated to port2.
188 */
189 first = port * 32;
190 entries = 32;
191 ate_shadow = ce_kern->ce_ate3240_shadow;
192 ate_reg = ce_mmr->ce_ure_ate3240;
193 pagesize = GB(16);
194 bus_base = TIOCE_M40S_MIN;
195 break;
196 default:
197 return 0;
198 }
199
200 nates = ATE_NPAGES(ct_addr, len, pagesize);
201 if (nates > entries)
202 return 0;
203
204 last = first + entries - nates;
205 for (i = first; i <= last; i++) {
206 if (ATE_VALID(ate_shadow[i]))
207 continue;
208
209 for (j = i; j < i + nates; j++)
210 if (ATE_VALID(ate_shadow[j]))
211 break;
212
213 if (j >= i + nates)
214 break;
215 }
216
217 if (i > last)
218 return 0;
219
220 map = kcalloc(1, sizeof(struct tioce_dmamap), GFP_ATOMIC);
221 if (!map)
222 return 0;
223
224 addr = ct_addr;
225 for (j = 0; j < nates; j++) {
226 uint64_t ate;
227
228 ate = ATE_MAKE(addr, pagesize);
229 ate_shadow[i + j] = ate;
230 ate_reg[i + j] = ate;
231 addr += pagesize;
232 }
233
234 map->refcnt = 1;
235 map->nbytes = nates * pagesize;
236 map->ct_start = ct_addr & ~ATE_PAGEMASK(pagesize);
237 map->pci_start = bus_base + (i * pagesize);
238 map->ate_hw = &ate_reg[i];
239 map->ate_shadow = &ate_shadow[i];
240 map->ate_count = nates;
241
242 list_add(&map->ce_dmamap_list, &ce_kern->ce_dmamap_list);
243
244 return (map->pci_start + (ct_addr - map->ct_start));
245}
246
247/**
248 * tioce_dma_d32 - create a DMA mapping using 32-bit direct mode
249 * @pdev: linux pci_dev representing the function
250 * @paddr: system physical address
251 *
252 * Map @paddr into 32-bit bus space of the CE associated with @pcidev_info.
253 */
254static uint64_t
255tioce_dma_d32(struct pci_dev *pdev, uint64_t ct_addr)
256{
257 int dma_ok;
258 int port;
259 struct tioce *ce_mmr;
260 struct tioce_kernel *ce_kern;
261 uint64_t ct_upper;
262 uint64_t ct_lower;
263 dma_addr_t bus_addr;
264
265 ct_upper = ct_addr & ~0x3fffffffUL;
266 ct_lower = ct_addr & 0x3fffffffUL;
267
268 pcidev_to_tioce(pdev, &ce_mmr, &ce_kern, &port);
269
270 if (ce_kern->ce_port[port].dirmap_refcnt == 0) {
271 volatile uint64_t tmp;
272
273 ce_kern->ce_port[port].dirmap_shadow = ct_upper;
274 ce_mmr->ce_ure_dir_map[port] = ct_upper;
275 tmp = ce_mmr->ce_ure_dir_map[port];
276 dma_ok = 1;
277 } else
278 dma_ok = (ce_kern->ce_port[port].dirmap_shadow == ct_upper);
279
280 if (dma_ok) {
281 ce_kern->ce_port[port].dirmap_refcnt++;
282 bus_addr = TIOCE_D32_MIN + ct_lower;
283 } else
284 bus_addr = 0;
285
286 return bus_addr;
287}
288
289/**
290 * tioce_dma_barrier - swizzle a TIOCE bus address to include or exclude
291 * the barrier bit.
292 * @bus_addr: bus address to swizzle
293 *
294 * Given a TIOCE bus address, set the appropriate bit to indicate barrier
295 * attributes.
296 */
297static uint64_t
298tioce_dma_barrier(uint64_t bus_addr, int on)
299{
300 uint64_t barrier_bit;
301
302 /* barrier not supported in M40/M40S mode */
303 if (TIOCE_M40_ADDR(bus_addr) || TIOCE_M40S_ADDR(bus_addr))
304 return bus_addr;
305
306 if (TIOCE_D64_ADDR(bus_addr))
307 barrier_bit = (1UL << 62);
308 else /* must be m32 or d32 */
309 barrier_bit = (1UL << 30);
310
311 return (on) ? (bus_addr | barrier_bit) : (bus_addr & ~barrier_bit);
312}
313
314/**
315 * tioce_dma_unmap - release CE mapping resources
316 * @pdev: linux pci_dev representing the function
317 * @bus_addr: bus address returned by an earlier tioce_dma_map
318 * @dir: mapping direction (unused)
319 *
320 * Locate mapping resources associated with @bus_addr and release them.
321 * For mappings created using the direct modes there are no resources
322 * to release.
323 */
324void
325tioce_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
326{
327 int i;
328 int port;
329 struct tioce_kernel *ce_kern;
330 struct tioce *ce_mmr;
331 unsigned long flags;
332
333 bus_addr = tioce_dma_barrier(bus_addr, 0);
334 pcidev_to_tioce(pdev, &ce_mmr, &ce_kern, &port);
335
336 /* nothing to do for D64 */
337
338 if (TIOCE_D64_ADDR(bus_addr))
339 return;
340
341 spin_lock_irqsave(&ce_kern->ce_lock, flags);
342
343 if (TIOCE_D32_ADDR(bus_addr)) {
344 if (--ce_kern->ce_port[port].dirmap_refcnt == 0) {
345 ce_kern->ce_port[port].dirmap_shadow = 0;
346 ce_mmr->ce_ure_dir_map[port] = 0;
347 }
348 } else {
349 struct tioce_dmamap *map;
350
351 list_for_each_entry(map, &ce_kern->ce_dmamap_list,
352 ce_dmamap_list) {
353 uint64_t last;
354
355 last = map->pci_start + map->nbytes - 1;
356 if (bus_addr >= map->pci_start && bus_addr <= last)
357 break;
358 }
359
360 if (&map->ce_dmamap_list == &ce_kern->ce_dmamap_list) {
361 printk(KERN_WARNING
362 "%s: %s - no map found for bus_addr 0x%lx\n",
363 __FUNCTION__, pci_name(pdev), bus_addr);
364 } else if (--map->refcnt == 0) {
365 for (i = 0; i < map->ate_count; i++) {
366 map->ate_shadow[i] = 0;
367 map->ate_hw[i] = 0;
368 }
369
370 list_del(&map->ce_dmamap_list);
371 kfree(map);
372 }
373 }
374
375 spin_unlock_irqrestore(&ce_kern->ce_lock, flags);
376}
377
378/**
379 * tioce_do_dma_map - map pages for PCI DMA
380 * @pdev: linux pci_dev representing the function
381 * @paddr: host physical address to map
382 * @byte_count: bytes to map
383 *
384 * This is the main wrapper for mapping host physical pages to CE PCI space.
385 * The mapping mode used is based on the device's dma_mask.
386 */
387static uint64_t
388tioce_do_dma_map(struct pci_dev *pdev, uint64_t paddr, size_t byte_count,
389 int barrier)
390{
391 unsigned long flags;
392 uint64_t ct_addr;
393 uint64_t mapaddr = 0;
394 struct tioce_kernel *ce_kern;
395 struct tioce_dmamap *map;
396 int port;
397 uint64_t dma_mask;
398
399 dma_mask = (barrier) ? pdev->dev.coherent_dma_mask : pdev->dma_mask;
400
401 /* cards must be able to address at least 31 bits */
402 if (dma_mask < 0x7fffffffUL)
403 return 0;
404
405 ct_addr = PHYS_TO_TIODMA(paddr);
406
407 /*
408 * If the device can generate 64 bit addresses, create a D64 map.
409 * Since this should never fail, bypass the rest of the checks.
410 */
411 if (dma_mask == ~0UL) {
412 mapaddr = tioce_dma_d64(ct_addr);
413 goto dma_map_done;
414 }
415
416 pcidev_to_tioce(pdev, NULL, &ce_kern, &port);
417
418 spin_lock_irqsave(&ce_kern->ce_lock, flags);
419
420 /*
421 * D64 didn't work ... See if we have an existing map that covers
422 * this address range. Must account for devices dma_mask here since
423 * an existing map might have been done in a mode using more pci
424 * address bits than this device can support.
425 */
426 list_for_each_entry(map, &ce_kern->ce_dmamap_list, ce_dmamap_list) {
427 uint64_t last;
428
429 last = map->ct_start + map->nbytes - 1;
430 if (ct_addr >= map->ct_start &&
431 ct_addr + byte_count - 1 <= last &&
432 map->pci_start <= dma_mask) {
433 map->refcnt++;
434 mapaddr = map->pci_start + (ct_addr - map->ct_start);
435 break;
436 }
437 }
438
439 /*
440 * If we don't have a map yet, and the card can generate 40
441 * bit addresses, try the M40/M40S modes. Note these modes do not
442 * support a barrier bit, so if we need a consistent map these
443 * won't work.
444 */
445 if (!mapaddr && !barrier && dma_mask >= 0xffffffffffUL) {
446 /*
447 * We have two options for 40-bit mappings: 16GB "super" ATE's
448 * and 64MB "regular" ATE's. We'll try both if needed for a
449 * given mapping but which one we try first depends on the
450 * size. For requests >64MB, prefer to use a super page with
451 * regular as the fallback. Otherwise, try in the reverse order.
452 */
453
454 if (byte_count > MB(64)) {
455 mapaddr = tioce_alloc_map(ce_kern, TIOCE_ATE_M40S,
456 port, ct_addr, byte_count);
457 if (!mapaddr)
458 mapaddr =
459 tioce_alloc_map(ce_kern, TIOCE_ATE_M40, -1,
460 ct_addr, byte_count);
461 } else {
462 mapaddr = tioce_alloc_map(ce_kern, TIOCE_ATE_M40, -1,
463 ct_addr, byte_count);
464 if (!mapaddr)
465 mapaddr =
466 tioce_alloc_map(ce_kern, TIOCE_ATE_M40S,
467 port, ct_addr, byte_count);
468 }
469 }
470
471 /*
472 * 32-bit direct is the next mode to try
473 */
474 if (!mapaddr && dma_mask >= 0xffffffffUL)
475 mapaddr = tioce_dma_d32(pdev, ct_addr);
476
477 /*
478 * Last resort, try 32-bit ATE-based map.
479 */
480 if (!mapaddr)
481 mapaddr =
482 tioce_alloc_map(ce_kern, TIOCE_ATE_M32, -1, ct_addr,
483 byte_count);
484
485 spin_unlock_irqrestore(&ce_kern->ce_lock, flags);
486
487dma_map_done:
488 if (mapaddr & barrier)
489 mapaddr = tioce_dma_barrier(mapaddr, 1);
490
491 return mapaddr;
492}
493
494/**
495 * tioce_dma - standard pci dma map interface
496 * @pdev: pci device requesting the map
497 * @paddr: system physical address to map into pci space
498 * @byte_count: # bytes to map
499 *
500 * Simply call tioce_do_dma_map() to create a map with the barrier bit clear
501 * in the address.
502 */
503static uint64_t
504tioce_dma(struct pci_dev *pdev, uint64_t paddr, size_t byte_count)
505{
506 return tioce_do_dma_map(pdev, paddr, byte_count, 0);
507}
508
509/**
510 * tioce_dma_consistent - consistent pci dma map interface
511 * @pdev: pci device requesting the map
512 * @paddr: system physical address to map into pci space
513 * @byte_count: # bytes to map
514 *
515 * Simply call tioce_do_dma_map() to create a map with the barrier bit set
516 * in the address.
517 */ static uint64_t
518tioce_dma_consistent(struct pci_dev *pdev, uint64_t paddr, size_t byte_count)
519{
520 return tioce_do_dma_map(pdev, paddr, byte_count, 1);
521}
522
523/**
524 * tioce_error_intr_handler - SGI TIO CE error interrupt handler
525 * @irq: unused
526 * @arg: pointer to tioce_common struct for the given CE
527 * @pt: unused
528 *
529 * Handle a CE error interrupt. Simply a wrapper around a SAL call which
530 * defers processing to the SGI prom.
531 */ static irqreturn_t
532tioce_error_intr_handler(int irq, void *arg, struct pt_regs *pt)
533{
534 struct tioce_common *soft = arg;
535 struct ia64_sal_retval ret_stuff;
536 ret_stuff.status = 0;
537 ret_stuff.v0 = 0;
538
539 SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_ERROR_INTERRUPT,
540 soft->ce_pcibus.bs_persist_segment,
541 soft->ce_pcibus.bs_persist_busnum, 0, 0, 0, 0, 0);
542
543 return IRQ_HANDLED;
544}
545
546/**
547 * tioce_kern_init - init kernel structures related to a given TIOCE
548 * @tioce_common: ptr to a cached tioce_common struct that originated in prom
549 */ static struct tioce_kernel *
550tioce_kern_init(struct tioce_common *tioce_common)
551{
552 int i;
553 uint32_t tmp;
554 struct tioce *tioce_mmr;
555 struct tioce_kernel *tioce_kern;
556
557 tioce_kern = kcalloc(1, sizeof(struct tioce_kernel), GFP_KERNEL);
558 if (!tioce_kern) {
559 return NULL;
560 }
561
562 tioce_kern->ce_common = tioce_common;
563 spin_lock_init(&tioce_kern->ce_lock);
564 INIT_LIST_HEAD(&tioce_kern->ce_dmamap_list);
565 tioce_common->ce_kernel_private = (uint64_t) tioce_kern;
566
567 /*
568 * Determine the secondary bus number of the port2 logical PPB.
569 * This is used to decide whether a given pci device resides on
570 * port1 or port2. Note: We don't have enough plumbing set up
571 * here to use pci_read_config_xxx() so use the raw_pci_ops vector.
572 */
573
574 raw_pci_ops->read(tioce_common->ce_pcibus.bs_persist_segment,
575 tioce_common->ce_pcibus.bs_persist_busnum,
576 PCI_DEVFN(2, 0), PCI_SECONDARY_BUS, 1, &tmp);
577 tioce_kern->ce_port1_secondary = (uint8_t) tmp;
578
579 /*
580 * Set PMU pagesize to the largest size available, and zero out
581 * the ate's.
582 */
583
584 tioce_mmr = (struct tioce *)tioce_common->ce_pcibus.bs_base;
585 tioce_mmr->ce_ure_page_map &= ~CE_URE_PAGESIZE_MASK;
586 tioce_mmr->ce_ure_page_map |= CE_URE_256K_PAGESIZE;
587 tioce_kern->ce_ate3240_pagesize = KB(256);
588
589 for (i = 0; i < TIOCE_NUM_M40_ATES; i++) {
590 tioce_kern->ce_ate40_shadow[i] = 0;
591 tioce_mmr->ce_ure_ate40[i] = 0;
592 }
593
594 for (i = 0; i < TIOCE_NUM_M3240_ATES; i++) {
595 tioce_kern->ce_ate3240_shadow[i] = 0;
596 tioce_mmr->ce_ure_ate3240[i] = 0;
597 }
598
599 return tioce_kern;
600}
601
602/**
603 * tioce_force_interrupt - implement altix force_interrupt() backend for CE
604 * @sn_irq_info: sn asic irq that we need an interrupt generated for
605 *
606 * Given an sn_irq_info struct, set the proper bit in ce_adm_force_int to
607 * force a secondary interrupt to be generated. This is to work around an
608 * asic issue where there is a small window of opportunity for a legacy device
609 * interrupt to be lost.
610 */
611static void
612tioce_force_interrupt(struct sn_irq_info *sn_irq_info)
613{
614 struct pcidev_info *pcidev_info;
615 struct tioce_common *ce_common;
616 struct tioce *ce_mmr;
617 uint64_t force_int_val;
618
619 if (!sn_irq_info->irq_bridge)
620 return;
621
622 if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_TIOCE)
623 return;
624
625 pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
626 if (!pcidev_info)
627 return;
628
629 ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
630 ce_mmr = (struct tioce *)ce_common->ce_pcibus.bs_base;
631
632 /*
633 * irq_int_bit is originally set up by prom, and holds the interrupt
634 * bit shift (not mask) as defined by the bit definitions in the
635 * ce_adm_int mmr. These shifts are not the same for the
636 * ce_adm_force_int register, so do an explicit mapping here to make
637 * things clearer.
638 */
639
640 switch (sn_irq_info->irq_int_bit) {
641 case CE_ADM_INT_PCIE_PORT1_DEV_A_SHFT:
642 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_A_SHFT;
643 break;
644 case CE_ADM_INT_PCIE_PORT1_DEV_B_SHFT:
645 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_B_SHFT;
646 break;
647 case CE_ADM_INT_PCIE_PORT1_DEV_C_SHFT:
648 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_C_SHFT;
649 break;
650 case CE_ADM_INT_PCIE_PORT1_DEV_D_SHFT:
651 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_D_SHFT;
652 break;
653 case CE_ADM_INT_PCIE_PORT2_DEV_A_SHFT:
654 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_A_SHFT;
655 break;
656 case CE_ADM_INT_PCIE_PORT2_DEV_B_SHFT:
657 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_B_SHFT;
658 break;
659 case CE_ADM_INT_PCIE_PORT2_DEV_C_SHFT:
660 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_C_SHFT;
661 break;
662 case CE_ADM_INT_PCIE_PORT2_DEV_D_SHFT:
663 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_D_SHFT;
664 break;
665 default:
666 return;
667 }
668 ce_mmr->ce_adm_force_int = force_int_val;
669}
670
671/**
672 * tioce_bus_fixup - perform final PCI fixup for a TIO CE bus
673 * @prom_bussoft: Common prom/kernel struct representing the bus
674 *
675 * Replicates the tioce_common pointed to by @prom_bussoft in kernel
676 * space. Allocates and initializes a kernel-only area for a given CE,
677 * and sets up an irq for handling CE error interrupts.
678 *
679 * On successful setup, returns the kernel version of tioce_common back to
680 * the caller.
681 */
682static void *
683tioce_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller)
684{
685 struct tioce_common *tioce_common;
686
687 /*
688 * Allocate kernel bus soft and copy from prom.
689 */
690
691 tioce_common = kcalloc(1, sizeof(struct tioce_common), GFP_KERNEL);
692 if (!tioce_common)
693 return NULL;
694
695 memcpy(tioce_common, prom_bussoft, sizeof(struct tioce_common));
696 tioce_common->ce_pcibus.bs_base |= __IA64_UNCACHED_OFFSET;
697
698 if (tioce_kern_init(tioce_common) == NULL) {
699 kfree(tioce_common);
700 return NULL;
701 }
702
703 if (request_irq(SGI_PCIASIC_ERROR,
704 tioce_error_intr_handler,
705 SA_SHIRQ, "TIOCE error", (void *)tioce_common))
706 printk(KERN_WARNING
707 "%s: Unable to get irq %d. "
708 "Error interrupts won't be routed for "
709 "TIOCE bus %04x:%02x\n",
710 __FUNCTION__, SGI_PCIASIC_ERROR,
711 tioce_common->ce_pcibus.bs_persist_segment,
712 tioce_common->ce_pcibus.bs_persist_busnum);
713
714 return tioce_common;
715}
716
717static struct sn_pcibus_provider tioce_pci_interfaces = {
718 .dma_map = tioce_dma,
719 .dma_map_consistent = tioce_dma_consistent,
720 .dma_unmap = tioce_dma_unmap,
721 .bus_fixup = tioce_bus_fixup,
722 .force_interrupt = tioce_force_interrupt
723};
724
725/**
726 * tioce_init_provider - init SN PCI provider ops for TIO CE
727 */
728int
729tioce_init_provider(void)
730{
731 sn_pci_provider[PCIIO_ASIC_TYPE_TIOCE] = &tioce_pci_interfaces;
732 return 0;
733}
diff --git a/include/asm-ia64/sn/pcibus_provider_defs.h b/include/asm-ia64/sn/pcibus_provider_defs.h
index 5c3ba5708e82..5a92f5149a94 100644
--- a/include/asm-ia64/sn/pcibus_provider_defs.h
+++ b/include/asm-ia64/sn/pcibus_provider_defs.h
@@ -18,8 +18,9 @@
18#define PCIIO_ASIC_TYPE_PIC 2 18#define PCIIO_ASIC_TYPE_PIC 2
19#define PCIIO_ASIC_TYPE_TIOCP 3 19#define PCIIO_ASIC_TYPE_TIOCP 3
20#define PCIIO_ASIC_TYPE_TIOCA 4 20#define PCIIO_ASIC_TYPE_TIOCA 4
21#define PCIIO_ASIC_TYPE_TIOCE 5
21 22
22#define PCIIO_ASIC_MAX_TYPES 5 23#define PCIIO_ASIC_MAX_TYPES 6
23 24
24/* 25/*
25 * Common pciio bus provider data. There should be one of these as the 26 * Common pciio bus provider data. There should be one of these as the
diff --git a/include/asm-ia64/sn/tioce.h b/include/asm-ia64/sn/tioce.h
new file mode 100644
index 000000000000..22879853e46c
--- /dev/null
+++ b/include/asm-ia64/sn/tioce.h
@@ -0,0 +1,740 @@
1/**************************************************************************
2 * *
3 * Unpublished copyright (c) 2005, Silicon Graphics, Inc. *
4 * THIS IS UNPUBLISHED CONFIDENTIAL AND PROPRIETARY SOURCE CODE OF SGI. *
5 * *
6 * The copyright notice above does not evidence any actual or intended *
7 * publication or disclosure of this source code, which includes *
8 * information that is confidential and/or proprietary, and is a trade *
9 * secret, of Silicon Graphics, Inc. ANY REPRODUCTION, MODIFICATION, *
10 * DISTRIBUTION, PUBLIC PERFORMANCE, OR PUBLIC DISPLAY OF OR THROUGH *
11 * USE OF THIS SOURCE CODE WITHOUT THE EXPRESS WRITTEN CONSENT OF *
12 * SILICON GRAPHICS, INC. IS STRICTLY PROHIBITED, AND IN VIOLATION OF *
13 * APPLICABLE LAWS AND INTERNATIONAL TREATIES. THE RECEIPT OR *
14 * POSSESSION OF THIS SOURCE CODE AND/OR RELATED INFORMATION DOES NOT *
15 * CONVEY OR IMPLY ANY RIGHTS TO REPRODUCE, DISCLOSE OR DISTRIBUTE ITS *
16 * CONTENTS, OR TO MANUFACTURE, USE, OR SELL ANYTHING THAT IT MAY *
17 * DESCRIBE, IN WHOLE OR IN PART. *
18 * *
19 **************************************************************************/
20
21#ifndef __ASM_IA64_SN_TIOCE_H__
22#define __ASM_IA64_SN_TIOCE_H__
23
24/* CE ASIC part & mfgr information */
25#define TIOCE_PART_NUM 0xCE00
26#define TIOCE_MFGR_NUM 0x36
27#define TIOCE_REV_A 0x1
28
29/* CE Virtual PPB Vendor/Device IDs */
30#define CE_VIRT_PPB_VENDOR_ID 0x10a9
31#define CE_VIRT_PPB_DEVICE_ID 0x4002
32
33/* CE Host Bridge Vendor/Device IDs */
34#define CE_HOST_BRIDGE_VENDOR_ID 0x10a9
35#define CE_HOST_BRIDGE_DEVICE_ID 0x4003
36
37
38#define TIOCE_NUM_M40_ATES 4096
39#define TIOCE_NUM_M3240_ATES 2048
40#define TIOCE_NUM_PORTS 2
41
42/*
43 * Register layout for TIOCE. MMR offsets are shown at the far right of the
44 * structure definition.
45 */
46typedef volatile struct tioce {
47 /*
48 * ADMIN : Administration Registers
49 */
50 uint64_t ce_adm_id; /* 0x000000 */
51 uint64_t ce_pad_000008; /* 0x000008 */
52 uint64_t ce_adm_dyn_credit_status; /* 0x000010 */
53 uint64_t ce_adm_last_credit_status; /* 0x000018 */
54 uint64_t ce_adm_credit_limit; /* 0x000020 */
55 uint64_t ce_adm_force_credit; /* 0x000028 */
56 uint64_t ce_adm_control; /* 0x000030 */
57 uint64_t ce_adm_mmr_chn_timeout; /* 0x000038 */
58 uint64_t ce_adm_ssp_ure_timeout; /* 0x000040 */
59 uint64_t ce_adm_ssp_dre_timeout; /* 0x000048 */
60 uint64_t ce_adm_ssp_debug_sel; /* 0x000050 */
61 uint64_t ce_adm_int_status; /* 0x000058 */
62 uint64_t ce_adm_int_status_alias; /* 0x000060 */
63 uint64_t ce_adm_int_mask; /* 0x000068 */
64 uint64_t ce_adm_int_pending; /* 0x000070 */
65 uint64_t ce_adm_force_int; /* 0x000078 */
66 uint64_t ce_adm_ure_ups_buf_barrier_flush; /* 0x000080 */
67 uint64_t ce_adm_int_dest[15]; /* 0x000088 -- 0x0000F8 */
68 uint64_t ce_adm_error_summary; /* 0x000100 */
69 uint64_t ce_adm_error_summary_alias; /* 0x000108 */
70 uint64_t ce_adm_error_mask; /* 0x000110 */
71 uint64_t ce_adm_first_error; /* 0x000118 */
72 uint64_t ce_adm_error_overflow; /* 0x000120 */
73 uint64_t ce_adm_error_overflow_alias; /* 0x000128 */
74 uint64_t ce_pad_000130[2]; /* 0x000130 -- 0x000138 */
75 uint64_t ce_adm_tnum_error; /* 0x000140 */
76 uint64_t ce_adm_mmr_err_detail; /* 0x000148 */
77 uint64_t ce_adm_msg_sram_perr_detail; /* 0x000150 */
78 uint64_t ce_adm_bap_sram_perr_detail; /* 0x000158 */
79 uint64_t ce_adm_ce_sram_perr_detail; /* 0x000160 */
80 uint64_t ce_adm_ce_credit_oflow_detail; /* 0x000168 */
81 uint64_t ce_adm_tx_link_idle_max_timer; /* 0x000170 */
82 uint64_t ce_adm_pcie_debug_sel; /* 0x000178 */
83 uint64_t ce_pad_000180[16]; /* 0x000180 -- 0x0001F8 */
84
85 uint64_t ce_adm_pcie_debug_sel_top; /* 0x000200 */
86 uint64_t ce_adm_pcie_debug_lat_sel_lo_top; /* 0x000208 */
87 uint64_t ce_adm_pcie_debug_lat_sel_hi_top; /* 0x000210 */
88 uint64_t ce_adm_pcie_debug_trig_sel_top; /* 0x000218 */
89 uint64_t ce_adm_pcie_debug_trig_lat_sel_lo_top; /* 0x000220 */
90 uint64_t ce_adm_pcie_debug_trig_lat_sel_hi_top; /* 0x000228 */
91 uint64_t ce_adm_pcie_trig_compare_top; /* 0x000230 */
92 uint64_t ce_adm_pcie_trig_compare_en_top; /* 0x000238 */
93 uint64_t ce_adm_ssp_debug_sel_top; /* 0x000240 */
94 uint64_t ce_adm_ssp_debug_lat_sel_lo_top; /* 0x000248 */
95 uint64_t ce_adm_ssp_debug_lat_sel_hi_top; /* 0x000250 */
96 uint64_t ce_adm_ssp_debug_trig_sel_top; /* 0x000258 */
97 uint64_t ce_adm_ssp_debug_trig_lat_sel_lo_top; /* 0x000260 */
98 uint64_t ce_adm_ssp_debug_trig_lat_sel_hi_top; /* 0x000268 */
99 uint64_t ce_adm_ssp_trig_compare_top; /* 0x000270 */
100 uint64_t ce_adm_ssp_trig_compare_en_top; /* 0x000278 */
101 uint64_t ce_pad_000280[48]; /* 0x000280 -- 0x0003F8 */
102
103 uint64_t ce_adm_bap_ctrl; /* 0x000400 */
104 uint64_t ce_pad_000408[127]; /* 0x000408 -- 0x0007F8 */
105
106 uint64_t ce_msg_buf_data63_0[35]; /* 0x000800 -- 0x000918 */
107 uint64_t ce_pad_000920[29]; /* 0x000920 -- 0x0009F8 */
108
109 uint64_t ce_msg_buf_data127_64[35]; /* 0x000A00 -- 0x000B18 */
110 uint64_t ce_pad_000B20[29]; /* 0x000B20 -- 0x000BF8 */
111
112 uint64_t ce_msg_buf_parity[35]; /* 0x000C00 -- 0x000D18 */
113 uint64_t ce_pad_000D20[29]; /* 0x000D20 -- 0x000DF8 */
114
115 uint64_t ce_pad_000E00[576]; /* 0x000E00 -- 0x001FF8 */
116
117 /*
118 * LSI : LSI's PCI Express Link Registers (Link#1 and Link#2)
119 * Link#1 MMRs at start at 0x002000, Link#2 MMRs at 0x003000
120 * NOTE: the comment offsets at far right: let 'z' = {2 or 3}
121 */
122 #define ce_lsi(link_num) ce_lsi[link_num-1]
123 struct ce_lsi_reg {
124 uint64_t ce_lsi_lpu_id; /* 0x00z000 */
125 uint64_t ce_lsi_rst; /* 0x00z008 */
126 uint64_t ce_lsi_dbg_stat; /* 0x00z010 */
127 uint64_t ce_lsi_dbg_cfg; /* 0x00z018 */
128 uint64_t ce_lsi_ltssm_ctrl; /* 0x00z020 */
129 uint64_t ce_lsi_lk_stat; /* 0x00z028 */
130 uint64_t ce_pad_00z030[2]; /* 0x00z030 -- 0x00z038 */
131 uint64_t ce_lsi_int_and_stat; /* 0x00z040 */
132 uint64_t ce_lsi_int_mask; /* 0x00z048 */
133 uint64_t ce_pad_00z050[22]; /* 0x00z050 -- 0x00z0F8 */
134 uint64_t ce_lsi_lk_perf_cnt_sel; /* 0x00z100 */
135 uint64_t ce_pad_00z108; /* 0x00z108 */
136 uint64_t ce_lsi_lk_perf_cnt_ctrl; /* 0x00z110 */
137 uint64_t ce_pad_00z118; /* 0x00z118 */
138 uint64_t ce_lsi_lk_perf_cnt1; /* 0x00z120 */
139 uint64_t ce_lsi_lk_perf_cnt1_test; /* 0x00z128 */
140 uint64_t ce_lsi_lk_perf_cnt2; /* 0x00z130 */
141 uint64_t ce_lsi_lk_perf_cnt2_test; /* 0x00z138 */
142 uint64_t ce_pad_00z140[24]; /* 0x00z140 -- 0x00z1F8 */
143 uint64_t ce_lsi_lk_lyr_cfg; /* 0x00z200 */
144 uint64_t ce_lsi_lk_lyr_status; /* 0x00z208 */
145 uint64_t ce_lsi_lk_lyr_int_stat; /* 0x00z210 */
146 uint64_t ce_lsi_lk_ly_int_stat_test; /* 0x00z218 */
147 uint64_t ce_lsi_lk_ly_int_stat_mask; /* 0x00z220 */
148 uint64_t ce_pad_00z228[3]; /* 0x00z228 -- 0x00z238 */
149 uint64_t ce_lsi_fc_upd_ctl; /* 0x00z240 */
150 uint64_t ce_pad_00z248[3]; /* 0x00z248 -- 0x00z258 */
151 uint64_t ce_lsi_flw_ctl_upd_to_timer; /* 0x00z260 */
152 uint64_t ce_lsi_flw_ctl_upd_timer0; /* 0x00z268 */
153 uint64_t ce_lsi_flw_ctl_upd_timer1; /* 0x00z270 */
154 uint64_t ce_pad_00z278[49]; /* 0x00z278 -- 0x00z3F8 */
155 uint64_t ce_lsi_freq_nak_lat_thrsh; /* 0x00z400 */
156 uint64_t ce_lsi_ack_nak_lat_tmr; /* 0x00z408 */
157 uint64_t ce_lsi_rply_tmr_thr; /* 0x00z410 */
158 uint64_t ce_lsi_rply_tmr; /* 0x00z418 */
159 uint64_t ce_lsi_rply_num_stat; /* 0x00z420 */
160 uint64_t ce_lsi_rty_buf_max_addr; /* 0x00z428 */
161 uint64_t ce_lsi_rty_fifo_ptr; /* 0x00z430 */
162 uint64_t ce_lsi_rty_fifo_rd_wr_ptr; /* 0x00z438 */
163 uint64_t ce_lsi_rty_fifo_cred; /* 0x00z440 */
164 uint64_t ce_lsi_seq_cnt; /* 0x00z448 */
165 uint64_t ce_lsi_ack_sent_seq_num; /* 0x00z450 */
166 uint64_t ce_lsi_seq_cnt_fifo_max_addr; /* 0x00z458 */
167 uint64_t ce_lsi_seq_cnt_fifo_ptr; /* 0x00z460 */
168 uint64_t ce_lsi_seq_cnt_rd_wr_ptr; /* 0x00z468 */
169 uint64_t ce_lsi_tx_lk_ts_ctl; /* 0x00z470 */
170 uint64_t ce_pad_00z478; /* 0x00z478 */
171 uint64_t ce_lsi_mem_addr_ctl; /* 0x00z480 */
172 uint64_t ce_lsi_mem_d_ld0; /* 0x00z488 */
173 uint64_t ce_lsi_mem_d_ld1; /* 0x00z490 */
174 uint64_t ce_lsi_mem_d_ld2; /* 0x00z498 */
175 uint64_t ce_lsi_mem_d_ld3; /* 0x00z4A0 */
176 uint64_t ce_lsi_mem_d_ld4; /* 0x00z4A8 */
177 uint64_t ce_pad_00z4B0[2]; /* 0x00z4B0 -- 0x00z4B8 */
178 uint64_t ce_lsi_rty_d_cnt; /* 0x00z4C0 */
179 uint64_t ce_lsi_seq_buf_cnt; /* 0x00z4C8 */
180 uint64_t ce_lsi_seq_buf_bt_d; /* 0x00z4D0 */
181 uint64_t ce_pad_00z4D8; /* 0x00z4D8 */
182 uint64_t ce_lsi_ack_lat_thr; /* 0x00z4E0 */
183 uint64_t ce_pad_00z4E8[3]; /* 0x00z4E8 -- 0x00z4F8 */
184 uint64_t ce_lsi_nxt_rcv_seq_1_cntr; /* 0x00z500 */
185 uint64_t ce_lsi_unsp_dllp_rcvd; /* 0x00z508 */
186 uint64_t ce_lsi_rcv_lk_ts_ctl; /* 0x00z510 */
187 uint64_t ce_pad_00z518[29]; /* 0x00z518 -- 0x00z5F8 */
188 uint64_t ce_lsi_phy_lyr_cfg; /* 0x00z600 */
189 uint64_t ce_pad_00z608; /* 0x00z608 */
190 uint64_t ce_lsi_phy_lyr_int_stat; /* 0x00z610 */
191 uint64_t ce_lsi_phy_lyr_int_stat_test; /* 0x00z618 */
192 uint64_t ce_lsi_phy_lyr_int_mask; /* 0x00z620 */
193 uint64_t ce_pad_00z628[11]; /* 0x00z628 -- 0x00z678 */
194 uint64_t ce_lsi_rcv_phy_cfg; /* 0x00z680 */
195 uint64_t ce_lsi_rcv_phy_stat1; /* 0x00z688 */
196 uint64_t ce_lsi_rcv_phy_stat2; /* 0x00z690 */
197 uint64_t ce_lsi_rcv_phy_stat3; /* 0x00z698 */
198 uint64_t ce_lsi_rcv_phy_int_stat; /* 0x00z6A0 */
199 uint64_t ce_lsi_rcv_phy_int_stat_test; /* 0x00z6A8 */
200 uint64_t ce_lsi_rcv_phy_int_mask; /* 0x00z6B0 */
201 uint64_t ce_pad_00z6B8[9]; /* 0x00z6B8 -- 0x00z6F8 */
202 uint64_t ce_lsi_tx_phy_cfg; /* 0x00z700 */
203 uint64_t ce_lsi_tx_phy_stat; /* 0x00z708 */
204 uint64_t ce_lsi_tx_phy_int_stat; /* 0x00z710 */
205 uint64_t ce_lsi_tx_phy_int_stat_test; /* 0x00z718 */
206 uint64_t ce_lsi_tx_phy_int_mask; /* 0x00z720 */
207 uint64_t ce_lsi_tx_phy_stat2; /* 0x00z728 */
208 uint64_t ce_pad_00z730[10]; /* 0x00z730 -- 0x00z77F */
209 uint64_t ce_lsi_ltssm_cfg1; /* 0x00z780 */
210 uint64_t ce_lsi_ltssm_cfg2; /* 0x00z788 */
211 uint64_t ce_lsi_ltssm_cfg3; /* 0x00z790 */
212 uint64_t ce_lsi_ltssm_cfg4; /* 0x00z798 */
213 uint64_t ce_lsi_ltssm_cfg5; /* 0x00z7A0 */
214 uint64_t ce_lsi_ltssm_stat1; /* 0x00z7A8 */
215 uint64_t ce_lsi_ltssm_stat2; /* 0x00z7B0 */
216 uint64_t ce_lsi_ltssm_int_stat; /* 0x00z7B8 */
217 uint64_t ce_lsi_ltssm_int_stat_test; /* 0x00z7C0 */
218 uint64_t ce_lsi_ltssm_int_mask; /* 0x00z7C8 */
219 uint64_t ce_lsi_ltssm_stat_wr_en; /* 0x00z7D0 */
220 uint64_t ce_pad_00z7D8[5]; /* 0x00z7D8 -- 0x00z7F8 */
221 uint64_t ce_lsi_gb_cfg1; /* 0x00z800 */
222 uint64_t ce_lsi_gb_cfg2; /* 0x00z808 */
223 uint64_t ce_lsi_gb_cfg3; /* 0x00z810 */
224 uint64_t ce_lsi_gb_cfg4; /* 0x00z818 */
225 uint64_t ce_lsi_gb_stat; /* 0x00z820 */
226 uint64_t ce_lsi_gb_int_stat; /* 0x00z828 */
227 uint64_t ce_lsi_gb_int_stat_test; /* 0x00z830 */
228 uint64_t ce_lsi_gb_int_mask; /* 0x00z838 */
229 uint64_t ce_lsi_gb_pwr_dn1; /* 0x00z840 */
230 uint64_t ce_lsi_gb_pwr_dn2; /* 0x00z848 */
231 uint64_t ce_pad_00z850[246]; /* 0x00z850 -- 0x00zFF8 */
232 } ce_lsi[2];
233
234 uint64_t ce_pad_004000[10]; /* 0x004000 -- 0x004048 */
235
236 /*
237 * CRM: Coretalk Receive Module Registers
238 */
239 uint64_t ce_crm_debug_mux; /* 0x004050 */
240 uint64_t ce_pad_004058; /* 0x004058 */
241 uint64_t ce_crm_ssp_err_cmd_wrd; /* 0x004060 */
242 uint64_t ce_crm_ssp_err_addr; /* 0x004068 */
243 uint64_t ce_crm_ssp_err_syn; /* 0x004070 */
244
245 uint64_t ce_pad_004078[499]; /* 0x004078 -- 0x005008 */
246
247 /*
248 * CXM: Coretalk Xmit Module Registers
249 */
250 uint64_t ce_cxm_dyn_credit_status; /* 0x005010 */
251 uint64_t ce_cxm_last_credit_status; /* 0x005018 */
252 uint64_t ce_cxm_credit_limit; /* 0x005020 */
253 uint64_t ce_cxm_force_credit; /* 0x005028 */
254 uint64_t ce_cxm_disable_bypass; /* 0x005030 */
255 uint64_t ce_pad_005038[3]; /* 0x005038 -- 0x005048 */
256 uint64_t ce_cxm_debug_mux; /* 0x005050 */
257
258 uint64_t ce_pad_005058[501]; /* 0x005058 -- 0x005FF8 */
259
260 /*
261 * DTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
262 * DTL: Link#1 MMRs at start at 0x006000, Link#2 MMRs at 0x008000
263 * DTL: the comment offsets at far right: let 'y' = {6 or 8}
264 *
265 * UTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
266 * UTL: Link#1 MMRs at start at 0x007000, Link#2 MMRs at 0x009000
267 * UTL: the comment offsets at far right: let 'z' = {7 or 9}
268 */
269 #define ce_dtl(link_num) ce_dtl_utl[link_num-1]
270 #define ce_utl(link_num) ce_dtl_utl[link_num-1]
271 struct ce_dtl_utl_reg {
272 /* DTL */
273 uint64_t ce_dtl_dtdr_credit_limit; /* 0x00y000 */
274 uint64_t ce_dtl_dtdr_credit_force; /* 0x00y008 */
275 uint64_t ce_dtl_dyn_credit_status; /* 0x00y010 */
276 uint64_t ce_dtl_dtl_last_credit_stat; /* 0x00y018 */
277 uint64_t ce_dtl_dtl_ctrl; /* 0x00y020 */
278 uint64_t ce_pad_00y028[5]; /* 0x00y028 -- 0x00y048 */
279 uint64_t ce_dtl_debug_sel; /* 0x00y050 */
280 uint64_t ce_pad_00y058[501]; /* 0x00y058 -- 0x00yFF8 */
281
282 /* UTL */
283 uint64_t ce_utl_utl_ctrl; /* 0x00z000 */
284 uint64_t ce_utl_debug_sel; /* 0x00z008 */
285 uint64_t ce_pad_00z010[510]; /* 0x00z010 -- 0x00zFF8 */
286 } ce_dtl_utl[2];
287
288 uint64_t ce_pad_00A000[514]; /* 0x00A000 -- 0x00B008 */
289
290 /*
291 * URE: Upstream Request Engine
292 */
293 uint64_t ce_ure_dyn_credit_status; /* 0x00B010 */
294 uint64_t ce_ure_last_credit_status; /* 0x00B018 */
295 uint64_t ce_ure_credit_limit; /* 0x00B020 */
296 uint64_t ce_pad_00B028; /* 0x00B028 */
297 uint64_t ce_ure_control; /* 0x00B030 */
298 uint64_t ce_ure_status; /* 0x00B038 */
299 uint64_t ce_pad_00B040[2]; /* 0x00B040 -- 0x00B048 */
300 uint64_t ce_ure_debug_sel; /* 0x00B050 */
301 uint64_t ce_ure_pcie_debug_sel; /* 0x00B058 */
302 uint64_t ce_ure_ssp_err_cmd_wrd; /* 0x00B060 */
303 uint64_t ce_ure_ssp_err_addr; /* 0x00B068 */
304 uint64_t ce_ure_page_map; /* 0x00B070 */
305 uint64_t ce_ure_dir_map[TIOCE_NUM_PORTS]; /* 0x00B078 */
306 uint64_t ce_ure_pipe_sel1; /* 0x00B088 */
307 uint64_t ce_ure_pipe_mask1; /* 0x00B090 */
308 uint64_t ce_ure_pipe_sel2; /* 0x00B098 */
309 uint64_t ce_ure_pipe_mask2; /* 0x00B0A0 */
310 uint64_t ce_ure_pcie1_credits_sent; /* 0x00B0A8 */
311 uint64_t ce_ure_pcie1_credits_used; /* 0x00B0B0 */
312 uint64_t ce_ure_pcie1_credit_limit; /* 0x00B0B8 */
313 uint64_t ce_ure_pcie2_credits_sent; /* 0x00B0C0 */
314 uint64_t ce_ure_pcie2_credits_used; /* 0x00B0C8 */
315 uint64_t ce_ure_pcie2_credit_limit; /* 0x00B0D0 */
316 uint64_t ce_ure_pcie_force_credit; /* 0x00B0D8 */
317 uint64_t ce_ure_rd_tnum_val; /* 0x00B0E0 */
318 uint64_t ce_ure_rd_tnum_rsp_rcvd; /* 0x00B0E8 */
319 uint64_t ce_ure_rd_tnum_esent_timer; /* 0x00B0F0 */
320 uint64_t ce_ure_rd_tnum_error; /* 0x00B0F8 */
321 uint64_t ce_ure_rd_tnum_first_cl; /* 0x00B100 */
322 uint64_t ce_ure_rd_tnum_link_buf; /* 0x00B108 */
323 uint64_t ce_ure_wr_tnum_val; /* 0x00B110 */
324 uint64_t ce_ure_sram_err_addr0; /* 0x00B118 */
325 uint64_t ce_ure_sram_err_addr1; /* 0x00B120 */
326 uint64_t ce_ure_sram_err_addr2; /* 0x00B128 */
327 uint64_t ce_ure_sram_rd_addr0; /* 0x00B130 */
328 uint64_t ce_ure_sram_rd_addr1; /* 0x00B138 */
329 uint64_t ce_ure_sram_rd_addr2; /* 0x00B140 */
330 uint64_t ce_ure_sram_wr_addr0; /* 0x00B148 */
331 uint64_t ce_ure_sram_wr_addr1; /* 0x00B150 */
332 uint64_t ce_ure_sram_wr_addr2; /* 0x00B158 */
333 uint64_t ce_ure_buf_flush10; /* 0x00B160 */
334 uint64_t ce_ure_buf_flush11; /* 0x00B168 */
335 uint64_t ce_ure_buf_flush12; /* 0x00B170 */
336 uint64_t ce_ure_buf_flush13; /* 0x00B178 */
337 uint64_t ce_ure_buf_flush20; /* 0x00B180 */
338 uint64_t ce_ure_buf_flush21; /* 0x00B188 */
339 uint64_t ce_ure_buf_flush22; /* 0x00B190 */
340 uint64_t ce_ure_buf_flush23; /* 0x00B198 */
341 uint64_t ce_ure_pcie_control1; /* 0x00B1A0 */
342 uint64_t ce_ure_pcie_control2; /* 0x00B1A8 */
343
344 uint64_t ce_pad_00B1B0[458]; /* 0x00B1B0 -- 0x00BFF8 */
345
346 /* Upstream Data Buffer, Port1 */
347 struct ce_ure_maint_ups_dat1_data {
348 uint64_t data63_0[512]; /* 0x00C000 -- 0x00CFF8 */
349 uint64_t data127_64[512]; /* 0x00D000 -- 0x00DFF8 */
350 uint64_t parity[512]; /* 0x00E000 -- 0x00EFF8 */
351 } ce_ure_maint_ups_dat1;
352
353 /* Upstream Header Buffer, Port1 */
354 struct ce_ure_maint_ups_hdr1_data {
355 uint64_t data63_0[512]; /* 0x00F000 -- 0x00FFF8 */
356 uint64_t data127_64[512]; /* 0x010000 -- 0x010FF8 */
357 uint64_t parity[512]; /* 0x011000 -- 0x011FF8 */
358 } ce_ure_maint_ups_hdr1;
359
360 /* Upstream Data Buffer, Port2 */
361 struct ce_ure_maint_ups_dat2_data {
362 uint64_t data63_0[512]; /* 0x012000 -- 0x012FF8 */
363 uint64_t data127_64[512]; /* 0x013000 -- 0x013FF8 */
364 uint64_t parity[512]; /* 0x014000 -- 0x014FF8 */
365 } ce_ure_maint_ups_dat2;
366
367 /* Upstream Header Buffer, Port2 */
368 struct ce_ure_maint_ups_hdr2_data {
369 uint64_t data63_0[512]; /* 0x015000 -- 0x015FF8 */
370 uint64_t data127_64[512]; /* 0x016000 -- 0x016FF8 */
371 uint64_t parity[512]; /* 0x017000 -- 0x017FF8 */
372 } ce_ure_maint_ups_hdr2;
373
374 /* Downstream Data Buffer */
375 struct ce_ure_maint_dns_dat_data {
376 uint64_t data63_0[512]; /* 0x018000 -- 0x018FF8 */
377 uint64_t data127_64[512]; /* 0x019000 -- 0x019FF8 */
378 uint64_t parity[512]; /* 0x01A000 -- 0x01AFF8 */
379 } ce_ure_maint_dns_dat;
380
381 /* Downstream Header Buffer */
382 struct ce_ure_maint_dns_hdr_data {
383 uint64_t data31_0[64]; /* 0x01B000 -- 0x01B1F8 */
384 uint64_t data95_32[64]; /* 0x01B200 -- 0x01B3F8 */
385 uint64_t parity[64]; /* 0x01B400 -- 0x01B5F8 */
386 } ce_ure_maint_dns_hdr;
387
388 /* RCI Buffer Data */
389 struct ce_ure_maint_rci_data {
390 uint64_t data41_0[64]; /* 0x01B600 -- 0x01B7F8 */
391 uint64_t data69_42[64]; /* 0x01B800 -- 0x01B9F8 */
392 } ce_ure_maint_rci;
393
394 /* Response Queue */
395 uint64_t ce_ure_maint_rspq[64]; /* 0x01BA00 -- 0x01BBF8 */
396
397 uint64_t ce_pad_01C000[4224]; /* 0x01BC00 -- 0x023FF8 */
398
399 /* Admin Build-a-Packet Buffer */
400 struct ce_adm_maint_bap_buf_data {
401 uint64_t data63_0[258]; /* 0x024000 -- 0x024808 */
402 uint64_t data127_64[258]; /* 0x024810 -- 0x025018 */
403 uint64_t parity[258]; /* 0x025020 -- 0x025828 */
404 } ce_adm_maint_bap_buf;
405
406 uint64_t ce_pad_025830[5370]; /* 0x025830 -- 0x02FFF8 */
407
408 /* URE: 40bit PMU ATE Buffer */ /* 0x030000 -- 0x037FF8 */
409 uint64_t ce_ure_ate40[TIOCE_NUM_M40_ATES];
410
411 /* URE: 32/40bit PMU ATE Buffer */ /* 0x038000 -- 0x03BFF8 */
412 uint64_t ce_ure_ate3240[TIOCE_NUM_M3240_ATES];
413
414 uint64_t ce_pad_03C000[2050]; /* 0x03C000 -- 0x040008 */
415
416 /*
417 * DRE: Down Stream Request Engine
418 */
419 uint64_t ce_dre_dyn_credit_status1; /* 0x040010 */
420 uint64_t ce_dre_dyn_credit_status2; /* 0x040018 */
421 uint64_t ce_dre_last_credit_status1; /* 0x040020 */
422 uint64_t ce_dre_last_credit_status2; /* 0x040028 */
423 uint64_t ce_dre_credit_limit1; /* 0x040030 */
424 uint64_t ce_dre_credit_limit2; /* 0x040038 */
425 uint64_t ce_dre_force_credit1; /* 0x040040 */
426 uint64_t ce_dre_force_credit2; /* 0x040048 */
427 uint64_t ce_dre_debug_mux1; /* 0x040050 */
428 uint64_t ce_dre_debug_mux2; /* 0x040058 */
429 uint64_t ce_dre_ssp_err_cmd_wrd; /* 0x040060 */
430 uint64_t ce_dre_ssp_err_addr; /* 0x040068 */
431 uint64_t ce_dre_comp_err_cmd_wrd; /* 0x040070 */
432 uint64_t ce_dre_comp_err_addr; /* 0x040078 */
433 uint64_t ce_dre_req_status; /* 0x040080 */
434 uint64_t ce_dre_config1; /* 0x040088 */
435 uint64_t ce_dre_config2; /* 0x040090 */
436 uint64_t ce_dre_config_req_status; /* 0x040098 */
437 uint64_t ce_pad_0400A0[12]; /* 0x0400A0 -- 0x0400F8 */
438 uint64_t ce_dre_dyn_fifo; /* 0x040100 */
439 uint64_t ce_pad_040108[3]; /* 0x040108 -- 0x040118 */
440 uint64_t ce_dre_last_fifo; /* 0x040120 */
441
442 uint64_t ce_pad_040128[27]; /* 0x040128 -- 0x0401F8 */
443
444 /* DRE Downstream Head Queue */
445 struct ce_dre_maint_ds_head_queue {
446 uint64_t data63_0[32]; /* 0x040200 -- 0x0402F8 */
447 uint64_t data127_64[32]; /* 0x040300 -- 0x0403F8 */
448 uint64_t parity[32]; /* 0x040400 -- 0x0404F8 */
449 } ce_dre_maint_ds_head_q;
450
451 uint64_t ce_pad_040500[352]; /* 0x040500 -- 0x040FF8 */
452
453 /* DRE Downstream Data Queue */
454 struct ce_dre_maint_ds_data_queue {
455 uint64_t data63_0[256]; /* 0x041000 -- 0x0417F8 */
456 uint64_t ce_pad_041800[256]; /* 0x041800 -- 0x041FF8 */
457 uint64_t data127_64[256]; /* 0x042000 -- 0x0427F8 */
458 uint64_t ce_pad_042800[256]; /* 0x042800 -- 0x042FF8 */
459 uint64_t parity[256]; /* 0x043000 -- 0x0437F8 */
460 uint64_t ce_pad_043800[256]; /* 0x043800 -- 0x043FF8 */
461 } ce_dre_maint_ds_data_q;
462
463 /* DRE URE Upstream Response Queue */
464 struct ce_dre_maint_ure_us_rsp_queue {
465 uint64_t data63_0[8]; /* 0x044000 -- 0x044038 */
466 uint64_t ce_pad_044040[24]; /* 0x044040 -- 0x0440F8 */
467 uint64_t data127_64[8]; /* 0x044100 -- 0x044138 */
468 uint64_t ce_pad_044140[24]; /* 0x044140 -- 0x0441F8 */
469 uint64_t parity[8]; /* 0x044200 -- 0x044238 */
470 uint64_t ce_pad_044240[24]; /* 0x044240 -- 0x0442F8 */
471 } ce_dre_maint_ure_us_rsp_q;
472
473 uint64_t ce_dre_maint_us_wrt_rsp[32];/* 0x044300 -- 0x0443F8 */
474
475 uint64_t ce_end_of_struct; /* 0x044400 */
476} tioce_t;
477
478
479/* ce_adm_int_mask/ce_adm_int_status register bit defines */
480#define CE_ADM_INT_CE_ERROR_SHFT 0
481#define CE_ADM_INT_LSI1_IP_ERROR_SHFT 1
482#define CE_ADM_INT_LSI2_IP_ERROR_SHFT 2
483#define CE_ADM_INT_PCIE_ERROR_SHFT 3
484#define CE_ADM_INT_PORT1_HOTPLUG_EVENT_SHFT 4
485#define CE_ADM_INT_PORT2_HOTPLUG_EVENT_SHFT 5
486#define CE_ADM_INT_PCIE_PORT1_DEV_A_SHFT 6
487#define CE_ADM_INT_PCIE_PORT1_DEV_B_SHFT 7
488#define CE_ADM_INT_PCIE_PORT1_DEV_C_SHFT 8
489#define CE_ADM_INT_PCIE_PORT1_DEV_D_SHFT 9
490#define CE_ADM_INT_PCIE_PORT2_DEV_A_SHFT 10
491#define CE_ADM_INT_PCIE_PORT2_DEV_B_SHFT 11
492#define CE_ADM_INT_PCIE_PORT2_DEV_C_SHFT 12
493#define CE_ADM_INT_PCIE_PORT2_DEV_D_SHFT 13
494#define CE_ADM_INT_PCIE_MSG_SHFT 14 /*see int_dest_14*/
495#define CE_ADM_INT_PCIE_MSG_SLOT_0_SHFT 14
496#define CE_ADM_INT_PCIE_MSG_SLOT_1_SHFT 15
497#define CE_ADM_INT_PCIE_MSG_SLOT_2_SHFT 16
498#define CE_ADM_INT_PCIE_MSG_SLOT_3_SHFT 17
499#define CE_ADM_INT_PORT1_PM_PME_MSG_SHFT 22
500#define CE_ADM_INT_PORT2_PM_PME_MSG_SHFT 23
501
502/* ce_adm_force_int register bit defines */
503#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_A_SHFT 0
504#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_B_SHFT 1
505#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_C_SHFT 2
506#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_D_SHFT 3
507#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_A_SHFT 4
508#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_B_SHFT 5
509#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_C_SHFT 6
510#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_D_SHFT 7
511#define CE_ADM_FORCE_INT_ALWAYS_SHFT 8
512
513/* ce_adm_int_dest register bit masks & shifts */
514#define INTR_VECTOR_SHFT 56
515
516/* ce_adm_error_mask and ce_adm_error_summary register bit masks */
517#define CE_ADM_ERR_CRM_SSP_REQ_INVALID (0x1ULL << 0)
518#define CE_ADM_ERR_SSP_REQ_HEADER (0x1ULL << 1)
519#define CE_ADM_ERR_SSP_RSP_HEADER (0x1ULL << 2)
520#define CE_ADM_ERR_SSP_PROTOCOL_ERROR (0x1ULL << 3)
521#define CE_ADM_ERR_SSP_SBE (0x1ULL << 4)
522#define CE_ADM_ERR_SSP_MBE (0x1ULL << 5)
523#define CE_ADM_ERR_CXM_CREDIT_OFLOW (0x1ULL << 6)
524#define CE_ADM_ERR_DRE_SSP_REQ_INVAL (0x1ULL << 7)
525#define CE_ADM_ERR_SSP_REQ_LONG (0x1ULL << 8)
526#define CE_ADM_ERR_SSP_REQ_OFLOW (0x1ULL << 9)
527#define CE_ADM_ERR_SSP_REQ_SHORT (0x1ULL << 10)
528#define CE_ADM_ERR_SSP_REQ_SIDEBAND (0x1ULL << 11)
529#define CE_ADM_ERR_SSP_REQ_ADDR_ERR (0x1ULL << 12)
530#define CE_ADM_ERR_SSP_REQ_BAD_BE (0x1ULL << 13)
531#define CE_ADM_ERR_PCIE_COMPL_TIMEOUT (0x1ULL << 14)
532#define CE_ADM_ERR_PCIE_UNEXP_COMPL (0x1ULL << 15)
533#define CE_ADM_ERR_PCIE_ERR_COMPL (0x1ULL << 16)
534#define CE_ADM_ERR_DRE_CREDIT_OFLOW (0x1ULL << 17)
535#define CE_ADM_ERR_DRE_SRAM_PE (0x1ULL << 18)
536#define CE_ADM_ERR_SSP_RSP_INVALID (0x1ULL << 19)
537#define CE_ADM_ERR_SSP_RSP_LONG (0x1ULL << 20)
538#define CE_ADM_ERR_SSP_RSP_SHORT (0x1ULL << 21)
539#define CE_ADM_ERR_SSP_RSP_SIDEBAND (0x1ULL << 22)
540#define CE_ADM_ERR_URE_SSP_RSP_UNEXP (0x1ULL << 23)
541#define CE_ADM_ERR_URE_SSP_WR_REQ_TIMEOUT (0x1ULL << 24)
542#define CE_ADM_ERR_URE_SSP_RD_REQ_TIMEOUT (0x1ULL << 25)
543#define CE_ADM_ERR_URE_ATE3240_PAGE_FAULT (0x1ULL << 26)
544#define CE_ADM_ERR_URE_ATE40_PAGE_FAULT (0x1ULL << 27)
545#define CE_ADM_ERR_URE_CREDIT_OFLOW (0x1ULL << 28)
546#define CE_ADM_ERR_URE_SRAM_PE (0x1ULL << 29)
547#define CE_ADM_ERR_ADM_SSP_RSP_UNEXP (0x1ULL << 30)
548#define CE_ADM_ERR_ADM_SSP_REQ_TIMEOUT (0x1ULL << 31)
549#define CE_ADM_ERR_MMR_ACCESS_ERROR (0x1ULL << 32)
550#define CE_ADM_ERR_MMR_ADDR_ERROR (0x1ULL << 33)
551#define CE_ADM_ERR_ADM_CREDIT_OFLOW (0x1ULL << 34)
552#define CE_ADM_ERR_ADM_SRAM_PE (0x1ULL << 35)
553#define CE_ADM_ERR_DTL1_MIN_PDATA_CREDIT_ERR (0x1ULL << 36)
554#define CE_ADM_ERR_DTL1_INF_COMPL_CRED_UPDT_ERR (0x1ULL << 37)
555#define CE_ADM_ERR_DTL1_INF_POSTED_CRED_UPDT_ERR (0x1ULL << 38)
556#define CE_ADM_ERR_DTL1_INF_NPOSTED_CRED_UPDT_ERR (0x1ULL << 39)
557#define CE_ADM_ERR_DTL1_COMP_HD_CRED_MAX_ERR (0x1ULL << 40)
558#define CE_ADM_ERR_DTL1_COMP_D_CRED_MAX_ERR (0x1ULL << 41)
559#define CE_ADM_ERR_DTL1_NPOSTED_HD_CRED_MAX_ERR (0x1ULL << 42)
560#define CE_ADM_ERR_DTL1_NPOSTED_D_CRED_MAX_ERR (0x1ULL << 43)
561#define CE_ADM_ERR_DTL1_POSTED_HD_CRED_MAX_ERR (0x1ULL << 44)
562#define CE_ADM_ERR_DTL1_POSTED_D_CRED_MAX_ERR (0x1ULL << 45)
563#define CE_ADM_ERR_DTL2_MIN_PDATA_CREDIT_ERR (0x1ULL << 46)
564#define CE_ADM_ERR_DTL2_INF_COMPL_CRED_UPDT_ERR (0x1ULL << 47)
565#define CE_ADM_ERR_DTL2_INF_POSTED_CRED_UPDT_ERR (0x1ULL << 48)
566#define CE_ADM_ERR_DTL2_INF_NPOSTED_CRED_UPDT_ERR (0x1ULL << 49)
567#define CE_ADM_ERR_DTL2_COMP_HD_CRED_MAX_ERR (0x1ULL << 50)
568#define CE_ADM_ERR_DTL2_COMP_D_CRED_MAX_ERR (0x1ULL << 51)
569#define CE_ADM_ERR_DTL2_NPOSTED_HD_CRED_MAX_ERR (0x1ULL << 52)
570#define CE_ADM_ERR_DTL2_NPOSTED_D_CRED_MAX_ERR (0x1ULL << 53)
571#define CE_ADM_ERR_DTL2_POSTED_HD_CRED_MAX_ERR (0x1ULL << 54)
572#define CE_ADM_ERR_DTL2_POSTED_D_CRED_MAX_ERR (0x1ULL << 55)
573#define CE_ADM_ERR_PORT1_PCIE_COR_ERR (0x1ULL << 56)
574#define CE_ADM_ERR_PORT1_PCIE_NFAT_ERR (0x1ULL << 57)
575#define CE_ADM_ERR_PORT1_PCIE_FAT_ERR (0x1ULL << 58)
576#define CE_ADM_ERR_PORT2_PCIE_COR_ERR (0x1ULL << 59)
577#define CE_ADM_ERR_PORT2_PCIE_NFAT_ERR (0x1ULL << 60)
578#define CE_ADM_ERR_PORT2_PCIE_FAT_ERR (0x1ULL << 61)
579
580/* ce_adm_ure_ups_buf_barrier_flush register bit masks and shifts */
581#define FLUSH_SEL_PORT1_PIPE0_SHFT 0
582#define FLUSH_SEL_PORT1_PIPE1_SHFT 4
583#define FLUSH_SEL_PORT1_PIPE2_SHFT 8
584#define FLUSH_SEL_PORT1_PIPE3_SHFT 12
585#define FLUSH_SEL_PORT2_PIPE0_SHFT 16
586#define FLUSH_SEL_PORT2_PIPE1_SHFT 20
587#define FLUSH_SEL_PORT2_PIPE2_SHFT 24
588#define FLUSH_SEL_PORT2_PIPE3_SHFT 28
589
590/* ce_dre_config1 register bit masks and shifts */
591#define CE_DRE_RO_ENABLE (0x1ULL << 0)
592#define CE_DRE_DYN_RO_ENABLE (0x1ULL << 1)
593#define CE_DRE_SUP_CONFIG_COMP_ERROR (0x1ULL << 2)
594#define CE_DRE_SUP_IO_COMP_ERROR (0x1ULL << 3)
595#define CE_DRE_ADDR_MODE_SHFT 4
596
597/* ce_dre_config_req_status register bit masks */
598#define CE_DRE_LAST_CONFIG_COMPLETION (0x7ULL << 0)
599#define CE_DRE_DOWNSTREAM_CONFIG_ERROR (0x1ULL << 3)
600#define CE_DRE_CONFIG_COMPLETION_VALID (0x1ULL << 4)
601#define CE_DRE_CONFIG_REQUEST_ACTIVE (0x1ULL << 5)
602
603/* ce_ure_control register bit masks & shifts */
604#define CE_URE_RD_MRG_ENABLE (0x1ULL << 0)
605#define CE_URE_WRT_MRG_ENABLE1 (0x1ULL << 4)
606#define CE_URE_WRT_MRG_ENABLE2 (0x1ULL << 5)
607#define CE_URE_RSPQ_BYPASS_DISABLE (0x1ULL << 24)
608#define CE_URE_UPS_DAT1_PAR_DISABLE (0x1ULL << 32)
609#define CE_URE_UPS_HDR1_PAR_DISABLE (0x1ULL << 33)
610#define CE_URE_UPS_DAT2_PAR_DISABLE (0x1ULL << 34)
611#define CE_URE_UPS_HDR2_PAR_DISABLE (0x1ULL << 35)
612#define CE_URE_ATE_PAR_DISABLE (0x1ULL << 36)
613#define CE_URE_RCI_PAR_DISABLE (0x1ULL << 37)
614#define CE_URE_RSPQ_PAR_DISABLE (0x1ULL << 38)
615#define CE_URE_DNS_DAT_PAR_DISABLE (0x1ULL << 39)
616#define CE_URE_DNS_HDR_PAR_DISABLE (0x1ULL << 40)
617#define CE_URE_MALFORM_DISABLE (0x1ULL << 44)
618#define CE_URE_UNSUP_DISABLE (0x1ULL << 45)
619
620/* ce_ure_page_map register bit masks & shifts */
621#define CE_URE_ATE3240_ENABLE (0x1ULL << 0)
622#define CE_URE_ATE40_ENABLE (0x1ULL << 1)
623#define CE_URE_PAGESIZE_SHFT 4
624#define CE_URE_PAGESIZE_MASK (0x7ULL << CE_URE_PAGESIZE_SHFT)
625#define CE_URE_4K_PAGESIZE (0x0ULL << CE_URE_PAGESIZE_SHFT)
626#define CE_URE_16K_PAGESIZE (0x1ULL << CE_URE_PAGESIZE_SHFT)
627#define CE_URE_64K_PAGESIZE (0x2ULL << CE_URE_PAGESIZE_SHFT)
628#define CE_URE_128K_PAGESIZE (0x3ULL << CE_URE_PAGESIZE_SHFT)
629#define CE_URE_256K_PAGESIZE (0x4ULL << CE_URE_PAGESIZE_SHFT)
630
631/* ce_ure_pipe_sel register bit masks & shifts */
632#define PKT_TRAFIC_SHRT 16
633#define BUS_SRC_ID_SHFT 8
634#define DEV_SRC_ID_SHFT 3
635#define FNC_SRC_ID_SHFT 0
636#define CE_URE_TC_MASK (0x07ULL << PKT_TRAFIC_SHRT)
637#define CE_URE_BUS_MASK (0xFFULL << BUS_SRC_ID_SHFT)
638#define CE_URE_DEV_MASK (0x1FULL << DEV_SRC_ID_SHFT)
639#define CE_URE_FNC_MASK (0x07ULL << FNC_SRC_ID_SHFT)
640#define CE_URE_PIPE_BUS(b) (((uint64_t)(b) << BUS_SRC_ID_SHFT) & \
641 CE_URE_BUS_MASK)
642#define CE_URE_PIPE_DEV(d) (((uint64_t)(d) << DEV_SRC_ID_SHFT) & \
643 CE_URE_DEV_MASK)
644#define CE_URE_PIPE_FNC(f) (((uint64_t)(f) << FNC_SRC_ID_SHFT) & \
645 CE_URE_FNC_MASK)
646
647#define CE_URE_SEL1_SHFT 0
648#define CE_URE_SEL2_SHFT 20
649#define CE_URE_SEL3_SHFT 40
650#define CE_URE_SEL1_MASK (0x7FFFFULL << CE_URE_SEL1_SHFT)
651#define CE_URE_SEL2_MASK (0x7FFFFULL << CE_URE_SEL2_SHFT)
652#define CE_URE_SEL3_MASK (0x7FFFFULL << CE_URE_SEL3_SHFT)
653
654
655/* ce_ure_pipe_mask register bit masks & shifts */
656#define CE_URE_MASK1_SHFT 0
657#define CE_URE_MASK2_SHFT 20
658#define CE_URE_MASK3_SHFT 40
659#define CE_URE_MASK1_MASK (0x7FFFFULL << CE_URE_MASK1_SHFT)
660#define CE_URE_MASK2_MASK (0x7FFFFULL << CE_URE_MASK2_SHFT)
661#define CE_URE_MASK3_MASK (0x7FFFFULL << CE_URE_MASK3_SHFT)
662
663
664/* ce_ure_pcie_control1 register bit masks & shifts */
665#define CE_URE_SI (0x1ULL << 0)
666#define CE_URE_ELAL_SHFT 4
667#define CE_URE_ELAL_MASK (0x7ULL << CE_URE_ELAL_SHFT)
668#define CE_URE_ELAL1_SHFT 8
669#define CE_URE_ELAL1_MASK (0x7ULL << CE_URE_ELAL1_SHFT)
670#define CE_URE_SCC (0x1ULL << 12)
671#define CE_URE_PN1_SHFT 16
672#define CE_URE_PN1_MASK (0xFFULL << CE_URE_PN1_SHFT)
673#define CE_URE_PN2_SHFT 24
674#define CE_URE_PN2_MASK (0xFFULL << CE_URE_PN2_SHFT)
675#define CE_URE_PN1_SET(n) (((uint64_t)(n) << CE_URE_PN1_SHFT) & \
676 CE_URE_PN1_MASK)
677#define CE_URE_PN2_SET(n) (((uint64_t)(n) << CE_URE_PN2_SHFT) & \
678 CE_URE_PN2_MASK)
679
680/* ce_ure_pcie_control2 register bit masks & shifts */
681#define CE_URE_ABP (0x1ULL << 0)
682#define CE_URE_PCP (0x1ULL << 1)
683#define CE_URE_MSP (0x1ULL << 2)
684#define CE_URE_AIP (0x1ULL << 3)
685#define CE_URE_PIP (0x1ULL << 4)
686#define CE_URE_HPS (0x1ULL << 5)
687#define CE_URE_HPC (0x1ULL << 6)
688#define CE_URE_SPLV_SHFT 7
689#define CE_URE_SPLV_MASK (0xFFULL << CE_URE_SPLV_SHFT)
690#define CE_URE_SPLS_SHFT 15
691#define CE_URE_SPLS_MASK (0x3ULL << CE_URE_SPLS_SHFT)
692#define CE_URE_PSN1_SHFT 19
693#define CE_URE_PSN1_MASK (0x1FFFULL << CE_URE_PSN1_SHFT)
694#define CE_URE_PSN2_SHFT 32
695#define CE_URE_PSN2_MASK (0x1FFFULL << CE_URE_PSN2_SHFT)
696#define CE_URE_PSN1_SET(n) (((uint64_t)(n) << CE_URE_PSN1_SHFT) & \
697 CE_URE_PSN1_MASK)
698#define CE_URE_PSN2_SET(n) (((uint64_t)(n) << CE_URE_PSN2_SHFT) & \
699 CE_URE_PSN2_MASK)
700
701/*
702 * PIO address space ranges for CE
703 */
704
705/* Local CE Registers Space */
706#define CE_PIO_MMR 0x00000000
707#define CE_PIO_MMR_LEN 0x04000000
708
709/* PCI Compatible Config Space */
710#define CE_PIO_CONFIG_SPACE 0x04000000
711#define CE_PIO_CONFIG_SPACE_LEN 0x04000000
712
713/* PCI I/O Space Alias */
714#define CE_PIO_IO_SPACE_ALIAS 0x08000000
715#define CE_PIO_IO_SPACE_ALIAS_LEN 0x08000000
716
717/* PCI Enhanced Config Space */
718#define CE_PIO_E_CONFIG_SPACE 0x10000000
719#define CE_PIO_E_CONFIG_SPACE_LEN 0x10000000
720
721/* PCI I/O Space */
722#define CE_PIO_IO_SPACE 0x100000000
723#define CE_PIO_IO_SPACE_LEN 0x100000000
724
725/* PCI MEM Space */
726#define CE_PIO_MEM_SPACE 0x200000000
727#define CE_PIO_MEM_SPACE_LEN TIO_HWIN_SIZE
728
729
730/*
731 * CE PCI Enhanced Config Space shifts & masks
732 */
733#define CE_E_CONFIG_BUS_SHFT 20
734#define CE_E_CONFIG_BUS_MASK (0xFF << CE_E_CONFIG_BUS_SHFT)
735#define CE_E_CONFIG_DEVICE_SHFT 15
736#define CE_E_CONFIG_DEVICE_MASK (0x1F << CE_E_CONFIG_DEVICE_SHFT)
737#define CE_E_CONFIG_FUNC_SHFT 12
738#define CE_E_CONFIG_FUNC_MASK (0x7 << CE_E_CONFIG_FUNC_SHFT)
739
740#endif /* __ASM_IA64_SN_TIOCE_H__ */
diff --git a/include/asm-ia64/sn/tioce_provider.h b/include/asm-ia64/sn/tioce_provider.h
new file mode 100644
index 000000000000..7f63dec0a79a
--- /dev/null
+++ b/include/asm-ia64/sn/tioce_provider.h
@@ -0,0 +1,66 @@
1/**************************************************************************
2 * Copyright (C) 2005, Silicon Graphics, Inc. *
3 * *
4 * These coded instructions, statements, and computer programs contain *
5 * unpublished proprietary information of Silicon Graphics, Inc., and *
6 * are protected by Federal copyright law. They may not be disclosed *
7 * to third parties or copied or duplicated in any form, in whole or *
8 * in part, without the prior written consent of Silicon Graphics, Inc. *
9 * *
10 **************************************************************************/
11
12#ifndef _ASM_IA64_SN_CE_PROVIDER_H
13#define _ASM_IA64_SN_CE_PROVIDER_H
14
15#include <asm/sn/pcibus_provider_defs.h>
16#include <asm/sn/tioce.h>
17
18/*
19 * Common TIOCE structure shared between the prom and kernel
20 *
21 * DO NOT CHANGE THIS STRUCT WITHOUT MAKING CORRESPONDING CHANGES TO THE
22 * PROM VERSION.
23 */
24struct tioce_common {
25 struct pcibus_bussoft ce_pcibus; /* common pciio header */
26
27 uint32_t ce_rev;
28 uint64_t ce_kernel_private;
29 uint64_t ce_prom_private;
30};
31
32struct tioce_kernel {
33 struct tioce_common *ce_common;
34 spinlock_t ce_lock;
35 struct list_head ce_dmamap_list;
36
37 uint64_t ce_ate40_shadow[TIOCE_NUM_M40_ATES];
38 uint64_t ce_ate3240_shadow[TIOCE_NUM_M3240_ATES];
39 uint32_t ce_ate3240_pagesize;
40
41 uint8_t ce_port1_secondary;
42
43 /* per-port resources */
44 struct {
45 int dirmap_refcnt;
46 uint64_t dirmap_shadow;
47 } ce_port[TIOCE_NUM_PORTS];
48};
49
50struct tioce_dmamap {
51 struct list_head ce_dmamap_list; /* headed by tioce_kernel */
52 uint32_t refcnt;
53
54 uint64_t nbytes; /* # bytes mapped */
55
56 uint64_t ct_start; /* coretalk start address */
57 uint64_t pci_start; /* bus start address */
58
59 uint64_t *ate_hw; /* hw ptr of first ate in map */
60 uint64_t *ate_shadow; /* shadow ptr of firat ate */
61 uint16_t ate_count; /* # ate's in the map */
62};
63
64extern int tioce_init_provider(void);
65
66#endif /* __ASM_IA64_SN_CE_PROVIDER_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-02 14:20:14 -0400