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authorAndrew Victor <andrew@sanpeople.com>2007-02-08 04:25:38 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-02-08 09:55:27 -0500
commitc177a1e75a07237efe1f68fbf430892fdf2bb868 (patch)
tree4ee68b4037cbe5c64c4385bb1d903270703db90c
parente6d92e6397634ac7d2e80b16c52f0dfab9b673b4 (diff)
[ARM] 4147/1: AT91: Define Timer/Counter clocks.
Define the Timer/Counter Unit clocks on the AT91RM9200, AT91SAM9260 and AT91SAM9261 processors. Original patch from David Brownell. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--arch/arm/mach-at91/at91rm9200.c37
-rw-r--r--arch/arm/mach-at91/at91sam9260.c38
-rw-r--r--arch/arm/mach-at91/at91sam9261.c19
3 files changed, 90 insertions, 4 deletions
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 870d4a4eb806..2ddcdd69df7d 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -117,6 +117,36 @@ static struct clk pioD_clk = {
117 .pmc_mask = 1 << AT91RM9200_ID_PIOD, 117 .pmc_mask = 1 << AT91RM9200_ID_PIOD,
118 .type = CLK_TYPE_PERIPHERAL, 118 .type = CLK_TYPE_PERIPHERAL,
119}; 119};
120static struct clk tc0_clk = {
121 .name = "tc0_clk",
122 .pmc_mask = 1 << AT91RM9200_ID_TC0,
123 .type = CLK_TYPE_PERIPHERAL,
124};
125static struct clk tc1_clk = {
126 .name = "tc1_clk",
127 .pmc_mask = 1 << AT91RM9200_ID_TC1,
128 .type = CLK_TYPE_PERIPHERAL,
129};
130static struct clk tc2_clk = {
131 .name = "tc2_clk",
132 .pmc_mask = 1 << AT91RM9200_ID_TC2,
133 .type = CLK_TYPE_PERIPHERAL,
134};
135static struct clk tc3_clk = {
136 .name = "tc3_clk",
137 .pmc_mask = 1 << AT91RM9200_ID_TC3,
138 .type = CLK_TYPE_PERIPHERAL,
139};
140static struct clk tc4_clk = {
141 .name = "tc4_clk",
142 .pmc_mask = 1 << AT91RM9200_ID_TC4,
143 .type = CLK_TYPE_PERIPHERAL,
144};
145static struct clk tc5_clk = {
146 .name = "tc5_clk",
147 .pmc_mask = 1 << AT91RM9200_ID_TC5,
148 .type = CLK_TYPE_PERIPHERAL,
149};
120 150
121static struct clk *periph_clocks[] __initdata = { 151static struct clk *periph_clocks[] __initdata = {
122 &pioA_clk, 152 &pioA_clk,
@@ -132,7 +162,12 @@ static struct clk *periph_clocks[] __initdata = {
132 &twi_clk, 162 &twi_clk,
133 &spi_clk, 163 &spi_clk,
134 // ssc 0 .. ssc2 164 // ssc 0 .. ssc2
135 // tc0 .. tc5 165 &tc0_clk,
166 &tc1_clk,
167 &tc2_clk,
168 &tc3_clk,
169 &tc4_clk,
170 &tc5_clk,
136 &ohci_clk, 171 &ohci_clk,
137 &ether_clk, 172 &ether_clk,
138 // irq0 .. irq6 173 // irq0 .. irq6
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index ffc4c0944740..e03ee625f40c 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -107,6 +107,21 @@ static struct clk spi1_clk = {
107 .pmc_mask = 1 << AT91SAM9260_ID_SPI1, 107 .pmc_mask = 1 << AT91SAM9260_ID_SPI1,
108 .type = CLK_TYPE_PERIPHERAL, 108 .type = CLK_TYPE_PERIPHERAL,
109}; 109};
110static struct clk tc0_clk = {
111 .name = "tc0_clk",
112 .pmc_mask = 1 << AT91SAM9260_ID_TC0,
113 .type = CLK_TYPE_PERIPHERAL,
114};
115static struct clk tc1_clk = {
116 .name = "tc1_clk",
117 .pmc_mask = 1 << AT91SAM9260_ID_TC1,
118 .type = CLK_TYPE_PERIPHERAL,
119};
120static struct clk tc2_clk = {
121 .name = "tc2_clk",
122 .pmc_mask = 1 << AT91SAM9260_ID_TC2,
123 .type = CLK_TYPE_PERIPHERAL,
124};
110static struct clk ohci_clk = { 125static struct clk ohci_clk = {
111 .name = "ohci_clk", 126 .name = "ohci_clk",
112 .pmc_mask = 1 << AT91SAM9260_ID_UHP, 127 .pmc_mask = 1 << AT91SAM9260_ID_UHP,
@@ -137,6 +152,21 @@ static struct clk usart5_clk = {
137 .pmc_mask = 1 << AT91SAM9260_ID_US5, 152 .pmc_mask = 1 << AT91SAM9260_ID_US5,
138 .type = CLK_TYPE_PERIPHERAL, 153 .type = CLK_TYPE_PERIPHERAL,
139}; 154};
155static struct clk tc3_clk = {
156 .name = "tc3_clk",
157 .pmc_mask = 1 << AT91SAM9260_ID_TC3,
158 .type = CLK_TYPE_PERIPHERAL,
159};
160static struct clk tc4_clk = {
161 .name = "tc4_clk",
162 .pmc_mask = 1 << AT91SAM9260_ID_TC4,
163 .type = CLK_TYPE_PERIPHERAL,
164};
165static struct clk tc5_clk = {
166 .name = "tc5_clk",
167 .pmc_mask = 1 << AT91SAM9260_ID_TC5,
168 .type = CLK_TYPE_PERIPHERAL,
169};
140 170
141static struct clk *periph_clocks[] __initdata = { 171static struct clk *periph_clocks[] __initdata = {
142 &pioA_clk, 172 &pioA_clk,
@@ -152,14 +182,18 @@ static struct clk *periph_clocks[] __initdata = {
152 &spi0_clk, 182 &spi0_clk,
153 &spi1_clk, 183 &spi1_clk,
154 // ssc 184 // ssc
155 // tc0 .. tc2 185 &tc0_clk,
186 &tc1_clk,
187 &tc2_clk,
156 &ohci_clk, 188 &ohci_clk,
157 &ether_clk, 189 &ether_clk,
158 &isi_clk, 190 &isi_clk,
159 &usart3_clk, 191 &usart3_clk,
160 &usart4_clk, 192 &usart4_clk,
161 &usart5_clk, 193 &usart5_clk,
162 // tc3 .. tc5 194 &tc3_clk,
195 &tc4_clk,
196 &tc5_clk,
163 // irq0 .. irq2 197 // irq0 .. irq2
164}; 198};
165 199
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 47e02ff7e872..1a9102368f11 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -97,6 +97,21 @@ static struct clk spi1_clk = {
97 .pmc_mask = 1 << AT91SAM9261_ID_SPI1, 97 .pmc_mask = 1 << AT91SAM9261_ID_SPI1,
98 .type = CLK_TYPE_PERIPHERAL, 98 .type = CLK_TYPE_PERIPHERAL,
99}; 99};
100static struct clk tc0_clk = {
101 .name = "tc0_clk",
102 .pmc_mask = 1 << AT91SAM9261_ID_TC0,
103 .type = CLK_TYPE_PERIPHERAL,
104};
105static struct clk tc1_clk = {
106 .name = "tc1_clk",
107 .pmc_mask = 1 << AT91SAM9261_ID_TC1,
108 .type = CLK_TYPE_PERIPHERAL,
109};
110static struct clk tc2_clk = {
111 .name = "tc2_clk",
112 .pmc_mask = 1 << AT91SAM9261_ID_TC2,
113 .type = CLK_TYPE_PERIPHERAL,
114};
100static struct clk ohci_clk = { 115static struct clk ohci_clk = {
101 .name = "ohci_clk", 116 .name = "ohci_clk",
102 .pmc_mask = 1 << AT91SAM9261_ID_UHP, 117 .pmc_mask = 1 << AT91SAM9261_ID_UHP,
@@ -121,7 +136,9 @@ static struct clk *periph_clocks[] __initdata = {
121 &spi0_clk, 136 &spi0_clk,
122 &spi1_clk, 137 &spi1_clk,
123 // ssc 0 .. ssc2 138 // ssc 0 .. ssc2
124 // tc0 .. tc2 139 &tc0_clk,
140 &tc1_clk,
141 &tc2_clk,
125 &ohci_clk, 142 &ohci_clk,
126 &lcdc_clk, 143 &lcdc_clk,
127 // irq0 .. irq2 144 // irq0 .. irq2