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authorPeter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>2009-09-01 09:49:56 -0400
committerDavid S. Miller <davem@davemloft.net>2009-09-01 20:40:18 -0400
commitb7fdb714856541cd4b659a7b86ec04415e2809f7 (patch)
tree66efbbbae92932967599ad7ae3e44981f1fabf4e
parent8620a103b5e38d952280f3d97b5e1bcce8d7874c (diff)
ixgbe: Properly disable DCB arbiters prior to applying changes
When disabling the Rx and Tx data arbiters prior to configuration changes, the arbiters were not being shut down properly. This can create a race in the DCB hardware blocks, and potentially hang the arbiters. Also, the Tx descriptor arbiter shouldn't be disabled when applying configuration changes; disabling this arbiter can cause a Tx hang. Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_82599.c21
1 files changed, 14 insertions, 7 deletions
diff --git a/drivers/net/ixgbe/ixgbe_dcb_82599.c b/drivers/net/ixgbe/ixgbe_dcb_82599.c
index 589f62c7062a..ec8a252636d3 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_82599.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_82599.c
@@ -145,8 +145,12 @@ s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
145 u32 credit_max = 0; 145 u32 credit_max = 0;
146 u8 i = 0; 146 u8 i = 0;
147 147
148 /* Disable the arbiter before changing parameters */ 148 /*
149 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RTRPCS_ARBDIS); 149 * Disable the arbiter before changing parameters
150 * (always enable recycle mode; WSP)
151 */
152 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
153 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
150 154
151 /* Map all traffic classes to their UP, 1 to 1 */ 155 /* Map all traffic classes to their UP, 1 to 1 */
152 reg = 0; 156 reg = 0;
@@ -194,9 +198,6 @@ s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
194 u32 reg, max_credits; 198 u32 reg, max_credits;
195 u8 i; 199 u8 i;
196 200
197 /* Disable the arbiter before changing parameters */
198 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, IXGBE_RTTDCS_ARBDIS);
199
200 /* Clear the per-Tx queue credits; we use per-TC instead */ 201 /* Clear the per-Tx queue credits; we use per-TC instead */
201 for (i = 0; i < 128; i++) { 202 for (i = 0; i < 128; i++) {
202 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 203 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
@@ -244,8 +245,14 @@ s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
244 u32 reg; 245 u32 reg;
245 u8 i; 246 u8 i;
246 247
247 /* Disable the arbiter before changing parameters */ 248 /*
248 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, IXGBE_RTTPCS_ARBDIS); 249 * Disable the arbiter before changing parameters
250 * (always enable recycle mode; SP; arb delay)
251 */
252 reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
253 (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) |
254 IXGBE_RTTPCS_ARBDIS;
255 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
249 256
250 /* Map all traffic classes to their UP, 1 to 1 */ 257 /* Map all traffic classes to their UP, 1 to 1 */
251 reg = 0; 258 reg = 0;