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authorMingkai Hu <Mingkai.hu@freescale.com>2010-10-12 06:18:31 -0400
committerGrant Likely <grant.likely@secretlab.ca>2010-10-12 23:38:12 -0400
commitb36ece832512c1a0afa54ff0a56d63492a1caf08 (patch)
tree1c8a35d3dd485eb80a56355b5d5cb3bc4b4b2699
parent3272029fb33a88873b9b02224ebeb23bf3a4668e (diff)
spi/mpc8xxx: refactor the common code for SPI/eSPI controller
Refactor the common code in file spi_fsl_spi.c to spi_fsl_lib.c used by SPI/eSPI controller driver as a library, and leave the QE/CPM SPI controller code in the SPI controller driver spi_fsl_spi.c. Because the register map of the SPI controller and eSPI controller is so different, also leave the code operated the register to the driver code, not the common code. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat
-rw-r--r--drivers/spi/Kconfig5
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/spi_fsl_lib.c237
-rw-r--r--drivers/spi/spi_fsl_lib.h119
-rw-r--r--drivers/spi/spi_fsl_spi.c552
5 files changed, 522 insertions, 392 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index e8f02a6f2d23..0e6619426ea4 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -182,9 +182,14 @@ config SPI_MPC512x_PSC
182 This enables using the Freescale MPC5121 Programmable Serial 182 This enables using the Freescale MPC5121 Programmable Serial
183 Controller in SPI master mode. 183 Controller in SPI master mode.
184 184
185config SPI_FSL_LIB
186 tristate
187 depends on FSL_SOC
188
185config SPI_FSL_SPI 189config SPI_FSL_SPI
186 tristate "Freescale SPI controller" 190 tristate "Freescale SPI controller"
187 depends on FSL_SOC 191 depends on FSL_SOC
192 select SPI_FSL_LIB
188 help 193 help
189 This enables using the Freescale SPI controllers in master mode. 194 This enables using the Freescale SPI controllers in master mode.
190 MPC83xx platform uses the controller in cpu mode or CPM/QE mode. 195 MPC83xx platform uses the controller in cpu mode or CPM/QE mode.
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index c6a56c798823..54bd95d63a59 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_SPI_PL022) += amba-pl022.o
32obj-$(CONFIG_SPI_MPC512x_PSC) += mpc512x_psc_spi.o 32obj-$(CONFIG_SPI_MPC512x_PSC) += mpc512x_psc_spi.o
33obj-$(CONFIG_SPI_MPC52xx_PSC) += mpc52xx_psc_spi.o 33obj-$(CONFIG_SPI_MPC52xx_PSC) += mpc52xx_psc_spi.o
34obj-$(CONFIG_SPI_MPC52xx) += mpc52xx_spi.o 34obj-$(CONFIG_SPI_MPC52xx) += mpc52xx_spi.o
35obj-$(CONFIG_SPI_FSL_LIB) += spi_fsl_lib.o
35obj-$(CONFIG_SPI_FSL_SPI) += spi_fsl_spi.o 36obj-$(CONFIG_SPI_FSL_SPI) += spi_fsl_spi.o
36obj-$(CONFIG_SPI_PPC4xx) += spi_ppc4xx.o 37obj-$(CONFIG_SPI_PPC4xx) += spi_ppc4xx.o
37obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o 38obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
diff --git a/drivers/spi/spi_fsl_lib.c b/drivers/spi/spi_fsl_lib.c
new file mode 100644
index 000000000000..5cd741fdb5c3
--- /dev/null
+++ b/drivers/spi/spi_fsl_lib.c
@@ -0,0 +1,237 @@
1/*
2 * Freescale SPI/eSPI controller driver library.
3 *
4 * Maintainer: Kumar Gala
5 *
6 * Copyright (C) 2006 Polycom, Inc.
7 *
8 * CPM SPI and QE buffer descriptors mode support:
9 * Copyright (c) 2009 MontaVista Software, Inc.
10 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
11 *
12 * Copyright 2010 Freescale Semiconductor, Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 */
19#include <linux/kernel.h>
20#include <linux/interrupt.h>
21#include <linux/fsl_devices.h>
22#include <linux/dma-mapping.h>
23#include <linux/mm.h>
24#include <linux/of_platform.h>
25#include <linux/of_spi.h>
26#include <sysdev/fsl_soc.h>
27
28#include "spi_fsl_lib.h"
29
30#define MPC8XXX_SPI_RX_BUF(type) \
31void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
32{ \
33 type *rx = mpc8xxx_spi->rx; \
34 *rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \
35 mpc8xxx_spi->rx = rx; \
36}
37
38#define MPC8XXX_SPI_TX_BUF(type) \
39u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
40{ \
41 u32 data; \
42 const type *tx = mpc8xxx_spi->tx; \
43 if (!tx) \
44 return 0; \
45 data = *tx++ << mpc8xxx_spi->tx_shift; \
46 mpc8xxx_spi->tx = tx; \
47 return data; \
48}
49
50MPC8XXX_SPI_RX_BUF(u8)
51MPC8XXX_SPI_RX_BUF(u16)
52MPC8XXX_SPI_RX_BUF(u32)
53MPC8XXX_SPI_TX_BUF(u8)
54MPC8XXX_SPI_TX_BUF(u16)
55MPC8XXX_SPI_TX_BUF(u32)
56
57struct mpc8xxx_spi_probe_info *to_of_pinfo(struct fsl_spi_platform_data *pdata)
58{
59 return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
60}
61
62void mpc8xxx_spi_work(struct work_struct *work)
63{
64 struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
65 work);
66
67 spin_lock_irq(&mpc8xxx_spi->lock);
68 while (!list_empty(&mpc8xxx_spi->queue)) {
69 struct spi_message *m = container_of(mpc8xxx_spi->queue.next,
70 struct spi_message, queue);
71
72 list_del_init(&m->queue);
73 spin_unlock_irq(&mpc8xxx_spi->lock);
74
75 if (mpc8xxx_spi->spi_do_one_msg)
76 mpc8xxx_spi->spi_do_one_msg(m);
77
78 spin_lock_irq(&mpc8xxx_spi->lock);
79 }
80 spin_unlock_irq(&mpc8xxx_spi->lock);
81}
82
83int mpc8xxx_spi_transfer(struct spi_device *spi,
84 struct spi_message *m)
85{
86 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
87 unsigned long flags;
88
89 m->actual_length = 0;
90 m->status = -EINPROGRESS;
91
92 spin_lock_irqsave(&mpc8xxx_spi->lock, flags);
93 list_add_tail(&m->queue, &mpc8xxx_spi->queue);
94 queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work);
95 spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags);
96
97 return 0;
98}
99
100void mpc8xxx_spi_cleanup(struct spi_device *spi)
101{
102 kfree(spi->controller_state);
103}
104
105const char *mpc8xxx_spi_strmode(unsigned int flags)
106{
107 if (flags & SPI_QE_CPU_MODE) {
108 return "QE CPU";
109 } else if (flags & SPI_CPM_MODE) {
110 if (flags & SPI_QE)
111 return "QE";
112 else if (flags & SPI_CPM2)
113 return "CPM2";
114 else
115 return "CPM1";
116 }
117 return "CPU";
118}
119
120int mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
121 unsigned int irq)
122{
123 struct fsl_spi_platform_data *pdata = dev->platform_data;
124 struct spi_master *master;
125 struct mpc8xxx_spi *mpc8xxx_spi;
126 int ret = 0;
127
128 master = dev_get_drvdata(dev);
129
130 /* the spi->mode bits understood by this driver: */
131 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
132 | SPI_LSB_FIRST | SPI_LOOP;
133
134 master->transfer = mpc8xxx_spi_transfer;
135 master->cleanup = mpc8xxx_spi_cleanup;
136 master->dev.of_node = dev->of_node;
137
138 mpc8xxx_spi = spi_master_get_devdata(master);
139 mpc8xxx_spi->dev = dev;
140 mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
141 mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
142 mpc8xxx_spi->flags = pdata->flags;
143 mpc8xxx_spi->spibrg = pdata->sysclk;
144 mpc8xxx_spi->irq = irq;
145
146 mpc8xxx_spi->rx_shift = 0;
147 mpc8xxx_spi->tx_shift = 0;
148
149 init_completion(&mpc8xxx_spi->done);
150
151 master->bus_num = pdata->bus_num;
152 master->num_chipselect = pdata->max_chipselect;
153
154 spin_lock_init(&mpc8xxx_spi->lock);
155 init_completion(&mpc8xxx_spi->done);
156 INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work);
157 INIT_LIST_HEAD(&mpc8xxx_spi->queue);
158
159 mpc8xxx_spi->workqueue = create_singlethread_workqueue(
160 dev_name(master->dev.parent));
161 if (mpc8xxx_spi->workqueue == NULL) {
162 ret = -EBUSY;
163 goto err;
164 }
165
166 return 0;
167
168err:
169 return ret;
170}
171
172int __devexit mpc8xxx_spi_remove(struct device *dev)
173{
174 struct mpc8xxx_spi *mpc8xxx_spi;
175 struct spi_master *master;
176
177 master = dev_get_drvdata(dev);
178 mpc8xxx_spi = spi_master_get_devdata(master);
179
180 flush_workqueue(mpc8xxx_spi->workqueue);
181 destroy_workqueue(mpc8xxx_spi->workqueue);
182 spi_unregister_master(master);
183
184 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
185
186 if (mpc8xxx_spi->spi_remove)
187 mpc8xxx_spi->spi_remove(mpc8xxx_spi);
188
189 return 0;
190}
191
192int __devinit of_mpc8xxx_spi_probe(struct platform_device *ofdev,
193 const struct of_device_id *ofid)
194{
195 struct device *dev = &ofdev->dev;
196 struct device_node *np = ofdev->dev.of_node;
197 struct mpc8xxx_spi_probe_info *pinfo;
198 struct fsl_spi_platform_data *pdata;
199 const void *prop;
200 int ret = -ENOMEM;
201
202 pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL);
203 if (!pinfo)
204 return -ENOMEM;
205
206 pdata = &pinfo->pdata;
207 dev->platform_data = pdata;
208
209 /* Allocate bus num dynamically. */
210 pdata->bus_num = -1;
211
212 /* SPI controller is either clocked from QE or SoC clock. */
213 pdata->sysclk = get_brgfreq();
214 if (pdata->sysclk == -1) {
215 pdata->sysclk = fsl_get_sys_freq();
216 if (pdata->sysclk == -1) {
217 ret = -ENODEV;
218 goto err;
219 }
220 }
221
222 prop = of_get_property(np, "mode", NULL);
223 if (prop && !strcmp(prop, "cpu-qe"))
224 pdata->flags = SPI_QE_CPU_MODE;
225 else if (prop && !strcmp(prop, "qe"))
226 pdata->flags = SPI_CPM_MODE | SPI_QE;
227 else if (of_device_is_compatible(np, "fsl,cpm2-spi"))
228 pdata->flags = SPI_CPM_MODE | SPI_CPM2;
229 else if (of_device_is_compatible(np, "fsl,cpm1-spi"))
230 pdata->flags = SPI_CPM_MODE | SPI_CPM1;
231
232 return 0;
233
234err:
235 kfree(pinfo);
236 return ret;
237}
diff --git a/drivers/spi/spi_fsl_lib.h b/drivers/spi/spi_fsl_lib.h
new file mode 100644
index 000000000000..6ae894917387
--- /dev/null
+++ b/drivers/spi/spi_fsl_lib.h
@@ -0,0 +1,119 @@
1/*
2 * Freescale SPI/eSPI controller driver library.
3 *
4 * Maintainer: Kumar Gala
5 *
6 * Copyright 2010 Freescale Semiconductor, Inc.
7 * Copyright (C) 2006 Polycom, Inc.
8 *
9 * CPM SPI and QE buffer descriptors mode support:
10 * Copyright (c) 2009 MontaVista Software, Inc.
11 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18#ifndef __SPI_FSL_LIB_H__
19#define __SPI_FSL_LIB_H__
20
21/* SPI/eSPI Controller driver's private data. */
22struct mpc8xxx_spi {
23 struct device *dev;
24 void *reg_base;
25
26 /* rx & tx bufs from the spi_transfer */
27 const void *tx;
28 void *rx;
29
30 int subblock;
31 struct spi_pram __iomem *pram;
32 struct cpm_buf_desc __iomem *tx_bd;
33 struct cpm_buf_desc __iomem *rx_bd;
34
35 struct spi_transfer *xfer_in_progress;
36
37 /* dma addresses for CPM transfers */
38 dma_addr_t tx_dma;
39 dma_addr_t rx_dma;
40 bool map_tx_dma;
41 bool map_rx_dma;
42
43 dma_addr_t dma_dummy_tx;
44 dma_addr_t dma_dummy_rx;
45
46 /* functions to deal with different sized buffers */
47 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
48 u32(*get_tx) (struct mpc8xxx_spi *);
49
50 /* hooks for different controller driver */
51 void (*spi_do_one_msg) (struct spi_message *m);
52 void (*spi_remove) (struct mpc8xxx_spi *mspi);
53
54 unsigned int count;
55 unsigned int irq;
56
57 unsigned nsecs; /* (clock cycle time)/2 */
58
59 u32 spibrg; /* SPIBRG input clock */
60 u32 rx_shift; /* RX data reg shift when in qe mode */
61 u32 tx_shift; /* TX data reg shift when in qe mode */
62
63 unsigned int flags;
64
65 struct workqueue_struct *workqueue;
66 struct work_struct work;
67
68 struct list_head queue;
69 spinlock_t lock;
70
71 struct completion done;
72};
73
74struct spi_mpc8xxx_cs {
75 /* functions to deal with different sized buffers */
76 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
77 u32 (*get_tx) (struct mpc8xxx_spi *);
78 u32 rx_shift; /* RX data reg shift when in qe mode */
79 u32 tx_shift; /* TX data reg shift when in qe mode */
80 u32 hw_mode; /* Holds HW mode register settings */
81};
82
83static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
84{
85 out_be32(reg, val);
86}
87
88static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
89{
90 return in_be32(reg);
91}
92
93struct mpc8xxx_spi_probe_info {
94 struct fsl_spi_platform_data pdata;
95 int *gpios;
96 bool *alow_flags;
97};
98
99extern u32 mpc8xxx_spi_tx_buf_u8(struct mpc8xxx_spi *mpc8xxx_spi);
100extern u32 mpc8xxx_spi_tx_buf_u16(struct mpc8xxx_spi *mpc8xxx_spi);
101extern u32 mpc8xxx_spi_tx_buf_u32(struct mpc8xxx_spi *mpc8xxx_spi);
102extern void mpc8xxx_spi_rx_buf_u8(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
103extern void mpc8xxx_spi_rx_buf_u16(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
104extern void mpc8xxx_spi_rx_buf_u32(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
105
106extern struct mpc8xxx_spi_probe_info *to_of_pinfo(
107 struct fsl_spi_platform_data *pdata);
108extern int mpc8xxx_spi_bufs(struct mpc8xxx_spi *mspi,
109 struct spi_transfer *t, unsigned int len);
110extern int mpc8xxx_spi_transfer(struct spi_device *spi, struct spi_message *m);
111extern void mpc8xxx_spi_cleanup(struct spi_device *spi);
112extern const char *mpc8xxx_spi_strmode(unsigned int flags);
113extern int mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
114 unsigned int irq);
115extern int mpc8xxx_spi_remove(struct device *dev);
116extern int of_mpc8xxx_spi_probe(struct platform_device *ofdev,
117 const struct of_device_id *ofid);
118
119#endif /* __SPI_FSL_LIB_H__ */
diff --git a/drivers/spi/spi_fsl_spi.c b/drivers/spi/spi_fsl_spi.c
index 1dd86b835cd8..7ca52d3ae8f8 100644
--- a/drivers/spi/spi_fsl_spi.c
+++ b/drivers/spi/spi_fsl_spi.c
@@ -1,9 +1,10 @@
1/* 1/*
2 * MPC8xxx SPI controller driver. 2 * Freescale SPI controller driver.
3 * 3 *
4 * Maintainer: Kumar Gala 4 * Maintainer: Kumar Gala
5 * 5 *
6 * Copyright (C) 2006 Polycom, Inc. 6 * Copyright (C) 2006 Polycom, Inc.
7 * Copyright 2010 Freescale Semiconductor, Inc.
7 * 8 *
8 * CPM SPI and QE buffer descriptors mode support: 9 * CPM SPI and QE buffer descriptors mode support:
9 * Copyright (c) 2009 MontaVista Software, Inc. 10 * Copyright (c) 2009 MontaVista Software, Inc.
@@ -15,18 +16,11 @@
15 * option) any later version. 16 * option) any later version.
16 */ 17 */
17#include <linux/module.h> 18#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/types.h> 19#include <linux/types.h>
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/bug.h>
22#include <linux/errno.h>
23#include <linux/err.h>
24#include <linux/io.h>
25#include <linux/completion.h>
26#include <linux/interrupt.h> 21#include <linux/interrupt.h>
27#include <linux/delay.h> 22#include <linux/delay.h>
28#include <linux/irq.h> 23#include <linux/irq.h>
29#include <linux/device.h>
30#include <linux/spi/spi.h> 24#include <linux/spi/spi.h>
31#include <linux/spi/spi_bitbang.h> 25#include <linux/spi/spi_bitbang.h>
32#include <linux/platform_device.h> 26#include <linux/platform_device.h>
@@ -38,12 +32,12 @@
38#include <linux/of_platform.h> 32#include <linux/of_platform.h>
39#include <linux/gpio.h> 33#include <linux/gpio.h>
40#include <linux/of_gpio.h> 34#include <linux/of_gpio.h>
41#include <linux/slab.h>
42 35
43#include <sysdev/fsl_soc.h> 36#include <sysdev/fsl_soc.h>
44#include <asm/cpm.h> 37#include <asm/cpm.h>
45#include <asm/qe.h> 38#include <asm/qe.h>
46#include <asm/irq.h> 39
40#include "spi_fsl_lib.h"
47 41
48/* CPM1 and CPM2 are mutually exclusive. */ 42/* CPM1 and CPM2 are mutually exclusive. */
49#ifdef CONFIG_CPM1 43#ifdef CONFIG_CPM1
@@ -55,7 +49,7 @@
55#endif 49#endif
56 50
57/* SPI Controller registers */ 51/* SPI Controller registers */
58struct mpc8xxx_spi_reg { 52struct fsl_spi_reg {
59 u8 res1[0x20]; 53 u8 res1[0x20];
60 __be32 mode; 54 __be32 mode;
61 __be32 event; 55 __be32 event;
@@ -80,7 +74,7 @@ struct mpc8xxx_spi_reg {
80 74
81/* 75/*
82 * Default for SPI Mode: 76 * Default for SPI Mode:
83 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk 77 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
84 */ 78 */
85#define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \ 79#define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
86 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf)) 80 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
@@ -102,112 +96,16 @@ struct mpc8xxx_spi_reg {
102#define SPI_PRAM_SIZE 0x100 96#define SPI_PRAM_SIZE 0x100
103#define SPI_MRBLR ((unsigned int)PAGE_SIZE) 97#define SPI_MRBLR ((unsigned int)PAGE_SIZE)
104 98
105/* SPI Controller driver's private data. */ 99static void *fsl_dummy_rx;
106struct mpc8xxx_spi { 100static DEFINE_MUTEX(fsl_dummy_rx_lock);
107 struct device *dev; 101static int fsl_dummy_rx_refcnt;
108 struct mpc8xxx_spi_reg __iomem *base;
109
110 /* rx & tx bufs from the spi_transfer */
111 const void *tx;
112 void *rx;
113
114 int subblock;
115 struct spi_pram __iomem *pram;
116 struct cpm_buf_desc __iomem *tx_bd;
117 struct cpm_buf_desc __iomem *rx_bd;
118
119 struct spi_transfer *xfer_in_progress;
120
121 /* dma addresses for CPM transfers */
122 dma_addr_t tx_dma;
123 dma_addr_t rx_dma;
124 bool map_tx_dma;
125 bool map_rx_dma;
126
127 dma_addr_t dma_dummy_tx;
128 dma_addr_t dma_dummy_rx;
129
130 /* functions to deal with different sized buffers */
131 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
132 u32(*get_tx) (struct mpc8xxx_spi *);
133
134 unsigned int count;
135 unsigned int irq;
136
137 unsigned nsecs; /* (clock cycle time)/2 */
138
139 u32 spibrg; /* SPIBRG input clock */
140 u32 rx_shift; /* RX data reg shift when in qe mode */
141 u32 tx_shift; /* TX data reg shift when in qe mode */
142
143 unsigned int flags;
144
145 struct workqueue_struct *workqueue;
146 struct work_struct work;
147
148 struct list_head queue;
149 spinlock_t lock;
150
151 struct completion done;
152};
153
154static void *mpc8xxx_dummy_rx;
155static DEFINE_MUTEX(mpc8xxx_dummy_rx_lock);
156static int mpc8xxx_dummy_rx_refcnt;
157
158struct spi_mpc8xxx_cs {
159 /* functions to deal with different sized buffers */
160 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
161 u32 (*get_tx) (struct mpc8xxx_spi *);
162 u32 rx_shift; /* RX data reg shift when in qe mode */
163 u32 tx_shift; /* TX data reg shift when in qe mode */
164 u32 hw_mode; /* Holds HW mode register settings */
165};
166
167static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
168{
169 out_be32(reg, val);
170}
171
172static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
173{
174 return in_be32(reg);
175}
176
177#define MPC83XX_SPI_RX_BUF(type) \
178static \
179void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
180{ \
181 type *rx = mpc8xxx_spi->rx; \
182 *rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \
183 mpc8xxx_spi->rx = rx; \
184}
185
186#define MPC83XX_SPI_TX_BUF(type) \
187static \
188u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
189{ \
190 u32 data; \
191 const type *tx = mpc8xxx_spi->tx; \
192 if (!tx) \
193 return 0; \
194 data = *tx++ << mpc8xxx_spi->tx_shift; \
195 mpc8xxx_spi->tx = tx; \
196 return data; \
197}
198 102
199MPC83XX_SPI_RX_BUF(u8) 103static void fsl_spi_change_mode(struct spi_device *spi)
200MPC83XX_SPI_RX_BUF(u16)
201MPC83XX_SPI_RX_BUF(u32)
202MPC83XX_SPI_TX_BUF(u8)
203MPC83XX_SPI_TX_BUF(u16)
204MPC83XX_SPI_TX_BUF(u32)
205
206static void mpc8xxx_spi_change_mode(struct spi_device *spi)
207{ 104{
208 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); 105 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
209 struct spi_mpc8xxx_cs *cs = spi->controller_state; 106 struct spi_mpc8xxx_cs *cs = spi->controller_state;
210 __be32 __iomem *mode = &mspi->base->mode; 107 struct fsl_spi_reg *reg_base = mspi->reg_base;
108 __be32 __iomem *mode = &reg_base->mode;
211 unsigned long flags; 109 unsigned long flags;
212 110
213 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) 111 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
@@ -238,7 +136,7 @@ static void mpc8xxx_spi_change_mode(struct spi_device *spi)
238 local_irq_restore(flags); 136 local_irq_restore(flags);
239} 137}
240 138
241static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value) 139static void fsl_spi_chipselect(struct spi_device *spi, int value)
242{ 140{
243 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 141 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
244 struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data; 142 struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data;
@@ -256,18 +154,17 @@ static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value)
256 mpc8xxx_spi->get_rx = cs->get_rx; 154 mpc8xxx_spi->get_rx = cs->get_rx;
257 mpc8xxx_spi->get_tx = cs->get_tx; 155 mpc8xxx_spi->get_tx = cs->get_tx;
258 156
259 mpc8xxx_spi_change_mode(spi); 157 fsl_spi_change_mode(spi);
260 158
261 if (pdata->cs_control) 159 if (pdata->cs_control)
262 pdata->cs_control(spi, pol); 160 pdata->cs_control(spi, pol);
263 } 161 }
264} 162}
265 163
266static int 164static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
267mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs, 165 struct spi_device *spi,
268 struct spi_device *spi, 166 struct mpc8xxx_spi *mpc8xxx_spi,
269 struct mpc8xxx_spi *mpc8xxx_spi, 167 int bits_per_word)
270 int bits_per_word)
271{ 168{
272 cs->rx_shift = 0; 169 cs->rx_shift = 0;
273 cs->tx_shift = 0; 170 cs->tx_shift = 0;
@@ -307,10 +204,9 @@ mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
307 return bits_per_word; 204 return bits_per_word;
308} 205}
309 206
310static int 207static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
311mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs, 208 struct spi_device *spi,
312 struct spi_device *spi, 209 int bits_per_word)
313 int bits_per_word)
314{ 210{
315 /* QE uses Little Endian for words > 8 211 /* QE uses Little Endian for words > 8
316 * so transform all words > 8 into 8 bits 212 * so transform all words > 8 into 8 bits
@@ -326,13 +222,13 @@ mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
326 return bits_per_word; 222 return bits_per_word;
327} 223}
328 224
329static 225static int fsl_spi_setup_transfer(struct spi_device *spi,
330int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) 226 struct spi_transfer *t)
331{ 227{
332 struct mpc8xxx_spi *mpc8xxx_spi; 228 struct mpc8xxx_spi *mpc8xxx_spi;
333 int bits_per_word; 229 int bits_per_word = 0;
334 u8 pm; 230 u8 pm;
335 u32 hz; 231 u32 hz = 0;
336 struct spi_mpc8xxx_cs *cs = spi->controller_state; 232 struct spi_mpc8xxx_cs *cs = spi->controller_state;
337 233
338 mpc8xxx_spi = spi_master_get_devdata(spi->master); 234 mpc8xxx_spi = spi_master_get_devdata(spi->master);
@@ -340,9 +236,6 @@ int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
340 if (t) { 236 if (t) {
341 bits_per_word = t->bits_per_word; 237 bits_per_word = t->bits_per_word;
342 hz = t->speed_hz; 238 hz = t->speed_hz;
343 } else {
344 bits_per_word = 0;
345 hz = 0;
346 } 239 }
347 240
348 /* spi_transfer level calls that work per-word */ 241 /* spi_transfer level calls that work per-word */
@@ -388,23 +281,25 @@ int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
388 hz, mpc8xxx_spi->spibrg / 1024); 281 hz, mpc8xxx_spi->spibrg / 1024);
389 if (pm > 16) 282 if (pm > 16)
390 pm = 16; 283 pm = 16;
391 } else 284 } else {
392 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; 285 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
286 }
393 if (pm) 287 if (pm)
394 pm--; 288 pm--;
395 289
396 cs->hw_mode |= SPMODE_PM(pm); 290 cs->hw_mode |= SPMODE_PM(pm);
397 291
398 mpc8xxx_spi_change_mode(spi); 292 fsl_spi_change_mode(spi);
399 return 0; 293 return 0;
400} 294}
401 295
402static void mpc8xxx_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi) 296static void fsl_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi)
403{ 297{
404 struct cpm_buf_desc __iomem *tx_bd = mspi->tx_bd; 298 struct cpm_buf_desc __iomem *tx_bd = mspi->tx_bd;
405 struct cpm_buf_desc __iomem *rx_bd = mspi->rx_bd; 299 struct cpm_buf_desc __iomem *rx_bd = mspi->rx_bd;
406 unsigned int xfer_len = min(mspi->count, SPI_MRBLR); 300 unsigned int xfer_len = min(mspi->count, SPI_MRBLR);
407 unsigned int xfer_ofs; 301 unsigned int xfer_ofs;
302 struct fsl_spi_reg *reg_base = mspi->reg_base;
408 303
409 xfer_ofs = mspi->xfer_in_progress->len - mspi->count; 304 xfer_ofs = mspi->xfer_in_progress->len - mspi->count;
410 305
@@ -424,13 +319,14 @@ static void mpc8xxx_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi)
424 BD_SC_LAST); 319 BD_SC_LAST);
425 320
426 /* start transfer */ 321 /* start transfer */
427 mpc8xxx_spi_write_reg(&mspi->base->command, SPCOM_STR); 322 mpc8xxx_spi_write_reg(&reg_base->command, SPCOM_STR);
428} 323}
429 324
430static int mpc8xxx_spi_cpm_bufs(struct mpc8xxx_spi *mspi, 325static int fsl_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
431 struct spi_transfer *t, bool is_dma_mapped) 326 struct spi_transfer *t, bool is_dma_mapped)
432{ 327{
433 struct device *dev = mspi->dev; 328 struct device *dev = mspi->dev;
329 struct fsl_spi_reg *reg_base = mspi->reg_base;
434 330
435 if (is_dma_mapped) { 331 if (is_dma_mapped) {
436 mspi->map_tx_dma = 0; 332 mspi->map_tx_dma = 0;
@@ -475,13 +371,13 @@ static int mpc8xxx_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
475 } 371 }
476 372
477 /* enable rx ints */ 373 /* enable rx ints */
478 mpc8xxx_spi_write_reg(&mspi->base->mask, SPIE_RXB); 374 mpc8xxx_spi_write_reg(&reg_base->mask, SPIE_RXB);
479 375
480 mspi->xfer_in_progress = t; 376 mspi->xfer_in_progress = t;
481 mspi->count = t->len; 377 mspi->count = t->len;
482 378
483 /* start CPM transfers */ 379 /* start CPM transfers */
484 mpc8xxx_spi_cpm_bufs_start(mspi); 380 fsl_spi_cpm_bufs_start(mspi);
485 381
486 return 0; 382 return 0;
487 383
@@ -491,7 +387,7 @@ err_rx_dma:
491 return -ENOMEM; 387 return -ENOMEM;
492} 388}
493 389
494static void mpc8xxx_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi) 390static void fsl_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
495{ 391{
496 struct device *dev = mspi->dev; 392 struct device *dev = mspi->dev;
497 struct spi_transfer *t = mspi->xfer_in_progress; 393 struct spi_transfer *t = mspi->xfer_in_progress;
@@ -503,31 +399,34 @@ static void mpc8xxx_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
503 mspi->xfer_in_progress = NULL; 399 mspi->xfer_in_progress = NULL;
504} 400}
505 401
506static int mpc8xxx_spi_cpu_bufs(struct mpc8xxx_spi *mspi, 402static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
507 struct spi_transfer *t, unsigned int len) 403 struct spi_transfer *t, unsigned int len)
508{ 404{
509 u32 word; 405 u32 word;
406 struct fsl_spi_reg *reg_base = mspi->reg_base;
510 407
511 mspi->count = len; 408 mspi->count = len;
512 409
513 /* enable rx ints */ 410 /* enable rx ints */
514 mpc8xxx_spi_write_reg(&mspi->base->mask, SPIM_NE); 411 mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
515 412
516 /* transmit word */ 413 /* transmit word */
517 word = mspi->get_tx(mspi); 414 word = mspi->get_tx(mspi);
518 mpc8xxx_spi_write_reg(&mspi->base->transmit, word); 415 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
519 416
520 return 0; 417 return 0;
521} 418}
522 419
523static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t, 420static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
524 bool is_dma_mapped) 421 bool is_dma_mapped)
525{ 422{
526 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 423 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
424 struct fsl_spi_reg *reg_base;
527 unsigned int len = t->len; 425 unsigned int len = t->len;
528 u8 bits_per_word; 426 u8 bits_per_word;
529 int ret; 427 int ret;
530 428
429 reg_base = mpc8xxx_spi->reg_base;
531 bits_per_word = spi->bits_per_word; 430 bits_per_word = spi->bits_per_word;
532 if (t->bits_per_word) 431 if (t->bits_per_word)
533 bits_per_word = t->bits_per_word; 432 bits_per_word = t->bits_per_word;
@@ -551,24 +450,24 @@ static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
551 INIT_COMPLETION(mpc8xxx_spi->done); 450 INIT_COMPLETION(mpc8xxx_spi->done);
552 451
553 if (mpc8xxx_spi->flags & SPI_CPM_MODE) 452 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
554 ret = mpc8xxx_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped); 453 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
555 else 454 else
556 ret = mpc8xxx_spi_cpu_bufs(mpc8xxx_spi, t, len); 455 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
557 if (ret) 456 if (ret)
558 return ret; 457 return ret;
559 458
560 wait_for_completion(&mpc8xxx_spi->done); 459 wait_for_completion(&mpc8xxx_spi->done);
561 460
562 /* disable rx ints */ 461 /* disable rx ints */
563 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0); 462 mpc8xxx_spi_write_reg(&reg_base->mask, 0);
564 463
565 if (mpc8xxx_spi->flags & SPI_CPM_MODE) 464 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
566 mpc8xxx_spi_cpm_bufs_complete(mpc8xxx_spi); 465 fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
567 466
568 return mpc8xxx_spi->count; 467 return mpc8xxx_spi->count;
569} 468}
570 469
571static void mpc8xxx_spi_do_one_msg(struct spi_message *m) 470static void fsl_spi_do_one_msg(struct spi_message *m)
572{ 471{
573 struct spi_device *spi = m->spi; 472 struct spi_device *spi = m->spi;
574 struct spi_transfer *t; 473 struct spi_transfer *t;
@@ -584,18 +483,18 @@ static void mpc8xxx_spi_do_one_msg(struct spi_message *m)
584 status = -EINVAL; 483 status = -EINVAL;
585 484
586 if (cs_change) 485 if (cs_change)
587 status = mpc8xxx_spi_setup_transfer(spi, t); 486 status = fsl_spi_setup_transfer(spi, t);
588 if (status < 0) 487 if (status < 0)
589 break; 488 break;
590 } 489 }
591 490
592 if (cs_change) { 491 if (cs_change) {
593 mpc8xxx_spi_chipselect(spi, BITBANG_CS_ACTIVE); 492 fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
594 ndelay(nsecs); 493 ndelay(nsecs);
595 } 494 }
596 cs_change = t->cs_change; 495 cs_change = t->cs_change;
597 if (t->len) 496 if (t->len)
598 status = mpc8xxx_spi_bufs(spi, t, m->is_dma_mapped); 497 status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
599 if (status) { 498 if (status) {
600 status = -EMSGSIZE; 499 status = -EMSGSIZE;
601 break; 500 break;
@@ -607,7 +506,7 @@ static void mpc8xxx_spi_do_one_msg(struct spi_message *m)
607 506
608 if (cs_change) { 507 if (cs_change) {
609 ndelay(nsecs); 508 ndelay(nsecs);
610 mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE); 509 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
611 ndelay(nsecs); 510 ndelay(nsecs);
612 } 511 }
613 } 512 }
@@ -617,35 +516,16 @@ static void mpc8xxx_spi_do_one_msg(struct spi_message *m)
617 516
618 if (status || !cs_change) { 517 if (status || !cs_change) {
619 ndelay(nsecs); 518 ndelay(nsecs);
620 mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE); 519 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
621 } 520 }
622 521
623 mpc8xxx_spi_setup_transfer(spi, NULL); 522 fsl_spi_setup_transfer(spi, NULL);
624}
625
626static void mpc8xxx_spi_work(struct work_struct *work)
627{
628 struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
629 work);
630
631 spin_lock_irq(&mpc8xxx_spi->lock);
632 while (!list_empty(&mpc8xxx_spi->queue)) {
633 struct spi_message *m = container_of(mpc8xxx_spi->queue.next,
634 struct spi_message, queue);
635
636 list_del_init(&m->queue);
637 spin_unlock_irq(&mpc8xxx_spi->lock);
638
639 mpc8xxx_spi_do_one_msg(m);
640
641 spin_lock_irq(&mpc8xxx_spi->lock);
642 }
643 spin_unlock_irq(&mpc8xxx_spi->lock);
644} 523}
645 524
646static int mpc8xxx_spi_setup(struct spi_device *spi) 525static int fsl_spi_setup(struct spi_device *spi)
647{ 526{
648 struct mpc8xxx_spi *mpc8xxx_spi; 527 struct mpc8xxx_spi *mpc8xxx_spi;
528 struct fsl_spi_reg *reg_base;
649 int retval; 529 int retval;
650 u32 hw_mode; 530 u32 hw_mode;
651 struct spi_mpc8xxx_cs *cs = spi->controller_state; 531 struct spi_mpc8xxx_cs *cs = spi->controller_state;
@@ -661,8 +541,10 @@ static int mpc8xxx_spi_setup(struct spi_device *spi)
661 } 541 }
662 mpc8xxx_spi = spi_master_get_devdata(spi->master); 542 mpc8xxx_spi = spi_master_get_devdata(spi->master);
663 543
544 reg_base = mpc8xxx_spi->reg_base;
545
664 hw_mode = cs->hw_mode; /* Save original settings */ 546 hw_mode = cs->hw_mode; /* Save original settings */
665 cs->hw_mode = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode); 547 cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
666 /* mask out bits we are going to set */ 548 /* mask out bits we are going to set */
667 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH 549 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
668 | SPMODE_REV | SPMODE_LOOP); 550 | SPMODE_REV | SPMODE_LOOP);
@@ -676,7 +558,7 @@ static int mpc8xxx_spi_setup(struct spi_device *spi)
676 if (spi->mode & SPI_LOOP) 558 if (spi->mode & SPI_LOOP)
677 cs->hw_mode |= SPMODE_LOOP; 559 cs->hw_mode |= SPMODE_LOOP;
678 560
679 retval = mpc8xxx_spi_setup_transfer(spi, NULL); 561 retval = fsl_spi_setup_transfer(spi, NULL);
680 if (retval < 0) { 562 if (retval < 0) {
681 cs->hw_mode = hw_mode; /* Restore settings */ 563 cs->hw_mode = hw_mode; /* Restore settings */
682 return retval; 564 return retval;
@@ -684,9 +566,10 @@ static int mpc8xxx_spi_setup(struct spi_device *spi)
684 return 0; 566 return 0;
685} 567}
686 568
687static void mpc8xxx_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events) 569static void fsl_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events)
688{ 570{
689 u16 len; 571 u16 len;
572 struct fsl_spi_reg *reg_base = mspi->reg_base;
690 573
691 dev_dbg(mspi->dev, "%s: bd datlen %d, count %d\n", __func__, 574 dev_dbg(mspi->dev, "%s: bd datlen %d, count %d\n", __func__,
692 in_be16(&mspi->rx_bd->cbd_datlen), mspi->count); 575 in_be16(&mspi->rx_bd->cbd_datlen), mspi->count);
@@ -698,20 +581,22 @@ static void mpc8xxx_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events)
698 } 581 }
699 582
700 /* Clear the events */ 583 /* Clear the events */
701 mpc8xxx_spi_write_reg(&mspi->base->event, events); 584 mpc8xxx_spi_write_reg(&reg_base->event, events);
702 585
703 mspi->count -= len; 586 mspi->count -= len;
704 if (mspi->count) 587 if (mspi->count)
705 mpc8xxx_spi_cpm_bufs_start(mspi); 588 fsl_spi_cpm_bufs_start(mspi);
706 else 589 else
707 complete(&mspi->done); 590 complete(&mspi->done);
708} 591}
709 592
710static void mpc8xxx_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) 593static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
711{ 594{
595 struct fsl_spi_reg *reg_base = mspi->reg_base;
596
712 /* We need handle RX first */ 597 /* We need handle RX first */
713 if (events & SPIE_NE) { 598 if (events & SPIE_NE) {
714 u32 rx_data = mpc8xxx_spi_read_reg(&mspi->base->receive); 599 u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
715 600
716 if (mspi->rx) 601 if (mspi->rx)
717 mspi->get_rx(rx_data, mspi); 602 mspi->get_rx(rx_data, mspi);
@@ -720,102 +605,80 @@ static void mpc8xxx_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
720 if ((events & SPIE_NF) == 0) 605 if ((events & SPIE_NF) == 0)
721 /* spin until TX is done */ 606 /* spin until TX is done */
722 while (((events = 607 while (((events =
723 mpc8xxx_spi_read_reg(&mspi->base->event)) & 608 mpc8xxx_spi_read_reg(&reg_base->event)) &
724 SPIE_NF) == 0) 609 SPIE_NF) == 0)
725 cpu_relax(); 610 cpu_relax();
726 611
727 /* Clear the events */ 612 /* Clear the events */
728 mpc8xxx_spi_write_reg(&mspi->base->event, events); 613 mpc8xxx_spi_write_reg(&reg_base->event, events);
729 614
730 mspi->count -= 1; 615 mspi->count -= 1;
731 if (mspi->count) { 616 if (mspi->count) {
732 u32 word = mspi->get_tx(mspi); 617 u32 word = mspi->get_tx(mspi);
733 618
734 mpc8xxx_spi_write_reg(&mspi->base->transmit, word); 619 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
735 } else { 620 } else {
736 complete(&mspi->done); 621 complete(&mspi->done);
737 } 622 }
738} 623}
739 624
740static irqreturn_t mpc8xxx_spi_irq(s32 irq, void *context_data) 625static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
741{ 626{
742 struct mpc8xxx_spi *mspi = context_data; 627 struct mpc8xxx_spi *mspi = context_data;
743 irqreturn_t ret = IRQ_NONE; 628 irqreturn_t ret = IRQ_NONE;
744 u32 events; 629 u32 events;
630 struct fsl_spi_reg *reg_base = mspi->reg_base;
745 631
746 /* Get interrupt events(tx/rx) */ 632 /* Get interrupt events(tx/rx) */
747 events = mpc8xxx_spi_read_reg(&mspi->base->event); 633 events = mpc8xxx_spi_read_reg(&reg_base->event);
748 if (events) 634 if (events)
749 ret = IRQ_HANDLED; 635 ret = IRQ_HANDLED;
750 636
751 dev_dbg(mspi->dev, "%s: events %x\n", __func__, events); 637 dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
752 638
753 if (mspi->flags & SPI_CPM_MODE) 639 if (mspi->flags & SPI_CPM_MODE)
754 mpc8xxx_spi_cpm_irq(mspi, events); 640 fsl_spi_cpm_irq(mspi, events);
755 else 641 else
756 mpc8xxx_spi_cpu_irq(mspi, events); 642 fsl_spi_cpu_irq(mspi, events);
757 643
758 return ret; 644 return ret;
759} 645}
760 646
761static int mpc8xxx_spi_transfer(struct spi_device *spi, 647static void *fsl_spi_alloc_dummy_rx(void)
762 struct spi_message *m)
763{ 648{
764 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 649 mutex_lock(&fsl_dummy_rx_lock);
765 unsigned long flags;
766 650
767 m->actual_length = 0; 651 if (!fsl_dummy_rx)
768 m->status = -EINPROGRESS; 652 fsl_dummy_rx = kmalloc(SPI_MRBLR, GFP_KERNEL);
653 if (fsl_dummy_rx)
654 fsl_dummy_rx_refcnt++;
769 655
770 spin_lock_irqsave(&mpc8xxx_spi->lock, flags); 656 mutex_unlock(&fsl_dummy_rx_lock);
771 list_add_tail(&m->queue, &mpc8xxx_spi->queue);
772 queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work);
773 spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags);
774 657
775 return 0; 658 return fsl_dummy_rx;
776} 659}
777 660
778 661static void fsl_spi_free_dummy_rx(void)
779static void mpc8xxx_spi_cleanup(struct spi_device *spi)
780{ 662{
781 kfree(spi->controller_state); 663 mutex_lock(&fsl_dummy_rx_lock);
782}
783 664
784static void *mpc8xxx_spi_alloc_dummy_rx(void) 665 switch (fsl_dummy_rx_refcnt) {
785{
786 mutex_lock(&mpc8xxx_dummy_rx_lock);
787
788 if (!mpc8xxx_dummy_rx)
789 mpc8xxx_dummy_rx = kmalloc(SPI_MRBLR, GFP_KERNEL);
790 if (mpc8xxx_dummy_rx)
791 mpc8xxx_dummy_rx_refcnt++;
792
793 mutex_unlock(&mpc8xxx_dummy_rx_lock);
794
795 return mpc8xxx_dummy_rx;
796}
797
798static void mpc8xxx_spi_free_dummy_rx(void)
799{
800 mutex_lock(&mpc8xxx_dummy_rx_lock);
801
802 switch (mpc8xxx_dummy_rx_refcnt) {
803 case 0: 666 case 0:
804 WARN_ON(1); 667 WARN_ON(1);
805 break; 668 break;
806 case 1: 669 case 1:
807 kfree(mpc8xxx_dummy_rx); 670 kfree(fsl_dummy_rx);
808 mpc8xxx_dummy_rx = NULL; 671 fsl_dummy_rx = NULL;
809 /* fall through */ 672 /* fall through */
810 default: 673 default:
811 mpc8xxx_dummy_rx_refcnt--; 674 fsl_dummy_rx_refcnt--;
812 break; 675 break;
813 } 676 }
814 677
815 mutex_unlock(&mpc8xxx_dummy_rx_lock); 678 mutex_unlock(&fsl_dummy_rx_lock);
816} 679}
817 680
818static unsigned long mpc8xxx_spi_cpm_get_pram(struct mpc8xxx_spi *mspi) 681static unsigned long fsl_spi_cpm_get_pram(struct mpc8xxx_spi *mspi)
819{ 682{
820 struct device *dev = mspi->dev; 683 struct device *dev = mspi->dev;
821 struct device_node *np = dev->of_node; 684 struct device_node *np = dev->of_node;
@@ -869,7 +732,7 @@ static unsigned long mpc8xxx_spi_cpm_get_pram(struct mpc8xxx_spi *mspi)
869 return pram_ofs; 732 return pram_ofs;
870} 733}
871 734
872static int mpc8xxx_spi_cpm_init(struct mpc8xxx_spi *mspi) 735static int fsl_spi_cpm_init(struct mpc8xxx_spi *mspi)
873{ 736{
874 struct device *dev = mspi->dev; 737 struct device *dev = mspi->dev;
875 struct device_node *np = dev->of_node; 738 struct device_node *np = dev->of_node;
@@ -881,7 +744,7 @@ static int mpc8xxx_spi_cpm_init(struct mpc8xxx_spi *mspi)
881 if (!(mspi->flags & SPI_CPM_MODE)) 744 if (!(mspi->flags & SPI_CPM_MODE))
882 return 0; 745 return 0;
883 746
884 if (!mpc8xxx_spi_alloc_dummy_rx()) 747 if (!fsl_spi_alloc_dummy_rx())
885 return -ENOMEM; 748 return -ENOMEM;
886 749
887 if (mspi->flags & SPI_QE) { 750 if (mspi->flags & SPI_QE) {
@@ -902,7 +765,7 @@ static int mpc8xxx_spi_cpm_init(struct mpc8xxx_spi *mspi)
902 } 765 }
903 } 766 }
904 767
905 pram_ofs = mpc8xxx_spi_cpm_get_pram(mspi); 768 pram_ofs = fsl_spi_cpm_get_pram(mspi);
906 if (IS_ERR_VALUE(pram_ofs)) { 769 if (IS_ERR_VALUE(pram_ofs)) {
907 dev_err(dev, "can't allocate spi parameter ram\n"); 770 dev_err(dev, "can't allocate spi parameter ram\n");
908 goto err_pram; 771 goto err_pram;
@@ -922,7 +785,7 @@ static int mpc8xxx_spi_cpm_init(struct mpc8xxx_spi *mspi)
922 goto err_dummy_tx; 785 goto err_dummy_tx;
923 } 786 }
924 787
925 mspi->dma_dummy_rx = dma_map_single(dev, mpc8xxx_dummy_rx, SPI_MRBLR, 788 mspi->dma_dummy_rx = dma_map_single(dev, fsl_dummy_rx, SPI_MRBLR,
926 DMA_FROM_DEVICE); 789 DMA_FROM_DEVICE);
927 if (dma_mapping_error(dev, mspi->dma_dummy_rx)) { 790 if (dma_mapping_error(dev, mspi->dma_dummy_rx)) {
928 dev_err(dev, "unable to map dummy rx buffer\n"); 791 dev_err(dev, "unable to map dummy rx buffer\n");
@@ -960,11 +823,11 @@ err_dummy_tx:
960err_bds: 823err_bds:
961 cpm_muram_free(pram_ofs); 824 cpm_muram_free(pram_ofs);
962err_pram: 825err_pram:
963 mpc8xxx_spi_free_dummy_rx(); 826 fsl_spi_free_dummy_rx();
964 return -ENOMEM; 827 return -ENOMEM;
965} 828}
966 829
967static void mpc8xxx_spi_cpm_free(struct mpc8xxx_spi *mspi) 830static void fsl_spi_cpm_free(struct mpc8xxx_spi *mspi)
968{ 831{
969 struct device *dev = mspi->dev; 832 struct device *dev = mspi->dev;
970 833
@@ -972,30 +835,22 @@ static void mpc8xxx_spi_cpm_free(struct mpc8xxx_spi *mspi)
972 dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE); 835 dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
973 cpm_muram_free(cpm_muram_offset(mspi->tx_bd)); 836 cpm_muram_free(cpm_muram_offset(mspi->tx_bd));
974 cpm_muram_free(cpm_muram_offset(mspi->pram)); 837 cpm_muram_free(cpm_muram_offset(mspi->pram));
975 mpc8xxx_spi_free_dummy_rx(); 838 fsl_spi_free_dummy_rx();
976} 839}
977 840
978static const char *mpc8xxx_spi_strmode(unsigned int flags) 841static void fsl_spi_remove(struct mpc8xxx_spi *mspi)
979{ 842{
980 if (flags & SPI_QE_CPU_MODE) { 843 iounmap(mspi->reg_base);
981 return "QE CPU"; 844 fsl_spi_cpm_free(mspi);
982 } else if (flags & SPI_CPM_MODE) {
983 if (flags & SPI_QE)
984 return "QE";
985 else if (flags & SPI_CPM2)
986 return "CPM2";
987 else
988 return "CPM1";
989 }
990 return "CPU";
991} 845}
992 846
993static struct spi_master * __devinit 847static struct spi_master * __devinit fsl_spi_probe(struct device *dev,
994mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq) 848 struct resource *mem, unsigned int irq)
995{ 849{
996 struct fsl_spi_platform_data *pdata = dev->platform_data; 850 struct fsl_spi_platform_data *pdata = dev->platform_data;
997 struct spi_master *master; 851 struct spi_master *master;
998 struct mpc8xxx_spi *mpc8xxx_spi; 852 struct mpc8xxx_spi *mpc8xxx_spi;
853 struct fsl_spi_reg *reg_base;
999 u32 regval; 854 u32 regval;
1000 int ret = 0; 855 int ret = 0;
1001 856
@@ -1007,132 +862,77 @@ mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
1007 862
1008 dev_set_drvdata(dev, master); 863 dev_set_drvdata(dev, master);
1009 864
1010 /* the spi->mode bits understood by this driver: */ 865 ret = mpc8xxx_spi_probe(dev, mem, irq);
1011 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH 866 if (ret)
1012 | SPI_LSB_FIRST | SPI_LOOP; 867 goto err_probe;
1013 868
1014 master->setup = mpc8xxx_spi_setup; 869 master->setup = fsl_spi_setup;
1015 master->transfer = mpc8xxx_spi_transfer;
1016 master->cleanup = mpc8xxx_spi_cleanup;
1017 master->dev.of_node = dev->of_node;
1018 870
1019 mpc8xxx_spi = spi_master_get_devdata(master); 871 mpc8xxx_spi = spi_master_get_devdata(master);
1020 mpc8xxx_spi->dev = dev; 872 mpc8xxx_spi->spi_do_one_msg = fsl_spi_do_one_msg;
1021 mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8; 873 mpc8xxx_spi->spi_remove = fsl_spi_remove;
1022 mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8; 874
1023 mpc8xxx_spi->flags = pdata->flags;
1024 mpc8xxx_spi->spibrg = pdata->sysclk;
1025 875
1026 ret = mpc8xxx_spi_cpm_init(mpc8xxx_spi); 876 ret = fsl_spi_cpm_init(mpc8xxx_spi);
1027 if (ret) 877 if (ret)
1028 goto err_cpm_init; 878 goto err_cpm_init;
1029 879
1030 mpc8xxx_spi->rx_shift = 0;
1031 mpc8xxx_spi->tx_shift = 0;
1032 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) { 880 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
1033 mpc8xxx_spi->rx_shift = 16; 881 mpc8xxx_spi->rx_shift = 16;
1034 mpc8xxx_spi->tx_shift = 24; 882 mpc8xxx_spi->tx_shift = 24;
1035 } 883 }
1036 884
1037 init_completion(&mpc8xxx_spi->done); 885 mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
1038 886 if (mpc8xxx_spi->reg_base == NULL) {
1039 mpc8xxx_spi->base = ioremap(mem->start, resource_size(mem));
1040 if (mpc8xxx_spi->base == NULL) {
1041 ret = -ENOMEM; 887 ret = -ENOMEM;
1042 goto err_ioremap; 888 goto err_ioremap;
1043 } 889 }
1044 890
1045 mpc8xxx_spi->irq = irq;
1046
1047 /* Register for SPI Interrupt */ 891 /* Register for SPI Interrupt */
1048 ret = request_irq(mpc8xxx_spi->irq, mpc8xxx_spi_irq, 892 ret = request_irq(mpc8xxx_spi->irq, fsl_spi_irq,
1049 0, "mpc8xxx_spi", mpc8xxx_spi); 893 0, "fsl_spi", mpc8xxx_spi);
1050 894
1051 if (ret != 0) 895 if (ret != 0)
1052 goto unmap_io; 896 goto free_irq;
1053 897
1054 master->bus_num = pdata->bus_num; 898 reg_base = mpc8xxx_spi->reg_base;
1055 master->num_chipselect = pdata->max_chipselect;
1056 899
1057 /* SPI controller initializations */ 900 /* SPI controller initializations */
1058 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, 0); 901 mpc8xxx_spi_write_reg(&reg_base->mode, 0);
1059 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0); 902 mpc8xxx_spi_write_reg(&reg_base->mask, 0);
1060 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->command, 0); 903 mpc8xxx_spi_write_reg(&reg_base->command, 0);
1061 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, 0xffffffff); 904 mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
1062 905
1063 /* Enable SPI interface */ 906 /* Enable SPI interface */
1064 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; 907 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
1065 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) 908 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
1066 regval |= SPMODE_OP; 909 regval |= SPMODE_OP;
1067 910
1068 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, regval); 911 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
1069 spin_lock_init(&mpc8xxx_spi->lock);
1070 init_completion(&mpc8xxx_spi->done);
1071 INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work);
1072 INIT_LIST_HEAD(&mpc8xxx_spi->queue);
1073
1074 mpc8xxx_spi->workqueue = create_singlethread_workqueue(
1075 dev_name(master->dev.parent));
1076 if (mpc8xxx_spi->workqueue == NULL) {
1077 ret = -EBUSY;
1078 goto free_irq;
1079 }
1080 912
1081 ret = spi_register_master(master); 913 ret = spi_register_master(master);
1082 if (ret < 0) 914 if (ret < 0)
1083 goto unreg_master; 915 goto unreg_master;
1084 916
1085 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", mpc8xxx_spi->base, 917 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
1086 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags)); 918 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
1087 919
1088 return master; 920 return master;
1089 921
1090unreg_master: 922unreg_master:
1091 destroy_workqueue(mpc8xxx_spi->workqueue);
1092free_irq:
1093 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi); 923 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
1094unmap_io: 924free_irq:
1095 iounmap(mpc8xxx_spi->base); 925 iounmap(mpc8xxx_spi->reg_base);
1096err_ioremap: 926err_ioremap:
1097 mpc8xxx_spi_cpm_free(mpc8xxx_spi); 927 fsl_spi_cpm_free(mpc8xxx_spi);
1098err_cpm_init: 928err_cpm_init:
929err_probe:
1099 spi_master_put(master); 930 spi_master_put(master);
1100err: 931err:
1101 return ERR_PTR(ret); 932 return ERR_PTR(ret);
1102} 933}
1103 934
1104static int __devexit mpc8xxx_spi_remove(struct device *dev) 935static void fsl_spi_cs_control(struct spi_device *spi, bool on)
1105{
1106 struct mpc8xxx_spi *mpc8xxx_spi;
1107 struct spi_master *master;
1108
1109 master = dev_get_drvdata(dev);
1110 mpc8xxx_spi = spi_master_get_devdata(master);
1111
1112 flush_workqueue(mpc8xxx_spi->workqueue);
1113 destroy_workqueue(mpc8xxx_spi->workqueue);
1114 spi_unregister_master(master);
1115
1116 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
1117 iounmap(mpc8xxx_spi->base);
1118 mpc8xxx_spi_cpm_free(mpc8xxx_spi);
1119
1120 return 0;
1121}
1122
1123struct mpc8xxx_spi_probe_info {
1124 struct fsl_spi_platform_data pdata;
1125 int *gpios;
1126 bool *alow_flags;
1127};
1128
1129static struct mpc8xxx_spi_probe_info *
1130to_of_pinfo(struct fsl_spi_platform_data *pdata)
1131{
1132 return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
1133}
1134
1135static void mpc8xxx_spi_cs_control(struct spi_device *spi, bool on)
1136{ 936{
1137 struct device *dev = spi->dev.parent; 937 struct device *dev = spi->dev.parent;
1138 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data); 938 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data);
@@ -1143,7 +943,7 @@ static void mpc8xxx_spi_cs_control(struct spi_device *spi, bool on)
1143 gpio_set_value(gpio, on ^ alow); 943 gpio_set_value(gpio, on ^ alow);
1144} 944}
1145 945
1146static int of_mpc8xxx_spi_get_chipselects(struct device *dev) 946static int of_fsl_spi_get_chipselects(struct device *dev)
1147{ 947{
1148 struct device_node *np = dev->of_node; 948 struct device_node *np = dev->of_node;
1149 struct fsl_spi_platform_data *pdata = dev->platform_data; 949 struct fsl_spi_platform_data *pdata = dev->platform_data;
@@ -1204,7 +1004,7 @@ static int of_mpc8xxx_spi_get_chipselects(struct device *dev)
1204 } 1004 }
1205 1005
1206 pdata->max_chipselect = ngpios; 1006 pdata->max_chipselect = ngpios;
1207 pdata->cs_control = mpc8xxx_spi_cs_control; 1007 pdata->cs_control = fsl_spi_cs_control;
1208 1008
1209 return 0; 1009 return 0;
1210 1010
@@ -1223,7 +1023,7 @@ err_alloc_flags:
1223 return ret; 1023 return ret;
1224} 1024}
1225 1025
1226static int of_mpc8xxx_spi_free_chipselects(struct device *dev) 1026static int of_fsl_spi_free_chipselects(struct device *dev)
1227{ 1027{
1228 struct fsl_spi_platform_data *pdata = dev->platform_data; 1028 struct fsl_spi_platform_data *pdata = dev->platform_data;
1229 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); 1029 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
@@ -1242,50 +1042,21 @@ static int of_mpc8xxx_spi_free_chipselects(struct device *dev)
1242 return 0; 1042 return 0;
1243} 1043}
1244 1044
1245static int __devinit of_mpc8xxx_spi_probe(struct platform_device *ofdev, 1045static int __devinit of_fsl_spi_probe(struct platform_device *ofdev,
1246 const struct of_device_id *ofid) 1046 const struct of_device_id *ofid)
1247{ 1047{
1248 struct device *dev = &ofdev->dev; 1048 struct device *dev = &ofdev->dev;
1249 struct device_node *np = ofdev->dev.of_node; 1049 struct device_node *np = ofdev->dev.of_node;
1250 struct mpc8xxx_spi_probe_info *pinfo;
1251 struct fsl_spi_platform_data *pdata;
1252 struct spi_master *master; 1050 struct spi_master *master;
1253 struct resource mem; 1051 struct resource mem;
1254 struct resource irq; 1052 struct resource irq;
1255 const void *prop;
1256 int ret = -ENOMEM; 1053 int ret = -ENOMEM;
1257 1054
1258 pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL); 1055 ret = of_mpc8xxx_spi_probe(ofdev, ofid);
1259 if (!pinfo) 1056 if (ret)
1260 return -ENOMEM; 1057 return ret;
1261
1262 pdata = &pinfo->pdata;
1263 dev->platform_data = pdata;
1264
1265 /* Allocate bus num dynamically. */
1266 pdata->bus_num = -1;
1267
1268 /* SPI controller is either clocked from QE or SoC clock. */
1269 pdata->sysclk = get_brgfreq();
1270 if (pdata->sysclk == -1) {
1271 pdata->sysclk = fsl_get_sys_freq();
1272 if (pdata->sysclk == -1) {
1273 ret = -ENODEV;
1274 goto err_clk;
1275 }
1276 }
1277 1058
1278 prop = of_get_property(np, "mode", NULL); 1059 ret = of_fsl_spi_get_chipselects(dev);
1279 if (prop && !strcmp(prop, "cpu-qe"))
1280 pdata->flags = SPI_QE_CPU_MODE;
1281 else if (prop && !strcmp(prop, "qe"))
1282 pdata->flags = SPI_CPM_MODE | SPI_QE;
1283 else if (of_device_is_compatible(np, "fsl,cpm2-spi"))
1284 pdata->flags = SPI_CPM_MODE | SPI_CPM2;
1285 else if (of_device_is_compatible(np, "fsl,cpm1-spi"))
1286 pdata->flags = SPI_CPM_MODE | SPI_CPM1;
1287
1288 ret = of_mpc8xxx_spi_get_chipselects(dev);
1289 if (ret) 1060 if (ret)
1290 goto err; 1061 goto err;
1291 1062
@@ -1299,7 +1070,7 @@ static int __devinit of_mpc8xxx_spi_probe(struct platform_device *ofdev,
1299 goto err; 1070 goto err;
1300 } 1071 }
1301 1072
1302 master = mpc8xxx_spi_probe(dev, &mem, irq.start); 1073 master = fsl_spi_probe(dev, &mem, irq.start);
1303 if (IS_ERR(master)) { 1074 if (IS_ERR(master)) {
1304 ret = PTR_ERR(master); 1075 ret = PTR_ERR(master);
1305 goto err; 1076 goto err;
@@ -1308,42 +1079,40 @@ static int __devinit of_mpc8xxx_spi_probe(struct platform_device *ofdev,
1308 return 0; 1079 return 0;
1309 1080
1310err: 1081err:
1311 of_mpc8xxx_spi_free_chipselects(dev); 1082 of_fsl_spi_free_chipselects(dev);
1312err_clk:
1313 kfree(pinfo);
1314 return ret; 1083 return ret;
1315} 1084}
1316 1085
1317static int __devexit of_mpc8xxx_spi_remove(struct platform_device *ofdev) 1086static int __devexit of_fsl_spi_remove(struct platform_device *ofdev)
1318{ 1087{
1319 int ret; 1088 int ret;
1320 1089
1321 ret = mpc8xxx_spi_remove(&ofdev->dev); 1090 ret = mpc8xxx_spi_remove(&ofdev->dev);
1322 if (ret) 1091 if (ret)
1323 return ret; 1092 return ret;
1324 of_mpc8xxx_spi_free_chipselects(&ofdev->dev); 1093 of_fsl_spi_free_chipselects(&ofdev->dev);
1325 return 0; 1094 return 0;
1326} 1095}
1327 1096
1328static const struct of_device_id of_mpc8xxx_spi_match[] = { 1097static const struct of_device_id of_fsl_spi_match[] = {
1329 { .compatible = "fsl,spi" }, 1098 { .compatible = "fsl,spi" },
1330 {}, 1099 {}
1331}; 1100};
1332MODULE_DEVICE_TABLE(of, of_mpc8xxx_spi_match); 1101MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
1333 1102
1334static struct of_platform_driver of_mpc8xxx_spi_driver = { 1103static struct of_platform_driver of_fsl_spi_driver = {
1335 .driver = { 1104 .driver = {
1336 .name = "mpc8xxx_spi", 1105 .name = "fsl_spi",
1337 .owner = THIS_MODULE, 1106 .owner = THIS_MODULE,
1338 .of_match_table = of_mpc8xxx_spi_match, 1107 .of_match_table = of_fsl_spi_match,
1339 }, 1108 },
1340 .probe = of_mpc8xxx_spi_probe, 1109 .probe = of_fsl_spi_probe,
1341 .remove = __devexit_p(of_mpc8xxx_spi_remove), 1110 .remove = __devexit_p(of_fsl_spi_remove),
1342}; 1111};
1343 1112
1344#ifdef CONFIG_MPC832x_RDB 1113#ifdef CONFIG_MPC832x_RDB
1345/* 1114/*
1346 * XXX XXX XXX 1115 * XXX XXX XXX
1347 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards 1116 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
1348 * only. The driver should go away soon, since newer MPC8323E-RDB's device 1117 * only. The driver should go away soon, since newer MPC8323E-RDB's device
1349 * tree can work with OpenFirmware driver. But for now we support old trees 1118 * tree can work with OpenFirmware driver. But for now we support old trees
@@ -1366,7 +1135,7 @@ static int __devinit plat_mpc8xxx_spi_probe(struct platform_device *pdev)
1366 if (irq <= 0) 1135 if (irq <= 0)
1367 return -EINVAL; 1136 return -EINVAL;
1368 1137
1369 master = mpc8xxx_spi_probe(&pdev->dev, mem, irq); 1138 master = fsl_spi_probe(&pdev->dev, mem, irq);
1370 if (IS_ERR(master)) 1139 if (IS_ERR(master))
1371 return PTR_ERR(master); 1140 return PTR_ERR(master);
1372 return 0; 1141 return 0;
@@ -1405,21 +1174,20 @@ static void __init legacy_driver_register(void) {}
1405static void __exit legacy_driver_unregister(void) {} 1174static void __exit legacy_driver_unregister(void) {}
1406#endif /* CONFIG_MPC832x_RDB */ 1175#endif /* CONFIG_MPC832x_RDB */
1407 1176
1408static int __init mpc8xxx_spi_init(void) 1177static int __init fsl_spi_init(void)
1409{ 1178{
1410 legacy_driver_register(); 1179 legacy_driver_register();
1411 return of_register_platform_driver(&of_mpc8xxx_spi_driver); 1180 return of_register_platform_driver(&of_fsl_spi_driver);
1412} 1181}
1182module_init(fsl_spi_init);
1413 1183
1414static void __exit mpc8xxx_spi_exit(void) 1184static void __exit fsl_spi_exit(void)
1415{ 1185{
1416 of_unregister_platform_driver(&of_mpc8xxx_spi_driver); 1186 of_unregister_platform_driver(&of_fsl_spi_driver);
1417 legacy_driver_unregister(); 1187 legacy_driver_unregister();
1418} 1188}
1419 1189module_exit(fsl_spi_exit);
1420module_init(mpc8xxx_spi_init);
1421module_exit(mpc8xxx_spi_exit);
1422 1190
1423MODULE_AUTHOR("Kumar Gala"); 1191MODULE_AUTHOR("Kumar Gala");
1424MODULE_DESCRIPTION("Simple MPC8xxx SPI Driver"); 1192MODULE_DESCRIPTION("Simple Freescale SPI Driver");
1425MODULE_LICENSE("GPL"); 1193MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-29 04:39:15 -0500