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authorLinus Torvalds <torvalds@linux-foundation.org>2010-05-21 13:50:00 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-05-21 13:50:00 -0400
commita6f039869ff87e0a8d621e31d14bbb120c1dfa93 (patch)
treec8975a8d02893633d03efe5435aa8b0635298a93
parente0bc5d4a54938eedcde14005210e6c08aa9727e4 (diff)
parentf6304f5804f228b6c2fea9e3dfac25c5b2db9b38 (diff)
Merge branch 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
* 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (113 commits) omap4: Add support for i2c init omap: Fix i2c platform init code for omap4 OMAP2 clock: fix recursive spinlock attempt when CONFIG_CPU_FREQ=y OMAP powerdomain, hwmod, omap_device: add some credits OMAP4 powerdomain: Support LOWPOWERSTATECHANGE for powerdomains OMAP3 clock: add support for setting the divider for sys_clkout2 using clk_set_rate OMAP4 powerdomain: Fix pwrsts flags for ALWAYS ON domains OMAP: timers: Fix clock source names for OMAP4 OMAP4 clock: Support clk_set_parent OMAP4: PRCM: Add offset defines for all CM registers OMAP4: PRCM: Add offset defines for all PRM registers OMAP4: PRCM: Remove duplicate definition of base addresses OMAP4: PRM: Remove MPU internal code name and apply PRCM naming convention OMAP4: CM: Remove non-functional registers in ES1.0 OMAP: hwmod: Replace WARN by pr_warning for clockdomain check OMAP: hwmod: Rename hwmod name for the MPU OMAP: hwmod: Do not exit the iteration if one clock init failed OMAP: hwmod: Replace WARN by pr_warning if clock lookup failed OMAP: hwmod: Remove IS_ERR check with omap_clk_get_by_name return value OMAP: hwmod: Fix wrong pointer iteration in oh->slaves ...
Diffstat
-rw-r--r--arch/arm/configs/am3517_evm_defconfig92
-rw-r--r--arch/arm/configs/ams_delta_defconfig10
-rw-r--r--arch/arm/configs/devkit8000_defconfig157
-rw-r--r--arch/arm/configs/omap3_defconfig151
-rw-r--r--arch/arm/configs/omap3_stalker_lks_defconfig1691
-rw-r--r--arch/arm/configs/omap_4430sdp_defconfig448
-rw-r--r--arch/arm/mach-omap1/Kconfig10
-rw-r--r--arch/arm/mach-omap1/Makefile1
-rw-r--r--arch/arm/mach-omap1/ams-delta-fiq-handler.S278
-rw-r--r--arch/arm/mach-omap1/ams-delta-fiq.c155
-rw-r--r--arch/arm/mach-omap1/board-ams-delta.c18
-rw-r--r--arch/arm/mach-omap1/clock.c2
-rw-r--r--arch/arm/mach-omap1/clock.h2
-rw-r--r--arch/arm/mach-omap1/include/mach/ams-delta-fiq.h79
-rw-r--r--arch/arm/mach-omap1/include/mach/debug-macro.S21
-rw-r--r--arch/arm/mach-omap2/Kconfig7
-rw-r--r--arch/arm/mach-omap2/Makefile12
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c21
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c1
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c360
-rw-r--r--arch/arm/mach-omap2/board-am3517evm.c166
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c1
-rw-r--r--arch/arm/mach-omap2/board-devkit8000.c155
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c6
-rw-r--r--arch/arm/mach-omap2/board-omap3stalker.c672
-rw-r--r--arch/arm/mach-omap2/board-overo.c14
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c92
-rw-r--r--arch/arm/mach-omap2/board-zoom-debugboard.c2
-rw-r--r--arch/arm/mach-omap2/board-zoom2.c4
-rw-r--r--arch/arm/mach-omap2/board-zoom3.c4
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_apll.c4
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c17
-rw-r--r--arch/arm/mach-omap2/clkt_clksel.c472
-rw-r--r--arch/arm/mach-omap2/clock.c9
-rw-r--r--arch/arm/mach-omap2/clock.h11
-rw-r--r--arch/arm/mach-omap2/clock2420_data.c50
-rw-r--r--arch/arm/mach-omap2/clock2430_data.c54
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c412
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c5
-rw-r--r--arch/arm/mach-omap2/clock_common_data.c12
-rw-r--r--arch/arm/mach-omap2/clockdomain.c4
-rw-r--r--arch/arm/mach-omap2/clockdomains44xx.h4
-rw-r--r--arch/arm/mach-omap2/cm-regbits-24xx.h236
-rw-r--r--arch/arm/mach-omap2/cm-regbits-34xx.h222
-rw-r--r--arch/arm/mach-omap2/cm.c3
-rw-r--r--arch/arm/mach-omap2/cm.h16
-rw-r--r--arch/arm/mach-omap2/cm44xx.h301
-rw-r--r--arch/arm/mach-omap2/cm4xxx.c54
-rw-r--r--arch/arm/mach-omap2/control.c7
-rw-r--r--arch/arm/mach-omap2/devices.c37
-rw-r--r--arch/arm/mach-omap2/hsmmc.c120
-rw-r--r--arch/arm/mach-omap2/include/mach/am35xx.h20
-rw-r--r--arch/arm/mach-omap2/include/mach/debug-macro.S15
-rw-r--r--arch/arm/mach-omap2/include/mach/omap4-common.h26
-rw-r--r--arch/arm/mach-omap2/io.c9
-rw-r--r--arch/arm/mach-omap2/iommu2.c6
-rw-r--r--arch/arm/mach-omap2/mux34xx.c86
-rw-r--r--arch/arm/mach-omap2/omap-iommu.c157
-rw-r--r--arch/arm/mach-omap2/omap-smp.c2
-rw-r--r--arch/arm/mach-omap2/omap3-iommu.c105
-rw-r--r--arch/arm/mach-omap2/omap4-common.c72
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c121
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c2
-rw-r--r--arch/arm/mach-omap2/pm-debug.c3
-rw-r--r--arch/arm/mach-omap2/pm.h1
-rw-r--r--arch/arm/mach-omap2/pm24xx.c130
-rw-r--r--arch/arm/mach-omap2/pm34xx.c259
-rw-r--r--arch/arm/mach-omap2/powerdomain.c56
-rw-r--r--arch/arm/mach-omap2/powerdomains44xx.h23
-rw-r--r--arch/arm/mach-omap2/prcm-common.h164
-rw-r--r--arch/arm/mach-omap2/prcm.c4
-rw-r--r--arch/arm/mach-omap2/prm-regbits-24xx.h120
-rw-r--r--arch/arm/mach-omap2/prm-regbits-34xx.h360
-rw-r--r--arch/arm/mach-omap2/prm.h22
-rw-r--r--arch/arm/mach-omap2/prm44xx.h389
-rw-r--r--arch/arm/plat-omap/Kconfig9
-rw-r--r--arch/arm/plat-omap/clock.c25
-rw-r--r--arch/arm/plat-omap/common.c3
-rw-r--r--arch/arm/plat-omap/dma.c45
-rw-r--r--arch/arm/plat-omap/dmtimer.c4
-rw-r--r--arch/arm/plat-omap/gpio.c236
-rw-r--r--arch/arm/plat-omap/i2c.c98
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h14
-rw-r--r--arch/arm/plat-omap/include/plat/common.h3
-rw-r--r--arch/arm/plat-omap/include/plat/control.h20
-rw-r--r--arch/arm/plat-omap/include/plat/gpio.h4
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h4
-rw-r--r--arch/arm/plat-omap/include/plat/mmc.h4
-rw-r--r--arch/arm/plat-omap/include/plat/multi.h16
-rw-r--r--arch/arm/plat-omap/include/plat/omap44xx.h4
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h16
-rw-r--r--arch/arm/plat-omap/include/plat/powerdomain.h7
-rw-r--r--arch/arm/plat-omap/include/plat/serial.h16
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h44
-rw-r--r--arch/arm/plat-omap/iommu.c101
-rw-r--r--arch/arm/plat-omap/iovmm.c9
-rw-r--r--arch/arm/plat-omap/omap_device.c4
-rw-r--r--arch/arm/plat-omap/sram.c16
-rw-r--r--drivers/input/serio/Kconfig16
-rw-r--r--drivers/input/serio/Makefile1
-rw-r--r--drivers/input/serio/ams_delta_serio.c177
-rw-r--r--drivers/spi/Kconfig6
104 files changed, 7514 insertions, 2226 deletions
diff --git a/arch/arm/configs/am3517_evm_defconfig b/arch/arm/configs/am3517_evm_defconfig
index 66a10b50d938..232f8eeb72e3 100644
--- a/arch/arm/configs/am3517_evm_defconfig
+++ b/arch/arm/configs/am3517_evm_defconfig
@@ -422,15 +422,29 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
422# 422#
423# CONFIG_NET_PKTGEN is not set 423# CONFIG_NET_PKTGEN is not set
424# CONFIG_HAMRADIO is not set 424# CONFIG_HAMRADIO is not set
425# CONFIG_CAN is not set 425CONFIG_CAN=y
426CONFIG_CAN_RAW=y
427CONFIG_CAN_BCM=y
428
429#
430# CAN Device Drivers
431#
432CONFIG_CAN_VCAN=y
433CONFIG_CAN_DEV=y
434CONFIG_CAN_CALC_BITTIMING=y
435CONFIG_CAN_TI_HECC=y
436# CONFIG_CAN_SJA1000 is not set
437
438#
439# CAN USB interfaces
440#
441# CONFIG_CAN_EMS_USB is not set
442CONFIG_CAN_DEBUG_DEVICES=y
426# CONFIG_IRDA is not set 443# CONFIG_IRDA is not set
427# CONFIG_BT is not set 444# CONFIG_BT is not set
428# CONFIG_AF_RXRPC is not set 445# CONFIG_AF_RXRPC is not set
429CONFIG_WIRELESS=y 446CONFIG_WIRELESS=y
430# CONFIG_CFG80211 is not set 447# CONFIG_CFG80211 is not set
431CONFIG_CFG80211_DEFAULT_PS_VALUE=0
432# CONFIG_WIRELESS_OLD_REGULATORY is not set
433# CONFIG_WIRELESS_EXT is not set
434# CONFIG_LIB80211 is not set 448# CONFIG_LIB80211 is not set
435 449
436# 450#
@@ -517,7 +531,75 @@ CONFIG_SCSI_LOWLEVEL=y
517# CONFIG_SCSI_OSD_INITIATOR is not set 531# CONFIG_SCSI_OSD_INITIATOR is not set
518# CONFIG_ATA is not set 532# CONFIG_ATA is not set
519# CONFIG_MD is not set 533# CONFIG_MD is not set
520# CONFIG_NETDEVICES is not set 534CONFIG_NETDEVICES=y
535# CONFIG_DUMMY is not set
536# CONFIG_BONDING is not set
537# CONFIG_MACVLAN is not set
538# CONFIG_EQUALIZER is not set
539# CONFIG_TUN is not set
540# CONFIG_VETH is not set
541CONFIG_PHYLIB=y
542
543#
544# MII PHY device drivers
545#
546# CONFIG_MARVELL_PHY is not set
547# CONFIG_DAVICOM_PHY is not set
548# CONFIG_QSEMI_PHY is not set
549# CONFIG_LXT_PHY is not set
550# CONFIG_CICADA_PHY is not set
551# CONFIG_VITESSE_PHY is not set
552# CONFIG_SMSC_PHY is not set
553# CONFIG_BROADCOM_PHY is not set
554# CONFIG_ICPLUS_PHY is not set
555# CONFIG_REALTEK_PHY is not set
556# CONFIG_NATIONAL_PHY is not set
557# CONFIG_STE10XP is not set
558# CONFIG_LSI_ET1011C_PHY is not set
559# CONFIG_FIXED_PHY is not set
560# CONFIG_MDIO_BITBANG is not set
561CONFIG_NET_ETHERNET=y
562# CONFIG_MII is not set
563# CONFIG_AX88796 is not set
564# CONFIG_SMC91X is not set
565CONFIG_TI_DAVINCI_EMAC=y
566# CONFIG_DM9000 is not set
567# CONFIG_ETHOC is not set
568# CONFIG_SMC911X is not set
569# CONFIG_SMSC911X is not set
570# CONFIG_DNET is not set
571# CONFIG_IBM_NEW_EMAC_ZMII is not set
572# CONFIG_IBM_NEW_EMAC_RGMII is not set
573# CONFIG_IBM_NEW_EMAC_TAH is not set
574# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
575# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
576# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
577# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
578# CONFIG_B44 is not set
579# CONFIG_KS8842 is not set
580# CONFIG_KS8851_MLL is not set
581# CONFIG_NETDEV_1000 is not set
582# CONFIG_NETDEV_10000 is not set
583# CONFIG_WLAN is not set
584
585#
586# Enable WiMAX (Networking options) to see the WiMAX drivers
587#
588
589#
590# USB Network Adapters
591#
592# CONFIG_USB_CATC is not set
593# CONFIG_USB_KAWETH is not set
594# CONFIG_USB_PEGASUS is not set
595# CONFIG_USB_RTL8150 is not set
596# CONFIG_USB_USBNET is not set
597# CONFIG_WAN is not set
598# CONFIG_PPP is not set
599# CONFIG_SLIP is not set
600# CONFIG_NETCONSOLE is not set
601# CONFIG_NETPOLL is not set
602# CONFIG_NET_POLL_CONTROLLER is not set
521# CONFIG_ISDN is not set 603# CONFIG_ISDN is not set
522# CONFIG_PHONE is not set 604# CONFIG_PHONE is not set
523 605
diff --git a/arch/arm/configs/ams_delta_defconfig b/arch/arm/configs/ams_delta_defconfig
index 3b3a3775bbf4..6d8a0c891f80 100644
--- a/arch/arm/configs/ams_delta_defconfig
+++ b/arch/arm/configs/ams_delta_defconfig
@@ -47,6 +47,7 @@ CONFIG_SYSVIPC_SYSCTL=y
47# CONFIG_TASKSTATS is not set 47# CONFIG_TASKSTATS is not set
48# CONFIG_UTS_NS is not set 48# CONFIG_UTS_NS is not set
49# CONFIG_AUDIT is not set 49# CONFIG_AUDIT is not set
50CONFIG_TREE_PREEMPT_RCU=y
50# CONFIG_IKCONFIG is not set 51# CONFIG_IKCONFIG is not set
51CONFIG_LOG_BUF_SHIFT=14 52CONFIG_LOG_BUF_SHIFT=14
52CONFIG_SYSFS_DEPRECATED=y 53CONFIG_SYSFS_DEPRECATED=y
@@ -95,9 +96,8 @@ CONFIG_KMOD=y
95# Block layer 96# Block layer
96# 97#
97CONFIG_BLOCK=y 98CONFIG_BLOCK=y
98# CONFIG_LBD is not set 99# CONFIG_LBDAF is not set
99# CONFIG_BLK_DEV_IO_TRACE is not set 100# CONFIG_BLK_DEV_IO_TRACE is not set
100# CONFIG_LSF is not set
101 101
102# 102#
103# IO Schedulers 103# IO Schedulers
@@ -699,6 +699,7 @@ CONFIG_SERIO=y
699CONFIG_SERIO_SERPORT=y 699CONFIG_SERIO_SERPORT=y
700CONFIG_SERIO_LIBPS2=y 700CONFIG_SERIO_LIBPS2=y
701# CONFIG_SERIO_RAW is not set 701# CONFIG_SERIO_RAW is not set
702CONFIG_SERIO_AMS_DELTA=y
702# CONFIG_GAMEPORT is not set 703# CONFIG_GAMEPORT is not set
703 704
704# 705#
@@ -835,7 +836,8 @@ CONFIG_DAB=y
835# 836#
836# Graphics support 837# Graphics support
837# 838#
838# CONFIG_BACKLIGHT_LCD_SUPPORT is not set 839CONFIG_BACKLIGHT_LCD_SUPPORT=y
840CONFIG_LCD_CLASS_DEVICE=y
839 841
840# 842#
841# Display device support 843# Display device support
@@ -1283,7 +1285,7 @@ CONFIG_DEBUG_PREEMPT=y
1283# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1285# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1284# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1286# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1285# CONFIG_DEBUG_KOBJECT is not set 1287# CONFIG_DEBUG_KOBJECT is not set
1286CONFIG_DEBUG_BUGVERBOSE=y 1288# CONFIG_DEBUG_BUGVERBOSE is not set
1287# CONFIG_DEBUG_INFO is not set 1289# CONFIG_DEBUG_INFO is not set
1288# CONFIG_DEBUG_VM is not set 1290# CONFIG_DEBUG_VM is not set
1289# CONFIG_DEBUG_LIST is not set 1291# CONFIG_DEBUG_LIST is not set
diff --git a/arch/arm/configs/devkit8000_defconfig b/arch/arm/configs/devkit8000_defconfig
index 61a817e8cf81..c7a68202fa3f 100644
--- a/arch/arm/configs/devkit8000_defconfig
+++ b/arch/arm/configs/devkit8000_defconfig
@@ -1,13 +1,14 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.33-rc6 3# Linux kernel version: 2.6.34-rc2
4# Thu Feb 4 15:42:56 2010 4# Wed Mar 24 13:27:25 2010
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y 7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y 8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y 9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y 10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_HAVE_PROC_CPU=y
11CONFIG_GENERIC_HARDIRQS=y 12CONFIG_GENERIC_HARDIRQS=y
12CONFIG_STACKTRACE_SUPPORT=y 13CONFIG_STACKTRACE_SUPPORT=y
13CONFIG_HAVE_LATENCYTOP_SUPPORT=y 14CONFIG_HAVE_LATENCYTOP_SUPPORT=y
@@ -19,7 +20,9 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
19CONFIG_ARCH_HAS_CPUFREQ=y 20CONFIG_ARCH_HAS_CPUFREQ=y
20CONFIG_GENERIC_HWEIGHT=y 21CONFIG_GENERIC_HWEIGHT=y
21CONFIG_GENERIC_CALIBRATE_DELAY=y 22CONFIG_GENERIC_CALIBRATE_DELAY=y
23CONFIG_NEED_DMA_MAP_STATE=y
22CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y 24CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
25CONFIG_ARM_L1_CACHE_SHIFT_6=y
23CONFIG_VECTORS_BASE=0xffff0000 26CONFIG_VECTORS_BASE=0xffff0000
24CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 27CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
25CONFIG_CONSTRUCTORS=y 28CONFIG_CONSTRUCTORS=y
@@ -60,11 +63,6 @@ CONFIG_RCU_FANOUT=32
60CONFIG_IKCONFIG=y 63CONFIG_IKCONFIG=y
61CONFIG_IKCONFIG_PROC=y 64CONFIG_IKCONFIG_PROC=y
62CONFIG_LOG_BUF_SHIFT=14 65CONFIG_LOG_BUF_SHIFT=14
63CONFIG_GROUP_SCHED=y
64CONFIG_FAIR_GROUP_SCHED=y
65# CONFIG_RT_GROUP_SCHED is not set
66CONFIG_USER_SCHED=y
67# CONFIG_CGROUP_SCHED is not set
68# CONFIG_CGROUPS is not set 66# CONFIG_CGROUPS is not set
69# CONFIG_SYSFS_DEPRECATED_V2 is not set 67# CONFIG_SYSFS_DEPRECATED_V2 is not set
70# CONFIG_RELAY is not set 68# CONFIG_RELAY is not set
@@ -96,10 +94,14 @@ CONFIG_TIMERFD=y
96CONFIG_EVENTFD=y 94CONFIG_EVENTFD=y
97CONFIG_SHMEM=y 95CONFIG_SHMEM=y
98CONFIG_AIO=y 96CONFIG_AIO=y
97CONFIG_HAVE_PERF_EVENTS=y
98CONFIG_PERF_USE_VMALLOC=y
99 99
100# 100#
101# Kernel Performance Events And Counters 101# Kernel Performance Events And Counters
102# 102#
103# CONFIG_PERF_EVENTS is not set
104# CONFIG_PERF_COUNTERS is not set
103CONFIG_VM_EVENT_COUNTERS=y 105CONFIG_VM_EVENT_COUNTERS=y
104CONFIG_COMPAT_BRK=y 106CONFIG_COMPAT_BRK=y
105CONFIG_SLAB=y 107CONFIG_SLAB=y
@@ -170,7 +172,7 @@ CONFIG_INLINE_WRITE_UNLOCK=y
170CONFIG_INLINE_WRITE_UNLOCK_IRQ=y 172CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
171# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set 173# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
172# CONFIG_MUTEX_SPIN_ON_OWNER is not set 174# CONFIG_MUTEX_SPIN_ON_OWNER is not set
173# CONFIG_FREEZER is not set 175CONFIG_FREEZER=y
174 176
175# 177#
176# System Type 178# System Type
@@ -181,6 +183,7 @@ CONFIG_MMU=y
181# CONFIG_ARCH_REALVIEW is not set 183# CONFIG_ARCH_REALVIEW is not set
182# CONFIG_ARCH_VERSATILE is not set 184# CONFIG_ARCH_VERSATILE is not set
183# CONFIG_ARCH_AT91 is not set 185# CONFIG_ARCH_AT91 is not set
186# CONFIG_ARCH_BCMRING is not set
184# CONFIG_ARCH_CLPS711X is not set 187# CONFIG_ARCH_CLPS711X is not set
185# CONFIG_ARCH_GEMINI is not set 188# CONFIG_ARCH_GEMINI is not set
186# CONFIG_ARCH_EBSA110 is not set 189# CONFIG_ARCH_EBSA110 is not set
@@ -190,7 +193,6 @@ CONFIG_MMU=y
190# CONFIG_ARCH_STMP3XXX is not set 193# CONFIG_ARCH_STMP3XXX is not set
191# CONFIG_ARCH_NETX is not set 194# CONFIG_ARCH_NETX is not set
192# CONFIG_ARCH_H720X is not set 195# CONFIG_ARCH_H720X is not set
193# CONFIG_ARCH_NOMADIK is not set
194# CONFIG_ARCH_IOP13XX is not set 196# CONFIG_ARCH_IOP13XX is not set
195# CONFIG_ARCH_IOP32X is not set 197# CONFIG_ARCH_IOP32X is not set
196# CONFIG_ARCH_IOP33X is not set 198# CONFIG_ARCH_IOP33X is not set
@@ -207,21 +209,26 @@ CONFIG_MMU=y
207# CONFIG_ARCH_KS8695 is not set 209# CONFIG_ARCH_KS8695 is not set
208# CONFIG_ARCH_NS9XXX is not set 210# CONFIG_ARCH_NS9XXX is not set
209# CONFIG_ARCH_W90X900 is not set 211# CONFIG_ARCH_W90X900 is not set
212# CONFIG_ARCH_NUC93X is not set
210# CONFIG_ARCH_PNX4008 is not set 213# CONFIG_ARCH_PNX4008 is not set
211# CONFIG_ARCH_PXA is not set 214# CONFIG_ARCH_PXA is not set
212# CONFIG_ARCH_MSM is not set 215# CONFIG_ARCH_MSM is not set
216# CONFIG_ARCH_SHMOBILE is not set
213# CONFIG_ARCH_RPC is not set 217# CONFIG_ARCH_RPC is not set
214# CONFIG_ARCH_SA1100 is not set 218# CONFIG_ARCH_SA1100 is not set
215# CONFIG_ARCH_S3C2410 is not set 219# CONFIG_ARCH_S3C2410 is not set
216# CONFIG_ARCH_S3C64XX is not set 220# CONFIG_ARCH_S3C64XX is not set
221# CONFIG_ARCH_S5P6440 is not set
222# CONFIG_ARCH_S5P6442 is not set
217# CONFIG_ARCH_S5PC1XX is not set 223# CONFIG_ARCH_S5PC1XX is not set
224# CONFIG_ARCH_S5PV210 is not set
218# CONFIG_ARCH_SHARK is not set 225# CONFIG_ARCH_SHARK is not set
219# CONFIG_ARCH_LH7A40X is not set 226# CONFIG_ARCH_LH7A40X is not set
220# CONFIG_ARCH_U300 is not set 227# CONFIG_ARCH_U300 is not set
228# CONFIG_ARCH_U8500 is not set
229# CONFIG_ARCH_NOMADIK is not set
221# CONFIG_ARCH_DAVINCI is not set 230# CONFIG_ARCH_DAVINCI is not set
222CONFIG_ARCH_OMAP=y 231CONFIG_ARCH_OMAP=y
223# CONFIG_ARCH_BCMRING is not set
224# CONFIG_ARCH_U8500 is not set
225 232
226# 233#
227# TI OMAP Implementations 234# TI OMAP Implementations
@@ -237,16 +244,20 @@ CONFIG_ARCH_OMAP3=y
237# OMAP Feature Selections 244# OMAP Feature Selections
238# 245#
239# CONFIG_OMAP_RESET_CLOCKS is not set 246# CONFIG_OMAP_RESET_CLOCKS is not set
240# CONFIG_OMAP_MUX is not set 247CONFIG_OMAP_MUX=y
248# CONFIG_OMAP_MUX_DEBUG is not set
249CONFIG_OMAP_MUX_WARNINGS=y
241CONFIG_OMAP_MCBSP=y 250CONFIG_OMAP_MCBSP=y
242# CONFIG_OMAP_MBOX_FWK is not set 251# CONFIG_OMAP_MBOX_FWK is not set
243# CONFIG_OMAP_MPU_TIMER is not set 252# CONFIG_OMAP_MPU_TIMER is not set
244CONFIG_OMAP_32K_TIMER=y 253CONFIG_OMAP_32K_TIMER=y
254# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set
245CONFIG_OMAP_32K_TIMER_HZ=128 255CONFIG_OMAP_32K_TIMER_HZ=128
246CONFIG_OMAP_DM_TIMER=y 256CONFIG_OMAP_DM_TIMER=y
247# CONFIG_OMAP_PM_NONE is not set 257# CONFIG_OMAP_PM_NONE is not set
248CONFIG_OMAP_PM_NOOP=y 258CONFIG_OMAP_PM_NOOP=y
249CONFIG_ARCH_OMAP3430=y 259CONFIG_ARCH_OMAP3430=y
260CONFIG_OMAP_PACKAGE_CUS=y
250 261
251# 262#
252# OMAP Board Type 263# OMAP Board Type
@@ -295,6 +306,7 @@ CONFIG_ARM_THUMB=y
295# CONFIG_CPU_BPREDICT_DISABLE is not set 306# CONFIG_CPU_BPREDICT_DISABLE is not set
296CONFIG_HAS_TLS_REG=y 307CONFIG_HAS_TLS_REG=y
297CONFIG_ARM_L1_CACHE_SHIFT=6 308CONFIG_ARM_L1_CACHE_SHIFT=6
309CONFIG_CPU_HAS_PMU=y
298# CONFIG_ARM_ERRATA_430973 is not set 310# CONFIG_ARM_ERRATA_430973 is not set
299# CONFIG_ARM_ERRATA_458693 is not set 311# CONFIG_ARM_ERRATA_458693 is not set
300# CONFIG_ARM_ERRATA_460075 is not set 312# CONFIG_ARM_ERRATA_460075 is not set
@@ -387,7 +399,14 @@ CONFIG_HAVE_AOUT=y
387# 399#
388# Power management options 400# Power management options
389# 401#
390# CONFIG_PM is not set 402CONFIG_PM=y
403# CONFIG_PM_DEBUG is not set
404CONFIG_PM_SLEEP=y
405CONFIG_SUSPEND=y
406CONFIG_SUSPEND_FREEZER=y
407# CONFIG_APM_EMULATION is not set
408# CONFIG_PM_RUNTIME is not set
409CONFIG_PM_OPS=y
391CONFIG_ARCH_SUSPEND_POSSIBLE=y 410CONFIG_ARCH_SUSPEND_POSSIBLE=y
392CONFIG_NET=y 411CONFIG_NET=y
393 412
@@ -395,7 +414,6 @@ CONFIG_NET=y
395# Networking options 414# Networking options
396# 415#
397CONFIG_PACKET=y 416CONFIG_PACKET=y
398# CONFIG_PACKET_MMAP is not set
399CONFIG_UNIX=y 417CONFIG_UNIX=y
400CONFIG_XFRM=y 418CONFIG_XFRM=y
401# CONFIG_XFRM_USER is not set 419# CONFIG_XFRM_USER is not set
@@ -666,6 +684,7 @@ CONFIG_HAVE_IDE=y
666# 684#
667# SCSI device support 685# SCSI device support
668# 686#
687CONFIG_SCSI_MOD=y
669# CONFIG_RAID_ATTRS is not set 688# CONFIG_RAID_ATTRS is not set
670CONFIG_SCSI=y 689CONFIG_SCSI=y
671CONFIG_SCSI_DMA=y 690CONFIG_SCSI_DMA=y
@@ -717,6 +736,7 @@ CONFIG_NET_ETHERNET=y
717CONFIG_MII=y 736CONFIG_MII=y
718# CONFIG_AX88796 is not set 737# CONFIG_AX88796 is not set
719# CONFIG_SMC91X is not set 738# CONFIG_SMC91X is not set
739# CONFIG_TI_DAVINCI_EMAC is not set
720CONFIG_DM9000=y 740CONFIG_DM9000=y
721CONFIG_DM9000_DEBUGLEVEL=4 741CONFIG_DM9000_DEBUGLEVEL=4
722CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y 742CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y
@@ -863,6 +883,7 @@ CONFIG_SERIAL_8250_RSA=y
863# CONFIG_SERIAL_MAX3100 is not set 883# CONFIG_SERIAL_MAX3100 is not set
864CONFIG_SERIAL_CORE=y 884CONFIG_SERIAL_CORE=y
865CONFIG_SERIAL_CORE_CONSOLE=y 885CONFIG_SERIAL_CORE_CONSOLE=y
886# CONFIG_SERIAL_TIMBERDALE is not set
866CONFIG_UNIX98_PTYS=y 887CONFIG_UNIX98_PTYS=y
867# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 888# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
868# CONFIG_LEGACY_PTYS is not set 889# CONFIG_LEGACY_PTYS is not set
@@ -891,6 +912,7 @@ CONFIG_I2C_HELPER_AUTO=y
891# CONFIG_I2C_OCORES is not set 912# CONFIG_I2C_OCORES is not set
892CONFIG_I2C_OMAP=y 913CONFIG_I2C_OMAP=y
893# CONFIG_I2C_SIMTEC is not set 914# CONFIG_I2C_SIMTEC is not set
915# CONFIG_I2C_XILINX is not set
894 916
895# 917#
896# External I2C/SMBus adapter drivers 918# External I2C/SMBus adapter drivers
@@ -904,15 +926,9 @@ CONFIG_I2C_OMAP=y
904# 926#
905# CONFIG_I2C_PCA_PLATFORM is not set 927# CONFIG_I2C_PCA_PLATFORM is not set
906# CONFIG_I2C_STUB is not set 928# CONFIG_I2C_STUB is not set
907
908#
909# Miscellaneous I2C Chip support
910#
911# CONFIG_SENSORS_TSL2550 is not set
912# CONFIG_I2C_DEBUG_CORE is not set 929# CONFIG_I2C_DEBUG_CORE is not set
913# CONFIG_I2C_DEBUG_ALGO is not set 930# CONFIG_I2C_DEBUG_ALGO is not set
914# CONFIG_I2C_DEBUG_BUS is not set 931# CONFIG_I2C_DEBUG_BUS is not set
915# CONFIG_I2C_DEBUG_CHIP is not set
916CONFIG_SPI=y 932CONFIG_SPI=y
917# CONFIG_SPI_DEBUG is not set 933# CONFIG_SPI_DEBUG is not set
918CONFIG_SPI_MASTER=y 934CONFIG_SPI_MASTER=y
@@ -944,10 +960,12 @@ CONFIG_GPIOLIB=y
944# 960#
945# Memory mapped GPIO expanders: 961# Memory mapped GPIO expanders:
946# 962#
963# CONFIG_GPIO_IT8761E is not set
947 964
948# 965#
949# I2C GPIO expanders: 966# I2C GPIO expanders:
950# 967#
968# CONFIG_GPIO_MAX7300 is not set
951# CONFIG_GPIO_MAX732X is not set 969# CONFIG_GPIO_MAX732X is not set
952# CONFIG_GPIO_PCA953X is not set 970# CONFIG_GPIO_PCA953X is not set
953# CONFIG_GPIO_PCF857X is not set 971# CONFIG_GPIO_PCF857X is not set
@@ -984,10 +1002,12 @@ CONFIG_SSB_POSSIBLE=y
984# Multifunction device drivers 1002# Multifunction device drivers
985# 1003#
986CONFIG_MFD_CORE=y 1004CONFIG_MFD_CORE=y
1005# CONFIG_MFD_88PM860X is not set
987# CONFIG_MFD_SM501 is not set 1006# CONFIG_MFD_SM501 is not set
988# CONFIG_MFD_ASIC3 is not set 1007# CONFIG_MFD_ASIC3 is not set
989# CONFIG_HTC_EGPIO is not set 1008# CONFIG_HTC_EGPIO is not set
990# CONFIG_HTC_PASIC3 is not set 1009# CONFIG_HTC_PASIC3 is not set
1010# CONFIG_HTC_I2CPLD is not set
991# CONFIG_TPS65010 is not set 1011# CONFIG_TPS65010 is not set
992CONFIG_TWL4030_CORE=y 1012CONFIG_TWL4030_CORE=y
993CONFIG_TWL4030_POWER=y 1013CONFIG_TWL4030_POWER=y
@@ -998,22 +1018,25 @@ CONFIG_TWL4030_CODEC=y
998# CONFIG_MFD_TC6393XB is not set 1018# CONFIG_MFD_TC6393XB is not set
999# CONFIG_PMIC_DA903X is not set 1019# CONFIG_PMIC_DA903X is not set
1000# CONFIG_PMIC_ADP5520 is not set 1020# CONFIG_PMIC_ADP5520 is not set
1021# CONFIG_MFD_MAX8925 is not set
1001# CONFIG_MFD_WM8400 is not set 1022# CONFIG_MFD_WM8400 is not set
1002# CONFIG_MFD_WM831X is not set 1023# CONFIG_MFD_WM831X is not set
1003# CONFIG_MFD_WM8350_I2C is not set 1024# CONFIG_MFD_WM8350_I2C is not set
1025# CONFIG_MFD_WM8994 is not set
1004# CONFIG_MFD_PCF50633 is not set 1026# CONFIG_MFD_PCF50633 is not set
1005# CONFIG_MFD_MC13783 is not set 1027# CONFIG_MFD_MC13783 is not set
1006# CONFIG_AB3100_CORE is not set 1028# CONFIG_AB3100_CORE is not set
1007# CONFIG_EZX_PCAP is not set 1029# CONFIG_EZX_PCAP is not set
1008# CONFIG_MFD_88PM8607 is not set
1009# CONFIG_AB4500_CORE is not set 1030# CONFIG_AB4500_CORE is not set
1010CONFIG_REGULATOR=y 1031CONFIG_REGULATOR=y
1011# CONFIG_REGULATOR_DEBUG is not set 1032# CONFIG_REGULATOR_DEBUG is not set
1033# CONFIG_REGULATOR_DUMMY is not set
1012# CONFIG_REGULATOR_FIXED_VOLTAGE is not set 1034# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
1013# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set 1035# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
1014# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set 1036# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
1015# CONFIG_REGULATOR_BQ24022 is not set 1037# CONFIG_REGULATOR_BQ24022 is not set
1016# CONFIG_REGULATOR_MAX1586 is not set 1038# CONFIG_REGULATOR_MAX1586 is not set
1039# CONFIG_REGULATOR_MAX8649 is not set
1017# CONFIG_REGULATOR_MAX8660 is not set 1040# CONFIG_REGULATOR_MAX8660 is not set
1018CONFIG_REGULATOR_TWL4030=y 1041CONFIG_REGULATOR_TWL4030=y
1019# CONFIG_REGULATOR_LP3971 is not set 1042# CONFIG_REGULATOR_LP3971 is not set
@@ -1072,7 +1095,6 @@ CONFIG_OMAP2_DSS_VENC=y
1072CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 1095CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
1073CONFIG_FB_OMAP2=y 1096CONFIG_FB_OMAP2=y
1074CONFIG_FB_OMAP2_DEBUG_SUPPORT=y 1097CONFIG_FB_OMAP2_DEBUG_SUPPORT=y
1075# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
1076CONFIG_FB_OMAP2_NUM_FBS=3 1098CONFIG_FB_OMAP2_NUM_FBS=3
1077 1099
1078# 1100#
@@ -1080,7 +1102,9 @@ CONFIG_FB_OMAP2_NUM_FBS=3
1080# 1102#
1081CONFIG_PANEL_GENERIC=y 1103CONFIG_PANEL_GENERIC=y
1082# CONFIG_PANEL_SHARP_LS037V7DW01 is not set 1104# CONFIG_PANEL_SHARP_LS037V7DW01 is not set
1083CONFIG_PANEL_INNOLUX_AT070TN83=y 1105# CONFIG_PANEL_SHARP_LQ043T1DG01 is not set
1106# CONFIG_PANEL_TOPPOLY_TDO35S is not set
1107# CONFIG_PANEL_TPO_TD043MTEA1 is not set
1084# CONFIG_BACKLIGHT_LCD_SUPPORT is not set 1108# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1085 1109
1086# 1110#
@@ -1136,6 +1160,7 @@ CONFIG_SND_ARM=y
1136CONFIG_SND_SPI=y 1160CONFIG_SND_SPI=y
1137CONFIG_SND_USB=y 1161CONFIG_SND_USB=y
1138# CONFIG_SND_USB_AUDIO is not set 1162# CONFIG_SND_USB_AUDIO is not set
1163# CONFIG_SND_USB_UA101 is not set
1139# CONFIG_SND_USB_CAIAQ is not set 1164# CONFIG_SND_USB_CAIAQ is not set
1140CONFIG_SND_SOC=y 1165CONFIG_SND_SOC=y
1141CONFIG_SND_OMAP_SOC=y 1166CONFIG_SND_OMAP_SOC=y
@@ -1147,42 +1172,44 @@ CONFIG_SND_SOC_TWL4030=y
1147# CONFIG_SOUND_PRIME is not set 1172# CONFIG_SOUND_PRIME is not set
1148CONFIG_HID_SUPPORT=y 1173CONFIG_HID_SUPPORT=y
1149CONFIG_HID=y 1174CONFIG_HID=y
1150CONFIG_HIDRAW=y 1175# CONFIG_HIDRAW is not set
1151 1176
1152# 1177#
1153# USB Input Devices 1178# USB Input Devices
1154# 1179#
1155CONFIG_USB_HID=y 1180CONFIG_USB_HID=y
1156# CONFIG_HID_PID is not set 1181# CONFIG_HID_PID is not set
1157CONFIG_USB_HIDDEV=y 1182# CONFIG_USB_HIDDEV is not set
1158 1183
1159# 1184#
1160# Special HID drivers 1185# Special HID drivers
1161# 1186#
1162CONFIG_HID_A4TECH=y 1187# CONFIG_HID_3M_PCT is not set
1163CONFIG_HID_APPLE=y 1188# CONFIG_HID_A4TECH is not set
1164CONFIG_HID_BELKIN=y 1189# CONFIG_HID_APPLE is not set
1165CONFIG_HID_CHERRY=y 1190# CONFIG_HID_BELKIN is not set
1166CONFIG_HID_CHICONY=y 1191# CONFIG_HID_CHERRY is not set
1167CONFIG_HID_CYPRESS=y 1192# CONFIG_HID_CHICONY is not set
1193# CONFIG_HID_CYPRESS is not set
1168# CONFIG_HID_DRAGONRISE is not set 1194# CONFIG_HID_DRAGONRISE is not set
1169CONFIG_HID_EZKEY=y 1195# CONFIG_HID_EZKEY is not set
1170# CONFIG_HID_KYE is not set 1196# CONFIG_HID_KYE is not set
1171CONFIG_HID_GYRATION=y 1197# CONFIG_HID_GYRATION is not set
1172# CONFIG_HID_TWINHAN is not set 1198# CONFIG_HID_TWINHAN is not set
1173# CONFIG_HID_KENSINGTON is not set 1199# CONFIG_HID_KENSINGTON is not set
1174CONFIG_HID_LOGITECH=y 1200# CONFIG_HID_LOGITECH is not set
1175# CONFIG_LOGITECH_FF is not set 1201# CONFIG_HID_MICROSOFT is not set
1176# CONFIG_LOGIRUMBLEPAD2_FF is not set 1202# CONFIG_HID_MOSART is not set
1177CONFIG_HID_MICROSOFT=y 1203# CONFIG_HID_MONTEREY is not set
1178CONFIG_HID_MONTEREY=y
1179# CONFIG_HID_NTRIG is not set 1204# CONFIG_HID_NTRIG is not set
1180CONFIG_HID_PANTHERLORD=y 1205# CONFIG_HID_ORTEK is not set
1181# CONFIG_PANTHERLORD_FF is not set 1206# CONFIG_HID_PANTHERLORD is not set
1182CONFIG_HID_PETALYNX=y 1207# CONFIG_HID_PETALYNX is not set
1183CONFIG_HID_SAMSUNG=y 1208# CONFIG_HID_QUANTA is not set
1184CONFIG_HID_SONY=y 1209# CONFIG_HID_SAMSUNG is not set
1185CONFIG_HID_SUNPLUS=y 1210# CONFIG_HID_SONY is not set
1211# CONFIG_HID_STANTUM is not set
1212# CONFIG_HID_SUNPLUS is not set
1186# CONFIG_HID_GREENASIA is not set 1213# CONFIG_HID_GREENASIA is not set
1187# CONFIG_HID_SMARTJOYPLUS is not set 1214# CONFIG_HID_SMARTJOYPLUS is not set
1188# CONFIG_HID_TOPSEED is not set 1215# CONFIG_HID_TOPSEED is not set
@@ -1193,7 +1220,7 @@ CONFIG_USB_ARCH_HAS_HCD=y
1193CONFIG_USB_ARCH_HAS_OHCI=y 1220CONFIG_USB_ARCH_HAS_OHCI=y
1194CONFIG_USB_ARCH_HAS_EHCI=y 1221CONFIG_USB_ARCH_HAS_EHCI=y
1195CONFIG_USB=y 1222CONFIG_USB=y
1196# CONFIG_USB_DEBUG is not set 1223CONFIG_USB_DEBUG=y
1197CONFIG_USB_ANNOUNCE_NEW_DEVICES=y 1224CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1198 1225
1199# 1226#
@@ -1202,7 +1229,7 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1202# CONFIG_USB_DEVICEFS is not set 1229# CONFIG_USB_DEVICEFS is not set
1203# CONFIG_USB_DEVICE_CLASS is not set 1230# CONFIG_USB_DEVICE_CLASS is not set
1204# CONFIG_USB_DYNAMIC_MINORS is not set 1231# CONFIG_USB_DYNAMIC_MINORS is not set
1205# CONFIG_USB_OTG is not set 1232CONFIG_USB_OTG=y
1206# CONFIG_USB_OTG_WHITELIST is not set 1233# CONFIG_USB_OTG_WHITELIST is not set
1207# CONFIG_USB_OTG_BLACKLIST_HUB is not set 1234# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1208CONFIG_USB_MON=y 1235CONFIG_USB_MON=y
@@ -1230,15 +1257,15 @@ CONFIG_USB_MUSB_SOC=y
1230# 1257#
1231# OMAP 343x high speed USB support 1258# OMAP 343x high speed USB support
1232# 1259#
1233CONFIG_USB_MUSB_HOST=y 1260# CONFIG_USB_MUSB_HOST is not set
1234# CONFIG_USB_MUSB_PERIPHERAL is not set 1261# CONFIG_USB_MUSB_PERIPHERAL is not set
1235# CONFIG_USB_MUSB_OTG is not set 1262CONFIG_USB_MUSB_OTG=y
1236# CONFIG_USB_GADGET_MUSB_HDRC is not set 1263CONFIG_USB_GADGET_MUSB_HDRC=y
1237CONFIG_USB_MUSB_HDRC_HCD=y 1264CONFIG_USB_MUSB_HDRC_HCD=y
1238# CONFIG_MUSB_PIO_ONLY is not set 1265# CONFIG_MUSB_PIO_ONLY is not set
1239CONFIG_USB_INVENTRA_DMA=y 1266CONFIG_USB_INVENTRA_DMA=y
1240# CONFIG_USB_TI_CPPI_DMA is not set 1267# CONFIG_USB_TI_CPPI_DMA is not set
1241# CONFIG_USB_MUSB_DEBUG is not set 1268CONFIG_USB_MUSB_DEBUG=y
1242 1269
1243# 1270#
1244# USB Device Class drivers 1271# USB Device Class drivers
@@ -1291,7 +1318,6 @@ CONFIG_USB_STORAGE=m
1291# CONFIG_USB_RIO500 is not set 1318# CONFIG_USB_RIO500 is not set
1292# CONFIG_USB_LEGOTOWER is not set 1319# CONFIG_USB_LEGOTOWER is not set
1293# CONFIG_USB_LCD is not set 1320# CONFIG_USB_LCD is not set
1294# CONFIG_USB_BERRY_CHARGE is not set
1295# CONFIG_USB_LED is not set 1321# CONFIG_USB_LED is not set
1296# CONFIG_USB_CYPRESS_CY7C63 is not set 1322# CONFIG_USB_CYPRESS_CY7C63 is not set
1297# CONFIG_USB_CYTHERM is not set 1323# CONFIG_USB_CYTHERM is not set
@@ -1304,9 +1330,8 @@ CONFIG_USB_STORAGE=m
1304# CONFIG_USB_IOWARRIOR is not set 1330# CONFIG_USB_IOWARRIOR is not set
1305# CONFIG_USB_TEST is not set 1331# CONFIG_USB_TEST is not set
1306# CONFIG_USB_ISIGHTFW is not set 1332# CONFIG_USB_ISIGHTFW is not set
1307# CONFIG_USB_VST is not set
1308CONFIG_USB_GADGET=y 1333CONFIG_USB_GADGET=y
1309# CONFIG_USB_GADGET_DEBUG is not set 1334CONFIG_USB_GADGET_DEBUG=y
1310# CONFIG_USB_GADGET_DEBUG_FILES is not set 1335# CONFIG_USB_GADGET_DEBUG_FILES is not set
1311CONFIG_USB_GADGET_VBUS_DRAW=2 1336CONFIG_USB_GADGET_VBUS_DRAW=2
1312CONFIG_USB_GADGET_SELECTED=y 1337CONFIG_USB_GADGET_SELECTED=y
@@ -1314,8 +1339,7 @@ CONFIG_USB_GADGET_SELECTED=y
1314# CONFIG_USB_GADGET_ATMEL_USBA is not set 1339# CONFIG_USB_GADGET_ATMEL_USBA is not set
1315# CONFIG_USB_GADGET_FSL_USB2 is not set 1340# CONFIG_USB_GADGET_FSL_USB2 is not set
1316# CONFIG_USB_GADGET_LH7A40X is not set 1341# CONFIG_USB_GADGET_LH7A40X is not set
1317CONFIG_USB_GADGET_OMAP=y 1342# CONFIG_USB_GADGET_OMAP is not set
1318CONFIG_USB_OMAP=y
1319# CONFIG_USB_GADGET_PXA25X is not set 1343# CONFIG_USB_GADGET_PXA25X is not set
1320# CONFIG_USB_GADGET_R8A66597 is not set 1344# CONFIG_USB_GADGET_R8A66597 is not set
1321# CONFIG_USB_GADGET_PXA27X is not set 1345# CONFIG_USB_GADGET_PXA27X is not set
@@ -1330,19 +1354,20 @@ CONFIG_USB_OMAP=y
1330# CONFIG_USB_GADGET_GOKU is not set 1354# CONFIG_USB_GADGET_GOKU is not set
1331# CONFIG_USB_GADGET_LANGWELL is not set 1355# CONFIG_USB_GADGET_LANGWELL is not set
1332# CONFIG_USB_GADGET_DUMMY_HCD is not set 1356# CONFIG_USB_GADGET_DUMMY_HCD is not set
1333# CONFIG_USB_GADGET_DUALSPEED is not set 1357CONFIG_USB_GADGET_DUALSPEED=y
1334# CONFIG_USB_ZERO is not set 1358# CONFIG_USB_ZERO is not set
1335CONFIG_USB_AUDIO=m 1359# CONFIG_USB_AUDIO is not set
1336CONFIG_USB_ETH=m 1360CONFIG_USB_ETH=y
1337CONFIG_USB_ETH_RNDIS=y 1361# CONFIG_USB_ETH_RNDIS is not set
1338CONFIG_USB_ETH_EEM=y 1362# CONFIG_USB_ETH_EEM is not set
1339CONFIG_USB_GADGETFS=m 1363# CONFIG_USB_GADGETFS is not set
1340# CONFIG_USB_FILE_STORAGE is not set 1364# CONFIG_USB_FILE_STORAGE is not set
1341# CONFIG_USB_MASS_STORAGE is not set 1365# CONFIG_USB_MASS_STORAGE is not set
1342CONFIG_USB_G_SERIAL=m 1366# CONFIG_USB_G_SERIAL is not set
1343# CONFIG_USB_MIDI_GADGET is not set 1367# CONFIG_USB_MIDI_GADGET is not set
1344CONFIG_USB_G_PRINTER=m 1368# CONFIG_USB_G_PRINTER is not set
1345# CONFIG_USB_CDC_COMPOSITE is not set 1369# CONFIG_USB_CDC_COMPOSITE is not set
1370# CONFIG_USB_G_NOKIA is not set
1346# CONFIG_USB_G_MULTI is not set 1371# CONFIG_USB_G_MULTI is not set
1347 1372
1348# 1373#
@@ -1373,8 +1398,6 @@ CONFIG_MMC_SDHCI=y
1373CONFIG_MMC_SDHCI_PLTFM=m 1398CONFIG_MMC_SDHCI_PLTFM=m
1374# CONFIG_MMC_OMAP is not set 1399# CONFIG_MMC_OMAP is not set
1375CONFIG_MMC_OMAP_HS=y 1400CONFIG_MMC_OMAP_HS=y
1376# CONFIG_MMC_AT91 is not set
1377# CONFIG_MMC_ATMELMCI is not set
1378CONFIG_MMC_SPI=m 1401CONFIG_MMC_SPI=m
1379# CONFIG_MEMSTICK is not set 1402# CONFIG_MEMSTICK is not set
1380CONFIG_NEW_LEDS=y 1403CONFIG_NEW_LEDS=y
@@ -1392,11 +1415,11 @@ CONFIG_LEDS_GPIO_PLATFORM=y
1392# CONFIG_LEDS_REGULATOR is not set 1415# CONFIG_LEDS_REGULATOR is not set
1393# CONFIG_LEDS_BD2802 is not set 1416# CONFIG_LEDS_BD2802 is not set
1394# CONFIG_LEDS_LT3593 is not set 1417# CONFIG_LEDS_LT3593 is not set
1418CONFIG_LEDS_TRIGGERS=y
1395 1419
1396# 1420#
1397# LED Triggers 1421# LED Triggers
1398# 1422#
1399CONFIG_LEDS_TRIGGERS=y
1400# CONFIG_LEDS_TRIGGER_TIMER is not set 1423# CONFIG_LEDS_TRIGGER_TIMER is not set
1401CONFIG_LEDS_TRIGGER_HEARTBEAT=y 1424CONFIG_LEDS_TRIGGER_HEARTBEAT=y
1402# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set 1425# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
@@ -1580,6 +1603,7 @@ CONFIG_UBIFS_FS=y
1580CONFIG_UBIFS_FS_LZO=y 1603CONFIG_UBIFS_FS_LZO=y
1581CONFIG_UBIFS_FS_ZLIB=y 1604CONFIG_UBIFS_FS_ZLIB=y
1582# CONFIG_UBIFS_FS_DEBUG is not set 1605# CONFIG_UBIFS_FS_DEBUG is not set
1606# CONFIG_LOGFS is not set
1583CONFIG_CRAMFS=y 1607CONFIG_CRAMFS=y
1584# CONFIG_SQUASHFS is not set 1608# CONFIG_SQUASHFS is not set
1585# CONFIG_VXFS_FS is not set 1609# CONFIG_VXFS_FS is not set
@@ -1606,6 +1630,7 @@ CONFIG_SUNRPC_GSS=y
1606CONFIG_RPCSEC_GSS_KRB5=y 1630CONFIG_RPCSEC_GSS_KRB5=y
1607# CONFIG_RPCSEC_GSS_SPKM3 is not set 1631# CONFIG_RPCSEC_GSS_SPKM3 is not set
1608# CONFIG_SMB_FS is not set 1632# CONFIG_SMB_FS is not set
1633# CONFIG_CEPH_FS is not set
1609# CONFIG_CIFS is not set 1634# CONFIG_CIFS is not set
1610# CONFIG_NCP_FS is not set 1635# CONFIG_NCP_FS is not set
1611# CONFIG_CODA_FS is not set 1636# CONFIG_CODA_FS is not set
diff --git a/arch/arm/configs/omap3_defconfig b/arch/arm/configs/omap3_defconfig
index d6ad92177324..94dfcf0aa674 100644
--- a/arch/arm/configs/omap3_defconfig
+++ b/arch/arm/configs/omap3_defconfig
@@ -1,13 +1,14 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.33-rc5 3# Linux kernel version: 2.6.34-rc7
4# Tue Jan 26 11:05:31 2010 4# Thu May 13 10:54:43 2010
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y 7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y 8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y 9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y 10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_HAVE_PROC_CPU=y
11CONFIG_GENERIC_HARDIRQS=y 12CONFIG_GENERIC_HARDIRQS=y
12CONFIG_STACKTRACE_SUPPORT=y 13CONFIG_STACKTRACE_SUPPORT=y
13CONFIG_HAVE_LATENCYTOP_SUPPORT=y 14CONFIG_HAVE_LATENCYTOP_SUPPORT=y
@@ -19,7 +20,9 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
19CONFIG_ARCH_HAS_CPUFREQ=y 20CONFIG_ARCH_HAS_CPUFREQ=y
20CONFIG_GENERIC_HWEIGHT=y 21CONFIG_GENERIC_HWEIGHT=y
21CONFIG_GENERIC_CALIBRATE_DELAY=y 22CONFIG_GENERIC_CALIBRATE_DELAY=y
23CONFIG_NEED_DMA_MAP_STATE=y
22CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y 24CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
25CONFIG_ARM_L1_CACHE_SHIFT_6=y
23CONFIG_OPROFILE_ARMV6=y 26CONFIG_OPROFILE_ARMV6=y
24CONFIG_OPROFILE_ARM11_CORE=y 27CONFIG_OPROFILE_ARM11_CORE=y
25CONFIG_OPROFILE_ARMV7=y 28CONFIG_OPROFILE_ARMV7=y
@@ -63,12 +66,7 @@ CONFIG_RCU_FANOUT=32
63# CONFIG_TREE_RCU_TRACE is not set 66# CONFIG_TREE_RCU_TRACE is not set
64CONFIG_IKCONFIG=y 67CONFIG_IKCONFIG=y
65CONFIG_IKCONFIG_PROC=y 68CONFIG_IKCONFIG_PROC=y
66CONFIG_LOG_BUF_SHIFT=14 69CONFIG_LOG_BUF_SHIFT=16
67CONFIG_GROUP_SCHED=y
68CONFIG_FAIR_GROUP_SCHED=y
69# CONFIG_RT_GROUP_SCHED is not set
70CONFIG_USER_SCHED=y
71# CONFIG_CGROUP_SCHED is not set
72# CONFIG_CGROUPS is not set 70# CONFIG_CGROUPS is not set
73# CONFIG_SYSFS_DEPRECATED_V2 is not set 71# CONFIG_SYSFS_DEPRECATED_V2 is not set
74# CONFIG_RELAY is not set 72# CONFIG_RELAY is not set
@@ -100,17 +98,21 @@ CONFIG_TIMERFD=y
100CONFIG_EVENTFD=y 98CONFIG_EVENTFD=y
101CONFIG_SHMEM=y 99CONFIG_SHMEM=y
102CONFIG_AIO=y 100CONFIG_AIO=y
101CONFIG_HAVE_PERF_EVENTS=y
102CONFIG_PERF_USE_VMALLOC=y
103 103
104# 104#
105# Kernel Performance Events And Counters 105# Kernel Performance Events And Counters
106# 106#
107CONFIG_PERF_EVENTS=y
108# CONFIG_PERF_COUNTERS is not set
109# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
107CONFIG_VM_EVENT_COUNTERS=y 110CONFIG_VM_EVENT_COUNTERS=y
108CONFIG_COMPAT_BRK=y 111CONFIG_COMPAT_BRK=y
109CONFIG_SLAB=y 112CONFIG_SLAB=y
110# CONFIG_SLUB is not set 113# CONFIG_SLUB is not set
111# CONFIG_SLOB is not set 114# CONFIG_SLOB is not set
112CONFIG_PROFILING=y 115CONFIG_PROFILING=y
113CONFIG_TRACEPOINTS=y
114CONFIG_OPROFILE=y 116CONFIG_OPROFILE=y
115CONFIG_HAVE_OPROFILE=y 117CONFIG_HAVE_OPROFILE=y
116CONFIG_KPROBES=y 118CONFIG_KPROBES=y
@@ -189,6 +191,7 @@ CONFIG_MMU=y
189# CONFIG_ARCH_REALVIEW is not set 191# CONFIG_ARCH_REALVIEW is not set
190# CONFIG_ARCH_VERSATILE is not set 192# CONFIG_ARCH_VERSATILE is not set
191# CONFIG_ARCH_AT91 is not set 193# CONFIG_ARCH_AT91 is not set
194# CONFIG_ARCH_BCMRING is not set
192# CONFIG_ARCH_CLPS711X is not set 195# CONFIG_ARCH_CLPS711X is not set
193# CONFIG_ARCH_GEMINI is not set 196# CONFIG_ARCH_GEMINI is not set
194# CONFIG_ARCH_EBSA110 is not set 197# CONFIG_ARCH_EBSA110 is not set
@@ -198,7 +201,6 @@ CONFIG_MMU=y
198# CONFIG_ARCH_STMP3XXX is not set 201# CONFIG_ARCH_STMP3XXX is not set
199# CONFIG_ARCH_NETX is not set 202# CONFIG_ARCH_NETX is not set
200# CONFIG_ARCH_H720X is not set 203# CONFIG_ARCH_H720X is not set
201# CONFIG_ARCH_NOMADIK is not set
202# CONFIG_ARCH_IOP13XX is not set 204# CONFIG_ARCH_IOP13XX is not set
203# CONFIG_ARCH_IOP32X is not set 205# CONFIG_ARCH_IOP32X is not set
204# CONFIG_ARCH_IOP33X is not set 206# CONFIG_ARCH_IOP33X is not set
@@ -215,21 +217,26 @@ CONFIG_MMU=y
215# CONFIG_ARCH_KS8695 is not set 217# CONFIG_ARCH_KS8695 is not set
216# CONFIG_ARCH_NS9XXX is not set 218# CONFIG_ARCH_NS9XXX is not set
217# CONFIG_ARCH_W90X900 is not set 219# CONFIG_ARCH_W90X900 is not set
220# CONFIG_ARCH_NUC93X is not set
218# CONFIG_ARCH_PNX4008 is not set 221# CONFIG_ARCH_PNX4008 is not set
219# CONFIG_ARCH_PXA is not set 222# CONFIG_ARCH_PXA is not set
220# CONFIG_ARCH_MSM is not set 223# CONFIG_ARCH_MSM is not set
224# CONFIG_ARCH_SHMOBILE is not set
221# CONFIG_ARCH_RPC is not set 225# CONFIG_ARCH_RPC is not set
222# CONFIG_ARCH_SA1100 is not set 226# CONFIG_ARCH_SA1100 is not set
223# CONFIG_ARCH_S3C2410 is not set 227# CONFIG_ARCH_S3C2410 is not set
224# CONFIG_ARCH_S3C64XX is not set 228# CONFIG_ARCH_S3C64XX is not set
229# CONFIG_ARCH_S5P6440 is not set
230# CONFIG_ARCH_S5P6442 is not set
225# CONFIG_ARCH_S5PC1XX is not set 231# CONFIG_ARCH_S5PC1XX is not set
232# CONFIG_ARCH_S5PV210 is not set
226# CONFIG_ARCH_SHARK is not set 233# CONFIG_ARCH_SHARK is not set
227# CONFIG_ARCH_LH7A40X is not set 234# CONFIG_ARCH_LH7A40X is not set
228# CONFIG_ARCH_U300 is not set 235# CONFIG_ARCH_U300 is not set
236# CONFIG_ARCH_U8500 is not set
237# CONFIG_ARCH_NOMADIK is not set
229# CONFIG_ARCH_DAVINCI is not set 238# CONFIG_ARCH_DAVINCI is not set
230CONFIG_ARCH_OMAP=y 239CONFIG_ARCH_OMAP=y
231# CONFIG_ARCH_BCMRING is not set
232# CONFIG_ARCH_U8500 is not set
233 240
234# 241#
235# TI OMAP Implementations 242# TI OMAP Implementations
@@ -254,6 +261,7 @@ CONFIG_OMAP_MCBSP=y
254# CONFIG_OMAP_MBOX_FWK is not set 261# CONFIG_OMAP_MBOX_FWK is not set
255# CONFIG_OMAP_MPU_TIMER is not set 262# CONFIG_OMAP_MPU_TIMER is not set
256CONFIG_OMAP_32K_TIMER=y 263CONFIG_OMAP_32K_TIMER=y
264# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set
257CONFIG_OMAP_32K_TIMER_HZ=128 265CONFIG_OMAP_32K_TIMER_HZ=128
258CONFIG_OMAP_DM_TIMER=y 266CONFIG_OMAP_DM_TIMER=y
259# CONFIG_OMAP_PM_NONE is not set 267# CONFIG_OMAP_PM_NONE is not set
@@ -264,7 +272,7 @@ CONFIG_MACH_OMAP_GENERIC=y
264# OMAP Core Type 272# OMAP Core Type
265# 273#
266CONFIG_ARCH_OMAP2420=y 274CONFIG_ARCH_OMAP2420=y
267# CONFIG_ARCH_OMAP2430 is not set 275CONFIG_ARCH_OMAP2430=y
268CONFIG_ARCH_OMAP3430=y 276CONFIG_ARCH_OMAP3430=y
269CONFIG_OMAP_PACKAGE_CBB=y 277CONFIG_OMAP_PACKAGE_CBB=y
270CONFIG_OMAP_PACKAGE_CUS=y 278CONFIG_OMAP_PACKAGE_CUS=y
@@ -276,8 +284,9 @@ CONFIG_OMAP_PACKAGE_CBP=y
276CONFIG_MACH_OMAP2_TUSB6010=y 284CONFIG_MACH_OMAP2_TUSB6010=y
277CONFIG_MACH_OMAP_H4=y 285CONFIG_MACH_OMAP_H4=y
278CONFIG_MACH_OMAP_APOLLON=y 286CONFIG_MACH_OMAP_APOLLON=y
279# CONFIG_MACH_OMAP_2430SDP is not set 287CONFIG_MACH_OMAP_2430SDP=y
280CONFIG_MACH_OMAP3_BEAGLE=y 288CONFIG_MACH_OMAP3_BEAGLE=y
289CONFIG_MACH_DEVKIT8000=y
281CONFIG_MACH_OMAP_LDP=y 290CONFIG_MACH_OMAP_LDP=y
282CONFIG_MACH_OVERO=y 291CONFIG_MACH_OVERO=y
283CONFIG_MACH_OMAP3EVM=y 292CONFIG_MACH_OMAP3EVM=y
@@ -294,6 +303,7 @@ CONFIG_MACH_OMAP_ZOOM2=y
294CONFIG_MACH_OMAP_ZOOM3=y 303CONFIG_MACH_OMAP_ZOOM3=y
295CONFIG_MACH_CM_T35=y 304CONFIG_MACH_CM_T35=y
296CONFIG_MACH_IGEP0020=y 305CONFIG_MACH_IGEP0020=y
306CONFIG_MACH_SBC3530=y
297CONFIG_MACH_OMAP_3630SDP=y 307CONFIG_MACH_OMAP_3630SDP=y
298CONFIG_MACH_OMAP_4430SDP=y 308CONFIG_MACH_OMAP_4430SDP=y
299# CONFIG_OMAP3_EMU is not set 309# CONFIG_OMAP3_EMU is not set
@@ -330,11 +340,16 @@ CONFIG_ARM_THUMBEE=y
330# CONFIG_CPU_DCACHE_DISABLE is not set 340# CONFIG_CPU_DCACHE_DISABLE is not set
331# CONFIG_CPU_BPREDICT_DISABLE is not set 341# CONFIG_CPU_BPREDICT_DISABLE is not set
332CONFIG_HAS_TLS_REG=y 342CONFIG_HAS_TLS_REG=y
343CONFIG_OUTER_CACHE=y
344CONFIG_OUTER_CACHE_SYNC=y
345CONFIG_CACHE_L2X0=y
333CONFIG_ARM_L1_CACHE_SHIFT=6 346CONFIG_ARM_L1_CACHE_SHIFT=6
347CONFIG_CPU_HAS_PMU=y
334# CONFIG_ARM_ERRATA_411920 is not set 348# CONFIG_ARM_ERRATA_411920 is not set
335# CONFIG_ARM_ERRATA_430973 is not set 349# CONFIG_ARM_ERRATA_430973 is not set
336# CONFIG_ARM_ERRATA_458693 is not set 350# CONFIG_ARM_ERRATA_458693 is not set
337# CONFIG_ARM_ERRATA_460075 is not set 351# CONFIG_ARM_ERRATA_460075 is not set
352# CONFIG_PL310_ERRATA_588369 is not set
338CONFIG_ARM_GIC=y 353CONFIG_ARM_GIC=y
339CONFIG_COMMON_CLKDEV=y 354CONFIG_COMMON_CLKDEV=y
340 355
@@ -368,6 +383,7 @@ CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
368# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set 383# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
369# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set 384# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
370# CONFIG_HIGHMEM is not set 385# CONFIG_HIGHMEM is not set
386CONFIG_HW_PERF_EVENTS=y
371CONFIG_SELECT_MEMORY_MODEL=y 387CONFIG_SELECT_MEMORY_MODEL=y
372CONFIG_FLATMEM_MANUAL=y 388CONFIG_FLATMEM_MANUAL=y
373# CONFIG_DISCONTIGMEM_MANUAL is not set 389# CONFIG_DISCONTIGMEM_MANUAL is not set
@@ -390,7 +406,7 @@ CONFIG_ALIGNMENT_TRAP=y
390# 406#
391CONFIG_ZBOOT_ROM_TEXT=0x0 407CONFIG_ZBOOT_ROM_TEXT=0x0
392CONFIG_ZBOOT_ROM_BSS=0x0 408CONFIG_ZBOOT_ROM_BSS=0x0
393CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" 409CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyS2,115200"
394# CONFIG_XIP_KERNEL is not set 410# CONFIG_XIP_KERNEL is not set
395CONFIG_KEXEC=y 411CONFIG_KEXEC=y
396CONFIG_ATAGS_PROC=y 412CONFIG_ATAGS_PROC=y
@@ -443,7 +459,8 @@ CONFIG_BINFMT_MISC=y
443# 459#
444CONFIG_PM=y 460CONFIG_PM=y
445CONFIG_PM_DEBUG=y 461CONFIG_PM_DEBUG=y
446CONFIG_PM_VERBOSE=y 462# CONFIG_PM_ADVANCED_DEBUG is not set
463# CONFIG_PM_VERBOSE is not set
447CONFIG_CAN_PM_TRACE=y 464CONFIG_CAN_PM_TRACE=y
448CONFIG_PM_SLEEP=y 465CONFIG_PM_SLEEP=y
449CONFIG_SUSPEND=y 466CONFIG_SUSPEND=y
@@ -451,6 +468,7 @@ CONFIG_SUSPEND=y
451CONFIG_SUSPEND_FREEZER=y 468CONFIG_SUSPEND_FREEZER=y
452# CONFIG_APM_EMULATION is not set 469# CONFIG_APM_EMULATION is not set
453CONFIG_PM_RUNTIME=y 470CONFIG_PM_RUNTIME=y
471CONFIG_PM_OPS=y
454CONFIG_ARCH_SUSPEND_POSSIBLE=y 472CONFIG_ARCH_SUSPEND_POSSIBLE=y
455CONFIG_NET=y 473CONFIG_NET=y
456 474
@@ -458,7 +476,6 @@ CONFIG_NET=y
458# Networking options 476# Networking options
459# 477#
460CONFIG_PACKET=y 478CONFIG_PACKET=y
461CONFIG_PACKET_MMAP=y
462CONFIG_UNIX=y 479CONFIG_UNIX=y
463CONFIG_XFRM=y 480CONFIG_XFRM=y
464CONFIG_XFRM_USER=y 481CONFIG_XFRM_USER=y
@@ -544,7 +561,6 @@ CONFIG_NETFILTER_ADVANCED=y
544# 561#
545# CONFIG_NET_PKTGEN is not set 562# CONFIG_NET_PKTGEN is not set
546# CONFIG_NET_TCPPROBE is not set 563# CONFIG_NET_TCPPROBE is not set
547# CONFIG_NET_DROP_MONITOR is not set
548# CONFIG_HAMRADIO is not set 564# CONFIG_HAMRADIO is not set
549# CONFIG_CAN is not set 565# CONFIG_CAN is not set
550# CONFIG_IRDA is not set 566# CONFIG_IRDA is not set
@@ -584,7 +600,7 @@ CONFIG_CFG80211=y
584# CONFIG_CFG80211_REG_DEBUG is not set 600# CONFIG_CFG80211_REG_DEBUG is not set
585CONFIG_CFG80211_DEFAULT_PS=y 601CONFIG_CFG80211_DEFAULT_PS=y
586# CONFIG_CFG80211_DEBUGFS is not set 602# CONFIG_CFG80211_DEBUGFS is not set
587CONFIG_WIRELESS_OLD_REGULATORY=y 603# CONFIG_CFG80211_INTERNAL_REGDB is not set
588CONFIG_CFG80211_WEXT=y 604CONFIG_CFG80211_WEXT=y
589CONFIG_WIRELESS_EXT_SYSFS=y 605CONFIG_WIRELESS_EXT_SYSFS=y
590CONFIG_LIB80211=y 606CONFIG_LIB80211=y
@@ -676,7 +692,6 @@ CONFIG_MTD_CFI_UTIL=y
676# CONFIG_MTD_COMPLEX_MAPPINGS is not set 692# CONFIG_MTD_COMPLEX_MAPPINGS is not set
677# CONFIG_MTD_PHYSMAP is not set 693# CONFIG_MTD_PHYSMAP is not set
678# CONFIG_MTD_ARM_INTEGRATOR is not set 694# CONFIG_MTD_ARM_INTEGRATOR is not set
679CONFIG_MTD_OMAP_NOR=y
680# CONFIG_MTD_PLATRAM is not set 695# CONFIG_MTD_PLATRAM is not set
681 696
682# 697#
@@ -754,6 +769,7 @@ CONFIG_MISC_DEVICES=y
754# CONFIG_ICS932S401 is not set 769# CONFIG_ICS932S401 is not set
755# CONFIG_ENCLOSURE_SERVICES is not set 770# CONFIG_ENCLOSURE_SERVICES is not set
756# CONFIG_ISL29003 is not set 771# CONFIG_ISL29003 is not set
772# CONFIG_SENSORS_TSL2550 is not set
757# CONFIG_DS1682 is not set 773# CONFIG_DS1682 is not set
758# CONFIG_TI_DAC7512 is not set 774# CONFIG_TI_DAC7512 is not set
759# CONFIG_C2PORT is not set 775# CONFIG_C2PORT is not set
@@ -773,6 +789,7 @@ CONFIG_HAVE_IDE=y
773# 789#
774# SCSI device support 790# SCSI device support
775# 791#
792CONFIG_SCSI_MOD=y
776# CONFIG_RAID_ATTRS is not set 793# CONFIG_RAID_ATTRS is not set
777CONFIG_SCSI=y 794CONFIG_SCSI=y
778CONFIG_SCSI_DMA=y 795CONFIG_SCSI_DMA=y
@@ -839,12 +856,14 @@ CONFIG_SMSC_PHY=y
839# CONFIG_NATIONAL_PHY is not set 856# CONFIG_NATIONAL_PHY is not set
840# CONFIG_STE10XP is not set 857# CONFIG_STE10XP is not set
841# CONFIG_LSI_ET1011C_PHY is not set 858# CONFIG_LSI_ET1011C_PHY is not set
859# CONFIG_MICREL_PHY is not set
842# CONFIG_FIXED_PHY is not set 860# CONFIG_FIXED_PHY is not set
843# CONFIG_MDIO_BITBANG is not set 861# CONFIG_MDIO_BITBANG is not set
844CONFIG_NET_ETHERNET=y 862CONFIG_NET_ETHERNET=y
845CONFIG_MII=y 863CONFIG_MII=y
846# CONFIG_AX88796 is not set 864# CONFIG_AX88796 is not set
847CONFIG_SMC91X=y 865CONFIG_SMC91X=y
866# CONFIG_TI_DAVINCI_EMAC is not set
848# CONFIG_DM9000 is not set 867# CONFIG_DM9000 is not set
849# CONFIG_ENC28J60 is not set 868# CONFIG_ENC28J60 is not set
850# CONFIG_ETHOC is not set 869# CONFIG_ETHOC is not set
@@ -881,6 +900,7 @@ CONFIG_LIBERTAS_USB=y
881CONFIG_LIBERTAS_SDIO=y 900CONFIG_LIBERTAS_SDIO=y
882# CONFIG_LIBERTAS_SPI is not set 901# CONFIG_LIBERTAS_SPI is not set
883CONFIG_LIBERTAS_DEBUG=y 902CONFIG_LIBERTAS_DEBUG=y
903# CONFIG_LIBERTAS_MESH is not set
884# CONFIG_P54_COMMON is not set 904# CONFIG_P54_COMMON is not set
885# CONFIG_RT2X00 is not set 905# CONFIG_RT2X00 is not set
886# CONFIG_WL12XX is not set 906# CONFIG_WL12XX is not set
@@ -902,6 +922,7 @@ CONFIG_USB_NET_AX8817X=y
902CONFIG_USB_NET_CDCETHER=y 922CONFIG_USB_NET_CDCETHER=y
903# CONFIG_USB_NET_CDC_EEM is not set 923# CONFIG_USB_NET_CDC_EEM is not set
904# CONFIG_USB_NET_DM9601 is not set 924# CONFIG_USB_NET_DM9601 is not set
925# CONFIG_USB_NET_SMSC75XX is not set
905# CONFIG_USB_NET_SMSC95XX is not set 926# CONFIG_USB_NET_SMSC95XX is not set
906# CONFIG_USB_NET_GL620A is not set 927# CONFIG_USB_NET_GL620A is not set
907CONFIG_USB_NET_NET1080=y 928CONFIG_USB_NET_NET1080=y
@@ -917,6 +938,8 @@ CONFIG_USB_EPSON2888=y
917CONFIG_USB_KC2190=y 938CONFIG_USB_KC2190=y
918CONFIG_USB_NET_ZAURUS=y 939CONFIG_USB_NET_ZAURUS=y
919# CONFIG_USB_NET_INT51X1 is not set 940# CONFIG_USB_NET_INT51X1 is not set
941# CONFIG_USB_IPHETH is not set
942# CONFIG_USB_SIERRA_NET is not set
920# CONFIG_WAN is not set 943# CONFIG_WAN is not set
921# CONFIG_PPP is not set 944# CONFIG_PPP is not set
922# CONFIG_SLIP is not set 945# CONFIG_SLIP is not set
@@ -1012,6 +1035,7 @@ CONFIG_INPUT_MISC=y
1012# CONFIG_INPUT_YEALINK is not set 1035# CONFIG_INPUT_YEALINK is not set
1013# CONFIG_INPUT_CM109 is not set 1036# CONFIG_INPUT_CM109 is not set
1014CONFIG_INPUT_TWL4030_PWRBUTTON=y 1037CONFIG_INPUT_TWL4030_PWRBUTTON=y
1038# CONFIG_INPUT_TWL4030_VIBRA is not set
1015# CONFIG_INPUT_UINPUT is not set 1039# CONFIG_INPUT_UINPUT is not set
1016# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set 1040# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
1017 1041
@@ -1055,6 +1079,7 @@ CONFIG_SERIAL_8250_RSA=y
1055# CONFIG_SERIAL_MAX3100 is not set 1079# CONFIG_SERIAL_MAX3100 is not set
1056CONFIG_SERIAL_CORE=y 1080CONFIG_SERIAL_CORE=y
1057CONFIG_SERIAL_CORE_CONSOLE=y 1081CONFIG_SERIAL_CORE_CONSOLE=y
1082# CONFIG_SERIAL_TIMBERDALE is not set
1058CONFIG_UNIX98_PTYS=y 1083CONFIG_UNIX98_PTYS=y
1059# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 1084# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
1060# CONFIG_LEGACY_PTYS is not set 1085# CONFIG_LEGACY_PTYS is not set
@@ -1083,6 +1108,7 @@ CONFIG_I2C_HELPER_AUTO=y
1083# CONFIG_I2C_OCORES is not set 1108# CONFIG_I2C_OCORES is not set
1084CONFIG_I2C_OMAP=y 1109CONFIG_I2C_OMAP=y
1085# CONFIG_I2C_SIMTEC is not set 1110# CONFIG_I2C_SIMTEC is not set
1111# CONFIG_I2C_XILINX is not set
1086 1112
1087# 1113#
1088# External I2C/SMBus adapter drivers 1114# External I2C/SMBus adapter drivers
@@ -1096,15 +1122,9 @@ CONFIG_I2C_OMAP=y
1096# 1122#
1097# CONFIG_I2C_PCA_PLATFORM is not set 1123# CONFIG_I2C_PCA_PLATFORM is not set
1098# CONFIG_I2C_STUB is not set 1124# CONFIG_I2C_STUB is not set
1099
1100#
1101# Miscellaneous I2C Chip support
1102#
1103# CONFIG_SENSORS_TSL2550 is not set
1104# CONFIG_I2C_DEBUG_CORE is not set 1125# CONFIG_I2C_DEBUG_CORE is not set
1105# CONFIG_I2C_DEBUG_ALGO is not set 1126# CONFIG_I2C_DEBUG_ALGO is not set
1106# CONFIG_I2C_DEBUG_BUS is not set 1127# CONFIG_I2C_DEBUG_BUS is not set
1107# CONFIG_I2C_DEBUG_CHIP is not set
1108CONFIG_SPI=y 1128CONFIG_SPI=y
1109# CONFIG_SPI_DEBUG is not set 1129# CONFIG_SPI_DEBUG is not set
1110CONFIG_SPI_MASTER=y 1130CONFIG_SPI_MASTER=y
@@ -1136,10 +1156,12 @@ CONFIG_GPIO_SYSFS=y
1136# 1156#
1137# Memory mapped GPIO expanders: 1157# Memory mapped GPIO expanders:
1138# 1158#
1159# CONFIG_GPIO_IT8761E is not set
1139 1160
1140# 1161#
1141# I2C GPIO expanders: 1162# I2C GPIO expanders:
1142# 1163#
1164# CONFIG_GPIO_MAX7300 is not set
1143# CONFIG_GPIO_MAX732X is not set 1165# CONFIG_GPIO_MAX732X is not set
1144# CONFIG_GPIO_PCA953X is not set 1166# CONFIG_GPIO_PCA953X is not set
1145# CONFIG_GPIO_PCF857X is not set 1167# CONFIG_GPIO_PCF857X is not set
@@ -1204,10 +1226,11 @@ CONFIG_HWMON=y
1204# CONFIG_SENSORS_ADM1029 is not set 1226# CONFIG_SENSORS_ADM1029 is not set
1205# CONFIG_SENSORS_ADM1031 is not set 1227# CONFIG_SENSORS_ADM1031 is not set
1206# CONFIG_SENSORS_ADM9240 is not set 1228# CONFIG_SENSORS_ADM9240 is not set
1229# CONFIG_SENSORS_ADT7411 is not set
1207# CONFIG_SENSORS_ADT7462 is not set 1230# CONFIG_SENSORS_ADT7462 is not set
1208# CONFIG_SENSORS_ADT7470 is not set 1231# CONFIG_SENSORS_ADT7470 is not set
1209# CONFIG_SENSORS_ADT7473 is not set
1210# CONFIG_SENSORS_ADT7475 is not set 1232# CONFIG_SENSORS_ADT7475 is not set
1233# CONFIG_SENSORS_ASC7621 is not set
1211# CONFIG_SENSORS_ATXP1 is not set 1234# CONFIG_SENSORS_ATXP1 is not set
1212# CONFIG_SENSORS_DS1621 is not set 1235# CONFIG_SENSORS_DS1621 is not set
1213# CONFIG_SENSORS_F71805F is not set 1236# CONFIG_SENSORS_F71805F is not set
@@ -1262,7 +1285,7 @@ CONFIG_HWMON=y
1262# CONFIG_SENSORS_LIS3_I2C is not set 1285# CONFIG_SENSORS_LIS3_I2C is not set
1263# CONFIG_THERMAL is not set 1286# CONFIG_THERMAL is not set
1264CONFIG_WATCHDOG=y 1287CONFIG_WATCHDOG=y
1265CONFIG_WATCHDOG_NOWAYOUT=y 1288# CONFIG_WATCHDOG_NOWAYOUT is not set
1266 1289
1267# 1290#
1268# Watchdog Device Drivers 1291# Watchdog Device Drivers
@@ -1270,6 +1293,7 @@ CONFIG_WATCHDOG_NOWAYOUT=y
1270# CONFIG_SOFT_WATCHDOG is not set 1293# CONFIG_SOFT_WATCHDOG is not set
1271CONFIG_OMAP_WATCHDOG=y 1294CONFIG_OMAP_WATCHDOG=y
1272CONFIG_TWL4030_WATCHDOG=y 1295CONFIG_TWL4030_WATCHDOG=y
1296# CONFIG_MAX63XX_WATCHDOG is not set
1273 1297
1274# 1298#
1275# USB-based Watchdog Cards 1299# USB-based Watchdog Cards
@@ -1286,14 +1310,16 @@ CONFIG_SSB_POSSIBLE=y
1286# Multifunction device drivers 1310# Multifunction device drivers
1287# 1311#
1288CONFIG_MFD_CORE=y 1312CONFIG_MFD_CORE=y
1313# CONFIG_MFD_88PM860X is not set
1289# CONFIG_MFD_SM501 is not set 1314# CONFIG_MFD_SM501 is not set
1290# CONFIG_MFD_ASIC3 is not set 1315# CONFIG_MFD_ASIC3 is not set
1291# CONFIG_HTC_EGPIO is not set 1316# CONFIG_HTC_EGPIO is not set
1292# CONFIG_HTC_PASIC3 is not set 1317# CONFIG_HTC_PASIC3 is not set
1318# CONFIG_HTC_I2CPLD is not set
1293# CONFIG_TPS65010 is not set 1319# CONFIG_TPS65010 is not set
1294# CONFIG_MENELAUS is not set 1320CONFIG_MENELAUS=y
1295CONFIG_TWL4030_CORE=y 1321CONFIG_TWL4030_CORE=y
1296# CONFIG_TWL4030_POWER is not set 1322CONFIG_TWL4030_POWER=y
1297CONFIG_TWL4030_CODEC=y 1323CONFIG_TWL4030_CODEC=y
1298# CONFIG_MFD_TMIO is not set 1324# CONFIG_MFD_TMIO is not set
1299# CONFIG_MFD_T7L66XB is not set 1325# CONFIG_MFD_T7L66XB is not set
@@ -1301,27 +1327,30 @@ CONFIG_TWL4030_CODEC=y
1301# CONFIG_MFD_TC6393XB is not set 1327# CONFIG_MFD_TC6393XB is not set
1302# CONFIG_PMIC_DA903X is not set 1328# CONFIG_PMIC_DA903X is not set
1303# CONFIG_PMIC_ADP5520 is not set 1329# CONFIG_PMIC_ADP5520 is not set
1330# CONFIG_MFD_MAX8925 is not set
1304# CONFIG_MFD_WM8400 is not set 1331# CONFIG_MFD_WM8400 is not set
1305# CONFIG_MFD_WM831X is not set 1332# CONFIG_MFD_WM831X is not set
1306# CONFIG_MFD_WM8350_I2C is not set 1333# CONFIG_MFD_WM8350_I2C is not set
1334# CONFIG_MFD_WM8994 is not set
1307# CONFIG_MFD_PCF50633 is not set 1335# CONFIG_MFD_PCF50633 is not set
1308# CONFIG_MFD_MC13783 is not set 1336# CONFIG_MFD_MC13783 is not set
1309# CONFIG_AB3100_CORE is not set 1337# CONFIG_AB3100_CORE is not set
1310# CONFIG_EZX_PCAP is not set 1338# CONFIG_EZX_PCAP is not set
1311# CONFIG_MFD_88PM8607 is not set
1312# CONFIG_AB4500_CORE is not set 1339# CONFIG_AB4500_CORE is not set
1313CONFIG_REGULATOR=y 1340CONFIG_REGULATOR=y
1314# CONFIG_REGULATOR_DEBUG is not set 1341# CONFIG_REGULATOR_DEBUG is not set
1315CONFIG_REGULATOR_FIXED_VOLTAGE=y 1342# CONFIG_REGULATOR_DUMMY is not set
1343# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
1316# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set 1344# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
1317# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set 1345# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
1318# CONFIG_REGULATOR_BQ24022 is not set 1346# CONFIG_REGULATOR_BQ24022 is not set
1319# CONFIG_REGULATOR_MAX1586 is not set 1347# CONFIG_REGULATOR_MAX1586 is not set
1348# CONFIG_REGULATOR_MAX8649 is not set
1320# CONFIG_REGULATOR_MAX8660 is not set 1349# CONFIG_REGULATOR_MAX8660 is not set
1321CONFIG_REGULATOR_TWL4030=y 1350CONFIG_REGULATOR_TWL4030=y
1322# CONFIG_REGULATOR_LP3971 is not set 1351# CONFIG_REGULATOR_LP3971 is not set
1323# CONFIG_REGULATOR_TPS65023 is not set 1352CONFIG_REGULATOR_TPS65023=y
1324# CONFIG_REGULATOR_TPS6507X is not set 1353CONFIG_REGULATOR_TPS6507X=y
1325# CONFIG_MEDIA_SUPPORT is not set 1354# CONFIG_MEDIA_SUPPORT is not set
1326 1355
1327# 1356#
@@ -1333,9 +1362,9 @@ CONFIG_FB=y
1333CONFIG_FIRMWARE_EDID=y 1362CONFIG_FIRMWARE_EDID=y
1334# CONFIG_FB_DDC is not set 1363# CONFIG_FB_DDC is not set
1335# CONFIG_FB_BOOT_VESA_SUPPORT is not set 1364# CONFIG_FB_BOOT_VESA_SUPPORT is not set
1336CONFIG_FB_CFB_FILLRECT=y 1365# CONFIG_FB_CFB_FILLRECT is not set
1337CONFIG_FB_CFB_COPYAREA=y 1366# CONFIG_FB_CFB_COPYAREA is not set
1338CONFIG_FB_CFB_IMAGEBLIT=y 1367# CONFIG_FB_CFB_IMAGEBLIT is not set
1339# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set 1368# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
1340# CONFIG_FB_SYS_FILLRECT is not set 1369# CONFIG_FB_SYS_FILLRECT is not set
1341# CONFIG_FB_SYS_COPYAREA is not set 1370# CONFIG_FB_SYS_COPYAREA is not set
@@ -1358,19 +1387,12 @@ CONFIG_FB_TILEBLITTING=y
1358# CONFIG_FB_METRONOME is not set 1387# CONFIG_FB_METRONOME is not set
1359# CONFIG_FB_MB862XX is not set 1388# CONFIG_FB_MB862XX is not set
1360# CONFIG_FB_BROADSHEET is not set 1389# CONFIG_FB_BROADSHEET is not set
1361CONFIG_FB_OMAP=y 1390# CONFIG_FB_OMAP is not set
1362CONFIG_FB_OMAP_LCD_VGA=y 1391CONFIG_FB_OMAP_LCD_VGA=y
1363# CONFIG_FB_OMAP_031M3R is not set
1364# CONFIG_FB_OMAP_048M3R is not set
1365CONFIG_FB_OMAP_079M3R=y
1366# CONFIG_FB_OMAP_092M9R is not set
1367# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
1368# CONFIG_FB_OMAP_LCD_MIPID is not set
1369# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
1370CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
1371# CONFIG_OMAP2_DSS is not set 1392# CONFIG_OMAP2_DSS is not set
1372CONFIG_BACKLIGHT_LCD_SUPPORT=y 1393CONFIG_BACKLIGHT_LCD_SUPPORT=y
1373CONFIG_LCD_CLASS_DEVICE=y 1394CONFIG_LCD_CLASS_DEVICE=y
1395# CONFIG_LCD_L4F00242T03 is not set
1374# CONFIG_LCD_LMS283GF05 is not set 1396# CONFIG_LCD_LMS283GF05 is not set
1375# CONFIG_LCD_LTV350QV is not set 1397# CONFIG_LCD_LTV350QV is not set
1376# CONFIG_LCD_ILI9320 is not set 1398# CONFIG_LCD_ILI9320 is not set
@@ -1448,6 +1470,7 @@ CONFIG_SND_ARM=y
1448CONFIG_SND_SPI=y 1470CONFIG_SND_SPI=y
1449CONFIG_SND_USB=y 1471CONFIG_SND_USB=y
1450CONFIG_SND_USB_AUDIO=y 1472CONFIG_SND_USB_AUDIO=y
1473# CONFIG_SND_USB_UA101 is not set
1451# CONFIG_SND_USB_CAIAQ is not set 1474# CONFIG_SND_USB_CAIAQ is not set
1452CONFIG_SND_SOC=y 1475CONFIG_SND_SOC=y
1453CONFIG_SND_OMAP_SOC=y 1476CONFIG_SND_OMAP_SOC=y
@@ -1479,6 +1502,7 @@ CONFIG_USB_HID=y
1479# 1502#
1480# Special HID drivers 1503# Special HID drivers
1481# 1504#
1505# CONFIG_HID_3M_PCT is not set
1482# CONFIG_HID_A4TECH is not set 1506# CONFIG_HID_A4TECH is not set
1483# CONFIG_HID_APPLE is not set 1507# CONFIG_HID_APPLE is not set
1484# CONFIG_HID_BELKIN is not set 1508# CONFIG_HID_BELKIN is not set
@@ -1492,13 +1516,18 @@ CONFIG_USB_HID=y
1492# CONFIG_HID_TWINHAN is not set 1516# CONFIG_HID_TWINHAN is not set
1493# CONFIG_HID_KENSINGTON is not set 1517# CONFIG_HID_KENSINGTON is not set
1494# CONFIG_HID_LOGITECH is not set 1518# CONFIG_HID_LOGITECH is not set
1519# CONFIG_HID_MAGICMOUSE is not set
1495# CONFIG_HID_MICROSOFT is not set 1520# CONFIG_HID_MICROSOFT is not set
1521# CONFIG_HID_MOSART is not set
1496# CONFIG_HID_MONTEREY is not set 1522# CONFIG_HID_MONTEREY is not set
1497# CONFIG_HID_NTRIG is not set 1523# CONFIG_HID_NTRIG is not set
1524# CONFIG_HID_ORTEK is not set
1498# CONFIG_HID_PANTHERLORD is not set 1525# CONFIG_HID_PANTHERLORD is not set
1499# CONFIG_HID_PETALYNX is not set 1526# CONFIG_HID_PETALYNX is not set
1527# CONFIG_HID_QUANTA is not set
1500# CONFIG_HID_SAMSUNG is not set 1528# CONFIG_HID_SAMSUNG is not set
1501# CONFIG_HID_SONY is not set 1529# CONFIG_HID_SONY is not set
1530# CONFIG_HID_STANTUM is not set
1502# CONFIG_HID_SUNPLUS is not set 1531# CONFIG_HID_SUNPLUS is not set
1503# CONFIG_HID_GREENASIA is not set 1532# CONFIG_HID_GREENASIA is not set
1504# CONFIG_HID_SMARTJOYPLUS is not set 1533# CONFIG_HID_SMARTJOYPLUS is not set
@@ -1545,6 +1574,10 @@ CONFIG_USB_MUSB_HDRC=y
1545CONFIG_USB_MUSB_SOC=y 1574CONFIG_USB_MUSB_SOC=y
1546 1575
1547# 1576#
1577# OMAP 243x high speed USB support
1578#
1579
1580#
1548# OMAP 343x high speed USB support 1581# OMAP 343x high speed USB support
1549# 1582#
1550# CONFIG_USB_MUSB_HOST is not set 1583# CONFIG_USB_MUSB_HOST is not set
@@ -1608,7 +1641,6 @@ CONFIG_USB_LIBUSUAL=y
1608# CONFIG_USB_RIO500 is not set 1641# CONFIG_USB_RIO500 is not set
1609# CONFIG_USB_LEGOTOWER is not set 1642# CONFIG_USB_LEGOTOWER is not set
1610# CONFIG_USB_LCD is not set 1643# CONFIG_USB_LCD is not set
1611# CONFIG_USB_BERRY_CHARGE is not set
1612# CONFIG_USB_LED is not set 1644# CONFIG_USB_LED is not set
1613# CONFIG_USB_CYPRESS_CY7C63 is not set 1645# CONFIG_USB_CYPRESS_CY7C63 is not set
1614# CONFIG_USB_CYTHERM is not set 1646# CONFIG_USB_CYTHERM is not set
@@ -1621,7 +1653,6 @@ CONFIG_USB_LIBUSUAL=y
1621# CONFIG_USB_IOWARRIOR is not set 1653# CONFIG_USB_IOWARRIOR is not set
1622CONFIG_USB_TEST=y 1654CONFIG_USB_TEST=y
1623# CONFIG_USB_ISIGHTFW is not set 1655# CONFIG_USB_ISIGHTFW is not set
1624# CONFIG_USB_VST is not set
1625CONFIG_USB_GADGET=y 1656CONFIG_USB_GADGET=y
1626CONFIG_USB_GADGET_DEBUG=y 1657CONFIG_USB_GADGET_DEBUG=y
1627CONFIG_USB_GADGET_DEBUG_FILES=y 1658CONFIG_USB_GADGET_DEBUG_FILES=y
@@ -1659,6 +1690,7 @@ CONFIG_USB_ZERO=m
1659# CONFIG_USB_MIDI_GADGET is not set 1690# CONFIG_USB_MIDI_GADGET is not set
1660# CONFIG_USB_G_PRINTER is not set 1691# CONFIG_USB_G_PRINTER is not set
1661# CONFIG_USB_CDC_COMPOSITE is not set 1692# CONFIG_USB_CDC_COMPOSITE is not set
1693# CONFIG_USB_G_NOKIA is not set
1662# CONFIG_USB_G_MULTI is not set 1694# CONFIG_USB_G_MULTI is not set
1663 1695
1664# 1696#
@@ -1686,10 +1718,8 @@ CONFIG_SDIO_UART=y
1686# MMC/SD/SDIO Host Controller Drivers 1718# MMC/SD/SDIO Host Controller Drivers
1687# 1719#
1688# CONFIG_MMC_SDHCI is not set 1720# CONFIG_MMC_SDHCI is not set
1689# CONFIG_MMC_OMAP is not set 1721CONFIG_MMC_OMAP=y
1690CONFIG_MMC_OMAP_HS=y 1722CONFIG_MMC_OMAP_HS=y
1691# CONFIG_MMC_AT91 is not set
1692# CONFIG_MMC_ATMELMCI is not set
1693# CONFIG_MMC_SPI is not set 1723# CONFIG_MMC_SPI is not set
1694# CONFIG_MEMSTICK is not set 1724# CONFIG_MEMSTICK is not set
1695CONFIG_NEW_LEDS=y 1725CONFIG_NEW_LEDS=y
@@ -1707,11 +1737,11 @@ CONFIG_LEDS_GPIO_PLATFORM=y
1707# CONFIG_LEDS_REGULATOR is not set 1737# CONFIG_LEDS_REGULATOR is not set
1708# CONFIG_LEDS_BD2802 is not set 1738# CONFIG_LEDS_BD2802 is not set
1709# CONFIG_LEDS_LT3593 is not set 1739# CONFIG_LEDS_LT3593 is not set
1740CONFIG_LEDS_TRIGGERS=y
1710 1741
1711# 1742#
1712# LED Triggers 1743# LED Triggers
1713# 1744#
1714CONFIG_LEDS_TRIGGERS=y
1715CONFIG_LEDS_TRIGGER_TIMER=y 1745CONFIG_LEDS_TRIGGER_TIMER=y
1716CONFIG_LEDS_TRIGGER_HEARTBEAT=y 1746CONFIG_LEDS_TRIGGER_HEARTBEAT=y
1717# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set 1747# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
@@ -1751,6 +1781,7 @@ CONFIG_RTC_INTF_DEV=y
1751# CONFIG_RTC_DRV_PCF8583 is not set 1781# CONFIG_RTC_DRV_PCF8583 is not set
1752# CONFIG_RTC_DRV_M41T80 is not set 1782# CONFIG_RTC_DRV_M41T80 is not set
1753# CONFIG_RTC_DRV_BQ32K is not set 1783# CONFIG_RTC_DRV_BQ32K is not set
1784CONFIG_RTC_DRV_TWL92330=y
1754CONFIG_RTC_DRV_TWL4030=y 1785CONFIG_RTC_DRV_TWL4030=y
1755# CONFIG_RTC_DRV_S35390A is not set 1786# CONFIG_RTC_DRV_S35390A is not set
1756# CONFIG_RTC_DRV_FM3130 is not set 1787# CONFIG_RTC_DRV_FM3130 is not set
@@ -1799,6 +1830,11 @@ CONFIG_RTC_DRV_TWL4030=y
1799# CONFIG_STAGING is not set 1830# CONFIG_STAGING is not set
1800 1831
1801# 1832#
1833# CBUS support
1834#
1835# CONFIG_CBUS is not set
1836
1837#
1802# File systems 1838# File systems
1803# 1839#
1804CONFIG_EXT2_FS=y 1840CONFIG_EXT2_FS=y
@@ -1826,6 +1862,7 @@ CONFIG_INOTIFY_USER=y
1826CONFIG_QUOTA=y 1862CONFIG_QUOTA=y
1827# CONFIG_QUOTA_NETLINK_INTERFACE is not set 1863# CONFIG_QUOTA_NETLINK_INTERFACE is not set
1828CONFIG_PRINT_QUOTA_WARNING=y 1864CONFIG_PRINT_QUOTA_WARNING=y
1865# CONFIG_QUOTA_DEBUG is not set
1829CONFIG_QUOTA_TREE=y 1866CONFIG_QUOTA_TREE=y
1830# CONFIG_QFMT_V1 is not set 1867# CONFIG_QFMT_V1 is not set
1831CONFIG_QFMT_V2=y 1868CONFIG_QFMT_V2=y
@@ -1897,6 +1934,7 @@ CONFIG_UBIFS_FS=y
1897CONFIG_UBIFS_FS_LZO=y 1934CONFIG_UBIFS_FS_LZO=y
1898CONFIG_UBIFS_FS_ZLIB=y 1935CONFIG_UBIFS_FS_ZLIB=y
1899# CONFIG_UBIFS_FS_DEBUG is not set 1936# CONFIG_UBIFS_FS_DEBUG is not set
1937# CONFIG_LOGFS is not set
1900CONFIG_CRAMFS=y 1938CONFIG_CRAMFS=y
1901# CONFIG_SQUASHFS is not set 1939# CONFIG_SQUASHFS is not set
1902# CONFIG_VXFS_FS is not set 1940# CONFIG_VXFS_FS is not set
@@ -1924,6 +1962,7 @@ CONFIG_SUNRPC_GSS=y
1924CONFIG_RPCSEC_GSS_KRB5=y 1962CONFIG_RPCSEC_GSS_KRB5=y
1925# CONFIG_RPCSEC_GSS_SPKM3 is not set 1963# CONFIG_RPCSEC_GSS_SPKM3 is not set
1926# CONFIG_SMB_FS is not set 1964# CONFIG_SMB_FS is not set
1965# CONFIG_CEPH_FS is not set
1927# CONFIG_CIFS is not set 1966# CONFIG_CIFS is not set
1928# CONFIG_NCP_FS is not set 1967# CONFIG_NCP_FS is not set
1929# CONFIG_CODA_FS is not set 1968# CONFIG_CODA_FS is not set
@@ -2024,6 +2063,7 @@ CONFIG_DEBUG_SPINLOCK=y
2024CONFIG_DEBUG_MUTEXES=y 2063CONFIG_DEBUG_MUTEXES=y
2025CONFIG_DEBUG_LOCK_ALLOC=y 2064CONFIG_DEBUG_LOCK_ALLOC=y
2026CONFIG_PROVE_LOCKING=y 2065CONFIG_PROVE_LOCKING=y
2066# CONFIG_PROVE_RCU is not set
2027CONFIG_LOCKDEP=y 2067CONFIG_LOCKDEP=y
2028CONFIG_LOCK_STAT=y 2068CONFIG_LOCK_STAT=y
2029# CONFIG_DEBUG_LOCKDEP is not set 2069# CONFIG_DEBUG_LOCKDEP is not set
@@ -2053,13 +2093,9 @@ CONFIG_DEBUG_INFO=y
2053# CONFIG_LATENCYTOP is not set 2093# CONFIG_LATENCYTOP is not set
2054# CONFIG_SYSCTL_SYSCALL_CHECK is not set 2094# CONFIG_SYSCTL_SYSCALL_CHECK is not set
2055# CONFIG_PAGE_POISONING is not set 2095# CONFIG_PAGE_POISONING is not set
2056CONFIG_NOP_TRACER=y
2057CONFIG_HAVE_FUNCTION_TRACER=y 2096CONFIG_HAVE_FUNCTION_TRACER=y
2058CONFIG_RING_BUFFER=y 2097CONFIG_RING_BUFFER=y
2059CONFIG_EVENT_TRACING=y
2060CONFIG_CONTEXT_SWITCH_TRACER=y
2061CONFIG_RING_BUFFER_ALLOW_SWAP=y 2098CONFIG_RING_BUFFER_ALLOW_SWAP=y
2062CONFIG_TRACING=y
2063CONFIG_TRACING_SUPPORT=y 2099CONFIG_TRACING_SUPPORT=y
2064CONFIG_FTRACE=y 2100CONFIG_FTRACE=y
2065# CONFIG_FUNCTION_TRACER is not set 2101# CONFIG_FUNCTION_TRACER is not set
@@ -2199,7 +2235,7 @@ CONFIG_CRYPTO_LZO=y
2199# 2235#
2200# CONFIG_CRYPTO_ANSI_CPRNG is not set 2236# CONFIG_CRYPTO_ANSI_CPRNG is not set
2201CONFIG_CRYPTO_HW=y 2237CONFIG_CRYPTO_HW=y
2202CONFIG_BINARY_PRINTF=y 2238# CONFIG_BINARY_PRINTF is not set
2203 2239
2204# 2240#
2205# Library routines 2241# Library routines
@@ -2222,3 +2258,4 @@ CONFIG_HAS_IOMEM=y
2222CONFIG_HAS_IOPORT=y 2258CONFIG_HAS_IOPORT=y
2223CONFIG_HAS_DMA=y 2259CONFIG_HAS_DMA=y
2224CONFIG_NLATTR=y 2260CONFIG_NLATTR=y
2261CONFIG_GENERIC_ATOMIC64=y
diff --git a/arch/arm/configs/omap3_stalker_lks_defconfig b/arch/arm/configs/omap3_stalker_lks_defconfig
new file mode 100644
index 000000000000..83365f075cea
--- /dev/null
+++ b/arch/arm/configs/omap3_stalker_lks_defconfig
@@ -0,0 +1,1691 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.34-rc7
4# Mon May 17 16:57:28 2010
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_HAVE_PROC_CPU=y
12CONFIG_GENERIC_HARDIRQS=y
13CONFIG_STACKTRACE_SUPPORT=y
14CONFIG_HAVE_LATENCYTOP_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20CONFIG_ARCH_HAS_CPUFREQ=y
21CONFIG_GENERIC_HWEIGHT=y
22CONFIG_GENERIC_CALIBRATE_DELAY=y
23CONFIG_NEED_DMA_MAP_STATE=y
24CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
25CONFIG_ARM_L1_CACHE_SHIFT_6=y
26CONFIG_VECTORS_BASE=0xffff0000
27CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
28CONFIG_CONSTRUCTORS=y
29
30#
31# General setup
32#
33CONFIG_EXPERIMENTAL=y
34CONFIG_BROKEN_ON_SMP=y
35CONFIG_INIT_ENV_ARG_LIMIT=32
36CONFIG_LOCALVERSION=""
37CONFIG_LOCALVERSION_AUTO=y
38CONFIG_HAVE_KERNEL_GZIP=y
39CONFIG_HAVE_KERNEL_LZO=y
40CONFIG_KERNEL_GZIP=y
41# CONFIG_KERNEL_BZIP2 is not set
42# CONFIG_KERNEL_LZMA is not set
43# CONFIG_KERNEL_LZO is not set
44CONFIG_SWAP=y
45CONFIG_SYSVIPC=y
46CONFIG_SYSVIPC_SYSCTL=y
47# CONFIG_POSIX_MQUEUE is not set
48CONFIG_BSD_PROCESS_ACCT=y
49# CONFIG_BSD_PROCESS_ACCT_V3 is not set
50# CONFIG_TASKSTATS is not set
51# CONFIG_AUDIT is not set
52
53#
54# RCU Subsystem
55#
56CONFIG_TREE_RCU=y
57# CONFIG_TREE_PREEMPT_RCU is not set
58# CONFIG_TINY_RCU is not set
59# CONFIG_RCU_TRACE is not set
60CONFIG_RCU_FANOUT=32
61# CONFIG_RCU_FANOUT_EXACT is not set
62# CONFIG_TREE_RCU_TRACE is not set
63# CONFIG_IKCONFIG is not set
64CONFIG_LOG_BUF_SHIFT=14
65# CONFIG_CGROUPS is not set
66# CONFIG_SYSFS_DEPRECATED_V2 is not set
67# CONFIG_RELAY is not set
68# CONFIG_NAMESPACES is not set
69CONFIG_BLK_DEV_INITRD=y
70CONFIG_INITRAMFS_SOURCE=""
71CONFIG_RD_GZIP=y
72# CONFIG_RD_BZIP2 is not set
73# CONFIG_RD_LZMA is not set
74# CONFIG_RD_LZO is not set
75CONFIG_CC_OPTIMIZE_FOR_SIZE=y
76CONFIG_SYSCTL=y
77CONFIG_ANON_INODES=y
78CONFIG_EMBEDDED=y
79CONFIG_UID16=y
80# CONFIG_SYSCTL_SYSCALL is not set
81CONFIG_KALLSYMS=y
82# CONFIG_KALLSYMS_ALL is not set
83CONFIG_KALLSYMS_EXTRA_PASS=y
84CONFIG_HOTPLUG=y
85CONFIG_PRINTK=y
86CONFIG_BUG=y
87CONFIG_ELF_CORE=y
88CONFIG_BASE_FULL=y
89CONFIG_FUTEX=y
90CONFIG_EPOLL=y
91CONFIG_SIGNALFD=y
92CONFIG_TIMERFD=y
93CONFIG_EVENTFD=y
94CONFIG_SHMEM=y
95CONFIG_AIO=y
96CONFIG_HAVE_PERF_EVENTS=y
97CONFIG_PERF_USE_VMALLOC=y
98
99#
100# Kernel Performance Events And Counters
101#
102# CONFIG_PERF_EVENTS is not set
103# CONFIG_PERF_COUNTERS is not set
104CONFIG_VM_EVENT_COUNTERS=y
105CONFIG_COMPAT_BRK=y
106CONFIG_SLAB=y
107# CONFIG_SLUB is not set
108# CONFIG_SLOB is not set
109# CONFIG_PROFILING is not set
110CONFIG_HAVE_OPROFILE=y
111# CONFIG_KPROBES is not set
112CONFIG_HAVE_KPROBES=y
113CONFIG_HAVE_KRETPROBES=y
114CONFIG_HAVE_CLK=y
115
116#
117# GCOV-based kernel profiling
118#
119# CONFIG_GCOV_KERNEL is not set
120# CONFIG_SLOW_WORK is not set
121CONFIG_HAVE_GENERIC_DMA_COHERENT=y
122CONFIG_SLABINFO=y
123CONFIG_RT_MUTEXES=y
124CONFIG_BASE_SMALL=0
125CONFIG_MODULES=y
126# CONFIG_MODULE_FORCE_LOAD is not set
127CONFIG_MODULE_UNLOAD=y
128# CONFIG_MODULE_FORCE_UNLOAD is not set
129CONFIG_MODVERSIONS=y
130CONFIG_MODULE_SRCVERSION_ALL=y
131CONFIG_BLOCK=y
132CONFIG_LBDAF=y
133# CONFIG_BLK_DEV_BSG is not set
134# CONFIG_BLK_DEV_INTEGRITY is not set
135
136#
137# IO Schedulers
138#
139CONFIG_IOSCHED_NOOP=y
140CONFIG_IOSCHED_DEADLINE=y
141CONFIG_IOSCHED_CFQ=y
142# CONFIG_DEFAULT_DEADLINE is not set
143CONFIG_DEFAULT_CFQ=y
144# CONFIG_DEFAULT_NOOP is not set
145CONFIG_DEFAULT_IOSCHED="cfq"
146# CONFIG_INLINE_SPIN_TRYLOCK is not set
147# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
148# CONFIG_INLINE_SPIN_LOCK is not set
149# CONFIG_INLINE_SPIN_LOCK_BH is not set
150# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
151# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
152CONFIG_INLINE_SPIN_UNLOCK=y
153# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
154CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
155# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
156# CONFIG_INLINE_READ_TRYLOCK is not set
157# CONFIG_INLINE_READ_LOCK is not set
158# CONFIG_INLINE_READ_LOCK_BH is not set
159# CONFIG_INLINE_READ_LOCK_IRQ is not set
160# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
161CONFIG_INLINE_READ_UNLOCK=y
162# CONFIG_INLINE_READ_UNLOCK_BH is not set
163CONFIG_INLINE_READ_UNLOCK_IRQ=y
164# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
165# CONFIG_INLINE_WRITE_TRYLOCK is not set
166# CONFIG_INLINE_WRITE_LOCK is not set
167# CONFIG_INLINE_WRITE_LOCK_BH is not set
168# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
169# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
170CONFIG_INLINE_WRITE_UNLOCK=y
171# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
172CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
173# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
174# CONFIG_MUTEX_SPIN_ON_OWNER is not set
175CONFIG_FREEZER=y
176
177#
178# System Type
179#
180CONFIG_MMU=y
181# CONFIG_ARCH_AAEC2000 is not set
182# CONFIG_ARCH_INTEGRATOR is not set
183# CONFIG_ARCH_REALVIEW is not set
184# CONFIG_ARCH_VERSATILE is not set
185# CONFIG_ARCH_AT91 is not set
186# CONFIG_ARCH_BCMRING is not set
187# CONFIG_ARCH_CLPS711X is not set
188# CONFIG_ARCH_GEMINI is not set
189# CONFIG_ARCH_EBSA110 is not set
190# CONFIG_ARCH_EP93XX is not set
191# CONFIG_ARCH_FOOTBRIDGE is not set
192# CONFIG_ARCH_MXC is not set
193# CONFIG_ARCH_STMP3XXX is not set
194# CONFIG_ARCH_NETX is not set
195# CONFIG_ARCH_H720X is not set
196# CONFIG_ARCH_IOP13XX is not set
197# CONFIG_ARCH_IOP32X is not set
198# CONFIG_ARCH_IOP33X is not set
199# CONFIG_ARCH_IXP23XX is not set
200# CONFIG_ARCH_IXP2000 is not set
201# CONFIG_ARCH_IXP4XX is not set
202# CONFIG_ARCH_L7200 is not set
203# CONFIG_ARCH_DOVE is not set
204# CONFIG_ARCH_KIRKWOOD is not set
205# CONFIG_ARCH_LOKI is not set
206# CONFIG_ARCH_MV78XX0 is not set
207# CONFIG_ARCH_ORION5X is not set
208# CONFIG_ARCH_MMP is not set
209# CONFIG_ARCH_KS8695 is not set
210# CONFIG_ARCH_NS9XXX is not set
211# CONFIG_ARCH_W90X900 is not set
212# CONFIG_ARCH_NUC93X is not set
213# CONFIG_ARCH_PNX4008 is not set
214# CONFIG_ARCH_PXA is not set
215# CONFIG_ARCH_MSM is not set
216# CONFIG_ARCH_SHMOBILE is not set
217# CONFIG_ARCH_RPC is not set
218# CONFIG_ARCH_SA1100 is not set
219# CONFIG_ARCH_S3C2410 is not set
220# CONFIG_ARCH_S3C64XX is not set
221# CONFIG_ARCH_S5P6440 is not set
222# CONFIG_ARCH_S5P6442 is not set
223# CONFIG_ARCH_S5PC1XX is not set
224# CONFIG_ARCH_S5PV210 is not set
225# CONFIG_ARCH_SHARK is not set
226# CONFIG_ARCH_LH7A40X is not set
227# CONFIG_ARCH_U300 is not set
228# CONFIG_ARCH_U8500 is not set
229# CONFIG_ARCH_NOMADIK is not set
230# CONFIG_ARCH_DAVINCI is not set
231CONFIG_ARCH_OMAP=y
232
233#
234# TI OMAP Implementations
235#
236CONFIG_ARCH_OMAP_OTG=y
237# CONFIG_ARCH_OMAP1 is not set
238CONFIG_ARCH_OMAP2PLUS=y
239# CONFIG_ARCH_OMAP2 is not set
240CONFIG_ARCH_OMAP3=y
241# CONFIG_ARCH_OMAP4 is not set
242
243#
244# OMAP Feature Selections
245#
246CONFIG_OMAP_RESET_CLOCKS=y
247CONFIG_OMAP_MUX=y
248# CONFIG_OMAP_MUX_DEBUG is not set
249CONFIG_OMAP_MUX_WARNINGS=y
250# CONFIG_OMAP_MCBSP is not set
251# CONFIG_OMAP_MBOX_FWK is not set
252# CONFIG_OMAP_MPU_TIMER is not set
253CONFIG_OMAP_32K_TIMER=y
254# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set
255CONFIG_OMAP_32K_TIMER_HZ=128
256CONFIG_OMAP_DM_TIMER=y
257# CONFIG_OMAP_PM_NONE is not set
258CONFIG_OMAP_PM_NOOP=y
259CONFIG_ARCH_OMAP3430=y
260CONFIG_OMAP_PACKAGE_CUS=y
261
262#
263# OMAP Board Type
264#
265# CONFIG_MACH_OMAP3_BEAGLE is not set
266# CONFIG_MACH_DEVKIT8000 is not set
267# CONFIG_MACH_OMAP_LDP is not set
268# CONFIG_MACH_OVERO is not set
269# CONFIG_MACH_OMAP3EVM is not set
270# CONFIG_MACH_OMAP3517EVM is not set
271# CONFIG_MACH_OMAP3_PANDORA is not set
272# CONFIG_MACH_OMAP3_TOUCHBOOK is not set
273# CONFIG_MACH_OMAP_3430SDP is not set
274# CONFIG_MACH_NOKIA_RX51 is not set
275# CONFIG_MACH_OMAP_ZOOM2 is not set
276# CONFIG_MACH_OMAP_ZOOM3 is not set
277# CONFIG_MACH_CM_T35 is not set
278# CONFIG_MACH_IGEP0020 is not set
279CONFIG_MACH_SBC3530=y
280# CONFIG_MACH_OMAP_3630SDP is not set
281# CONFIG_OMAP3_EMU is not set
282# CONFIG_OMAP3_SDRC_AC_TIMING is not set
283
284#
285# Processor Type
286#
287CONFIG_CPU_32v6K=y
288CONFIG_CPU_V7=y
289CONFIG_CPU_32v7=y
290CONFIG_CPU_ABRT_EV7=y
291CONFIG_CPU_PABRT_V7=y
292CONFIG_CPU_CACHE_V7=y
293CONFIG_CPU_CACHE_VIPT=y
294CONFIG_CPU_COPY_V6=y
295CONFIG_CPU_TLB_V7=y
296CONFIG_CPU_HAS_ASID=y
297CONFIG_CPU_CP15=y
298CONFIG_CPU_CP15_MMU=y
299
300#
301# Processor Features
302#
303CONFIG_ARM_THUMB=y
304# CONFIG_ARM_THUMBEE is not set
305# CONFIG_CPU_ICACHE_DISABLE is not set
306# CONFIG_CPU_DCACHE_DISABLE is not set
307# CONFIG_CPU_BPREDICT_DISABLE is not set
308CONFIG_HAS_TLS_REG=y
309CONFIG_ARM_L1_CACHE_SHIFT=6
310CONFIG_CPU_HAS_PMU=y
311# CONFIG_ARM_ERRATA_430973 is not set
312# CONFIG_ARM_ERRATA_458693 is not set
313# CONFIG_ARM_ERRATA_460075 is not set
314CONFIG_COMMON_CLKDEV=y
315
316#
317# Bus support
318#
319# CONFIG_PCI_SYSCALL is not set
320# CONFIG_ARCH_SUPPORTS_MSI is not set
321# CONFIG_PCCARD is not set
322
323#
324# Kernel Features
325#
326CONFIG_TICK_ONESHOT=y
327CONFIG_NO_HZ=y
328CONFIG_HIGH_RES_TIMERS=y
329CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
330CONFIG_VMSPLIT_3G=y
331# CONFIG_VMSPLIT_2G is not set
332# CONFIG_VMSPLIT_1G is not set
333CONFIG_PAGE_OFFSET=0xC0000000
334CONFIG_PREEMPT_NONE=y
335# CONFIG_PREEMPT_VOLUNTARY is not set
336# CONFIG_PREEMPT is not set
337CONFIG_HZ=128
338# CONFIG_THUMB2_KERNEL is not set
339CONFIG_AEABI=y
340CONFIG_OABI_COMPAT=y
341CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
342# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
343# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
344# CONFIG_HIGHMEM is not set
345CONFIG_SELECT_MEMORY_MODEL=y
346CONFIG_FLATMEM_MANUAL=y
347# CONFIG_DISCONTIGMEM_MANUAL is not set
348# CONFIG_SPARSEMEM_MANUAL is not set
349CONFIG_FLATMEM=y
350CONFIG_FLAT_NODE_MEM_MAP=y
351CONFIG_PAGEFLAGS_EXTENDED=y
352CONFIG_SPLIT_PTLOCK_CPUS=4
353# CONFIG_PHYS_ADDR_T_64BIT is not set
354CONFIG_ZONE_DMA_FLAG=0
355CONFIG_VIRT_TO_BUS=y
356# CONFIG_KSM is not set
357CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
358# CONFIG_LEDS is not set
359CONFIG_ALIGNMENT_TRAP=y
360# CONFIG_UACCESS_WITH_MEMCPY is not set
361
362#
363# Boot options
364#
365CONFIG_ZBOOT_ROM_TEXT=0x0
366CONFIG_ZBOOT_ROM_BSS=0x0
367CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8"
368# CONFIG_XIP_KERNEL is not set
369# CONFIG_KEXEC is not set
370
371#
372# CPU Power Management
373#
374# CONFIG_CPU_FREQ is not set
375# CONFIG_CPU_IDLE is not set
376
377#
378# Floating point emulation
379#
380
381#
382# At least one emulation must be selected
383#
384CONFIG_FPE_NWFPE=y
385# CONFIG_FPE_NWFPE_XP is not set
386# CONFIG_FPE_FASTFPE is not set
387CONFIG_VFP=y
388CONFIG_VFPv3=y
389CONFIG_NEON=y
390
391#
392# Userspace binary formats
393#
394CONFIG_BINFMT_ELF=y
395# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
396CONFIG_HAVE_AOUT=y
397# CONFIG_BINFMT_AOUT is not set
398CONFIG_BINFMT_MISC=y
399
400#
401# Power management options
402#
403CONFIG_PM=y
404CONFIG_PM_DEBUG=y
405# CONFIG_PM_ADVANCED_DEBUG is not set
406# CONFIG_PM_VERBOSE is not set
407CONFIG_CAN_PM_TRACE=y
408CONFIG_PM_SLEEP=y
409CONFIG_SUSPEND=y
410CONFIG_SUSPEND_FREEZER=y
411# CONFIG_APM_EMULATION is not set
412# CONFIG_PM_RUNTIME is not set
413CONFIG_PM_OPS=y
414CONFIG_ARCH_SUSPEND_POSSIBLE=y
415CONFIG_NET=y
416
417#
418# Networking options
419#
420CONFIG_PACKET=y
421CONFIG_UNIX=y
422CONFIG_XFRM=y
423# CONFIG_XFRM_USER is not set
424# CONFIG_XFRM_SUB_POLICY is not set
425# CONFIG_XFRM_MIGRATE is not set
426# CONFIG_XFRM_STATISTICS is not set
427CONFIG_NET_KEY=y
428# CONFIG_NET_KEY_MIGRATE is not set
429CONFIG_INET=y
430# CONFIG_IP_MULTICAST is not set
431# CONFIG_IP_ADVANCED_ROUTER is not set
432CONFIG_IP_FIB_HASH=y
433CONFIG_IP_PNP=y
434CONFIG_IP_PNP_DHCP=y
435CONFIG_IP_PNP_BOOTP=y
436CONFIG_IP_PNP_RARP=y
437# CONFIG_NET_IPIP is not set
438# CONFIG_NET_IPGRE is not set
439# CONFIG_ARPD is not set
440# CONFIG_SYN_COOKIES is not set
441# CONFIG_INET_AH is not set
442# CONFIG_INET_ESP is not set
443# CONFIG_INET_IPCOMP is not set
444# CONFIG_INET_XFRM_TUNNEL is not set
445# CONFIG_INET_TUNNEL is not set
446CONFIG_INET_XFRM_MODE_TRANSPORT=y
447CONFIG_INET_XFRM_MODE_TUNNEL=y
448CONFIG_INET_XFRM_MODE_BEET=y
449# CONFIG_INET_LRO is not set
450CONFIG_INET_DIAG=y
451CONFIG_INET_TCP_DIAG=y
452# CONFIG_TCP_CONG_ADVANCED is not set
453CONFIG_TCP_CONG_CUBIC=y
454CONFIG_DEFAULT_TCP_CONG="cubic"
455# CONFIG_TCP_MD5SIG is not set
456# CONFIG_IPV6 is not set
457# CONFIG_NETWORK_SECMARK is not set
458# CONFIG_NETFILTER is not set
459# CONFIG_IP_DCCP is not set
460# CONFIG_IP_SCTP is not set
461# CONFIG_RDS is not set
462# CONFIG_TIPC is not set
463# CONFIG_ATM is not set
464# CONFIG_BRIDGE is not set
465# CONFIG_NET_DSA is not set
466# CONFIG_VLAN_8021Q is not set
467# CONFIG_DECNET is not set
468# CONFIG_LLC2 is not set
469# CONFIG_IPX is not set
470# CONFIG_ATALK is not set
471# CONFIG_X25 is not set
472# CONFIG_LAPB is not set
473# CONFIG_ECONET is not set
474# CONFIG_WAN_ROUTER is not set
475# CONFIG_PHONET is not set
476# CONFIG_IEEE802154 is not set
477# CONFIG_NET_SCHED is not set
478# CONFIG_DCB is not set
479
480#
481# Network testing
482#
483# CONFIG_NET_PKTGEN is not set
484# CONFIG_HAMRADIO is not set
485# CONFIG_CAN is not set
486# CONFIG_IRDA is not set
487# CONFIG_BT is not set
488# CONFIG_AF_RXRPC is not set
489CONFIG_WIRELESS=y
490# CONFIG_CFG80211 is not set
491# CONFIG_LIB80211 is not set
492
493#
494# CFG80211 needs to be enabled for MAC80211
495#
496# CONFIG_WIMAX is not set
497# CONFIG_RFKILL is not set
498# CONFIG_NET_9P is not set
499
500#
501# Device Drivers
502#
503
504#
505# Generic Driver Options
506#
507CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
508# CONFIG_DEVTMPFS is not set
509CONFIG_STANDALONE=y
510CONFIG_PREVENT_FIRMWARE_BUILD=y
511# CONFIG_FW_LOADER is not set
512# CONFIG_DEBUG_DRIVER is not set
513# CONFIG_DEBUG_DEVRES is not set
514# CONFIG_SYS_HYPERVISOR is not set
515# CONFIG_CONNECTOR is not set
516CONFIG_MTD=y
517# CONFIG_MTD_DEBUG is not set
518# CONFIG_MTD_TESTS is not set
519CONFIG_MTD_CONCAT=y
520CONFIG_MTD_PARTITIONS=y
521# CONFIG_MTD_REDBOOT_PARTS is not set
522CONFIG_MTD_CMDLINE_PARTS=y
523# CONFIG_MTD_AFS_PARTS is not set
524# CONFIG_MTD_AR7_PARTS is not set
525
526#
527# User Modules And Translation Layers
528#
529CONFIG_MTD_CHAR=y
530CONFIG_MTD_BLKDEVS=y
531CONFIG_MTD_BLOCK=y
532# CONFIG_FTL is not set
533# CONFIG_NFTL is not set
534# CONFIG_INFTL is not set
535# CONFIG_RFD_FTL is not set
536# CONFIG_SSFDC is not set
537# CONFIG_MTD_OOPS is not set
538
539#
540# RAM/ROM/Flash chip drivers
541#
542CONFIG_MTD_CFI=y
543# CONFIG_MTD_JEDECPROBE is not set
544CONFIG_MTD_GEN_PROBE=y
545# CONFIG_MTD_CFI_ADV_OPTIONS is not set
546CONFIG_MTD_MAP_BANK_WIDTH_1=y
547CONFIG_MTD_MAP_BANK_WIDTH_2=y
548CONFIG_MTD_MAP_BANK_WIDTH_4=y
549# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
550# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
551# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
552CONFIG_MTD_CFI_I1=y
553CONFIG_MTD_CFI_I2=y
554# CONFIG_MTD_CFI_I4 is not set
555# CONFIG_MTD_CFI_I8 is not set
556CONFIG_MTD_CFI_INTELEXT=y
557# CONFIG_MTD_CFI_AMDSTD is not set
558# CONFIG_MTD_CFI_STAA is not set
559CONFIG_MTD_CFI_UTIL=y
560# CONFIG_MTD_RAM is not set
561# CONFIG_MTD_ROM is not set
562# CONFIG_MTD_ABSENT is not set
563
564#
565# Mapping drivers for chip access
566#
567# CONFIG_MTD_COMPLEX_MAPPINGS is not set
568# CONFIG_MTD_PHYSMAP is not set
569# CONFIG_MTD_ARM_INTEGRATOR is not set
570# CONFIG_MTD_PLATRAM is not set
571
572#
573# Self-contained MTD device drivers
574#
575# CONFIG_MTD_DATAFLASH is not set
576# CONFIG_MTD_M25P80 is not set
577# CONFIG_MTD_SST25L is not set
578# CONFIG_MTD_SLRAM is not set
579# CONFIG_MTD_PHRAM is not set
580# CONFIG_MTD_MTDRAM is not set
581# CONFIG_MTD_BLOCK2MTD is not set
582
583#
584# Disk-On-Chip Device Drivers
585#
586# CONFIG_MTD_DOC2000 is not set
587# CONFIG_MTD_DOC2001 is not set
588# CONFIG_MTD_DOC2001PLUS is not set
589CONFIG_MTD_NAND=y
590# CONFIG_MTD_NAND_VERIFY_WRITE is not set
591# CONFIG_MTD_NAND_ECC_SMC is not set
592# CONFIG_MTD_NAND_MUSEUM_IDS is not set
593# CONFIG_MTD_NAND_GPIO is not set
594# CONFIG_MTD_NAND_OMAP2 is not set
595CONFIG_MTD_NAND_IDS=y
596# CONFIG_MTD_NAND_DISKONCHIP is not set
597# CONFIG_MTD_NAND_NANDSIM is not set
598# CONFIG_MTD_NAND_PLATFORM is not set
599# CONFIG_MTD_ALAUDA is not set
600CONFIG_MTD_ONENAND=y
601CONFIG_MTD_ONENAND_VERIFY_WRITE=y
602# CONFIG_MTD_ONENAND_GENERIC is not set
603CONFIG_MTD_ONENAND_OMAP2=y
604# CONFIG_MTD_ONENAND_OTP is not set
605# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
606# CONFIG_MTD_ONENAND_SIM is not set
607
608#
609# LPDDR flash memory drivers
610#
611# CONFIG_MTD_LPDDR is not set
612
613#
614# UBI - Unsorted block images
615#
616# CONFIG_MTD_UBI is not set
617# CONFIG_PARPORT is not set
618CONFIG_BLK_DEV=y
619# CONFIG_BLK_DEV_COW_COMMON is not set
620CONFIG_BLK_DEV_LOOP=y
621# CONFIG_BLK_DEV_CRYPTOLOOP is not set
622
623#
624# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
625#
626# CONFIG_BLK_DEV_NBD is not set
627# CONFIG_BLK_DEV_UB is not set
628CONFIG_BLK_DEV_RAM=y
629CONFIG_BLK_DEV_RAM_COUNT=16
630CONFIG_BLK_DEV_RAM_SIZE=16384
631# CONFIG_BLK_DEV_XIP is not set
632# CONFIG_CDROM_PKTCDVD is not set
633# CONFIG_ATA_OVER_ETH is not set
634# CONFIG_MG_DISK is not set
635# CONFIG_MISC_DEVICES is not set
636CONFIG_HAVE_IDE=y
637# CONFIG_IDE is not set
638
639#
640# SCSI device support
641#
642CONFIG_SCSI_MOD=y
643# CONFIG_RAID_ATTRS is not set
644CONFIG_SCSI=y
645CONFIG_SCSI_DMA=y
646# CONFIG_SCSI_TGT is not set
647# CONFIG_SCSI_NETLINK is not set
648CONFIG_SCSI_PROC_FS=y
649
650#
651# SCSI support type (disk, tape, CD-ROM)
652#
653CONFIG_BLK_DEV_SD=y
654# CONFIG_CHR_DEV_ST is not set
655# CONFIG_CHR_DEV_OSST is not set
656# CONFIG_BLK_DEV_SR is not set
657# CONFIG_CHR_DEV_SG is not set
658# CONFIG_CHR_DEV_SCH is not set
659# CONFIG_SCSI_MULTI_LUN is not set
660# CONFIG_SCSI_CONSTANTS is not set
661# CONFIG_SCSI_LOGGING is not set
662# CONFIG_SCSI_SCAN_ASYNC is not set
663CONFIG_SCSI_WAIT_SCAN=m
664
665#
666# SCSI Transports
667#
668# CONFIG_SCSI_SPI_ATTRS is not set
669# CONFIG_SCSI_FC_ATTRS is not set
670# CONFIG_SCSI_ISCSI_ATTRS is not set
671# CONFIG_SCSI_SAS_LIBSAS is not set
672# CONFIG_SCSI_SRP_ATTRS is not set
673CONFIG_SCSI_LOWLEVEL=y
674# CONFIG_ISCSI_TCP is not set
675# CONFIG_LIBFC is not set
676# CONFIG_LIBFCOE is not set
677# CONFIG_SCSI_DEBUG is not set
678# CONFIG_SCSI_DH is not set
679# CONFIG_SCSI_OSD_INITIATOR is not set
680# CONFIG_ATA is not set
681# CONFIG_MD is not set
682CONFIG_NETDEVICES=y
683# CONFIG_DUMMY is not set
684# CONFIG_BONDING is not set
685# CONFIG_MACVLAN is not set
686# CONFIG_EQUALIZER is not set
687# CONFIG_TUN is not set
688# CONFIG_VETH is not set
689CONFIG_PHYLIB=y
690
691#
692# MII PHY device drivers
693#
694# CONFIG_MARVELL_PHY is not set
695# CONFIG_DAVICOM_PHY is not set
696# CONFIG_QSEMI_PHY is not set
697# CONFIG_LXT_PHY is not set
698# CONFIG_CICADA_PHY is not set
699# CONFIG_VITESSE_PHY is not set
700# CONFIG_SMSC_PHY is not set
701# CONFIG_BROADCOM_PHY is not set
702# CONFIG_ICPLUS_PHY is not set
703# CONFIG_REALTEK_PHY is not set
704# CONFIG_NATIONAL_PHY is not set
705# CONFIG_STE10XP is not set
706# CONFIG_LSI_ET1011C_PHY is not set
707# CONFIG_MICREL_PHY is not set
708# CONFIG_FIXED_PHY is not set
709# CONFIG_MDIO_BITBANG is not set
710CONFIG_NET_ETHERNET=y
711CONFIG_MII=y
712# CONFIG_AX88796 is not set
713# CONFIG_SMC91X is not set
714# CONFIG_TI_DAVINCI_EMAC is not set
715# CONFIG_DM9000 is not set
716# CONFIG_ENC28J60 is not set
717# CONFIG_ETHOC is not set
718# CONFIG_SMC911X is not set
719CONFIG_SMSC911X=y
720# CONFIG_DNET is not set
721# CONFIG_IBM_NEW_EMAC_ZMII is not set
722# CONFIG_IBM_NEW_EMAC_RGMII is not set
723# CONFIG_IBM_NEW_EMAC_TAH is not set
724# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
725# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
726# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
727# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
728# CONFIG_B44 is not set
729# CONFIG_KS8842 is not set
730# CONFIG_KS8851 is not set
731# CONFIG_KS8851_MLL is not set
732# CONFIG_NETDEV_1000 is not set
733# CONFIG_NETDEV_10000 is not set
734CONFIG_WLAN=y
735# CONFIG_USB_ZD1201 is not set
736# CONFIG_HOSTAP is not set
737
738#
739# Enable WiMAX (Networking options) to see the WiMAX drivers
740#
741
742#
743# USB Network Adapters
744#
745# CONFIG_USB_CATC is not set
746# CONFIG_USB_KAWETH is not set
747# CONFIG_USB_PEGASUS is not set
748# CONFIG_USB_RTL8150 is not set
749# CONFIG_USB_USBNET is not set
750# CONFIG_USB_IPHETH is not set
751# CONFIG_WAN is not set
752# CONFIG_PPP is not set
753# CONFIG_SLIP is not set
754# CONFIG_NETCONSOLE is not set
755# CONFIG_NETPOLL is not set
756# CONFIG_NET_POLL_CONTROLLER is not set
757# CONFIG_ISDN is not set
758# CONFIG_PHONE is not set
759
760#
761# Input device support
762#
763CONFIG_INPUT=y
764# CONFIG_INPUT_FF_MEMLESS is not set
765# CONFIG_INPUT_POLLDEV is not set
766# CONFIG_INPUT_SPARSEKMAP is not set
767
768#
769# Userland interfaces
770#
771# CONFIG_INPUT_MOUSEDEV is not set
772# CONFIG_INPUT_JOYDEV is not set
773CONFIG_INPUT_EVDEV=y
774# CONFIG_INPUT_EVBUG is not set
775
776#
777# Input Device Drivers
778#
779CONFIG_INPUT_KEYBOARD=y
780# CONFIG_KEYBOARD_ADP5588 is not set
781# CONFIG_KEYBOARD_ATKBD is not set
782# CONFIG_QT2160 is not set
783# CONFIG_KEYBOARD_LKKBD is not set
784# CONFIG_KEYBOARD_GPIO is not set
785# CONFIG_KEYBOARD_MATRIX is not set
786# CONFIG_KEYBOARD_MAX7359 is not set
787# CONFIG_KEYBOARD_NEWTON is not set
788# CONFIG_KEYBOARD_OPENCORES is not set
789# CONFIG_KEYBOARD_STOWAWAY is not set
790# CONFIG_KEYBOARD_SUNKBD is not set
791CONFIG_KEYBOARD_TWL4030=y
792# CONFIG_KEYBOARD_XTKBD is not set
793# CONFIG_INPUT_MOUSE is not set
794# CONFIG_INPUT_JOYSTICK is not set
795# CONFIG_INPUT_TABLET is not set
796CONFIG_INPUT_TOUCHSCREEN=y
797CONFIG_TOUCHSCREEN_ADS7846=y
798# CONFIG_TOUCHSCREEN_AD7877 is not set
799# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
800# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
801# CONFIG_TOUCHSCREEN_AD7879 is not set
802# CONFIG_TOUCHSCREEN_DYNAPRO is not set
803# CONFIG_TOUCHSCREEN_EETI is not set
804# CONFIG_TOUCHSCREEN_FUJITSU is not set
805# CONFIG_TOUCHSCREEN_GUNZE is not set
806# CONFIG_TOUCHSCREEN_ELO is not set
807# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
808# CONFIG_TOUCHSCREEN_MCS5000 is not set
809# CONFIG_TOUCHSCREEN_MTOUCH is not set
810# CONFIG_TOUCHSCREEN_INEXIO is not set
811# CONFIG_TOUCHSCREEN_MK712 is not set
812# CONFIG_TOUCHSCREEN_PENMOUNT is not set
813# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
814# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
815# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
816# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
817# CONFIG_TOUCHSCREEN_TSC2007 is not set
818# CONFIG_TOUCHSCREEN_W90X900 is not set
819# CONFIG_INPUT_MISC is not set
820
821#
822# Hardware I/O ports
823#
824# CONFIG_SERIO is not set
825# CONFIG_GAMEPORT is not set
826
827#
828# Character devices
829#
830CONFIG_VT=y
831CONFIG_CONSOLE_TRANSLATIONS=y
832CONFIG_VT_CONSOLE=y
833CONFIG_HW_CONSOLE=y
834# CONFIG_VT_HW_CONSOLE_BINDING is not set
835CONFIG_DEVKMEM=y
836# CONFIG_SERIAL_NONSTANDARD is not set
837
838#
839# Serial drivers
840#
841CONFIG_SERIAL_8250=y
842CONFIG_SERIAL_8250_CONSOLE=y
843CONFIG_SERIAL_8250_NR_UARTS=32
844CONFIG_SERIAL_8250_RUNTIME_UARTS=4
845CONFIG_SERIAL_8250_EXTENDED=y
846CONFIG_SERIAL_8250_MANY_PORTS=y
847CONFIG_SERIAL_8250_SHARE_IRQ=y
848CONFIG_SERIAL_8250_DETECT_IRQ=y
849CONFIG_SERIAL_8250_RSA=y
850
851#
852# Non-8250 serial port support
853#
854# CONFIG_SERIAL_MAX3100 is not set
855CONFIG_SERIAL_CORE=y
856CONFIG_SERIAL_CORE_CONSOLE=y
857# CONFIG_SERIAL_TIMBERDALE is not set
858CONFIG_UNIX98_PTYS=y
859# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
860# CONFIG_LEGACY_PTYS is not set
861# CONFIG_IPMI_HANDLER is not set
862CONFIG_HW_RANDOM=y
863# CONFIG_HW_RANDOM_TIMERIOMEM is not set
864# CONFIG_R3964 is not set
865# CONFIG_RAW_DRIVER is not set
866# CONFIG_TCG_TPM is not set
867CONFIG_I2C=y
868CONFIG_I2C_BOARDINFO=y
869CONFIG_I2C_COMPAT=y
870CONFIG_I2C_CHARDEV=y
871CONFIG_I2C_HELPER_AUTO=y
872
873#
874# I2C Hardware Bus support
875#
876
877#
878# I2C system bus drivers (mostly embedded / system-on-chip)
879#
880# CONFIG_I2C_DESIGNWARE is not set
881# CONFIG_I2C_GPIO is not set
882# CONFIG_I2C_OCORES is not set
883CONFIG_I2C_OMAP=y
884# CONFIG_I2C_SIMTEC is not set
885# CONFIG_I2C_XILINX is not set
886
887#
888# External I2C/SMBus adapter drivers
889#
890# CONFIG_I2C_PARPORT_LIGHT is not set
891# CONFIG_I2C_TAOS_EVM is not set
892# CONFIG_I2C_TINY_USB is not set
893
894#
895# Other I2C/SMBus bus drivers
896#
897# CONFIG_I2C_PCA_PLATFORM is not set
898# CONFIG_I2C_STUB is not set
899# CONFIG_I2C_DEBUG_CORE is not set
900# CONFIG_I2C_DEBUG_ALGO is not set
901# CONFIG_I2C_DEBUG_BUS is not set
902CONFIG_SPI=y
903# CONFIG_SPI_DEBUG is not set
904CONFIG_SPI_MASTER=y
905
906#
907# SPI Master Controller Drivers
908#
909# CONFIG_SPI_BITBANG is not set
910# CONFIG_SPI_GPIO is not set
911CONFIG_SPI_OMAP24XX=y
912# CONFIG_SPI_XILINX is not set
913# CONFIG_SPI_DESIGNWARE is not set
914
915#
916# SPI Protocol Masters
917#
918# CONFIG_SPI_SPIDEV is not set
919# CONFIG_SPI_TLE62X0 is not set
920
921#
922# PPS support
923#
924# CONFIG_PPS is not set
925CONFIG_ARCH_REQUIRE_GPIOLIB=y
926CONFIG_GPIOLIB=y
927# CONFIG_DEBUG_GPIO is not set
928# CONFIG_GPIO_SYSFS is not set
929
930#
931# Memory mapped GPIO expanders:
932#
933# CONFIG_GPIO_IT8761E is not set
934
935#
936# I2C GPIO expanders:
937#
938# CONFIG_GPIO_MAX7300 is not set
939# CONFIG_GPIO_MAX732X is not set
940# CONFIG_GPIO_PCA953X is not set
941# CONFIG_GPIO_PCF857X is not set
942CONFIG_GPIO_TWL4030=y
943# CONFIG_GPIO_ADP5588 is not set
944
945#
946# PCI GPIO expanders:
947#
948
949#
950# SPI GPIO expanders:
951#
952# CONFIG_GPIO_MAX7301 is not set
953# CONFIG_GPIO_MCP23S08 is not set
954# CONFIG_GPIO_MC33880 is not set
955
956#
957# AC97 GPIO expanders:
958#
959# CONFIG_W1 is not set
960# CONFIG_POWER_SUPPLY is not set
961# CONFIG_HWMON is not set
962# CONFIG_THERMAL is not set
963CONFIG_WATCHDOG=y
964CONFIG_WATCHDOG_NOWAYOUT=y
965
966#
967# Watchdog Device Drivers
968#
969# CONFIG_SOFT_WATCHDOG is not set
970CONFIG_OMAP_WATCHDOG=y
971# CONFIG_TWL4030_WATCHDOG is not set
972# CONFIG_MAX63XX_WATCHDOG is not set
973
974#
975# USB-based Watchdog Cards
976#
977# CONFIG_USBPCWATCHDOG is not set
978CONFIG_SSB_POSSIBLE=y
979
980#
981# Sonics Silicon Backplane
982#
983# CONFIG_SSB is not set
984
985#
986# Multifunction device drivers
987#
988# CONFIG_MFD_CORE is not set
989# CONFIG_MFD_88PM860X is not set
990# CONFIG_MFD_SM501 is not set
991# CONFIG_MFD_ASIC3 is not set
992# CONFIG_HTC_EGPIO is not set
993# CONFIG_HTC_PASIC3 is not set
994# CONFIG_HTC_I2CPLD is not set
995# CONFIG_TPS65010 is not set
996CONFIG_TWL4030_CORE=y
997# CONFIG_TWL4030_POWER is not set
998# CONFIG_TWL4030_CODEC is not set
999# CONFIG_MFD_TMIO is not set
1000# CONFIG_MFD_T7L66XB is not set
1001# CONFIG_MFD_TC6387XB is not set
1002# CONFIG_MFD_TC6393XB is not set
1003# CONFIG_PMIC_DA903X is not set
1004# CONFIG_PMIC_ADP5520 is not set
1005# CONFIG_MFD_MAX8925 is not set
1006# CONFIG_MFD_WM8400 is not set
1007# CONFIG_MFD_WM831X is not set
1008# CONFIG_MFD_WM8350_I2C is not set
1009# CONFIG_MFD_WM8994 is not set
1010# CONFIG_MFD_PCF50633 is not set
1011# CONFIG_MFD_MC13783 is not set
1012# CONFIG_AB3100_CORE is not set
1013# CONFIG_EZX_PCAP is not set
1014# CONFIG_AB4500_CORE is not set
1015CONFIG_REGULATOR=y
1016# CONFIG_REGULATOR_DEBUG is not set
1017# CONFIG_REGULATOR_DUMMY is not set
1018# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
1019# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
1020# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
1021# CONFIG_REGULATOR_BQ24022 is not set
1022# CONFIG_REGULATOR_MAX1586 is not set
1023# CONFIG_REGULATOR_MAX8649 is not set
1024# CONFIG_REGULATOR_MAX8660 is not set
1025CONFIG_REGULATOR_TWL4030=y
1026# CONFIG_REGULATOR_LP3971 is not set
1027# CONFIG_REGULATOR_TPS65023 is not set
1028# CONFIG_REGULATOR_TPS6507X is not set
1029# CONFIG_MEDIA_SUPPORT is not set
1030
1031#
1032# Graphics support
1033#
1034# CONFIG_VGASTATE is not set
1035CONFIG_VIDEO_OUTPUT_CONTROL=m
1036# CONFIG_FB is not set
1037# CONFIG_OMAP2_DSS is not set
1038# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1039
1040#
1041# Display device support
1042#
1043# CONFIG_DISPLAY_SUPPORT is not set
1044
1045#
1046# Console display driver support
1047#
1048# CONFIG_VGA_CONSOLE is not set
1049CONFIG_DUMMY_CONSOLE=y
1050# CONFIG_SOUND is not set
1051CONFIG_HID_SUPPORT=y
1052CONFIG_HID=y
1053# CONFIG_HIDRAW is not set
1054
1055#
1056# USB Input Devices
1057#
1058CONFIG_USB_HID=y
1059# CONFIG_HID_PID is not set
1060# CONFIG_USB_HIDDEV is not set
1061
1062#
1063# Special HID drivers
1064#
1065# CONFIG_HID_3M_PCT is not set
1066# CONFIG_HID_A4TECH is not set
1067# CONFIG_HID_APPLE is not set
1068# CONFIG_HID_BELKIN is not set
1069# CONFIG_HID_CHERRY is not set
1070# CONFIG_HID_CHICONY is not set
1071# CONFIG_HID_CYPRESS is not set
1072# CONFIG_HID_DRAGONRISE is not set
1073# CONFIG_HID_EZKEY is not set
1074# CONFIG_HID_KYE is not set
1075# CONFIG_HID_GYRATION is not set
1076# CONFIG_HID_TWINHAN is not set
1077# CONFIG_HID_KENSINGTON is not set
1078# CONFIG_HID_LOGITECH is not set
1079# CONFIG_HID_MICROSOFT is not set
1080# CONFIG_HID_MOSART is not set
1081# CONFIG_HID_MONTEREY is not set
1082# CONFIG_HID_NTRIG is not set
1083# CONFIG_HID_ORTEK is not set
1084# CONFIG_HID_PANTHERLORD is not set
1085# CONFIG_HID_PETALYNX is not set
1086# CONFIG_HID_QUANTA is not set
1087# CONFIG_HID_SAMSUNG is not set
1088# CONFIG_HID_SONY is not set
1089# CONFIG_HID_STANTUM is not set
1090# CONFIG_HID_SUNPLUS is not set
1091# CONFIG_HID_GREENASIA is not set
1092# CONFIG_HID_SMARTJOYPLUS is not set
1093# CONFIG_HID_TOPSEED is not set
1094# CONFIG_HID_THRUSTMASTER is not set
1095# CONFIG_HID_ZEROPLUS is not set
1096CONFIG_USB_SUPPORT=y
1097CONFIG_USB_ARCH_HAS_HCD=y
1098CONFIG_USB_ARCH_HAS_OHCI=y
1099CONFIG_USB_ARCH_HAS_EHCI=y
1100CONFIG_USB=y
1101# CONFIG_USB_DEBUG is not set
1102CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1103
1104#
1105# Miscellaneous USB options
1106#
1107CONFIG_USB_DEVICEFS=y
1108# CONFIG_USB_DEVICE_CLASS is not set
1109# CONFIG_USB_DYNAMIC_MINORS is not set
1110CONFIG_USB_OTG=y
1111# CONFIG_USB_OTG_WHITELIST is not set
1112# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1113CONFIG_USB_MON=y
1114# CONFIG_USB_WUSB is not set
1115# CONFIG_USB_WUSB_CBAF is not set
1116
1117#
1118# USB Host Controller Drivers
1119#
1120# CONFIG_USB_C67X00_HCD is not set
1121# CONFIG_USB_EHCI_HCD is not set
1122# CONFIG_USB_OXU210HP_HCD is not set
1123# CONFIG_USB_ISP116X_HCD is not set
1124# CONFIG_USB_ISP1760_HCD is not set
1125# CONFIG_USB_ISP1362_HCD is not set
1126# CONFIG_USB_OHCI_HCD is not set
1127# CONFIG_USB_SL811_HCD is not set
1128# CONFIG_USB_R8A66597_HCD is not set
1129# CONFIG_USB_HWA_HCD is not set
1130CONFIG_USB_MUSB_HDRC=y
1131CONFIG_USB_MUSB_SOC=y
1132
1133#
1134# OMAP 343x high speed USB support
1135#
1136# CONFIG_USB_MUSB_HOST is not set
1137# CONFIG_USB_MUSB_PERIPHERAL is not set
1138CONFIG_USB_MUSB_OTG=y
1139CONFIG_USB_GADGET_MUSB_HDRC=y
1140CONFIG_USB_MUSB_HDRC_HCD=y
1141# CONFIG_MUSB_PIO_ONLY is not set
1142CONFIG_USB_INVENTRA_DMA=y
1143# CONFIG_USB_TI_CPPI_DMA is not set
1144# CONFIG_USB_MUSB_DEBUG is not set
1145
1146#
1147# USB Device Class drivers
1148#
1149# CONFIG_USB_ACM is not set
1150# CONFIG_USB_PRINTER is not set
1151# CONFIG_USB_WDM is not set
1152# CONFIG_USB_TMC is not set
1153
1154#
1155# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
1156#
1157
1158#
1159# also be needed; see USB_STORAGE Help for more info
1160#
1161CONFIG_USB_STORAGE=y
1162# CONFIG_USB_STORAGE_DEBUG is not set
1163# CONFIG_USB_STORAGE_DATAFAB is not set
1164# CONFIG_USB_STORAGE_FREECOM is not set
1165# CONFIG_USB_STORAGE_ISD200 is not set
1166# CONFIG_USB_STORAGE_USBAT is not set
1167# CONFIG_USB_STORAGE_SDDR09 is not set
1168# CONFIG_USB_STORAGE_SDDR55 is not set
1169# CONFIG_USB_STORAGE_JUMPSHOT is not set
1170# CONFIG_USB_STORAGE_ALAUDA is not set
1171# CONFIG_USB_STORAGE_ONETOUCH is not set
1172# CONFIG_USB_STORAGE_KARMA is not set
1173# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1174# CONFIG_USB_LIBUSUAL is not set
1175
1176#
1177# USB Imaging devices
1178#
1179# CONFIG_USB_MDC800 is not set
1180# CONFIG_USB_MICROTEK is not set
1181
1182#
1183# USB port drivers
1184#
1185# CONFIG_USB_SERIAL is not set
1186
1187#
1188# USB Miscellaneous drivers
1189#
1190# CONFIG_USB_EMI62 is not set
1191# CONFIG_USB_EMI26 is not set
1192# CONFIG_USB_ADUTUX is not set
1193# CONFIG_USB_SEVSEG is not set
1194# CONFIG_USB_RIO500 is not set
1195# CONFIG_USB_LEGOTOWER is not set
1196# CONFIG_USB_LCD is not set
1197# CONFIG_USB_LED is not set
1198# CONFIG_USB_CYPRESS_CY7C63 is not set
1199# CONFIG_USB_CYTHERM is not set
1200# CONFIG_USB_IDMOUSE is not set
1201# CONFIG_USB_FTDI_ELAN is not set
1202# CONFIG_USB_APPLEDISPLAY is not set
1203# CONFIG_USB_SISUSBVGA is not set
1204# CONFIG_USB_LD is not set
1205# CONFIG_USB_TRANCEVIBRATOR is not set
1206# CONFIG_USB_IOWARRIOR is not set
1207CONFIG_USB_TEST=y
1208# CONFIG_USB_ISIGHTFW is not set
1209CONFIG_USB_GADGET=y
1210# CONFIG_USB_GADGET_DEBUG is not set
1211# CONFIG_USB_GADGET_DEBUG_FILES is not set
1212# CONFIG_USB_GADGET_DEBUG_FS is not set
1213CONFIG_USB_GADGET_VBUS_DRAW=2
1214CONFIG_USB_GADGET_SELECTED=y
1215# CONFIG_USB_GADGET_AT91 is not set
1216# CONFIG_USB_GADGET_ATMEL_USBA is not set
1217# CONFIG_USB_GADGET_FSL_USB2 is not set
1218# CONFIG_USB_GADGET_LH7A40X is not set
1219# CONFIG_USB_GADGET_OMAP is not set
1220# CONFIG_USB_GADGET_PXA25X is not set
1221# CONFIG_USB_GADGET_R8A66597 is not set
1222# CONFIG_USB_GADGET_PXA27X is not set
1223# CONFIG_USB_GADGET_S3C_HSOTG is not set
1224# CONFIG_USB_GADGET_IMX is not set
1225# CONFIG_USB_GADGET_S3C2410 is not set
1226# CONFIG_USB_GADGET_M66592 is not set
1227# CONFIG_USB_GADGET_AMD5536UDC is not set
1228# CONFIG_USB_GADGET_FSL_QE is not set
1229# CONFIG_USB_GADGET_CI13XXX is not set
1230# CONFIG_USB_GADGET_NET2280 is not set
1231# CONFIG_USB_GADGET_GOKU is not set
1232# CONFIG_USB_GADGET_LANGWELL is not set
1233# CONFIG_USB_GADGET_DUMMY_HCD is not set
1234CONFIG_USB_GADGET_DUALSPEED=y
1235CONFIG_USB_ZERO=m
1236# CONFIG_USB_ZERO_HNPTEST is not set
1237# CONFIG_USB_AUDIO is not set
1238# CONFIG_USB_ETH is not set
1239# CONFIG_USB_GADGETFS is not set
1240# CONFIG_USB_FILE_STORAGE is not set
1241# CONFIG_USB_MASS_STORAGE is not set
1242# CONFIG_USB_G_SERIAL is not set
1243# CONFIG_USB_MIDI_GADGET is not set
1244# CONFIG_USB_G_PRINTER is not set
1245# CONFIG_USB_CDC_COMPOSITE is not set
1246# CONFIG_USB_G_NOKIA is not set
1247# CONFIG_USB_G_MULTI is not set
1248
1249#
1250# OTG and related infrastructure
1251#
1252CONFIG_USB_OTG_UTILS=y
1253# CONFIG_USB_GPIO_VBUS is not set
1254# CONFIG_ISP1301_OMAP is not set
1255# CONFIG_USB_ULPI is not set
1256CONFIG_TWL4030_USB=y
1257# CONFIG_NOP_USB_XCEIV is not set
1258CONFIG_MMC=y
1259# CONFIG_MMC_DEBUG is not set
1260# CONFIG_MMC_UNSAFE_RESUME is not set
1261
1262#
1263# MMC/SD/SDIO Card Drivers
1264#
1265CONFIG_MMC_BLOCK=y
1266CONFIG_MMC_BLOCK_BOUNCE=y
1267# CONFIG_SDIO_UART is not set
1268# CONFIG_MMC_TEST is not set
1269
1270#
1271# MMC/SD/SDIO Host Controller Drivers
1272#
1273# CONFIG_MMC_SDHCI is not set
1274# CONFIG_MMC_OMAP is not set
1275CONFIG_MMC_OMAP_HS=y
1276# CONFIG_MMC_SPI is not set
1277# CONFIG_MEMSTICK is not set
1278# CONFIG_NEW_LEDS is not set
1279# CONFIG_ACCESSIBILITY is not set
1280CONFIG_RTC_LIB=y
1281# CONFIG_RTC_CLASS is not set
1282# CONFIG_DMADEVICES is not set
1283# CONFIG_AUXDISPLAY is not set
1284# CONFIG_UIO is not set
1285
1286#
1287# TI VLYNQ
1288#
1289# CONFIG_STAGING is not set
1290
1291#
1292# File systems
1293#
1294CONFIG_EXT2_FS=y
1295# CONFIG_EXT2_FS_XATTR is not set
1296# CONFIG_EXT2_FS_XIP is not set
1297CONFIG_EXT3_FS=y
1298# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1299# CONFIG_EXT3_FS_XATTR is not set
1300# CONFIG_EXT4_FS is not set
1301CONFIG_JBD=y
1302# CONFIG_JBD_DEBUG is not set
1303# CONFIG_REISERFS_FS is not set
1304# CONFIG_JFS_FS is not set
1305# CONFIG_FS_POSIX_ACL is not set
1306# CONFIG_XFS_FS is not set
1307# CONFIG_GFS2_FS is not set
1308# CONFIG_OCFS2_FS is not set
1309# CONFIG_BTRFS_FS is not set
1310# CONFIG_NILFS2_FS is not set
1311CONFIG_FILE_LOCKING=y
1312CONFIG_FSNOTIFY=y
1313CONFIG_DNOTIFY=y
1314CONFIG_INOTIFY=y
1315CONFIG_INOTIFY_USER=y
1316CONFIG_QUOTA=y
1317# CONFIG_QUOTA_NETLINK_INTERFACE is not set
1318CONFIG_PRINT_QUOTA_WARNING=y
1319# CONFIG_QUOTA_DEBUG is not set
1320CONFIG_QUOTA_TREE=y
1321# CONFIG_QFMT_V1 is not set
1322CONFIG_QFMT_V2=y
1323CONFIG_QUOTACTL=y
1324# CONFIG_AUTOFS_FS is not set
1325# CONFIG_AUTOFS4_FS is not set
1326# CONFIG_FUSE_FS is not set
1327
1328#
1329# Caches
1330#
1331# CONFIG_FSCACHE is not set
1332
1333#
1334# CD-ROM/DVD Filesystems
1335#
1336# CONFIG_ISO9660_FS is not set
1337# CONFIG_UDF_FS is not set
1338
1339#
1340# DOS/FAT/NT Filesystems
1341#
1342CONFIG_FAT_FS=y
1343CONFIG_MSDOS_FS=y
1344CONFIG_VFAT_FS=y
1345CONFIG_FAT_DEFAULT_CODEPAGE=437
1346CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1347# CONFIG_NTFS_FS is not set
1348
1349#
1350# Pseudo filesystems
1351#
1352CONFIG_PROC_FS=y
1353CONFIG_PROC_SYSCTL=y
1354CONFIG_PROC_PAGE_MONITOR=y
1355CONFIG_SYSFS=y
1356CONFIG_TMPFS=y
1357# CONFIG_TMPFS_POSIX_ACL is not set
1358# CONFIG_HUGETLB_PAGE is not set
1359# CONFIG_CONFIGFS_FS is not set
1360CONFIG_MISC_FILESYSTEMS=y
1361# CONFIG_ADFS_FS is not set
1362# CONFIG_AFFS_FS is not set
1363# CONFIG_HFS_FS is not set
1364# CONFIG_HFSPLUS_FS is not set
1365# CONFIG_BEFS_FS is not set
1366# CONFIG_BFS_FS is not set
1367# CONFIG_EFS_FS is not set
1368CONFIG_JFFS2_FS=y
1369CONFIG_JFFS2_FS_DEBUG=0
1370CONFIG_JFFS2_FS_WRITEBUFFER=y
1371# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1372# CONFIG_JFFS2_SUMMARY is not set
1373# CONFIG_JFFS2_FS_XATTR is not set
1374CONFIG_JFFS2_COMPRESSION_OPTIONS=y
1375CONFIG_JFFS2_ZLIB=y
1376# CONFIG_JFFS2_LZO is not set
1377CONFIG_JFFS2_RTIME=y
1378# CONFIG_JFFS2_RUBIN is not set
1379# CONFIG_JFFS2_CMODE_NONE is not set
1380CONFIG_JFFS2_CMODE_PRIORITY=y
1381# CONFIG_JFFS2_CMODE_SIZE is not set
1382# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
1383# CONFIG_LOGFS is not set
1384# CONFIG_CRAMFS is not set
1385# CONFIG_SQUASHFS is not set
1386# CONFIG_VXFS_FS is not set
1387# CONFIG_MINIX_FS is not set
1388# CONFIG_OMFS_FS is not set
1389# CONFIG_HPFS_FS is not set
1390# CONFIG_QNX4FS_FS is not set
1391# CONFIG_ROMFS_FS is not set
1392# CONFIG_SYSV_FS is not set
1393# CONFIG_UFS_FS is not set
1394CONFIG_NETWORK_FILESYSTEMS=y
1395CONFIG_NFS_FS=y
1396CONFIG_NFS_V3=y
1397# CONFIG_NFS_V3_ACL is not set
1398CONFIG_NFS_V4=y
1399# CONFIG_NFS_V4_1 is not set
1400CONFIG_ROOT_NFS=y
1401# CONFIG_NFSD is not set
1402CONFIG_LOCKD=y
1403CONFIG_LOCKD_V4=y
1404CONFIG_NFS_COMMON=y
1405CONFIG_SUNRPC=y
1406CONFIG_SUNRPC_GSS=y
1407CONFIG_RPCSEC_GSS_KRB5=y
1408# CONFIG_RPCSEC_GSS_SPKM3 is not set
1409# CONFIG_SMB_FS is not set
1410# CONFIG_CEPH_FS is not set
1411# CONFIG_CIFS is not set
1412# CONFIG_NCP_FS is not set
1413# CONFIG_CODA_FS is not set
1414# CONFIG_AFS_FS is not set
1415
1416#
1417# Partition Types
1418#
1419CONFIG_PARTITION_ADVANCED=y
1420# CONFIG_ACORN_PARTITION is not set
1421# CONFIG_OSF_PARTITION is not set
1422# CONFIG_AMIGA_PARTITION is not set
1423# CONFIG_ATARI_PARTITION is not set
1424# CONFIG_MAC_PARTITION is not set
1425CONFIG_MSDOS_PARTITION=y
1426# CONFIG_BSD_DISKLABEL is not set
1427# CONFIG_MINIX_SUBPARTITION is not set
1428# CONFIG_SOLARIS_X86_PARTITION is not set
1429# CONFIG_UNIXWARE_DISKLABEL is not set
1430# CONFIG_LDM_PARTITION is not set
1431# CONFIG_SGI_PARTITION is not set
1432# CONFIG_ULTRIX_PARTITION is not set
1433# CONFIG_SUN_PARTITION is not set
1434# CONFIG_KARMA_PARTITION is not set
1435# CONFIG_EFI_PARTITION is not set
1436# CONFIG_SYSV68_PARTITION is not set
1437CONFIG_NLS=y
1438CONFIG_NLS_DEFAULT="iso8859-1"
1439CONFIG_NLS_CODEPAGE_437=y
1440# CONFIG_NLS_CODEPAGE_737 is not set
1441# CONFIG_NLS_CODEPAGE_775 is not set
1442# CONFIG_NLS_CODEPAGE_850 is not set
1443# CONFIG_NLS_CODEPAGE_852 is not set
1444# CONFIG_NLS_CODEPAGE_855 is not set
1445# CONFIG_NLS_CODEPAGE_857 is not set
1446# CONFIG_NLS_CODEPAGE_860 is not set
1447# CONFIG_NLS_CODEPAGE_861 is not set
1448# CONFIG_NLS_CODEPAGE_862 is not set
1449# CONFIG_NLS_CODEPAGE_863 is not set
1450# CONFIG_NLS_CODEPAGE_864 is not set
1451# CONFIG_NLS_CODEPAGE_865 is not set
1452# CONFIG_NLS_CODEPAGE_866 is not set
1453# CONFIG_NLS_CODEPAGE_869 is not set
1454# CONFIG_NLS_CODEPAGE_936 is not set
1455# CONFIG_NLS_CODEPAGE_950 is not set
1456# CONFIG_NLS_CODEPAGE_932 is not set
1457# CONFIG_NLS_CODEPAGE_949 is not set
1458# CONFIG_NLS_CODEPAGE_874 is not set
1459# CONFIG_NLS_ISO8859_8 is not set
1460# CONFIG_NLS_CODEPAGE_1250 is not set
1461# CONFIG_NLS_CODEPAGE_1251 is not set
1462# CONFIG_NLS_ASCII is not set
1463CONFIG_NLS_ISO8859_1=y
1464# CONFIG_NLS_ISO8859_2 is not set
1465# CONFIG_NLS_ISO8859_3 is not set
1466# CONFIG_NLS_ISO8859_4 is not set
1467# CONFIG_NLS_ISO8859_5 is not set
1468# CONFIG_NLS_ISO8859_6 is not set
1469# CONFIG_NLS_ISO8859_7 is not set
1470# CONFIG_NLS_ISO8859_9 is not set
1471# CONFIG_NLS_ISO8859_13 is not set
1472# CONFIG_NLS_ISO8859_14 is not set
1473# CONFIG_NLS_ISO8859_15 is not set
1474# CONFIG_NLS_KOI8_R is not set
1475# CONFIG_NLS_KOI8_U is not set
1476# CONFIG_NLS_UTF8 is not set
1477# CONFIG_DLM is not set
1478
1479#
1480# Kernel hacking
1481#
1482# CONFIG_PRINTK_TIME is not set
1483CONFIG_ENABLE_WARN_DEPRECATED=y
1484CONFIG_ENABLE_MUST_CHECK=y
1485CONFIG_FRAME_WARN=1024
1486CONFIG_MAGIC_SYSRQ=y
1487# CONFIG_STRIP_ASM_SYMS is not set
1488# CONFIG_UNUSED_SYMBOLS is not set
1489CONFIG_DEBUG_FS=y
1490# CONFIG_HEADERS_CHECK is not set
1491CONFIG_DEBUG_KERNEL=y
1492# CONFIG_DEBUG_SHIRQ is not set
1493CONFIG_DETECT_SOFTLOCKUP=y
1494# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1495CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1496CONFIG_DETECT_HUNG_TASK=y
1497# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
1498CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1499# CONFIG_SCHED_DEBUG is not set
1500# CONFIG_SCHEDSTATS is not set
1501# CONFIG_TIMER_STATS is not set
1502# CONFIG_DEBUG_OBJECTS is not set
1503# CONFIG_DEBUG_SLAB is not set
1504# CONFIG_DEBUG_KMEMLEAK is not set
1505# CONFIG_DEBUG_RT_MUTEXES is not set
1506# CONFIG_RT_MUTEX_TESTER is not set
1507# CONFIG_DEBUG_SPINLOCK is not set
1508CONFIG_DEBUG_MUTEXES=y
1509# CONFIG_DEBUG_LOCK_ALLOC is not set
1510# CONFIG_PROVE_LOCKING is not set
1511# CONFIG_LOCK_STAT is not set
1512# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1513# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1514# CONFIG_DEBUG_KOBJECT is not set
1515# CONFIG_DEBUG_BUGVERBOSE is not set
1516CONFIG_DEBUG_INFO=y
1517# CONFIG_DEBUG_VM is not set
1518# CONFIG_DEBUG_WRITECOUNT is not set
1519# CONFIG_DEBUG_MEMORY_INIT is not set
1520# CONFIG_DEBUG_LIST is not set
1521# CONFIG_DEBUG_SG is not set
1522# CONFIG_DEBUG_NOTIFIERS is not set
1523# CONFIG_DEBUG_CREDENTIALS is not set
1524# CONFIG_BOOT_PRINTK_DELAY is not set
1525# CONFIG_RCU_TORTURE_TEST is not set
1526# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1527# CONFIG_BACKTRACE_SELF_TEST is not set
1528# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1529# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
1530# CONFIG_LKDTM is not set
1531# CONFIG_FAULT_INJECTION is not set
1532# CONFIG_LATENCYTOP is not set
1533# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1534# CONFIG_PAGE_POISONING is not set
1535CONFIG_HAVE_FUNCTION_TRACER=y
1536CONFIG_TRACING_SUPPORT=y
1537CONFIG_FTRACE=y
1538# CONFIG_FUNCTION_TRACER is not set
1539# CONFIG_IRQSOFF_TRACER is not set
1540# CONFIG_SCHED_TRACER is not set
1541# CONFIG_ENABLE_DEFAULT_TRACERS is not set
1542# CONFIG_BOOT_TRACER is not set
1543CONFIG_BRANCH_PROFILE_NONE=y
1544# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
1545# CONFIG_PROFILE_ALL_BRANCHES is not set
1546# CONFIG_STACK_TRACER is not set
1547# CONFIG_KMEMTRACE is not set
1548# CONFIG_WORKQUEUE_TRACER is not set
1549# CONFIG_BLK_DEV_IO_TRACE is not set
1550# CONFIG_DYNAMIC_DEBUG is not set
1551# CONFIG_SAMPLES is not set
1552CONFIG_HAVE_ARCH_KGDB=y
1553# CONFIG_KGDB is not set
1554CONFIG_ARM_UNWIND=y
1555# CONFIG_DEBUG_USER is not set
1556# CONFIG_DEBUG_ERRORS is not set
1557# CONFIG_DEBUG_STACK_USAGE is not set
1558CONFIG_DEBUG_LL=y
1559# CONFIG_EARLY_PRINTK is not set
1560# CONFIG_DEBUG_ICEDCC is not set
1561# CONFIG_OC_ETM is not set
1562
1563#
1564# Security options
1565#
1566# CONFIG_KEYS is not set
1567# CONFIG_SECURITY is not set
1568# CONFIG_SECURITYFS is not set
1569# CONFIG_DEFAULT_SECURITY_SELINUX is not set
1570# CONFIG_DEFAULT_SECURITY_SMACK is not set
1571# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
1572CONFIG_DEFAULT_SECURITY_DAC=y
1573CONFIG_DEFAULT_SECURITY=""
1574CONFIG_CRYPTO=y
1575
1576#
1577# Crypto core or helper
1578#
1579CONFIG_CRYPTO_ALGAPI=y
1580CONFIG_CRYPTO_ALGAPI2=y
1581CONFIG_CRYPTO_AEAD2=y
1582CONFIG_CRYPTO_BLKCIPHER=y
1583CONFIG_CRYPTO_BLKCIPHER2=y
1584CONFIG_CRYPTO_HASH=y
1585CONFIG_CRYPTO_HASH2=y
1586CONFIG_CRYPTO_RNG2=y
1587CONFIG_CRYPTO_PCOMP=y
1588CONFIG_CRYPTO_MANAGER=y
1589CONFIG_CRYPTO_MANAGER2=y
1590# CONFIG_CRYPTO_GF128MUL is not set
1591# CONFIG_CRYPTO_NULL is not set
1592CONFIG_CRYPTO_WORKQUEUE=y
1593# CONFIG_CRYPTO_CRYPTD is not set
1594# CONFIG_CRYPTO_AUTHENC is not set
1595# CONFIG_CRYPTO_TEST is not set
1596
1597#
1598# Authenticated Encryption with Associated Data
1599#
1600# CONFIG_CRYPTO_CCM is not set
1601# CONFIG_CRYPTO_GCM is not set
1602# CONFIG_CRYPTO_SEQIV is not set
1603
1604#
1605# Block modes
1606#
1607CONFIG_CRYPTO_CBC=y
1608# CONFIG_CRYPTO_CTR is not set
1609# CONFIG_CRYPTO_CTS is not set
1610CONFIG_CRYPTO_ECB=m
1611# CONFIG_CRYPTO_LRW is not set
1612CONFIG_CRYPTO_PCBC=m
1613# CONFIG_CRYPTO_XTS is not set
1614
1615#
1616# Hash modes
1617#
1618# CONFIG_CRYPTO_HMAC is not set
1619# CONFIG_CRYPTO_XCBC is not set
1620# CONFIG_CRYPTO_VMAC is not set
1621
1622#
1623# Digest
1624#
1625CONFIG_CRYPTO_CRC32C=y
1626# CONFIG_CRYPTO_GHASH is not set
1627# CONFIG_CRYPTO_MD4 is not set
1628CONFIG_CRYPTO_MD5=y
1629# CONFIG_CRYPTO_MICHAEL_MIC is not set
1630# CONFIG_CRYPTO_RMD128 is not set
1631# CONFIG_CRYPTO_RMD160 is not set
1632# CONFIG_CRYPTO_RMD256 is not set
1633# CONFIG_CRYPTO_RMD320 is not set
1634# CONFIG_CRYPTO_SHA1 is not set
1635# CONFIG_CRYPTO_SHA256 is not set
1636# CONFIG_CRYPTO_SHA512 is not set
1637# CONFIG_CRYPTO_TGR192 is not set
1638# CONFIG_CRYPTO_WP512 is not set
1639
1640#
1641# Ciphers
1642#
1643# CONFIG_CRYPTO_AES is not set
1644# CONFIG_CRYPTO_ANUBIS is not set
1645# CONFIG_CRYPTO_ARC4 is not set
1646# CONFIG_CRYPTO_BLOWFISH is not set
1647# CONFIG_CRYPTO_CAMELLIA is not set
1648# CONFIG_CRYPTO_CAST5 is not set
1649# CONFIG_CRYPTO_CAST6 is not set
1650CONFIG_CRYPTO_DES=y
1651# CONFIG_CRYPTO_FCRYPT is not set
1652# CONFIG_CRYPTO_KHAZAD is not set
1653# CONFIG_CRYPTO_SALSA20 is not set
1654# CONFIG_CRYPTO_SEED is not set
1655# CONFIG_CRYPTO_SERPENT is not set
1656# CONFIG_CRYPTO_TEA is not set
1657# CONFIG_CRYPTO_TWOFISH is not set
1658
1659#
1660# Compression
1661#
1662# CONFIG_CRYPTO_DEFLATE is not set
1663# CONFIG_CRYPTO_ZLIB is not set
1664# CONFIG_CRYPTO_LZO is not set
1665
1666#
1667# Random Number Generation
1668#
1669# CONFIG_CRYPTO_ANSI_CPRNG is not set
1670CONFIG_CRYPTO_HW=y
1671# CONFIG_BINARY_PRINTF is not set
1672
1673#
1674# Library routines
1675#
1676CONFIG_BITREVERSE=y
1677CONFIG_GENERIC_FIND_LAST_BIT=y
1678CONFIG_CRC_CCITT=y
1679# CONFIG_CRC16 is not set
1680# CONFIG_CRC_T10DIF is not set
1681# CONFIG_CRC_ITU_T is not set
1682CONFIG_CRC32=y
1683# CONFIG_CRC7 is not set
1684CONFIG_LIBCRC32C=y
1685CONFIG_ZLIB_INFLATE=y
1686CONFIG_ZLIB_DEFLATE=y
1687CONFIG_DECOMPRESS_GZIP=y
1688CONFIG_HAS_IOMEM=y
1689CONFIG_HAS_IOPORT=y
1690CONFIG_HAS_DMA=y
1691CONFIG_NLATTR=y
diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig
index a96bca290cd1..1fb04567f6e1 100644
--- a/arch/arm/configs/omap_4430sdp_defconfig
+++ b/arch/arm/configs/omap_4430sdp_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.32 3# Linux kernel version: 2.6.34-rc7
4# Sun Dec 6 23:37:45 2009 4# Wed May 12 12:26:05 2010
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y 7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -9,6 +9,7 @@ CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y 9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y 10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y 11CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
12CONFIG_HAVE_PROC_CPU=y
12CONFIG_GENERIC_HARDIRQS=y 13CONFIG_GENERIC_HARDIRQS=y
13CONFIG_STACKTRACE_SUPPORT=y 14CONFIG_STACKTRACE_SUPPORT=y
14CONFIG_LOCKDEP_SUPPORT=y 15CONFIG_LOCKDEP_SUPPORT=y
@@ -20,6 +21,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
20CONFIG_ARCH_HAS_CPUFREQ=y 21CONFIG_ARCH_HAS_CPUFREQ=y
21CONFIG_GENERIC_HWEIGHT=y 22CONFIG_GENERIC_HWEIGHT=y
22CONFIG_GENERIC_CALIBRATE_DELAY=y 23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_NEED_DMA_MAP_STATE=y
23CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y 25CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
24CONFIG_VECTORS_BASE=0xffff0000 26CONFIG_VECTORS_BASE=0xffff0000
25CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 27CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -33,28 +35,33 @@ CONFIG_LOCK_KERNEL=y
33CONFIG_INIT_ENV_ARG_LIMIT=32 35CONFIG_INIT_ENV_ARG_LIMIT=32
34CONFIG_LOCALVERSION="" 36CONFIG_LOCALVERSION=""
35CONFIG_LOCALVERSION_AUTO=y 37CONFIG_LOCALVERSION_AUTO=y
38CONFIG_HAVE_KERNEL_GZIP=y
39CONFIG_HAVE_KERNEL_LZO=y
40CONFIG_KERNEL_GZIP=y
41# CONFIG_KERNEL_BZIP2 is not set
42# CONFIG_KERNEL_LZMA is not set
43# CONFIG_KERNEL_LZO is not set
36CONFIG_SWAP=y 44CONFIG_SWAP=y
37CONFIG_SYSVIPC=y 45CONFIG_SYSVIPC=y
38CONFIG_SYSVIPC_SYSCTL=y 46CONFIG_SYSVIPC_SYSCTL=y
47# CONFIG_POSIX_MQUEUE is not set
39CONFIG_BSD_PROCESS_ACCT=y 48CONFIG_BSD_PROCESS_ACCT=y
40# CONFIG_BSD_PROCESS_ACCT_V3 is not set 49# CONFIG_BSD_PROCESS_ACCT_V3 is not set
50# CONFIG_TASKSTATS is not set
51# CONFIG_AUDIT is not set
41 52
42# 53#
43# RCU Subsystem 54# RCU Subsystem
44# 55#
45CONFIG_TREE_RCU=y 56CONFIG_TREE_RCU=y
46# CONFIG_TREE_PREEMPT_RCU is not set 57# CONFIG_TREE_PREEMPT_RCU is not set
58# CONFIG_TINY_RCU is not set
47# CONFIG_RCU_TRACE is not set 59# CONFIG_RCU_TRACE is not set
48CONFIG_RCU_FANOUT=32 60CONFIG_RCU_FANOUT=32
49# CONFIG_RCU_FANOUT_EXACT is not set 61# CONFIG_RCU_FANOUT_EXACT is not set
50# CONFIG_TREE_RCU_TRACE is not set 62# CONFIG_TREE_RCU_TRACE is not set
51# CONFIG_IKCONFIG is not set 63# CONFIG_IKCONFIG is not set
52CONFIG_LOG_BUF_SHIFT=14 64CONFIG_LOG_BUF_SHIFT=14
53CONFIG_GROUP_SCHED=y
54CONFIG_FAIR_GROUP_SCHED=y
55# CONFIG_RT_GROUP_SCHED is not set
56CONFIG_USER_SCHED=y
57# CONFIG_CGROUP_SCHED is not set
58# CONFIG_CGROUPS is not set 65# CONFIG_CGROUPS is not set
59# CONFIG_SYSFS_DEPRECATED_V2 is not set 66# CONFIG_SYSFS_DEPRECATED_V2 is not set
60# CONFIG_RELAY is not set 67# CONFIG_RELAY is not set
@@ -64,6 +71,7 @@ CONFIG_INITRAMFS_SOURCE=""
64CONFIG_RD_GZIP=y 71CONFIG_RD_GZIP=y
65# CONFIG_RD_BZIP2 is not set 72# CONFIG_RD_BZIP2 is not set
66# CONFIG_RD_LZMA is not set 73# CONFIG_RD_LZMA is not set
74# CONFIG_RD_LZO is not set
67CONFIG_CC_OPTIMIZE_FOR_SIZE=y 75CONFIG_CC_OPTIMIZE_FOR_SIZE=y
68CONFIG_SYSCTL=y 76CONFIG_SYSCTL=y
69CONFIG_ANON_INODES=y 77CONFIG_ANON_INODES=y
@@ -85,10 +93,14 @@ CONFIG_TIMERFD=y
85CONFIG_EVENTFD=y 93CONFIG_EVENTFD=y
86CONFIG_SHMEM=y 94CONFIG_SHMEM=y
87CONFIG_AIO=y 95CONFIG_AIO=y
96CONFIG_HAVE_PERF_EVENTS=y
97CONFIG_PERF_USE_VMALLOC=y
88 98
89# 99#
90# Kernel Performance Events And Counters 100# Kernel Performance Events And Counters
91# 101#
102# CONFIG_PERF_EVENTS is not set
103# CONFIG_PERF_COUNTERS is not set
92CONFIG_VM_EVENT_COUNTERS=y 104CONFIG_VM_EVENT_COUNTERS=y
93CONFIG_SLUB_DEBUG=y 105CONFIG_SLUB_DEBUG=y
94CONFIG_COMPAT_BRK=y 106CONFIG_COMPAT_BRK=y
@@ -127,14 +139,41 @@ CONFIG_LBDAF=y
127# IO Schedulers 139# IO Schedulers
128# 140#
129CONFIG_IOSCHED_NOOP=y 141CONFIG_IOSCHED_NOOP=y
130CONFIG_IOSCHED_AS=y
131CONFIG_IOSCHED_DEADLINE=y 142CONFIG_IOSCHED_DEADLINE=y
132CONFIG_IOSCHED_CFQ=y 143CONFIG_IOSCHED_CFQ=y
133CONFIG_DEFAULT_AS=y
134# CONFIG_DEFAULT_DEADLINE is not set 144# CONFIG_DEFAULT_DEADLINE is not set
135# CONFIG_DEFAULT_CFQ is not set 145CONFIG_DEFAULT_CFQ=y
136# CONFIG_DEFAULT_NOOP is not set 146# CONFIG_DEFAULT_NOOP is not set
137CONFIG_DEFAULT_IOSCHED="anticipatory" 147CONFIG_DEFAULT_IOSCHED="cfq"
148# CONFIG_INLINE_SPIN_TRYLOCK is not set
149# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
150# CONFIG_INLINE_SPIN_LOCK is not set
151# CONFIG_INLINE_SPIN_LOCK_BH is not set
152# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
153# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
154# CONFIG_INLINE_SPIN_UNLOCK is not set
155# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
156# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
157# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
158# CONFIG_INLINE_READ_TRYLOCK is not set
159# CONFIG_INLINE_READ_LOCK is not set
160# CONFIG_INLINE_READ_LOCK_BH is not set
161# CONFIG_INLINE_READ_LOCK_IRQ is not set
162# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
163# CONFIG_INLINE_READ_UNLOCK is not set
164# CONFIG_INLINE_READ_UNLOCK_BH is not set
165# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
166# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
167# CONFIG_INLINE_WRITE_TRYLOCK is not set
168# CONFIG_INLINE_WRITE_LOCK is not set
169# CONFIG_INLINE_WRITE_LOCK_BH is not set
170# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
171# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
172# CONFIG_INLINE_WRITE_UNLOCK is not set
173# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
174# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
175# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
176CONFIG_MUTEX_SPIN_ON_OWNER=y
138# CONFIG_FREEZER is not set 177# CONFIG_FREEZER is not set
139 178
140# 179#
@@ -146,6 +185,7 @@ CONFIG_MMU=y
146# CONFIG_ARCH_REALVIEW is not set 185# CONFIG_ARCH_REALVIEW is not set
147# CONFIG_ARCH_VERSATILE is not set 186# CONFIG_ARCH_VERSATILE is not set
148# CONFIG_ARCH_AT91 is not set 187# CONFIG_ARCH_AT91 is not set
188# CONFIG_ARCH_BCMRING is not set
149# CONFIG_ARCH_CLPS711X is not set 189# CONFIG_ARCH_CLPS711X is not set
150# CONFIG_ARCH_GEMINI is not set 190# CONFIG_ARCH_GEMINI is not set
151# CONFIG_ARCH_EBSA110 is not set 191# CONFIG_ARCH_EBSA110 is not set
@@ -155,7 +195,6 @@ CONFIG_MMU=y
155# CONFIG_ARCH_STMP3XXX is not set 195# CONFIG_ARCH_STMP3XXX is not set
156# CONFIG_ARCH_NETX is not set 196# CONFIG_ARCH_NETX is not set
157# CONFIG_ARCH_H720X is not set 197# CONFIG_ARCH_H720X is not set
158# CONFIG_ARCH_NOMADIK is not set
159# CONFIG_ARCH_IOP13XX is not set 198# CONFIG_ARCH_IOP13XX is not set
160# CONFIG_ARCH_IOP32X is not set 199# CONFIG_ARCH_IOP32X is not set
161# CONFIG_ARCH_IOP33X is not set 200# CONFIG_ARCH_IOP33X is not set
@@ -163,6 +202,7 @@ CONFIG_MMU=y
163# CONFIG_ARCH_IXP2000 is not set 202# CONFIG_ARCH_IXP2000 is not set
164# CONFIG_ARCH_IXP4XX is not set 203# CONFIG_ARCH_IXP4XX is not set
165# CONFIG_ARCH_L7200 is not set 204# CONFIG_ARCH_L7200 is not set
205# CONFIG_ARCH_DOVE is not set
166# CONFIG_ARCH_KIRKWOOD is not set 206# CONFIG_ARCH_KIRKWOOD is not set
167# CONFIG_ARCH_LOKI is not set 207# CONFIG_ARCH_LOKI is not set
168# CONFIG_ARCH_MV78XX0 is not set 208# CONFIG_ARCH_MV78XX0 is not set
@@ -171,25 +211,32 @@ CONFIG_MMU=y
171# CONFIG_ARCH_KS8695 is not set 211# CONFIG_ARCH_KS8695 is not set
172# CONFIG_ARCH_NS9XXX is not set 212# CONFIG_ARCH_NS9XXX is not set
173# CONFIG_ARCH_W90X900 is not set 213# CONFIG_ARCH_W90X900 is not set
214# CONFIG_ARCH_NUC93X is not set
174# CONFIG_ARCH_PNX4008 is not set 215# CONFIG_ARCH_PNX4008 is not set
175# CONFIG_ARCH_PXA is not set 216# CONFIG_ARCH_PXA is not set
176# CONFIG_ARCH_MSM is not set 217# CONFIG_ARCH_MSM is not set
218# CONFIG_ARCH_SHMOBILE is not set
177# CONFIG_ARCH_RPC is not set 219# CONFIG_ARCH_RPC is not set
178# CONFIG_ARCH_SA1100 is not set 220# CONFIG_ARCH_SA1100 is not set
179# CONFIG_ARCH_S3C2410 is not set 221# CONFIG_ARCH_S3C2410 is not set
180# CONFIG_ARCH_S3C64XX is not set 222# CONFIG_ARCH_S3C64XX is not set
223# CONFIG_ARCH_S5P6440 is not set
224# CONFIG_ARCH_S5P6442 is not set
181# CONFIG_ARCH_S5PC1XX is not set 225# CONFIG_ARCH_S5PC1XX is not set
226# CONFIG_ARCH_S5PV210 is not set
182# CONFIG_ARCH_SHARK is not set 227# CONFIG_ARCH_SHARK is not set
183# CONFIG_ARCH_LH7A40X is not set 228# CONFIG_ARCH_LH7A40X is not set
184# CONFIG_ARCH_U300 is not set 229# CONFIG_ARCH_U300 is not set
230# CONFIG_ARCH_U8500 is not set
231# CONFIG_ARCH_NOMADIK is not set
185# CONFIG_ARCH_DAVINCI is not set 232# CONFIG_ARCH_DAVINCI is not set
186CONFIG_ARCH_OMAP=y 233CONFIG_ARCH_OMAP=y
187# CONFIG_ARCH_BCMRING is not set
188 234
189# 235#
190# TI OMAP Implementations 236# TI OMAP Implementations
191# 237#
192# CONFIG_ARCH_OMAP1 is not set 238# CONFIG_ARCH_OMAP1 is not set
239CONFIG_ARCH_OMAP2PLUS=y
193# CONFIG_ARCH_OMAP2 is not set 240# CONFIG_ARCH_OMAP2 is not set
194# CONFIG_ARCH_OMAP3 is not set 241# CONFIG_ARCH_OMAP3 is not set
195CONFIG_ARCH_OMAP4=y 242CONFIG_ARCH_OMAP4=y
@@ -205,10 +252,6 @@ CONFIG_OMAP_MCBSP=y
205CONFIG_OMAP_32K_TIMER=y 252CONFIG_OMAP_32K_TIMER=y
206CONFIG_OMAP_32K_TIMER_HZ=128 253CONFIG_OMAP_32K_TIMER_HZ=128
207CONFIG_OMAP_DM_TIMER=y 254CONFIG_OMAP_DM_TIMER=y
208# CONFIG_OMAP_LL_DEBUG_UART1 is not set
209# CONFIG_OMAP_LL_DEBUG_UART2 is not set
210CONFIG_OMAP_LL_DEBUG_UART3=y
211# CONFIG_OMAP_LL_DEBUG_NONE is not set
212# CONFIG_OMAP_PM_NONE is not set 255# CONFIG_OMAP_PM_NONE is not set
213CONFIG_OMAP_PM_NOOP=y 256CONFIG_OMAP_PM_NOOP=y
214 257
@@ -243,13 +286,16 @@ CONFIG_CPU_CP15_MMU=y
243# CONFIG_CPU_BPREDICT_DISABLE is not set 286# CONFIG_CPU_BPREDICT_DISABLE is not set
244CONFIG_HAS_TLS_REG=y 287CONFIG_HAS_TLS_REG=y
245CONFIG_OUTER_CACHE=y 288CONFIG_OUTER_CACHE=y
289CONFIG_OUTER_CACHE_SYNC=y
246CONFIG_CACHE_L2X0=y 290CONFIG_CACHE_L2X0=y
247CONFIG_ARM_L1_CACHE_SHIFT=5 291CONFIG_ARM_L1_CACHE_SHIFT=5
292CONFIG_CPU_HAS_PMU=y
248# CONFIG_ARM_ERRATA_430973 is not set 293# CONFIG_ARM_ERRATA_430973 is not set
249# CONFIG_ARM_ERRATA_458693 is not set 294# CONFIG_ARM_ERRATA_458693 is not set
250# CONFIG_ARM_ERRATA_460075 is not set 295# CONFIG_ARM_ERRATA_460075 is not set
251CONFIG_PL310_ERRATA_588369=y 296CONFIG_PL310_ERRATA_588369=y
252CONFIG_ARM_GIC=y 297CONFIG_ARM_GIC=y
298CONFIG_COMMON_CLKDEV=y
253 299
254# 300#
255# Bus support 301# Bus support
@@ -280,6 +326,7 @@ CONFIG_HZ=128
280# CONFIG_THUMB2_KERNEL is not set 326# CONFIG_THUMB2_KERNEL is not set
281CONFIG_AEABI=y 327CONFIG_AEABI=y
282CONFIG_OABI_COMPAT=y 328CONFIG_OABI_COMPAT=y
329CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
283# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set 330# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
284# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set 331# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
285# CONFIG_HIGHMEM is not set 332# CONFIG_HIGHMEM is not set
@@ -294,8 +341,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
294# CONFIG_PHYS_ADDR_T_64BIT is not set 341# CONFIG_PHYS_ADDR_T_64BIT is not set
295CONFIG_ZONE_DMA_FLAG=0 342CONFIG_ZONE_DMA_FLAG=0
296CONFIG_VIRT_TO_BUS=y 343CONFIG_VIRT_TO_BUS=y
297CONFIG_HAVE_MLOCK=y
298CONFIG_HAVE_MLOCKED_PAGE_BIT=y
299# CONFIG_KSM is not set 344# CONFIG_KSM is not set
300CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 345CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
301# CONFIG_LEDS is not set 346# CONFIG_LEDS is not set
@@ -343,7 +388,83 @@ CONFIG_BINFMT_MISC=y
343# 388#
344# CONFIG_PM is not set 389# CONFIG_PM is not set
345CONFIG_ARCH_SUSPEND_POSSIBLE=y 390CONFIG_ARCH_SUSPEND_POSSIBLE=y
346# CONFIG_NET is not set 391CONFIG_NET=y
392
393#
394# Networking options
395#
396CONFIG_PACKET=y
397# CONFIG_UNIX is not set
398CONFIG_XFRM=y
399# CONFIG_XFRM_USER is not set
400# CONFIG_XFRM_SUB_POLICY is not set
401# CONFIG_XFRM_MIGRATE is not set
402# CONFIG_XFRM_STATISTICS is not set
403# CONFIG_NET_KEY is not set
404CONFIG_INET=y
405# CONFIG_IP_MULTICAST is not set
406# CONFIG_IP_ADVANCED_ROUTER is not set
407CONFIG_IP_FIB_HASH=y
408CONFIG_IP_PNP=y
409CONFIG_IP_PNP_DHCP=y
410CONFIG_IP_PNP_BOOTP=y
411CONFIG_IP_PNP_RARP=y
412# CONFIG_NET_IPIP is not set
413# CONFIG_NET_IPGRE is not set
414# CONFIG_ARPD is not set
415# CONFIG_SYN_COOKIES is not set
416# CONFIG_INET_AH is not set
417# CONFIG_INET_ESP is not set
418# CONFIG_INET_IPCOMP is not set
419# CONFIG_INET_XFRM_TUNNEL is not set
420# CONFIG_INET_TUNNEL is not set
421CONFIG_INET_XFRM_MODE_TRANSPORT=y
422CONFIG_INET_XFRM_MODE_TUNNEL=y
423CONFIG_INET_XFRM_MODE_BEET=y
424CONFIG_INET_LRO=y
425CONFIG_INET_DIAG=y
426CONFIG_INET_TCP_DIAG=y
427# CONFIG_TCP_CONG_ADVANCED is not set
428CONFIG_TCP_CONG_CUBIC=y
429CONFIG_DEFAULT_TCP_CONG="cubic"
430# CONFIG_TCP_MD5SIG is not set
431# CONFIG_IPV6 is not set
432# CONFIG_NETWORK_SECMARK is not set
433# CONFIG_NETFILTER is not set
434# CONFIG_IP_DCCP is not set
435# CONFIG_IP_SCTP is not set
436# CONFIG_RDS is not set
437# CONFIG_TIPC is not set
438# CONFIG_ATM is not set
439# CONFIG_BRIDGE is not set
440# CONFIG_NET_DSA is not set
441# CONFIG_VLAN_8021Q is not set
442# CONFIG_DECNET is not set
443# CONFIG_LLC2 is not set
444# CONFIG_IPX is not set
445# CONFIG_ATALK is not set
446# CONFIG_X25 is not set
447# CONFIG_LAPB is not set
448# CONFIG_ECONET is not set
449# CONFIG_WAN_ROUTER is not set
450# CONFIG_PHONET is not set
451# CONFIG_IEEE802154 is not set
452# CONFIG_NET_SCHED is not set
453# CONFIG_DCB is not set
454
455#
456# Network testing
457#
458# CONFIG_NET_PKTGEN is not set
459# CONFIG_HAMRADIO is not set
460# CONFIG_CAN is not set
461# CONFIG_IRDA is not set
462# CONFIG_BT is not set
463# CONFIG_AF_RXRPC is not set
464# CONFIG_WIRELESS is not set
465# CONFIG_WIMAX is not set
466# CONFIG_RFKILL is not set
467# CONFIG_NET_9P is not set
347 468
348# 469#
349# Device Drivers 470# Device Drivers
@@ -360,17 +481,24 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
360# CONFIG_DEBUG_DRIVER is not set 481# CONFIG_DEBUG_DRIVER is not set
361# CONFIG_DEBUG_DEVRES is not set 482# CONFIG_DEBUG_DEVRES is not set
362# CONFIG_SYS_HYPERVISOR is not set 483# CONFIG_SYS_HYPERVISOR is not set
484# CONFIG_CONNECTOR is not set
363# CONFIG_MTD is not set 485# CONFIG_MTD is not set
364# CONFIG_PARPORT is not set 486# CONFIG_PARPORT is not set
365CONFIG_BLK_DEV=y 487CONFIG_BLK_DEV=y
366# CONFIG_BLK_DEV_COW_COMMON is not set 488# CONFIG_BLK_DEV_COW_COMMON is not set
367CONFIG_BLK_DEV_LOOP=y 489CONFIG_BLK_DEV_LOOP=y
368# CONFIG_BLK_DEV_CRYPTOLOOP is not set 490# CONFIG_BLK_DEV_CRYPTOLOOP is not set
491
492#
493# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
494#
495# CONFIG_BLK_DEV_NBD is not set
369CONFIG_BLK_DEV_RAM=y 496CONFIG_BLK_DEV_RAM=y
370CONFIG_BLK_DEV_RAM_COUNT=16 497CONFIG_BLK_DEV_RAM_COUNT=16
371CONFIG_BLK_DEV_RAM_SIZE=16384 498CONFIG_BLK_DEV_RAM_SIZE=16384
372# CONFIG_BLK_DEV_XIP is not set 499# CONFIG_BLK_DEV_XIP is not set
373# CONFIG_CDROM_PKTCDVD is not set 500# CONFIG_CDROM_PKTCDVD is not set
501# CONFIG_ATA_OVER_ETH is not set
374# CONFIG_MG_DISK is not set 502# CONFIG_MG_DISK is not set
375# CONFIG_MISC_DEVICES is not set 503# CONFIG_MISC_DEVICES is not set
376CONFIG_HAVE_IDE=y 504CONFIG_HAVE_IDE=y
@@ -379,12 +507,56 @@ CONFIG_HAVE_IDE=y
379# 507#
380# SCSI device support 508# SCSI device support
381# 509#
510CONFIG_SCSI_MOD=y
382# CONFIG_RAID_ATTRS is not set 511# CONFIG_RAID_ATTRS is not set
383# CONFIG_SCSI is not set 512# CONFIG_SCSI is not set
384# CONFIG_SCSI_DMA is not set 513# CONFIG_SCSI_DMA is not set
385# CONFIG_SCSI_NETLINK is not set 514# CONFIG_SCSI_NETLINK is not set
386# CONFIG_ATA is not set 515# CONFIG_ATA is not set
387# CONFIG_MD is not set 516# CONFIG_MD is not set
517CONFIG_NETDEVICES=y
518# CONFIG_DUMMY is not set
519# CONFIG_BONDING is not set
520# CONFIG_MACVLAN is not set
521# CONFIG_EQUALIZER is not set
522# CONFIG_TUN is not set
523# CONFIG_VETH is not set
524# CONFIG_PHYLIB is not set
525CONFIG_NET_ETHERNET=y
526CONFIG_MII=y
527# CONFIG_AX88796 is not set
528# CONFIG_SMC91X is not set
529# CONFIG_DM9000 is not set
530# CONFIG_ENC28J60 is not set
531# CONFIG_ETHOC is not set
532# CONFIG_SMC911X is not set
533# CONFIG_SMSC911X is not set
534# CONFIG_DNET is not set
535# CONFIG_IBM_NEW_EMAC_ZMII is not set
536# CONFIG_IBM_NEW_EMAC_RGMII is not set
537# CONFIG_IBM_NEW_EMAC_TAH is not set
538# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
539# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
540# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
541# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
542# CONFIG_B44 is not set
543# CONFIG_KS8842 is not set
544CONFIG_KS8851=y
545# CONFIG_KS8851_MLL is not set
546# CONFIG_NETDEV_1000 is not set
547# CONFIG_NETDEV_10000 is not set
548# CONFIG_WLAN is not set
549
550#
551# Enable WiMAX (Networking options) to see the WiMAX drivers
552#
553# CONFIG_WAN is not set
554# CONFIG_PPP is not set
555# CONFIG_SLIP is not set
556# CONFIG_NETCONSOLE is not set
557# CONFIG_NETPOLL is not set
558# CONFIG_NET_POLL_CONTROLLER is not set
559# CONFIG_ISDN is not set
388# CONFIG_PHONE is not set 560# CONFIG_PHONE is not set
389 561
390# 562#
@@ -393,6 +565,7 @@ CONFIG_HAVE_IDE=y
393CONFIG_INPUT=y 565CONFIG_INPUT=y
394# CONFIG_INPUT_FF_MEMLESS is not set 566# CONFIG_INPUT_FF_MEMLESS is not set
395# CONFIG_INPUT_POLLDEV is not set 567# CONFIG_INPUT_POLLDEV is not set
568# CONFIG_INPUT_SPARSEKMAP is not set
396 569
397# 570#
398# Userland interfaces 571# Userland interfaces
@@ -445,8 +618,10 @@ CONFIG_SERIAL_8250_RSA=y
445# 618#
446# Non-8250 serial port support 619# Non-8250 serial port support
447# 620#
621# CONFIG_SERIAL_MAX3100 is not set
448CONFIG_SERIAL_CORE=y 622CONFIG_SERIAL_CORE=y
449CONFIG_SERIAL_CORE_CONSOLE=y 623CONFIG_SERIAL_CORE_CONSOLE=y
624# CONFIG_SERIAL_TIMBERDALE is not set
450CONFIG_UNIX98_PTYS=y 625CONFIG_UNIX98_PTYS=y
451# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 626# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
452# CONFIG_LEGACY_PTYS is not set 627# CONFIG_LEGACY_PTYS is not set
@@ -456,8 +631,58 @@ CONFIG_HW_RANDOM=y
456# CONFIG_R3964 is not set 631# CONFIG_R3964 is not set
457# CONFIG_RAW_DRIVER is not set 632# CONFIG_RAW_DRIVER is not set
458# CONFIG_TCG_TPM is not set 633# CONFIG_TCG_TPM is not set
459# CONFIG_I2C is not set 634CONFIG_I2C=y
460# CONFIG_SPI is not set 635CONFIG_I2C_BOARDINFO=y
636CONFIG_I2C_COMPAT=y
637CONFIG_I2C_CHARDEV=y
638CONFIG_I2C_HELPER_AUTO=y
639
640#
641# I2C Hardware Bus support
642#
643
644#
645# I2C system bus drivers (mostly embedded / system-on-chip)
646#
647# CONFIG_I2C_DESIGNWARE is not set
648# CONFIG_I2C_GPIO is not set
649# CONFIG_I2C_OCORES is not set
650CONFIG_I2C_OMAP=y
651# CONFIG_I2C_SIMTEC is not set
652# CONFIG_I2C_XILINX is not set
653
654#
655# External I2C/SMBus adapter drivers
656#
657# CONFIG_I2C_PARPORT_LIGHT is not set
658# CONFIG_I2C_TAOS_EVM is not set
659
660#
661# Other I2C/SMBus bus drivers
662#
663# CONFIG_I2C_PCA_PLATFORM is not set
664# CONFIG_I2C_STUB is not set
665# CONFIG_I2C_DEBUG_CORE is not set
666# CONFIG_I2C_DEBUG_ALGO is not set
667# CONFIG_I2C_DEBUG_BUS is not set
668CONFIG_SPI=y
669# CONFIG_SPI_DEBUG is not set
670CONFIG_SPI_MASTER=y
671
672#
673# SPI Master Controller Drivers
674#
675# CONFIG_SPI_BITBANG is not set
676# CONFIG_SPI_GPIO is not set
677CONFIG_SPI_OMAP24XX=y
678# CONFIG_SPI_XILINX is not set
679# CONFIG_SPI_DESIGNWARE is not set
680
681#
682# SPI Protocol Masters
683#
684# CONFIG_SPI_SPIDEV is not set
685# CONFIG_SPI_TLE62X0 is not set
461 686
462# 687#
463# PPS support 688# PPS support
@@ -471,10 +696,17 @@ CONFIG_GPIOLIB=y
471# 696#
472# Memory mapped GPIO expanders: 697# Memory mapped GPIO expanders:
473# 698#
699# CONFIG_GPIO_IT8761E is not set
474 700
475# 701#
476# I2C GPIO expanders: 702# I2C GPIO expanders:
477# 703#
704# CONFIG_GPIO_MAX7300 is not set
705# CONFIG_GPIO_MAX732X is not set
706# CONFIG_GPIO_PCA953X is not set
707# CONFIG_GPIO_PCF857X is not set
708# CONFIG_GPIO_TWL4030 is not set
709# CONFIG_GPIO_ADP5588 is not set
478 710
479# 711#
480# PCI GPIO expanders: 712# PCI GPIO expanders:
@@ -483,6 +715,9 @@ CONFIG_GPIOLIB=y
483# 715#
484# SPI GPIO expanders: 716# SPI GPIO expanders:
485# 717#
718# CONFIG_GPIO_MAX7301 is not set
719# CONFIG_GPIO_MCP23S08 is not set
720# CONFIG_GPIO_MC33880 is not set
486 721
487# 722#
488# AC97 GPIO expanders: 723# AC97 GPIO expanders:
@@ -492,7 +727,15 @@ CONFIG_GPIOLIB=y
492# CONFIG_HWMON is not set 727# CONFIG_HWMON is not set
493# CONFIG_THERMAL is not set 728# CONFIG_THERMAL is not set
494CONFIG_WATCHDOG=y 729CONFIG_WATCHDOG=y
730# CONFIG_WATCHDOG_NOWAYOUT is not set
731
732#
733# Watchdog Device Drivers
734#
735# CONFIG_SOFT_WATCHDOG is not set
495CONFIG_OMAP_WATCHDOG=y 736CONFIG_OMAP_WATCHDOG=y
737# CONFIG_TWL4030_WATCHDOG is not set
738# CONFIG_MAX63XX_WATCHDOG is not set
496CONFIG_SSB_POSSIBLE=y 739CONFIG_SSB_POSSIBLE=y
497 740
498# 741#
@@ -504,15 +747,46 @@ CONFIG_SSB_POSSIBLE=y
504# Multifunction device drivers 747# Multifunction device drivers
505# 748#
506# CONFIG_MFD_CORE is not set 749# CONFIG_MFD_CORE is not set
750# CONFIG_MFD_88PM860X is not set
507# CONFIG_MFD_SM501 is not set 751# CONFIG_MFD_SM501 is not set
508# CONFIG_MFD_ASIC3 is not set 752# CONFIG_MFD_ASIC3 is not set
509# CONFIG_HTC_EGPIO is not set 753# CONFIG_HTC_EGPIO is not set
510# CONFIG_HTC_PASIC3 is not set 754# CONFIG_HTC_PASIC3 is not set
755# CONFIG_HTC_I2CPLD is not set
756# CONFIG_TPS65010 is not set
757CONFIG_TWL4030_CORE=y
758# CONFIG_TWL4030_POWER is not set
759# CONFIG_TWL4030_CODEC is not set
511# CONFIG_MFD_TMIO is not set 760# CONFIG_MFD_TMIO is not set
512# CONFIG_MFD_T7L66XB is not set 761# CONFIG_MFD_T7L66XB is not set
513# CONFIG_MFD_TC6387XB is not set 762# CONFIG_MFD_TC6387XB is not set
514# CONFIG_MFD_TC6393XB is not set 763# CONFIG_MFD_TC6393XB is not set
515# CONFIG_REGULATOR is not set 764# CONFIG_PMIC_DA903X is not set
765# CONFIG_PMIC_ADP5520 is not set
766# CONFIG_MFD_MAX8925 is not set
767# CONFIG_MFD_WM8400 is not set
768# CONFIG_MFD_WM831X is not set
769# CONFIG_MFD_WM8350_I2C is not set
770# CONFIG_MFD_WM8994 is not set
771# CONFIG_MFD_PCF50633 is not set
772# CONFIG_MFD_MC13783 is not set
773# CONFIG_AB3100_CORE is not set
774# CONFIG_EZX_PCAP is not set
775# CONFIG_AB4500_CORE is not set
776CONFIG_REGULATOR=y
777# CONFIG_REGULATOR_DEBUG is not set
778# CONFIG_REGULATOR_DUMMY is not set
779# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
780# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
781# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
782# CONFIG_REGULATOR_BQ24022 is not set
783# CONFIG_REGULATOR_MAX1586 is not set
784# CONFIG_REGULATOR_MAX8649 is not set
785# CONFIG_REGULATOR_MAX8660 is not set
786CONFIG_REGULATOR_TWL4030=y
787# CONFIG_REGULATOR_LP3971 is not set
788# CONFIG_REGULATOR_TPS65023 is not set
789# CONFIG_REGULATOR_TPS6507X is not set
516# CONFIG_MEDIA_SUPPORT is not set 790# CONFIG_MEDIA_SUPPORT is not set
517 791
518# 792#
@@ -536,12 +810,94 @@ CONFIG_DUMMY_CONSOLE=y
536# CONFIG_SOUND is not set 810# CONFIG_SOUND is not set
537# CONFIG_HID_SUPPORT is not set 811# CONFIG_HID_SUPPORT is not set
538# CONFIG_USB_SUPPORT is not set 812# CONFIG_USB_SUPPORT is not set
539# CONFIG_MMC is not set 813CONFIG_MMC=y
814# CONFIG_MMC_DEBUG is not set
815# CONFIG_MMC_UNSAFE_RESUME is not set
816
817#
818# MMC/SD/SDIO Card Drivers
819#
820CONFIG_MMC_BLOCK=y
821CONFIG_MMC_BLOCK_BOUNCE=y
822# CONFIG_SDIO_UART is not set
823# CONFIG_MMC_TEST is not set
824
825#
826# MMC/SD/SDIO Host Controller Drivers
827#
828# CONFIG_MMC_SDHCI is not set
829# CONFIG_MMC_OMAP is not set
830CONFIG_MMC_OMAP_HS=y
540# CONFIG_MEMSTICK is not set 831# CONFIG_MEMSTICK is not set
541# CONFIG_NEW_LEDS is not set 832# CONFIG_NEW_LEDS is not set
542# CONFIG_ACCESSIBILITY is not set 833# CONFIG_ACCESSIBILITY is not set
543CONFIG_RTC_LIB=y 834CONFIG_RTC_LIB=y
544# CONFIG_RTC_CLASS is not set 835CONFIG_RTC_CLASS=y
836CONFIG_RTC_HCTOSYS=y
837CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
838# CONFIG_RTC_DEBUG is not set
839
840#
841# RTC interfaces
842#
843CONFIG_RTC_INTF_SYSFS=y
844CONFIG_RTC_INTF_PROC=y
845CONFIG_RTC_INTF_DEV=y
846# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
847# CONFIG_RTC_DRV_TEST is not set
848
849#
850# I2C RTC drivers
851#
852# CONFIG_RTC_DRV_DS1307 is not set
853# CONFIG_RTC_DRV_DS1374 is not set
854# CONFIG_RTC_DRV_DS1672 is not set
855# CONFIG_RTC_DRV_MAX6900 is not set
856# CONFIG_RTC_DRV_RS5C372 is not set
857# CONFIG_RTC_DRV_ISL1208 is not set
858# CONFIG_RTC_DRV_X1205 is not set
859# CONFIG_RTC_DRV_PCF8563 is not set
860# CONFIG_RTC_DRV_PCF8583 is not set
861# CONFIG_RTC_DRV_M41T80 is not set
862# CONFIG_RTC_DRV_BQ32K is not set
863CONFIG_RTC_DRV_TWL4030=y
864# CONFIG_RTC_DRV_S35390A is not set
865# CONFIG_RTC_DRV_FM3130 is not set
866# CONFIG_RTC_DRV_RX8581 is not set
867# CONFIG_RTC_DRV_RX8025 is not set
868
869#
870# SPI RTC drivers
871#
872# CONFIG_RTC_DRV_M41T94 is not set
873# CONFIG_RTC_DRV_DS1305 is not set
874# CONFIG_RTC_DRV_DS1390 is not set
875# CONFIG_RTC_DRV_MAX6902 is not set
876# CONFIG_RTC_DRV_R9701 is not set
877# CONFIG_RTC_DRV_RS5C348 is not set
878# CONFIG_RTC_DRV_DS3234 is not set
879# CONFIG_RTC_DRV_PCF2123 is not set
880
881#
882# Platform RTC drivers
883#
884# CONFIG_RTC_DRV_CMOS is not set
885# CONFIG_RTC_DRV_DS1286 is not set
886# CONFIG_RTC_DRV_DS1511 is not set
887# CONFIG_RTC_DRV_DS1553 is not set
888# CONFIG_RTC_DRV_DS1742 is not set
889# CONFIG_RTC_DRV_STK17TA8 is not set
890# CONFIG_RTC_DRV_M48T86 is not set
891# CONFIG_RTC_DRV_M48T35 is not set
892# CONFIG_RTC_DRV_M48T59 is not set
893# CONFIG_RTC_DRV_MSM6242 is not set
894# CONFIG_RTC_DRV_BQ4802 is not set
895# CONFIG_RTC_DRV_RP5C01 is not set
896# CONFIG_RTC_DRV_V3020 is not set
897
898#
899# on-CPU RTC drivers
900#
545# CONFIG_DMADEVICES is not set 901# CONFIG_DMADEVICES is not set
546# CONFIG_AUXDISPLAY is not set 902# CONFIG_AUXDISPLAY is not set
547# CONFIG_UIO is not set 903# CONFIG_UIO is not set
@@ -564,9 +920,10 @@ CONFIG_EXT3_FS=y
564CONFIG_JBD=y 920CONFIG_JBD=y
565# CONFIG_REISERFS_FS is not set 921# CONFIG_REISERFS_FS is not set
566# CONFIG_JFS_FS is not set 922# CONFIG_JFS_FS is not set
567# CONFIG_FS_POSIX_ACL is not set 923CONFIG_FS_POSIX_ACL=y
568# CONFIG_XFS_FS is not set 924# CONFIG_XFS_FS is not set
569# CONFIG_GFS2_FS is not set 925# CONFIG_GFS2_FS is not set
926# CONFIG_OCFS2_FS is not set
570# CONFIG_BTRFS_FS is not set 927# CONFIG_BTRFS_FS is not set
571# CONFIG_NILFS2_FS is not set 928# CONFIG_NILFS2_FS is not set
572CONFIG_FILE_LOCKING=y 929CONFIG_FILE_LOCKING=y
@@ -575,7 +932,9 @@ CONFIG_DNOTIFY=y
575CONFIG_INOTIFY=y 932CONFIG_INOTIFY=y
576CONFIG_INOTIFY_USER=y 933CONFIG_INOTIFY_USER=y
577CONFIG_QUOTA=y 934CONFIG_QUOTA=y
935# CONFIG_QUOTA_NETLINK_INTERFACE is not set
578CONFIG_PRINT_QUOTA_WARNING=y 936CONFIG_PRINT_QUOTA_WARNING=y
937# CONFIG_QUOTA_DEBUG is not set
579CONFIG_QUOTA_TREE=y 938CONFIG_QUOTA_TREE=y
580# CONFIG_QFMT_V1 is not set 939# CONFIG_QFMT_V1 is not set
581CONFIG_QFMT_V2=y 940CONFIG_QFMT_V2=y
@@ -624,6 +983,7 @@ CONFIG_MISC_FILESYSTEMS=y
624# CONFIG_BEFS_FS is not set 983# CONFIG_BEFS_FS is not set
625# CONFIG_BFS_FS is not set 984# CONFIG_BFS_FS is not set
626# CONFIG_EFS_FS is not set 985# CONFIG_EFS_FS is not set
986# CONFIG_LOGFS is not set
627# CONFIG_CRAMFS is not set 987# CONFIG_CRAMFS is not set
628# CONFIG_SQUASHFS is not set 988# CONFIG_SQUASHFS is not set
629# CONFIG_VXFS_FS is not set 989# CONFIG_VXFS_FS is not set
@@ -634,6 +994,28 @@ CONFIG_MISC_FILESYSTEMS=y
634# CONFIG_ROMFS_FS is not set 994# CONFIG_ROMFS_FS is not set
635# CONFIG_SYSV_FS is not set 995# CONFIG_SYSV_FS is not set
636# CONFIG_UFS_FS is not set 996# CONFIG_UFS_FS is not set
997CONFIG_NETWORK_FILESYSTEMS=y
998CONFIG_NFS_FS=y
999CONFIG_NFS_V3=y
1000CONFIG_NFS_V3_ACL=y
1001CONFIG_NFS_V4=y
1002# CONFIG_NFS_V4_1 is not set
1003CONFIG_ROOT_NFS=y
1004# CONFIG_NFSD is not set
1005CONFIG_LOCKD=y
1006CONFIG_LOCKD_V4=y
1007CONFIG_NFS_ACL_SUPPORT=y
1008CONFIG_NFS_COMMON=y
1009CONFIG_SUNRPC=y
1010CONFIG_SUNRPC_GSS=y
1011CONFIG_RPCSEC_GSS_KRB5=y
1012# CONFIG_RPCSEC_GSS_SPKM3 is not set
1013# CONFIG_SMB_FS is not set
1014# CONFIG_CEPH_FS is not set
1015# CONFIG_CIFS is not set
1016# CONFIG_NCP_FS is not set
1017# CONFIG_CODA_FS is not set
1018# CONFIG_AFS_FS is not set
637 1019
638# 1020#
639# Partition Types 1021# Partition Types
@@ -696,6 +1078,7 @@ CONFIG_NLS_ISO8859_1=y
696# CONFIG_NLS_KOI8_R is not set 1078# CONFIG_NLS_KOI8_R is not set
697# CONFIG_NLS_KOI8_U is not set 1079# CONFIG_NLS_KOI8_U is not set
698# CONFIG_NLS_UTF8 is not set 1080# CONFIG_NLS_UTF8 is not set
1081# CONFIG_DLM is not set
699 1082
700# 1083#
701# Kernel hacking 1084# Kernel hacking
@@ -750,13 +1133,11 @@ CONFIG_FRAME_POINTER=y
750# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set 1133# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
751# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set 1134# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
752# CONFIG_FAULT_INJECTION is not set 1135# CONFIG_FAULT_INJECTION is not set
1136# CONFIG_SYSCTL_SYSCALL_CHECK is not set
753# CONFIG_PAGE_POISONING is not set 1137# CONFIG_PAGE_POISONING is not set
754CONFIG_HAVE_FUNCTION_TRACER=y 1138CONFIG_HAVE_FUNCTION_TRACER=y
755CONFIG_TRACING_SUPPORT=y 1139CONFIG_TRACING_SUPPORT=y
756# CONFIG_FTRACE is not set 1140# CONFIG_FTRACE is not set
757# CONFIG_BRANCH_PROFILE_NONE is not set
758# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
759# CONFIG_PROFILE_ALL_BRANCHES is not set
760# CONFIG_SAMPLES is not set 1141# CONFIG_SAMPLES is not set
761CONFIG_HAVE_ARCH_KGDB=y 1142CONFIG_HAVE_ARCH_KGDB=y
762# CONFIG_KGDB is not set 1143# CONFIG_KGDB is not set
@@ -765,6 +1146,7 @@ CONFIG_HAVE_ARCH_KGDB=y
765# CONFIG_DEBUG_ERRORS is not set 1146# CONFIG_DEBUG_ERRORS is not set
766# CONFIG_DEBUG_STACK_USAGE is not set 1147# CONFIG_DEBUG_STACK_USAGE is not set
767# CONFIG_DEBUG_LL is not set 1148# CONFIG_DEBUG_LL is not set
1149# CONFIG_OC_ETM is not set
768 1150
769# 1151#
770# Security options 1152# Security options
@@ -772,7 +1154,11 @@ CONFIG_HAVE_ARCH_KGDB=y
772# CONFIG_KEYS is not set 1154# CONFIG_KEYS is not set
773# CONFIG_SECURITY is not set 1155# CONFIG_SECURITY is not set
774# CONFIG_SECURITYFS is not set 1156# CONFIG_SECURITYFS is not set
775# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1157# CONFIG_DEFAULT_SECURITY_SELINUX is not set
1158# CONFIG_DEFAULT_SECURITY_SMACK is not set
1159# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
1160CONFIG_DEFAULT_SECURITY_DAC=y
1161CONFIG_DEFAULT_SECURITY=""
776CONFIG_CRYPTO=y 1162CONFIG_CRYPTO=y
777 1163
778# 1164#
@@ -791,6 +1177,7 @@ CONFIG_CRYPTO_MANAGER=y
791CONFIG_CRYPTO_MANAGER2=y 1177CONFIG_CRYPTO_MANAGER2=y
792# CONFIG_CRYPTO_GF128MUL is not set 1178# CONFIG_CRYPTO_GF128MUL is not set
793# CONFIG_CRYPTO_NULL is not set 1179# CONFIG_CRYPTO_NULL is not set
1180# CONFIG_CRYPTO_PCRYPT is not set
794CONFIG_CRYPTO_WORKQUEUE=y 1181CONFIG_CRYPTO_WORKQUEUE=y
795# CONFIG_CRYPTO_CRYPTD is not set 1182# CONFIG_CRYPTO_CRYPTD is not set
796# CONFIG_CRYPTO_AUTHENC is not set 1183# CONFIG_CRYPTO_AUTHENC is not set
@@ -889,3 +1276,4 @@ CONFIG_DECOMPRESS_GZIP=y
889CONFIG_HAS_IOMEM=y 1276CONFIG_HAS_IOMEM=y
890CONFIG_HAS_IOPORT=y 1277CONFIG_HAS_IOPORT=y
891CONFIG_HAS_DMA=y 1278CONFIG_HAS_DMA=y
1279CONFIG_NLATTR=y
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 27f489747bbd..b18d7c28ab7a 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -152,6 +152,16 @@ config MACH_AMS_DELTA
152 Support for the Amstrad E3 (codename Delta) videophone. Say Y here 152 Support for the Amstrad E3 (codename Delta) videophone. Say Y here
153 if you have such a device. 153 if you have such a device.
154 154
155config AMS_DELTA_FIQ
156 bool "Fast Interrupt Request (FIQ) support for the E3"
157 depends on MACH_AMS_DELTA
158 select FIQ
159 help
160 Provide a FIQ handler for the E3.
161 This allows for fast handling of interrupts generated
162 by the clock line of the E3 mailboard (or a PS/2 keyboard)
163 connected to the GPIO based external keyboard port.
164
155config MACH_OMAP_GENERIC 165config MACH_OMAP_GENERIC
156 bool "Generic OMAP board" 166 bool "Generic OMAP board"
157 depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX) 167 depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX)
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index b6a537c875b8..ea231c7a550a 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o
37obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o 37obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o
38obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o 38obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o
39obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o 39obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o
40obj-$(CONFIG_AMS_DELTA_FIQ) += ams-delta-fiq.o ams-delta-fiq-handler.o
40obj-$(CONFIG_MACH_SX1) += board-sx1.o board-sx1-mmc.o 41obj-$(CONFIG_MACH_SX1) += board-sx1.o board-sx1-mmc.o
41obj-$(CONFIG_MACH_HERALD) += board-htcherald.o 42obj-$(CONFIG_MACH_HERALD) += board-htcherald.o
42 43
diff --git a/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
new file mode 100644
index 000000000000..927d5a181760
--- /dev/null
+++ b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
@@ -0,0 +1,278 @@
1/*
2 * linux/arch/arm/mach-omap1/ams-delta-fiq-handler.S
3 *
4 * Based on linux/arch/arm/lib/floppydma.S
5 * Renamed and modified to work with 2.6 kernel by Matt Callow
6 * Copyright (C) 1995, 1996 Russell King
7 * Copyright (C) 2004 Pete Trapps
8 * Copyright (C) 2006 Matt Callow
9 * Copyright (C) 2010 Janusz Krzysztofik
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2
13 * as published by the Free Software Foundation.
14 */
15
16#include <linux/linkage.h>
17
18#include <plat/io.h>
19#include <plat/board-ams-delta.h>
20
21#include <mach/ams-delta-fiq.h>
22
23/*
24 * GPIO related definitions, copied from arch/arm/plat-omap/gpio.c.
25 * Unfortunately, those were not placed in a separate header file.
26 */
27#define OMAP1510_GPIO_BASE 0xFFFCE000
28#define OMAP1510_GPIO_DATA_INPUT 0x00
29#define OMAP1510_GPIO_DATA_OUTPUT 0x04
30#define OMAP1510_GPIO_DIR_CONTROL 0x08
31#define OMAP1510_GPIO_INT_CONTROL 0x0c
32#define OMAP1510_GPIO_INT_MASK 0x10
33#define OMAP1510_GPIO_INT_STATUS 0x14
34#define OMAP1510_GPIO_PIN_CONTROL 0x18
35
36/* GPIO register bitmasks */
37#define KEYBRD_DATA_MASK (0x1 << AMS_DELTA_GPIO_PIN_KEYBRD_DATA)
38#define KEYBRD_CLK_MASK (0x1 << AMS_DELTA_GPIO_PIN_KEYBRD_CLK)
39#define MODEM_IRQ_MASK (0x1 << AMS_DELTA_GPIO_PIN_MODEM_IRQ)
40#define HOOK_SWITCH_MASK (0x1 << AMS_DELTA_GPIO_PIN_HOOK_SWITCH)
41#define OTHERS_MASK (MODEM_IRQ_MASK | HOOK_SWITCH_MASK)
42
43/* IRQ handler register bitmasks */
44#define DEFERRED_FIQ_MASK (0x1 << (INT_DEFERRED_FIQ % IH2_BASE))
45#define GPIO_BANK1_MASK (0x1 << INT_GPIO_BANK1)
46
47/* Driver buffer byte offsets */
48#define BUF_MASK (FIQ_MASK * 4)
49#define BUF_STATE (FIQ_STATE * 4)
50#define BUF_KEYS_CNT (FIQ_KEYS_CNT * 4)
51#define BUF_TAIL_OFFSET (FIQ_TAIL_OFFSET * 4)
52#define BUF_HEAD_OFFSET (FIQ_HEAD_OFFSET * 4)
53#define BUF_BUF_LEN (FIQ_BUF_LEN * 4)
54#define BUF_KEY (FIQ_KEY * 4)
55#define BUF_MISSED_KEYS (FIQ_MISSED_KEYS * 4)
56#define BUF_BUFFER_START (FIQ_BUFFER_START * 4)
57#define BUF_GPIO_INT_MASK (FIQ_GPIO_INT_MASK * 4)
58#define BUF_KEYS_HICNT (FIQ_KEYS_HICNT * 4)
59#define BUF_IRQ_PEND (FIQ_IRQ_PEND * 4)
60#define BUF_SIR_CODE_L1 (FIQ_SIR_CODE_L1 * 4)
61#define BUF_SIR_CODE_L2 (IRQ_SIR_CODE_L2 * 4)
62#define BUF_CNT_INT_00 (FIQ_CNT_INT_00 * 4)
63#define BUF_CNT_INT_KEY (FIQ_CNT_INT_KEY * 4)
64#define BUF_CNT_INT_MDM (FIQ_CNT_INT_MDM * 4)
65#define BUF_CNT_INT_03 (FIQ_CNT_INT_03 * 4)
66#define BUF_CNT_INT_HSW (FIQ_CNT_INT_HSW * 4)
67#define BUF_CNT_INT_05 (FIQ_CNT_INT_05 * 4)
68#define BUF_CNT_INT_06 (FIQ_CNT_INT_06 * 4)
69#define BUF_CNT_INT_07 (FIQ_CNT_INT_07 * 4)
70#define BUF_CNT_INT_08 (FIQ_CNT_INT_08 * 4)
71#define BUF_CNT_INT_09 (FIQ_CNT_INT_09 * 4)
72#define BUF_CNT_INT_10 (FIQ_CNT_INT_10 * 4)
73#define BUF_CNT_INT_11 (FIQ_CNT_INT_11 * 4)
74#define BUF_CNT_INT_12 (FIQ_CNT_INT_12 * 4)
75#define BUF_CNT_INT_13 (FIQ_CNT_INT_13 * 4)
76#define BUF_CNT_INT_14 (FIQ_CNT_INT_14 * 4)
77#define BUF_CNT_INT_15 (FIQ_CNT_INT_15 * 4)
78#define BUF_CIRC_BUFF (FIQ_CIRC_BUFF * 4)
79
80
81/*
82 * Register useage
83 * r8 - temporary
84 * r9 - the driver buffer
85 * r10 - temporary
86 * r11 - interrupts mask
87 * r12 - base pointers
88 * r13 - interrupts status
89 */
90
91 .text
92
93 .global qwerty_fiqin_end
94
95ENTRY(qwerty_fiqin_start)
96 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
97 @ FIQ intrrupt handler
98 ldr r12, omap_ih1_base @ set pointer to level1 handler
99
100 ldr r11, [r12, #IRQ_MIR_REG_OFFSET] @ fetch interrupts mask
101
102 ldr r13, [r12, #IRQ_ITR_REG_OFFSET] @ fetch interrupts status
103 bics r13, r13, r11 @ clear masked - any left?
104 beq exit @ none - spurious FIQ? exit
105
106 ldr r10, [r12, #IRQ_SIR_FIQ_REG_OFFSET] @ get requested interrupt number
107
108 mov r8, #2 @ reset FIQ agreement
109 str r8, [r12, #IRQ_CONTROL_REG_OFFSET]
110
111 cmp r10, #INT_GPIO_BANK1 @ is it GPIO bank interrupt?
112 beq gpio @ yes - process it
113
114 mov r8, #1
115 orr r8, r11, r8, lsl r10 @ mask spurious interrupt
116 str r8, [r12, #IRQ_MIR_REG_OFFSET]
117exit:
118 subs pc, lr, #4 @ return from FIQ
119 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
120
121
122 @@@@@@@@@@@@@@@@@@@@@@@@@@@
123gpio: @ GPIO bank interrupt handler
124 ldr r12, omap1510_gpio_base @ set base pointer to GPIO bank
125
126 ldr r11, [r12, #OMAP1510_GPIO_INT_MASK] @ fetch GPIO interrupts mask
127restart:
128 ldr r13, [r12, #OMAP1510_GPIO_INT_STATUS] @ fetch status bits
129 bics r13, r13, r11 @ clear masked - any left?
130 beq exit @ no - spurious interrupt? exit
131
132 orr r11, r11, r13 @ mask all requested interrupts
133 str r11, [r12, #OMAP1510_GPIO_INT_MASK]
134
135 ands r10, r13, #KEYBRD_CLK_MASK @ extract keyboard status - set?
136 beq hksw @ no - try next source
137
138
139 @@@@@@@@@@@@@@@@@@@@@@
140 @ Keyboard clock FIQ mode interrupt handler
141 @ r10 now contains KEYBRD_CLK_MASK, use it
142 str r10, [r12, #OMAP1510_GPIO_INT_STATUS] @ ack the interrupt
143 bic r11, r11, r10 @ unmask it
144 str r11, [r12, #OMAP1510_GPIO_INT_MASK]
145
146 @ Process keyboard data
147 ldr r8, [r12, #OMAP1510_GPIO_DATA_INPUT] @ fetch GPIO input
148
149 ldr r10, [r9, #BUF_STATE] @ fetch kbd interface state
150 cmp r10, #0 @ are we expecting start bit?
151 bne data @ no - go to data processing
152
153 ands r8, r8, #KEYBRD_DATA_MASK @ check start bit - detected?
154 beq hksw @ no - try next source
155
156 @ r8 contains KEYBRD_DATA_MASK, use it
157 str r8, [r9, #BUF_STATE] @ enter data processing state
158 @ r10 already contains 0, reuse it
159 str r10, [r9, #BUF_KEY] @ clear keycode
160 mov r10, #2 @ reset input bit mask
161 str r10, [r9, #BUF_MASK]
162
163 @ Mask other GPIO line interrupts till key done
164 str r11, [r9, #BUF_GPIO_INT_MASK] @ save mask for later restore
165 mvn r11, #KEYBRD_CLK_MASK @ prepare all except kbd mask
166 str r11, [r12, #OMAP1510_GPIO_INT_MASK] @ store into the mask register
167
168 b restart @ restart
169
170data: ldr r10, [r9, #BUF_MASK] @ fetch current input bit mask
171
172 @ r8 still contains GPIO input bits
173 ands r8, r8, #KEYBRD_DATA_MASK @ is keyboard data line low?
174 ldreq r8, [r9, #BUF_KEY] @ yes - fetch collected so far,
175 orreq r8, r8, r10 @ set 1 at current mask position
176 streq r8, [r9, #BUF_KEY] @ and save back
177
178 mov r10, r10, lsl #1 @ shift mask left
179 bics r10, r10, #0x800 @ have we got all the bits?
180 strne r10, [r9, #BUF_MASK] @ not yet - store the mask
181 bne restart @ and restart
182
183 @ r10 already contains 0, reuse it
184 str r10, [r9, #BUF_STATE] @ reset state to start
185
186 @ Key done - restore interrupt mask
187 ldr r10, [r9, #BUF_GPIO_INT_MASK] @ fetch saved mask
188 and r11, r11, r10 @ unmask all saved as unmasked
189 str r11, [r12, #OMAP1510_GPIO_INT_MASK] @ restore into the mask register
190
191 @ Try appending the keycode to the circular buffer
192 ldr r10, [r9, #BUF_KEYS_CNT] @ get saved keystrokes count
193 ldr r8, [r9, #BUF_BUF_LEN] @ get buffer size
194 cmp r10, r8 @ is buffer full?
195 beq hksw @ yes - key lost, next source
196
197 add r10, r10, #1 @ incremet keystrokes counter
198 str r10, [r9, #BUF_KEYS_CNT]
199
200 ldr r10, [r9, #BUF_TAIL_OFFSET] @ get buffer tail offset
201 @ r8 already contains buffer size
202 cmp r10, r8 @ end of buffer?
203 moveq r10, #0 @ yes - rewind to buffer start
204
205 ldr r12, [r9, #BUF_BUFFER_START] @ get buffer start address
206 add r12, r12, r10, LSL #2 @ calculate buffer tail address
207 ldr r8, [r9, #BUF_KEY] @ get last keycode
208 str r8, [r12] @ append it to the buffer tail
209
210 add r10, r10, #1 @ increment buffer tail offset
211 str r10, [r9, #BUF_TAIL_OFFSET]
212
213 ldr r10, [r9, #BUF_CNT_INT_KEY] @ increment interrupts counter
214 add r10, r10, #1
215 str r10, [r9, #BUF_CNT_INT_KEY]
216 @@@@@@@@@@@@@@@@@@@@@@@@
217
218
219hksw: @Is hook switch interrupt requested?
220 tst r13, #HOOK_SWITCH_MASK @ is hook switch status bit set?
221 beq mdm @ no - try next source
222
223
224 @@@@@@@@@@@@@@@@@@@@@@@@
225 @ Hook switch interrupt FIQ mode simple handler
226
227 @ Don't toggle active edge, the switch always bounces
228
229 @ Increment hook switch interrupt counter
230 ldr r10, [r9, #BUF_CNT_INT_HSW]
231 add r10, r10, #1
232 str r10, [r9, #BUF_CNT_INT_HSW]
233 @@@@@@@@@@@@@@@@@@@@@@@@
234
235
236mdm: @Is it a modem interrupt?
237 tst r13, #MODEM_IRQ_MASK @ is modem status bit set?
238 beq irq @ no - check for next interrupt
239
240
241 @@@@@@@@@@@@@@@@@@@@@@@@
242 @ Modem FIQ mode interrupt handler stub
243
244 @ Increment modem interrupt counter
245 ldr r10, [r9, #BUF_CNT_INT_MDM]
246 add r10, r10, #1
247 str r10, [r9, #BUF_CNT_INT_MDM]
248 @@@@@@@@@@@@@@@@@@@@@@@@
249
250
251irq: @ Place deferred_fiq interrupt request
252 ldr r12, deferred_fiq_ih_base @ set pointer to IRQ handler
253 mov r10, #DEFERRED_FIQ_MASK @ set deferred_fiq bit
254 str r10, [r12, #IRQ_ISR_REG_OFFSET] @ place it in the ISR register
255
256 ldr r12, omap1510_gpio_base @ set pointer back to GPIO bank
257 b restart @ check for next GPIO interrupt
258 @@@@@@@@@@@@@@@@@@@@@@@@@@@
259
260
261/*
262 * Virtual addresses for IO
263 */
264omap_ih1_base:
265 .word OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
266deferred_fiq_ih_base:
267 .word OMAP1_IO_ADDRESS(DEFERRED_FIQ_IH_BASE)
268omap1510_gpio_base:
269 .word OMAP1_IO_ADDRESS(OMAP1510_GPIO_BASE)
270qwerty_fiqin_end:
271
272/*
273 * Check the size of the FIQ,
274 * it cannot go beyond 0xffff0200, and is copied to 0xffff001c
275 */
276.if (qwerty_fiqin_end - qwerty_fiqin_start) > (0x200 - 0x1c)
277 .err
278.endif
diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c
new file mode 100644
index 000000000000..6c994e2d8879
--- /dev/null
+++ b/arch/arm/mach-omap1/ams-delta-fiq.c
@@ -0,0 +1,155 @@
1/*
2 * Amstrad E3 FIQ handling
3 *
4 * Copyright (C) 2009 Janusz Krzysztofik
5 * Copyright (c) 2006 Matt Callow
6 * Copyright (c) 2004 Amstrad Plc
7 * Copyright (C) 2001 RidgeRun, Inc.
8 *
9 * Parts of this code are taken from linux/arch/arm/mach-omap/irq.c
10 * in the MontaVista 2.4 kernel (and the Amstrad changes therein)
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License version 2 as published by
14 * the Free Software Foundation.
15 */
16#include <linux/gpio.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/module.h>
20#include <linux/io.h>
21
22#include <plat/board-ams-delta.h>
23
24#include <asm/fiq.h>
25#include <mach/ams-delta-fiq.h>
26
27static struct fiq_handler fh = {
28 .name = "ams-delta-fiq"
29};
30
31/*
32 * This buffer is shared between FIQ and IRQ contexts.
33 * The FIQ and IRQ isrs can both read and write it.
34 * It is structured as a header section several 32bit slots,
35 * followed by the circular buffer where the FIQ isr stores
36 * keystrokes received from the qwerty keyboard.
37 * See ams-delta-fiq.h for details of offsets.
38 */
39unsigned int fiq_buffer[1024];
40EXPORT_SYMBOL(fiq_buffer);
41
42static unsigned int irq_counter[16];
43
44static irqreturn_t deferred_fiq(int irq, void *dev_id)
45{
46 struct irq_desc *irq_desc;
47 struct irq_chip *irq_chip = NULL;
48 int gpio, irq_num, fiq_count;
49
50 irq_desc = irq_to_desc(IH_GPIO_BASE);
51 if (irq_desc)
52 irq_chip = irq_desc->chip;
53
54 /*
55 * For each handled GPIO interrupt, keep calling its interrupt handler
56 * until the IRQ counter catches the FIQ incremented interrupt counter.
57 */
58 for (gpio = AMS_DELTA_GPIO_PIN_KEYBRD_CLK;
59 gpio <= AMS_DELTA_GPIO_PIN_HOOK_SWITCH; gpio++) {
60 irq_num = gpio_to_irq(gpio);
61 fiq_count = fiq_buffer[FIQ_CNT_INT_00 + gpio];
62
63 while (irq_counter[gpio] < fiq_count) {
64 if (gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) {
65 /*
66 * It looks like handle_edge_irq() that
67 * OMAP GPIO edge interrupts default to,
68 * expects interrupt already unmasked.
69 */
70 if (irq_chip && irq_chip->unmask)
71 irq_chip->unmask(irq_num);
72 }
73 generic_handle_irq(irq_num);
74
75 irq_counter[gpio]++;
76 }
77 }
78 return IRQ_HANDLED;
79}
80
81void __init ams_delta_init_fiq(void)
82{
83 void *fiqhandler_start;
84 unsigned int fiqhandler_length;
85 struct pt_regs FIQ_regs;
86 unsigned long val, offset;
87 int i, retval;
88
89 fiqhandler_start = &qwerty_fiqin_start;
90 fiqhandler_length = &qwerty_fiqin_end - &qwerty_fiqin_start;
91 pr_info("Installing fiq handler from %p, length 0x%x\n",
92 fiqhandler_start, fiqhandler_length);
93
94 retval = claim_fiq(&fh);
95 if (retval) {
96 pr_err("ams_delta_init_fiq(): couldn't claim FIQ, ret=%d\n",
97 retval);
98 return;
99 }
100
101 retval = request_irq(INT_DEFERRED_FIQ, deferred_fiq,
102 IRQ_TYPE_EDGE_RISING, "deferred_fiq", 0);
103 if (retval < 0) {
104 pr_err("Failed to get deferred_fiq IRQ, ret=%d\n", retval);
105 release_fiq(&fh);
106 return;
107 }
108 /*
109 * Since no set_type() method is provided by OMAP irq chip,
110 * switch to edge triggered interrupt type manually.
111 */
112 offset = IRQ_ILR0_REG_OFFSET + INT_DEFERRED_FIQ * 0x4;
113 val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1);
114 omap_writel(val, DEFERRED_FIQ_IH_BASE + offset);
115
116 set_fiq_handler(fiqhandler_start, fiqhandler_length);
117
118 /*
119 * Initialise the buffer which is shared
120 * between FIQ mode and IRQ mode
121 */
122 fiq_buffer[FIQ_GPIO_INT_MASK] = 0;
123 fiq_buffer[FIQ_MASK] = 0;
124 fiq_buffer[FIQ_STATE] = 0;
125 fiq_buffer[FIQ_KEY] = 0;
126 fiq_buffer[FIQ_KEYS_CNT] = 0;
127 fiq_buffer[FIQ_KEYS_HICNT] = 0;
128 fiq_buffer[FIQ_TAIL_OFFSET] = 0;
129 fiq_buffer[FIQ_HEAD_OFFSET] = 0;
130 fiq_buffer[FIQ_BUF_LEN] = 256;
131 fiq_buffer[FIQ_MISSED_KEYS] = 0;
132 fiq_buffer[FIQ_BUFFER_START] =
133 (unsigned int) &fiq_buffer[FIQ_CIRC_BUFF];
134
135 for (i = FIQ_CNT_INT_00; i <= FIQ_CNT_INT_15; i++)
136 fiq_buffer[i] = 0;
137
138 /*
139 * FIQ mode r9 always points to the fiq_buffer, becauses the FIQ isr
140 * will run in an unpredictable context. The fiq_buffer is the FIQ isr's
141 * only means of communication with the IRQ level and other kernel
142 * context code.
143 */
144 FIQ_regs.ARM_r9 = (unsigned int)fiq_buffer;
145 set_fiq_regs(&FIQ_regs);
146
147 pr_info("request_fiq(): fiq_buffer = %p\n", fiq_buffer);
148
149 /*
150 * Redirect GPIO interrupts to FIQ
151 */
152 offset = IRQ_ILR0_REG_OFFSET + INT_GPIO_BANK1 * 0x4;
153 val = omap_readl(OMAP_IH1_BASE + offset) | 1;
154 omap_writel(val, OMAP_IH1_BASE + offset);
155}
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 7fc11c34b696..fdd1dd53fa9c 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -33,6 +33,8 @@
33#include <plat/board.h> 33#include <plat/board.h>
34#include <plat/common.h> 34#include <plat/common.h>
35 35
36#include <mach/ams-delta-fiq.h>
37
36static u8 ams_delta_latch1_reg; 38static u8 ams_delta_latch1_reg;
37static u16 ams_delta_latch2_reg; 39static u16 ams_delta_latch2_reg;
38 40
@@ -236,6 +238,10 @@ static void __init ams_delta_init(void)
236 omap_usb_init(&ams_delta_usb_config); 238 omap_usb_init(&ams_delta_usb_config);
237 platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices)); 239 platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices));
238 240
241#ifdef CONFIG_AMS_DELTA_FIQ
242 ams_delta_init_fiq();
243#endif
244
239 omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1); 245 omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1);
240} 246}
241 247
@@ -263,8 +269,18 @@ static struct platform_device ams_delta_modem_device = {
263 269
264static int __init ams_delta_modem_init(void) 270static int __init ams_delta_modem_init(void)
265{ 271{
272 int err;
273
266 omap_cfg_reg(M14_1510_GPIO2); 274 omap_cfg_reg(M14_1510_GPIO2);
267 ams_delta_modem_ports[0].irq = gpio_to_irq(2); 275 ams_delta_modem_ports[0].irq =
276 gpio_to_irq(AMS_DELTA_GPIO_PIN_MODEM_IRQ);
277
278 err = gpio_request(AMS_DELTA_GPIO_PIN_MODEM_IRQ, "modem");
279 if (err) {
280 pr_err("Couldn't request gpio pin for modem\n");
281 return err;
282 }
283 gpio_direction_input(AMS_DELTA_GPIO_PIN_MODEM_IRQ);
268 284
269 ams_delta_latch2_write( 285 ams_delta_latch2_write(
270 AMS_DELTA_LATCH2_MODEM_NRESET | AMS_DELTA_LATCH2_MODEM_CODEC, 286 AMS_DELTA_LATCH2_MODEM_NRESET | AMS_DELTA_LATCH2_MODEM_CODEC,
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index e0aec1007a0d..6bbb1b8b8294 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -578,7 +578,7 @@ int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
578 578
579#ifdef CONFIG_OMAP_RESET_CLOCKS 579#ifdef CONFIG_OMAP_RESET_CLOCKS
580 580
581void __init omap1_clk_disable_unused(struct clk *clk) 581void omap1_clk_disable_unused(struct clk *clk)
582{ 582{
583 __u32 regval32; 583 __u32 regval32;
584 584
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index a4190afb8614..75d0d7d90bff 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -39,7 +39,7 @@ extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
39extern unsigned long omap1_watchdog_recalc(struct clk *clk); 39extern unsigned long omap1_watchdog_recalc(struct clk *clk);
40 40
41#ifdef CONFIG_OMAP_RESET_CLOCKS 41#ifdef CONFIG_OMAP_RESET_CLOCKS
42extern void __init omap1_clk_disable_unused(struct clk *clk); 42extern void omap1_clk_disable_unused(struct clk *clk);
43#else 43#else
44#define omap1_clk_disable_unused NULL 44#define omap1_clk_disable_unused NULL
45#endif 45#endif
diff --git a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h
new file mode 100644
index 000000000000..7a2df29400ca
--- /dev/null
+++ b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h
@@ -0,0 +1,79 @@
1/*
2 * arch/arm/mach-omap1/include/ams-delta-fiq.h
3 *
4 * Taken from the original Amstrad modifications to fiq.h
5 *
6 * Copyright (c) 2004 Amstrad Plc
7 * Copyright (c) 2006 Matt Callow
8 * Copyright (c) 2010 Janusz Krzysztofik
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#ifndef __AMS_DELTA_FIQ_H
15#define __AMS_DELTA_FIQ_H
16
17#include <plat/irqs.h>
18
19/*
20 * Interrupt number used for passing control from FIQ to IRQ.
21 * IRQ12, described as reserved, has been selected.
22 */
23#define INT_DEFERRED_FIQ INT_1510_RES12
24/*
25 * Base address of an interrupt handler that the INT_DEFERRED_FIQ belongs to.
26 */
27#if (INT_DEFERRED_FIQ < IH2_BASE)
28#define DEFERRED_FIQ_IH_BASE OMAP_IH1_BASE
29#else
30#define DEFERRED_FIQ_IH_BASE OMAP_IH2_BASE
31#endif
32
33/*
34 * These are the offsets from the begining of the fiq_buffer. They are put here
35 * since the buffer and header need to be accessed by drivers servicing devices
36 * which generate GPIO interrupts - e.g. keyboard, modem, hook switch.
37 */
38#define FIQ_MASK 0
39#define FIQ_STATE 1
40#define FIQ_KEYS_CNT 2
41#define FIQ_TAIL_OFFSET 3
42#define FIQ_HEAD_OFFSET 4
43#define FIQ_BUF_LEN 5
44#define FIQ_KEY 6
45#define FIQ_MISSED_KEYS 7
46#define FIQ_BUFFER_START 8
47#define FIQ_GPIO_INT_MASK 9
48#define FIQ_KEYS_HICNT 10
49#define FIQ_IRQ_PEND 11
50#define FIQ_SIR_CODE_L1 12
51#define IRQ_SIR_CODE_L2 13
52
53#define FIQ_CNT_INT_00 14
54#define FIQ_CNT_INT_KEY 15
55#define FIQ_CNT_INT_MDM 16
56#define FIQ_CNT_INT_03 17
57#define FIQ_CNT_INT_HSW 18
58#define FIQ_CNT_INT_05 19
59#define FIQ_CNT_INT_06 20
60#define FIQ_CNT_INT_07 21
61#define FIQ_CNT_INT_08 22
62#define FIQ_CNT_INT_09 23
63#define FIQ_CNT_INT_10 24
64#define FIQ_CNT_INT_11 25
65#define FIQ_CNT_INT_12 26
66#define FIQ_CNT_INT_13 27
67#define FIQ_CNT_INT_14 28
68#define FIQ_CNT_INT_15 29
69
70#define FIQ_CIRC_BUFF 30 /*Start of circular buffer */
71
72#ifndef __ASSEMBLER__
73extern unsigned int fiq_buffer[];
74extern unsigned char qwerty_fiqin_start, qwerty_fiqin_end;
75
76extern void __init ams_delta_init_fiq(void);
77#endif
78
79#endif
diff --git a/arch/arm/mach-omap1/include/mach/debug-macro.S b/arch/arm/mach-omap1/include/mach/debug-macro.S
index b6d9584544b4..e8a8cf36b7f0 100644
--- a/arch/arm/mach-omap1/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap1/include/mach/debug-macro.S
@@ -13,6 +13,8 @@
13 13
14#include <linux/serial_reg.h> 14#include <linux/serial_reg.h>
15 15
16#include <asm/memory.h>
17
16#include <plat/serial.h> 18#include <plat/serial.h>
17 19
18 .pushsection .data 20 .pushsection .data
@@ -37,23 +39,12 @@ omap_uart_virt: .word 0x0
37 cmp \rx, #0 @ is port configured? 39 cmp \rx, #0 @ is port configured?
38 bne 99f @ already configured 40 bne 99f @ already configured
39 41
40 /* Check 7XX UART1 scratchpad register for uart to use */ 42 /* Check the debug UART configuration set in uncompress.h */
41 mrc p15, 0, \rx, c1, c0 43 mrc p15, 0, \rx, c1, c0
42 tst \rx, #1 @ MMU enabled? 44 tst \rx, #1 @ MMU enabled?
43 moveq \rx, #0xff000000 @ physical base address 45 ldreq \rx, =OMAP_UART_INFO
44 movne \rx, #0xfe000000 @ virtual base 46 ldrne \rx, =__phys_to_virt(OMAP_UART_INFO)
45 orr \rx, \rx, #0x00fb0000 @ OMAP1UART1 47 ldr \rx, [\rx, #0]
46 ldrb \rx, [\rx, #(UART_SCR << OMAP7XX_PORT_SHIFT)]
47 cmp \rx, #0 @ anything in 7XX scratchpad?
48 bne 10f @ found 7XX uart
49
50 /* Check 15xx/16xx UART1 scratchpad register for uart to use */
51 mrc p15, 0, \rx, c1, c0
52 tst \rx, #1 @ MMU enabled?
53 moveq \rx, #0xff000000 @ physical base address
54 movne \rx, #0xfe000000 @ virtual base
55 orr \rx, \rx, #0x00fb0000 @ OMAP1UART1
56 ldrb \rx, [\rx, #(UART_SCR << OMAP_PORT_SHIFT)]
57 48
58 /* Select the UART to use based on the UART1 scratchpad value */ 49 /* Select the UART to use based on the UART1 scratchpad value */
5910: cmp \rx, #0 @ no port configured? 5010: cmp \rx, #0 @ no port configured?
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 2455dcc744a0..b31b6f123122 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -10,6 +10,7 @@ config ARCH_OMAP2420
10config ARCH_OMAP2430 10config ARCH_OMAP2430
11 bool "OMAP2430 support" 11 bool "OMAP2430 support"
12 depends on ARCH_OMAP2 12 depends on ARCH_OMAP2
13 select ARCH_OMAP_OTG
13 14
14config ARCH_OMAP3430 15config ARCH_OMAP3430
15 bool "OMAP3430 support" 16 bool "OMAP3430 support"
@@ -141,6 +142,12 @@ config MACH_IGEP0020
141 depends on ARCH_OMAP3 142 depends on ARCH_OMAP3
142 select OMAP_PACKAGE_CBB 143 select OMAP_PACKAGE_CBB
143 144
145config MACH_SBC3530
146 bool "OMAP3 SBC STALKER board"
147 depends on ARCH_OMAP3
148 select OMAP_PACKAGE_CUS
149 select OMAP_MUX
150
144config MACH_OMAP_3630SDP 151config MACH_OMAP_3630SDP
145 bool "OMAP3630 SDP board" 152 bool "OMAP3630 SDP board"
146 depends on ARCH_OMAP3 153 depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 4b9fc57770db..d28e9e5702a0 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -22,7 +22,7 @@ obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
22# SMP support ONLY available for OMAP4 22# SMP support ONLY available for OMAP4
23obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o 23obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o
24obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o 24obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o
25obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o 25obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o
26 26
27AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a 27AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a
28 28
@@ -89,10 +89,7 @@ obj-$(CONFIG_OMAP3_EMU) += emu.o
89obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o 89obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
90mailbox_mach-objs := mailbox.o 90mailbox_mach-objs := mailbox.o
91 91
92iommu-y += iommu2.o 92obj-$(CONFIG_OMAP_IOMMU) := iommu2.o omap-iommu.o
93iommu-$(CONFIG_ARCH_OMAP3) += omap3-iommu.o
94
95obj-$(CONFIG_OMAP_IOMMU) += $(iommu-y)
96 93
97i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o 94i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
98obj-y += $(i2c-omap-m) $(i2c-omap-y) 95obj-y += $(i2c-omap-m) $(i2c-omap-y)
@@ -140,10 +137,13 @@ obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o \
140 hsmmc.o 137 hsmmc.o
141obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ 138obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \
142 hsmmc.o 139 hsmmc.o
143obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o 140obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o \
141 hsmmc.o
144 142
145obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o 143obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o
146 144
145obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o \
146 hsmmc.o
147# Platform specific device init code 147# Platform specific device init code
148obj-y += usb-musb.o 148obj-y += usb-musb.o
149obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o 149obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 01d113ff9fcf..a11a575745e4 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -174,9 +174,18 @@ static struct i2c_board_info __initdata sdp2430_i2c_boardinfo[] = {
174 }, 174 },
175}; 175};
176 176
177static struct i2c_board_info __initdata sdp2430_i2c1_boardinfo[] = {
178 {
179 I2C_BOARD_INFO("isp1301_omap", 0x2D),
180 .flags = I2C_CLIENT_WAKE,
181 .irq = OMAP_GPIO_IRQ(78),
182 },
183};
184
177static int __init omap2430_i2c_init(void) 185static int __init omap2430_i2c_init(void)
178{ 186{
179 omap_register_i2c_bus(1, 400, NULL, 0); 187 omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo,
188 ARRAY_SIZE(sdp2430_i2c1_boardinfo));
180 omap_register_i2c_bus(2, 2600, sdp2430_i2c_boardinfo, 189 omap_register_i2c_bus(2, 2600, sdp2430_i2c_boardinfo,
181 ARRAY_SIZE(sdp2430_i2c_boardinfo)); 190 ARRAY_SIZE(sdp2430_i2c_boardinfo));
182 return 0; 191 return 0;
@@ -198,6 +207,15 @@ static struct omap_musb_board_data musb_board_data = {
198 .mode = MUSB_OTG, 207 .mode = MUSB_OTG,
199 .power = 100, 208 .power = 100,
200}; 209};
210static struct omap_usb_config sdp2430_usb_config __initdata = {
211 .otg = 1,
212#ifdef CONFIG_USB_GADGET_OMAP
213 .hmc_mode = 0x0,
214#elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
215 .hmc_mode = 0x1,
216#endif
217 .pins[0] = 3,
218};
201 219
202static void __init omap_2430sdp_init(void) 220static void __init omap_2430sdp_init(void)
203{ 221{
@@ -208,6 +226,7 @@ static void __init omap_2430sdp_init(void)
208 platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); 226 platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
209 omap_serial_init(); 227 omap_serial_init();
210 omap2_hsmmc_init(mmc); 228 omap2_hsmmc_init(mmc);
229 omap_usb_init(&sdp2430_usb_config);
211 usb_musb_init(&musb_board_data); 230 usb_musb_init(&musb_board_data);
212 board_smc91x_init(); 231 board_smc91x_init();
213 232
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 5822bcf7b15f..e7d629b3c76a 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -150,6 +150,7 @@ static int ads7846_get_pendown_state(void)
150static struct ads7846_platform_data tsc2046_config __initdata = { 150static struct ads7846_platform_data tsc2046_config __initdata = {
151 .get_pendown_state = ads7846_get_pendown_state, 151 .get_pendown_state = ads7846_get_pendown_state,
152 .keep_vref_on = 1, 152 .keep_vref_on = 1,
153 .wakeup = true,
153}; 154};
154 155
155 156
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index b88f28c5814b..e4a5d66b83b8 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -18,8 +18,12 @@
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/gpio.h> 19#include <linux/gpio.h>
20#include <linux/usb/otg.h> 20#include <linux/usb/otg.h>
21#include <linux/spi/spi.h>
22#include <linux/i2c/twl.h>
23#include <linux/regulator/machine.h>
21 24
22#include <mach/hardware.h> 25#include <mach/hardware.h>
26#include <mach/omap4-common.h>
23#include <asm/mach-types.h> 27#include <asm/mach-types.h>
24#include <asm/mach/arch.h> 28#include <asm/mach/arch.h>
25#include <asm/mach/map.h> 29#include <asm/mach/map.h>
@@ -29,8 +33,77 @@
29#include <plat/control.h> 33#include <plat/control.h>
30#include <plat/timer-gp.h> 34#include <plat/timer-gp.h>
31#include <plat/usb.h> 35#include <plat/usb.h>
32#include <asm/hardware/gic.h> 36#include <plat/mmc.h>
33#include <asm/hardware/cache-l2x0.h> 37#include "hsmmc.h"
38
39#define ETH_KS8851_IRQ 34
40#define ETH_KS8851_POWER_ON 48
41#define ETH_KS8851_QUART 138
42
43static struct spi_board_info sdp4430_spi_board_info[] __initdata = {
44 {
45 .modalias = "ks8851",
46 .bus_num = 1,
47 .chip_select = 0,
48 .max_speed_hz = 24000000,
49 .irq = ETH_KS8851_IRQ,
50 },
51};
52
53static int omap_ethernet_init(void)
54{
55 int status;
56
57 /* Request of GPIO lines */
58
59 status = gpio_request(ETH_KS8851_POWER_ON, "eth_power");
60 if (status) {
61 pr_err("Cannot request GPIO %d\n", ETH_KS8851_POWER_ON);
62 return status;
63 }
64
65 status = gpio_request(ETH_KS8851_QUART, "quart");
66 if (status) {
67 pr_err("Cannot request GPIO %d\n", ETH_KS8851_QUART);
68 goto error1;
69 }
70
71 status = gpio_request(ETH_KS8851_IRQ, "eth_irq");
72 if (status) {
73 pr_err("Cannot request GPIO %d\n", ETH_KS8851_IRQ);
74 goto error2;
75 }
76
77 /* Configuration of requested GPIO lines */
78
79 status = gpio_direction_output(ETH_KS8851_POWER_ON, 1);
80 if (status) {
81 pr_err("Cannot set output GPIO %d\n", ETH_KS8851_IRQ);
82 goto error3;
83 }
84
85 status = gpio_direction_output(ETH_KS8851_QUART, 1);
86 if (status) {
87 pr_err("Cannot set output GPIO %d\n", ETH_KS8851_QUART);
88 goto error3;
89 }
90
91 status = gpio_direction_input(ETH_KS8851_IRQ);
92 if (status) {
93 pr_err("Cannot set input GPIO %d\n", ETH_KS8851_IRQ);
94 goto error3;
95 }
96
97 return 0;
98
99error3:
100 gpio_free(ETH_KS8851_IRQ);
101error2:
102 gpio_free(ETH_KS8851_QUART);
103error1:
104 gpio_free(ETH_KS8851_POWER_ON);
105 return status;
106}
34 107
35static struct platform_device sdp4430_lcd_device = { 108static struct platform_device sdp4430_lcd_device = {
36 .name = "sdp4430_lcd", 109 .name = "sdp4430_lcd",
@@ -49,50 +122,6 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = {
49 { OMAP_TAG_LCD, &sdp4430_lcd_config }, 122 { OMAP_TAG_LCD, &sdp4430_lcd_config },
50}; 123};
51 124
52#ifdef CONFIG_CACHE_L2X0
53static int __init omap_l2_cache_init(void)
54{
55 extern void omap_smc1(u32 fn, u32 arg);
56 void __iomem *l2cache_base;
57
58 /* To avoid code running on other OMAPs in
59 * multi-omap builds
60 */
61 if (!cpu_is_omap44xx())
62 return -ENODEV;
63
64 /* Static mapping, never released */
65 l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
66 BUG_ON(!l2cache_base);
67
68 /* Enable PL310 L2 Cache controller */
69 omap_smc1(0x102, 0x1);
70
71 /* 32KB way size, 16-way associativity,
72 * parity disabled
73 */
74 l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff);
75
76 return 0;
77}
78early_initcall(omap_l2_cache_init);
79#endif
80
81static void __init gic_init_irq(void)
82{
83 void __iomem *base;
84
85 /* Static mapping, never released */
86 base = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
87 BUG_ON(!base);
88 gic_dist_init(0, base, 29);
89
90 /* Static mapping, never released */
91 gic_cpu_base_addr = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
92 BUG_ON(!gic_cpu_base_addr);
93 gic_cpu_init(0, gic_cpu_base_addr);
94}
95
96static void __init omap_4430sdp_init_irq(void) 125static void __init omap_4430sdp_init_irq(void)
97{ 126{
98 omap_board_config = sdp4430_config; 127 omap_board_config = sdp4430_config;
@@ -111,15 +140,254 @@ static struct omap_musb_board_data musb_board_data = {
111 .power = 100, 140 .power = 100,
112}; 141};
113 142
143static struct omap2_hsmmc_info mmc[] = {
144 {
145 .mmc = 1,
146 .wires = 8,
147 .gpio_wp = -EINVAL,
148 },
149 {
150 .mmc = 2,
151 .wires = 8,
152 .gpio_cd = -EINVAL,
153 .gpio_wp = -EINVAL,
154 .nonremovable = true,
155 },
156 {} /* Terminator */
157};
158
159static struct regulator_consumer_supply sdp4430_vmmc_supply[] = {
160 {
161 .supply = "vmmc",
162 .dev_name = "mmci-omap-hs.0",
163 },
164 {
165 .supply = "vmmc",
166 .dev_name = "mmci-omap-hs.1",
167 },
168};
169
170static int omap4_twl6030_hsmmc_late_init(struct device *dev)
171{
172 int ret = 0;
173 struct platform_device *pdev = container_of(dev,
174 struct platform_device, dev);
175 struct omap_mmc_platform_data *pdata = dev->platform_data;
176
177 /* Setting MMC1 Card detect Irq */
178 if (pdev->id == 0)
179 pdata->slots[0].card_detect_irq = TWL6030_IRQ_BASE +
180 MMCDETECT_INTR_OFFSET;
181 return ret;
182}
183
184static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
185{
186 struct omap_mmc_platform_data *pdata = dev->platform_data;
187
188 pdata->init = omap4_twl6030_hsmmc_late_init;
189}
190
191static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
192{
193 struct omap2_hsmmc_info *c;
194
195 omap2_hsmmc_init(controllers);
196 for (c = controllers; c->mmc; c++)
197 omap4_twl6030_hsmmc_set_late_init(c->dev);
198
199 return 0;
200}
201
202static struct regulator_init_data sdp4430_vaux1 = {
203 .constraints = {
204 .min_uV = 1000000,
205 .max_uV = 3000000,
206 .apply_uV = true,
207 .valid_modes_mask = REGULATOR_MODE_NORMAL
208 | REGULATOR_MODE_STANDBY,
209 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
210 | REGULATOR_CHANGE_MODE
211 | REGULATOR_CHANGE_STATUS,
212 },
213};
214
215static struct regulator_init_data sdp4430_vaux2 = {
216 .constraints = {
217 .min_uV = 1200000,
218 .max_uV = 2800000,
219 .apply_uV = true,
220 .valid_modes_mask = REGULATOR_MODE_NORMAL
221 | REGULATOR_MODE_STANDBY,
222 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
223 | REGULATOR_CHANGE_MODE
224 | REGULATOR_CHANGE_STATUS,
225 },
226};
227
228static struct regulator_init_data sdp4430_vaux3 = {
229 .constraints = {
230 .min_uV = 1000000,
231 .max_uV = 3000000,
232 .apply_uV = true,
233 .valid_modes_mask = REGULATOR_MODE_NORMAL
234 | REGULATOR_MODE_STANDBY,
235 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
236 | REGULATOR_CHANGE_MODE
237 | REGULATOR_CHANGE_STATUS,
238 },
239};
240
241/* VMMC1 for MMC1 card */
242static struct regulator_init_data sdp4430_vmmc = {
243 .constraints = {
244 .min_uV = 1200000,
245 .max_uV = 3000000,
246 .apply_uV = true,
247 .valid_modes_mask = REGULATOR_MODE_NORMAL
248 | REGULATOR_MODE_STANDBY,
249 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
250 | REGULATOR_CHANGE_MODE
251 | REGULATOR_CHANGE_STATUS,
252 },
253 .num_consumer_supplies = 2,
254 .consumer_supplies = sdp4430_vmmc_supply,
255};
256
257static struct regulator_init_data sdp4430_vpp = {
258 .constraints = {
259 .min_uV = 1800000,
260 .max_uV = 2500000,
261 .apply_uV = true,
262 .valid_modes_mask = REGULATOR_MODE_NORMAL
263 | REGULATOR_MODE_STANDBY,
264 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
265 | REGULATOR_CHANGE_MODE
266 | REGULATOR_CHANGE_STATUS,
267 },
268};
269
270static struct regulator_init_data sdp4430_vusim = {
271 .constraints = {
272 .min_uV = 1200000,
273 .max_uV = 2900000,
274 .apply_uV = true,
275 .valid_modes_mask = REGULATOR_MODE_NORMAL
276 | REGULATOR_MODE_STANDBY,
277 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
278 | REGULATOR_CHANGE_MODE
279 | REGULATOR_CHANGE_STATUS,
280 },
281};
282
283static struct regulator_init_data sdp4430_vana = {
284 .constraints = {
285 .min_uV = 2100000,
286 .max_uV = 2100000,
287 .apply_uV = true,
288 .valid_modes_mask = REGULATOR_MODE_NORMAL
289 | REGULATOR_MODE_STANDBY,
290 .valid_ops_mask = REGULATOR_CHANGE_MODE
291 | REGULATOR_CHANGE_STATUS,
292 },
293};
294
295static struct regulator_init_data sdp4430_vcxio = {
296 .constraints = {
297 .min_uV = 1800000,
298 .max_uV = 1800000,
299 .apply_uV = true,
300 .valid_modes_mask = REGULATOR_MODE_NORMAL
301 | REGULATOR_MODE_STANDBY,
302 .valid_ops_mask = REGULATOR_CHANGE_MODE
303 | REGULATOR_CHANGE_STATUS,
304 },
305};
306
307static struct regulator_init_data sdp4430_vdac = {
308 .constraints = {
309 .min_uV = 1800000,
310 .max_uV = 1800000,
311 .apply_uV = true,
312 .valid_modes_mask = REGULATOR_MODE_NORMAL
313 | REGULATOR_MODE_STANDBY,
314 .valid_ops_mask = REGULATOR_CHANGE_MODE
315 | REGULATOR_CHANGE_STATUS,
316 },
317};
318
319static struct regulator_init_data sdp4430_vusb = {
320 .constraints = {
321 .min_uV = 3300000,
322 .max_uV = 3300000,
323 .apply_uV = true,
324 .valid_modes_mask = REGULATOR_MODE_NORMAL
325 | REGULATOR_MODE_STANDBY,
326 .valid_ops_mask = REGULATOR_CHANGE_MODE
327 | REGULATOR_CHANGE_STATUS,
328 },
329};
330
331static struct twl4030_platform_data sdp4430_twldata = {
332 .irq_base = TWL6030_IRQ_BASE,
333 .irq_end = TWL6030_IRQ_END,
334
335 /* Regulators */
336 .vmmc = &sdp4430_vmmc,
337 .vpp = &sdp4430_vpp,
338 .vusim = &sdp4430_vusim,
339 .vana = &sdp4430_vana,
340 .vcxio = &sdp4430_vcxio,
341 .vdac = &sdp4430_vdac,
342 .vusb = &sdp4430_vusb,
343 .vaux1 = &sdp4430_vaux1,
344 .vaux2 = &sdp4430_vaux2,
345 .vaux3 = &sdp4430_vaux3,
346};
347
348static struct i2c_board_info __initdata sdp4430_i2c_boardinfo[] = {
349 {
350 I2C_BOARD_INFO("twl6030", 0x48),
351 .flags = I2C_CLIENT_WAKE,
352 .irq = OMAP44XX_IRQ_SYS_1N,
353 .platform_data = &sdp4430_twldata,
354 },
355};
356static int __init omap4_i2c_init(void)
357{
358 /*
359 * Phoenix Audio IC needs I2C1 to
360 * start with 400 KHz or less
361 */
362 omap_register_i2c_bus(1, 400, sdp4430_i2c_boardinfo,
363 ARRAY_SIZE(sdp4430_i2c_boardinfo));
364 omap_register_i2c_bus(2, 400, NULL, 0);
365 omap_register_i2c_bus(3, 400, NULL, 0);
366 omap_register_i2c_bus(4, 400, NULL, 0);
367 return 0;
368}
114static void __init omap_4430sdp_init(void) 369static void __init omap_4430sdp_init(void)
115{ 370{
371 int status;
372
373 omap4_i2c_init();
116 platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); 374 platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
117 omap_serial_init(); 375 omap_serial_init();
376 omap4_twl6030_hsmmc_init(mmc);
118 /* OMAP4 SDP uses internal transceiver so register nop transceiver */ 377 /* OMAP4 SDP uses internal transceiver so register nop transceiver */
119 usb_nop_xceiv_register(); 378 usb_nop_xceiv_register();
120 /* FIXME: allow multi-omap to boot until musb is updated for omap4 */ 379 /* FIXME: allow multi-omap to boot until musb is updated for omap4 */
121 if (!cpu_is_omap44xx()) 380 if (!cpu_is_omap44xx())
122 usb_musb_init(&musb_board_data); 381 usb_musb_init(&musb_board_data);
382
383 status = omap_ethernet_init();
384 if (status) {
385 pr_err("Ethernet initialization failed: %d\n", status);
386 } else {
387 sdp4430_spi_board_info[0].irq = gpio_to_irq(ETH_KS8851_IRQ);
388 spi_register_board_info(sdp4430_spi_board_info,
389 ARRAY_SIZE(sdp4430_spi_board_info));
390 }
123} 391}
124 392
125static void __init omap_4430sdp_map_io(void) 393static void __init omap_4430sdp_map_io(void)
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index c1c4389fbd8f..af383a876943 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -21,6 +21,8 @@
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/gpio.h> 22#include <linux/gpio.h>
23#include <linux/i2c/pca953x.h> 23#include <linux/i2c/pca953x.h>
24#include <linux/can/platform/ti_hecc.h>
25#include <linux/davinci_emac.h>
24 26
25#include <mach/hardware.h> 27#include <mach/hardware.h>
26#include <mach/am35xx.h> 28#include <mach/am35xx.h>
@@ -30,16 +32,111 @@
30 32
31#include <plat/board.h> 33#include <plat/board.h>
32#include <plat/common.h> 34#include <plat/common.h>
35#include <plat/control.h>
33#include <plat/usb.h> 36#include <plat/usb.h>
34#include <plat/display.h> 37#include <plat/display.h>
35 38
36#include "mux.h" 39#include "mux.h"
37 40
41#define AM35XX_EVM_PHY_MASK (0xF)
42#define AM35XX_EVM_MDIO_FREQUENCY (1000000)
43
44static struct emac_platform_data am3517_evm_emac_pdata = {
45 .phy_mask = AM35XX_EVM_PHY_MASK,
46 .mdio_max_freq = AM35XX_EVM_MDIO_FREQUENCY,
47 .rmii_en = 1,
48};
49
50static struct resource am3517_emac_resources[] = {
51 {
52 .start = AM35XX_IPSS_EMAC_BASE,
53 .end = AM35XX_IPSS_EMAC_BASE + 0x3FFFF,
54 .flags = IORESOURCE_MEM,
55 },
56 {
57 .start = INT_35XX_EMAC_C0_RXTHRESH_IRQ,
58 .end = INT_35XX_EMAC_C0_RXTHRESH_IRQ,
59 .flags = IORESOURCE_IRQ,
60 },
61 {
62 .start = INT_35XX_EMAC_C0_RX_PULSE_IRQ,
63 .end = INT_35XX_EMAC_C0_RX_PULSE_IRQ,
64 .flags = IORESOURCE_IRQ,
65 },
66 {
67 .start = INT_35XX_EMAC_C0_TX_PULSE_IRQ,
68 .end = INT_35XX_EMAC_C0_TX_PULSE_IRQ,
69 .flags = IORESOURCE_IRQ,
70 },
71 {
72 .start = INT_35XX_EMAC_C0_MISC_PULSE_IRQ,
73 .end = INT_35XX_EMAC_C0_MISC_PULSE_IRQ,
74 .flags = IORESOURCE_IRQ,
75 },
76};
77
78static struct platform_device am3517_emac_device = {
79 .name = "davinci_emac",
80 .id = -1,
81 .num_resources = ARRAY_SIZE(am3517_emac_resources),
82 .resource = am3517_emac_resources,
83};
84
85static void am3517_enable_ethernet_int(void)
86{
87 u32 regval;
88
89 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
90 regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
91 AM35XX_CPGMAC_C0_TX_PULSE_CLR |
92 AM35XX_CPGMAC_C0_MISC_PULSE_CLR |
93 AM35XX_CPGMAC_C0_RX_THRESH_CLR);
94 omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
95 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
96}
97
98static void am3517_disable_ethernet_int(void)
99{
100 u32 regval;
101
102 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
103 regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
104 AM35XX_CPGMAC_C0_TX_PULSE_CLR);
105 omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
106 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
107}
108
109void am3517_evm_ethernet_init(struct emac_platform_data *pdata)
110{
111 unsigned int regval;
112
113 pdata->ctrl_reg_offset = AM35XX_EMAC_CNTRL_OFFSET;
114 pdata->ctrl_mod_reg_offset = AM35XX_EMAC_CNTRL_MOD_OFFSET;
115 pdata->ctrl_ram_offset = AM35XX_EMAC_CNTRL_RAM_OFFSET;
116 pdata->mdio_reg_offset = AM35XX_EMAC_MDIO_OFFSET;
117 pdata->ctrl_ram_size = AM35XX_EMAC_CNTRL_RAM_SIZE;
118 pdata->version = EMAC_VERSION_2;
119 pdata->hw_ram_addr = AM35XX_EMAC_HW_RAM_ADDR;
120 pdata->interrupt_enable = am3517_enable_ethernet_int;
121 pdata->interrupt_disable = am3517_disable_ethernet_int;
122 am3517_emac_device.dev.platform_data = pdata;
123 platform_device_register(&am3517_emac_device);
124
125 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
126 regval = regval & (~(AM35XX_CPGMACSS_SW_RST));
127 omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
128 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
129
130 return ;
131}
132
133
134
38#define LCD_PANEL_PWR 176 135#define LCD_PANEL_PWR 176
39#define LCD_PANEL_BKLIGHT_PWR 182 136#define LCD_PANEL_BKLIGHT_PWR 182
40#define LCD_PANEL_PWM 181 137#define LCD_PANEL_PWM 181
41 138
42static struct i2c_board_info __initdata am3517evm_i2c_boardinfo[] = { 139static struct i2c_board_info __initdata am3517evm_i2c1_boardinfo[] = {
43 { 140 {
44 I2C_BOARD_INFO("s35390a", 0x30), 141 I2C_BOARD_INFO("s35390a", 0x30),
45 .type = "s35390a", 142 .type = "s35390a",
@@ -69,7 +166,7 @@ static void __init am3517_evm_rtc_init(void)
69 gpio_free(GPIO_RTCS35390A_IRQ); 166 gpio_free(GPIO_RTCS35390A_IRQ);
70 return; 167 return;
71 } 168 }
72 am3517evm_i2c_boardinfo[0].irq = gpio_to_irq(GPIO_RTCS35390A_IRQ); 169 am3517evm_i2c1_boardinfo[0].irq = gpio_to_irq(GPIO_RTCS35390A_IRQ);
73} 170}
74 171
75/* 172/*
@@ -80,7 +177,7 @@ static void __init am3517_evm_rtc_init(void)
80static struct pca953x_platform_data am3517evm_gpio_expander_info_0 = { 177static struct pca953x_platform_data am3517evm_gpio_expander_info_0 = {
81 .gpio_base = OMAP_MAX_GPIO_LINES, 178 .gpio_base = OMAP_MAX_GPIO_LINES,
82}; 179};
83static struct i2c_board_info __initdata am3517evm_tca6416_info_0[] = { 180static struct i2c_board_info __initdata am3517evm_i2c2_boardinfo[] = {
84 { 181 {
85 I2C_BOARD_INFO("tca6416", 0x21), 182 I2C_BOARD_INFO("tca6416", 0x21),
86 .platform_data = &am3517evm_gpio_expander_info_0, 183 .platform_data = &am3517evm_gpio_expander_info_0,
@@ -94,7 +191,7 @@ static struct pca953x_platform_data am3517evm_ui_gpio_expander_info_1 = {
94static struct pca953x_platform_data am3517evm_ui_gpio_expander_info_2 = { 191static struct pca953x_platform_data am3517evm_ui_gpio_expander_info_2 = {
95 .gpio_base = OMAP_MAX_GPIO_LINES + 32, 192 .gpio_base = OMAP_MAX_GPIO_LINES + 32,
96}; 193};
97static struct i2c_board_info __initdata am3517evm_ui_tca6416_info[] = { 194static struct i2c_board_info __initdata am3517evm_i2c3_boardinfo[] = {
98 { 195 {
99 I2C_BOARD_INFO("tca6416", 0x20), 196 I2C_BOARD_INFO("tca6416", 0x20),
100 .platform_data = &am3517evm_ui_gpio_expander_info_1, 197 .platform_data = &am3517evm_ui_gpio_expander_info_1,
@@ -108,10 +205,10 @@ static struct i2c_board_info __initdata am3517evm_ui_tca6416_info[] = {
108static int __init am3517_evm_i2c_init(void) 205static int __init am3517_evm_i2c_init(void)
109{ 206{
110 omap_register_i2c_bus(1, 400, NULL, 0); 207 omap_register_i2c_bus(1, 400, NULL, 0);
111 omap_register_i2c_bus(2, 400, am3517evm_tca6416_info_0, 208 omap_register_i2c_bus(2, 400, am3517evm_i2c2_boardinfo,
112 ARRAY_SIZE(am3517evm_tca6416_info_0)); 209 ARRAY_SIZE(am3517evm_i2c2_boardinfo));
113 omap_register_i2c_bus(3, 400, am3517evm_ui_tca6416_info, 210 omap_register_i2c_bus(3, 400, am3517evm_i2c3_boardinfo,
114 ARRAY_SIZE(am3517evm_ui_tca6416_info)); 211 ARRAY_SIZE(am3517evm_i2c3_boardinfo));
115 212
116 return 0; 213 return 0;
117} 214}
@@ -119,6 +216,8 @@ static int __init am3517_evm_i2c_init(void)
119static int lcd_enabled; 216static int lcd_enabled;
120static int dvi_enabled; 217static int dvi_enabled;
121 218
219#if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
220 defined(CONFIG_PANEL_SHARP_LQ043T1DG01_MODULE)
122static void __init am3517_evm_display_init(void) 221static void __init am3517_evm_display_init(void)
123{ 222{
124 int r; 223 int r;
@@ -162,6 +261,9 @@ err_2:
162err_1: 261err_1:
163 gpio_free(LCD_PANEL_BKLIGHT_PWR); 262 gpio_free(LCD_PANEL_BKLIGHT_PWR);
164} 263}
264#else
265static void __init am3517_evm_display_init(void) {}
266#endif
165 267
166static int am3517_evm_panel_enable_lcd(struct omap_dss_device *dssdev) 268static int am3517_evm_panel_enable_lcd(struct omap_dss_device *dssdev)
167{ 269{
@@ -275,7 +377,12 @@ static void __init am3517_evm_init_irq(void)
275 377
276static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { 378static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
277 .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, 379 .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
380#if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
381 defined(CONFIG_PANEL_SHARP_LQ043T1DG01_MODULE)
382 .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
383#else
278 .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, 384 .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
385#endif
279 .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, 386 .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
280 387
281 .phy_reset = true, 388 .phy_reset = true,
@@ -292,6 +399,42 @@ static struct omap_board_mux board_mux[] __initdata = {
292#define board_mux NULL 399#define board_mux NULL
293#endif 400#endif
294 401
402
403static struct resource am3517_hecc_resources[] = {
404 {
405 .start = AM35XX_IPSS_HECC_BASE,
406 .end = AM35XX_IPSS_HECC_BASE + 0x3FFF,
407 .flags = IORESOURCE_MEM,
408 },
409 {
410 .start = INT_35XX_HECC0_IRQ,
411 .end = INT_35XX_HECC0_IRQ,
412 .flags = IORESOURCE_IRQ,
413 },
414};
415
416static struct platform_device am3517_hecc_device = {
417 .name = "ti_hecc",
418 .id = -1,
419 .num_resources = ARRAY_SIZE(am3517_hecc_resources),
420 .resource = am3517_hecc_resources,
421};
422
423static struct ti_hecc_platform_data am3517_evm_hecc_pdata = {
424 .scc_hecc_offset = AM35XX_HECC_SCC_HECC_OFFSET,
425 .scc_ram_offset = AM35XX_HECC_SCC_RAM_OFFSET,
426 .hecc_ram_offset = AM35XX_HECC_RAM_OFFSET,
427 .mbx_offset = AM35XX_HECC_MBOX_OFFSET,
428 .int_line = AM35XX_HECC_INT_LINE,
429 .version = AM35XX_HECC_VERSION,
430};
431
432static void am3517_evm_hecc_init(struct ti_hecc_platform_data *pdata)
433{
434 am3517_hecc_device.dev.platform_data = pdata;
435 platform_device_register(&am3517_hecc_device);
436}
437
295static void __init am3517_evm_init(void) 438static void __init am3517_evm_init(void)
296{ 439{
297 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 440 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
@@ -305,14 +448,17 @@ static void __init am3517_evm_init(void)
305 /* Configure GPIO for EHCI port */ 448 /* Configure GPIO for EHCI port */
306 omap_mux_init_gpio(57, OMAP_PIN_OUTPUT); 449 omap_mux_init_gpio(57, OMAP_PIN_OUTPUT);
307 usb_ehci_init(&ehci_pdata); 450 usb_ehci_init(&ehci_pdata);
451 am3517_evm_hecc_init(&am3517_evm_hecc_pdata);
308 /* DSS */ 452 /* DSS */
309 am3517_evm_display_init(); 453 am3517_evm_display_init();
310 454
311 /* RTC - S35390A */ 455 /* RTC - S35390A */
312 am3517_evm_rtc_init(); 456 am3517_evm_rtc_init();
313 457
314 i2c_register_board_info(1, am3517evm_i2c_boardinfo, 458 i2c_register_board_info(1, am3517evm_i2c1_boardinfo,
315 ARRAY_SIZE(am3517evm_i2c_boardinfo)); 459 ARRAY_SIZE(am3517evm_i2c1_boardinfo));
460 /*Ethernet*/
461 am3517_evm_ethernet_init(&am3517_evm_emac_pdata);
316} 462}
317 463
318static void __init am3517_evm_map_io(void) 464static void __init am3517_evm_map_io(void)
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 2de4f79f03a0..e679a2cc86c3 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -45,6 +45,7 @@
45#include <plat/gpmc.h> 45#include <plat/gpmc.h>
46#include <plat/usb.h> 46#include <plat/usb.h>
47#include <plat/display.h> 47#include <plat/display.h>
48#include <plat/mcspi.h>
48 49
49#include <mach/hardware.h> 50#include <mach/hardware.h>
50 51
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 47e3af2166d4..77022b588816 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -633,8 +633,163 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
633 .reset_gpio_port[2] = -EINVAL 633 .reset_gpio_port[2] = -EINVAL
634}; 634};
635 635
636static struct omap_board_mux board_mux[] __initdata = {
637 /* nCS and IRQ for Devkit8000 ethernet */
638 OMAP3_MUX(GPMC_NCS6, OMAP_MUX_MODE0),
639 OMAP3_MUX(ETK_D11, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
640
641 /* McSPI 2*/
642 OMAP3_MUX(MCSPI2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
643 OMAP3_MUX(MCSPI2_SIMO, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
644 OMAP3_MUX(MCSPI2_SOMI, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
645 OMAP3_MUX(MCSPI2_CS0, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
646 OMAP3_MUX(MCSPI2_CS1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
647
648 /* PENDOWN GPIO */
649 OMAP3_MUX(ETK_D13, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
650
651 /* mUSB */
652 OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
653 OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
654 OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
655 OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
656 OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
657 OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
658 OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
659 OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
660 OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
661 OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
662 OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
663 OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
664
665 /* USB 1 */
666 OMAP3_MUX(ETK_CTL, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
667 OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
668 OMAP3_MUX(ETK_D8, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
669 OMAP3_MUX(ETK_D9, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
670 OMAP3_MUX(ETK_D0, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
671 OMAP3_MUX(ETK_D1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
672 OMAP3_MUX(ETK_D2, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
673 OMAP3_MUX(ETK_D3, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
674 OMAP3_MUX(ETK_D4, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
675 OMAP3_MUX(ETK_D5, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
676 OMAP3_MUX(ETK_D6, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
677 OMAP3_MUX(ETK_D7, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
678
679 /* MMC 1 */
680 OMAP3_MUX(SDMMC1_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
681 OMAP3_MUX(SDMMC1_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
682 OMAP3_MUX(SDMMC1_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
683 OMAP3_MUX(SDMMC1_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
684 OMAP3_MUX(SDMMC1_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
685 OMAP3_MUX(SDMMC1_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
686 OMAP3_MUX(SDMMC1_DAT4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
687 OMAP3_MUX(SDMMC1_DAT5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
688 OMAP3_MUX(SDMMC1_DAT6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
689 OMAP3_MUX(SDMMC1_DAT7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
690
691 /* McBSP 2 */
692 OMAP3_MUX(MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
693 OMAP3_MUX(MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
694 OMAP3_MUX(MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
695 OMAP3_MUX(MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
696
697 /* I2C 1 */
698 OMAP3_MUX(I2C1_SCL, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
699 OMAP3_MUX(I2C1_SDA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
700
701 /* I2C 2 */
702 OMAP3_MUX(I2C2_SCL, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
703 OMAP3_MUX(I2C2_SDA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
704
705 /* I2C 3 */
706 OMAP3_MUX(I2C3_SCL, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
707 OMAP3_MUX(I2C3_SDA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
708
709 /* I2C 4 */
710 OMAP3_MUX(I2C4_SCL, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
711 OMAP3_MUX(I2C4_SDA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
712
713 /* serial ports */
714 OMAP3_MUX(MCBSP3_CLKX, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
715 OMAP3_MUX(MCBSP3_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
716 OMAP3_MUX(UART1_TX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
717 OMAP3_MUX(UART1_RX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
718
719 /* DSS */
720 OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
721 OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
722 OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
723 OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
724 OMAP3_MUX(DSS_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
725 OMAP3_MUX(DSS_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
726 OMAP3_MUX(DSS_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
727 OMAP3_MUX(DSS_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
728 OMAP3_MUX(DSS_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
729 OMAP3_MUX(DSS_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
730 OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
731 OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
732 OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
733 OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
734 OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
735 OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
736 OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
737 OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
738 OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
739 OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
740 OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
741 OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
742 OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
743 OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
744 OMAP3_MUX(DSS_DATA20, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
745 OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
746 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
747 OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
748
749 /* expansion port */
750 /* McSPI 1 */
751 OMAP3_MUX(MCSPI1_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
752 OMAP3_MUX(MCSPI1_SIMO, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
753 OMAP3_MUX(MCSPI1_SOMI, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
754 OMAP3_MUX(MCSPI1_CS0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
755 OMAP3_MUX(MCSPI1_CS3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
756
757 /* HDQ */
758 OMAP3_MUX(HDQ_SIO, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
759
760 /* McSPI4 */
761 OMAP3_MUX(MCBSP1_CLKR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
762 OMAP3_MUX(MCBSP1_DX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
763 OMAP3_MUX(MCBSP1_DR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
764 OMAP3_MUX(MCBSP1_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT_PULLUP),
765
766 /* MMC 2 */
767 OMAP3_MUX(SDMMC2_DAT4, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
768 OMAP3_MUX(SDMMC2_DAT5, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
769 OMAP3_MUX(SDMMC2_DAT6, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
770 OMAP3_MUX(SDMMC2_DAT7, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
771
772 /* I2C3 */
773 OMAP3_MUX(I2C3_SCL, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
774 OMAP3_MUX(I2C3_SDA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
775
776 OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
777 OMAP3_MUX(MCBSP_CLKS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
778 OMAP3_MUX(MCBSP1_FSR, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
779
780 OMAP3_MUX(GPMC_NCS7, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
781 OMAP3_MUX(GPMC_NCS3, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
782
783 /* TPS IRQ */
784 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_WAKEUP_EN | \
785 OMAP_PIN_INPUT_PULLUP),
786
787 { .reg_offset = OMAP_MUX_TERMINATOR },
788};
789
636static void __init devkit8000_init(void) 790static void __init devkit8000_init(void)
637{ 791{
792 omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
638 omap_serial_init(); 793 omap_serial_init();
639 794
640 omap_dm9000_init(); 795 omap_dm9000_init();
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 7d7b5bc8dc31..81bba194b030 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -600,6 +600,7 @@ struct ads7846_platform_data ads7846_config = {
600 .get_pendown_state = ads7846_get_pendown_state, 600 .get_pendown_state = ads7846_get_pendown_state,
601 .keep_vref_on = 1, 601 .keep_vref_on = 1,
602 .settle_delay_usecs = 150, 602 .settle_delay_usecs = 150,
603 .wakeup = true,
603}; 604};
604 605
605static struct omap2_mcspi_device_config ads7846_mcspi_config = { 606static struct omap2_mcspi_device_config ads7846_mcspi_config = {
@@ -651,11 +652,10 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
651#ifdef CONFIG_OMAP_MUX 652#ifdef CONFIG_OMAP_MUX
652static struct omap_board_mux board_mux[] __initdata = { 653static struct omap_board_mux board_mux[] __initdata = {
653 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP | 654 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
654 OMAP_PIN_OFF_INPUT_PULLUP | 655 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
655 OMAP_PIN_OFF_WAKEUPENABLE), 656 OMAP_PIN_OFF_WAKEUPENABLE),
656 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | 657 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
657 OMAP_PIN_OFF_INPUT_PULLUP | 658 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW),
658 OMAP_PIN_OFF_WAKEUPENABLE),
659 { .reg_offset = OMAP_MUX_TERMINATOR }, 659 { .reg_offset = OMAP_MUX_TERMINATOR },
660}; 660};
661#else 661#else
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
new file mode 100644
index 000000000000..f848ba8dbc16
--- /dev/null
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -0,0 +1,672 @@
1/*
2 * linux/arch/arm/mach-omap2/board-omap3evm.c
3 *
4 * Copyright (C) 2008 Guangzhou EMA-Tech
5 *
6 * Modified from mach-omap2/board-omap3evm.c
7 *
8 * Initial code: Syed Mohammed Khasim
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/leds.h>
23#include <linux/gpio.h>
24#include <linux/input.h>
25#include <linux/gpio_keys.h>
26
27#include <linux/regulator/machine.h>
28#include <linux/i2c/twl.h>
29
30#include <mach/hardware.h>
31#include <asm/mach-types.h>
32#include <asm/mach/arch.h>
33#include <asm/mach/map.h>
34#include <asm/mach/flash.h>
35
36#include <plat/board.h>
37#include <plat/common.h>
38#include <plat/gpmc.h>
39#include <plat/nand.h>
40#include <plat/usb.h>
41#include <plat/timer-gp.h>
42#include <plat/display.h>
43
44#include <plat/mcspi.h>
45#include <linux/input/matrix_keypad.h>
46#include <linux/spi/spi.h>
47#include <linux/spi/ads7846.h>
48#include <linux/interrupt.h>
49#include <linux/smsc911x.h>
50#include <linux/i2c/at24.h>
51
52#include "sdram-micron-mt46h32m32lf-6.h"
53#include "mux.h"
54#include "hsmmc.h"
55
56#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
57#define OMAP3STALKER_ETHR_START 0x2c000000
58#define OMAP3STALKER_ETHR_SIZE 1024
59#define OMAP3STALKER_ETHR_GPIO_IRQ 19
60#define OMAP3STALKER_SMC911X_CS 5
61
62static struct resource omap3stalker_smsc911x_resources[] = {
63 [0] = {
64 .start = OMAP3STALKER_ETHR_START,
65 .end =
66 (OMAP3STALKER_ETHR_START + OMAP3STALKER_ETHR_SIZE - 1),
67 .flags = IORESOURCE_MEM,
68 },
69 [1] = {
70 .start = OMAP_GPIO_IRQ(OMAP3STALKER_ETHR_GPIO_IRQ),
71 .end = OMAP_GPIO_IRQ(OMAP3STALKER_ETHR_GPIO_IRQ),
72 .flags = (IORESOURCE_IRQ | IRQF_TRIGGER_LOW),
73 },
74};
75
76static struct smsc911x_platform_config smsc911x_config = {
77 .phy_interface = PHY_INTERFACE_MODE_MII,
78 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
79 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
80 .flags = (SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS),
81};
82
83static struct platform_device omap3stalker_smsc911x_device = {
84 .name = "smsc911x",
85 .id = -1,
86 .num_resources = ARRAY_SIZE(omap3stalker_smsc911x_resources),
87 .resource = &omap3stalker_smsc911x_resources[0],
88 .dev = {
89 .platform_data = &smsc911x_config,
90 },
91};
92
93static inline void __init omap3stalker_init_eth(void)
94{
95 int eth_cs;
96 struct clk *l3ck;
97 unsigned int rate;
98
99 eth_cs = OMAP3STALKER_SMC911X_CS;
100
101 l3ck = clk_get(NULL, "l3_ck");
102 if (IS_ERR(l3ck))
103 rate = 100000000;
104 else
105 rate = clk_get_rate(l3ck);
106
107 omap_mux_init_gpio(19, OMAP_PIN_INPUT_PULLUP);
108 if (gpio_request(OMAP3STALKER_ETHR_GPIO_IRQ, "SMC911x irq") < 0) {
109 printk(KERN_ERR
110 "Failed to request GPIO%d for smc911x IRQ\n",
111 OMAP3STALKER_ETHR_GPIO_IRQ);
112 return;
113 }
114
115 gpio_direction_input(OMAP3STALKER_ETHR_GPIO_IRQ);
116
117 platform_device_register(&omap3stalker_smsc911x_device);
118}
119
120#else
121static inline void __init omap3stalker_init_eth(void)
122{
123 return;
124}
125#endif
126
127/*
128 * OMAP3 DSS control signals
129 */
130
131#define DSS_ENABLE_GPIO 199
132#define LCD_PANEL_BKLIGHT_GPIO 210
133#define ENABLE_VPLL2_DEV_GRP 0xE0
134
135static int lcd_enabled;
136static int dvi_enabled;
137
138static void __init omap3_stalker_display_init(void)
139{
140 return;
141}
142
143static int omap3_stalker_enable_lcd(struct omap_dss_device *dssdev)
144{
145 if (dvi_enabled) {
146 printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
147 return -EINVAL;
148 }
149 gpio_set_value(DSS_ENABLE_GPIO, 1);
150 gpio_set_value(LCD_PANEL_BKLIGHT_GPIO, 1);
151 lcd_enabled = 1;
152 return 0;
153}
154
155static void omap3_stalker_disable_lcd(struct omap_dss_device *dssdev)
156{
157 gpio_set_value(DSS_ENABLE_GPIO, 0);
158 gpio_set_value(LCD_PANEL_BKLIGHT_GPIO, 0);
159 lcd_enabled = 0;
160}
161
162static struct omap_dss_device omap3_stalker_lcd_device = {
163 .name = "lcd",
164 .driver_name = "generic_panel",
165 .phy.dpi.data_lines = 24,
166 .type = OMAP_DISPLAY_TYPE_DPI,
167 .platform_enable = omap3_stalker_enable_lcd,
168 .platform_disable = omap3_stalker_disable_lcd,
169};
170
171static int omap3_stalker_enable_tv(struct omap_dss_device *dssdev)
172{
173 return 0;
174}
175
176static void omap3_stalker_disable_tv(struct omap_dss_device *dssdev)
177{
178}
179
180static struct omap_dss_device omap3_stalker_tv_device = {
181 .name = "tv",
182 .driver_name = "venc",
183 .type = OMAP_DISPLAY_TYPE_VENC,
184#if defined(CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO)
185 .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
186#elif defined(CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE)
187 .u.venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE,
188#endif
189 .platform_enable = omap3_stalker_enable_tv,
190 .platform_disable = omap3_stalker_disable_tv,
191};
192
193static int omap3_stalker_enable_dvi(struct omap_dss_device *dssdev)
194{
195 if (lcd_enabled) {
196 printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
197 return -EINVAL;
198 }
199 gpio_set_value(DSS_ENABLE_GPIO, 1);
200 dvi_enabled = 1;
201 return 0;
202}
203
204static void omap3_stalker_disable_dvi(struct omap_dss_device *dssdev)
205{
206 gpio_set_value(DSS_ENABLE_GPIO, 0);
207 dvi_enabled = 0;
208}
209
210static struct omap_dss_device omap3_stalker_dvi_device = {
211 .name = "dvi",
212 .driver_name = "generic_panel",
213 .type = OMAP_DISPLAY_TYPE_DPI,
214 .phy.dpi.data_lines = 24,
215 .platform_enable = omap3_stalker_enable_dvi,
216 .platform_disable = omap3_stalker_disable_dvi,
217};
218
219static struct omap_dss_device *omap3_stalker_dss_devices[] = {
220 &omap3_stalker_lcd_device,
221 &omap3_stalker_tv_device,
222 &omap3_stalker_dvi_device,
223};
224
225static struct omap_dss_board_info omap3_stalker_dss_data = {
226 .num_devices = ARRAY_SIZE(omap3_stalker_dss_devices),
227 .devices = omap3_stalker_dss_devices,
228 .default_device = &omap3_stalker_dvi_device,
229};
230
231static struct platform_device omap3_stalker_dss_device = {
232 .name = "omapdss",
233 .id = -1,
234 .dev = {
235 .platform_data = &omap3_stalker_dss_data,
236 },
237};
238
239static struct regulator_consumer_supply omap3stalker_vmmc1_supply = {
240 .supply = "vmmc",
241};
242
243static struct regulator_consumer_supply omap3stalker_vsim_supply = {
244 .supply = "vmmc_aux",
245};
246
247/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
248static struct regulator_init_data omap3stalker_vmmc1 = {
249 .constraints = {
250 .min_uV = 1850000,
251 .max_uV = 3150000,
252 .valid_modes_mask = REGULATOR_MODE_NORMAL
253 | REGULATOR_MODE_STANDBY,
254 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
255 | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
256 },
257 .num_consumer_supplies = 1,
258 .consumer_supplies = &omap3stalker_vmmc1_supply,
259};
260
261/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
262static struct regulator_init_data omap3stalker_vsim = {
263 .constraints = {
264 .min_uV = 1800000,
265 .max_uV = 3000000,
266 .valid_modes_mask = REGULATOR_MODE_NORMAL
267 | REGULATOR_MODE_STANDBY,
268 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
269 | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
270 },
271 .num_consumer_supplies = 1,
272 .consumer_supplies = &omap3stalker_vsim_supply,
273};
274
275static struct omap2_hsmmc_info mmc[] = {
276 {
277 .mmc = 1,
278 .wires = 4,
279 .gpio_cd = -EINVAL,
280 .gpio_wp = 23,
281 },
282 {} /* Terminator */
283};
284
285static struct gpio_keys_button gpio_buttons[] = {
286 {
287 .code = BTN_EXTRA,
288 .gpio = 18,
289 .desc = "user",
290 .wakeup = 1,
291 },
292};
293
294static struct gpio_keys_platform_data gpio_key_info = {
295 .buttons = gpio_buttons,
296 .nbuttons = ARRAY_SIZE(gpio_buttons),
297};
298
299static struct platform_device keys_gpio = {
300 .name = "gpio-keys",
301 .id = -1,
302 .dev = {
303 .platform_data = &gpio_key_info,
304 },
305};
306
307static struct gpio_led gpio_leds[] = {
308 {
309 .name = "stalker:D8:usr0",
310 .default_trigger = "default-on",
311 .gpio = 126,
312 },
313 {
314 .name = "stalker:D9:usr1",
315 .default_trigger = "default-on",
316 .gpio = 127,
317 },
318 {
319 .name = "stalker:D3:mmc0",
320 .gpio = -EINVAL, /* gets replaced */
321 .active_low = true,
322 .default_trigger = "mmc0",
323 },
324 {
325 .name = "stalker:D4:heartbeat",
326 .gpio = -EINVAL, /* gets replaced */
327 .active_low = true,
328 .default_trigger = "heartbeat",
329 },
330};
331
332static struct gpio_led_platform_data gpio_led_info = {
333 .leds = gpio_leds,
334 .num_leds = ARRAY_SIZE(gpio_leds),
335};
336
337static struct platform_device leds_gpio = {
338 .name = "leds-gpio",
339 .id = -1,
340 .dev = {
341 .platform_data = &gpio_led_info,
342 },
343};
344
345static int
346omap3stalker_twl_gpio_setup(struct device *dev,
347 unsigned gpio, unsigned ngpio)
348{
349 /* gpio + 0 is "mmc0_cd" (input/IRQ) */
350 omap_mux_init_gpio(23, OMAP_PIN_INPUT);
351 mmc[0].gpio_cd = gpio + 0;
352 omap2_hsmmc_init(mmc);
353
354 /* link regulators to MMC adapters */
355 omap3stalker_vmmc1_supply.dev = mmc[0].dev;
356 omap3stalker_vsim_supply.dev = mmc[0].dev;
357
358 /*
359 * Most GPIOs are for USB OTG. Some are mostly sent to
360 * the P2 connector; notably LEDA for the LCD backlight.
361 */
362
363 /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */
364 gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL");
365 gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0);
366
367 /* gpio + 7 == DVI Enable */
368 gpio_request(gpio + 7, "EN_DVI");
369 gpio_direction_output(gpio + 7, 0);
370
371 /* TWL4030_GPIO_MAX + 1 == ledB (out, mmc0) */
372 gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
373 /* GPIO + 13 == ledsync (out, heartbeat) */
374 gpio_leds[3].gpio = gpio + 13;
375
376 platform_device_register(&leds_gpio);
377 return 0;
378}
379
380static struct twl4030_gpio_platform_data omap3stalker_gpio_data = {
381 .gpio_base = OMAP_MAX_GPIO_LINES,
382 .irq_base = TWL4030_GPIO_IRQ_BASE,
383 .irq_end = TWL4030_GPIO_IRQ_END,
384 .use_leds = true,
385 .setup = omap3stalker_twl_gpio_setup,
386};
387
388static struct twl4030_usb_data omap3stalker_usb_data = {
389 .usb_mode = T2_USB_MODE_ULPI,
390};
391
392static int board_keymap[] = {
393 KEY(0, 0, KEY_LEFT),
394 KEY(0, 1, KEY_DOWN),
395 KEY(0, 2, KEY_ENTER),
396 KEY(0, 3, KEY_M),
397
398 KEY(1, 0, KEY_RIGHT),
399 KEY(1, 1, KEY_UP),
400 KEY(1, 2, KEY_I),
401 KEY(1, 3, KEY_N),
402
403 KEY(2, 0, KEY_A),
404 KEY(2, 1, KEY_E),
405 KEY(2, 2, KEY_J),
406 KEY(2, 3, KEY_O),
407
408 KEY(3, 0, KEY_B),
409 KEY(3, 1, KEY_F),
410 KEY(3, 2, KEY_K),
411 KEY(3, 3, KEY_P)
412};
413
414static struct matrix_keymap_data board_map_data = {
415 .keymap = board_keymap,
416 .keymap_size = ARRAY_SIZE(board_keymap),
417};
418
419static struct twl4030_keypad_data omap3stalker_kp_data = {
420 .keymap_data = &board_map_data,
421 .rows = 4,
422 .cols = 4,
423 .rep = 1,
424};
425
426static struct twl4030_madc_platform_data omap3stalker_madc_data = {
427 .irq_line = 1,
428};
429
430static struct twl4030_codec_audio_data omap3stalker_audio_data = {
431 .audio_mclk = 26000000,
432};
433
434static struct twl4030_codec_data omap3stalker_codec_data = {
435 .audio_mclk = 26000000,
436 .audio = &omap3stalker_audio_data,
437};
438
439static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply = {
440 .supply = "vdda_dac",
441 .dev = &omap3_stalker_dss_device.dev,
442};
443
444/* VDAC for DSS driving S-Video */
445static struct regulator_init_data omap3_stalker_vdac = {
446 .constraints = {
447 .min_uV = 1800000,
448 .max_uV = 1800000,
449 .apply_uV = true,
450 .valid_modes_mask = REGULATOR_MODE_NORMAL
451 | REGULATOR_MODE_STANDBY,
452 .valid_ops_mask = REGULATOR_CHANGE_MODE
453 | REGULATOR_CHANGE_STATUS,
454 },
455 .num_consumer_supplies = 1,
456 .consumer_supplies = &omap3_stalker_vdda_dac_supply,
457};
458
459/* VPLL2 for digital video outputs */
460static struct regulator_consumer_supply omap3_stalker_vpll2_supply = {
461 .supply = "vdds_dsi",
462 .dev = &omap3_stalker_lcd_device.dev,
463};
464
465static struct regulator_init_data omap3_stalker_vpll2 = {
466 .constraints = {
467 .name = "VDVI",
468 .min_uV = 1800000,
469 .max_uV = 1800000,
470 .apply_uV = true,
471 .valid_modes_mask = REGULATOR_MODE_NORMAL
472 | REGULATOR_MODE_STANDBY,
473 .valid_ops_mask = REGULATOR_CHANGE_MODE
474 | REGULATOR_CHANGE_STATUS,
475 },
476 .num_consumer_supplies = 1,
477 .consumer_supplies = &omap3_stalker_vpll2_supply,
478};
479
480static struct twl4030_platform_data omap3stalker_twldata = {
481 .irq_base = TWL4030_IRQ_BASE,
482 .irq_end = TWL4030_IRQ_END,
483
484 /* platform_data for children goes here */
485 .keypad = &omap3stalker_kp_data,
486 .madc = &omap3stalker_madc_data,
487 .usb = &omap3stalker_usb_data,
488 .gpio = &omap3stalker_gpio_data,
489 .codec = &omap3stalker_codec_data,
490 .vdac = &omap3_stalker_vdac,
491 .vpll2 = &omap3_stalker_vpll2,
492};
493
494static struct i2c_board_info __initdata omap3stalker_i2c_boardinfo[] = {
495 {
496 I2C_BOARD_INFO("twl4030", 0x48),
497 .flags = I2C_CLIENT_WAKE,
498 .irq = INT_34XX_SYS_NIRQ,
499 .platform_data = &omap3stalker_twldata,
500 },
501};
502
503static struct at24_platform_data fram_info = {
504 .byte_len = (64 * 1024) / 8,
505 .page_size = 8192,
506 .flags = AT24_FLAG_ADDR16 | AT24_FLAG_IRUGO,
507};
508
509static struct i2c_board_info __initdata omap3stalker_i2c_boardinfo3[] = {
510 {
511 I2C_BOARD_INFO("24c64", 0x50),
512 .flags = I2C_CLIENT_WAKE,
513 .platform_data = &fram_info,
514 },
515};
516
517static int __init omap3_stalker_i2c_init(void)
518{
519 /*
520 * REVISIT: These entries can be set in omap3evm_twl_data
521 * after a merge with MFD tree
522 */
523 omap3stalker_twldata.vmmc1 = &omap3stalker_vmmc1;
524 omap3stalker_twldata.vsim = &omap3stalker_vsim;
525
526 omap_register_i2c_bus(1, 2600, omap3stalker_i2c_boardinfo,
527 ARRAY_SIZE(omap3stalker_i2c_boardinfo));
528 omap_register_i2c_bus(2, 400, NULL, 0);
529 omap_register_i2c_bus(3, 400, omap3stalker_i2c_boardinfo3,
530 ARRAY_SIZE(omap3stalker_i2c_boardinfo3));
531 return 0;
532}
533
534#define OMAP3_STALKER_TS_GPIO 175
535static void ads7846_dev_init(void)
536{
537 if (gpio_request(OMAP3_STALKER_TS_GPIO, "ADS7846 pendown") < 0)
538 printk(KERN_ERR "can't get ads7846 pen down GPIO\n");
539
540 gpio_direction_input(OMAP3_STALKER_TS_GPIO);
541
542 omap_set_gpio_debounce(OMAP3_STALKER_TS_GPIO, 1);
543 omap_set_gpio_debounce_time(OMAP3_STALKER_TS_GPIO, 0xa);
544}
545
546static int ads7846_get_pendown_state(void)
547{
548 return !gpio_get_value(OMAP3_STALKER_TS_GPIO);
549}
550
551static struct ads7846_platform_data ads7846_config = {
552 .x_max = 0x0fff,
553 .y_max = 0x0fff,
554 .x_plate_ohms = 180,
555 .pressure_max = 255,
556 .debounce_max = 10,
557 .debounce_tol = 3,
558 .debounce_rep = 1,
559 .get_pendown_state = ads7846_get_pendown_state,
560 .keep_vref_on = 1,
561 .settle_delay_usecs = 150,
562};
563
564static struct omap2_mcspi_device_config ads7846_mcspi_config = {
565 .turbo_mode = 0,
566 .single_channel = 1, /* 0: slave, 1: master */
567};
568
569struct spi_board_info omap3stalker_spi_board_info[] = {
570 [0] = {
571 .modalias = "ads7846",
572 .bus_num = 1,
573 .chip_select = 0,
574 .max_speed_hz = 1500000,
575 .controller_data = &ads7846_mcspi_config,
576 .irq = OMAP_GPIO_IRQ(OMAP3_STALKER_TS_GPIO),
577 .platform_data = &ads7846_config,
578 },
579};
580
581static struct omap_board_config_kernel omap3_stalker_config[] __initdata = {
582};
583
584static void __init omap3_stalker_init_irq(void)
585{
586 omap_board_config = omap3_stalker_config;
587 omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
588 omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL);
589 omap_init_irq();
590#ifdef CONFIG_OMAP_32K_TIMER
591 omap2_gp_clockevent_set_gptimer(12);
592#endif
593 omap_gpio_init();
594}
595
596static struct platform_device *omap3_stalker_devices[] __initdata = {
597 &omap3_stalker_dss_device,
598 &keys_gpio,
599};
600
601static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
602 .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN,
603 .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
604 .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
605
606 .phy_reset = true,
607 .reset_gpio_port[0] = -EINVAL,
608 .reset_gpio_port[1] = 21,
609 .reset_gpio_port[2] = -EINVAL,
610};
611
612#ifdef CONFIG_OMAP_MUX
613static struct omap_board_mux board_mux[] __initdata = {
614 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
615 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
616 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
617 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
618 {.reg_offset = OMAP_MUX_TERMINATOR},
619};
620#else
621#define board_mux NULL
622#endif
623
624static struct omap_musb_board_data musb_board_data = {
625 .interface_type = MUSB_INTERFACE_ULPI,
626 .mode = MUSB_OTG,
627 .power = 100,
628};
629
630static void __init omap3_stalker_init(void)
631{
632 omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
633
634 omap3_stalker_i2c_init();
635
636 platform_add_devices(omap3_stalker_devices,
637 ARRAY_SIZE(omap3_stalker_devices));
638
639 spi_register_board_info(omap3stalker_spi_board_info,
640 ARRAY_SIZE(omap3stalker_spi_board_info));
641
642 omap_serial_init();
643 usb_musb_init(&musb_board_data);
644 usb_ehci_init(&ehci_pdata);
645 ads7846_dev_init();
646
647 omap_mux_init_gpio(21, OMAP_PIN_OUTPUT);
648 omap_mux_init_gpio(18, OMAP_PIN_INPUT_PULLUP);
649
650 omap3stalker_init_eth();
651 omap3_stalker_display_init();
652/* Ensure SDRC pins are mux'd for self-refresh */
653 omap_mux_init_signal("sdr_cke0", OMAP_PIN_OUTPUT);
654 omap_mux_init_signal("sdr_cke1", OMAP_PIN_OUTPUT);
655}
656
657static void __init omap3_stalker_map_io(void)
658{
659 omap2_set_globals_343x();
660 omap34xx_map_common_io();
661}
662
663MACHINE_START(SBC3530, "OMAP3 STALKER")
664 /* Maintainer: Jason Lam -lzg@ema-tech.com */
665 .phys_io = 0x48000000,
666 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
667 .boot_params = 0x80000100,
668 .map_io = omap3_stalker_map_io,
669 .init_irq = omap3_stalker_init_irq,
670 .init_machine = omap3_stalker_init,
671 .timer = &omap_timer,
672MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 8848c7c5ce48..79ac41400c21 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -63,6 +63,8 @@
63 63
64#define OVERO_SMSC911X_CS 5 64#define OVERO_SMSC911X_CS 5
65#define OVERO_SMSC911X_GPIO 176 65#define OVERO_SMSC911X_GPIO 176
66#define OVERO_SMSC911X2_CS 4
67#define OVERO_SMSC911X2_GPIO 65
66 68
67#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ 69#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
68 defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) 70 defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
@@ -137,6 +139,16 @@ static struct resource overo_smsc911x_resources[] = {
137 }, 139 },
138}; 140};
139 141
142static struct resource overo_smsc911x2_resources[] = {
143 {
144 .name = "smsc911x2-memory",
145 .flags = IORESOURCE_MEM,
146 },
147 {
148 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
149 },
150};
151
140static struct smsc911x_platform_config overo_smsc911x_config = { 152static struct smsc911x_platform_config overo_smsc911x_config = {
141 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 153 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
142 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, 154 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
@@ -146,7 +158,7 @@ static struct smsc911x_platform_config overo_smsc911x_config = {
146 158
147static struct platform_device overo_smsc911x_device = { 159static struct platform_device overo_smsc911x_device = {
148 .name = "smsc911x", 160 .name = "smsc911x",
149 .id = -1, 161 .id = 0,
150 .num_resources = ARRAY_SIZE(overo_smsc911x_resources), 162 .num_resources = ARRAY_SIZE(overo_smsc911x_resources),
151 .resource = overo_smsc911x_resources, 163 .resource = overo_smsc911x_resources,
152 .dev = { 164 .dev = {
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 4377a4cf36eb..966f5f84f2bd 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -277,7 +277,7 @@ static struct regulator_consumer_supply rx51_vmmc1_supply = {
277 .dev_name = "mmci-omap-hs.0", 277 .dev_name = "mmci-omap-hs.0",
278}; 278};
279 279
280static struct regulator_consumer_supply rx51_vmmc2_supply = { 280static struct regulator_consumer_supply rx51_vaux3_supply = {
281 .supply = "vmmc", 281 .supply = "vmmc",
282 .dev_name = "mmci-omap-hs.1", 282 .dev_name = "mmci-omap-hs.1",
283}; 283};
@@ -287,6 +287,48 @@ static struct regulator_consumer_supply rx51_vsim_supply = {
287 .dev_name = "mmci-omap-hs.1", 287 .dev_name = "mmci-omap-hs.1",
288}; 288};
289 289
290static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
291 /* tlv320aic3x analog supplies */
292 {
293 .supply = "AVDD",
294 .dev_name = "2-0018",
295 },
296 {
297 .supply = "DRVDD",
298 .dev_name = "2-0018",
299 },
300 /* Keep vmmc as last item. It is not iterated for newer boards */
301 {
302 .supply = "vmmc",
303 .dev_name = "mmci-omap-hs.1",
304 },
305};
306
307static struct regulator_consumer_supply rx51_vio_supplies[] = {
308 /* tlv320aic3x digital supplies */
309 {
310 .supply = "IOVDD",
311 .dev_name = "2-0018"
312 },
313 {
314 .supply = "DVDD",
315 .dev_name = "2-0018"
316 },
317};
318
319#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
320extern struct platform_device rx51_display_device;
321#endif
322
323static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
324#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
325 {
326 .supply = "vdds_sdi",
327 .dev = &rx51_display_device.dev,
328 },
329#endif
330};
331
290static struct regulator_init_data rx51_vaux1 = { 332static struct regulator_init_data rx51_vaux1 = {
291 .constraints = { 333 .constraints = {
292 .name = "V28", 334 .name = "V28",
@@ -297,6 +339,8 @@ static struct regulator_init_data rx51_vaux1 = {
297 .valid_ops_mask = REGULATOR_CHANGE_MODE 339 .valid_ops_mask = REGULATOR_CHANGE_MODE
298 | REGULATOR_CHANGE_STATUS, 340 | REGULATOR_CHANGE_STATUS,
299 }, 341 },
342 .num_consumer_supplies = ARRAY_SIZE(rx51_vaux1_consumers),
343 .consumer_supplies = rx51_vaux1_consumers,
300}; 344};
301 345
302static struct regulator_init_data rx51_vaux2 = { 346static struct regulator_init_data rx51_vaux2 = {
@@ -338,7 +382,7 @@ static struct regulator_init_data rx51_vaux3_mmc = {
338 | REGULATOR_CHANGE_STATUS, 382 | REGULATOR_CHANGE_STATUS,
339 }, 383 },
340 .num_consumer_supplies = 1, 384 .num_consumer_supplies = 1,
341 .consumer_supplies = &rx51_vmmc2_supply, 385 .consumer_supplies = &rx51_vaux3_supply,
342}; 386};
343 387
344static struct regulator_init_data rx51_vaux4 = { 388static struct regulator_init_data rx51_vaux4 = {
@@ -370,9 +414,9 @@ static struct regulator_init_data rx51_vmmc1 = {
370 414
371static struct regulator_init_data rx51_vmmc2 = { 415static struct regulator_init_data rx51_vmmc2 = {
372 .constraints = { 416 .constraints = {
373 .name = "VMMC2_30", 417 .name = "V28_A",
374 .min_uV = 1850000, 418 .min_uV = 2800000,
375 .max_uV = 3150000, 419 .max_uV = 3000000,
376 .apply_uV = true, 420 .apply_uV = true,
377 .valid_modes_mask = REGULATOR_MODE_NORMAL 421 .valid_modes_mask = REGULATOR_MODE_NORMAL
378 | REGULATOR_MODE_STANDBY, 422 | REGULATOR_MODE_STANDBY,
@@ -380,8 +424,8 @@ static struct regulator_init_data rx51_vmmc2 = {
380 | REGULATOR_CHANGE_MODE 424 | REGULATOR_CHANGE_MODE
381 | REGULATOR_CHANGE_STATUS, 425 | REGULATOR_CHANGE_STATUS,
382 }, 426 },
383 .num_consumer_supplies = 1, 427 .num_consumer_supplies = ARRAY_SIZE(rx51_vmmc2_supplies),
384 .consumer_supplies = &rx51_vmmc2_supply, 428 .consumer_supplies = rx51_vmmc2_supplies,
385}; 429};
386 430
387static struct regulator_init_data rx51_vsim = { 431static struct regulator_init_data rx51_vsim = {
@@ -411,6 +455,20 @@ static struct regulator_init_data rx51_vdac = {
411 }, 455 },
412}; 456};
413 457
458static struct regulator_init_data rx51_vio = {
459 .constraints = {
460 .min_uV = 1800000,
461 .max_uV = 1800000,
462 .valid_modes_mask = REGULATOR_MODE_NORMAL
463 | REGULATOR_MODE_STANDBY,
464 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
465 | REGULATOR_CHANGE_MODE
466 | REGULATOR_CHANGE_STATUS,
467 },
468 .num_consumer_supplies = ARRAY_SIZE(rx51_vio_supplies),
469 .consumer_supplies = rx51_vio_supplies,
470};
471
414static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n) 472static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n)
415{ 473{
416 /* FIXME this gpio setup is just a placeholder for now */ 474 /* FIXME this gpio setup is just a placeholder for now */
@@ -618,6 +676,7 @@ static struct twl4030_platform_data rx51_twldata __initdata = {
618 .vmmc1 = &rx51_vmmc1, 676 .vmmc1 = &rx51_vmmc1,
619 .vsim = &rx51_vsim, 677 .vsim = &rx51_vsim,
620 .vdac = &rx51_vdac, 678 .vdac = &rx51_vdac,
679 .vio = &rx51_vio,
621}; 680};
622 681
623static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = { 682static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = {
@@ -629,18 +688,27 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = {
629 }, 688 },
630}; 689};
631 690
691static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = {
692 {
693 I2C_BOARD_INFO("tlv320aic3x", 0x18),
694 },
695};
696
632static int __init rx51_i2c_init(void) 697static int __init rx51_i2c_init(void)
633{ 698{
634 if ((system_rev >= SYSTEM_REV_S_USES_VAUX3 && system_rev < 0x100) || 699 if ((system_rev >= SYSTEM_REV_S_USES_VAUX3 && system_rev < 0x100) ||
635 system_rev >= SYSTEM_REV_B_USES_VAUX3) 700 system_rev >= SYSTEM_REV_B_USES_VAUX3) {
636 rx51_twldata.vaux3 = &rx51_vaux3_mmc; 701 rx51_twldata.vaux3 = &rx51_vaux3_mmc;
637 else { 702 /* Only older boards use VMMC2 for internal MMC */
703 rx51_vmmc2.num_consumer_supplies--;
704 } else {
638 rx51_twldata.vaux3 = &rx51_vaux3_cam; 705 rx51_twldata.vaux3 = &rx51_vaux3_cam;
639 rx51_twldata.vmmc2 = &rx51_vmmc2;
640 } 706 }
707 rx51_twldata.vmmc2 = &rx51_vmmc2;
641 omap_register_i2c_bus(1, 2200, rx51_peripherals_i2c_board_info_1, 708 omap_register_i2c_bus(1, 2200, rx51_peripherals_i2c_board_info_1,
642 ARRAY_SIZE(rx51_peripherals_i2c_board_info_1)); 709 ARRAY_SIZE(rx51_peripherals_i2c_board_info_1));
643 omap_register_i2c_bus(2, 100, NULL, 0); 710 omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
711 ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));
644 omap_register_i2c_bus(3, 400, NULL, 0); 712 omap_register_i2c_bus(3, 400, NULL, 0);
645 return 0; 713 return 0;
646} 714}
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index e15d2e87cfc1..1d7f827b0408 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -82,7 +82,7 @@ static inline void __init zoom_init_smsc911x(void)
82 82
83static struct plat_serial8250_port serial_platform_data[] = { 83static struct plat_serial8250_port serial_platform_data[] = {
84 { 84 {
85 .mapbase = 0x10000000, 85 .mapbase = ZOOM_UART_BASE,
86 .irq = OMAP_GPIO_IRQ(102), 86 .irq = OMAP_GPIO_IRQ(102),
87 .flags = UPF_BOOT_AUTOCONF|UPF_IOREMAP|UPF_SHARE_IRQ, 87 .flags = UPF_BOOT_AUTOCONF|UPF_IOREMAP|UPF_SHARE_IRQ,
88 .irqflags = IRQF_SHARED | IRQF_TRIGGER_RISING, 88 .irqflags = IRQF_SHARED | IRQF_TRIGGER_RISING,
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c
index 9a26f84b1141..803ef14cbf2d 100644
--- a/arch/arm/mach-omap2/board-zoom2.c
+++ b/arch/arm/mach-omap2/board-zoom2.c
@@ -91,8 +91,8 @@ static void __init omap_zoom2_map_io(void)
91} 91}
92 92
93MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") 93MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
94 .phys_io = 0x48000000, 94 .phys_io = ZOOM_UART_BASE,
95 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, 95 .io_pg_offst = (ZOOM_UART_VIRT >> 18) & 0xfffc,
96 .boot_params = 0x80000100, 96 .boot_params = 0x80000100,
97 .map_io = omap_zoom2_map_io, 97 .map_io = omap_zoom2_map_io,
98 .init_irq = omap_zoom2_init_irq, 98 .init_irq = omap_zoom2_init_irq,
diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c
index cd3e40cf3ac1..33147042485f 100644
--- a/arch/arm/mach-omap2/board-zoom3.c
+++ b/arch/arm/mach-omap2/board-zoom3.c
@@ -73,8 +73,8 @@ static void __init omap_zoom_init(void)
73} 73}
74 74
75MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") 75MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
76 .phys_io = 0x48000000, 76 .phys_io = ZOOM_UART_BASE,
77 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, 77 .io_pg_offst = (ZOOM_UART_VIRT >> 18) & 0xfffc,
78 .boot_params = 0x80000100, 78 .boot_params = 0x80000100,
79 .map_io = omap_zoom_map_io, 79 .map_io = omap_zoom_map_io,
80 .init_irq = omap_zoom_init_irq, 80 .init_irq = omap_zoom_init_irq,
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index 43d7246ce335..66e01acfd585 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -70,12 +70,12 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
70 70
71static int omap2_clk_apll96_enable(struct clk *clk) 71static int omap2_clk_apll96_enable(struct clk *clk)
72{ 72{
73 return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL); 73 return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL_MASK);
74} 74}
75 75
76static int omap2_clk_apll54_enable(struct clk *clk) 76static int omap2_clk_apll54_enable(struct clk *clk)
77{ 77{
78 return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL); 78 return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK);
79} 79}
80 80
81/* Stop APLL */ 81/* Stop APLL */
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index e60ca4e47bbd..aef62918aaf0 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -68,16 +68,13 @@ long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
68{ 68{
69 const struct prcm_config *ptr; 69 const struct prcm_config *ptr;
70 long highest_rate; 70 long highest_rate;
71 long sys_ck_rate;
72
73 sys_ck_rate = clk_get_rate(sclk);
74 71
75 highest_rate = -EINVAL; 72 highest_rate = -EINVAL;
76 73
77 for (ptr = rate_table; ptr->mpu_speed; ptr++) { 74 for (ptr = rate_table; ptr->mpu_speed; ptr++) {
78 if (!(ptr->flags & cpu_mask)) 75 if (!(ptr->flags & cpu_mask))
79 continue; 76 continue;
80 if (ptr->xtal_speed != sys_ck_rate) 77 if (ptr->xtal_speed != sclk->rate)
81 continue; 78 continue;
82 79
83 highest_rate = ptr->mpu_speed; 80 highest_rate = ptr->mpu_speed;
@@ -96,15 +93,12 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
96 const struct prcm_config *prcm; 93 const struct prcm_config *prcm;
97 unsigned long found_speed = 0; 94 unsigned long found_speed = 0;
98 unsigned long flags; 95 unsigned long flags;
99 long sys_ck_rate;
100
101 sys_ck_rate = clk_get_rate(sclk);
102 96
103 for (prcm = rate_table; prcm->mpu_speed; prcm++) { 97 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
104 if (!(prcm->flags & cpu_mask)) 98 if (!(prcm->flags & cpu_mask))
105 continue; 99 continue;
106 100
107 if (prcm->xtal_speed != sys_ck_rate) 101 if (prcm->xtal_speed != sclk->rate)
108 continue; 102 continue;
109 103
110 if (prcm->mpu_speed <= rate) { 104 if (prcm->mpu_speed <= rate) {
@@ -181,19 +175,16 @@ static struct cpufreq_frequency_table *freq_table;
181void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table) 175void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
182{ 176{
183 const struct prcm_config *prcm; 177 const struct prcm_config *prcm;
184 long sys_ck_rate;
185 int i = 0; 178 int i = 0;
186 int tbl_sz = 0; 179 int tbl_sz = 0;
187 180
188 if (!cpu_is_omap24xx()) 181 if (!cpu_is_omap24xx())
189 return; 182 return;
190 183
191 sys_ck_rate = clk_get_rate(sclk);
192
193 for (prcm = rate_table; prcm->mpu_speed; prcm++) { 184 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
194 if (!(prcm->flags & cpu_mask)) 185 if (!(prcm->flags & cpu_mask))
195 continue; 186 continue;
196 if (prcm->xtal_speed != sys_ck_rate) 187 if (prcm->xtal_speed != sclk->rate)
197 continue; 188 continue;
198 189
199 /* don't put bypass rates in table */ 190 /* don't put bypass rates in table */
@@ -226,7 +217,7 @@ void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
226 for (prcm = rate_table; prcm->mpu_speed; prcm++) { 217 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
227 if (!(prcm->flags & cpu_mask)) 218 if (!(prcm->flags & cpu_mask))
228 continue; 219 continue;
229 if (prcm->xtal_speed != sys_ck_rate) 220 if (prcm->xtal_speed != sclk->rate)
230 continue; 221 continue;
231 222
232 /* don't put bypass rates in table */ 223 /* don't put bypass rates in table */
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index e50812dd03fd..a781cd6795a4 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -12,8 +12,26 @@
12 * it under the terms of the GNU General Public License version 2 as 12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation. 13 * published by the Free Software Foundation.
14 * 14 *
15 * XXX At some point these clksel clocks should be split into 15 *
16 * "divider" clocks and "mux" clocks to better match the hardware. 16 * clksel clocks are clocks that do not have a fixed parent, or that
17 * can divide their parent's rate, or possibly both at the same time, based
18 * on the contents of a hardware register bitfield.
19 *
20 * All of the various mux and divider settings can be encoded into
21 * struct clksel* data structures, and then these can be autogenerated
22 * from some hardware database for each new chip generation. This
23 * should avoid the need to write, review, and validate a lot of new
24 * clock code for each new chip, since it can be exported from the SoC
25 * design flow. This is now done on OMAP4.
26 *
27 * The fusion of mux and divider clocks is a software creation. In
28 * hardware reality, the multiplexer (parent selection) and the
29 * divider exist separately. XXX At some point these clksel clocks
30 * should be split into "divider" clocks and "mux" clocks to better
31 * match the hardware.
32 *
33 * (The name "clksel" comes from the name of the corresponding
34 * register field in the OMAP2/3 family of SoCs.)
17 * 35 *
18 * XXX Currently these clocks are only used in the OMAP2/3/4 code, but 36 * XXX Currently these clocks are only used in the OMAP2/3/4 code, but
19 * many of the OMAP1 clocks should be convertible to use this 37 * many of the OMAP1 clocks should be convertible to use this
@@ -29,14 +47,11 @@
29#include <plat/clock.h> 47#include <plat/clock.h>
30 48
31#include "clock.h" 49#include "clock.h"
32#include "cm.h"
33#include "cm-regbits-24xx.h"
34#include "cm-regbits-34xx.h"
35 50
36/* Private functions */ 51/* Private functions */
37 52
38/** 53/**
39 * _omap2_get_clksel_by_parent - return clksel struct for a given clk & parent 54 * _get_clksel_by_parent() - return clksel struct for a given clk & parent
40 * @clk: OMAP struct clk ptr to inspect 55 * @clk: OMAP struct clk ptr to inspect
41 * @src_clk: OMAP struct clk ptr of the parent clk to search for 56 * @src_clk: OMAP struct clk ptr of the parent clk to search for
42 * 57 *
@@ -44,141 +59,217 @@
44 * the element associated with the supplied parent clock address. 59 * the element associated with the supplied parent clock address.
45 * Returns a pointer to the struct clksel on success or NULL on error. 60 * Returns a pointer to the struct clksel on success or NULL on error.
46 */ 61 */
47static const struct clksel *_omap2_get_clksel_by_parent(struct clk *clk, 62static const struct clksel *_get_clksel_by_parent(struct clk *clk,
48 struct clk *src_clk) 63 struct clk *src_clk)
49{ 64{
50 const struct clksel *clks; 65 const struct clksel *clks;
51 66
52 if (!clk->clksel) 67 for (clks = clk->clksel; clks->parent; clks++)
53 return NULL;
54
55 for (clks = clk->clksel; clks->parent; clks++) {
56 if (clks->parent == src_clk) 68 if (clks->parent == src_clk)
57 break; /* Found the requested parent */ 69 break; /* Found the requested parent */
58 }
59 70
60 if (!clks->parent) { 71 if (!clks->parent) {
61 printk(KERN_ERR "clock: Could not find parent clock %s in " 72 /* This indicates a data problem */
62 "clksel array of clock %s\n", src_clk->name, 73 WARN(1, "clock: Could not find parent clock %s in clksel array "
63 clk->name); 74 "of clock %s\n", src_clk->name, clk->name);
64 return NULL; 75 return NULL;
65 } 76 }
66 77
67 return clks; 78 return clks;
68} 79}
69 80
70/* 81/**
71 * Converts encoded control register address into a full address 82 * _get_div_and_fieldval() - find the new clksel divisor and field value to use
72 * On error, the return value (parent_div) will be 0. 83 * @src_clk: planned new parent struct clk *
84 * @clk: struct clk * that is being reparented
85 * @field_val: pointer to a u32 to contain the register data for the divisor
86 *
87 * Given an intended new parent struct clk * @src_clk, and the struct
88 * clk * @clk to the clock that is being reparented, find the
89 * appropriate rate divisor for the new clock (returned as the return
90 * value), and the corresponding register bitfield data to program to
91 * reach that divisor (returned in the u32 pointed to by @field_val).
92 * Returns 0 on error, or returns the newly-selected divisor upon
93 * success (in this latter case, the corresponding register bitfield
94 * value is passed back in the variable pointed to by @field_val)
73 */ 95 */
74static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk, 96static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
75 u32 *field_val) 97 u32 *field_val)
76{ 98{
77 const struct clksel *clks; 99 const struct clksel *clks;
78 const struct clksel_rate *clkr; 100 const struct clksel_rate *clkr, *max_clkr;
101 u8 max_div = 0;
79 102
80 clks = _omap2_get_clksel_by_parent(clk, src_clk); 103 clks = _get_clksel_by_parent(clk, src_clk);
81 if (!clks) 104 if (!clks)
82 return 0; 105 return 0;
83 106
107 /*
108 * Find the highest divisor (e.g., the one resulting in the
109 * lowest rate) to use as the default. This should avoid
110 * clock rates that are too high for the device. XXX A better
111 * solution here would be to try to determine if there is a
112 * divisor matching the original clock rate before the parent
113 * switch, and if it cannot be found, to fall back to the
114 * highest divisor.
115 */
84 for (clkr = clks->rates; clkr->div; clkr++) { 116 for (clkr = clks->rates; clkr->div; clkr++) {
85 if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE) 117 if (!(clkr->flags & cpu_mask))
86 break; /* Found the default rate for this platform */ 118 continue;
119
120 if (clkr->div > max_div) {
121 max_div = clkr->div;
122 max_clkr = clkr;
123 }
87 } 124 }
88 125
89 if (!clkr->div) { 126 if (max_div == 0) {
90 printk(KERN_ERR "clock: Could not find default rate for " 127 /* This indicates an error in the clksel data */
91 "clock %s parent %s\n", clk->name, 128 WARN(1, "clock: Could not find divisor for clock %s parent %s"
92 src_clk->parent->name); 129 "\n", clk->name, src_clk->parent->name);
93 return 0; 130 return 0;
94 } 131 }
95 132
96 /* Should never happen. Add a clksel mask to the struct clk. */ 133 *field_val = max_clkr->val;
97 WARN_ON(clk->clksel_mask == 0);
98 134
99 *field_val = clkr->val; 135 return max_div;
100
101 return clkr->div;
102} 136}
103 137
138/**
139 * _write_clksel_reg() - program a clock's clksel register in hardware
140 * @clk: struct clk * to program
141 * @v: clksel bitfield value to program (with LSB at bit 0)
142 *
143 * Shift the clksel register bitfield value @v to its appropriate
144 * location in the clksel register and write it in. This function
145 * will ensure that the write to the clksel_reg reaches its
146 * destination before returning -- important since PRM and CM register
147 * accesses can be quite slow compared to ARM cycles -- but does not
148 * take into account any time the hardware might take to switch the
149 * clock source.
150 */
151static void _write_clksel_reg(struct clk *clk, u32 field_val)
152{
153 u32 v;
104 154
105/* Public functions */ 155 v = __raw_readl(clk->clksel_reg);
156 v &= ~clk->clksel_mask;
157 v |= field_val << __ffs(clk->clksel_mask);
158 __raw_writel(v, clk->clksel_reg);
159
160 v = __raw_readl(clk->clksel_reg); /* OCP barrier */
161}
106 162
107/** 163/**
108 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware 164 * _clksel_to_divisor() - turn clksel field value into integer divider
109 * @clk: OMAP clock struct ptr to use 165 * @clk: OMAP struct clk to use
166 * @field_val: register field value to find
110 * 167 *
111 * Given a pointer to a source-selectable struct clk, read the hardware 168 * Given a struct clk of a rate-selectable clksel clock, and a register field
112 * register and determine what its parent is currently set to. Update the 169 * value to search for, find the corresponding clock divisor. The register
113 * clk->parent field with the appropriate clk ptr. 170 * field value should be pre-masked and shifted down so the LSB is at bit 0
171 * before calling. Returns 0 on error or returns the actual integer divisor
172 * upon success.
114 */ 173 */
115void omap2_init_clksel_parent(struct clk *clk) 174static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
116{ 175{
117 const struct clksel *clks; 176 const struct clksel *clks;
118 const struct clksel_rate *clkr; 177 const struct clksel_rate *clkr;
119 u32 r, found = 0;
120 178
121 if (!clk->clksel) 179 clks = _get_clksel_by_parent(clk, clk->parent);
122 return; 180 if (!clks)
181 return 0;
123 182
124 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; 183 for (clkr = clks->rates; clkr->div; clkr++) {
125 r >>= __ffs(clk->clksel_mask); 184 if (!(clkr->flags & cpu_mask))
185 continue;
126 186
127 for (clks = clk->clksel; clks->parent && !found; clks++) { 187 if (clkr->val == field_val)
128 for (clkr = clks->rates; clkr->div && !found; clkr++) { 188 break;
129 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
130 if (clk->parent != clks->parent) {
131 pr_debug("clock: inited %s parent "
132 "to %s (was %s)\n",
133 clk->name, clks->parent->name,
134 ((clk->parent) ?
135 clk->parent->name : "NULL"));
136 clk_reparent(clk, clks->parent);
137 };
138 found = 1;
139 }
140 }
141 } 189 }
142 190
143 if (!found) 191 if (!clkr->div) {
144 printk(KERN_ERR "clock: init parent: could not find " 192 /* This indicates a data error */
145 "regval %0x for clock %s\n", r, clk->name); 193 WARN(1, "clock: Could not find fieldval %d for clock %s parent "
194 "%s\n", field_val, clk->name, clk->parent->name);
195 return 0;
196 }
146 197
147 return; 198 return clkr->div;
148} 199}
149 200
150/* 201/**
151 * Used for clocks that are part of CLKSEL_xyz governed clocks. 202 * _divisor_to_clksel() - turn clksel integer divisor into a field value
152 * REVISIT: Maybe change to use clk->enable() functions like on omap1? 203 * @clk: OMAP struct clk to use
204 * @div: integer divisor to search for
205 *
206 * Given a struct clk of a rate-selectable clksel clock, and a clock
207 * divisor, find the corresponding register field value. Returns the
208 * register field value _before_ left-shifting (i.e., LSB is at bit
209 * 0); or returns 0xFFFFFFFF (~0) upon error.
153 */ 210 */
154unsigned long omap2_clksel_recalc(struct clk *clk) 211static u32 _divisor_to_clksel(struct clk *clk, u32 div)
155{ 212{
156 unsigned long rate; 213 const struct clksel *clks;
157 u32 div = 0; 214 const struct clksel_rate *clkr;
158 215
159 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); 216 /* should never happen */
217 WARN_ON(div == 0);
160 218
161 div = omap2_clksel_get_divisor(clk); 219 clks = _get_clksel_by_parent(clk, clk->parent);
162 if (div == 0) 220 if (!clks)
163 return clk->rate; 221 return ~0;
164 222
165 rate = clk->parent->rate / div; 223 for (clkr = clks->rates; clkr->div; clkr++) {
224 if (!(clkr->flags & cpu_mask))
225 continue;
166 226
167 pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div); 227 if (clkr->div == div)
228 break;
229 }
168 230
169 return rate; 231 if (!clkr->div) {
232 pr_err("clock: Could not find divisor %d for clock %s parent "
233 "%s\n", div, clk->name, clk->parent->name);
234 return ~0;
235 }
236
237 return clkr->val;
238}
239
240/**
241 * _read_divisor() - get current divisor applied to parent clock (from hdwr)
242 * @clk: OMAP struct clk to use.
243 *
244 * Read the current divisor register value for @clk that is programmed
245 * into the hardware, convert it into the actual divisor value, and
246 * return it; or return 0 on error.
247 */
248static u32 _read_divisor(struct clk *clk)
249{
250 u32 v;
251
252 if (!clk->clksel || !clk->clksel_mask)
253 return 0;
254
255 v = __raw_readl(clk->clksel_reg);
256 v &= clk->clksel_mask;
257 v >>= __ffs(clk->clksel_mask);
258
259 return _clksel_to_divisor(clk, v);
170} 260}
171 261
262/* Public functions */
263
172/** 264/**
173 * omap2_clksel_round_rate_div - find divisor for the given clock and rate 265 * omap2_clksel_round_rate_div() - find divisor for the given clock and rate
174 * @clk: OMAP struct clk to use 266 * @clk: OMAP struct clk to use
175 * @target_rate: desired clock rate 267 * @target_rate: desired clock rate
176 * @new_div: ptr to where we should store the divisor 268 * @new_div: ptr to where we should store the divisor
177 * 269 *
178 * Finds 'best' divider value in an array based on the source and target 270 * Finds 'best' divider value in an array based on the source and target
179 * rates. The divider array must be sorted with smallest divider first. 271 * rates. The divider array must be sorted with smallest divider first.
180 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, 272 * This function is also used by the DPLL3 M2 divider code.
181 * they are only settable as part of virtual_prcm set.
182 * 273 *
183 * Returns the rounded clock rate or returns 0xffffffff on error. 274 * Returns the rounded clock rate or returns 0xffffffff on error.
184 */ 275 */
@@ -190,12 +281,15 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
190 const struct clksel_rate *clkr; 281 const struct clksel_rate *clkr;
191 u32 last_div = 0; 282 u32 last_div = 0;
192 283
284 if (!clk->clksel || !clk->clksel_mask)
285 return ~0;
286
193 pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", 287 pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
194 clk->name, target_rate); 288 clk->name, target_rate);
195 289
196 *new_div = 1; 290 *new_div = 1;
197 291
198 clks = _omap2_get_clksel_by_parent(clk, clk->parent); 292 clks = _get_clksel_by_parent(clk, clk->parent);
199 if (!clks) 293 if (!clks)
200 return ~0; 294 return ~0;
201 295
@@ -231,168 +325,174 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
231 return clk->parent->rate / clkr->div; 325 return clk->parent->rate / clkr->div;
232} 326}
233 327
234/** 328/*
235 * omap2_clksel_round_rate - find rounded rate for the given clock and rate 329 * Clocktype interface functions to the OMAP clock code
236 * @clk: OMAP struct clk to use 330 * (i.e., those used in struct clk field function pointers, etc.)
237 * @target_rate: desired clock rate
238 *
239 * Compatibility wrapper for OMAP clock framework
240 * Finds best target rate based on the source clock and possible dividers.
241 * rates. The divider array must be sorted with smallest divider first.
242 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
243 * they are only settable as part of virtual_prcm set.
244 *
245 * Returns the rounded clock rate or returns 0xffffffff on error.
246 */ 331 */
247long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
248{
249 u32 new_div;
250
251 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
252}
253
254
255/* Given a clock and a rate apply a clock specific rounding function */
256long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
257{
258 if (clk->round_rate)
259 return clk->round_rate(clk, rate);
260
261 return clk->rate;
262}
263 332
264/** 333/**
265 * omap2_clksel_to_divisor() - turn clksel field value into integer divider 334 * omap2_init_clksel_parent() - set a clksel clk's parent field from the hdwr
266 * @clk: OMAP struct clk to use 335 * @clk: OMAP clock struct ptr to use
267 * @field_val: register field value to find
268 * 336 *
269 * Given a struct clk of a rate-selectable clksel clock, and a register field 337 * Given a pointer @clk to a source-selectable struct clk, read the
270 * value to search for, find the corresponding clock divisor. The register 338 * hardware register and determine what its parent is currently set
271 * field value should be pre-masked and shifted down so the LSB is at bit 0 339 * to. Update @clk's .parent field with the appropriate clk ptr. No
272 * before calling. Returns 0 on error 340 * return value.
273 */ 341 */
274u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val) 342void omap2_init_clksel_parent(struct clk *clk)
275{ 343{
276 const struct clksel *clks; 344 const struct clksel *clks;
277 const struct clksel_rate *clkr; 345 const struct clksel_rate *clkr;
346 u32 r, found = 0;
278 347
279 clks = _omap2_get_clksel_by_parent(clk, clk->parent); 348 if (!clk->clksel || !clk->clksel_mask)
280 if (!clks) 349 return;
281 return 0;
282 350
283 for (clkr = clks->rates; clkr->div; clkr++) { 351 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
284 if ((clkr->flags & cpu_mask) && (clkr->val == field_val)) 352 r >>= __ffs(clk->clksel_mask);
285 break;
286 }
287 353
288 if (!clkr->div) { 354 for (clks = clk->clksel; clks->parent && !found; clks++) {
289 printk(KERN_ERR "clock: Could not find fieldval %d for " 355 for (clkr = clks->rates; clkr->div && !found; clkr++) {
290 "clock %s parent %s\n", field_val, clk->name, 356 if (!(clkr->flags & cpu_mask))
291 clk->parent->name); 357 continue;
292 return 0; 358
359 if (clkr->val == r) {
360 if (clk->parent != clks->parent) {
361 pr_debug("clock: inited %s parent "
362 "to %s (was %s)\n",
363 clk->name, clks->parent->name,
364 ((clk->parent) ?
365 clk->parent->name : "NULL"));
366 clk_reparent(clk, clks->parent);
367 };
368 found = 1;
369 }
370 }
293 } 371 }
294 372
295 return clkr->div; 373 /* This indicates a data error */
374 WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
375 clk->name, r);
376
377 return;
296} 378}
297 379
298/** 380/**
299 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value 381 * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field
300 * @clk: OMAP struct clk to use 382 * @clk: struct clk *
301 * @div: integer divisor to search for
302 * 383 *
303 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor, 384 * This function is intended to be called only by the clock framework.
304 * find the corresponding register field value. The return register value is 385 * Each clksel clock should have its struct clk .recalc field set to this
305 * the value before left-shifting. Returns ~0 on error 386 * function. Returns the clock's current rate, based on its parent's rate
387 * and its current divisor setting in the hardware.
306 */ 388 */
307u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) 389unsigned long omap2_clksel_recalc(struct clk *clk)
308{ 390{
309 const struct clksel *clks; 391 unsigned long rate;
310 const struct clksel_rate *clkr; 392 u32 div = 0;
311
312 /* should never happen */
313 WARN_ON(div == 0);
314 393
315 clks = _omap2_get_clksel_by_parent(clk, clk->parent); 394 div = _read_divisor(clk);
316 if (!clks) 395 if (div == 0)
317 return ~0; 396 return clk->rate;
318 397
319 for (clkr = clks->rates; clkr->div; clkr++) { 398 rate = clk->parent->rate / div;
320 if ((clkr->flags & cpu_mask) && (clkr->div == div))
321 break;
322 }
323 399
324 if (!clkr->div) { 400 pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name,
325 printk(KERN_ERR "clock: Could not find divisor %d for " 401 rate, div);
326 "clock %s parent %s\n", div, clk->name,
327 clk->parent->name);
328 return ~0;
329 }
330 402
331 return clkr->val; 403 return rate;
332} 404}
333 405
334/** 406/**
335 * omap2_clksel_get_divisor - get current divider applied to parent clock. 407 * omap2_clksel_round_rate() - find rounded rate for the given clock and rate
336 * @clk: OMAP struct clk to use. 408 * @clk: OMAP struct clk to use
409 * @target_rate: desired clock rate
410 *
411 * This function is intended to be called only by the clock framework.
412 * Finds best target rate based on the source clock and possible dividers.
413 * rates. The divider array must be sorted with smallest divider first.
337 * 414 *
338 * Returns the integer divisor upon success or 0 on error. 415 * Returns the rounded clock rate or returns 0xffffffff on error.
339 */ 416 */
340u32 omap2_clksel_get_divisor(struct clk *clk) 417long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
341{ 418{
342 u32 v; 419 u32 new_div;
343
344 if (!clk->clksel_mask)
345 return 0;
346
347 v = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
348 v >>= __ffs(clk->clksel_mask);
349 420
350 return omap2_clksel_to_divisor(clk, v); 421 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
351} 422}
352 423
424/**
425 * omap2_clksel_set_rate() - program clock rate in hardware
426 * @clk: struct clk * to program rate
427 * @rate: target rate to program
428 *
429 * This function is intended to be called only by the clock framework.
430 * Program @clk's rate to @rate in the hardware. The clock can be
431 * either enabled or disabled when this happens, although if the clock
432 * is enabled, some downstream devices may glitch or behave
433 * unpredictably when the clock rate is changed - this depends on the
434 * hardware. This function does not currently check the usecount of
435 * the clock, so if multiple drivers are using the clock, and the rate
436 * is changed, they will all be affected without any notification.
437 * Returns -EINVAL upon error, or 0 upon success.
438 */
353int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) 439int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
354{ 440{
355 u32 v, field_val, validrate, new_div = 0; 441 u32 field_val, validrate, new_div = 0;
356 442
357 if (!clk->clksel_mask) 443 if (!clk->clksel || !clk->clksel_mask)
358 return -EINVAL; 444 return -EINVAL;
359 445
360 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); 446 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
361 if (validrate != rate) 447 if (validrate != rate)
362 return -EINVAL; 448 return -EINVAL;
363 449
364 field_val = omap2_divisor_to_clksel(clk, new_div); 450 field_val = _divisor_to_clksel(clk, new_div);
365 if (field_val == ~0) 451 if (field_val == ~0)
366 return -EINVAL; 452 return -EINVAL;
367 453
368 v = __raw_readl(clk->clksel_reg); 454 _write_clksel_reg(clk, field_val);
369 v &= ~clk->clksel_mask;
370 v |= field_val << __ffs(clk->clksel_mask);
371 __raw_writel(v, clk->clksel_reg);
372 v = __raw_readl(clk->clksel_reg); /* OCP barrier */
373 455
374 clk->rate = clk->parent->rate / new_div; 456 clk->rate = clk->parent->rate / new_div;
375 457
458 pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate);
459
376 return 0; 460 return 0;
377} 461}
378 462
463/*
464 * Clksel parent setting function - not passed in struct clk function
465 * pointer - instead, the OMAP clock code currently assumes that any
466 * parent-setting clock is a clksel clock, and calls
467 * omap2_clksel_set_parent() by default
468 */
469
470/**
471 * omap2_clksel_set_parent() - change a clock's parent clock
472 * @clk: struct clk * of the child clock
473 * @new_parent: struct clk * of the new parent clock
474 *
475 * This function is intended to be called only by the clock framework.
476 * Change the parent clock of clock @clk to @new_parent. This is
477 * intended to be used while @clk is disabled. This function does not
478 * currently check the usecount of the clock, so if multiple drivers
479 * are using the clock, and the parent is changed, they will all be
480 * affected without any notification. Returns -EINVAL upon error, or
481 * 0 upon success.
482 */
379int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) 483int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
380{ 484{
381 u32 field_val, v, parent_div; 485 u32 field_val = 0;
486 u32 parent_div;
382 487
383 if (!clk->clksel) 488 if (!clk->clksel || !clk->clksel_mask)
384 return -EINVAL; 489 return -EINVAL;
385 490
386 parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val); 491 parent_div = _get_div_and_fieldval(new_parent, clk, &field_val);
387 if (!parent_div) 492 if (!parent_div)
388 return -EINVAL; 493 return -EINVAL;
389 494
390 /* Set new source value (previous dividers if any in effect) */ 495 _write_clksel_reg(clk, field_val);
391 v = __raw_readl(clk->clksel_reg);
392 v &= ~clk->clksel_mask;
393 v |= field_val << __ffs(clk->clksel_mask);
394 __raw_writel(v, clk->clksel_reg);
395 v = __raw_readl(clk->clksel_reg); /* OCP barrier */
396 496
397 clk_reparent(clk, new_parent); 497 clk_reparent(clk, new_parent);
398 498
@@ -402,7 +502,7 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
402 if (parent_div > 0) 502 if (parent_div > 0)
403 clk->rate /= parent_div; 503 clk->rate /= parent_div;
404 504
405 pr_debug("clock: set parent of %s to %s (new rate %ld)\n", 505 pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
406 clk->name, clk->parent->name, clk->rate); 506 clk->name, clk->parent->name, clk->rate);
407 507
408 return 0; 508 return 0;
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index a6d0b34b7990..605f531783a8 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -334,6 +334,15 @@ oce_err1:
334 return ret; 334 return ret;
335} 335}
336 336
337/* Given a clock and a rate apply a clock specific rounding function */
338long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
339{
340 if (clk->round_rate)
341 return clk->round_rate(clk, rate);
342
343 return clk->rate;
344}
345
337/* Set the clock rate for a clock source */ 346/* Set the clock rate for a clock source */
338int omap2_clk_set_rate(struct clk *clk, unsigned long rate) 347int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
339{ 348{
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index ad8a1f7c1afc..a535c7a2a62a 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -73,19 +73,20 @@ void omap2_clk_disable_unused(struct clk *clk);
73#define omap2_clk_disable_unused NULL 73#define omap2_clk_disable_unused NULL
74#endif 74#endif
75 75
76unsigned long omap2_clksel_recalc(struct clk *clk);
77void omap2_init_clk_clkdm(struct clk *clk); 76void omap2_init_clk_clkdm(struct clk *clk);
78void omap2_init_clksel_parent(struct clk *clk); 77
79u32 omap2_clksel_get_divisor(struct clk *clk); 78/* clkt_clksel.c public functions */
80u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, 79u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
81 u32 *new_div); 80 u32 *new_div);
82u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val); 81void omap2_init_clksel_parent(struct clk *clk);
83u32 omap2_divisor_to_clksel(struct clk *clk, u32 div); 82unsigned long omap2_clksel_recalc(struct clk *clk);
84long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); 83long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
85int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); 84int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
86int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent); 85int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
86
87u32 omap2_get_dpll_rate(struct clk *clk); 87u32 omap2_get_dpll_rate(struct clk *clk);
88void omap2_init_dpll_parent(struct clk *clk); 88void omap2_init_dpll_parent(struct clk *clk);
89
89int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); 90int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
90 91
91 92
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index d932b142d0b6..23bc981574f6 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -155,12 +155,12 @@ static struct clk apll54_ck = {
155/* func_54m_ck */ 155/* func_54m_ck */
156 156
157static const struct clksel_rate func_54m_apll54_rates[] = { 157static const struct clksel_rate func_54m_apll54_rates[] = {
158 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 158 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
159 { .div = 0 }, 159 { .div = 0 },
160}; 160};
161 161
162static const struct clksel_rate func_54m_alt_rates[] = { 162static const struct clksel_rate func_54m_alt_rates[] = {
163 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 163 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
164 { .div = 0 }, 164 { .div = 0 },
165}; 165};
166 166
@@ -177,7 +177,7 @@ static struct clk func_54m_ck = {
177 .clkdm_name = "wkup_clkdm", 177 .clkdm_name = "wkup_clkdm",
178 .init = &omap2_init_clksel_parent, 178 .init = &omap2_init_clksel_parent,
179 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 179 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
180 .clksel_mask = OMAP24XX_54M_SOURCE, 180 .clksel_mask = OMAP24XX_54M_SOURCE_MASK,
181 .clksel = func_54m_clksel, 181 .clksel = func_54m_clksel,
182 .recalc = &omap2_clksel_recalc, 182 .recalc = &omap2_clksel_recalc,
183}; 183};
@@ -201,12 +201,12 @@ static struct clk func_96m_ck = {
201/* func_48m_ck */ 201/* func_48m_ck */
202 202
203static const struct clksel_rate func_48m_apll96_rates[] = { 203static const struct clksel_rate func_48m_apll96_rates[] = {
204 { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 204 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
205 { .div = 0 }, 205 { .div = 0 },
206}; 206};
207 207
208static const struct clksel_rate func_48m_alt_rates[] = { 208static const struct clksel_rate func_48m_alt_rates[] = {
209 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 209 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
210 { .div = 0 }, 210 { .div = 0 },
211}; 211};
212 212
@@ -223,7 +223,7 @@ static struct clk func_48m_ck = {
223 .clkdm_name = "wkup_clkdm", 223 .clkdm_name = "wkup_clkdm",
224 .init = &omap2_init_clksel_parent, 224 .init = &omap2_init_clksel_parent,
225 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 225 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
226 .clksel_mask = OMAP24XX_48M_SOURCE, 226 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
227 .clksel = func_48m_clksel, 227 .clksel = func_48m_clksel,
228 .recalc = &omap2_clksel_recalc, 228 .recalc = &omap2_clksel_recalc,
229 .round_rate = &omap2_clksel_round_rate, 229 .round_rate = &omap2_clksel_round_rate,
@@ -256,22 +256,22 @@ static struct clk wdt1_osc_ck = {
256 * flags fields, which mark them as 2420-only. 256 * flags fields, which mark them as 2420-only.
257 */ 257 */
258static const struct clksel_rate common_clkout_src_core_rates[] = { 258static const struct clksel_rate common_clkout_src_core_rates[] = {
259 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 259 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
260 { .div = 0 } 260 { .div = 0 }
261}; 261};
262 262
263static const struct clksel_rate common_clkout_src_sys_rates[] = { 263static const struct clksel_rate common_clkout_src_sys_rates[] = {
264 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 264 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
265 { .div = 0 } 265 { .div = 0 }
266}; 266};
267 267
268static const struct clksel_rate common_clkout_src_96m_rates[] = { 268static const struct clksel_rate common_clkout_src_96m_rates[] = {
269 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, 269 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
270 { .div = 0 } 270 { .div = 0 }
271}; 271};
272 272
273static const struct clksel_rate common_clkout_src_54m_rates[] = { 273static const struct clksel_rate common_clkout_src_54m_rates[] = {
274 { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE }, 274 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
275 { .div = 0 } 275 { .div = 0 }
276}; 276};
277 277
@@ -300,7 +300,7 @@ static struct clk sys_clkout_src = {
300}; 300};
301 301
302static const struct clksel_rate common_clkout_rates[] = { 302static const struct clksel_rate common_clkout_rates[] = {
303 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 303 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
304 { .div = 2, .val = 1, .flags = RATE_IN_24XX }, 304 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
305 { .div = 4, .val = 2, .flags = RATE_IN_24XX }, 305 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
306 { .div = 8, .val = 3, .flags = RATE_IN_24XX }, 306 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
@@ -384,7 +384,7 @@ static struct clk emul_ck = {
384 * 384 *
385 */ 385 */
386static const struct clksel_rate mpu_core_rates[] = { 386static const struct clksel_rate mpu_core_rates[] = {
387 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 387 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
388 { .div = 2, .val = 2, .flags = RATE_IN_24XX }, 388 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
389 { .div = 4, .val = 4, .flags = RATE_IN_242X }, 389 { .div = 4, .val = 4, .flags = RATE_IN_242X },
390 { .div = 6, .val = 6, .flags = RATE_IN_242X }, 390 { .div = 6, .val = 6, .flags = RATE_IN_242X },
@@ -420,7 +420,7 @@ static struct clk mpu_ck = { /* Control cpu */
420 * routed into a synchronizer and out of clocks abc. 420 * routed into a synchronizer and out of clocks abc.
421 */ 421 */
422static const struct clksel_rate dsp_fck_core_rates[] = { 422static const struct clksel_rate dsp_fck_core_rates[] = {
423 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 423 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
424 { .div = 2, .val = 2, .flags = RATE_IN_24XX }, 424 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
425 { .div = 3, .val = 3, .flags = RATE_IN_24XX }, 425 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
426 { .div = 4, .val = 4, .flags = RATE_IN_24XX }, 426 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
@@ -450,7 +450,7 @@ static struct clk dsp_fck = {
450 450
451/* DSP interface clock */ 451/* DSP interface clock */
452static const struct clksel_rate dsp_irate_ick_rates[] = { 452static const struct clksel_rate dsp_irate_ick_rates[] = {
453 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 453 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
454 { .div = 2, .val = 2, .flags = RATE_IN_24XX }, 454 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
455 { .div = 0 }, 455 { .div = 0 },
456}; 456};
@@ -532,7 +532,7 @@ static struct clk iva1_mpu_int_ifck = {
532static const struct clksel_rate core_l3_core_rates[] = { 532static const struct clksel_rate core_l3_core_rates[] = {
533 { .div = 1, .val = 1, .flags = RATE_IN_24XX }, 533 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
534 { .div = 2, .val = 2, .flags = RATE_IN_242X }, 534 { .div = 2, .val = 2, .flags = RATE_IN_242X },
535 { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE }, 535 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
536 { .div = 6, .val = 6, .flags = RATE_IN_24XX }, 536 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
537 { .div = 8, .val = 8, .flags = RATE_IN_242X }, 537 { .div = 8, .val = 8, .flags = RATE_IN_242X },
538 { .div = 12, .val = 12, .flags = RATE_IN_242X }, 538 { .div = 12, .val = 12, .flags = RATE_IN_242X },
@@ -559,7 +559,7 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
559/* usb_l4_ick */ 559/* usb_l4_ick */
560static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { 560static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
561 { .div = 1, .val = 1, .flags = RATE_IN_24XX }, 561 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
562 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, 562 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
563 { .div = 4, .val = 4, .flags = RATE_IN_24XX }, 563 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
564 { .div = 0 } 564 { .div = 0 }
565}; 565};
@@ -591,7 +591,7 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */
591 * this domain. 591 * this domain.
592 */ 592 */
593static const struct clksel_rate l4_core_l3_rates[] = { 593static const struct clksel_rate l4_core_l3_rates[] = {
594 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 594 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
595 { .div = 2, .val = 2, .flags = RATE_IN_24XX }, 595 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
596 { .div = 0 } 596 { .div = 0 }
597}; 597};
@@ -622,7 +622,7 @@ static struct clk l4_ck = { /* used both as an ick and fck */
622 */ 622 */
623static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { 623static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
624 { .div = 1, .val = 1, .flags = RATE_IN_24XX }, 624 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
625 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, 625 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
626 { .div = 3, .val = 3, .flags = RATE_IN_24XX }, 626 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
627 { .div = 4, .val = 4, .flags = RATE_IN_24XX }, 627 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
628 { .div = 6, .val = 6, .flags = RATE_IN_242X }, 628 { .div = 6, .val = 6, .flags = RATE_IN_242X },
@@ -730,7 +730,7 @@ static struct clk gfx_ick = {
730/* XXX Add RATE_NOT_VALIDATED */ 730/* XXX Add RATE_NOT_VALIDATED */
731 731
732static const struct clksel_rate dss1_fck_sys_rates[] = { 732static const struct clksel_rate dss1_fck_sys_rates[] = {
733 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 733 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
734 { .div = 0 } 734 { .div = 0 }
735}; 735};
736 736
@@ -744,7 +744,7 @@ static const struct clksel_rate dss1_fck_core_rates[] = {
744 { .div = 8, .val = 8, .flags = RATE_IN_24XX }, 744 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
745 { .div = 9, .val = 9, .flags = RATE_IN_24XX }, 745 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
746 { .div = 12, .val = 12, .flags = RATE_IN_24XX }, 746 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
747 { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE }, 747 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
748 { .div = 0 } 748 { .div = 0 }
749}; 749};
750 750
@@ -779,12 +779,12 @@ static struct clk dss1_fck = {
779}; 779};
780 780
781static const struct clksel_rate dss2_fck_sys_rates[] = { 781static const struct clksel_rate dss2_fck_sys_rates[] = {
782 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 782 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
783 { .div = 0 } 783 { .div = 0 }
784}; 784};
785 785
786static const struct clksel_rate dss2_fck_48m_rates[] = { 786static const struct clksel_rate dss2_fck_48m_rates[] = {
787 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 787 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
788 { .div = 0 } 788 { .div = 0 }
789}; 789};
790 790
@@ -825,7 +825,7 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */
825 * functional clock parents. 825 * functional clock parents.
826 */ 826 */
827static const struct clksel_rate gpt_alt_rates[] = { 827static const struct clksel_rate gpt_alt_rates[] = {
828 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, 828 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
829 { .div = 0 } 829 { .div = 0 }
830}; 830};
831 831
@@ -1588,7 +1588,7 @@ static struct clk vlynq_ick = {
1588}; 1588};
1589 1589
1590static const struct clksel_rate vlynq_fck_96m_rates[] = { 1590static const struct clksel_rate vlynq_fck_96m_rates[] = {
1591 { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE }, 1591 { .div = 1, .val = 0, .flags = RATE_IN_242X },
1592 { .div = 0 } 1592 { .div = 0 }
1593}; 1593};
1594 1594
@@ -1601,7 +1601,7 @@ static const struct clksel_rate vlynq_fck_core_rates[] = {
1601 { .div = 8, .val = 8, .flags = RATE_IN_242X }, 1601 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1602 { .div = 9, .val = 9, .flags = RATE_IN_242X }, 1602 { .div = 9, .val = 9, .flags = RATE_IN_242X },
1603 { .div = 12, .val = 12, .flags = RATE_IN_242X }, 1603 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1604 { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE }, 1604 { .div = 16, .val = 16, .flags = RATE_IN_242X },
1605 { .div = 18, .val = 18, .flags = RATE_IN_242X }, 1605 { .div = 18, .val = 18, .flags = RATE_IN_242X },
1606 { .div = 0 } 1606 { .div = 0 }
1607}; 1607};
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 0438b6e4f51a..2df50d97deb2 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -155,12 +155,12 @@ static struct clk apll54_ck = {
155/* func_54m_ck */ 155/* func_54m_ck */
156 156
157static const struct clksel_rate func_54m_apll54_rates[] = { 157static const struct clksel_rate func_54m_apll54_rates[] = {
158 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 158 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
159 { .div = 0 }, 159 { .div = 0 },
160}; 160};
161 161
162static const struct clksel_rate func_54m_alt_rates[] = { 162static const struct clksel_rate func_54m_alt_rates[] = {
163 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 163 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
164 { .div = 0 }, 164 { .div = 0 },
165}; 165};
166 166
@@ -177,7 +177,7 @@ static struct clk func_54m_ck = {
177 .clkdm_name = "wkup_clkdm", 177 .clkdm_name = "wkup_clkdm",
178 .init = &omap2_init_clksel_parent, 178 .init = &omap2_init_clksel_parent,
179 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 179 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
180 .clksel_mask = OMAP24XX_54M_SOURCE, 180 .clksel_mask = OMAP24XX_54M_SOURCE_MASK,
181 .clksel = func_54m_clksel, 181 .clksel = func_54m_clksel,
182 .recalc = &omap2_clksel_recalc, 182 .recalc = &omap2_clksel_recalc,
183}; 183};
@@ -192,12 +192,12 @@ static struct clk core_ck = {
192 192
193/* func_96m_ck */ 193/* func_96m_ck */
194static const struct clksel_rate func_96m_apll96_rates[] = { 194static const struct clksel_rate func_96m_apll96_rates[] = {
195 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 195 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
196 { .div = 0 }, 196 { .div = 0 },
197}; 197};
198 198
199static const struct clksel_rate func_96m_alt_rates[] = { 199static const struct clksel_rate func_96m_alt_rates[] = {
200 { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE }, 200 { .div = 1, .val = 1, .flags = RATE_IN_243X },
201 { .div = 0 }, 201 { .div = 0 },
202}; 202};
203 203
@@ -214,7 +214,7 @@ static struct clk func_96m_ck = {
214 .clkdm_name = "wkup_clkdm", 214 .clkdm_name = "wkup_clkdm",
215 .init = &omap2_init_clksel_parent, 215 .init = &omap2_init_clksel_parent,
216 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 216 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
217 .clksel_mask = OMAP2430_96M_SOURCE, 217 .clksel_mask = OMAP2430_96M_SOURCE_MASK,
218 .clksel = func_96m_clksel, 218 .clksel = func_96m_clksel,
219 .recalc = &omap2_clksel_recalc, 219 .recalc = &omap2_clksel_recalc,
220}; 220};
@@ -222,12 +222,12 @@ static struct clk func_96m_ck = {
222/* func_48m_ck */ 222/* func_48m_ck */
223 223
224static const struct clksel_rate func_48m_apll96_rates[] = { 224static const struct clksel_rate func_48m_apll96_rates[] = {
225 { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 225 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
226 { .div = 0 }, 226 { .div = 0 },
227}; 227};
228 228
229static const struct clksel_rate func_48m_alt_rates[] = { 229static const struct clksel_rate func_48m_alt_rates[] = {
230 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 230 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
231 { .div = 0 }, 231 { .div = 0 },
232}; 232};
233 233
@@ -244,7 +244,7 @@ static struct clk func_48m_ck = {
244 .clkdm_name = "wkup_clkdm", 244 .clkdm_name = "wkup_clkdm",
245 .init = &omap2_init_clksel_parent, 245 .init = &omap2_init_clksel_parent,
246 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 246 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
247 .clksel_mask = OMAP24XX_48M_SOURCE, 247 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
248 .clksel = func_48m_clksel, 248 .clksel = func_48m_clksel,
249 .recalc = &omap2_clksel_recalc, 249 .recalc = &omap2_clksel_recalc,
250 .round_rate = &omap2_clksel_round_rate, 250 .round_rate = &omap2_clksel_round_rate,
@@ -277,22 +277,22 @@ static struct clk wdt1_osc_ck = {
277 * flags fields, which mark them as 2420-only. 277 * flags fields, which mark them as 2420-only.
278 */ 278 */
279static const struct clksel_rate common_clkout_src_core_rates[] = { 279static const struct clksel_rate common_clkout_src_core_rates[] = {
280 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 280 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
281 { .div = 0 } 281 { .div = 0 }
282}; 282};
283 283
284static const struct clksel_rate common_clkout_src_sys_rates[] = { 284static const struct clksel_rate common_clkout_src_sys_rates[] = {
285 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 285 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
286 { .div = 0 } 286 { .div = 0 }
287}; 287};
288 288
289static const struct clksel_rate common_clkout_src_96m_rates[] = { 289static const struct clksel_rate common_clkout_src_96m_rates[] = {
290 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, 290 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
291 { .div = 0 } 291 { .div = 0 }
292}; 292};
293 293
294static const struct clksel_rate common_clkout_src_54m_rates[] = { 294static const struct clksel_rate common_clkout_src_54m_rates[] = {
295 { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE }, 295 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
296 { .div = 0 } 296 { .div = 0 }
297}; 297};
298 298
@@ -321,7 +321,7 @@ static struct clk sys_clkout_src = {
321}; 321};
322 322
323static const struct clksel_rate common_clkout_rates[] = { 323static const struct clksel_rate common_clkout_rates[] = {
324 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 324 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
325 { .div = 2, .val = 1, .flags = RATE_IN_24XX }, 325 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
326 { .div = 4, .val = 2, .flags = RATE_IN_24XX }, 326 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
327 { .div = 8, .val = 3, .flags = RATE_IN_24XX }, 327 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
@@ -369,7 +369,7 @@ static struct clk emul_ck = {
369 * 369 *
370 */ 370 */
371static const struct clksel_rate mpu_core_rates[] = { 371static const struct clksel_rate mpu_core_rates[] = {
372 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 372 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
373 { .div = 2, .val = 2, .flags = RATE_IN_24XX }, 373 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
374 { .div = 0 }, 374 { .div = 0 },
375}; 375};
@@ -402,7 +402,7 @@ static struct clk mpu_ck = { /* Control cpu */
402 * routed into a synchronizer and out of clocks abc. 402 * routed into a synchronizer and out of clocks abc.
403 */ 403 */
404static const struct clksel_rate dsp_fck_core_rates[] = { 404static const struct clksel_rate dsp_fck_core_rates[] = {
405 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 405 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
406 { .div = 2, .val = 2, .flags = RATE_IN_24XX }, 406 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
407 { .div = 3, .val = 3, .flags = RATE_IN_24XX }, 407 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
408 { .div = 4, .val = 4, .flags = RATE_IN_24XX }, 408 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
@@ -429,7 +429,7 @@ static struct clk dsp_fck = {
429 429
430/* DSP interface clock */ 430/* DSP interface clock */
431static const struct clksel_rate dsp_irate_ick_rates[] = { 431static const struct clksel_rate dsp_irate_ick_rates[] = {
432 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 432 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
433 { .div = 2, .val = 2, .flags = RATE_IN_24XX }, 433 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
434 { .div = 3, .val = 3, .flags = RATE_IN_243X }, 434 { .div = 3, .val = 3, .flags = RATE_IN_243X },
435 { .div = 0 }, 435 { .div = 0 },
@@ -481,7 +481,7 @@ static struct clk iva2_1_ick = {
481 */ 481 */
482static const struct clksel_rate core_l3_core_rates[] = { 482static const struct clksel_rate core_l3_core_rates[] = {
483 { .div = 1, .val = 1, .flags = RATE_IN_24XX }, 483 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
484 { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE }, 484 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
485 { .div = 6, .val = 6, .flags = RATE_IN_24XX }, 485 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
486 { .div = 0 } 486 { .div = 0 }
487}; 487};
@@ -505,7 +505,7 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
505/* usb_l4_ick */ 505/* usb_l4_ick */
506static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { 506static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
507 { .div = 1, .val = 1, .flags = RATE_IN_24XX }, 507 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
508 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, 508 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
509 { .div = 4, .val = 4, .flags = RATE_IN_24XX }, 509 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
510 { .div = 0 } 510 { .div = 0 }
511}; 511};
@@ -537,7 +537,7 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */
537 * this domain. 537 * this domain.
538 */ 538 */
539static const struct clksel_rate l4_core_l3_rates[] = { 539static const struct clksel_rate l4_core_l3_rates[] = {
540 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 540 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
541 { .div = 2, .val = 2, .flags = RATE_IN_24XX }, 541 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
542 { .div = 0 } 542 { .div = 0 }
543}; 543};
@@ -568,7 +568,7 @@ static struct clk l4_ck = { /* used both as an ick and fck */
568 */ 568 */
569static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { 569static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
570 { .div = 1, .val = 1, .flags = RATE_IN_24XX }, 570 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
571 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, 571 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
572 { .div = 3, .val = 3, .flags = RATE_IN_24XX }, 572 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
573 { .div = 4, .val = 4, .flags = RATE_IN_24XX }, 573 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
574 { .div = 5, .val = 5, .flags = RATE_IN_243X }, 574 { .div = 5, .val = 5, .flags = RATE_IN_243X },
@@ -673,7 +673,7 @@ static struct clk gfx_ick = {
673 */ 673 */
674static const struct clksel_rate mdm_ick_core_rates[] = { 674static const struct clksel_rate mdm_ick_core_rates[] = {
675 { .div = 1, .val = 1, .flags = RATE_IN_243X }, 675 { .div = 1, .val = 1, .flags = RATE_IN_243X },
676 { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE }, 676 { .div = 4, .val = 4, .flags = RATE_IN_243X },
677 { .div = 6, .val = 6, .flags = RATE_IN_243X }, 677 { .div = 6, .val = 6, .flags = RATE_IN_243X },
678 { .div = 9, .val = 9, .flags = RATE_IN_243X }, 678 { .div = 9, .val = 9, .flags = RATE_IN_243X },
679 { .div = 0 } 679 { .div = 0 }
@@ -718,7 +718,7 @@ static struct clk mdm_osc_ck = {
718/* XXX Add RATE_NOT_VALIDATED */ 718/* XXX Add RATE_NOT_VALIDATED */
719 719
720static const struct clksel_rate dss1_fck_sys_rates[] = { 720static const struct clksel_rate dss1_fck_sys_rates[] = {
721 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 721 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
722 { .div = 0 } 722 { .div = 0 }
723}; 723};
724 724
@@ -732,7 +732,7 @@ static const struct clksel_rate dss1_fck_core_rates[] = {
732 { .div = 8, .val = 8, .flags = RATE_IN_24XX }, 732 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
733 { .div = 9, .val = 9, .flags = RATE_IN_24XX }, 733 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
734 { .div = 12, .val = 12, .flags = RATE_IN_24XX }, 734 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
735 { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE }, 735 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
736 { .div = 0 } 736 { .div = 0 }
737}; 737};
738 738
@@ -767,12 +767,12 @@ static struct clk dss1_fck = {
767}; 767};
768 768
769static const struct clksel_rate dss2_fck_sys_rates[] = { 769static const struct clksel_rate dss2_fck_sys_rates[] = {
770 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 770 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
771 { .div = 0 } 771 { .div = 0 }
772}; 772};
773 773
774static const struct clksel_rate dss2_fck_48m_rates[] = { 774static const struct clksel_rate dss2_fck_48m_rates[] = {
775 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 775 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
776 { .div = 0 } 776 { .div = 0 }
777}; 777};
778 778
@@ -813,7 +813,7 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */
813 * functional clock parents. 813 * functional clock parents.
814 */ 814 */
815static const struct clksel_rate gpt_alt_rates[] = { 815static const struct clksel_rate gpt_alt_rates[] = {
816 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, 816 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
817 { .div = 0 } 817 { .div = 0 }
818}; 818};
819 819
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 9cba5560519b..833be485c89e 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -110,32 +110,32 @@ static struct clk virt_38_4m_ck = {
110}; 110};
111 111
112static const struct clksel_rate osc_sys_12m_rates[] = { 112static const struct clksel_rate osc_sys_12m_rates[] = {
113 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 113 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
114 { .div = 0 } 114 { .div = 0 }
115}; 115};
116 116
117static const struct clksel_rate osc_sys_13m_rates[] = { 117static const struct clksel_rate osc_sys_13m_rates[] = {
118 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 118 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
119 { .div = 0 } 119 { .div = 0 }
120}; 120};
121 121
122static const struct clksel_rate osc_sys_16_8m_rates[] = { 122static const struct clksel_rate osc_sys_16_8m_rates[] = {
123 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE }, 123 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS },
124 { .div = 0 } 124 { .div = 0 }
125}; 125};
126 126
127static const struct clksel_rate osc_sys_19_2m_rates[] = { 127static const struct clksel_rate osc_sys_19_2m_rates[] = {
128 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, 128 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
129 { .div = 0 } 129 { .div = 0 }
130}; 130};
131 131
132static const struct clksel_rate osc_sys_26m_rates[] = { 132static const struct clksel_rate osc_sys_26m_rates[] = {
133 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, 133 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
134 { .div = 0 } 134 { .div = 0 }
135}; 135};
136 136
137static const struct clksel_rate osc_sys_38_4m_rates[] = { 137static const struct clksel_rate osc_sys_38_4m_rates[] = {
138 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE }, 138 { .div = 1, .val = 4, .flags = RATE_IN_3XXX },
139 { .div = 0 } 139 { .div = 0 }
140}; 140};
141 141
@@ -163,8 +163,8 @@ static struct clk osc_sys_ck = {
163}; 163};
164 164
165static const struct clksel_rate div2_rates[] = { 165static const struct clksel_rate div2_rates[] = {
166 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 166 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
167 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 167 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
168 { .div = 0 } 168 { .div = 0 }
169}; 169};
170 170
@@ -213,42 +213,42 @@ static struct clk sys_clkout1 = {
213/* CM CLOCKS */ 213/* CM CLOCKS */
214 214
215static const struct clksel_rate div16_dpll_rates[] = { 215static const struct clksel_rate div16_dpll_rates[] = {
216 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 216 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
217 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 217 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
218 { .div = 3, .val = 3, .flags = RATE_IN_343X }, 218 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
219 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 219 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
220 { .div = 5, .val = 5, .flags = RATE_IN_343X }, 220 { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
221 { .div = 6, .val = 6, .flags = RATE_IN_343X }, 221 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
222 { .div = 7, .val = 7, .flags = RATE_IN_343X }, 222 { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
223 { .div = 8, .val = 8, .flags = RATE_IN_343X }, 223 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
224 { .div = 9, .val = 9, .flags = RATE_IN_343X }, 224 { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
225 { .div = 10, .val = 10, .flags = RATE_IN_343X }, 225 { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
226 { .div = 11, .val = 11, .flags = RATE_IN_343X }, 226 { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
227 { .div = 12, .val = 12, .flags = RATE_IN_343X }, 227 { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
228 { .div = 13, .val = 13, .flags = RATE_IN_343X }, 228 { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
229 { .div = 14, .val = 14, .flags = RATE_IN_343X }, 229 { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
230 { .div = 15, .val = 15, .flags = RATE_IN_343X }, 230 { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
231 { .div = 16, .val = 16, .flags = RATE_IN_343X }, 231 { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
232 { .div = 0 } 232 { .div = 0 }
233}; 233};
234 234
235static const struct clksel_rate div32_dpll4_rates_3630[] = { 235static const struct clksel_rate dpll4_rates[] = {
236 { .div = 1, .val = 1, .flags = RATE_IN_36XX | DEFAULT_RATE }, 236 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
237 { .div = 2, .val = 2, .flags = RATE_IN_36XX }, 237 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
238 { .div = 3, .val = 3, .flags = RATE_IN_36XX }, 238 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
239 { .div = 4, .val = 4, .flags = RATE_IN_36XX }, 239 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
240 { .div = 5, .val = 5, .flags = RATE_IN_36XX }, 240 { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
241 { .div = 6, .val = 6, .flags = RATE_IN_36XX }, 241 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
242 { .div = 7, .val = 7, .flags = RATE_IN_36XX }, 242 { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
243 { .div = 8, .val = 8, .flags = RATE_IN_36XX }, 243 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
244 { .div = 9, .val = 9, .flags = RATE_IN_36XX }, 244 { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
245 { .div = 10, .val = 10, .flags = RATE_IN_36XX }, 245 { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
246 { .div = 11, .val = 11, .flags = RATE_IN_36XX }, 246 { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
247 { .div = 12, .val = 12, .flags = RATE_IN_36XX }, 247 { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
248 { .div = 13, .val = 13, .flags = RATE_IN_36XX }, 248 { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
249 { .div = 14, .val = 14, .flags = RATE_IN_36XX }, 249 { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
250 { .div = 15, .val = 15, .flags = RATE_IN_36XX }, 250 { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
251 { .div = 16, .val = 16, .flags = RATE_IN_36XX }, 251 { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
252 { .div = 17, .val = 17, .flags = RATE_IN_36XX }, 252 { .div = 17, .val = 17, .flags = RATE_IN_36XX },
253 { .div = 18, .val = 18, .flags = RATE_IN_36XX }, 253 { .div = 18, .val = 18, .flags = RATE_IN_36XX },
254 { .div = 19, .val = 19, .flags = RATE_IN_36XX }, 254 { .div = 19, .val = 19, .flags = RATE_IN_36XX },
@@ -450,37 +450,37 @@ static struct clk dpll3_x2_ck = {
450}; 450};
451 451
452static const struct clksel_rate div31_dpll3_rates[] = { 452static const struct clksel_rate div31_dpll3_rates[] = {
453 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 453 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
454 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 454 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
455 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 }, 455 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS },
456 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 }, 456 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS },
457 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 }, 457 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS },
458 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 }, 458 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS },
459 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 }, 459 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS },
460 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 }, 460 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS },
461 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 }, 461 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS },
462 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 }, 462 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS },
463 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 }, 463 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS },
464 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 }, 464 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS },
465 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 }, 465 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS },
466 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 }, 466 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS },
467 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 }, 467 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS },
468 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 }, 468 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS },
469 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 }, 469 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS },
470 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 }, 470 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS },
471 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 }, 471 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS },
472 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 }, 472 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS },
473 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 }, 473 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS },
474 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 }, 474 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS },
475 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 }, 475 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS },
476 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 }, 476 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS },
477 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 }, 477 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS },
478 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 }, 478 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS },
479 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 }, 479 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS },
480 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 }, 480 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS },
481 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 }, 481 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS },
482 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 }, 482 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS },
483 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 }, 483 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS },
484 { .div = 0 }, 484 { .div = 0 },
485}; 485};
486 486
@@ -562,6 +562,7 @@ static struct clk emu_core_alwon_ck = {
562/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ 562/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
563/* Type: DPLL */ 563/* Type: DPLL */
564static struct dpll_data dpll4_dd; 564static struct dpll_data dpll4_dd;
565
565static struct dpll_data dpll4_dd_34xx __initdata = { 566static struct dpll_data dpll4_dd_34xx __initdata = {
566 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), 567 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
567 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, 568 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
@@ -632,39 +633,20 @@ static struct clk dpll4_x2_ck = {
632 .recalc = &omap3_clkoutx2_recalc, 633 .recalc = &omap3_clkoutx2_recalc,
633}; 634};
634 635
635static const struct clksel div16_dpll4_clksel[] = { 636static const struct clksel dpll4_clksel[] = {
636 { .parent = &dpll4_ck, .rates = div16_dpll_rates }, 637 { .parent = &dpll4_ck, .rates = dpll4_rates },
637 { .parent = NULL }
638};
639
640static const struct clksel div32_dpll4_clksel[] = {
641 { .parent = &dpll4_ck, .rates = div32_dpll4_rates_3630 },
642 { .parent = NULL } 638 { .parent = NULL }
643}; 639};
644 640
645/* This virtual clock is the source for dpll4_m2x2_ck */ 641/* This virtual clock is the source for dpll4_m2x2_ck */
646static struct clk dpll4_m2_ck; 642static struct clk dpll4_m2_ck = {
647
648static struct clk dpll4_m2_ck_34xx __initdata = {
649 .name = "dpll4_m2_ck",
650 .ops = &clkops_null,
651 .parent = &dpll4_ck,
652 .init = &omap2_init_clksel_parent,
653 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
654 .clksel_mask = OMAP3430_DIV_96M_MASK,
655 .clksel = div16_dpll4_clksel,
656 .clkdm_name = "dpll4_clkdm",
657 .recalc = &omap2_clksel_recalc,
658};
659
660static struct clk dpll4_m2_ck_3630 __initdata = {
661 .name = "dpll4_m2_ck", 643 .name = "dpll4_m2_ck",
662 .ops = &clkops_null, 644 .ops = &clkops_null,
663 .parent = &dpll4_ck, 645 .parent = &dpll4_ck,
664 .init = &omap2_init_clksel_parent, 646 .init = &omap2_init_clksel_parent,
665 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), 647 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
666 .clksel_mask = OMAP3630_DIV_96M_MASK, 648 .clksel_mask = OMAP3630_DIV_96M_MASK,
667 .clksel = div32_dpll4_clksel, 649 .clksel = dpll4_clksel,
668 .clkdm_name = "dpll4_clkdm", 650 .clkdm_name = "dpll4_clkdm",
669 .recalc = &omap2_clksel_recalc, 651 .recalc = &omap2_clksel_recalc,
670}; 652};
@@ -698,7 +680,7 @@ static struct clk omap_192m_alwon_fck = {
698 680
699static const struct clksel_rate omap_96m_alwon_fck_rates[] = { 681static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
700 { .div = 1, .val = 1, .flags = RATE_IN_36XX }, 682 { .div = 1, .val = 1, .flags = RATE_IN_36XX },
701 { .div = 2, .val = 2, .flags = RATE_IN_36XX | DEFAULT_RATE }, 683 { .div = 2, .val = 2, .flags = RATE_IN_36XX },
702 { .div = 0 } 684 { .div = 0 }
703}; 685};
704 686
@@ -708,12 +690,12 @@ static const struct clksel omap_96m_alwon_fck_clksel[] = {
708}; 690};
709 691
710static const struct clksel_rate omap_96m_dpll_rates[] = { 692static const struct clksel_rate omap_96m_dpll_rates[] = {
711 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 693 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
712 { .div = 0 } 694 { .div = 0 }
713}; 695};
714 696
715static const struct clksel_rate omap_96m_sys_rates[] = { 697static const struct clksel_rate omap_96m_sys_rates[] = {
716 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 698 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
717 { .div = 0 } 699 { .div = 0 }
718}; 700};
719 701
@@ -760,28 +742,14 @@ static struct clk omap_96m_fck = {
760}; 742};
761 743
762/* This virtual clock is the source for dpll4_m3x2_ck */ 744/* This virtual clock is the source for dpll4_m3x2_ck */
763static struct clk dpll4_m3_ck; 745static struct clk dpll4_m3_ck = {
764
765static struct clk dpll4_m3_ck_34xx __initdata = {
766 .name = "dpll4_m3_ck", 746 .name = "dpll4_m3_ck",
767 .ops = &clkops_null, 747 .ops = &clkops_null,
768 .parent = &dpll4_ck, 748 .parent = &dpll4_ck,
769 .init = &omap2_init_clksel_parent, 749 .init = &omap2_init_clksel_parent,
770 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), 750 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
771 .clksel_mask = OMAP3430_CLKSEL_TV_MASK, 751 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
772 .clksel = div16_dpll4_clksel, 752 .clksel = dpll4_clksel,
773 .clkdm_name = "dpll4_clkdm",
774 .recalc = &omap2_clksel_recalc,
775};
776
777static struct clk dpll4_m3_ck_3630 __initdata = {
778 .name = "dpll4_m3_ck",
779 .ops = &clkops_null,
780 .parent = &dpll4_ck,
781 .init = &omap2_init_clksel_parent,
782 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
783 .clksel_mask = OMAP3630_CLKSEL_TV_MASK,
784 .clksel = div32_dpll4_clksel,
785 .clkdm_name = "dpll4_clkdm", 753 .clkdm_name = "dpll4_clkdm",
786 .recalc = &omap2_clksel_recalc, 754 .recalc = &omap2_clksel_recalc,
787}; 755};
@@ -799,12 +767,12 @@ static struct clk dpll4_m3x2_ck = {
799}; 767};
800 768
801static const struct clksel_rate omap_54m_d4m3x2_rates[] = { 769static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
802 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 770 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
803 { .div = 0 } 771 { .div = 0 }
804}; 772};
805 773
806static const struct clksel_rate omap_54m_alt_rates[] = { 774static const struct clksel_rate omap_54m_alt_rates[] = {
807 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 775 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
808 { .div = 0 } 776 { .div = 0 }
809}; 777};
810 778
@@ -825,12 +793,12 @@ static struct clk omap_54m_fck = {
825}; 793};
826 794
827static const struct clksel_rate omap_48m_cm96m_rates[] = { 795static const struct clksel_rate omap_48m_cm96m_rates[] = {
828 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 796 { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
829 { .div = 0 } 797 { .div = 0 }
830}; 798};
831 799
832static const struct clksel_rate omap_48m_alt_rates[] = { 800static const struct clksel_rate omap_48m_alt_rates[] = {
833 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 801 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
834 { .div = 0 } 802 { .div = 0 }
835}; 803};
836 804
@@ -858,31 +826,15 @@ static struct clk omap_12m_fck = {
858 .recalc = &omap_fixed_divisor_recalc, 826 .recalc = &omap_fixed_divisor_recalc,
859}; 827};
860 828
861/* This virstual clock is the source for dpll4_m4x2_ck */ 829/* This virtual clock is the source for dpll4_m4x2_ck */
862static struct clk dpll4_m4_ck; 830static struct clk dpll4_m4_ck = {
863
864static struct clk dpll4_m4_ck_34xx __initdata = {
865 .name = "dpll4_m4_ck", 831 .name = "dpll4_m4_ck",
866 .ops = &clkops_null, 832 .ops = &clkops_null,
867 .parent = &dpll4_ck, 833 .parent = &dpll4_ck,
868 .init = &omap2_init_clksel_parent, 834 .init = &omap2_init_clksel_parent,
869 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), 835 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
870 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, 836 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
871 .clksel = div16_dpll4_clksel, 837 .clksel = dpll4_clksel,
872 .clkdm_name = "dpll4_clkdm",
873 .recalc = &omap2_clksel_recalc,
874 .set_rate = &omap2_clksel_set_rate,
875 .round_rate = &omap2_clksel_round_rate,
876};
877
878static struct clk dpll4_m4_ck_3630 __initdata = {
879 .name = "dpll4_m4_ck",
880 .ops = &clkops_null,
881 .parent = &dpll4_ck,
882 .init = &omap2_init_clksel_parent,
883 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
884 .clksel_mask = OMAP3630_CLKSEL_DSS1_MASK,
885 .clksel = div32_dpll4_clksel,
886 .clkdm_name = "dpll4_clkdm", 838 .clkdm_name = "dpll4_clkdm",
887 .recalc = &omap2_clksel_recalc, 839 .recalc = &omap2_clksel_recalc,
888 .set_rate = &omap2_clksel_set_rate, 840 .set_rate = &omap2_clksel_set_rate,
@@ -902,30 +854,14 @@ static struct clk dpll4_m4x2_ck = {
902}; 854};
903 855
904/* This virtual clock is the source for dpll4_m5x2_ck */ 856/* This virtual clock is the source for dpll4_m5x2_ck */
905static struct clk dpll4_m5_ck; 857static struct clk dpll4_m5_ck = {
906
907static struct clk dpll4_m5_ck_34xx __initdata = {
908 .name = "dpll4_m5_ck", 858 .name = "dpll4_m5_ck",
909 .ops = &clkops_null, 859 .ops = &clkops_null,
910 .parent = &dpll4_ck, 860 .parent = &dpll4_ck,
911 .init = &omap2_init_clksel_parent, 861 .init = &omap2_init_clksel_parent,
912 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), 862 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
913 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, 863 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
914 .clksel = div16_dpll4_clksel, 864 .clksel = dpll4_clksel,
915 .clkdm_name = "dpll4_clkdm",
916 .set_rate = &omap2_clksel_set_rate,
917 .round_rate = &omap2_clksel_round_rate,
918 .recalc = &omap2_clksel_recalc,
919};
920
921static struct clk dpll4_m5_ck_3630 __initdata = {
922 .name = "dpll4_m5_ck",
923 .ops = &clkops_null,
924 .parent = &dpll4_ck,
925 .init = &omap2_init_clksel_parent,
926 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
927 .clksel_mask = OMAP3630_CLKSEL_CAM_MASK,
928 .clksel = div32_dpll4_clksel,
929 .clkdm_name = "dpll4_clkdm", 865 .clkdm_name = "dpll4_clkdm",
930 .set_rate = &omap2_clksel_set_rate, 866 .set_rate = &omap2_clksel_set_rate,
931 .round_rate = &omap2_clksel_round_rate, 867 .round_rate = &omap2_clksel_round_rate,
@@ -945,28 +881,14 @@ static struct clk dpll4_m5x2_ck = {
945}; 881};
946 882
947/* This virtual clock is the source for dpll4_m6x2_ck */ 883/* This virtual clock is the source for dpll4_m6x2_ck */
948static struct clk dpll4_m6_ck; 884static struct clk dpll4_m6_ck = {
949
950static struct clk dpll4_m6_ck_34xx __initdata = {
951 .name = "dpll4_m6_ck", 885 .name = "dpll4_m6_ck",
952 .ops = &clkops_null, 886 .ops = &clkops_null,
953 .parent = &dpll4_ck, 887 .parent = &dpll4_ck,
954 .init = &omap2_init_clksel_parent, 888 .init = &omap2_init_clksel_parent,
955 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 889 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
956 .clksel_mask = OMAP3430_DIV_DPLL4_MASK, 890 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
957 .clksel = div16_dpll4_clksel, 891 .clksel = dpll4_clksel,
958 .clkdm_name = "dpll4_clkdm",
959 .recalc = &omap2_clksel_recalc,
960};
961
962static struct clk dpll4_m6_ck_3630 __initdata = {
963 .name = "dpll4_m6_ck",
964 .ops = &clkops_null,
965 .parent = &dpll4_ck,
966 .init = &omap2_init_clksel_parent,
967 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
968 .clksel_mask = OMAP3630_DIV_DPLL4_MASK,
969 .clksel = div32_dpll4_clksel,
970 .clkdm_name = "dpll4_clkdm", 892 .clkdm_name = "dpll4_clkdm",
971 .recalc = &omap2_clksel_recalc, 893 .recalc = &omap2_clksel_recalc,
972}; 894};
@@ -1049,22 +971,22 @@ static struct clk dpll5_m2_ck = {
1049/* CM EXTERNAL CLOCK OUTPUTS */ 971/* CM EXTERNAL CLOCK OUTPUTS */
1050 972
1051static const struct clksel_rate clkout2_src_core_rates[] = { 973static const struct clksel_rate clkout2_src_core_rates[] = {
1052 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 974 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1053 { .div = 0 } 975 { .div = 0 }
1054}; 976};
1055 977
1056static const struct clksel_rate clkout2_src_sys_rates[] = { 978static const struct clksel_rate clkout2_src_sys_rates[] = {
1057 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 979 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1058 { .div = 0 } 980 { .div = 0 }
1059}; 981};
1060 982
1061static const struct clksel_rate clkout2_src_96m_rates[] = { 983static const struct clksel_rate clkout2_src_96m_rates[] = {
1062 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, 984 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
1063 { .div = 0 } 985 { .div = 0 }
1064}; 986};
1065 987
1066static const struct clksel_rate clkout2_src_54m_rates[] = { 988static const struct clksel_rate clkout2_src_54m_rates[] = {
1067 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, 989 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
1068 { .div = 0 } 990 { .div = 0 }
1069}; 991};
1070 992
@@ -1090,11 +1012,11 @@ static struct clk clkout2_src_ck = {
1090}; 1012};
1091 1013
1092static const struct clksel_rate sys_clkout2_rates[] = { 1014static const struct clksel_rate sys_clkout2_rates[] = {
1093 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 1015 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1094 { .div = 2, .val = 1, .flags = RATE_IN_343X }, 1016 { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1095 { .div = 4, .val = 2, .flags = RATE_IN_343X }, 1017 { .div = 4, .val = 2, .flags = RATE_IN_3XXX },
1096 { .div = 8, .val = 3, .flags = RATE_IN_343X }, 1018 { .div = 8, .val = 3, .flags = RATE_IN_3XXX },
1097 { .div = 16, .val = 4, .flags = RATE_IN_343X }, 1019 { .div = 16, .val = 4, .flags = RATE_IN_3XXX },
1098 { .div = 0 }, 1020 { .div = 0 },
1099}; 1021};
1100 1022
@@ -1111,6 +1033,8 @@ static struct clk sys_clkout2 = {
1111 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, 1033 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
1112 .clksel = sys_clkout2_clksel, 1034 .clksel = sys_clkout2_clksel,
1113 .recalc = &omap2_clksel_recalc, 1035 .recalc = &omap2_clksel_recalc,
1036 .round_rate = &omap2_clksel_round_rate,
1037 .set_rate = &omap2_clksel_set_rate
1114}; 1038};
1115 1039
1116/* CM OUTPUT CLOCKS */ 1040/* CM OUTPUT CLOCKS */
@@ -1125,9 +1049,9 @@ static struct clk corex2_fck = {
1125/* DPLL power domain clock controls */ 1049/* DPLL power domain clock controls */
1126 1050
1127static const struct clksel_rate div4_rates[] = { 1051static const struct clksel_rate div4_rates[] = {
1128 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 1052 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1129 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 1053 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1130 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 1054 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1131 { .div = 0 } 1055 { .div = 0 }
1132}; 1056};
1133 1057
@@ -1161,8 +1085,8 @@ static struct clk mpu_ck = {
1161 1085
1162/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ 1086/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1163static const struct clksel_rate arm_fck_rates[] = { 1087static const struct clksel_rate arm_fck_rates[] = {
1164 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 1088 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1165 { .div = 2, .val = 1, .flags = RATE_IN_343X }, 1089 { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1166 { .div = 0 }, 1090 { .div = 0 },
1167}; 1091};
1168 1092
@@ -1333,25 +1257,25 @@ static struct clk gfx_cg2_ck = {
1333 1257
1334static const struct clksel_rate sgx_core_rates[] = { 1258static const struct clksel_rate sgx_core_rates[] = {
1335 { .div = 2, .val = 5, .flags = RATE_IN_36XX }, 1259 { .div = 2, .val = 5, .flags = RATE_IN_36XX },
1336 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 1260 { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
1337 { .div = 4, .val = 1, .flags = RATE_IN_343X }, 1261 { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
1338 { .div = 6, .val = 2, .flags = RATE_IN_343X }, 1262 { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
1339 { .div = 0 }, 1263 { .div = 0 },
1340}; 1264};
1341 1265
1342static const struct clksel_rate sgx_192m_rates[] = { 1266static const struct clksel_rate sgx_192m_rates[] = {
1343 { .div = 1, .val = 4, .flags = RATE_IN_36XX | DEFAULT_RATE }, 1267 { .div = 1, .val = 4, .flags = RATE_IN_36XX },
1344 { .div = 0 }, 1268 { .div = 0 },
1345}; 1269};
1346 1270
1347static const struct clksel_rate sgx_corex2_rates[] = { 1271static const struct clksel_rate sgx_corex2_rates[] = {
1348 { .div = 3, .val = 6, .flags = RATE_IN_36XX | DEFAULT_RATE }, 1272 { .div = 3, .val = 6, .flags = RATE_IN_36XX },
1349 { .div = 5, .val = 7, .flags = RATE_IN_36XX }, 1273 { .div = 5, .val = 7, .flags = RATE_IN_36XX },
1350 { .div = 0 }, 1274 { .div = 0 },
1351}; 1275};
1352 1276
1353static const struct clksel_rate sgx_96m_rates[] = { 1277static const struct clksel_rate sgx_96m_rates[] = {
1354 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, 1278 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
1355 { .div = 0 }, 1279 { .div = 0 },
1356}; 1280};
1357 1281
@@ -1576,12 +1500,12 @@ static struct clk i2c1_fck = {
1576 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. 1500 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1577 */ 1501 */
1578static const struct clksel_rate common_mcbsp_96m_rates[] = { 1502static const struct clksel_rate common_mcbsp_96m_rates[] = {
1579 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 1503 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1580 { .div = 0 } 1504 { .div = 0 }
1581}; 1505};
1582 1506
1583static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { 1507static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1584 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 1508 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1585 { .div = 0 } 1509 { .div = 0 }
1586}; 1510};
1587 1511
@@ -1714,12 +1638,12 @@ static struct clk hdq_fck = {
1714/* DPLL3-derived clock */ 1638/* DPLL3-derived clock */
1715 1639
1716static const struct clksel_rate ssi_ssr_corex2_rates[] = { 1640static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1717 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 1641 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1718 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 1642 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1719 { .div = 3, .val = 3, .flags = RATE_IN_343X }, 1643 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
1720 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 1644 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1721 { .div = 6, .val = 6, .flags = RATE_IN_343X }, 1645 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
1722 { .div = 8, .val = 8, .flags = RATE_IN_343X }, 1646 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
1723 { .div = 0 } 1647 { .div = 0 }
1724}; 1648};
1725 1649
@@ -2353,18 +2277,18 @@ static struct clk usbhost_ick = {
2353/* WKUP */ 2277/* WKUP */
2354 2278
2355static const struct clksel_rate usim_96m_rates[] = { 2279static const struct clksel_rate usim_96m_rates[] = {
2356 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, 2280 { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
2357 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 2281 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2358 { .div = 8, .val = 5, .flags = RATE_IN_343X }, 2282 { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
2359 { .div = 10, .val = 6, .flags = RATE_IN_343X }, 2283 { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
2360 { .div = 0 }, 2284 { .div = 0 },
2361}; 2285};
2362 2286
2363static const struct clksel_rate usim_120m_rates[] = { 2287static const struct clksel_rate usim_120m_rates[] = {
2364 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE }, 2288 { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
2365 { .div = 8, .val = 8, .flags = RATE_IN_343X }, 2289 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
2366 { .div = 16, .val = 9, .flags = RATE_IN_343X }, 2290 { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
2367 { .div = 20, .val = 10, .flags = RATE_IN_343X }, 2291 { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
2368 { .div = 0 }, 2292 { .div = 0 },
2369}; 2293};
2370 2294
@@ -2951,22 +2875,22 @@ static struct clk mcbsp4_fck = {
2951/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ 2875/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2952 2876
2953static const struct clksel_rate emu_src_sys_rates[] = { 2877static const struct clksel_rate emu_src_sys_rates[] = {
2954 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 2878 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2955 { .div = 0 }, 2879 { .div = 0 },
2956}; 2880};
2957 2881
2958static const struct clksel_rate emu_src_core_rates[] = { 2882static const struct clksel_rate emu_src_core_rates[] = {
2959 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 2883 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2960 { .div = 0 }, 2884 { .div = 0 },
2961}; 2885};
2962 2886
2963static const struct clksel_rate emu_src_per_rates[] = { 2887static const struct clksel_rate emu_src_per_rates[] = {
2964 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, 2888 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
2965 { .div = 0 }, 2889 { .div = 0 },
2966}; 2890};
2967 2891
2968static const struct clksel_rate emu_src_mpu_rates[] = { 2892static const struct clksel_rate emu_src_mpu_rates[] = {
2969 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, 2893 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2970 { .div = 0 }, 2894 { .div = 0 },
2971}; 2895};
2972 2896
@@ -2995,10 +2919,10 @@ static struct clk emu_src_ck = {
2995}; 2919};
2996 2920
2997static const struct clksel_rate pclk_emu_rates[] = { 2921static const struct clksel_rate pclk_emu_rates[] = {
2998 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, 2922 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2999 { .div = 3, .val = 3, .flags = RATE_IN_343X }, 2923 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
3000 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 2924 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3001 { .div = 6, .val = 6, .flags = RATE_IN_343X }, 2925 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
3002 { .div = 0 }, 2926 { .div = 0 },
3003}; 2927};
3004 2928
@@ -3019,9 +2943,9 @@ static struct clk pclk_fck = {
3019}; 2943};
3020 2944
3021static const struct clksel_rate pclkx2_emu_rates[] = { 2945static const struct clksel_rate pclkx2_emu_rates[] = {
3022 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 2946 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
3023 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 2947 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
3024 { .div = 3, .val = 3, .flags = RATE_IN_343X }, 2948 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
3025 { .div = 0 }, 2949 { .div = 0 },
3026}; 2950};
3027 2951
@@ -3069,9 +2993,9 @@ static struct clk traceclk_src_fck = {
3069}; 2993};
3070 2994
3071static const struct clksel_rate traceclk_rates[] = { 2995static const struct clksel_rate traceclk_rates[] = {
3072 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 2996 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
3073 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 2997 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
3074 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 2998 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3075 { .div = 0 }, 2999 { .div = 0 },
3076}; 3000};
3077 3001
@@ -3472,8 +3396,8 @@ static struct omap_clk omap3xxx_clks[] = {
3472 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX), 3396 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
3473 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX), 3397 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
3474 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX), 3398 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
3475 CLK("davinci_emac", "ick", &emac_ick, CK_AM35XX), 3399 CLK("davinci_emac", "emac_clk", &emac_ick, CK_AM35XX),
3476 CLK("davinci_emac", "fck", &emac_fck, CK_AM35XX), 3400 CLK("davinci_emac", "phy_clk", &emac_fck, CK_AM35XX),
3477 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), 3401 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
3478 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), 3402 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
3479 CLK("musb_hdrc", "ick", &hsotgusb_ick_am35xx, CK_AM35XX), 3403 CLK("musb_hdrc", "ick", &hsotgusb_ick_am35xx, CK_AM35XX),
@@ -3488,14 +3412,8 @@ int __init omap3xxx_clk_init(void)
3488 struct omap_clk *c; 3412 struct omap_clk *c;
3489 u32 cpu_clkflg = CK_3XXX; 3413 u32 cpu_clkflg = CK_3XXX;
3490 3414
3491 if (cpu_is_omap3517()) { 3415 if (cpu_is_omap34xx()) {
3492 cpu_mask = RATE_IN_343X | RATE_IN_3430ES2; 3416 cpu_mask = RATE_IN_3XXX;
3493 cpu_clkflg |= CK_3517;
3494 } else if (cpu_is_omap3505()) {
3495 cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
3496 cpu_clkflg |= CK_3505;
3497 } else if (cpu_is_omap34xx()) {
3498 cpu_mask = RATE_IN_343X;
3499 cpu_clkflg |= CK_343X; 3417 cpu_clkflg |= CK_343X;
3500 3418
3501 /* 3419 /*
@@ -3506,10 +3424,17 @@ int __init omap3xxx_clk_init(void)
3506 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ 3424 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
3507 cpu_clkflg |= CK_3430ES1; 3425 cpu_clkflg |= CK_3430ES1;
3508 } else { 3426 } else {
3509 cpu_mask |= RATE_IN_3430ES2; 3427 cpu_mask |= RATE_IN_3430ES2PLUS;
3510 cpu_clkflg |= CK_3430ES2; 3428 cpu_clkflg |= CK_3430ES2;
3511 } 3429 }
3430 } else if (cpu_is_omap3517()) {
3431 cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
3432 cpu_clkflg |= CK_3517;
3433 } else if (cpu_is_omap3505()) {
3434 cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
3435 cpu_clkflg |= CK_3505;
3512 } 3436 }
3437
3513 if (omap3_has_192mhz_clk()) 3438 if (omap3_has_192mhz_clk())
3514 omap_96m_alwon_fck = omap_96m_alwon_fck_3630; 3439 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3515 3440
@@ -3520,14 +3445,7 @@ int __init omap3xxx_clk_init(void)
3520 /* 3445 /*
3521 * XXX This type of dynamic rewriting of the clock tree is 3446 * XXX This type of dynamic rewriting of the clock tree is
3522 * deprecated and should be revised soon. 3447 * deprecated and should be revised soon.
3523 */ 3448 *
3524 dpll4_m2_ck = dpll4_m2_ck_3630;
3525 dpll4_m3_ck = dpll4_m3_ck_3630;
3526 dpll4_m4_ck = dpll4_m4_ck_3630;
3527 dpll4_m5_ck = dpll4_m5_ck_3630;
3528 dpll4_m6_ck = dpll4_m6_ck_3630;
3529
3530 /*
3531 * For 3630: override clkops_omap2_dflt_wait for the 3449 * For 3630: override clkops_omap2_dflt_wait for the
3532 * clocks affected from PWRDN reset Limitation 3450 * clocks affected from PWRDN reset Limitation
3533 */ 3451 */
@@ -3543,18 +3461,12 @@ int __init omap3xxx_clk_init(void)
3543 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; 3461 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3544 dpll4_m6x2_ck.ops = 3462 dpll4_m6x2_ck.ops =
3545 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; 3463 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3546 } else {
3547 /*
3548 * XXX This type of dynamic rewriting of the clock tree is
3549 * deprecated and should be revised soon.
3550 */
3551 dpll4_m2_ck = dpll4_m2_ck_34xx;
3552 dpll4_m3_ck = dpll4_m3_ck_34xx;
3553 dpll4_m4_ck = dpll4_m4_ck_34xx;
3554 dpll4_m5_ck = dpll4_m5_ck_34xx;
3555 dpll4_m6_ck = dpll4_m6_ck_34xx;
3556 } 3464 }
3557 3465
3466 /*
3467 * XXX This type of dynamic rewriting of the clock tree is
3468 * deprecated and should be revised soon.
3469 */
3558 if (cpu_is_omap3630()) 3470 if (cpu_is_omap3630())
3559 dpll4_dd = dpll4_dd_3630; 3471 dpll4_dd = dpll4_dd_3630;
3560 else 3472 else
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index a5c0c9c8e496..02804224517b 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -2675,6 +2675,11 @@ static struct omap_clk omap44xx_clks[] = {
2675 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), 2675 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X),
2676 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), 2676 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X),
2677 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), 2677 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X),
2678 CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X),
2679 CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X),
2680 CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X),
2681 CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X),
2682 CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X),
2678 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), 2683 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X),
2679 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), 2684 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
2680 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), 2685 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c
index f69096b88cdb..1cf8131205fa 100644
--- a/arch/arm/mach-omap2/clock_common_data.c
+++ b/arch/arm/mach-omap2/clock_common_data.c
@@ -20,20 +20,20 @@
20 20
21/* clksel_rate data common to 24xx/343x */ 21/* clksel_rate data common to 24xx/343x */
22const struct clksel_rate gpt_32k_rates[] = { 22const struct clksel_rate gpt_32k_rates[] = {
23 { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, 23 { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_3XXX },
24 { .div = 0 } 24 { .div = 0 }
25}; 25};
26 26
27const struct clksel_rate gpt_sys_rates[] = { 27const struct clksel_rate gpt_sys_rates[] = {
28 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, 28 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX },
29 { .div = 0 } 29 { .div = 0 }
30}; 30};
31 31
32const struct clksel_rate gfx_l3_rates[] = { 32const struct clksel_rate gfx_l3_rates[] = {
33 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X }, 33 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX },
34 { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, 34 { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_3XXX },
35 { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X }, 35 { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_3XXX },
36 { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X }, 36 { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_3XXX },
37 { .div = 0 } 37 { .div = 0 }
38}; 38};
39 39
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 6e568ec995ee..5d80cb897489 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -809,7 +809,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
809 809
810 if (cpu_is_omap24xx()) { 810 if (cpu_is_omap24xx()) {
811 811
812 cm_set_mod_reg_bits(OMAP24XX_FORCESTATE, 812 cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
813 clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); 813 clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
814 814
815 } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 815 } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
@@ -853,7 +853,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
853 853
854 if (cpu_is_omap24xx()) { 854 if (cpu_is_omap24xx()) {
855 855
856 cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE, 856 cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
857 clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); 857 clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
858 858
859 } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 859 } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
diff --git a/arch/arm/mach-omap2/clockdomains44xx.h b/arch/arm/mach-omap2/clockdomains44xx.h
index 438aaee2e392..7e5ba0f67925 100644
--- a/arch/arm/mach-omap2/clockdomains44xx.h
+++ b/arch/arm/mach-omap2/clockdomains44xx.h
@@ -131,7 +131,7 @@ static struct clockdomain mpuss_44xx_clkdm = {
131static struct clockdomain mpu0_44xx_clkdm = { 131static struct clockdomain mpu0_44xx_clkdm = {
132 .name = "mpu0_clkdm", 132 .name = "mpu0_clkdm",
133 .pwrdm = { .name = "cpu0_pwrdm" }, 133 .pwrdm = { .name = "cpu0_pwrdm" },
134 .clkstctrl_reg = OMAP4430_CM_PDA_CPU0_CLKSTCTRL, 134 .clkstctrl_reg = OMAP4430_CM_CPU0_CLKSTCTRL,
135 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, 135 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
136 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 136 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
137 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 137 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -140,7 +140,7 @@ static struct clockdomain mpu0_44xx_clkdm = {
140static struct clockdomain mpu1_44xx_clkdm = { 140static struct clockdomain mpu1_44xx_clkdm = {
141 .name = "mpu1_clkdm", 141 .name = "mpu1_clkdm",
142 .pwrdm = { .name = "cpu1_pwrdm" }, 142 .pwrdm = { .name = "cpu1_pwrdm" },
143 .clkstctrl_reg = OMAP4430_CM_PDA_CPU1_CLKSTCTRL, 143 .clkstctrl_reg = OMAP4430_CM_CPU1_CLKSTCTRL,
144 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, 144 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
145 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 145 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
146 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 146 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index 297a2fe634ea..da51cc3ed7eb 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -20,43 +20,43 @@
20 20
21/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ 21/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
22#define OMAP24XX_EN_CAM_SHIFT 31 22#define OMAP24XX_EN_CAM_SHIFT 31
23#define OMAP24XX_EN_CAM (1 << 31) 23#define OMAP24XX_EN_CAM_MASK (1 << 31)
24#define OMAP24XX_EN_WDT4_SHIFT 29 24#define OMAP24XX_EN_WDT4_SHIFT 29
25#define OMAP24XX_EN_WDT4 (1 << 29) 25#define OMAP24XX_EN_WDT4_MASK (1 << 29)
26#define OMAP2420_EN_WDT3_SHIFT 28 26#define OMAP2420_EN_WDT3_SHIFT 28
27#define OMAP2420_EN_WDT3 (1 << 28) 27#define OMAP2420_EN_WDT3_MASK (1 << 28)
28#define OMAP24XX_EN_MSPRO_SHIFT 27 28#define OMAP24XX_EN_MSPRO_SHIFT 27
29#define OMAP24XX_EN_MSPRO (1 << 27) 29#define OMAP24XX_EN_MSPRO_MASK (1 << 27)
30#define OMAP24XX_EN_FAC_SHIFT 25 30#define OMAP24XX_EN_FAC_SHIFT 25
31#define OMAP24XX_EN_FAC (1 << 25) 31#define OMAP24XX_EN_FAC_MASK (1 << 25)
32#define OMAP2420_EN_EAC_SHIFT 24 32#define OMAP2420_EN_EAC_SHIFT 24
33#define OMAP2420_EN_EAC (1 << 24) 33#define OMAP2420_EN_EAC_MASK (1 << 24)
34#define OMAP24XX_EN_HDQ_SHIFT 23 34#define OMAP24XX_EN_HDQ_SHIFT 23
35#define OMAP24XX_EN_HDQ (1 << 23) 35#define OMAP24XX_EN_HDQ_MASK (1 << 23)
36#define OMAP2420_EN_I2C2_SHIFT 20 36#define OMAP2420_EN_I2C2_SHIFT 20
37#define OMAP2420_EN_I2C2 (1 << 20) 37#define OMAP2420_EN_I2C2_MASK (1 << 20)
38#define OMAP2420_EN_I2C1_SHIFT 19 38#define OMAP2420_EN_I2C1_SHIFT 19
39#define OMAP2420_EN_I2C1 (1 << 19) 39#define OMAP2420_EN_I2C1_MASK (1 << 19)
40 40
41/* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */ 41/* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */
42#define OMAP2430_EN_MCBSP5_SHIFT 5 42#define OMAP2430_EN_MCBSP5_SHIFT 5
43#define OMAP2430_EN_MCBSP5 (1 << 5) 43#define OMAP2430_EN_MCBSP5_MASK (1 << 5)
44#define OMAP2430_EN_MCBSP4_SHIFT 4 44#define OMAP2430_EN_MCBSP4_SHIFT 4
45#define OMAP2430_EN_MCBSP4 (1 << 4) 45#define OMAP2430_EN_MCBSP4_MASK (1 << 4)
46#define OMAP2430_EN_MCBSP3_SHIFT 3 46#define OMAP2430_EN_MCBSP3_SHIFT 3
47#define OMAP2430_EN_MCBSP3 (1 << 3) 47#define OMAP2430_EN_MCBSP3_MASK (1 << 3)
48#define OMAP24XX_EN_SSI_SHIFT 1 48#define OMAP24XX_EN_SSI_SHIFT 1
49#define OMAP24XX_EN_SSI (1 << 1) 49#define OMAP24XX_EN_SSI_MASK (1 << 1)
50 50
51/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ 51/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
52#define OMAP24XX_EN_MPU_WDT_SHIFT 3 52#define OMAP24XX_EN_MPU_WDT_SHIFT 3
53#define OMAP24XX_EN_MPU_WDT (1 << 3) 53#define OMAP24XX_EN_MPU_WDT_MASK (1 << 3)
54 54
55/* Bits specific to each register */ 55/* Bits specific to each register */
56 56
57/* CM_IDLEST_MPU */ 57/* CM_IDLEST_MPU */
58/* 2430 only */ 58/* 2430 only */
59#define OMAP2430_ST_MPU (1 << 0) 59#define OMAP2430_ST_MPU_MASK (1 << 0)
60 60
61/* CM_CLKSEL_MPU */ 61/* CM_CLKSEL_MPU */
62#define OMAP24XX_CLKSEL_MPU_SHIFT 0 62#define OMAP24XX_CLKSEL_MPU_SHIFT 0
@@ -68,46 +68,46 @@
68 68
69/* CM_FCLKEN1_CORE specific bits*/ 69/* CM_FCLKEN1_CORE specific bits*/
70#define OMAP24XX_EN_TV_SHIFT 2 70#define OMAP24XX_EN_TV_SHIFT 2
71#define OMAP24XX_EN_TV (1 << 2) 71#define OMAP24XX_EN_TV_MASK (1 << 2)
72#define OMAP24XX_EN_DSS2_SHIFT 1 72#define OMAP24XX_EN_DSS2_SHIFT 1
73#define OMAP24XX_EN_DSS2 (1 << 1) 73#define OMAP24XX_EN_DSS2_MASK (1 << 1)
74#define OMAP24XX_EN_DSS1_SHIFT 0 74#define OMAP24XX_EN_DSS1_SHIFT 0
75#define OMAP24XX_EN_DSS1 (1 << 0) 75#define OMAP24XX_EN_DSS1_MASK (1 << 0)
76 76
77/* CM_FCLKEN2_CORE specific bits */ 77/* CM_FCLKEN2_CORE specific bits */
78#define OMAP2430_EN_I2CHS2_SHIFT 20 78#define OMAP2430_EN_I2CHS2_SHIFT 20
79#define OMAP2430_EN_I2CHS2 (1 << 20) 79#define OMAP2430_EN_I2CHS2_MASK (1 << 20)
80#define OMAP2430_EN_I2CHS1_SHIFT 19 80#define OMAP2430_EN_I2CHS1_SHIFT 19
81#define OMAP2430_EN_I2CHS1 (1 << 19) 81#define OMAP2430_EN_I2CHS1_MASK (1 << 19)
82#define OMAP2430_EN_MMCHSDB2_SHIFT 17 82#define OMAP2430_EN_MMCHSDB2_SHIFT 17
83#define OMAP2430_EN_MMCHSDB2 (1 << 17) 83#define OMAP2430_EN_MMCHSDB2_MASK (1 << 17)
84#define OMAP2430_EN_MMCHSDB1_SHIFT 16 84#define OMAP2430_EN_MMCHSDB1_SHIFT 16
85#define OMAP2430_EN_MMCHSDB1 (1 << 16) 85#define OMAP2430_EN_MMCHSDB1_MASK (1 << 16)
86 86
87/* CM_ICLKEN1_CORE specific bits */ 87/* CM_ICLKEN1_CORE specific bits */
88#define OMAP24XX_EN_MAILBOXES_SHIFT 30 88#define OMAP24XX_EN_MAILBOXES_SHIFT 30
89#define OMAP24XX_EN_MAILBOXES (1 << 30) 89#define OMAP24XX_EN_MAILBOXES_MASK (1 << 30)
90#define OMAP24XX_EN_DSS_SHIFT 0 90#define OMAP24XX_EN_DSS_SHIFT 0
91#define OMAP24XX_EN_DSS (1 << 0) 91#define OMAP24XX_EN_DSS_MASK (1 << 0)
92 92
93/* CM_ICLKEN2_CORE specific bits */ 93/* CM_ICLKEN2_CORE specific bits */
94 94
95/* CM_ICLKEN3_CORE */ 95/* CM_ICLKEN3_CORE */
96/* 2430 only */ 96/* 2430 only */
97#define OMAP2430_EN_SDRC_SHIFT 2 97#define OMAP2430_EN_SDRC_SHIFT 2
98#define OMAP2430_EN_SDRC (1 << 2) 98#define OMAP2430_EN_SDRC_MASK (1 << 2)
99 99
100/* CM_ICLKEN4_CORE */ 100/* CM_ICLKEN4_CORE */
101#define OMAP24XX_EN_PKA_SHIFT 4 101#define OMAP24XX_EN_PKA_SHIFT 4
102#define OMAP24XX_EN_PKA (1 << 4) 102#define OMAP24XX_EN_PKA_MASK (1 << 4)
103#define OMAP24XX_EN_AES_SHIFT 3 103#define OMAP24XX_EN_AES_SHIFT 3
104#define OMAP24XX_EN_AES (1 << 3) 104#define OMAP24XX_EN_AES_MASK (1 << 3)
105#define OMAP24XX_EN_RNG_SHIFT 2 105#define OMAP24XX_EN_RNG_SHIFT 2
106#define OMAP24XX_EN_RNG (1 << 2) 106#define OMAP24XX_EN_RNG_MASK (1 << 2)
107#define OMAP24XX_EN_SHA_SHIFT 1 107#define OMAP24XX_EN_SHA_SHIFT 1
108#define OMAP24XX_EN_SHA (1 << 1) 108#define OMAP24XX_EN_SHA_MASK (1 << 1)
109#define OMAP24XX_EN_DES_SHIFT 0 109#define OMAP24XX_EN_DES_SHIFT 0
110#define OMAP24XX_EN_DES (1 << 0) 110#define OMAP24XX_EN_DES_MASK (1 << 0)
111 111
112/* CM_IDLEST1_CORE specific bits */ 112/* CM_IDLEST1_CORE specific bits */
113#define OMAP24XX_ST_MAILBOXES_SHIFT 30 113#define OMAP24XX_ST_MAILBOXES_SHIFT 30
@@ -138,9 +138,9 @@
138/* CM_IDLEST2_CORE */ 138/* CM_IDLEST2_CORE */
139#define OMAP2430_ST_MCBSP5_SHIFT 5 139#define OMAP2430_ST_MCBSP5_SHIFT 5
140#define OMAP2430_ST_MCBSP5_MASK (1 << 5) 140#define OMAP2430_ST_MCBSP5_MASK (1 << 5)
141#define OMAP2430_ST_MCBSP4_SHIFT 4 141#define OMAP2430_ST_MCBSP4_SHIFT 4
142#define OMAP2430_ST_MCBSP4_MASK (1 << 4) 142#define OMAP2430_ST_MCBSP4_MASK (1 << 4)
143#define OMAP2430_ST_MCBSP3_SHIFT 3 143#define OMAP2430_ST_MCBSP3_SHIFT 3
144#define OMAP2430_ST_MCBSP3_MASK (1 << 3) 144#define OMAP2430_ST_MCBSP3_MASK (1 << 3)
145#define OMAP24XX_ST_SSI_SHIFT 1 145#define OMAP24XX_ST_SSI_SHIFT 1
146#define OMAP24XX_ST_SSI_MASK (1 << 1) 146#define OMAP24XX_ST_SSI_MASK (1 << 1)
@@ -162,62 +162,62 @@
162#define OMAP24XX_ST_DES_MASK (1 << 0) 162#define OMAP24XX_ST_DES_MASK (1 << 0)
163 163
164/* CM_AUTOIDLE1_CORE */ 164/* CM_AUTOIDLE1_CORE */
165#define OMAP24XX_AUTO_CAM (1 << 31) 165#define OMAP24XX_AUTO_CAM_MASK (1 << 31)
166#define OMAP24XX_AUTO_MAILBOXES (1 << 30) 166#define OMAP24XX_AUTO_MAILBOXES_MASK (1 << 30)
167#define OMAP24XX_AUTO_WDT4 (1 << 29) 167#define OMAP24XX_AUTO_WDT4_MASK (1 << 29)
168#define OMAP2420_AUTO_WDT3 (1 << 28) 168#define OMAP2420_AUTO_WDT3_MASK (1 << 28)
169#define OMAP24XX_AUTO_MSPRO (1 << 27) 169#define OMAP24XX_AUTO_MSPRO_MASK (1 << 27)
170#define OMAP2420_AUTO_MMC (1 << 26) 170#define OMAP2420_AUTO_MMC_MASK (1 << 26)
171#define OMAP24XX_AUTO_FAC (1 << 25) 171#define OMAP24XX_AUTO_FAC_MASK (1 << 25)
172#define OMAP2420_AUTO_EAC (1 << 24) 172#define OMAP2420_AUTO_EAC_MASK (1 << 24)
173#define OMAP24XX_AUTO_HDQ (1 << 23) 173#define OMAP24XX_AUTO_HDQ_MASK (1 << 23)
174#define OMAP24XX_AUTO_UART2 (1 << 22) 174#define OMAP24XX_AUTO_UART2_MASK (1 << 22)
175#define OMAP24XX_AUTO_UART1 (1 << 21) 175#define OMAP24XX_AUTO_UART1_MASK (1 << 21)
176#define OMAP24XX_AUTO_I2C2 (1 << 20) 176#define OMAP24XX_AUTO_I2C2_MASK (1 << 20)
177#define OMAP24XX_AUTO_I2C1 (1 << 19) 177#define OMAP24XX_AUTO_I2C1_MASK (1 << 19)
178#define OMAP24XX_AUTO_MCSPI2 (1 << 18) 178#define OMAP24XX_AUTO_MCSPI2_MASK (1 << 18)
179#define OMAP24XX_AUTO_MCSPI1 (1 << 17) 179#define OMAP24XX_AUTO_MCSPI1_MASK (1 << 17)
180#define OMAP24XX_AUTO_MCBSP2 (1 << 16) 180#define OMAP24XX_AUTO_MCBSP2_MASK (1 << 16)
181#define OMAP24XX_AUTO_MCBSP1 (1 << 15) 181#define OMAP24XX_AUTO_MCBSP1_MASK (1 << 15)
182#define OMAP24XX_AUTO_GPT12 (1 << 14) 182#define OMAP24XX_AUTO_GPT12_MASK (1 << 14)
183#define OMAP24XX_AUTO_GPT11 (1 << 13) 183#define OMAP24XX_AUTO_GPT11_MASK (1 << 13)
184#define OMAP24XX_AUTO_GPT10 (1 << 12) 184#define OMAP24XX_AUTO_GPT10_MASK (1 << 12)
185#define OMAP24XX_AUTO_GPT9 (1 << 11) 185#define OMAP24XX_AUTO_GPT9_MASK (1 << 11)
186#define OMAP24XX_AUTO_GPT8 (1 << 10) 186#define OMAP24XX_AUTO_GPT8_MASK (1 << 10)
187#define OMAP24XX_AUTO_GPT7 (1 << 9) 187#define OMAP24XX_AUTO_GPT7_MASK (1 << 9)
188#define OMAP24XX_AUTO_GPT6 (1 << 8) 188#define OMAP24XX_AUTO_GPT6_MASK (1 << 8)
189#define OMAP24XX_AUTO_GPT5 (1 << 7) 189#define OMAP24XX_AUTO_GPT5_MASK (1 << 7)
190#define OMAP24XX_AUTO_GPT4 (1 << 6) 190#define OMAP24XX_AUTO_GPT4_MASK (1 << 6)
191#define OMAP24XX_AUTO_GPT3 (1 << 5) 191#define OMAP24XX_AUTO_GPT3_MASK (1 << 5)
192#define OMAP24XX_AUTO_GPT2 (1 << 4) 192#define OMAP24XX_AUTO_GPT2_MASK (1 << 4)
193#define OMAP2420_AUTO_VLYNQ (1 << 3) 193#define OMAP2420_AUTO_VLYNQ_MASK (1 << 3)
194#define OMAP24XX_AUTO_DSS (1 << 0) 194#define OMAP24XX_AUTO_DSS_MASK (1 << 0)
195 195
196/* CM_AUTOIDLE2_CORE */ 196/* CM_AUTOIDLE2_CORE */
197#define OMAP2430_AUTO_MDM_INTC (1 << 11) 197#define OMAP2430_AUTO_MDM_INTC_MASK (1 << 11)
198#define OMAP2430_AUTO_GPIO5 (1 << 10) 198#define OMAP2430_AUTO_GPIO5_MASK (1 << 10)
199#define OMAP2430_AUTO_MCSPI3 (1 << 9) 199#define OMAP2430_AUTO_MCSPI3_MASK (1 << 9)
200#define OMAP2430_AUTO_MMCHS2 (1 << 8) 200#define OMAP2430_AUTO_MMCHS2_MASK (1 << 8)
201#define OMAP2430_AUTO_MMCHS1 (1 << 7) 201#define OMAP2430_AUTO_MMCHS1_MASK (1 << 7)
202#define OMAP2430_AUTO_USBHS (1 << 6) 202#define OMAP2430_AUTO_USBHS_MASK (1 << 6)
203#define OMAP2430_AUTO_MCBSP5 (1 << 5) 203#define OMAP2430_AUTO_MCBSP5_MASK (1 << 5)
204#define OMAP2430_AUTO_MCBSP4 (1 << 4) 204#define OMAP2430_AUTO_MCBSP4_MASK (1 << 4)
205#define OMAP2430_AUTO_MCBSP3 (1 << 3) 205#define OMAP2430_AUTO_MCBSP3_MASK (1 << 3)
206#define OMAP24XX_AUTO_UART3 (1 << 2) 206#define OMAP24XX_AUTO_UART3_MASK (1 << 2)
207#define OMAP24XX_AUTO_SSI (1 << 1) 207#define OMAP24XX_AUTO_SSI_MASK (1 << 1)
208#define OMAP24XX_AUTO_USB (1 << 0) 208#define OMAP24XX_AUTO_USB_MASK (1 << 0)
209 209
210/* CM_AUTOIDLE3_CORE */ 210/* CM_AUTOIDLE3_CORE */
211#define OMAP24XX_AUTO_SDRC (1 << 2) 211#define OMAP24XX_AUTO_SDRC_MASK (1 << 2)
212#define OMAP24XX_AUTO_GPMC (1 << 1) 212#define OMAP24XX_AUTO_GPMC_MASK (1 << 1)
213#define OMAP24XX_AUTO_SDMA (1 << 0) 213#define OMAP24XX_AUTO_SDMA_MASK (1 << 0)
214 214
215/* CM_AUTOIDLE4_CORE */ 215/* CM_AUTOIDLE4_CORE */
216#define OMAP24XX_AUTO_PKA (1 << 4) 216#define OMAP24XX_AUTO_PKA_MASK (1 << 4)
217#define OMAP24XX_AUTO_AES (1 << 3) 217#define OMAP24XX_AUTO_AES_MASK (1 << 3)
218#define OMAP24XX_AUTO_RNG (1 << 2) 218#define OMAP24XX_AUTO_RNG_MASK (1 << 2)
219#define OMAP24XX_AUTO_SHA (1 << 1) 219#define OMAP24XX_AUTO_SHA_MASK (1 << 1)
220#define OMAP24XX_AUTO_DES (1 << 0) 220#define OMAP24XX_AUTO_DES_MASK (1 << 0)
221 221
222/* CM_CLKSEL1_CORE */ 222/* CM_CLKSEL1_CORE */
223#define OMAP24XX_CLKSEL_USB_SHIFT 25 223#define OMAP24XX_CLKSEL_USB_SHIFT 25
@@ -269,9 +269,9 @@
269 269
270/* CM_FCLKEN_GFX */ 270/* CM_FCLKEN_GFX */
271#define OMAP24XX_EN_3D_SHIFT 2 271#define OMAP24XX_EN_3D_SHIFT 2
272#define OMAP24XX_EN_3D (1 << 2) 272#define OMAP24XX_EN_3D_MASK (1 << 2)
273#define OMAP24XX_EN_2D_SHIFT 1 273#define OMAP24XX_EN_2D_SHIFT 1
274#define OMAP24XX_EN_2D (1 << 1) 274#define OMAP24XX_EN_2D_MASK (1 << 1)
275 275
276/* CM_ICLKEN_GFX specific bits */ 276/* CM_ICLKEN_GFX specific bits */
277 277
@@ -287,13 +287,13 @@
287 287
288/* CM_ICLKEN_WKUP specific bits */ 288/* CM_ICLKEN_WKUP specific bits */
289#define OMAP2430_EN_ICR_SHIFT 6 289#define OMAP2430_EN_ICR_SHIFT 6
290#define OMAP2430_EN_ICR (1 << 6) 290#define OMAP2430_EN_ICR_MASK (1 << 6)
291#define OMAP24XX_EN_OMAPCTRL_SHIFT 5 291#define OMAP24XX_EN_OMAPCTRL_SHIFT 5
292#define OMAP24XX_EN_OMAPCTRL (1 << 5) 292#define OMAP24XX_EN_OMAPCTRL_MASK (1 << 5)
293#define OMAP24XX_EN_WDT1_SHIFT 4 293#define OMAP24XX_EN_WDT1_SHIFT 4
294#define OMAP24XX_EN_WDT1 (1 << 4) 294#define OMAP24XX_EN_WDT1_MASK (1 << 4)
295#define OMAP24XX_EN_32KSYNC_SHIFT 1 295#define OMAP24XX_EN_32KSYNC_SHIFT 1
296#define OMAP24XX_EN_32KSYNC (1 << 1) 296#define OMAP24XX_EN_32KSYNC_MASK (1 << 1)
297 297
298/* CM_IDLEST_WKUP specific bits */ 298/* CM_IDLEST_WKUP specific bits */
299#define OMAP2430_ST_ICR_SHIFT 6 299#define OMAP2430_ST_ICR_SHIFT 6
@@ -308,12 +308,12 @@
308#define OMAP24XX_ST_32KSYNC_MASK (1 << 1) 308#define OMAP24XX_ST_32KSYNC_MASK (1 << 1)
309 309
310/* CM_AUTOIDLE_WKUP */ 310/* CM_AUTOIDLE_WKUP */
311#define OMAP24XX_AUTO_OMAPCTRL (1 << 5) 311#define OMAP24XX_AUTO_OMAPCTRL_MASK (1 << 5)
312#define OMAP24XX_AUTO_WDT1 (1 << 4) 312#define OMAP24XX_AUTO_WDT1_MASK (1 << 4)
313#define OMAP24XX_AUTO_MPU_WDT (1 << 3) 313#define OMAP24XX_AUTO_MPU_WDT_MASK (1 << 3)
314#define OMAP24XX_AUTO_GPIOS (1 << 2) 314#define OMAP24XX_AUTO_GPIOS_MASK (1 << 2)
315#define OMAP24XX_AUTO_32KSYNC (1 << 1) 315#define OMAP24XX_AUTO_32KSYNC_MASK (1 << 1)
316#define OMAP24XX_AUTO_GPT1 (1 << 0) 316#define OMAP24XX_AUTO_GPT1_MASK (1 << 0)
317 317
318/* CM_CLKSEL_WKUP */ 318/* CM_CLKSEL_WKUP */
319#define OMAP24XX_CLKSEL_GPT1_SHIFT 0 319#define OMAP24XX_CLKSEL_GPT1_SHIFT 0
@@ -328,12 +328,12 @@
328#define OMAP24XX_EN_DPLL_MASK (0x3 << 0) 328#define OMAP24XX_EN_DPLL_MASK (0x3 << 0)
329 329
330/* CM_IDLEST_CKGEN */ 330/* CM_IDLEST_CKGEN */
331#define OMAP24XX_ST_54M_APLL (1 << 9) 331#define OMAP24XX_ST_54M_APLL_MASK (1 << 9)
332#define OMAP24XX_ST_96M_APLL (1 << 8) 332#define OMAP24XX_ST_96M_APLL_MASK (1 << 8)
333#define OMAP24XX_ST_54M_CLK (1 << 6) 333#define OMAP24XX_ST_54M_CLK_MASK (1 << 6)
334#define OMAP24XX_ST_12M_CLK (1 << 5) 334#define OMAP24XX_ST_12M_CLK_MASK (1 << 5)
335#define OMAP24XX_ST_48M_CLK (1 << 4) 335#define OMAP24XX_ST_48M_CLK_MASK (1 << 4)
336#define OMAP24XX_ST_96M_CLK (1 << 2) 336#define OMAP24XX_ST_96M_CLK_MASK (1 << 2)
337#define OMAP24XX_ST_CORE_CLK_SHIFT 0 337#define OMAP24XX_ST_CORE_CLK_SHIFT 0
338#define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0) 338#define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0)
339 339
@@ -355,11 +355,11 @@
355#define OMAP24XX_DPLL_DIV_SHIFT 8 355#define OMAP24XX_DPLL_DIV_SHIFT 8
356#define OMAP24XX_DPLL_DIV_MASK (0xf << 8) 356#define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
357#define OMAP24XX_54M_SOURCE_SHIFT 5 357#define OMAP24XX_54M_SOURCE_SHIFT 5
358#define OMAP24XX_54M_SOURCE (1 << 5) 358#define OMAP24XX_54M_SOURCE_MASK (1 << 5)
359#define OMAP2430_96M_SOURCE_SHIFT 4 359#define OMAP2430_96M_SOURCE_SHIFT 4
360#define OMAP2430_96M_SOURCE (1 << 4) 360#define OMAP2430_96M_SOURCE_MASK (1 << 4)
361#define OMAP24XX_48M_SOURCE_SHIFT 3 361#define OMAP24XX_48M_SOURCE_SHIFT 3
362#define OMAP24XX_48M_SOURCE (1 << 3) 362#define OMAP24XX_48M_SOURCE_MASK (1 << 3)
363#define OMAP2430_ALTCLK_SOURCE_SHIFT 0 363#define OMAP2430_ALTCLK_SOURCE_SHIFT 0
364#define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0) 364#define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0)
365 365
@@ -369,29 +369,29 @@
369 369
370/* CM_FCLKEN_DSP */ 370/* CM_FCLKEN_DSP */
371#define OMAP2420_EN_IVA_COP_SHIFT 10 371#define OMAP2420_EN_IVA_COP_SHIFT 10
372#define OMAP2420_EN_IVA_COP (1 << 10) 372#define OMAP2420_EN_IVA_COP_MASK (1 << 10)
373#define OMAP2420_EN_IVA_MPU_SHIFT 8 373#define OMAP2420_EN_IVA_MPU_SHIFT 8
374#define OMAP2420_EN_IVA_MPU (1 << 8) 374#define OMAP2420_EN_IVA_MPU_MASK (1 << 8)
375#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0 375#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0
376#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP (1 << 0) 376#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_MASK (1 << 0)
377 377
378/* CM_ICLKEN_DSP */ 378/* CM_ICLKEN_DSP */
379#define OMAP2420_EN_DSP_IPI_SHIFT 1 379#define OMAP2420_EN_DSP_IPI_SHIFT 1
380#define OMAP2420_EN_DSP_IPI (1 << 1) 380#define OMAP2420_EN_DSP_IPI_MASK (1 << 1)
381 381
382/* CM_IDLEST_DSP */ 382/* CM_IDLEST_DSP */
383#define OMAP2420_ST_IVA (1 << 8) 383#define OMAP2420_ST_IVA_MASK (1 << 8)
384#define OMAP2420_ST_IPI (1 << 1) 384#define OMAP2420_ST_IPI_MASK (1 << 1)
385#define OMAP24XX_ST_DSP (1 << 0) 385#define OMAP24XX_ST_DSP_MASK (1 << 0)
386 386
387/* CM_AUTOIDLE_DSP */ 387/* CM_AUTOIDLE_DSP */
388#define OMAP2420_AUTO_DSP_IPI (1 << 1) 388#define OMAP2420_AUTO_DSP_IPI_MASK (1 << 1)
389 389
390/* CM_CLKSEL_DSP */ 390/* CM_CLKSEL_DSP */
391#define OMAP2420_SYNC_IVA (1 << 13) 391#define OMAP2420_SYNC_IVA_MASK (1 << 13)
392#define OMAP2420_CLKSEL_IVA_SHIFT 8 392#define OMAP2420_CLKSEL_IVA_SHIFT 8
393#define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8) 393#define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8)
394#define OMAP24XX_SYNC_DSP (1 << 7) 394#define OMAP24XX_SYNC_DSP_MASK (1 << 7)
395#define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5 395#define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5
396#define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5) 396#define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5)
397#define OMAP24XX_CLKSEL_DSP_SHIFT 0 397#define OMAP24XX_CLKSEL_DSP_SHIFT 0
@@ -406,24 +406,24 @@
406/* CM_FCLKEN_MDM */ 406/* CM_FCLKEN_MDM */
407/* 2430 only */ 407/* 2430 only */
408#define OMAP2430_EN_OSC_SHIFT 1 408#define OMAP2430_EN_OSC_SHIFT 1
409#define OMAP2430_EN_OSC (1 << 1) 409#define OMAP2430_EN_OSC_MASK (1 << 1)
410 410
411/* CM_ICLKEN_MDM */ 411/* CM_ICLKEN_MDM */
412/* 2430 only */ 412/* 2430 only */
413#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0 413#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0
414#define OMAP2430_CM_ICLKEN_MDM_EN_MDM (1 << 0) 414#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_MASK (1 << 0)
415 415
416/* CM_IDLEST_MDM specific bits */ 416/* CM_IDLEST_MDM specific bits */
417/* 2430 only */ 417/* 2430 only */
418 418
419/* CM_AUTOIDLE_MDM */ 419/* CM_AUTOIDLE_MDM */
420/* 2430 only */ 420/* 2430 only */
421#define OMAP2430_AUTO_OSC (1 << 1) 421#define OMAP2430_AUTO_OSC_MASK (1 << 1)
422#define OMAP2430_AUTO_MDM (1 << 0) 422#define OMAP2430_AUTO_MDM_MASK (1 << 0)
423 423
424/* CM_CLKSEL_MDM */ 424/* CM_CLKSEL_MDM */
425/* 2430 only */ 425/* 2430 only */
426#define OMAP2430_SYNC_MDM (1 << 4) 426#define OMAP2430_SYNC_MDM_MASK (1 << 4)
427#define OMAP2430_CLKSEL_MDM_SHIFT 0 427#define OMAP2430_CLKSEL_MDM_SHIFT 0
428#define OMAP2430_CLKSEL_MDM_MASK (0xf << 0) 428#define OMAP2430_CLKSEL_MDM_MASK (0xf << 0)
429 429
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index a3a3ca07e383..fe82b79d5f3b 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -21,15 +21,15 @@
21/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ 21/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
22#define OMAP3430ES2_EN_MMC3_MASK (1 << 30) 22#define OMAP3430ES2_EN_MMC3_MASK (1 << 30)
23#define OMAP3430ES2_EN_MMC3_SHIFT 30 23#define OMAP3430ES2_EN_MMC3_SHIFT 30
24#define OMAP3430_EN_MSPRO (1 << 23) 24#define OMAP3430_EN_MSPRO_MASK (1 << 23)
25#define OMAP3430_EN_MSPRO_SHIFT 23 25#define OMAP3430_EN_MSPRO_SHIFT 23
26#define OMAP3430_EN_HDQ (1 << 22) 26#define OMAP3430_EN_HDQ_MASK (1 << 22)
27#define OMAP3430_EN_HDQ_SHIFT 22 27#define OMAP3430_EN_HDQ_SHIFT 22
28#define OMAP3430ES1_EN_FSHOSTUSB (1 << 5) 28#define OMAP3430ES1_EN_FSHOSTUSB_MASK (1 << 5)
29#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 29#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5
30#define OMAP3430ES1_EN_D2D (1 << 3) 30#define OMAP3430ES1_EN_D2D_MASK (1 << 3)
31#define OMAP3430ES1_EN_D2D_SHIFT 3 31#define OMAP3430ES1_EN_D2D_SHIFT 3
32#define OMAP3430_EN_SSI (1 << 0) 32#define OMAP3430_EN_SSI_MASK (1 << 0)
33#define OMAP3430_EN_SSI_SHIFT 0 33#define OMAP3430_EN_SSI_SHIFT 0
34 34
35/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ 35/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
@@ -37,19 +37,19 @@
37#define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) 37#define OMAP3430ES2_EN_USBTLL_MASK (1 << 2)
38 38
39/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ 39/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
40#define OMAP3430_EN_WDT2 (1 << 5) 40#define OMAP3430_EN_WDT2_MASK (1 << 5)
41#define OMAP3430_EN_WDT2_SHIFT 5 41#define OMAP3430_EN_WDT2_SHIFT 5
42 42
43/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */ 43/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
44#define OMAP3430_EN_CAM (1 << 0) 44#define OMAP3430_EN_CAM_MASK (1 << 0)
45#define OMAP3430_EN_CAM_SHIFT 0 45#define OMAP3430_EN_CAM_SHIFT 0
46 46
47/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */ 47/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
48#define OMAP3430_EN_WDT3 (1 << 12) 48#define OMAP3430_EN_WDT3_MASK (1 << 12)
49#define OMAP3430_EN_WDT3_SHIFT 12 49#define OMAP3430_EN_WDT3_SHIFT 12
50 50
51/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */ 51/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
52#define OMAP3430_OVERRIDE_ENABLE (1 << 19) 52#define OMAP3430_OVERRIDE_ENABLE_MASK (1 << 19)
53 53
54 54
55/* Bits specific to each register */ 55/* Bits specific to each register */
@@ -69,7 +69,7 @@
69#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) 69#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)
70 70
71/* CM_IDLEST_IVA2 */ 71/* CM_IDLEST_IVA2 */
72#define OMAP3430_ST_IVA2 (1 << 0) 72#define OMAP3430_ST_IVA2_MASK (1 << 0)
73 73
74/* CM_IDLEST_PLL_IVA2 */ 74/* CM_IDLEST_PLL_IVA2 */
75#define OMAP3430_ST_IVA2_CLK_SHIFT 0 75#define OMAP3430_ST_IVA2_CLK_SHIFT 0
@@ -114,7 +114,7 @@
114#define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) 114#define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0)
115 115
116/* CM_IDLEST_MPU */ 116/* CM_IDLEST_MPU */
117#define OMAP3430_ST_MPU (1 << 0) 117#define OMAP3430_ST_MPU_MASK (1 << 0)
118 118
119/* CM_IDLEST_PLL_MPU */ 119/* CM_IDLEST_PLL_MPU */
120#define OMAP3430_ST_MPU_CLK_SHIFT 0 120#define OMAP3430_ST_MPU_CLK_SHIFT 0
@@ -145,50 +145,50 @@
145#define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0) 145#define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0)
146 146
147/* CM_FCLKEN1_CORE specific bits */ 147/* CM_FCLKEN1_CORE specific bits */
148#define OMAP3430_EN_MODEM (1 << 31) 148#define OMAP3430_EN_MODEM_MASK (1 << 31)
149#define OMAP3430_EN_MODEM_SHIFT 31 149#define OMAP3430_EN_MODEM_SHIFT 31
150 150
151/* CM_ICLKEN1_CORE specific bits */ 151/* CM_ICLKEN1_CORE specific bits */
152#define OMAP3430_EN_ICR (1 << 29) 152#define OMAP3430_EN_ICR_MASK (1 << 29)
153#define OMAP3430_EN_ICR_SHIFT 29 153#define OMAP3430_EN_ICR_SHIFT 29
154#define OMAP3430_EN_AES2 (1 << 28) 154#define OMAP3430_EN_AES2_MASK (1 << 28)
155#define OMAP3430_EN_AES2_SHIFT 28 155#define OMAP3430_EN_AES2_SHIFT 28
156#define OMAP3430_EN_SHA12 (1 << 27) 156#define OMAP3430_EN_SHA12_MASK (1 << 27)
157#define OMAP3430_EN_SHA12_SHIFT 27 157#define OMAP3430_EN_SHA12_SHIFT 27
158#define OMAP3430_EN_DES2 (1 << 26) 158#define OMAP3430_EN_DES2_MASK (1 << 26)
159#define OMAP3430_EN_DES2_SHIFT 26 159#define OMAP3430_EN_DES2_SHIFT 26
160#define OMAP3430ES1_EN_FAC (1 << 8) 160#define OMAP3430ES1_EN_FAC_MASK (1 << 8)
161#define OMAP3430ES1_EN_FAC_SHIFT 8 161#define OMAP3430ES1_EN_FAC_SHIFT 8
162#define OMAP3430_EN_MAILBOXES (1 << 7) 162#define OMAP3430_EN_MAILBOXES_MASK (1 << 7)
163#define OMAP3430_EN_MAILBOXES_SHIFT 7 163#define OMAP3430_EN_MAILBOXES_SHIFT 7
164#define OMAP3430_EN_OMAPCTRL (1 << 6) 164#define OMAP3430_EN_OMAPCTRL_MASK (1 << 6)
165#define OMAP3430_EN_OMAPCTRL_SHIFT 6 165#define OMAP3430_EN_OMAPCTRL_SHIFT 6
166#define OMAP3430_EN_SAD2D (1 << 3) 166#define OMAP3430_EN_SAD2D_MASK (1 << 3)
167#define OMAP3430_EN_SAD2D_SHIFT 3 167#define OMAP3430_EN_SAD2D_SHIFT 3
168#define OMAP3430_EN_SDRC (1 << 1) 168#define OMAP3430_EN_SDRC_MASK (1 << 1)
169#define OMAP3430_EN_SDRC_SHIFT 1 169#define OMAP3430_EN_SDRC_SHIFT 1
170 170
171/* AM35XX specific CM_ICLKEN1_CORE bits */ 171/* AM35XX specific CM_ICLKEN1_CORE bits */
172#define AM35XX_EN_IPSS_MASK (1 << 4) 172#define AM35XX_EN_IPSS_MASK (1 << 4)
173#define AM35XX_EN_IPSS_SHIFT 4 173#define AM35XX_EN_IPSS_SHIFT 4
174#define AM35XX_EN_UART4_MASK (1 << 23) 174#define AM35XX_EN_UART4_MASK (1 << 23)
175#define AM35XX_EN_UART4_SHIFT 23 175#define AM35XX_EN_UART4_SHIFT 23
176 176
177/* CM_ICLKEN2_CORE */ 177/* CM_ICLKEN2_CORE */
178#define OMAP3430_EN_PKA (1 << 4) 178#define OMAP3430_EN_PKA_MASK (1 << 4)
179#define OMAP3430_EN_PKA_SHIFT 4 179#define OMAP3430_EN_PKA_SHIFT 4
180#define OMAP3430_EN_AES1 (1 << 3) 180#define OMAP3430_EN_AES1_MASK (1 << 3)
181#define OMAP3430_EN_AES1_SHIFT 3 181#define OMAP3430_EN_AES1_SHIFT 3
182#define OMAP3430_EN_RNG (1 << 2) 182#define OMAP3430_EN_RNG_MASK (1 << 2)
183#define OMAP3430_EN_RNG_SHIFT 2 183#define OMAP3430_EN_RNG_SHIFT 2
184#define OMAP3430_EN_SHA11 (1 << 1) 184#define OMAP3430_EN_SHA11_MASK (1 << 1)
185#define OMAP3430_EN_SHA11_SHIFT 1 185#define OMAP3430_EN_SHA11_SHIFT 1
186#define OMAP3430_EN_DES1 (1 << 0) 186#define OMAP3430_EN_DES1_MASK (1 << 0)
187#define OMAP3430_EN_DES1_SHIFT 0 187#define OMAP3430_EN_DES1_SHIFT 0
188 188
189/* CM_ICLKEN3_CORE */ 189/* CM_ICLKEN3_CORE */
190#define OMAP3430_EN_MAD2D_SHIFT 3 190#define OMAP3430_EN_MAD2D_SHIFT 3
191#define OMAP3430_EN_MAD2D (1 << 3) 191#define OMAP3430_EN_MAD2D_MASK (1 << 3)
192 192
193/* CM_FCLKEN3_CORE specific bits */ 193/* CM_FCLKEN3_CORE specific bits */
194#define OMAP3430ES2_EN_TS_SHIFT 1 194#define OMAP3430ES2_EN_TS_SHIFT 1
@@ -249,79 +249,79 @@
249#define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) 249#define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0)
250 250
251/* CM_AUTOIDLE1_CORE */ 251/* CM_AUTOIDLE1_CORE */
252#define OMAP3430_AUTO_MODEM (1 << 31) 252#define OMAP3430_AUTO_MODEM_MASK (1 << 31)
253#define OMAP3430_AUTO_MODEM_SHIFT 31 253#define OMAP3430_AUTO_MODEM_SHIFT 31
254#define OMAP3430ES2_AUTO_MMC3 (1 << 30) 254#define OMAP3430ES2_AUTO_MMC3_MASK (1 << 30)
255#define OMAP3430ES2_AUTO_MMC3_SHIFT 30 255#define OMAP3430ES2_AUTO_MMC3_SHIFT 30
256#define OMAP3430ES2_AUTO_ICR (1 << 29) 256#define OMAP3430ES2_AUTO_ICR_MASK (1 << 29)
257#define OMAP3430ES2_AUTO_ICR_SHIFT 29 257#define OMAP3430ES2_AUTO_ICR_SHIFT 29
258#define OMAP3430_AUTO_AES2 (1 << 28) 258#define OMAP3430_AUTO_AES2_MASK (1 << 28)
259#define OMAP3430_AUTO_AES2_SHIFT 28 259#define OMAP3430_AUTO_AES2_SHIFT 28
260#define OMAP3430_AUTO_SHA12 (1 << 27) 260#define OMAP3430_AUTO_SHA12_MASK (1 << 27)
261#define OMAP3430_AUTO_SHA12_SHIFT 27 261#define OMAP3430_AUTO_SHA12_SHIFT 27
262#define OMAP3430_AUTO_DES2 (1 << 26) 262#define OMAP3430_AUTO_DES2_MASK (1 << 26)
263#define OMAP3430_AUTO_DES2_SHIFT 26 263#define OMAP3430_AUTO_DES2_SHIFT 26
264#define OMAP3430_AUTO_MMC2 (1 << 25) 264#define OMAP3430_AUTO_MMC2_MASK (1 << 25)
265#define OMAP3430_AUTO_MMC2_SHIFT 25 265#define OMAP3430_AUTO_MMC2_SHIFT 25
266#define OMAP3430_AUTO_MMC1 (1 << 24) 266#define OMAP3430_AUTO_MMC1_MASK (1 << 24)
267#define OMAP3430_AUTO_MMC1_SHIFT 24 267#define OMAP3430_AUTO_MMC1_SHIFT 24
268#define OMAP3430_AUTO_MSPRO (1 << 23) 268#define OMAP3430_AUTO_MSPRO_MASK (1 << 23)
269#define OMAP3430_AUTO_MSPRO_SHIFT 23 269#define OMAP3430_AUTO_MSPRO_SHIFT 23
270#define OMAP3430_AUTO_HDQ (1 << 22) 270#define OMAP3430_AUTO_HDQ_MASK (1 << 22)
271#define OMAP3430_AUTO_HDQ_SHIFT 22 271#define OMAP3430_AUTO_HDQ_SHIFT 22
272#define OMAP3430_AUTO_MCSPI4 (1 << 21) 272#define OMAP3430_AUTO_MCSPI4_MASK (1 << 21)
273#define OMAP3430_AUTO_MCSPI4_SHIFT 21 273#define OMAP3430_AUTO_MCSPI4_SHIFT 21
274#define OMAP3430_AUTO_MCSPI3 (1 << 20) 274#define OMAP3430_AUTO_MCSPI3_MASK (1 << 20)
275#define OMAP3430_AUTO_MCSPI3_SHIFT 20 275#define OMAP3430_AUTO_MCSPI3_SHIFT 20
276#define OMAP3430_AUTO_MCSPI2 (1 << 19) 276#define OMAP3430_AUTO_MCSPI2_MASK (1 << 19)
277#define OMAP3430_AUTO_MCSPI2_SHIFT 19 277#define OMAP3430_AUTO_MCSPI2_SHIFT 19
278#define OMAP3430_AUTO_MCSPI1 (1 << 18) 278#define OMAP3430_AUTO_MCSPI1_MASK (1 << 18)
279#define OMAP3430_AUTO_MCSPI1_SHIFT 18 279#define OMAP3430_AUTO_MCSPI1_SHIFT 18
280#define OMAP3430_AUTO_I2C3 (1 << 17) 280#define OMAP3430_AUTO_I2C3_MASK (1 << 17)
281#define OMAP3430_AUTO_I2C3_SHIFT 17 281#define OMAP3430_AUTO_I2C3_SHIFT 17
282#define OMAP3430_AUTO_I2C2 (1 << 16) 282#define OMAP3430_AUTO_I2C2_MASK (1 << 16)
283#define OMAP3430_AUTO_I2C2_SHIFT 16 283#define OMAP3430_AUTO_I2C2_SHIFT 16
284#define OMAP3430_AUTO_I2C1 (1 << 15) 284#define OMAP3430_AUTO_I2C1_MASK (1 << 15)
285#define OMAP3430_AUTO_I2C1_SHIFT 15 285#define OMAP3430_AUTO_I2C1_SHIFT 15
286#define OMAP3430_AUTO_UART2 (1 << 14) 286#define OMAP3430_AUTO_UART2_MASK (1 << 14)
287#define OMAP3430_AUTO_UART2_SHIFT 14 287#define OMAP3430_AUTO_UART2_SHIFT 14
288#define OMAP3430_AUTO_UART1 (1 << 13) 288#define OMAP3430_AUTO_UART1_MASK (1 << 13)
289#define OMAP3430_AUTO_UART1_SHIFT 13 289#define OMAP3430_AUTO_UART1_SHIFT 13
290#define OMAP3430_AUTO_GPT11 (1 << 12) 290#define OMAP3430_AUTO_GPT11_MASK (1 << 12)
291#define OMAP3430_AUTO_GPT11_SHIFT 12 291#define OMAP3430_AUTO_GPT11_SHIFT 12
292#define OMAP3430_AUTO_GPT10 (1 << 11) 292#define OMAP3430_AUTO_GPT10_MASK (1 << 11)
293#define OMAP3430_AUTO_GPT10_SHIFT 11 293#define OMAP3430_AUTO_GPT10_SHIFT 11
294#define OMAP3430_AUTO_MCBSP5 (1 << 10) 294#define OMAP3430_AUTO_MCBSP5_MASK (1 << 10)
295#define OMAP3430_AUTO_MCBSP5_SHIFT 10 295#define OMAP3430_AUTO_MCBSP5_SHIFT 10
296#define OMAP3430_AUTO_MCBSP1 (1 << 9) 296#define OMAP3430_AUTO_MCBSP1_MASK (1 << 9)
297#define OMAP3430_AUTO_MCBSP1_SHIFT 9 297#define OMAP3430_AUTO_MCBSP1_SHIFT 9
298#define OMAP3430ES1_AUTO_FAC (1 << 8) 298#define OMAP3430ES1_AUTO_FAC_MASK (1 << 8)
299#define OMAP3430ES1_AUTO_FAC_SHIFT 8 299#define OMAP3430ES1_AUTO_FAC_SHIFT 8
300#define OMAP3430_AUTO_MAILBOXES (1 << 7) 300#define OMAP3430_AUTO_MAILBOXES_MASK (1 << 7)
301#define OMAP3430_AUTO_MAILBOXES_SHIFT 7 301#define OMAP3430_AUTO_MAILBOXES_SHIFT 7
302#define OMAP3430_AUTO_OMAPCTRL (1 << 6) 302#define OMAP3430_AUTO_OMAPCTRL_MASK (1 << 6)
303#define OMAP3430_AUTO_OMAPCTRL_SHIFT 6 303#define OMAP3430_AUTO_OMAPCTRL_SHIFT 6
304#define OMAP3430ES1_AUTO_FSHOSTUSB (1 << 5) 304#define OMAP3430ES1_AUTO_FSHOSTUSB_MASK (1 << 5)
305#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5 305#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5
306#define OMAP3430_AUTO_HSOTGUSB (1 << 4) 306#define OMAP3430_AUTO_HSOTGUSB_MASK (1 << 4)
307#define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 307#define OMAP3430_AUTO_HSOTGUSB_SHIFT 4
308#define OMAP3430ES1_AUTO_D2D (1 << 3) 308#define OMAP3430ES1_AUTO_D2D_MASK (1 << 3)
309#define OMAP3430ES1_AUTO_D2D_SHIFT 3 309#define OMAP3430ES1_AUTO_D2D_SHIFT 3
310#define OMAP3430_AUTO_SAD2D (1 << 3) 310#define OMAP3430_AUTO_SAD2D_MASK (1 << 3)
311#define OMAP3430_AUTO_SAD2D_SHIFT 3 311#define OMAP3430_AUTO_SAD2D_SHIFT 3
312#define OMAP3430_AUTO_SSI (1 << 0) 312#define OMAP3430_AUTO_SSI_MASK (1 << 0)
313#define OMAP3430_AUTO_SSI_SHIFT 0 313#define OMAP3430_AUTO_SSI_SHIFT 0
314 314
315/* CM_AUTOIDLE2_CORE */ 315/* CM_AUTOIDLE2_CORE */
316#define OMAP3430_AUTO_PKA (1 << 4) 316#define OMAP3430_AUTO_PKA_MASK (1 << 4)
317#define OMAP3430_AUTO_PKA_SHIFT 4 317#define OMAP3430_AUTO_PKA_SHIFT 4
318#define OMAP3430_AUTO_AES1 (1 << 3) 318#define OMAP3430_AUTO_AES1_MASK (1 << 3)
319#define OMAP3430_AUTO_AES1_SHIFT 3 319#define OMAP3430_AUTO_AES1_SHIFT 3
320#define OMAP3430_AUTO_RNG (1 << 2) 320#define OMAP3430_AUTO_RNG_MASK (1 << 2)
321#define OMAP3430_AUTO_RNG_SHIFT 2 321#define OMAP3430_AUTO_RNG_SHIFT 2
322#define OMAP3430_AUTO_SHA11 (1 << 1) 322#define OMAP3430_AUTO_SHA11_MASK (1 << 1)
323#define OMAP3430_AUTO_SHA11_SHIFT 1 323#define OMAP3430_AUTO_SHA11_SHIFT 1
324#define OMAP3430_AUTO_DES1 (1 << 0) 324#define OMAP3430_AUTO_DES1_MASK (1 << 0)
325#define OMAP3430_AUTO_DES1_SHIFT 0 325#define OMAP3430_AUTO_DES1_SHIFT 0
326 326
327/* CM_AUTOIDLE3_CORE */ 327/* CM_AUTOIDLE3_CORE */
@@ -331,7 +331,7 @@
331#define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 331#define OMAP3430ES2_AUTO_USBTLL_SHIFT 2
332#define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) 332#define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2)
333#define OMAP3430_AUTO_MAD2D_SHIFT 3 333#define OMAP3430_AUTO_MAD2D_SHIFT 3
334#define OMAP3430_AUTO_MAD2D (1 << 3) 334#define OMAP3430_AUTO_MAD2D_MASK (1 << 3)
335 335
336/* CM_CLKSEL_CORE */ 336/* CM_CLKSEL_CORE */
337#define OMAP3430_CLKSEL_SSI_SHIFT 8 337#define OMAP3430_CLKSEL_SSI_SHIFT 8
@@ -366,9 +366,9 @@
366#define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0) 366#define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0)
367 367
368/* CM_FCLKEN_GFX */ 368/* CM_FCLKEN_GFX */
369#define OMAP3430ES1_EN_3D (1 << 2) 369#define OMAP3430ES1_EN_3D_MASK (1 << 2)
370#define OMAP3430ES1_EN_3D_SHIFT 2 370#define OMAP3430ES1_EN_3D_SHIFT 2
371#define OMAP3430ES1_EN_2D (1 << 1) 371#define OMAP3430ES1_EN_2D_MASK (1 << 1)
372#define OMAP3430ES1_EN_2D_SHIFT 1 372#define OMAP3430ES1_EN_2D_SHIFT 1
373 373
374/* CM_ICLKEN_GFX specific bits */ 374/* CM_ICLKEN_GFX specific bits */
@@ -416,9 +416,9 @@
416#define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9) 416#define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9)
417 417
418/* CM_ICLKEN_WKUP specific bits */ 418/* CM_ICLKEN_WKUP specific bits */
419#define OMAP3430_EN_WDT1 (1 << 4) 419#define OMAP3430_EN_WDT1_MASK (1 << 4)
420#define OMAP3430_EN_WDT1_SHIFT 4 420#define OMAP3430_EN_WDT1_SHIFT 4
421#define OMAP3430_EN_32KSYNC (1 << 2) 421#define OMAP3430_EN_32KSYNC_MASK (1 << 2)
422#define OMAP3430_EN_32KSYNC_SHIFT 2 422#define OMAP3430_EN_32KSYNC_SHIFT 2
423 423
424/* CM_IDLEST_WKUP specific bits */ 424/* CM_IDLEST_WKUP specific bits */
@@ -432,19 +432,19 @@
432#define OMAP3430_ST_32KSYNC_MASK (1 << 2) 432#define OMAP3430_ST_32KSYNC_MASK (1 << 2)
433 433
434/* CM_AUTOIDLE_WKUP */ 434/* CM_AUTOIDLE_WKUP */
435#define OMAP3430ES2_AUTO_USIMOCP (1 << 9) 435#define OMAP3430ES2_AUTO_USIMOCP_MASK (1 << 9)
436#define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9 436#define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9
437#define OMAP3430_AUTO_WDT2 (1 << 5) 437#define OMAP3430_AUTO_WDT2_MASK (1 << 5)
438#define OMAP3430_AUTO_WDT2_SHIFT 5 438#define OMAP3430_AUTO_WDT2_SHIFT 5
439#define OMAP3430_AUTO_WDT1 (1 << 4) 439#define OMAP3430_AUTO_WDT1_MASK (1 << 4)
440#define OMAP3430_AUTO_WDT1_SHIFT 4 440#define OMAP3430_AUTO_WDT1_SHIFT 4
441#define OMAP3430_AUTO_GPIO1 (1 << 3) 441#define OMAP3430_AUTO_GPIO1_MASK (1 << 3)
442#define OMAP3430_AUTO_GPIO1_SHIFT 3 442#define OMAP3430_AUTO_GPIO1_SHIFT 3
443#define OMAP3430_AUTO_32KSYNC (1 << 2) 443#define OMAP3430_AUTO_32KSYNC_MASK (1 << 2)
444#define OMAP3430_AUTO_32KSYNC_SHIFT 2 444#define OMAP3430_AUTO_32KSYNC_SHIFT 2
445#define OMAP3430_AUTO_GPT12 (1 << 1) 445#define OMAP3430_AUTO_GPT12_MASK (1 << 1)
446#define OMAP3430_AUTO_GPT12_SHIFT 1 446#define OMAP3430_AUTO_GPT12_SHIFT 1
447#define OMAP3430_AUTO_GPT1 (1 << 0) 447#define OMAP3430_AUTO_GPT1_MASK (1 << 0)
448#define OMAP3430_AUTO_GPT1_SHIFT 0 448#define OMAP3430_AUTO_GPT1_SHIFT 0
449 449
450/* CM_CLKSEL_WKUP */ 450/* CM_CLKSEL_WKUP */
@@ -479,7 +479,7 @@
479#define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) 479#define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0)
480 480
481/* CM_CLKEN2_PLL */ 481/* CM_CLKEN2_PLL */
482#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 482#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10
483#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) 483#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8)
484#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4 484#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4
485#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) 485#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4)
@@ -488,10 +488,10 @@
488#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) 488#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0)
489 489
490/* CM_IDLEST_CKGEN */ 490/* CM_IDLEST_CKGEN */
491#define OMAP3430_ST_54M_CLK (1 << 5) 491#define OMAP3430_ST_54M_CLK_MASK (1 << 5)
492#define OMAP3430_ST_12M_CLK (1 << 4) 492#define OMAP3430_ST_12M_CLK_MASK (1 << 4)
493#define OMAP3430_ST_48M_CLK (1 << 3) 493#define OMAP3430_ST_48M_CLK_MASK (1 << 3)
494#define OMAP3430_ST_96M_CLK (1 << 2) 494#define OMAP3430_ST_96M_CLK_MASK (1 << 2)
495#define OMAP3430_ST_PERIPH_CLK_SHIFT 1 495#define OMAP3430_ST_PERIPH_CLK_SHIFT 1
496#define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) 496#define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1)
497#define OMAP3430_ST_CORE_CLK_SHIFT 0 497#define OMAP3430_ST_CORE_CLK_SHIFT 0
@@ -558,22 +558,22 @@
558 558
559/* CM_CLKOUT_CTRL */ 559/* CM_CLKOUT_CTRL */
560#define OMAP3430_CLKOUT2_EN_SHIFT 7 560#define OMAP3430_CLKOUT2_EN_SHIFT 7
561#define OMAP3430_CLKOUT2_EN (1 << 7) 561#define OMAP3430_CLKOUT2_EN_MASK (1 << 7)
562#define OMAP3430_CLKOUT2_DIV_SHIFT 3 562#define OMAP3430_CLKOUT2_DIV_SHIFT 3
563#define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) 563#define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3)
564#define OMAP3430_CLKOUT2SOURCE_SHIFT 0 564#define OMAP3430_CLKOUT2SOURCE_SHIFT 0
565#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) 565#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0)
566 566
567/* CM_FCLKEN_DSS */ 567/* CM_FCLKEN_DSS */
568#define OMAP3430_EN_TV (1 << 2) 568#define OMAP3430_EN_TV_MASK (1 << 2)
569#define OMAP3430_EN_TV_SHIFT 2 569#define OMAP3430_EN_TV_SHIFT 2
570#define OMAP3430_EN_DSS2 (1 << 1) 570#define OMAP3430_EN_DSS2_MASK (1 << 1)
571#define OMAP3430_EN_DSS2_SHIFT 1 571#define OMAP3430_EN_DSS2_SHIFT 1
572#define OMAP3430_EN_DSS1 (1 << 0) 572#define OMAP3430_EN_DSS1_MASK (1 << 0)
573#define OMAP3430_EN_DSS1_SHIFT 0 573#define OMAP3430_EN_DSS1_SHIFT 0
574 574
575/* CM_ICLKEN_DSS */ 575/* CM_ICLKEN_DSS */
576#define OMAP3430_CM_ICLKEN_DSS_EN_DSS (1 << 0) 576#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK (1 << 0)
577#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 577#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0
578 578
579/* CM_IDLEST_DSS */ 579/* CM_IDLEST_DSS */
@@ -585,7 +585,7 @@
585#define OMAP3430ES1_ST_DSS_MASK (1 << 0) 585#define OMAP3430ES1_ST_DSS_MASK (1 << 0)
586 586
587/* CM_AUTOIDLE_DSS */ 587/* CM_AUTOIDLE_DSS */
588#define OMAP3430_AUTO_DSS (1 << 0) 588#define OMAP3430_AUTO_DSS_MASK (1 << 0)
589#define OMAP3430_AUTO_DSS_SHIFT 0 589#define OMAP3430_AUTO_DSS_SHIFT 0
590 590
591/* CM_CLKSEL_DSS */ 591/* CM_CLKSEL_DSS */
@@ -607,16 +607,16 @@
607#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) 607#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0)
608 608
609/* CM_FCLKEN_CAM specific bits */ 609/* CM_FCLKEN_CAM specific bits */
610#define OMAP3430_EN_CSI2 (1 << 1) 610#define OMAP3430_EN_CSI2_MASK (1 << 1)
611#define OMAP3430_EN_CSI2_SHIFT 1 611#define OMAP3430_EN_CSI2_SHIFT 1
612 612
613/* CM_ICLKEN_CAM specific bits */ 613/* CM_ICLKEN_CAM specific bits */
614 614
615/* CM_IDLEST_CAM */ 615/* CM_IDLEST_CAM */
616#define OMAP3430_ST_CAM (1 << 0) 616#define OMAP3430_ST_CAM_MASK (1 << 0)
617 617
618/* CM_AUTOIDLE_CAM */ 618/* CM_AUTOIDLE_CAM */
619#define OMAP3430_AUTO_CAM (1 << 0) 619#define OMAP3430_AUTO_CAM_MASK (1 << 0)
620#define OMAP3430_AUTO_CAM_SHIFT 0 620#define OMAP3430_AUTO_CAM_SHIFT 0
621 621
622/* CM_CLKSEL_CAM */ 622/* CM_CLKSEL_CAM */
@@ -649,41 +649,41 @@
649#define OMAP3430_ST_MCBSP2_MASK (1 << 0) 649#define OMAP3430_ST_MCBSP2_MASK (1 << 0)
650 650
651/* CM_AUTOIDLE_PER */ 651/* CM_AUTOIDLE_PER */
652#define OMAP3430_AUTO_GPIO6 (1 << 17) 652#define OMAP3430_AUTO_GPIO6_MASK (1 << 17)
653#define OMAP3430_AUTO_GPIO6_SHIFT 17 653#define OMAP3430_AUTO_GPIO6_SHIFT 17
654#define OMAP3430_AUTO_GPIO5 (1 << 16) 654#define OMAP3430_AUTO_GPIO5_MASK (1 << 16)
655#define OMAP3430_AUTO_GPIO5_SHIFT 16 655#define OMAP3430_AUTO_GPIO5_SHIFT 16
656#define OMAP3430_AUTO_GPIO4 (1 << 15) 656#define OMAP3430_AUTO_GPIO4_MASK (1 << 15)
657#define OMAP3430_AUTO_GPIO4_SHIFT 15 657#define OMAP3430_AUTO_GPIO4_SHIFT 15
658#define OMAP3430_AUTO_GPIO3 (1 << 14) 658#define OMAP3430_AUTO_GPIO3_MASK (1 << 14)
659#define OMAP3430_AUTO_GPIO3_SHIFT 14 659#define OMAP3430_AUTO_GPIO3_SHIFT 14
660#define OMAP3430_AUTO_GPIO2 (1 << 13) 660#define OMAP3430_AUTO_GPIO2_MASK (1 << 13)
661#define OMAP3430_AUTO_GPIO2_SHIFT 13 661#define OMAP3430_AUTO_GPIO2_SHIFT 13
662#define OMAP3430_AUTO_WDT3 (1 << 12) 662#define OMAP3430_AUTO_WDT3_MASK (1 << 12)
663#define OMAP3430_AUTO_WDT3_SHIFT 12 663#define OMAP3430_AUTO_WDT3_SHIFT 12
664#define OMAP3430_AUTO_UART3 (1 << 11) 664#define OMAP3430_AUTO_UART3_MASK (1 << 11)
665#define OMAP3430_AUTO_UART3_SHIFT 11 665#define OMAP3430_AUTO_UART3_SHIFT 11
666#define OMAP3430_AUTO_GPT9 (1 << 10) 666#define OMAP3430_AUTO_GPT9_MASK (1 << 10)
667#define OMAP3430_AUTO_GPT9_SHIFT 10 667#define OMAP3430_AUTO_GPT9_SHIFT 10
668#define OMAP3430_AUTO_GPT8 (1 << 9) 668#define OMAP3430_AUTO_GPT8_MASK (1 << 9)
669#define OMAP3430_AUTO_GPT8_SHIFT 9 669#define OMAP3430_AUTO_GPT8_SHIFT 9
670#define OMAP3430_AUTO_GPT7 (1 << 8) 670#define OMAP3430_AUTO_GPT7_MASK (1 << 8)
671#define OMAP3430_AUTO_GPT7_SHIFT 8 671#define OMAP3430_AUTO_GPT7_SHIFT 8
672#define OMAP3430_AUTO_GPT6 (1 << 7) 672#define OMAP3430_AUTO_GPT6_MASK (1 << 7)
673#define OMAP3430_AUTO_GPT6_SHIFT 7 673#define OMAP3430_AUTO_GPT6_SHIFT 7
674#define OMAP3430_AUTO_GPT5 (1 << 6) 674#define OMAP3430_AUTO_GPT5_MASK (1 << 6)
675#define OMAP3430_AUTO_GPT5_SHIFT 6 675#define OMAP3430_AUTO_GPT5_SHIFT 6
676#define OMAP3430_AUTO_GPT4 (1 << 5) 676#define OMAP3430_AUTO_GPT4_MASK (1 << 5)
677#define OMAP3430_AUTO_GPT4_SHIFT 5 677#define OMAP3430_AUTO_GPT4_SHIFT 5
678#define OMAP3430_AUTO_GPT3 (1 << 4) 678#define OMAP3430_AUTO_GPT3_MASK (1 << 4)
679#define OMAP3430_AUTO_GPT3_SHIFT 4 679#define OMAP3430_AUTO_GPT3_SHIFT 4
680#define OMAP3430_AUTO_GPT2 (1 << 3) 680#define OMAP3430_AUTO_GPT2_MASK (1 << 3)
681#define OMAP3430_AUTO_GPT2_SHIFT 3 681#define OMAP3430_AUTO_GPT2_SHIFT 3
682#define OMAP3430_AUTO_MCBSP4 (1 << 2) 682#define OMAP3430_AUTO_MCBSP4_MASK (1 << 2)
683#define OMAP3430_AUTO_MCBSP4_SHIFT 2 683#define OMAP3430_AUTO_MCBSP4_SHIFT 2
684#define OMAP3430_AUTO_MCBSP3 (1 << 1) 684#define OMAP3430_AUTO_MCBSP3_MASK (1 << 1)
685#define OMAP3430_AUTO_MCBSP3_SHIFT 1 685#define OMAP3430_AUTO_MCBSP3_SHIFT 1
686#define OMAP3430_AUTO_MCBSP2 (1 << 0) 686#define OMAP3430_AUTO_MCBSP2_MASK (1 << 0)
687#define OMAP3430_AUTO_MCBSP2_SHIFT 0 687#define OMAP3430_AUTO_MCBSP2_SHIFT 0
688 688
689/* CM_CLKSEL_PER */ 689/* CM_CLKSEL_PER */
@@ -705,7 +705,7 @@
705#define OMAP3430_CLKSEL_GPT2_SHIFT 0 705#define OMAP3430_CLKSEL_GPT2_SHIFT 0
706 706
707/* CM_SLEEPDEP_PER specific bits */ 707/* CM_SLEEPDEP_PER specific bits */
708#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2 (1 << 2) 708#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK (1 << 2)
709 709
710/* CM_CLKSTCTRL_PER */ 710/* CM_CLKSTCTRL_PER */
711#define OMAP3430_CLKTRCTRL_PER_SHIFT 0 711#define OMAP3430_CLKTRCTRL_PER_SHIFT 0
@@ -755,10 +755,10 @@
755#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0) 755#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0)
756 756
757/* CM_POLCTRL */ 757/* CM_POLCTRL */
758#define OMAP3430_CLKOUT2_POL (1 << 0) 758#define OMAP3430_CLKOUT2_POL_MASK (1 << 0)
759 759
760/* CM_IDLEST_NEON */ 760/* CM_IDLEST_NEON */
761#define OMAP3430_ST_NEON (1 << 0) 761#define OMAP3430_ST_NEON_MASK (1 << 0)
762 762
763/* CM_CLKSTCTRL_NEON */ 763/* CM_CLKSTCTRL_NEON */
764#define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 764#define OMAP3430_CLKTRCTRL_NEON_SHIFT 0
diff --git a/arch/arm/mach-omap2/cm.c b/arch/arm/mach-omap2/cm.c
index 58e4a1c557d8..2d83565d2be2 100644
--- a/arch/arm/mach-omap2/cm.c
+++ b/arch/arm/mach-omap2/cm.c
@@ -27,9 +27,6 @@
27#include "cm-regbits-24xx.h" 27#include "cm-regbits-24xx.h"
28#include "cm-regbits-34xx.h" 28#include "cm-regbits-34xx.h"
29 29
30/* MAX_MODULE_READY_TIME: max milliseconds for module to leave idle */
31#define MAX_MODULE_READY_TIME 20000
32
33static const u8 cm_idlest_offs[] = { 30static const u8 cm_idlest_offs[] = {
34 CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 31 CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
35}; 32};
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 94728b1ee3c4..a02ca30423dc 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -112,7 +112,7 @@ extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
112 112
113extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, 113extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
114 u8 idlest_shift); 114 u8 idlest_shift);
115extern int omap4_cm_wait_module_ready(u32 prcm_mod, u8 prcm_dev_offs); 115extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
116 116
117static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) 117static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
118{ 118{
@@ -134,13 +134,23 @@ static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
134 134
135/* CM_ICLKEN_GFX */ 135/* CM_ICLKEN_GFX */
136#define OMAP_EN_GFX_SHIFT 0 136#define OMAP_EN_GFX_SHIFT 0
137#define OMAP_EN_GFX (1 << 0) 137#define OMAP_EN_GFX_MASK (1 << 0)
138 138
139/* CM_IDLEST_GFX */ 139/* CM_IDLEST_GFX */
140#define OMAP_ST_GFX (1 << 0) 140#define OMAP_ST_GFX_MASK (1 << 0)
141
141 142
142/* CM_IDLEST indicator */ 143/* CM_IDLEST indicator */
143#define OMAP24XX_CM_IDLEST_VAL 0 144#define OMAP24XX_CM_IDLEST_VAL 0
144#define OMAP34XX_CM_IDLEST_VAL 1 145#define OMAP34XX_CM_IDLEST_VAL 1
145 146
147/*
148 * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the
149 * PRCM to request that a module exit the inactive state in the case of
150 * OMAP2 & 3.
151 * In the case of OMAP4 this is the max duration in microseconds for the
152 * module to reach the functionnal state from an inactive state.
153 */
154#define MAX_MODULE_READY_TIME 2000
155
146#endif 156#endif
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
index c575b9b0c041..336d94889e5b 100644
--- a/arch/arm/mach-omap2/cm44xx.h
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -1,8 +1,8 @@
1/* 1/*
2 * OMAP44xx CM1 & CM2 instance offset macros 2 * OMAP44xx CM1 & CM2 instance offset macros
3 * 3 *
4 * Copyright (C) 2009 Texas Instruments, Inc. 4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009 Nokia Corporation 5 * Copyright (C) 2009-2010 Nokia Corporation
6 * 6 *
7 * Paul Walmsley (paul@pwsan.com) 7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com) 8 * Rajendra Nayak (rnayak@ti.com)
@@ -25,334 +25,557 @@
25 25
26/* CM1 */ 26/* CM1 */
27 27
28
29/* CM1.OCP_SOCKET_CM1 register offsets */ 28/* CM1.OCP_SOCKET_CM1 register offsets */
29#define OMAP4_REVISION_CM1_OFFSET 0x0000
30#define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0000) 30#define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0000)
31#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040
31#define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0040) 32#define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0040)
32 33
33/* CM1.CKGEN_CM1 register offsets */ 34/* CM1.CKGEN_CM1 register offsets */
35#define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000
34#define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0000) 36#define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0000)
37#define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008
35#define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0008) 38#define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0008)
39#define OMAP4_CM_DLL_CTRL_OFFSET 0x0010
36#define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0010) 40#define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0010)
41#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
37#define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0020) 42#define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0020)
43#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
38#define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0024) 44#define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0024)
45#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
39#define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0028) 46#define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0028)
47#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
40#define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x002c) 48#define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x002c)
49#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
41#define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0030) 50#define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0030)
51#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
42#define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0034) 52#define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0034)
53#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038
43#define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0038) 54#define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0038)
55#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c
44#define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x003c) 56#define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x003c)
57#define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040
45#define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0040) 58#define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0040)
59#define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044
46#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0044) 60#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0044)
61#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
47#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0048) 62#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0048)
63#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
48#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x004c) 64#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x004c)
65#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050
49#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0050) 66#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0050)
67#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
50#define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0060) 68#define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0060)
69#define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
51#define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0064) 70#define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0064)
71#define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
52#define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0068) 72#define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0068)
73#define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
53#define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x006c) 74#define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x006c)
75#define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
54#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0070) 76#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0070)
77#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
55#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0088) 78#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0088)
79#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
56#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x008c) 80#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x008c)
81#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
57#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x009c) 82#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x009c)
83#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
58#define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a0) 84#define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a0)
85#define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
59#define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a4) 86#define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a4)
87#define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
60#define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a8) 88#define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a8)
89#define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
61#define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ac) 90#define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ac)
91#define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8
62#define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00b8) 92#define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00b8)
93#define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc
63#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00bc) 94#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00bc)
95#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
64#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00c8) 96#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00c8)
97#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
65#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00cc) 98#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00cc)
99#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
66#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00dc) 100#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00dc)
101#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
67#define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e0) 102#define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e0)
103#define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
68#define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e4) 104#define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e4)
105#define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
69#define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e8) 106#define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e8)
107#define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
70#define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ec) 108#define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ec)
109#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
71#define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f0) 110#define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f0)
111#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
72#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f4) 112#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f4)
113#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
73#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0108) 114#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0108)
115#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
74#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x010c) 116#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x010c)
117#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120
75#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0120) 118#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0120)
119#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124
76#define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0124) 120#define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0124)
121#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128
77#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0128) 122#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0128)
123#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c
78#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x012c) 124#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x012c)
125#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130
79#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0130) 126#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0130)
127#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138
80#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0138) 128#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0138)
129#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c
81#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x013c) 130#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x013c)
131#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140
82#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0140) 132#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0140)
133#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148
83#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0148) 134#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0148)
135#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
84#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x014c) 136#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x014c)
137#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
85#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0160) 138#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0160)
139#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
86#define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0164) 140#define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0164)
141#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
87#define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0170) 142#define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0170)
143#define OMAP4_CM_RESTORE_ST_OFFSET 0x0180
88#define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0180) 144#define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0180)
89 145
90/* CM1.MPU_CM1 register offsets */ 146/* CM1.MPU_CM1 register offsets */
147#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000
91#define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0000) 148#define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0000)
149#define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004
92#define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0004) 150#define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0004)
151#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008
93#define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0008) 152#define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0008)
153#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
94#define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0020) 154#define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0020)
95 155
96/* CM1.TESLA_CM1 register offsets */ 156/* CM1.TESLA_CM1 register offsets */
157#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000
97#define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0000) 158#define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0000)
159#define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004
98#define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0004) 160#define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0004)
161#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008
99#define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0008) 162#define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0008)
163#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020
100#define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0020) 164#define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0020)
101 165
102/* CM1.ABE_CM1 register offsets */ 166/* CM1.ABE_CM1 register offsets */
167#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000
103#define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0000) 168#define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0000)
169#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020
104#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0020) 170#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0020)
171#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028
105#define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0028) 172#define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0028)
173#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030
106#define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0030) 174#define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0030)
175#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038
107#define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0038) 176#define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0038)
177#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040
108#define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0040) 178#define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0040)
179#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048
109#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0048) 180#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0048)
181#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050
110#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0050) 182#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0050)
183#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058
111#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0058) 184#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0058)
185#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060
112#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0060) 186#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0060)
187#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068
113#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0068) 188#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0068)
189#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070
114#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0070) 190#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0070)
191#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078
115#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0078) 192#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0078)
193#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080
116#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0080) 194#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0080)
195#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
117#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088) 196#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088)
118 197
119/* CM1.RESTORE_CM1 register offsets */
120#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000)
121#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004)
122#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008)
123#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c)
124#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010)
125#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014)
126#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018)
127#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c)
128#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020)
129#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024)
130#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028)
131#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c)
132#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030)
133#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034)
134
135/* CM2 */ 198/* CM2 */
136 199
137
138/* CM2.OCP_SOCKET_CM2 register offsets */ 200/* CM2.OCP_SOCKET_CM2 register offsets */
201#define OMAP4_REVISION_CM2_OFFSET 0x0000
139#define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0000) 202#define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0000)
203#define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET 0x0040
140#define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0040) 204#define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0040)
141 205
142/* CM2.CKGEN_CM2 register offsets */ 206/* CM2.CKGEN_CM2 register offsets */
207#define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET 0x0000
143#define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0000) 208#define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0000)
209#define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004
144#define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0004) 210#define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0004)
211#define OMAP4_CM_SCALE_FCLK_OFFSET 0x0008
145#define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0008) 212#define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0008)
213#define OMAP4_CM_CORE_DVFS_PERF1_OFFSET 0x0010
146#define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0010) 214#define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0010)
215#define OMAP4_CM_CORE_DVFS_PERF2_OFFSET 0x0014
147#define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0014) 216#define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0014)
217#define OMAP4_CM_CORE_DVFS_PERF3_OFFSET 0x0018
148#define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0018) 218#define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0018)
219#define OMAP4_CM_CORE_DVFS_PERF4_OFFSET 0x001c
149#define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x001c) 220#define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x001c)
221#define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET 0x0024
150#define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0024) 222#define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0024)
223#define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET 0x0028
151#define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0028) 224#define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0028)
225#define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET 0x002c
152#define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x002c) 226#define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x002c)
227#define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET 0x0030
153#define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0030) 228#define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0030)
229#define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET 0x0038
154#define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0038) 230#define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0038)
231#define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET 0x0040
155#define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0040) 232#define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0040)
233#define OMAP4_CM_IDLEST_DPLL_PER_OFFSET 0x0044
156#define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0044) 234#define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0044)
235#define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048
157#define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0048) 236#define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0048)
237#define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET 0x004c
158#define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x004c) 238#define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x004c)
239#define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET 0x0050
159#define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0050) 240#define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0050)
241#define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET 0x0054
160#define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0054) 242#define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0054)
243#define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET 0x0058
161#define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0058) 244#define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0058)
245#define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET 0x005c
162#define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x005c) 246#define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x005c)
247#define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET 0x0060
163#define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0060) 248#define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0060)
249#define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET 0x0064
164#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0064) 250#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0064)
251#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068
165#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068) 252#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068)
253#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c
166#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c) 254#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c)
255#define OMAP4_CM_EMU_OVERRIDE_DPLL_PER_OFFSET 0x0070
167#define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070) 256#define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070)
257#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080
168#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080) 258#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080)
259#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084
169#define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0084) 260#define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0084)
261#define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088
170#define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0088) 262#define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0088)
263#define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET 0x008c
171#define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x008c) 264#define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x008c)
265#define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET 0x0090
172#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0090) 266#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0090)
267#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8
173#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00a8) 268#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00a8)
269#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac
174#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ac) 270#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ac)
271#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4
175#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00b4) 272#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00b4)
273#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0
176#define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c0) 274#define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c0)
275#define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET 0x00c4
177#define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c4) 276#define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c4)
277#define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET 0x00c8
178#define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c8) 278#define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c8)
279#define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET 0x00cc
179#define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00cc) 280#define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00cc)
281#define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET 0x00d0
180#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00d0) 282#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00d0)
283#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8
181#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00e8) 284#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00e8)
285#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec
182#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ec) 286#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ec)
183 287
184/* CM2.ALWAYS_ON_CM2 register offsets */ 288/* CM2.ALWAYS_ON_CM2 register offsets */
289#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000
185#define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0000) 290#define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0000)
291#define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET 0x0020
186#define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0020) 292#define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0020)
293#define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET 0x0028
187#define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0028) 294#define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0028)
295#define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET 0x0030
188#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030) 296#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030)
297#define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038
189#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038) 298#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038)
190 299
191/* CM2.CORE_CM2 register offsets */ 300/* CM2.CORE_CM2 register offsets */
301#define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000
192#define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0000) 302#define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0000)
303#define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET 0x0008
193#define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0008) 304#define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0008)
305#define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET 0x0020
194#define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0020) 306#define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0020)
307#define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET 0x0100
195#define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0100) 308#define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0100)
309#define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET 0x0108
196#define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0108) 310#define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0108)
311#define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET 0x0120
197#define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0120) 312#define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0120)
313#define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET 0x0128
198#define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0128) 314#define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0128)
315#define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET 0x0130
199#define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0130) 316#define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0130)
317#define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET 0x0200
200#define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0200) 318#define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0200)
319#define OMAP4_CM_DUCATI_STATICDEP_OFFSET 0x0204
201#define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0204) 320#define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0204)
321#define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET 0x0208
202#define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0208) 322#define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0208)
323#define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET 0x0220
203#define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0220) 324#define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0220)
325#define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET 0x0300
204#define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0300) 326#define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0300)
327#define OMAP4_CM_SDMA_STATICDEP_OFFSET 0x0304
205#define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0304) 328#define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0304)
329#define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET 0x0308
206#define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0308) 330#define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0308)
331#define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET 0x0320
207#define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0320) 332#define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0320)
333#define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET 0x0400
208#define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0400) 334#define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0400)
335#define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET 0x0420
209#define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0420) 336#define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0420)
337#define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET 0x0428
210#define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0428) 338#define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0428)
339#define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET 0x0430
211#define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0430) 340#define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0430)
341#define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET 0x0438
212#define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0438) 342#define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0438)
343#define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET 0x0440
213#define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0440) 344#define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0440)
345#define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET 0x0450
214#define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0450) 346#define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0450)
347#define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET 0x0458
215#define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0458) 348#define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0458)
349#define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET 0x0460
216#define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0460) 350#define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0460)
351#define OMAP4_CM_D2D_CLKSTCTRL_OFFSET 0x0500
217#define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0500) 352#define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0500)
353#define OMAP4_CM_D2D_STATICDEP_OFFSET 0x0504
218#define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0504) 354#define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0504)
355#define OMAP4_CM_D2D_DYNAMICDEP_OFFSET 0x0508
219#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0508) 356#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0508)
357#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520
220#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0520) 358#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0520)
359#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528
221#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0528) 360#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0528)
361#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530
222#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0530) 362#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0530)
363#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
223#define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0600) 364#define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0600)
365#define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608
224#define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0608) 366#define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0608)
367#define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620
225#define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0620) 368#define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0620)
369#define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET 0x0628
226#define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0628) 370#define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0628)
371#define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630
227#define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0630) 372#define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0630)
373#define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638
228#define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0638) 374#define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0638)
375#define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700
229#define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0700) 376#define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0700)
377#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET 0x0720
230#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0720) 378#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0720)
379#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728
231#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0728) 380#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0728)
381#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET 0x0740
232#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0740) 382#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0740)
233 383
234/* CM2.IVAHD_CM2 register offsets */ 384/* CM2.IVAHD_CM2 register offsets */
385#define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET 0x0000
235#define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0000) 386#define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0000)
387#define OMAP4_CM_IVAHD_STATICDEP_OFFSET 0x0004
236#define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0004) 388#define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0004)
389#define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET 0x0008
237#define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0008) 390#define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0008)
391#define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET 0x0020
238#define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0020) 392#define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0020)
393#define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET 0x0028
239#define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0028) 394#define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0028)
240 395
241/* CM2.CAM_CM2 register offsets */ 396/* CM2.CAM_CM2 register offsets */
397#define OMAP4_CM_CAM_CLKSTCTRL_OFFSET 0x0000
242#define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0000) 398#define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0000)
399#define OMAP4_CM_CAM_STATICDEP_OFFSET 0x0004
243#define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0004) 400#define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0004)
401#define OMAP4_CM_CAM_DYNAMICDEP_OFFSET 0x0008
244#define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0008) 402#define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0008)
403#define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020
245#define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0020) 404#define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0020)
405#define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028
246#define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0028) 406#define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0028)
247 407
248/* CM2.DSS_CM2 register offsets */ 408/* CM2.DSS_CM2 register offsets */
409#define OMAP4_CM_DSS_CLKSTCTRL_OFFSET 0x0000
249#define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0000) 410#define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0000)
411#define OMAP4_CM_DSS_STATICDEP_OFFSET 0x0004
250#define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0004) 412#define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0004)
413#define OMAP4_CM_DSS_DYNAMICDEP_OFFSET 0x0008
251#define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0008) 414#define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0008)
415#define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020
252#define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0020) 416#define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0020)
417#define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET 0x0028
253#define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0028) 418#define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0028)
254 419
255/* CM2.GFX_CM2 register offsets */ 420/* CM2.GFX_CM2 register offsets */
421#define OMAP4_CM_GFX_CLKSTCTRL_OFFSET 0x0000
256#define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0000) 422#define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0000)
423#define OMAP4_CM_GFX_STATICDEP_OFFSET 0x0004
257#define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0004) 424#define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0004)
425#define OMAP4_CM_GFX_DYNAMICDEP_OFFSET 0x0008
258#define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0008) 426#define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0008)
427#define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020
259#define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0020) 428#define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0020)
260 429
261/* CM2.L3INIT_CM2 register offsets */ 430/* CM2.L3INIT_CM2 register offsets */
431#define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000
262#define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0000) 432#define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0000)
433#define OMAP4_CM_L3INIT_STATICDEP_OFFSET 0x0004
263#define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0004) 434#define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0004)
435#define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008
264#define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0008) 436#define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0008)
437#define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028
265#define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0028) 438#define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0028)
439#define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030
266#define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0030) 440#define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0030)
441#define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038
267#define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0038) 442#define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0038)
443#define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET 0x0040
268#define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0040) 444#define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0040)
445#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET 0x0058
269#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0058) 446#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0058)
447#define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET 0x0060
270#define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0060) 448#define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0060)
449#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET 0x0068
271#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0068) 450#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0068)
451#define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET 0x0078
272#define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0078) 452#define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0078)
453#define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET 0x0080
273#define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0080) 454#define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0080)
455#define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088
274#define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0088) 456#define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0088)
457#define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET 0x0090
275#define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0090) 458#define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0090)
459#define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET 0x0098
276#define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0098) 460#define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0098)
461#define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET 0x00a8
277#define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00a8) 462#define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00a8)
463#define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET 0x00c0
278#define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c0) 464#define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c0)
465#define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET 0x00c8
279#define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c8) 466#define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c8)
467#define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET 0x00d0
280#define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00d0) 468#define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00d0)
469#define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET 0x00e0
281#define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00e0) 470#define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00e0)
282 471
283/* CM2.L4PER_CM2 register offsets */ 472/* CM2.L4PER_CM2 register offsets */
473#define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET 0x0000
284#define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0000) 474#define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0000)
475#define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET 0x0008
285#define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0008) 476#define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0008)
477#define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET 0x0020
286#define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0020) 478#define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0020)
479#define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET 0x0028
287#define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0028) 480#define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0028)
481#define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET 0x0030
288#define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0030) 482#define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0030)
483#define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET 0x0038
289#define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0038) 484#define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0038)
485#define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET 0x0040
290#define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0040) 486#define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0040)
487#define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET 0x0048
291#define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0048) 488#define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0048)
489#define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET 0x0050
292#define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0050) 490#define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0050)
491#define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058
293#define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0058) 492#define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0058)
493#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060
294#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0060) 494#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0060)
495#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068
295#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0068) 496#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0068)
497#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070
296#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0070) 498#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0070)
499#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078
297#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0078) 500#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0078)
501#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080
298#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0080) 502#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0080)
503#define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088
299#define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0088) 504#define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0088)
505#define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET 0x0090
300#define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0090) 506#define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0090)
507#define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET 0x0098
301#define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0098) 508#define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0098)
509#define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0
302#define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a0) 510#define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a0)
511#define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8
303#define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a8) 512#define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a8)
513#define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0
304#define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b0) 514#define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b0)
515#define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8
305#define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b8) 516#define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b8)
517#define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET 0x00c0
306#define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00c0) 518#define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00c0)
519#define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET 0x00d0
307#define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d0) 520#define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d0)
521#define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET 0x00d8
308#define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d8) 522#define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d8)
523#define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET 0x00e0
309#define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e0) 524#define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e0)
525#define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET 0x00e8
310#define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e8) 526#define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e8)
527#define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0
311#define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f0) 528#define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f0)
529#define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8
312#define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f8) 530#define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f8)
531#define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100
313#define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0100) 532#define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0100)
533#define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108
314#define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0108) 534#define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0108)
535#define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET 0x0120
315#define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0120) 536#define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0120)
537#define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET 0x0128
316#define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0128) 538#define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0128)
539#define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET 0x0130
317#define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0130) 540#define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0130)
541#define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET 0x0138
318#define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0138) 542#define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0138)
543#define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140
319#define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0140) 544#define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0140)
545#define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148
320#define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0148) 546#define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0148)
547#define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150
321#define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0150) 548#define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0150)
549#define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158
322#define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0158) 550#define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0158)
551#define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET 0x0160
323#define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0160) 552#define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0160)
553#define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0168
324#define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0168) 554#define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0168)
555#define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180
325#define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0180) 556#define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0180)
557#define OMAP4_CM_L4SEC_STATICDEP_OFFSET 0x0184
326#define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0184) 558#define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0184)
559#define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188
327#define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0188) 560#define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0188)
561#define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0
328#define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a0) 562#define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a0)
563#define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8
329#define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a8) 564#define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a8)
565#define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0
330#define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b0) 566#define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b0)
567#define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET 0x01b8
331#define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b8) 568#define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b8)
569#define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0
332#define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c0) 570#define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c0)
571#define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8
333#define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c8) 572#define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c8)
573#define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET 0x01d8
334#define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01d8) 574#define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01d8)
335 575
336/* CM2.CEFUSE_CM2 register offsets */ 576/* CM2.CEFUSE_CM2 register offsets */
577#define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000
337#define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000) 578#define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000)
579#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
338#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020) 580#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020)
339
340/* CM2.RESTORE_CM2 register offsets */
341#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000)
342#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004)
343#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008)
344#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c)
345#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010)
346#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014)
347#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018)
348#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c)
349#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020)
350#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024)
351#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028)
352#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c)
353#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030)
354#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034)
355#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038)
356#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c)
357#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040)
358#endif 581#endif
diff --git a/arch/arm/mach-omap2/cm4xxx.c b/arch/arm/mach-omap2/cm4xxx.c
index 4af76bb1003a..b101091e95d6 100644
--- a/arch/arm/mach-omap2/cm4xxx.c
+++ b/arch/arm/mach-omap2/cm4xxx.c
@@ -21,35 +21,41 @@
21 21
22#include <asm/atomic.h> 22#include <asm/atomic.h>
23 23
24#include "cm.h" 24#include <plat/common.h>
25
26/* XXX move this to cm.h */
27/* MAX_MODULE_READY_TIME: max milliseconds for module to leave idle */
28#define MAX_MODULE_READY_TIME 20000
29 25
30/* 26#include "cm.h"
31 * OMAP4_PRCM_CM_CLKCTRL_IDLEST_MASK: isolates the IDLEST field in the 27#include "cm-regbits-44xx.h"
32 * CM_CLKCTRL register.
33 */
34#define OMAP4_PRCM_CM_CLKCTRL_IDLEST_MASK (0x2 << 16)
35
36/*
37 * OMAP4 prcm_mod u32 fields contain packed data: the CM ID in bit 16 and
38 * the PRCM module offset address (from the CM module base) in bits 15-0.
39 */
40#define OMAP4_PRCM_MOD_CM_ID_SHIFT 16
41#define OMAP4_PRCM_MOD_OFFS_MASK 0xffff
42 28
43/** 29/**
44 * omap4_cm_wait_idlest_ready - wait for a module to leave idle or standby 30 * omap4_cm_wait_module_ready - wait for a module to be in 'func' state
45 * @prcm_mod: PRCM module offset (XXX example) 31 * @clkctrl_reg: CLKCTRL module address
46 * @prcm_dev_offs: PRCM device offset (e.g. MCASP XXX example) 32 *
33 * Wait for the module IDLEST to be functional. If the idle state is in any
34 * the non functional state (trans, idle or disabled), module and thus the
35 * sysconfig cannot be accessed and will probably lead to an "imprecise
36 * external abort"
37 *
38 * Module idle state:
39 * 0x0 func: Module is fully functional, including OCP
40 * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep
41 * abortion
42 * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if
43 * using separate functional clock
44 * 0x3 disabled: Module is disabled and cannot be accessed
47 * 45 *
48 * XXX document 46 * TODO: Need to handle module accessible in idle state
49 */ 47 */
50int omap4_cm_wait_idlest_ready(u32 prcm_mod, u8 prcm_dev_offs) 48int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg)
51{ 49{
52 /* FIXME: Add clock manager related code */ 50 int i = 0;
53 return 0; 51
52 if (!clkctrl_reg)
53 return 0;
54
55 omap_test_timeout(((__raw_readl(clkctrl_reg) &
56 OMAP4430_IDLEST_MASK) == 0),
57 MAX_MODULE_READY_TIME, i);
58
59 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
54} 60}
55 61
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 43f8a33655d4..a8d20eef2306 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -194,11 +194,12 @@ void omap3_clear_scratchpad_contents(void)
194 u32 offset = 0; 194 u32 offset = 0;
195 v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); 195 v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
196 if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & 196 if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
197 OMAP3430_GLOBAL_COLD_RST) { 197 OMAP3430_GLOBAL_COLD_RST_MASK) {
198 for ( ; offset <= max_offset; offset += 0x4) 198 for ( ; offset <= max_offset; offset += 0x4)
199 __raw_writel(0x0, (v_addr + offset)); 199 __raw_writel(0x0, (v_addr + offset));
200 prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST, OMAP3430_GR_MOD, 200 prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
201 OMAP3_PRM_RSTST_OFFSET); 201 OMAP3430_GR_MOD,
202 OMAP3_PRM_RSTST_OFFSET);
202 } 203 }
203} 204}
204 205
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 12154d10e536..705a7a30a87f 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -624,6 +624,15 @@ static inline void omap_hsmmc_reset(void) {}
624static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, 624static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
625 int controller_nr) 625 int controller_nr)
626{ 626{
627 if ((mmc_controller->slots[0].switch_pin > 0) && \
628 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
629 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
630 OMAP_PIN_INPUT_PULLUP);
631 if ((mmc_controller->slots[0].gpio_wp > 0) && \
632 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
633 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
634 OMAP_PIN_INPUT_PULLUP);
635
627 if (cpu_is_omap2420() && controller_nr == 0) { 636 if (cpu_is_omap2420() && controller_nr == 0) {
628 omap_cfg_reg(H18_24XX_MMC_CMD); 637 omap_cfg_reg(H18_24XX_MMC_CMD);
629 omap_cfg_reg(H15_24XX_MMC_CLKI); 638 omap_cfg_reg(H15_24XX_MMC_CLKI);
@@ -819,6 +828,33 @@ static inline void omap_hdq_init(void)
819static inline void omap_hdq_init(void) {} 828static inline void omap_hdq_init(void) {}
820#endif 829#endif
821 830
831/*---------------------------------------------------------------------------*/
832
833#if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
834 defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
835#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
836static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
837};
838#else
839static struct resource omap_vout_resource[2] = {
840};
841#endif
842
843static struct platform_device omap_vout_device = {
844 .name = "omap_vout",
845 .num_resources = ARRAY_SIZE(omap_vout_resource),
846 .resource = &omap_vout_resource[0],
847 .id = -1,
848};
849static void omap_init_vout(void)
850{
851 if (platform_device_register(&omap_vout_device) < 0)
852 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
853}
854#else
855static inline void omap_init_vout(void) {}
856#endif
857
822/*-------------------------------------------------------------------------*/ 858/*-------------------------------------------------------------------------*/
823 859
824static int __init omap2_init_devices(void) 860static int __init omap2_init_devices(void)
@@ -834,6 +870,7 @@ static int __init omap2_init_devices(void)
834 omap_hdq_init(); 870 omap_hdq_init();
835 omap_init_sti(); 871 omap_init_sti();
836 omap_init_sha1_md5(); 872 omap_init_sha1_md5();
873 omap_init_vout();
837 874
838 return 0; 875 return 0;
839} 876}
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 9ad229594b46..1ef54b036103 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -24,6 +24,7 @@
24 24
25static u16 control_pbias_offset; 25static u16 control_pbias_offset;
26static u16 control_devconf1_offset; 26static u16 control_devconf1_offset;
27static u16 control_mmc1;
27 28
28#define HSMMC_NAME_LEN 9 29#define HSMMC_NAME_LEN 9
29 30
@@ -42,7 +43,7 @@ static int hsmmc_get_context_loss(struct device *dev)
42#define hsmmc_get_context_loss NULL 43#define hsmmc_get_context_loss NULL
43#endif 44#endif
44 45
45static void hsmmc1_before_set_reg(struct device *dev, int slot, 46static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
46 int power_on, int vdd) 47 int power_on, int vdd)
47{ 48{
48 u32 reg, prog_io; 49 u32 reg, prog_io;
@@ -95,7 +96,7 @@ static void hsmmc1_before_set_reg(struct device *dev, int slot,
95 } 96 }
96} 97}
97 98
98static void hsmmc1_after_set_reg(struct device *dev, int slot, 99static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
99 int power_on, int vdd) 100 int power_on, int vdd)
100{ 101{
101 u32 reg; 102 u32 reg;
@@ -119,6 +120,60 @@ static void hsmmc1_after_set_reg(struct device *dev, int slot,
119 } 120 }
120} 121}
121 122
123static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
124 int power_on, int vdd)
125{
126 u32 reg;
127
128 /*
129 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
130 * card with Vcc regulator (from twl4030 or whatever). OMAP has both
131 * 1.8V and 3.0V modes, controlled by the PBIAS register.
132 *
133 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
134 * is most naturally TWL VSIM; those pins also use PBIAS.
135 *
136 * FIXME handle VMMC1A as needed ...
137 */
138 reg = omap_ctrl_readl(control_pbias_offset);
139 reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ |
140 OMAP4_USBC1_ICUSB_PWRDNZ);
141 omap_ctrl_writel(reg, control_pbias_offset);
142}
143
144static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
145 int power_on, int vdd)
146{
147 u32 reg;
148
149 if (power_on) {
150 reg = omap_ctrl_readl(control_pbias_offset);
151 reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ;
152 if ((1 << vdd) <= MMC_VDD_165_195)
153 reg &= ~OMAP4_MMC1_PBIASLITE_VMODE;
154 else
155 reg |= OMAP4_MMC1_PBIASLITE_VMODE;
156 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ |
157 OMAP4_USBC1_ICUSB_PWRDNZ);
158 omap_ctrl_writel(reg, control_pbias_offset);
159 /* 4 microsec delay for comparator to generate an error*/
160 udelay(4);
161 reg = omap_ctrl_readl(control_pbias_offset);
162 if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR) {
163 pr_err("Pbias Voltage is not same as LDO\n");
164 /* Caution : On VMODE_ERROR Power Down MMC IO */
165 reg &= ~(OMAP4_MMC1_PWRDNZ | OMAP4_USBC1_ICUSB_PWRDNZ);
166 omap_ctrl_writel(reg, control_pbias_offset);
167 }
168 } else {
169 reg = omap_ctrl_readl(control_pbias_offset);
170 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ |
171 OMAP4_MMC1_PBIASLITE_VMODE | OMAP4_MMC1_PWRDNZ |
172 OMAP4_USBC1_ICUSB_PWRDNZ);
173 omap_ctrl_writel(reg, control_pbias_offset);
174 }
175}
176
122static void hsmmc23_before_set_reg(struct device *dev, int slot, 177static void hsmmc23_before_set_reg(struct device *dev, int slot,
123 int power_on, int vdd) 178 int power_on, int vdd)
124{ 179{
@@ -139,6 +194,12 @@ static void hsmmc23_before_set_reg(struct device *dev, int slot,
139 } 194 }
140} 195}
141 196
197static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
198 int vdd)
199{
200 return 0;
201}
202
142static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; 203static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;
143 204
144void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) 205void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
@@ -146,13 +207,28 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
146 struct omap2_hsmmc_info *c; 207 struct omap2_hsmmc_info *c;
147 int nr_hsmmc = ARRAY_SIZE(hsmmc_data); 208 int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
148 int i; 209 int i;
210 u32 reg;
149 211
150 if (cpu_is_omap2430()) { 212 if (!cpu_is_omap44xx()) {
151 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; 213 if (cpu_is_omap2430()) {
152 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; 214 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
215 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
216 } else {
217 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
218 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
219 }
153 } else { 220 } else {
154 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; 221 control_pbias_offset = OMAP44XX_CONTROL_PBIAS_LITE;
155 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; 222 control_mmc1 = OMAP44XX_CONTROL_MMC1;
223 reg = omap_ctrl_readl(control_mmc1);
224 reg |= (OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 |
225 OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1);
226 reg &= ~(OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 |
227 OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3);
228 reg |= (OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL |
229 OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL |
230 OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL);
231 omap_ctrl_writel(reg, control_mmc1);
156 } 232 }
157 233
158 for (c = controllers; c->mmc; c++) { 234 for (c = controllers; c->mmc; c++) {
@@ -216,11 +292,27 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
216 */ 292 */
217 mmc->slots[0].ocr_mask = c->ocr_mask; 293 mmc->slots[0].ocr_mask = c->ocr_mask;
218 294
295 if (cpu_is_omap3517() || cpu_is_omap3505())
296 mmc->slots[0].set_power = nop_mmc_set_power;
297 else
298 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
299
219 switch (c->mmc) { 300 switch (c->mmc) {
220 case 1: 301 case 1:
221 /* on-chip level shifting via PBIAS0/PBIAS1 */ 302 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
222 mmc->slots[0].before_set_reg = hsmmc1_before_set_reg; 303 /* on-chip level shifting via PBIAS0/PBIAS1 */
223 mmc->slots[0].after_set_reg = hsmmc1_after_set_reg; 304 if (cpu_is_omap44xx()) {
305 mmc->slots[0].before_set_reg =
306 omap4_hsmmc1_before_set_reg;
307 mmc->slots[0].after_set_reg =
308 omap4_hsmmc1_after_set_reg;
309 } else {
310 mmc->slots[0].before_set_reg =
311 omap_hsmmc1_before_set_reg;
312 mmc->slots[0].after_set_reg =
313 omap_hsmmc1_after_set_reg;
314 }
315 }
224 316
225 /* Omap3630 HSMMC1 supports only 4-bit */ 317 /* Omap3630 HSMMC1 supports only 4-bit */
226 if (cpu_is_omap3630() && c->wires > 4) { 318 if (cpu_is_omap3630() && c->wires > 4) {
@@ -235,9 +327,11 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
235 c->wires = 4; 327 c->wires = 4;
236 /* FALLTHROUGH */ 328 /* FALLTHROUGH */
237 case 3: 329 case 3:
238 /* off-chip level shifting, or none */ 330 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
239 mmc->slots[0].before_set_reg = hsmmc23_before_set_reg; 331 /* off-chip level shifting, or none */
240 mmc->slots[0].after_set_reg = NULL; 332 mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
333 mmc->slots[0].after_set_reg = NULL;
334 }
241 break; 335 break;
242 default: 336 default:
243 pr_err("MMC%d configuration not supported!\n", c->mmc); 337 pr_err("MMC%d configuration not supported!\n", c->mmc);
diff --git a/arch/arm/mach-omap2/include/mach/am35xx.h b/arch/arm/mach-omap2/include/mach/am35xx.h
index a705f946fc46..f1e13d1ca5e7 100644
--- a/arch/arm/mach-omap2/include/mach/am35xx.h
+++ b/arch/arm/mach-omap2/include/mach/am35xx.h
@@ -23,4 +23,22 @@
23#define AM35XX_IPSS_HECC_BASE 0x5C050000 23#define AM35XX_IPSS_HECC_BASE 0x5C050000
24#define AM35XX_IPSS_VPFE_BASE 0x5C060000 24#define AM35XX_IPSS_VPFE_BASE 0x5C060000
25 25
26#endif /* __ASM_ARCH_AM35XX_H */ 26
27/* HECC module specifc offset definitions */
28#define AM35XX_HECC_SCC_HECC_OFFSET (0x0)
29#define AM35XX_HECC_SCC_RAM_OFFSET (0x3000)
30#define AM35XX_HECC_RAM_OFFSET (0x3000)
31#define AM35XX_HECC_MBOX_OFFSET (0x2000)
32#define AM35XX_HECC_INT_LINE (0x0)
33#define AM35XX_HECC_VERSION (0x1)
34
35#define AM35XX_EMAC_CNTRL_OFFSET (0x10000)
36#define AM35XX_EMAC_CNTRL_MOD_OFFSET (0x0)
37#define AM35XX_EMAC_CNTRL_RAM_OFFSET (0x20000)
38#define AM35XX_EMAC_MDIO_OFFSET (0x30000)
39#define AM35XX_EMAC_CNTRL_RAM_SIZE (0x2000)
40#define AM35XX_EMAC_RAM_ADDR (AM3517_EMAC_BASE + \
41 AM3517_EMAC_CNTRL_RAM_OFFSET)
42#define AM35XX_EMAC_HW_RAM_ADDR (0x01E20000)
43
44#endif /* __ASM_ARCH_AM35XX_H */
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index 4a63a2ea484d..35b24409a0c8 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -13,6 +13,8 @@
13 13
14#include <linux/serial_reg.h> 14#include <linux/serial_reg.h>
15 15
16#include <asm/memory.h>
17
16#include <plat/serial.h> 18#include <plat/serial.h>
17 19
18#define UART_OFFSET(addr) ((addr) & 0x00ffffff) 20#define UART_OFFSET(addr) ((addr) & 0x00ffffff)
@@ -40,13 +42,12 @@ omap_uart_lsr: .word 0
40 cmp \rx, #0 @ is port configured? 42 cmp \rx, #0 @ is port configured?
41 bne 99f @ already configured 43 bne 99f @ already configured
42 44
43 /* Check UART1 scratchpad register for uart to use */ 45 /* Check the debug UART configuration set in uncompress.h */
44 mrc p15, 0, \rx, c1, c0 46 mrc p15, 0, \rx, c1, c0
45 tst \rx, #1 @ MMU enabled? 47 tst \rx, #1 @ MMU enabled?
46 moveq \rx, #0x48000000 @ physical base address 48 ldreq \rx, =OMAP_UART_INFO
47 movne \rx, #0xfa000000 @ virtual base 49 ldrne \rx, =__phys_to_virt(OMAP_UART_INFO)
48 orr \rx, \rx, #0x0006a000 @ uart1 on omap2/3/4 50 ldr \rx, [\rx, #0]
49 ldrb \rx, [\rx, #(UART_SCR << OMAP_PORT_SHIFT)] @ scratchpad
50 51
51 /* Select the UART to use based on the UART1 scratchpad value */ 52 /* Select the UART to use based on the UART1 scratchpad value */
52 cmp \rx, #0 @ no port configured? 53 cmp \rx, #0 @ no port configured?
@@ -87,10 +88,10 @@ omap_uart_lsr: .word 0
87 b 98f 88 b 98f
8844: mov \rx, #UART_OFFSET(OMAP4_UART4_BASE) 8944: mov \rx, #UART_OFFSET(OMAP4_UART4_BASE)
89 b 98f 90 b 98f
9095: mov \rx, #ZOOM_UART_BASE 9195: ldr \rx, =ZOOM_UART_BASE
91 ldr \tmp, =omap_uart_phys 92 ldr \tmp, =omap_uart_phys
92 str \rx, [\tmp, #0] 93 str \rx, [\tmp, #0]
93 mov \rx, #ZOOM_UART_VIRT 94 ldr \rx, =ZOOM_UART_VIRT
94 ldr \tmp, =omap_uart_virt 95 ldr \tmp, =omap_uart_virt
95 str \rx, [\tmp, #0] 96 str \rx, [\tmp, #0]
96 mov \rx, #(UART_LSR << ZOOM_PORT_SHIFT) 97 mov \rx, #(UART_LSR << ZOOM_PORT_SHIFT)
diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h
new file mode 100644
index 000000000000..423af3a6dd31
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/omap4-common.h
@@ -0,0 +1,26 @@
1/*
2 * omap4-common.h: OMAP4 specific common header file
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc.
5 *
6 * Author:
7 * Santosh Shilimkar <santosh.shilimkar@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifndef OMAP_ARCH_OMAP4_COMMON_H
14#define OMAP_ARCH_OMAP4_COMMON_H
15
16#ifdef CONFIG_CACHE_L2X0
17extern void __iomem *l2cache_base;
18#endif
19
20extern void __iomem *gic_cpu_base_addr;
21extern void __iomem *gic_dist_base_addr;
22
23extern void __init gic_init_irq(void);
24extern void omap_smc1(u32 fn, u32 arg);
25
26#endif
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 87f676acf61d..3cfb425ea67e 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -166,6 +166,15 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
166 .length = L4_EMU_34XX_SIZE, 166 .length = L4_EMU_34XX_SIZE,
167 .type = MT_DEVICE 167 .type = MT_DEVICE
168 }, 168 },
169#if defined(CONFIG_DEBUG_LL) && \
170 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
171 {
172 .virtual = ZOOM_UART_VIRT,
173 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
174 .length = SZ_1M,
175 .type = MT_DEVICE
176 },
177#endif
169}; 178};
170#endif 179#endif
171#ifdef CONFIG_ARCH_OMAP4 180#ifdef CONFIG_ARCH_OMAP4
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index 4f63dc6859a4..e82da680d908 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -147,6 +147,7 @@ static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
147 printk("\n"); 147 printk("\n");
148 148
149 iommu_write_reg(obj, stat, MMU_IRQSTATUS); 149 iommu_write_reg(obj, stat, MMU_IRQSTATUS);
150 omap2_iommu_disable(obj);
150 return stat; 151 return stat;
151} 152}
152 153
@@ -184,7 +185,7 @@ static struct cr_regs *omap2_alloc_cr(struct iommu *obj, struct iotlb_entry *e)
184 if (!cr) 185 if (!cr)
185 return ERR_PTR(-ENOMEM); 186 return ERR_PTR(-ENOMEM);
186 187
187 cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz; 188 cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid;
188 cr->ram = e->pa | e->endian | e->elsz | e->mixed; 189 cr->ram = e->pa | e->endian | e->elsz | e->mixed;
189 190
190 return cr; 191 return cr;
@@ -212,7 +213,8 @@ static ssize_t omap2_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf)
212 char *p = buf; 213 char *p = buf;
213 214
214 /* FIXME: Need more detail analysis of cam/ram */ 215 /* FIXME: Need more detail analysis of cam/ram */
215 p += sprintf(p, "%08x %08x\n", cr->cam, cr->ram); 216 p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram,
217 (cr->cam & MMU_CAM_P) ? 1 : 0);
216 218
217 return p - buf; 219 return p - buf;
218} 220}
diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c
index 07aa7b3c95f7..2ff4dce95ee8 100644
--- a/arch/arm/mach-omap2/mux34xx.c
+++ b/arch/arm/mach-omap2/mux34xx.c
@@ -1901,26 +1901,15 @@ struct omap_ball __initdata omap36xx_cbp_ball[] = {
1901 _OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"), 1901 _OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"),
1902 _OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"), 1902 _OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"),
1903 _OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"), 1903 _OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"),
1904 _OMAP3_BALLENTRY(GPMC_D0, "k1", "m2"),
1905 _OMAP3_BALLENTRY(GPMC_D1, "l1", "m1"),
1906 _OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"), 1904 _OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"),
1907 _OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"), 1905 _OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"),
1908 _OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"), 1906 _OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"),
1909 _OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"), 1907 _OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"),
1910 _OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"), 1908 _OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"),
1911 _OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"), 1909 _OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"),
1912 _OMAP3_BALLENTRY(GPMC_D2, "l2", "n2"),
1913 _OMAP3_BALLENTRY(GPMC_D3, "p2", "n1"),
1914 _OMAP3_BALLENTRY(GPMC_D4, "t1", "r2"),
1915 _OMAP3_BALLENTRY(GPMC_D5, "v1", "r1"),
1916 _OMAP3_BALLENTRY(GPMC_D6, "v2", "t2"),
1917 _OMAP3_BALLENTRY(GPMC_D7, "w2", "t1"),
1918 _OMAP3_BALLENTRY(GPMC_D8, "h2", "ab3"),
1919 _OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"), 1910 _OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"),
1920 _OMAP3_BALLENTRY(GPMC_NADV_ALE, "f3", "w1"),
1921 _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"), 1911 _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"),
1922 _OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL), 1912 _OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL),
1923 _OMAP3_BALLENTRY(GPMC_NCS0, "g4", "y2"),
1924 _OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"), 1913 _OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"),
1925 _OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL), 1914 _OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL),
1926 _OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL), 1915 _OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL),
@@ -1928,10 +1917,7 @@ struct omap_ball __initdata omap36xx_cbp_ball[] = {
1928 _OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL), 1917 _OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL),
1929 _OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL), 1918 _OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL),
1930 _OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL), 1919 _OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL),
1931 _OMAP3_BALLENTRY(GPMC_NOE, "g2", "v2"),
1932 _OMAP3_BALLENTRY(GPMC_NWE, "f4", "v1"),
1933 _OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"), 1920 _OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"),
1934 _OMAP3_BALLENTRY(GPMC_WAIT0, "m8", "ab12"),
1935 _OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"), 1921 _OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"),
1936 _OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL), 1922 _OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL),
1937 _OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL), 1923 _OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL),
@@ -1948,8 +1934,6 @@ struct omap_ball __initdata omap36xx_cbp_ball[] = {
1948 _OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL), 1934 _OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL),
1949 _OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL), 1935 _OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL),
1950 _OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL), 1936 _OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL),
1951 _OMAP3_BALLENTRY(I2C1_SCL, "k21", NULL),
1952 _OMAP3_BALLENTRY(I2C1_SDA, "j21", NULL),
1953 _OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL), 1937 _OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL),
1954 _OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL), 1938 _OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL),
1955 _OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL), 1939 _OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL),
@@ -1958,11 +1942,6 @@ struct omap_ball __initdata omap36xx_cbp_ball[] = {
1958 _OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL), 1942 _OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL),
1959 _OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL), 1943 _OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL),
1960 _OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL), 1944 _OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL),
1961 _OMAP3_BALLENTRY(JTAG_RTCK, "aa12", NULL),
1962 _OMAP3_BALLENTRY(JTAG_TCK, "aa13", NULL),
1963 _OMAP3_BALLENTRY(JTAG_TDI, "aa20", NULL),
1964 _OMAP3_BALLENTRY(JTAG_TDO, "aa19", NULL),
1965 _OMAP3_BALLENTRY(JTAG_TMS_TMSC, "aa18", NULL),
1966 _OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL), 1945 _OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL),
1967 _OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL), 1946 _OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL),
1968 _OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL), 1947 _OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL),
@@ -2010,77 +1989,12 @@ struct omap_ball __initdata omap36xx_cbp_ball[] = {
2010 _OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL), 1989 _OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL),
2011 _OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL), 1990 _OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL),
2012 _OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL), 1991 _OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL),
2013 _OMAP3_BALLENTRY(SDRC_A0, NULL, "n22"),
2014 _OMAP3_BALLENTRY(SDRC_A1, NULL, "n23"),
2015 _OMAP3_BALLENTRY(SDRC_A10, NULL, "v22"),
2016 _OMAP3_BALLENTRY(SDRC_A11, NULL, "v23"),
2017 _OMAP3_BALLENTRY(SDRC_A12, NULL, "w22"),
2018 _OMAP3_BALLENTRY(SDRC_A13, NULL, "w23"),
2019 _OMAP3_BALLENTRY(SDRC_A14, NULL, "y22"),
2020 _OMAP3_BALLENTRY(SDRC_A2, NULL, "p22"),
2021 _OMAP3_BALLENTRY(SDRC_A3, NULL, "p23"),
2022 _OMAP3_BALLENTRY(SDRC_A4, NULL, "r22"),
2023 _OMAP3_BALLENTRY(SDRC_A5, NULL, "r23"),
2024 _OMAP3_BALLENTRY(SDRC_A6, NULL, "t22"),
2025 _OMAP3_BALLENTRY(SDRC_A7, NULL, "t23"),
2026 _OMAP3_BALLENTRY(SDRC_A8, NULL, "u22"),
2027 _OMAP3_BALLENTRY(SDRC_A9, NULL, "u23"),
2028 _OMAP3_BALLENTRY(SDRC_BA0, "h9", "ab21"),
2029 _OMAP3_BALLENTRY(SDRC_BA1, "h10", "ac21"),
2030 _OMAP3_BALLENTRY(SDRC_CKE0, "h16", "j22"), 1992 _OMAP3_BALLENTRY(SDRC_CKE0, "h16", "j22"),
2031 _OMAP3_BALLENTRY(SDRC_CKE1, "h17", "j23"), 1993 _OMAP3_BALLENTRY(SDRC_CKE1, "h17", "j23"),
2032 _OMAP3_BALLENTRY(SDRC_CLK, "a13", "a11"),
2033 _OMAP3_BALLENTRY(SDRC_D0, NULL, "j2"),
2034 _OMAP3_BALLENTRY(SDRC_D1, NULL, "j1"),
2035 _OMAP3_BALLENTRY(SDRC_D10, "c15", "b14"),
2036 _OMAP3_BALLENTRY(SDRC_D11, "b16", "a14"),
2037 _OMAP3_BALLENTRY(SDRC_D12, "d17", "b16"),
2038 _OMAP3_BALLENTRY(SDRC_D13, "c17", "a16"),
2039 _OMAP3_BALLENTRY(SDRC_D14, "b17", "b19"),
2040 _OMAP3_BALLENTRY(SDRC_D15, "d18", "a19"),
2041 _OMAP3_BALLENTRY(SDRC_D16, NULL, "b3"),
2042 _OMAP3_BALLENTRY(SDRC_D17, NULL, "a3"),
2043 _OMAP3_BALLENTRY(SDRC_D18, NULL, "b5"),
2044 _OMAP3_BALLENTRY(SDRC_D19, NULL, "a5"),
2045 _OMAP3_BALLENTRY(SDRC_D2, NULL, "g2"),
2046 _OMAP3_BALLENTRY(SDRC_D20, NULL, "b8"),
2047 _OMAP3_BALLENTRY(SDRC_D21, NULL, "a8"),
2048 _OMAP3_BALLENTRY(SDRC_D22, NULL, "b9"),
2049 _OMAP3_BALLENTRY(SDRC_D23, NULL, "a9"),
2050 _OMAP3_BALLENTRY(SDRC_D24, NULL, "b21"),
2051 _OMAP3_BALLENTRY(SDRC_D25, NULL, "a21"),
2052 _OMAP3_BALLENTRY(SDRC_D26, NULL, "d22"),
2053 _OMAP3_BALLENTRY(SDRC_D27, NULL, "d23"),
2054 _OMAP3_BALLENTRY(SDRC_D28, NULL, "e22"),
2055 _OMAP3_BALLENTRY(SDRC_D29, NULL, "e23"),
2056 _OMAP3_BALLENTRY(SDRC_D3, NULL, "g1"),
2057 _OMAP3_BALLENTRY(SDRC_D30, NULL, "g22"),
2058 _OMAP3_BALLENTRY(SDRC_D31, NULL, "g23"),
2059 _OMAP3_BALLENTRY(SDRC_D4, NULL, "f2"),
2060 _OMAP3_BALLENTRY(SDRC_D5, NULL, "f1"),
2061 _OMAP3_BALLENTRY(SDRC_D6, NULL, "d2"),
2062 _OMAP3_BALLENTRY(SDRC_D7, NULL, "d1"),
2063 _OMAP3_BALLENTRY(SDRC_D8, "c14", "b13"),
2064 _OMAP3_BALLENTRY(SDRC_D9, "b14", "a13"),
2065 _OMAP3_BALLENTRY(SDRC_DM0, NULL, "c1"),
2066 _OMAP3_BALLENTRY(SDRC_DM1, "a16", "a17"),
2067 _OMAP3_BALLENTRY(SDRC_DM2, NULL, "a6"),
2068 _OMAP3_BALLENTRY(SDRC_DM3, NULL, "a20"),
2069 _OMAP3_BALLENTRY(SDRC_DQS0, NULL, "c2"),
2070 _OMAP3_BALLENTRY(SDRC_DQS1, "a17", "b17"),
2071 _OMAP3_BALLENTRY(SDRC_DQS2, NULL, "b6"),
2072 _OMAP3_BALLENTRY(SDRC_DQS3, NULL, "b20"),
2073 _OMAP3_BALLENTRY(SDRC_NCAS, "h13", "l22"),
2074 _OMAP3_BALLENTRY(SDRC_NCLK, "a14", "b11"),
2075 _OMAP3_BALLENTRY(SDRC_NCS0, "h11", "m22"),
2076 _OMAP3_BALLENTRY(SDRC_NCS1, "h12", "m23"),
2077 _OMAP3_BALLENTRY(SDRC_NRAS, "h14", "l23"),
2078 _OMAP3_BALLENTRY(SDRC_NWE, "h15", "k23"),
2079 _OMAP3_BALLENTRY(SIM_CLK, "p26", NULL), 1994 _OMAP3_BALLENTRY(SIM_CLK, "p26", NULL),
2080 _OMAP3_BALLENTRY(SIM_IO, "p27", NULL), 1995 _OMAP3_BALLENTRY(SIM_IO, "p27", NULL),
2081 _OMAP3_BALLENTRY(SIM_PWRCTRL, "r27", NULL), 1996 _OMAP3_BALLENTRY(SIM_PWRCTRL, "r27", NULL),
2082 _OMAP3_BALLENTRY(SIM_RST, "r25", NULL), 1997 _OMAP3_BALLENTRY(SIM_RST, "r25", NULL),
2083 _OMAP3_BALLENTRY(SYS_32K, "ae25", NULL),
2084 _OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL), 1998 _OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL),
2085 _OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL), 1999 _OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL),
2086 _OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL), 2000 _OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL),
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
new file mode 100644
index 000000000000..eb9bee73e0cb
--- /dev/null
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -0,0 +1,157 @@
1/*
2 * omap iommu: omap device registration
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/platform_device.h>
14
15#include <plat/iommu.h>
16#include <plat/irqs.h>
17
18struct iommu_device {
19 resource_size_t base;
20 int irq;
21 struct iommu_platform_data pdata;
22 struct resource res[2];
23};
24static struct iommu_device *devices;
25static int num_iommu_devices;
26
27#ifdef CONFIG_ARCH_OMAP3
28static struct iommu_device omap3_devices[] = {
29 {
30 .base = 0x480bd400,
31 .irq = 24,
32 .pdata = {
33 .name = "isp",
34 .nr_tlb_entries = 8,
35 .clk_name = "cam_ick",
36 },
37 },
38#if defined(CONFIG_MPU_BRIDGE_IOMMU)
39 {
40 .base = 0x5d000000,
41 .irq = 28,
42 .pdata = {
43 .name = "iva2",
44 .nr_tlb_entries = 32,
45 .clk_name = "iva2_ck",
46 },
47 },
48#endif
49};
50#define NR_OMAP3_IOMMU_DEVICES ARRAY_SIZE(omap3_devices)
51static struct platform_device *omap3_iommu_pdev[NR_OMAP3_IOMMU_DEVICES];
52#else
53#define omap3_devices NULL
54#define NR_OMAP3_IOMMU_DEVICES 0
55#define omap3_iommu_pdev NULL
56#endif
57
58#ifdef CONFIG_ARCH_OMAP4
59static struct iommu_device omap4_devices[] = {
60 {
61 .base = OMAP4_MMU1_BASE,
62 .irq = INT_44XX_DUCATI_MMU_IRQ,
63 .pdata = {
64 .name = "ducati",
65 .nr_tlb_entries = 32,
66 .clk_name = "ducati_ick",
67 },
68 },
69#if defined(CONFIG_MPU_TESLA_IOMMU)
70 {
71 .base = OMAP4_MMU2_BASE,
72 .irq = INT_44XX_DSP_MMU,
73 .pdata = {
74 .name = "tesla",
75 .nr_tlb_entries = 32,
76 .clk_name = "tesla_ick",
77 },
78 },
79#endif
80};
81#define NR_OMAP4_IOMMU_DEVICES ARRAY_SIZE(omap4_devices)
82static struct platform_device *omap4_iommu_pdev[NR_OMAP4_IOMMU_DEVICES];
83#else
84#define omap4_devices NULL
85#define NR_OMAP4_IOMMU_DEVICES 0
86#define omap4_iommu_pdev NULL
87#endif
88
89static struct platform_device **omap_iommu_pdev;
90
91static int __init omap_iommu_init(void)
92{
93 int i, err;
94 struct resource res[] = {
95 { .flags = IORESOURCE_MEM },
96 { .flags = IORESOURCE_IRQ },
97 };
98
99 if (cpu_is_omap34xx()) {
100 devices = omap3_devices;
101 omap_iommu_pdev = omap3_iommu_pdev;
102 num_iommu_devices = NR_OMAP3_IOMMU_DEVICES;
103 } else if (cpu_is_omap44xx()) {
104 devices = omap4_devices;
105 omap_iommu_pdev = omap4_iommu_pdev;
106 num_iommu_devices = NR_OMAP4_IOMMU_DEVICES;
107 } else
108 return -ENODEV;
109
110 for (i = 0; i < num_iommu_devices; i++) {
111 struct platform_device *pdev;
112 const struct iommu_device *d = &devices[i];
113
114 pdev = platform_device_alloc("omap-iommu", i);
115 if (!pdev) {
116 err = -ENOMEM;
117 goto err_out;
118 }
119
120 res[0].start = d->base;
121 res[0].end = d->base + MMU_REG_SIZE - 1;
122 res[1].start = res[1].end = d->irq;
123
124 err = platform_device_add_resources(pdev, res,
125 ARRAY_SIZE(res));
126 if (err)
127 goto err_out;
128 err = platform_device_add_data(pdev, &d->pdata,
129 sizeof(d->pdata));
130 if (err)
131 goto err_out;
132 err = platform_device_add(pdev);
133 if (err)
134 goto err_out;
135 omap_iommu_pdev[i] = pdev;
136 }
137 return 0;
138
139err_out:
140 while (i--)
141 platform_device_put(omap_iommu_pdev[i]);
142 return err;
143}
144module_init(omap_iommu_init);
145
146static void __exit omap_iommu_exit(void)
147{
148 int i;
149
150 for (i = 0; i < num_iommu_devices; i++)
151 platform_device_unregister(omap_iommu_pdev[i]);
152}
153module_exit(omap_iommu_exit);
154
155MODULE_AUTHOR("Hiroshi DOYU");
156MODULE_DESCRIPTION("omap iommu: omap device registration");
157MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 38153e5fbca0..1cf52313759e 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -24,7 +24,7 @@
24#include <asm/localtimer.h> 24#include <asm/localtimer.h>
25#include <asm/smp_scu.h> 25#include <asm/smp_scu.h>
26#include <mach/hardware.h> 26#include <mach/hardware.h>
27#include <plat/common.h> 27#include <mach/omap4-common.h>
28 28
29/* SCU base address */ 29/* SCU base address */
30static void __iomem *scu_base; 30static void __iomem *scu_base;
diff --git a/arch/arm/mach-omap2/omap3-iommu.c b/arch/arm/mach-omap2/omap3-iommu.c
deleted file mode 100644
index fbbcb5c83367..000000000000
--- a/arch/arm/mach-omap2/omap3-iommu.c
+++ /dev/null
@@ -1,105 +0,0 @@
1/*
2 * omap iommu: omap3 device registration
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/platform_device.h>
14
15#include <plat/iommu.h>
16
17struct iommu_device {
18 resource_size_t base;
19 int irq;
20 struct iommu_platform_data pdata;
21 struct resource res[2];
22};
23
24static struct iommu_device devices[] = {
25 {
26 .base = 0x480bd400,
27 .irq = 24,
28 .pdata = {
29 .name = "isp",
30 .nr_tlb_entries = 8,
31 .clk_name = "cam_ick",
32 },
33 },
34#if defined(CONFIG_MPU_BRIDGE_IOMMU)
35 {
36 .base = 0x5d000000,
37 .irq = 28,
38 .pdata = {
39 .name = "iva2",
40 .nr_tlb_entries = 32,
41 .clk_name = "iva2_ck",
42 },
43 },
44#endif
45};
46#define NR_IOMMU_DEVICES ARRAY_SIZE(devices)
47
48static struct platform_device *omap3_iommu_pdev[NR_IOMMU_DEVICES];
49
50static int __init omap3_iommu_init(void)
51{
52 int i, err;
53 struct resource res[] = {
54 { .flags = IORESOURCE_MEM },
55 { .flags = IORESOURCE_IRQ },
56 };
57
58 for (i = 0; i < NR_IOMMU_DEVICES; i++) {
59 struct platform_device *pdev;
60 const struct iommu_device *d = &devices[i];
61
62 pdev = platform_device_alloc("omap-iommu", i);
63 if (!pdev) {
64 err = -ENOMEM;
65 goto err_out;
66 }
67
68 res[0].start = d->base;
69 res[0].end = d->base + MMU_REG_SIZE - 1;
70 res[1].start = res[1].end = d->irq;
71
72 err = platform_device_add_resources(pdev, res,
73 ARRAY_SIZE(res));
74 if (err)
75 goto err_out;
76 err = platform_device_add_data(pdev, &d->pdata,
77 sizeof(d->pdata));
78 if (err)
79 goto err_out;
80 err = platform_device_add(pdev);
81 if (err)
82 goto err_out;
83 omap3_iommu_pdev[i] = pdev;
84 }
85 return 0;
86
87err_out:
88 while (i--)
89 platform_device_put(omap3_iommu_pdev[i]);
90 return err;
91}
92module_init(omap3_iommu_init);
93
94static void __exit omap3_iommu_exit(void)
95{
96 int i;
97
98 for (i = 0; i < NR_IOMMU_DEVICES; i++)
99 platform_device_unregister(omap3_iommu_pdev[i]);
100}
101module_exit(omap3_iommu_exit);
102
103MODULE_AUTHOR("Hiroshi DOYU");
104MODULE_DESCRIPTION("omap iommu: omap3 device registration");
105MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
new file mode 100644
index 000000000000..13dc9794dcc2
--- /dev/null
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -0,0 +1,72 @@
1/*
2 * OMAP4 specific common source file.
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc.
5 * Author:
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 *
8 *
9 * This program is free software,you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/platform_device.h>
18
19#include <asm/hardware/gic.h>
20#include <asm/hardware/cache-l2x0.h>
21
22#include <mach/hardware.h>
23#include <mach/omap4-common.h>
24
25#ifdef CONFIG_CACHE_L2X0
26void __iomem *l2cache_base;
27#endif
28
29void __iomem *gic_cpu_base_addr;
30void __iomem *gic_dist_base_addr;
31
32
33void __init gic_init_irq(void)
34{
35 /* Static mapping, never released */
36 gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
37 BUG_ON(!gic_dist_base_addr);
38 gic_dist_init(0, gic_dist_base_addr, 29);
39
40 /* Static mapping, never released */
41 gic_cpu_base_addr = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
42 BUG_ON(!gic_cpu_base_addr);
43 gic_cpu_init(0, gic_cpu_base_addr);
44}
45
46#ifdef CONFIG_CACHE_L2X0
47static int __init omap_l2_cache_init(void)
48{
49 /*
50 * To avoid code running on other OMAPs in
51 * multi-omap builds
52 */
53 if (!cpu_is_omap44xx())
54 return -ENODEV;
55
56 /* Static mapping, never released */
57 l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
58 BUG_ON(!l2cache_base);
59
60 /* Enable PL310 L2 Cache controller */
61 omap_smc1(0x102, 0x1);
62
63 /*
64 * 32KB way size, 16-way associativity,
65 * parity disabled
66 */
67 l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff);
68
69 return 0;
70}
71early_initcall(omap_l2_cache_init);
72#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 2c12e8cd7183..95c9a5f774e1 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2,12 +2,12 @@
2 * omap_hwmod implementation for OMAP2/3/4 2 * omap_hwmod implementation for OMAP2/3/4
3 * 3 *
4 * Copyright (C) 2009 Nokia Corporation 4 * Copyright (C) 2009 Nokia Corporation
5 * Paul Walmsley
6 * With fixes and testing from Kevin Hilman
7 * 5 *
8 * Created in collaboration with (alphabetical order): Benoit Cousson, 6 * Paul Walmsley, Benoît Cousson, Kevin Hilman
9 * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari 7 *
10 * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff 8 * Created in collaboration with (alphabetical order): Thara Gopinath,
9 * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand
10 * Sawant, Santosh Shilimkar, Richard Woodruff
11 * 11 *
12 * This program is free software; you can redistribute it and/or modify 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as 13 * it under the terms of the GNU General Public License version 2 as
@@ -57,7 +57,7 @@
57#define MAX_MODULE_RESET_WAIT 10000 57#define MAX_MODULE_RESET_WAIT 10000
58 58
59/* Name of the OMAP hwmod for the MPU */ 59/* Name of the OMAP hwmod for the MPU */
60#define MPU_INITIATOR_NAME "mpu_hwmod" 60#define MPU_INITIATOR_NAME "mpu"
61 61
62/* omap_hwmod_list contains all registered struct omap_hwmods */ 62/* omap_hwmod_list contains all registered struct omap_hwmods */
63static LIST_HEAD(omap_hwmod_list); 63static LIST_HEAD(omap_hwmod_list);
@@ -403,21 +403,20 @@ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
403 */ 403 */
404static int _init_main_clk(struct omap_hwmod *oh) 404static int _init_main_clk(struct omap_hwmod *oh)
405{ 405{
406 struct clk *c;
407 int ret = 0; 406 int ret = 0;
408 407
409 if (!oh->main_clk) 408 if (!oh->main_clk)
410 return 0; 409 return 0;
411 410
412 c = omap_clk_get_by_name(oh->main_clk); 411 oh->_clk = omap_clk_get_by_name(oh->main_clk);
413 WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get main_clk %s\n", 412 if (!oh->_clk)
414 oh->name, oh->main_clk); 413 pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n",
415 if (IS_ERR(c)) 414 oh->name, oh->main_clk);
416 ret = -EINVAL; 415 return -EINVAL;
417 oh->_clk = c;
418 416
419 WARN(!c->clkdm, "omap_hwmod: %s: missing clockdomain for %s.\n", 417 if (!oh->_clk->clkdm)
420 oh->main_clk, c->name); 418 pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
419 oh->main_clk, oh->_clk->name);
421 420
422 return ret; 421 return ret;
423} 422}
@@ -431,7 +430,6 @@ static int _init_main_clk(struct omap_hwmod *oh)
431 */ 430 */
432static int _init_interface_clks(struct omap_hwmod *oh) 431static int _init_interface_clks(struct omap_hwmod *oh)
433{ 432{
434 struct omap_hwmod_ocp_if *os;
435 struct clk *c; 433 struct clk *c;
436 int i; 434 int i;
437 int ret = 0; 435 int ret = 0;
@@ -439,14 +437,16 @@ static int _init_interface_clks(struct omap_hwmod *oh)
439 if (oh->slaves_cnt == 0) 437 if (oh->slaves_cnt == 0)
440 return 0; 438 return 0;
441 439
442 for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) { 440 for (i = 0; i < oh->slaves_cnt; i++) {
441 struct omap_hwmod_ocp_if *os = oh->slaves[i];
442
443 if (!os->clk) 443 if (!os->clk)
444 continue; 444 continue;
445 445
446 c = omap_clk_get_by_name(os->clk); 446 c = omap_clk_get_by_name(os->clk);
447 WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get " 447 if (!c)
448 "interface_clk %s\n", oh->name, os->clk); 448 pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
449 if (IS_ERR(c)) 449 oh->name, os->clk);
450 ret = -EINVAL; 450 ret = -EINVAL;
451 os->_clk = c; 451 os->_clk = c;
452 } 452 }
@@ -470,9 +470,9 @@ static int _init_opt_clks(struct omap_hwmod *oh)
470 470
471 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { 471 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
472 c = omap_clk_get_by_name(oc->clk); 472 c = omap_clk_get_by_name(oc->clk);
473 WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get opt_clk " 473 if (!c)
474 "%s\n", oh->name, oc->clk); 474 pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
475 if (IS_ERR(c)) 475 oh->name, oc->clk);
476 ret = -EINVAL; 476 ret = -EINVAL;
477 oc->_clk = c; 477 oc->_clk = c;
478 } 478 }
@@ -489,19 +489,19 @@ static int _init_opt_clks(struct omap_hwmod *oh)
489 */ 489 */
490static int _enable_clocks(struct omap_hwmod *oh) 490static int _enable_clocks(struct omap_hwmod *oh)
491{ 491{
492 struct omap_hwmod_ocp_if *os;
493 int i; 492 int i;
494 493
495 pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); 494 pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name);
496 495
497 if (oh->_clk && !IS_ERR(oh->_clk)) 496 if (oh->_clk)
498 clk_enable(oh->_clk); 497 clk_enable(oh->_clk);
499 498
500 if (oh->slaves_cnt > 0) { 499 if (oh->slaves_cnt > 0) {
501 for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) { 500 for (i = 0; i < oh->slaves_cnt; i++) {
501 struct omap_hwmod_ocp_if *os = oh->slaves[i];
502 struct clk *c = os->_clk; 502 struct clk *c = os->_clk;
503 503
504 if (c && !IS_ERR(c) && (os->flags & OCPIF_SWSUP_IDLE)) 504 if (c && (os->flags & OCPIF_SWSUP_IDLE))
505 clk_enable(c); 505 clk_enable(c);
506 } 506 }
507 } 507 }
@@ -519,19 +519,19 @@ static int _enable_clocks(struct omap_hwmod *oh)
519 */ 519 */
520static int _disable_clocks(struct omap_hwmod *oh) 520static int _disable_clocks(struct omap_hwmod *oh)
521{ 521{
522 struct omap_hwmod_ocp_if *os;
523 int i; 522 int i;
524 523
525 pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); 524 pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name);
526 525
527 if (oh->_clk && !IS_ERR(oh->_clk)) 526 if (oh->_clk)
528 clk_disable(oh->_clk); 527 clk_disable(oh->_clk);
529 528
530 if (oh->slaves_cnt > 0) { 529 if (oh->slaves_cnt > 0) {
531 for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) { 530 for (i = 0; i < oh->slaves_cnt; i++) {
531 struct omap_hwmod_ocp_if *os = oh->slaves[i];
532 struct clk *c = os->_clk; 532 struct clk *c = os->_clk;
533 533
534 if (c && !IS_ERR(c) && (os->flags & OCPIF_SWSUP_IDLE)) 534 if (c && (os->flags & OCPIF_SWSUP_IDLE))
535 clk_disable(c); 535 clk_disable(c);
536 } 536 }
537 } 537 }
@@ -550,14 +550,15 @@ static int _disable_clocks(struct omap_hwmod *oh)
550 */ 550 */
551static int _find_mpu_port_index(struct omap_hwmod *oh) 551static int _find_mpu_port_index(struct omap_hwmod *oh)
552{ 552{
553 struct omap_hwmod_ocp_if *os;
554 int i; 553 int i;
555 int found = 0; 554 int found = 0;
556 555
557 if (!oh || oh->slaves_cnt == 0) 556 if (!oh || oh->slaves_cnt == 0)
558 return -EINVAL; 557 return -EINVAL;
559 558
560 for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) { 559 for (i = 0; i < oh->slaves_cnt; i++) {
560 struct omap_hwmod_ocp_if *os = oh->slaves[i];
561
561 if (os->user & OCP_USER_MPU) { 562 if (os->user & OCP_USER_MPU) {
562 found = 1; 563 found = 1;
563 break; 564 break;
@@ -592,7 +593,7 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
592 if (!oh || oh->slaves_cnt == 0) 593 if (!oh || oh->slaves_cnt == 0)
593 return NULL; 594 return NULL;
594 595
595 os = *oh->slaves + index; 596 os = oh->slaves[index];
596 597
597 for (i = 0, mem = os->addr; i < os->addr_cnt; i++, mem++) { 598 for (i = 0, mem = os->addr; i < os->addr_cnt; i++, mem++) {
598 if (mem->flags & ADDR_TYPE_RT) { 599 if (mem->flags & ADDR_TYPE_RT) {
@@ -780,9 +781,10 @@ static int _init_clocks(struct omap_hwmod *oh)
780 ret |= _init_interface_clks(oh); 781 ret |= _init_interface_clks(oh);
781 ret |= _init_opt_clks(oh); 782 ret |= _init_opt_clks(oh);
782 783
783 oh->_state = _HWMOD_STATE_CLKS_INITED; 784 if (!ret)
785 oh->_state = _HWMOD_STATE_CLKS_INITED;
784 786
785 return ret; 787 return 0;
786} 788}
787 789
788/** 790/**
@@ -805,9 +807,9 @@ static int _wait_target_ready(struct omap_hwmod *oh)
805 if (oh->_int_flags & _HWMOD_NO_MPU_PORT) 807 if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
806 return 0; 808 return 0;
807 809
808 os = *oh->slaves + oh->_mpu_port_index; 810 os = oh->slaves[oh->_mpu_port_index];
809 811
810 if (!(os->flags & OCPIF_HAS_IDLEST)) 812 if (oh->flags & HWMOD_NO_IDLEST)
811 return 0; 813 return 0;
812 814
813 /* XXX check module SIDLEMODE */ 815 /* XXX check module SIDLEMODE */
@@ -818,11 +820,8 @@ static int _wait_target_ready(struct omap_hwmod *oh)
818 ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs, 820 ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs,
819 oh->prcm.omap2.idlest_reg_id, 821 oh->prcm.omap2.idlest_reg_id,
820 oh->prcm.omap2.idlest_idle_bit); 822 oh->prcm.omap2.idlest_idle_bit);
821#if 0
822 } else if (cpu_is_omap44xx()) { 823 } else if (cpu_is_omap44xx()) {
823 ret = omap4_cm_wait_module_ready(oh->prcm.omap4.module_offs, 824 ret = omap4_cm_wait_module_ready(oh->prcm.omap4.clkctrl_reg);
824 oh->prcm.omap4.device_offs);
825#endif
826 } else { 825 } else {
827 BUG(); 826 BUG();
828 }; 827 };
@@ -911,16 +910,21 @@ static int _enable(struct omap_hwmod *oh)
911 _add_initiator_dep(oh, mpu_oh); 910 _add_initiator_dep(oh, mpu_oh);
912 _enable_clocks(oh); 911 _enable_clocks(oh);
913 912
914 if (oh->class->sysc) {
915 if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
916 _update_sysc_cache(oh);
917 _sysc_enable(oh);
918 }
919
920 r = _wait_target_ready(oh); 913 r = _wait_target_ready(oh);
921 if (!r) 914 if (!r) {
922 oh->_state = _HWMOD_STATE_ENABLED; 915 oh->_state = _HWMOD_STATE_ENABLED;
923 916
917 /* Access the sysconfig only if the target is ready */
918 if (oh->class->sysc) {
919 if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
920 _update_sysc_cache(oh);
921 _sysc_enable(oh);
922 }
923 } else {
924 pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
925 oh->name, r);
926 }
927
924 return r; 928 return r;
925} 929}
926 930
@@ -997,18 +1001,18 @@ static int _shutdown(struct omap_hwmod *oh)
997 */ 1001 */
998static int _setup(struct omap_hwmod *oh) 1002static int _setup(struct omap_hwmod *oh)
999{ 1003{
1000 struct omap_hwmod_ocp_if *os; 1004 int i, r;
1001 int i;
1002 1005
1003 if (!oh) 1006 if (!oh)
1004 return -EINVAL; 1007 return -EINVAL;
1005 1008
1006 /* Set iclk autoidle mode */ 1009 /* Set iclk autoidle mode */
1007 if (oh->slaves_cnt > 0) { 1010 if (oh->slaves_cnt > 0) {
1008 for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) { 1011 for (i = 0; i < oh->slaves_cnt; i++) {
1012 struct omap_hwmod_ocp_if *os = oh->slaves[i];
1009 struct clk *c = os->_clk; 1013 struct clk *c = os->_clk;
1010 1014
1011 if (!c || IS_ERR(c)) 1015 if (!c)
1012 continue; 1016 continue;
1013 1017
1014 if (os->flags & OCPIF_SWSUP_IDLE) { 1018 if (os->flags & OCPIF_SWSUP_IDLE) {
@@ -1022,7 +1026,12 @@ static int _setup(struct omap_hwmod *oh)
1022 1026
1023 oh->_state = _HWMOD_STATE_INITIALIZED; 1027 oh->_state = _HWMOD_STATE_INITIALIZED;
1024 1028
1025 _enable(oh); 1029 r = _enable(oh);
1030 if (r) {
1031 pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n",
1032 oh->name, oh->_state);
1033 return 0;
1034 }
1026 1035
1027 if (!(oh->flags & HWMOD_INIT_NO_RESET)) { 1036 if (!(oh->flags & HWMOD_INIT_NO_RESET)) {
1028 /* 1037 /*
@@ -1430,7 +1439,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
1430 ret = oh->mpu_irqs_cnt + oh->sdma_chs_cnt; 1439 ret = oh->mpu_irqs_cnt + oh->sdma_chs_cnt;
1431 1440
1432 for (i = 0; i < oh->slaves_cnt; i++) 1441 for (i = 0; i < oh->slaves_cnt; i++)
1433 ret += (*oh->slaves + i)->addr_cnt; 1442 ret += oh->slaves[i]->addr_cnt;
1434 1443
1435 return ret; 1444 return ret;
1436} 1445}
@@ -1471,7 +1480,7 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
1471 for (i = 0; i < oh->slaves_cnt; i++) { 1480 for (i = 0; i < oh->slaves_cnt; i++) {
1472 struct omap_hwmod_ocp_if *os; 1481 struct omap_hwmod_ocp_if *os;
1473 1482
1474 os = *oh->slaves + i; 1483 os = oh->slaves[i];
1475 1484
1476 for (j = 0; j < os->addr_cnt; j++) { 1485 for (j = 0; j < os->addr_cnt; j++) {
1477 (res + r)->start = (os->addr + j)->pa_start; 1486 (res + r)->start = (os->addr + j)->pa_start;
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index eb7ee2453b24..e5530c51f77d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -125,7 +125,7 @@ static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
125 125
126/* MPU */ 126/* MPU */
127static struct omap_hwmod omap2420_mpu_hwmod = { 127static struct omap_hwmod omap2420_mpu_hwmod = {
128 .name = "mpu_hwmod", 128 .name = "mpu",
129 .class = &mpu_hwmod_class, 129 .class = &mpu_hwmod_class,
130 .main_clk = "mpu_ck", 130 .main_clk = "mpu_ck",
131 .masters = omap2420_mpu_masters, 131 .masters = omap2420_mpu_masters,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 241bd8230729..0852d954da40 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -127,7 +127,7 @@ static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
127 127
128/* MPU */ 128/* MPU */
129static struct omap_hwmod omap2430_mpu_hwmod = { 129static struct omap_hwmod omap2430_mpu_hwmod = {
130 .name = "mpu_hwmod", 130 .name = "mpu",
131 .class = &mpu_hwmod_class, 131 .class = &mpu_hwmod_class,
132 .main_clk = "mpu_ck", 132 .main_clk = "mpu_ck",
133 .masters = omap2430_mpu_masters, 133 .masters = omap2430_mpu_masters,
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index ed6084004260..39b0c0eaa37d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -156,7 +156,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
156 156
157/* MPU */ 157/* MPU */
158static struct omap_hwmod omap3xxx_mpu_hwmod = { 158static struct omap_hwmod omap3xxx_mpu_hwmod = {
159 .name = "mpu_hwmod", 159 .name = "mpu",
160 .class = &mpu_hwmod_class, 160 .class = &mpu_hwmod_class,
161 .main_clk = "arm_fck", 161 .main_clk = "arm_fck",
162 .masters = omap3xxx_mpu_masters, 162 .masters = omap3xxx_mpu_masters,
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 6cac9817c243..723b44e252fd 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -548,6 +548,9 @@ static int option_set(void *data, u64 val)
548{ 548{
549 u32 *option = data; 549 u32 *option = data;
550 550
551 if (option == &wakeup_timer_milliseconds && val >= 1000)
552 return -EINVAL;
553
551 *option = val; 554 *option = val;
552 555
553 if (option == &enable_off_mode) 556 if (option == &enable_off_mode)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index bd6466a2b039..3de6ece23fc8 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -43,6 +43,7 @@ extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
43extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state); 43extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
44 44
45extern u32 wakeup_timer_seconds; 45extern u32 wakeup_timer_seconds;
46extern u32 wakeup_timer_milliseconds;
46extern struct omap_dm_timer *gptimer_wakeup; 47extern struct omap_dm_timer *gptimer_wakeup;
47 48
48#ifdef CONFIG_PM_DEBUG 49#ifdef CONFIG_PM_DEBUG
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 374299ea7ade..e321281ab6e1 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -70,8 +70,8 @@ static int omap2_fclks_active(void)
70 f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); 70 f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
71 71
72 /* Ignore UART clocks. These are handled by UART core (serial.c) */ 72 /* Ignore UART clocks. These are handled by UART core (serial.c) */
73 f1 &= ~(OMAP24XX_EN_UART1 | OMAP24XX_EN_UART2); 73 f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK);
74 f2 &= ~OMAP24XX_EN_UART3; 74 f2 &= ~OMAP24XX_EN_UART3_MASK;
75 75
76 if (f1 | f2) 76 if (f1 | f2)
77 return 1; 77 return 1;
@@ -107,7 +107,7 @@ static void omap2_enter_full_retention(void)
107 l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL; 107 l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
108 omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0); 108 omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
109 109
110 omap2_gpio_prepare_for_retention(); 110 omap2_gpio_prepare_for_idle(PWRDM_POWER_RET);
111 111
112 if (omap2_pm_debug) { 112 if (omap2_pm_debug) {
113 omap2_pm_dump(0, 0, 0); 113 omap2_pm_dump(0, 0, 0);
@@ -141,7 +141,7 @@ no_sleep:
141 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC; 141 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
142 omap2_pm_dump(0, 1, tmp); 142 omap2_pm_dump(0, 1, tmp);
143 } 143 }
144 omap2_gpio_resume_after_retention(); 144 omap2_gpio_resume_after_idle();
145 145
146 clk_enable(osc_ck); 146 clk_enable(osc_ck);
147 147
@@ -170,7 +170,7 @@ static int omap2_i2c_active(void)
170 u32 l; 170 u32 l;
171 171
172 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); 172 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
173 return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1); 173 return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
174} 174}
175 175
176static int sti_console_enabled; 176static int sti_console_enabled;
@@ -181,13 +181,13 @@ static int omap2_allow_mpu_retention(void)
181 181
182 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */ 182 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
183 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); 183 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
184 if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 | 184 if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
185 OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 | 185 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
186 OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1)) 186 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
187 return 0; 187 return 0;
188 /* Check for UART3. */ 188 /* Check for UART3. */
189 l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); 189 l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
190 if (l & OMAP24XX_EN_UART3) 190 if (l & OMAP24XX_EN_UART3_MASK)
191 return 0; 191 return 0;
192 if (sti_console_enabled) 192 if (sti_console_enabled)
193 return 0; 193 return 0;
@@ -215,12 +215,12 @@ static void omap2_enter_mpu_retention(void)
215 215
216 /* Try to enter MPU retention */ 216 /* Try to enter MPU retention */
217 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | 217 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
218 OMAP_LOGICRETSTATE, 218 OMAP_LOGICRETSTATE_MASK,
219 MPU_MOD, OMAP2_PM_PWSTCTRL); 219 MPU_MOD, OMAP2_PM_PWSTCTRL);
220 } else { 220 } else {
221 /* Block MPU retention */ 221 /* Block MPU retention */
222 222
223 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, 223 prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
224 OMAP2_PM_PWSTCTRL); 224 OMAP2_PM_PWSTCTRL);
225 only_idle = 1; 225 only_idle = 1;
226 } 226 }
@@ -288,7 +288,8 @@ static int omap2_pm_suspend(void)
288 u32 wken_wkup, mir1; 288 u32 wken_wkup, mir1;
289 289
290 wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN); 290 wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
291 prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN); 291 wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
292 prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
292 293
293 /* Mask GPT1 */ 294 /* Mask GPT1 */
294 mir1 = omap_readl(0x480fe0a4); 295 mir1 = omap_readl(0x480fe0a4);
@@ -351,7 +352,7 @@ static void __init prcm_setup_regs(void)
351 struct powerdomain *pwrdm; 352 struct powerdomain *pwrdm;
352 353
353 /* Enable autoidle */ 354 /* Enable autoidle */
354 prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD, 355 prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
355 OMAP2_PRCM_SYSCONFIG_OFFSET); 356 OMAP2_PRCM_SYSCONFIG_OFFSET);
356 357
357 /* 358 /*
@@ -390,53 +391,54 @@ static void __init prcm_setup_regs(void)
390 clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); 391 clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
391 392
392 /* Enable clock autoidle for all domains */ 393 /* Enable clock autoidle for all domains */
393 cm_write_mod_reg(OMAP24XX_AUTO_CAM | 394 cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK |
394 OMAP24XX_AUTO_MAILBOXES | 395 OMAP24XX_AUTO_MAILBOXES_MASK |
395 OMAP24XX_AUTO_WDT4 | 396 OMAP24XX_AUTO_WDT4_MASK |
396 OMAP2420_AUTO_WDT3 | 397 OMAP2420_AUTO_WDT3_MASK |
397 OMAP24XX_AUTO_MSPRO | 398 OMAP24XX_AUTO_MSPRO_MASK |
398 OMAP2420_AUTO_MMC | 399 OMAP2420_AUTO_MMC_MASK |
399 OMAP24XX_AUTO_FAC | 400 OMAP24XX_AUTO_FAC_MASK |
400 OMAP2420_AUTO_EAC | 401 OMAP2420_AUTO_EAC_MASK |
401 OMAP24XX_AUTO_HDQ | 402 OMAP24XX_AUTO_HDQ_MASK |
402 OMAP24XX_AUTO_UART2 | 403 OMAP24XX_AUTO_UART2_MASK |
403 OMAP24XX_AUTO_UART1 | 404 OMAP24XX_AUTO_UART1_MASK |
404 OMAP24XX_AUTO_I2C2 | 405 OMAP24XX_AUTO_I2C2_MASK |
405 OMAP24XX_AUTO_I2C1 | 406 OMAP24XX_AUTO_I2C1_MASK |
406 OMAP24XX_AUTO_MCSPI2 | 407 OMAP24XX_AUTO_MCSPI2_MASK |
407 OMAP24XX_AUTO_MCSPI1 | 408 OMAP24XX_AUTO_MCSPI1_MASK |
408 OMAP24XX_AUTO_MCBSP2 | 409 OMAP24XX_AUTO_MCBSP2_MASK |
409 OMAP24XX_AUTO_MCBSP1 | 410 OMAP24XX_AUTO_MCBSP1_MASK |
410 OMAP24XX_AUTO_GPT12 | 411 OMAP24XX_AUTO_GPT12_MASK |
411 OMAP24XX_AUTO_GPT11 | 412 OMAP24XX_AUTO_GPT11_MASK |
412 OMAP24XX_AUTO_GPT10 | 413 OMAP24XX_AUTO_GPT10_MASK |
413 OMAP24XX_AUTO_GPT9 | 414 OMAP24XX_AUTO_GPT9_MASK |
414 OMAP24XX_AUTO_GPT8 | 415 OMAP24XX_AUTO_GPT8_MASK |
415 OMAP24XX_AUTO_GPT7 | 416 OMAP24XX_AUTO_GPT7_MASK |
416 OMAP24XX_AUTO_GPT6 | 417 OMAP24XX_AUTO_GPT6_MASK |
417 OMAP24XX_AUTO_GPT5 | 418 OMAP24XX_AUTO_GPT5_MASK |
418 OMAP24XX_AUTO_GPT4 | 419 OMAP24XX_AUTO_GPT4_MASK |
419 OMAP24XX_AUTO_GPT3 | 420 OMAP24XX_AUTO_GPT3_MASK |
420 OMAP24XX_AUTO_GPT2 | 421 OMAP24XX_AUTO_GPT2_MASK |
421 OMAP2420_AUTO_VLYNQ | 422 OMAP2420_AUTO_VLYNQ_MASK |
422 OMAP24XX_AUTO_DSS, 423 OMAP24XX_AUTO_DSS_MASK,
423 CORE_MOD, CM_AUTOIDLE1); 424 CORE_MOD, CM_AUTOIDLE1);
424 cm_write_mod_reg(OMAP24XX_AUTO_UART3 | 425 cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK |
425 OMAP24XX_AUTO_SSI | 426 OMAP24XX_AUTO_SSI_MASK |
426 OMAP24XX_AUTO_USB, 427 OMAP24XX_AUTO_USB_MASK,
427 CORE_MOD, CM_AUTOIDLE2); 428 CORE_MOD, CM_AUTOIDLE2);
428 cm_write_mod_reg(OMAP24XX_AUTO_SDRC | 429 cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK |
429 OMAP24XX_AUTO_GPMC | 430 OMAP24XX_AUTO_GPMC_MASK |
430 OMAP24XX_AUTO_SDMA, 431 OMAP24XX_AUTO_SDMA_MASK,
431 CORE_MOD, CM_AUTOIDLE3); 432 CORE_MOD, CM_AUTOIDLE3);
432 cm_write_mod_reg(OMAP24XX_AUTO_PKA | 433 cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK |
433 OMAP24XX_AUTO_AES | 434 OMAP24XX_AUTO_AES_MASK |
434 OMAP24XX_AUTO_RNG | 435 OMAP24XX_AUTO_RNG_MASK |
435 OMAP24XX_AUTO_SHA | 436 OMAP24XX_AUTO_SHA_MASK |
436 OMAP24XX_AUTO_DES, 437 OMAP24XX_AUTO_DES_MASK,
437 CORE_MOD, OMAP24XX_CM_AUTOIDLE4); 438 CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
438 439
439 cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE); 440 cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
441 CM_AUTOIDLE);
440 442
441 /* Put DPLL and both APLLs into autoidle mode */ 443 /* Put DPLL and both APLLs into autoidle mode */
442 cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) | 444 cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
@@ -444,12 +446,12 @@ static void __init prcm_setup_regs(void)
444 (0x03 << OMAP24XX_AUTO_54M_SHIFT), 446 (0x03 << OMAP24XX_AUTO_54M_SHIFT),
445 PLL_MOD, CM_AUTOIDLE); 447 PLL_MOD, CM_AUTOIDLE);
446 448
447 cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL | 449 cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
448 OMAP24XX_AUTO_WDT1 | 450 OMAP24XX_AUTO_WDT1_MASK |
449 OMAP24XX_AUTO_MPU_WDT | 451 OMAP24XX_AUTO_MPU_WDT_MASK |
450 OMAP24XX_AUTO_GPIOS | 452 OMAP24XX_AUTO_GPIOS_MASK |
451 OMAP24XX_AUTO_32KSYNC | 453 OMAP24XX_AUTO_32KSYNC_MASK |
452 OMAP24XX_AUTO_GPT1, 454 OMAP24XX_AUTO_GPT1_MASK,
453 WKUP_MOD, CM_AUTOIDLE); 455 WKUP_MOD, CM_AUTOIDLE);
454 456
455 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk 457 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
@@ -460,15 +462,15 @@ static void __init prcm_setup_regs(void)
460 /* Configure automatic voltage transition */ 462 /* Configure automatic voltage transition */
461 prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, 463 prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
462 OMAP2_PRCM_VOLTSETUP_OFFSET); 464 OMAP2_PRCM_VOLTSETUP_OFFSET);
463 prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT | 465 prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
464 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | 466 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
465 OMAP24XX_MEMRETCTRL | 467 OMAP24XX_MEMRETCTRL_MASK |
466 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | 468 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
467 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT), 469 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
468 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET); 470 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
469 471
470 /* Enable wake-up events */ 472 /* Enable wake-up events */
471 prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1, 473 prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
472 WKUP_MOD, PM_WKEN); 474 WKUP_MOD, PM_WKEN);
473} 475}
474 476
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index ea0000bc5358..2e967716cc3f 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -58,6 +58,7 @@
58u32 enable_off_mode; 58u32 enable_off_mode;
59u32 sleep_while_idle; 59u32 sleep_while_idle;
60u32 wakeup_timer_seconds; 60u32 wakeup_timer_seconds;
61u32 wakeup_timer_milliseconds;
61 62
62struct power_state { 63struct power_state {
63 struct powerdomain *pwrdm; 64 struct powerdomain *pwrdm;
@@ -93,19 +94,20 @@ static void omap3_enable_io_chain(void)
93 int timeout = 0; 94 int timeout = 0;
94 95
95 if (omap_rev() >= OMAP3430_REV_ES3_1) { 96 if (omap_rev() >= OMAP3430_REV_ES3_1) {
96 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN); 97 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
98 PM_WKEN);
97 /* Do a readback to assure write has been done */ 99 /* Do a readback to assure write has been done */
98 prm_read_mod_reg(WKUP_MOD, PM_WKEN); 100 prm_read_mod_reg(WKUP_MOD, PM_WKEN);
99 101
100 while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) & 102 while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) &
101 OMAP3430_ST_IO_CHAIN)) { 103 OMAP3430_ST_IO_CHAIN_MASK)) {
102 timeout++; 104 timeout++;
103 if (timeout > 1000) { 105 if (timeout > 1000) {
104 printk(KERN_ERR "Wake up daisy chain " 106 printk(KERN_ERR "Wake up daisy chain "
105 "activation failed.\n"); 107 "activation failed.\n");
106 return; 108 return;
107 } 109 }
108 prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN, 110 prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
109 WKUP_MOD, PM_WKST); 111 WKUP_MOD, PM_WKST);
110 } 112 }
111 } 113 }
@@ -114,7 +116,8 @@ static void omap3_enable_io_chain(void)
114static void omap3_disable_io_chain(void) 116static void omap3_disable_io_chain(void)
115{ 117{
116 if (omap_rev() >= OMAP3430_REV_ES3_1) 118 if (omap_rev() >= OMAP3430_REV_ES3_1)
117 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN); 119 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
120 PM_WKEN);
118} 121}
119 122
120static void omap3_core_save_context(void) 123static void omap3_core_save_context(void)
@@ -267,14 +270,18 @@ static int _prcm_int_handle_wakeup(void)
267 */ 270 */
268static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) 271static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
269{ 272{
270 u32 irqstatus_mpu; 273 u32 irqenable_mpu, irqstatus_mpu;
271 int c = 0; 274 int c = 0;
272 275
273 do { 276 irqenable_mpu = prm_read_mod_reg(OCP_MOD,
274 irqstatus_mpu = prm_read_mod_reg(OCP_MOD, 277 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
275 OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 278 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
279 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
280 irqstatus_mpu &= irqenable_mpu;
276 281
277 if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) { 282 do {
283 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
284 OMAP3430_IO_ST_MASK)) {
278 c = _prcm_int_handle_wakeup(); 285 c = _prcm_int_handle_wakeup();
279 286
280 /* 287 /*
@@ -292,7 +299,11 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
292 prm_write_mod_reg(irqstatus_mpu, OCP_MOD, 299 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
293 OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 300 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
294 301
295 } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET)); 302 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
303 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
304 irqstatus_mpu &= irqenable_mpu;
305
306 } while (irqstatus_mpu);
296 307
297 return IRQ_HANDLED; 308 return IRQ_HANDLED;
298} 309}
@@ -371,12 +382,19 @@ void omap_sram_idle(void)
371 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 382 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
372 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); 383 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
373 384
374 /* PER */ 385 /* Enable IO-PAD and IO-CHAIN wakeups */
375 per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 386 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
376 core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 387 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
388 if (per_next_state < PWRDM_POWER_ON ||
389 core_next_state < PWRDM_POWER_ON) {
390 prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
391 omap3_enable_io_chain();
392 }
393
394 /* PER */
377 if (per_next_state < PWRDM_POWER_ON) { 395 if (per_next_state < PWRDM_POWER_ON) {
378 omap_uart_prepare_idle(2); 396 omap_uart_prepare_idle(2);
379 omap2_gpio_prepare_for_retention(); 397 omap2_gpio_prepare_for_idle(per_next_state);
380 if (per_next_state == PWRDM_POWER_OFF) { 398 if (per_next_state == PWRDM_POWER_OFF) {
381 if (core_next_state == PWRDM_POWER_ON) { 399 if (core_next_state == PWRDM_POWER_ON) {
382 per_next_state = PWRDM_POWER_RET; 400 per_next_state = PWRDM_POWER_RET;
@@ -398,10 +416,8 @@ void omap_sram_idle(void)
398 omap3_core_save_context(); 416 omap3_core_save_context();
399 omap3_prcm_save_context(); 417 omap3_prcm_save_context();
400 } 418 }
401 /* Enable IO-PAD and IO-CHAIN wakeups */
402 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
403 omap3_enable_io_chain();
404 } 419 }
420
405 omap3_intc_prepare_idle(); 421 omap3_intc_prepare_idle();
406 422
407 /* 423 /*
@@ -445,7 +461,7 @@ void omap_sram_idle(void)
445 omap_uart_resume_idle(0); 461 omap_uart_resume_idle(0);
446 omap_uart_resume_idle(1); 462 omap_uart_resume_idle(1);
447 if (core_next_state == PWRDM_POWER_OFF) 463 if (core_next_state == PWRDM_POWER_OFF)
448 prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF, 464 prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
449 OMAP3430_GR_MOD, 465 OMAP3430_GR_MOD,
450 OMAP3_PRM_VOLTCTRL_OFFSET); 466 OMAP3_PRM_VOLTCTRL_OFFSET);
451 } 467 }
@@ -454,9 +470,9 @@ void omap_sram_idle(void)
454 /* PER */ 470 /* PER */
455 if (per_next_state < PWRDM_POWER_ON) { 471 if (per_next_state < PWRDM_POWER_ON) {
456 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); 472 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
473 omap2_gpio_resume_after_idle();
457 if (per_prev_state == PWRDM_POWER_OFF) 474 if (per_prev_state == PWRDM_POWER_OFF)
458 omap3_per_restore_context(); 475 omap3_per_restore_context();
459 omap2_gpio_resume_after_retention();
460 omap_uart_resume_idle(2); 476 omap_uart_resume_idle(2);
461 if (per_state_modified) 477 if (per_state_modified)
462 pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF); 478 pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF);
@@ -464,7 +480,7 @@ void omap_sram_idle(void)
464 480
465 /* Disable IO-PAD and IO-CHAIN wakeup */ 481 /* Disable IO-PAD and IO-CHAIN wakeup */
466 if (core_next_state < PWRDM_POWER_ON) { 482 if (core_next_state < PWRDM_POWER_ON) {
467 prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); 483 prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
468 omap3_disable_io_chain(); 484 omap3_disable_io_chain();
469 } 485 }
470 486
@@ -548,20 +564,21 @@ out:
548#ifdef CONFIG_SUSPEND 564#ifdef CONFIG_SUSPEND
549static suspend_state_t suspend_state; 565static suspend_state_t suspend_state;
550 566
551static void omap2_pm_wakeup_on_timer(u32 seconds) 567static void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
552{ 568{
553 u32 tick_rate, cycles; 569 u32 tick_rate, cycles;
554 570
555 if (!seconds) 571 if (!seconds && !milliseconds)
556 return; 572 return;
557 573
558 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup)); 574 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
559 cycles = tick_rate * seconds; 575 cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
560 omap_dm_timer_stop(gptimer_wakeup); 576 omap_dm_timer_stop(gptimer_wakeup);
561 omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles); 577 omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
562 578
563 pr_info("PM: Resume timer in %d secs (%d ticks at %d ticks/sec.)\n", 579 pr_info("PM: Resume timer in %u.%03u secs"
564 seconds, cycles, tick_rate); 580 " (%d ticks at %d ticks/sec.)\n",
581 seconds, milliseconds, cycles, tick_rate);
565} 582}
566 583
567static int omap3_pm_prepare(void) 584static int omap3_pm_prepare(void)
@@ -575,8 +592,9 @@ static int omap3_pm_suspend(void)
575 struct power_state *pwrst; 592 struct power_state *pwrst;
576 int state, ret = 0; 593 int state, ret = 0;
577 594
578 if (wakeup_timer_seconds) 595 if (wakeup_timer_seconds || wakeup_timer_milliseconds)
579 omap2_pm_wakeup_on_timer(wakeup_timer_seconds); 596 omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
597 wakeup_timer_milliseconds);
580 598
581 /* Read current next_pwrsts */ 599 /* Read current next_pwrsts */
582 list_for_each_entry(pwrst, &pwrst_list, node) 600 list_for_each_entry(pwrst, &pwrst_list, node)
@@ -683,9 +701,9 @@ static void __init omap3_iva_idle(void)
683 return; 701 return;
684 702
685 /* Reset IVA2 */ 703 /* Reset IVA2 */
686 prm_write_mod_reg(OMAP3430_RST1_IVA2 | 704 prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
687 OMAP3430_RST2_IVA2 | 705 OMAP3430_RST2_IVA2_MASK |
688 OMAP3430_RST3_IVA2, 706 OMAP3430_RST3_IVA2_MASK,
689 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 707 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
690 708
691 /* Enable IVA2 clock */ 709 /* Enable IVA2 clock */
@@ -703,9 +721,9 @@ static void __init omap3_iva_idle(void)
703 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 721 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
704 722
705 /* Reset IVA2 */ 723 /* Reset IVA2 */
706 prm_write_mod_reg(OMAP3430_RST1_IVA2 | 724 prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
707 OMAP3430_RST2_IVA2 | 725 OMAP3430_RST2_IVA2_MASK |
708 OMAP3430_RST3_IVA2, 726 OMAP3430_RST3_IVA2_MASK,
709 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 727 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
710} 728}
711 729
@@ -727,8 +745,8 @@ static void __init omap3_d2d_idle(void)
727 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 745 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
728 746
729 /* reset modem */ 747 /* reset modem */
730 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON | 748 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
731 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST, 749 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
732 CORE_MOD, OMAP2_RM_RSTCTRL); 750 CORE_MOD, OMAP2_RM_RSTCTRL);
733 prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); 751 prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
734} 752}
@@ -754,102 +772,102 @@ static void __init prcm_setup_regs(void)
754 * Note that in the long run this should be done by clockfw 772 * Note that in the long run this should be done by clockfw
755 */ 773 */
756 cm_write_mod_reg( 774 cm_write_mod_reg(
757 OMAP3430_AUTO_MODEM | 775 OMAP3430_AUTO_MODEM_MASK |
758 OMAP3430ES2_AUTO_MMC3 | 776 OMAP3430ES2_AUTO_MMC3_MASK |
759 OMAP3430ES2_AUTO_ICR | 777 OMAP3430ES2_AUTO_ICR_MASK |
760 OMAP3430_AUTO_AES2 | 778 OMAP3430_AUTO_AES2_MASK |
761 OMAP3430_AUTO_SHA12 | 779 OMAP3430_AUTO_SHA12_MASK |
762 OMAP3430_AUTO_DES2 | 780 OMAP3430_AUTO_DES2_MASK |
763 OMAP3430_AUTO_MMC2 | 781 OMAP3430_AUTO_MMC2_MASK |
764 OMAP3430_AUTO_MMC1 | 782 OMAP3430_AUTO_MMC1_MASK |
765 OMAP3430_AUTO_MSPRO | 783 OMAP3430_AUTO_MSPRO_MASK |
766 OMAP3430_AUTO_HDQ | 784 OMAP3430_AUTO_HDQ_MASK |
767 OMAP3430_AUTO_MCSPI4 | 785 OMAP3430_AUTO_MCSPI4_MASK |
768 OMAP3430_AUTO_MCSPI3 | 786 OMAP3430_AUTO_MCSPI3_MASK |
769 OMAP3430_AUTO_MCSPI2 | 787 OMAP3430_AUTO_MCSPI2_MASK |
770 OMAP3430_AUTO_MCSPI1 | 788 OMAP3430_AUTO_MCSPI1_MASK |
771 OMAP3430_AUTO_I2C3 | 789 OMAP3430_AUTO_I2C3_MASK |
772 OMAP3430_AUTO_I2C2 | 790 OMAP3430_AUTO_I2C2_MASK |
773 OMAP3430_AUTO_I2C1 | 791 OMAP3430_AUTO_I2C1_MASK |
774 OMAP3430_AUTO_UART2 | 792 OMAP3430_AUTO_UART2_MASK |
775 OMAP3430_AUTO_UART1 | 793 OMAP3430_AUTO_UART1_MASK |
776 OMAP3430_AUTO_GPT11 | 794 OMAP3430_AUTO_GPT11_MASK |
777 OMAP3430_AUTO_GPT10 | 795 OMAP3430_AUTO_GPT10_MASK |
778 OMAP3430_AUTO_MCBSP5 | 796 OMAP3430_AUTO_MCBSP5_MASK |
779 OMAP3430_AUTO_MCBSP1 | 797 OMAP3430_AUTO_MCBSP1_MASK |
780 OMAP3430ES1_AUTO_FAC | /* This is es1 only */ 798 OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
781 OMAP3430_AUTO_MAILBOXES | 799 OMAP3430_AUTO_MAILBOXES_MASK |
782 OMAP3430_AUTO_OMAPCTRL | 800 OMAP3430_AUTO_OMAPCTRL_MASK |
783 OMAP3430ES1_AUTO_FSHOSTUSB | 801 OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
784 OMAP3430_AUTO_HSOTGUSB | 802 OMAP3430_AUTO_HSOTGUSB_MASK |
785 OMAP3430_AUTO_SAD2D | 803 OMAP3430_AUTO_SAD2D_MASK |
786 OMAP3430_AUTO_SSI, 804 OMAP3430_AUTO_SSI_MASK,
787 CORE_MOD, CM_AUTOIDLE1); 805 CORE_MOD, CM_AUTOIDLE1);
788 806
789 cm_write_mod_reg( 807 cm_write_mod_reg(
790 OMAP3430_AUTO_PKA | 808 OMAP3430_AUTO_PKA_MASK |
791 OMAP3430_AUTO_AES1 | 809 OMAP3430_AUTO_AES1_MASK |
792 OMAP3430_AUTO_RNG | 810 OMAP3430_AUTO_RNG_MASK |
793 OMAP3430_AUTO_SHA11 | 811 OMAP3430_AUTO_SHA11_MASK |
794 OMAP3430_AUTO_DES1, 812 OMAP3430_AUTO_DES1_MASK,
795 CORE_MOD, CM_AUTOIDLE2); 813 CORE_MOD, CM_AUTOIDLE2);
796 814
797 if (omap_rev() > OMAP3430_REV_ES1_0) { 815 if (omap_rev() > OMAP3430_REV_ES1_0) {
798 cm_write_mod_reg( 816 cm_write_mod_reg(
799 OMAP3430_AUTO_MAD2D | 817 OMAP3430_AUTO_MAD2D_MASK |
800 OMAP3430ES2_AUTO_USBTLL, 818 OMAP3430ES2_AUTO_USBTLL_MASK,
801 CORE_MOD, CM_AUTOIDLE3); 819 CORE_MOD, CM_AUTOIDLE3);
802 } 820 }
803 821
804 cm_write_mod_reg( 822 cm_write_mod_reg(
805 OMAP3430_AUTO_WDT2 | 823 OMAP3430_AUTO_WDT2_MASK |
806 OMAP3430_AUTO_WDT1 | 824 OMAP3430_AUTO_WDT1_MASK |
807 OMAP3430_AUTO_GPIO1 | 825 OMAP3430_AUTO_GPIO1_MASK |
808 OMAP3430_AUTO_32KSYNC | 826 OMAP3430_AUTO_32KSYNC_MASK |
809 OMAP3430_AUTO_GPT12 | 827 OMAP3430_AUTO_GPT12_MASK |
810 OMAP3430_AUTO_GPT1 , 828 OMAP3430_AUTO_GPT1_MASK,
811 WKUP_MOD, CM_AUTOIDLE); 829 WKUP_MOD, CM_AUTOIDLE);
812 830
813 cm_write_mod_reg( 831 cm_write_mod_reg(
814 OMAP3430_AUTO_DSS, 832 OMAP3430_AUTO_DSS_MASK,
815 OMAP3430_DSS_MOD, 833 OMAP3430_DSS_MOD,
816 CM_AUTOIDLE); 834 CM_AUTOIDLE);
817 835
818 cm_write_mod_reg( 836 cm_write_mod_reg(
819 OMAP3430_AUTO_CAM, 837 OMAP3430_AUTO_CAM_MASK,
820 OMAP3430_CAM_MOD, 838 OMAP3430_CAM_MOD,
821 CM_AUTOIDLE); 839 CM_AUTOIDLE);
822 840
823 cm_write_mod_reg( 841 cm_write_mod_reg(
824 OMAP3430_AUTO_GPIO6 | 842 OMAP3430_AUTO_GPIO6_MASK |
825 OMAP3430_AUTO_GPIO5 | 843 OMAP3430_AUTO_GPIO5_MASK |
826 OMAP3430_AUTO_GPIO4 | 844 OMAP3430_AUTO_GPIO4_MASK |
827 OMAP3430_AUTO_GPIO3 | 845 OMAP3430_AUTO_GPIO3_MASK |
828 OMAP3430_AUTO_GPIO2 | 846 OMAP3430_AUTO_GPIO2_MASK |
829 OMAP3430_AUTO_WDT3 | 847 OMAP3430_AUTO_WDT3_MASK |
830 OMAP3430_AUTO_UART3 | 848 OMAP3430_AUTO_UART3_MASK |
831 OMAP3430_AUTO_GPT9 | 849 OMAP3430_AUTO_GPT9_MASK |
832 OMAP3430_AUTO_GPT8 | 850 OMAP3430_AUTO_GPT8_MASK |
833 OMAP3430_AUTO_GPT7 | 851 OMAP3430_AUTO_GPT7_MASK |
834 OMAP3430_AUTO_GPT6 | 852 OMAP3430_AUTO_GPT6_MASK |
835 OMAP3430_AUTO_GPT5 | 853 OMAP3430_AUTO_GPT5_MASK |
836 OMAP3430_AUTO_GPT4 | 854 OMAP3430_AUTO_GPT4_MASK |
837 OMAP3430_AUTO_GPT3 | 855 OMAP3430_AUTO_GPT3_MASK |
838 OMAP3430_AUTO_GPT2 | 856 OMAP3430_AUTO_GPT2_MASK |
839 OMAP3430_AUTO_MCBSP4 | 857 OMAP3430_AUTO_MCBSP4_MASK |
840 OMAP3430_AUTO_MCBSP3 | 858 OMAP3430_AUTO_MCBSP3_MASK |
841 OMAP3430_AUTO_MCBSP2, 859 OMAP3430_AUTO_MCBSP2_MASK,
842 OMAP3430_PER_MOD, 860 OMAP3430_PER_MOD,
843 CM_AUTOIDLE); 861 CM_AUTOIDLE);
844 862
845 if (omap_rev() > OMAP3430_REV_ES1_0) { 863 if (omap_rev() > OMAP3430_REV_ES1_0) {
846 cm_write_mod_reg( 864 cm_write_mod_reg(
847 OMAP3430ES2_AUTO_USBHOST, 865 OMAP3430ES2_AUTO_USBHOST_MASK,
848 OMAP3430ES2_USBHOST_MOD, 866 OMAP3430ES2_USBHOST_MOD,
849 CM_AUTOIDLE); 867 CM_AUTOIDLE);
850 } 868 }
851 869
852 omap_ctrl_writel(OMAP3430_AUTOIDLE, OMAP2_CONTROL_SYSCONFIG); 870 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
853 871
854 /* 872 /*
855 * Set all plls to autoidle. This is needed until autoidle is 873 * Set all plls to autoidle. This is needed until autoidle is
@@ -879,35 +897,40 @@ static void __init prcm_setup_regs(void)
879 OMAP3_PRM_CLKSRC_CTRL_OFFSET); 897 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
880 898
881 /* setup wakup source */ 899 /* setup wakup source */
882 prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | 900 prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
883 OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12, 901 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
884 WKUP_MOD, PM_WKEN); 902 WKUP_MOD, PM_WKEN);
885 /* No need to write EN_IO, that is always enabled */ 903 /* No need to write EN_IO, that is always enabled */
886 prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 | 904 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
887 OMAP3430_EN_GPT12, 905 OMAP3430_GRPSEL_GPT1_MASK |
906 OMAP3430_GRPSEL_GPT12_MASK,
888 WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 907 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
889 /* For some reason IO doesn't generate wakeup event even if 908 /* For some reason IO doesn't generate wakeup event even if
890 * it is selected to mpu wakeup goup */ 909 * it is selected to mpu wakeup goup */
891 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN, 910 prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
892 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 911 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
893 912
894 /* Enable PM_WKEN to support DSS LPR */ 913 /* Enable PM_WKEN to support DSS LPR */
895 prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS, 914 prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
896 OMAP3430_DSS_MOD, PM_WKEN); 915 OMAP3430_DSS_MOD, PM_WKEN);
897 916
898 /* Enable wakeups in PER */ 917 /* Enable wakeups in PER */
899 prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 | 918 prm_write_mod_reg(OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
900 OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 | 919 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
901 OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3 | 920 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
902 OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 | 921 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
903 OMAP3430_EN_MCBSP4, 922 OMAP3430_EN_MCBSP4_MASK,
904 OMAP3430_PER_MOD, PM_WKEN); 923 OMAP3430_PER_MOD, PM_WKEN);
905 /* and allow them to wake up MPU */ 924 /* and allow them to wake up MPU */
906 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 | 925 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2_MASK |
907 OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 | 926 OMAP3430_GRPSEL_GPIO3_MASK |
908 OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3 | 927 OMAP3430_GRPSEL_GPIO4_MASK |
909 OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 | 928 OMAP3430_GRPSEL_GPIO5_MASK |
910 OMAP3430_EN_MCBSP4, 929 OMAP3430_GRPSEL_GPIO6_MASK |
930 OMAP3430_GRPSEL_UART3_MASK |
931 OMAP3430_GRPSEL_MCBSP2_MASK |
932 OMAP3430_GRPSEL_MCBSP3_MASK |
933 OMAP3430_GRPSEL_MCBSP4_MASK,
911 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 934 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
912 935
913 /* Don't attach IVA interrupts */ 936 /* Don't attach IVA interrupts */
@@ -1080,14 +1103,6 @@ static int __init omap3_pm_init(void)
1080 omap3_idle_init(); 1103 omap3_idle_init();
1081 1104
1082 clkdm_add_wkdep(neon_clkdm, mpu_clkdm); 1105 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
1083 /*
1084 * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for
1085 * IO-pad wakeup. Otherwise it will unnecessarily waste power
1086 * waking up PER with every CORE wakeup - see
1087 * http://marc.info/?l=linux-omap&m=121852150710062&w=2
1088 */
1089 clkdm_add_wkdep(per_clkdm, core_clkdm);
1090
1091 if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 1106 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
1092 omap3_secure_ram_storage = 1107 omap3_secure_ram_storage =
1093 kmalloc(0x803F, GFP_KERNEL); 1108 kmalloc(0x803F, GFP_KERNEL);
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index ebfce7d1a5d3..a2904aa7065e 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -5,8 +5,8 @@
5 * Copyright (C) 2007-2009 Nokia Corporation 5 * Copyright (C) 2007-2009 Nokia Corporation
6 * 6 *
7 * Written by Paul Walmsley 7 * Written by Paul Walmsley
8 *
9 * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com> 8 * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com>
9 * State counting code by Tero Kristo <tero.kristo@nokia.com>
10 * 10 *
11 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as 12 * it under the terms of the GNU General Public License version 2 as
@@ -64,10 +64,10 @@ static u16 pwrstst_reg_offs;
64#define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK 64#define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK
65 65
66/* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */ 66/* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */
67#define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE 67#define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK
68#define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE 68#define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE_MASK
69#define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE 69#define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK
70#define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE 70#define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE_MASK
71#define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK 71#define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK
72 72
73/* OMAP3 and OMAP4 Memory Status bits */ 73/* OMAP3 and OMAP4 Memory Status bits */
@@ -511,6 +511,8 @@ int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
511 */ 511 */
512int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) 512int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
513{ 513{
514 u32 v;
515
514 if (!pwrdm) 516 if (!pwrdm)
515 return -EINVAL; 517 return -EINVAL;
516 518
@@ -526,9 +528,9 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
526 * but the type of value returned is the same for each 528 * but the type of value returned is the same for each
527 * powerdomain. 529 * powerdomain.
528 */ 530 */
529 prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE, 531 v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK);
530 (pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE)), 532 prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v,
531 pwrdm->prcm_offs, pwrstctrl_reg_offs); 533 pwrdm->prcm_offs, pwrstctrl_reg_offs);
532 534
533 return 0; 535 return 0;
534} 536}
@@ -676,8 +678,8 @@ int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
676 if (!pwrdm) 678 if (!pwrdm)
677 return -EINVAL; 679 return -EINVAL;
678 680
679 return prm_read_mod_bits_shift(pwrdm->prcm_offs, 681 return prm_read_mod_bits_shift(pwrdm->prcm_offs, pwrstst_reg_offs,
680 pwrstst_reg_offs, OMAP3430_LOGICSTATEST); 682 OMAP3430_LOGICSTATEST_MASK);
681} 683}
682 684
683/** 685/**
@@ -700,7 +702,7 @@ int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
700 * powerdomain. 702 * powerdomain.
701 */ 703 */
702 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST, 704 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST,
703 OMAP3430_LASTLOGICSTATEENTERED); 705 OMAP3430_LASTLOGICSTATEENTERED_MASK);
704} 706}
705 707
706/** 708/**
@@ -723,7 +725,7 @@ int pwrdm_read_logic_retst(struct powerdomain *pwrdm)
723 * powerdomain. 725 * powerdomain.
724 */ 726 */
725 return prm_read_mod_bits_shift(pwrdm->prcm_offs, pwrstctrl_reg_offs, 727 return prm_read_mod_bits_shift(pwrdm->prcm_offs, pwrstctrl_reg_offs,
726 OMAP3430_LOGICSTATEST); 728 OMAP3430_LOGICSTATEST_MASK);
727} 729}
728 730
729/** 731/**
@@ -978,6 +980,34 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm)
978} 980}
979 981
980/** 982/**
983 * pwrdm_set_lowpwrstchange - Request a low power state change
984 * @pwrdm: struct powerdomain *
985 *
986 * Allows a powerdomain to transtion to a lower power sleep state
987 * from an existing sleep state without waking up the powerdomain.
988 * Returns -EINVAL if the powerdomain pointer is null or if the
989 * powerdomain does not support LOWPOWERSTATECHANGE, or returns 0
990 * upon success.
991 */
992int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
993{
994 if (!pwrdm)
995 return -EINVAL;
996
997 if (!(pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE))
998 return -EINVAL;
999
1000 pr_debug("powerdomain: %s: setting LOWPOWERSTATECHANGE bit\n",
1001 pwrdm->name);
1002
1003 prm_rmw_mod_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
1004 (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
1005 pwrdm->prcm_offs, pwrstctrl_reg_offs);
1006
1007 return 0;
1008}
1009
1010/**
981 * pwrdm_wait_transition - wait for powerdomain power transition to finish 1011 * pwrdm_wait_transition - wait for powerdomain power transition to finish
982 * @pwrdm: struct powerdomain * to wait for 1012 * @pwrdm: struct powerdomain * to wait for
983 * 1013 *
@@ -1002,7 +1032,7 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm)
1002 1032
1003 /* XXX Is this udelay() value meaningful? */ 1033 /* XXX Is this udelay() value meaningful? */
1004 while ((prm_read_mod_reg(pwrdm->prcm_offs, pwrstst_reg_offs) & 1034 while ((prm_read_mod_reg(pwrdm->prcm_offs, pwrstst_reg_offs) &
1005 OMAP_INTRANSITION) && 1035 OMAP_INTRANSITION_MASK) &&
1006 (c++ < PWRDM_TRANSITION_BAILOUT)) 1036 (c++ < PWRDM_TRANSITION_BAILOUT))
1007 udelay(1); 1037 udelay(1);
1008 1038
diff --git a/arch/arm/mach-omap2/powerdomains44xx.h b/arch/arm/mach-omap2/powerdomains44xx.h
index c1015147d579..c7219513472a 100644
--- a/arch/arm/mach-omap2/powerdomains44xx.h
+++ b/arch/arm/mach-omap2/powerdomains44xx.h
@@ -1,12 +1,12 @@
1/* 1/*
2 * OMAP4 Power domains framework 2 * OMAP4 Power domains framework
3 * 3 *
4 * Copyright (C) 2009 Texas Instruments, Inc. 4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009 Nokia Corporation 5 * Copyright (C) 2009-2010 Nokia Corporation
6 * 6 *
7 * Abhijit Pagare (abhijitpagare@ti.com) 7 * Abhijit Pagare (abhijitpagare@ti.com)
8 * Benoit Cousson (b-cousson@ti.com) 8 * Benoit Cousson (b-cousson@ti.com)
9 * Paul Walmsley 9 * Paul Walmsley (paul@pwsan.com)
10 * 10 *
11 * This file is automatically generated from the OMAP hardware databases. 11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated 12 * We respectfully ask that any modifications to this file be coordinated
@@ -54,6 +54,7 @@ static struct powerdomain core_44xx_pwrdm = {
54 [3] = PWRDM_POWER_ON, /* ducati_l2ram */ 54 [3] = PWRDM_POWER_ON, /* ducati_l2ram */
55 [4] = PWRDM_POWER_ON, /* ducati_unicache */ 55 [4] = PWRDM_POWER_ON, /* ducati_unicache */
56 }, 56 },
57 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
57}; 58};
58 59
59/* gfx_44xx_pwrdm: 3D accelerator power domain */ 60/* gfx_44xx_pwrdm: 3D accelerator power domain */
@@ -69,6 +70,7 @@ static struct powerdomain gfx_44xx_pwrdm = {
69 .pwrsts_mem_on = { 70 .pwrsts_mem_on = {
70 [0] = PWRDM_POWER_ON, /* gfx_mem */ 71 [0] = PWRDM_POWER_ON, /* gfx_mem */
71 }, 72 },
73 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
72}; 74};
73 75
74/* abe_44xx_pwrdm: Audio back end power domain */ 76/* abe_44xx_pwrdm: Audio back end power domain */
@@ -87,6 +89,7 @@ static struct powerdomain abe_44xx_pwrdm = {
87 [0] = PWRDM_POWER_ON, /* aessmem */ 89 [0] = PWRDM_POWER_ON, /* aessmem */
88 [1] = PWRDM_POWER_ON, /* periphmem */ 90 [1] = PWRDM_POWER_ON, /* periphmem */
89 }, 91 },
92 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
90}; 93};
91 94
92/* dss_44xx_pwrdm: Display subsystem power domain */ 95/* dss_44xx_pwrdm: Display subsystem power domain */
@@ -103,6 +106,7 @@ static struct powerdomain dss_44xx_pwrdm = {
103 .pwrsts_mem_on = { 106 .pwrsts_mem_on = {
104 [0] = PWRDM_POWER_ON, /* dss_mem */ 107 [0] = PWRDM_POWER_ON, /* dss_mem */
105 }, 108 },
109 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
106}; 110};
107 111
108/* tesla_44xx_pwrdm: Tesla processor power domain */ 112/* tesla_44xx_pwrdm: Tesla processor power domain */
@@ -123,6 +127,7 @@ static struct powerdomain tesla_44xx_pwrdm = {
123 [1] = PWRDM_POWER_ON, /* tesla_l1 */ 127 [1] = PWRDM_POWER_ON, /* tesla_l1 */
124 [2] = PWRDM_POWER_ON, /* tesla_l2 */ 128 [2] = PWRDM_POWER_ON, /* tesla_l2 */
125 }, 129 },
130 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
126}; 131};
127 132
128/* wkup_44xx_pwrdm: Wake-up power domain */ 133/* wkup_44xx_pwrdm: Wake-up power domain */
@@ -130,7 +135,7 @@ static struct powerdomain wkup_44xx_pwrdm = {
130 .name = "wkup_pwrdm", 135 .name = "wkup_pwrdm",
131 .prcm_offs = OMAP4430_PRM_WKUP_MOD, 136 .prcm_offs = OMAP4430_PRM_WKUP_MOD,
132 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 137 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
133 .pwrsts = PWRDM_POWER_ON, 138 .pwrsts = PWRSTS_ON,
134 .banks = 1, 139 .banks = 1,
135 .pwrsts_mem_ret = { 140 .pwrsts_mem_ret = {
136 [0] = PWRDM_POWER_OFF, /* wkup_bank */ 141 [0] = PWRDM_POWER_OFF, /* wkup_bank */
@@ -143,7 +148,7 @@ static struct powerdomain wkup_44xx_pwrdm = {
143/* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ 148/* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
144static struct powerdomain cpu0_44xx_pwrdm = { 149static struct powerdomain cpu0_44xx_pwrdm = {
145 .name = "cpu0_pwrdm", 150 .name = "cpu0_pwrdm",
146 .prcm_offs = OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 151 .prcm_offs = OMAP4430_PRCM_MPU_CPU0_MOD,
147 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 152 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
148 .pwrsts = PWRSTS_OFF_RET_ON, 153 .pwrsts = PWRSTS_OFF_RET_ON,
149 .pwrsts_logic_ret = PWRSTS_OFF_RET, 154 .pwrsts_logic_ret = PWRSTS_OFF_RET,
@@ -159,7 +164,7 @@ static struct powerdomain cpu0_44xx_pwrdm = {
159/* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ 164/* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
160static struct powerdomain cpu1_44xx_pwrdm = { 165static struct powerdomain cpu1_44xx_pwrdm = {
161 .name = "cpu1_pwrdm", 166 .name = "cpu1_pwrdm",
162 .prcm_offs = OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 167 .prcm_offs = OMAP4430_PRCM_MPU_CPU1_MOD,
163 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 168 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
164 .pwrsts = PWRSTS_OFF_RET_ON, 169 .pwrsts = PWRSTS_OFF_RET_ON,
165 .pwrsts_logic_ret = PWRSTS_OFF_RET, 170 .pwrsts_logic_ret = PWRSTS_OFF_RET,
@@ -227,6 +232,7 @@ static struct powerdomain ivahd_44xx_pwrdm = {
227 [2] = PWRDM_POWER_ON, /* tcm1_mem */ 232 [2] = PWRDM_POWER_ON, /* tcm1_mem */
228 [3] = PWRDM_POWER_ON, /* tcm2_mem */ 233 [3] = PWRDM_POWER_ON, /* tcm2_mem */
229 }, 234 },
235 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
230}; 236};
231 237
232/* cam_44xx_pwrdm: Camera subsystem power domain */ 238/* cam_44xx_pwrdm: Camera subsystem power domain */
@@ -242,6 +248,7 @@ static struct powerdomain cam_44xx_pwrdm = {
242 .pwrsts_mem_on = { 248 .pwrsts_mem_on = {
243 [0] = PWRDM_POWER_ON, /* cam_mem */ 249 [0] = PWRDM_POWER_ON, /* cam_mem */
244 }, 250 },
251 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
245}; 252};
246 253
247/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */ 254/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */
@@ -258,6 +265,7 @@ static struct powerdomain l3init_44xx_pwrdm = {
258 .pwrsts_mem_on = { 265 .pwrsts_mem_on = {
259 [0] = PWRDM_POWER_ON, /* l3init_bank1 */ 266 [0] = PWRDM_POWER_ON, /* l3init_bank1 */
260 }, 267 },
268 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
261}; 269};
262 270
263/* l4per_44xx_pwrdm: Target peripherals power domain */ 271/* l4per_44xx_pwrdm: Target peripherals power domain */
@@ -276,6 +284,7 @@ static struct powerdomain l4per_44xx_pwrdm = {
276 [0] = PWRDM_POWER_ON, /* nonretained_bank */ 284 [0] = PWRDM_POWER_ON, /* nonretained_bank */
277 [1] = PWRDM_POWER_ON, /* retained_bank */ 285 [1] = PWRDM_POWER_ON, /* retained_bank */
278 }, 286 },
287 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
279}; 288};
280 289
281/* 290/*
@@ -286,7 +295,7 @@ static struct powerdomain always_on_core_44xx_pwrdm = {
286 .name = "always_on_core_pwrdm", 295 .name = "always_on_core_pwrdm",
287 .prcm_offs = OMAP4430_PRM_ALWAYS_ON_MOD, 296 .prcm_offs = OMAP4430_PRM_ALWAYS_ON_MOD,
288 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 297 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
289 .pwrsts = PWRDM_POWER_ON, 298 .pwrsts = PWRSTS_ON,
290}; 299};
291 300
292/* cefuse_44xx_pwrdm: Customer efuse controller power domain */ 301/* cefuse_44xx_pwrdm: Customer efuse controller power domain */
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 90f603d434c6..995b7edbf18d 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -112,83 +112,75 @@
112 112
113#define OMAP4430_SCRM_SCRM_MOD 0x0000 113#define OMAP4430_SCRM_SCRM_MOD 0x0000
114 114
115/* CHIRONSS instances */ 115/* PRCM_MPU instances */
116 116
117#define OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD 0x0000 117#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD 0x0000
118#define OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD 0x0200 118#define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD 0x0200
119#define OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD 0x0400 119#define OMAP4430_PRCM_MPU_CPU0_MOD 0x0400
120#define OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD 0x0800 120#define OMAP4430_PRCM_MPU_CPU1_MOD 0x0800
121
122/* Base Addresses for the OMAP4 */
123
124#define OMAP4430_CM1_BASE 0x4a004000
125#define OMAP4430_CM2_BASE 0x4a008000
126#define OMAP4430_PRM_BASE 0x4a306000
127#define OMAP4430_SCRM_BASE 0x4a30a000
128#define OMAP4430_CHIRONSS_BASE 0x48243000
129 121
130 122
131/* 24XX register bits shared between CM & PRM registers */ 123/* 24XX register bits shared between CM & PRM registers */
132 124
133/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 125/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
134#define OMAP2420_EN_MMC_SHIFT 26 126#define OMAP2420_EN_MMC_SHIFT 26
135#define OMAP2420_EN_MMC (1 << 26) 127#define OMAP2420_EN_MMC_MASK (1 << 26)
136#define OMAP24XX_EN_UART2_SHIFT 22 128#define OMAP24XX_EN_UART2_SHIFT 22
137#define OMAP24XX_EN_UART2 (1 << 22) 129#define OMAP24XX_EN_UART2_MASK (1 << 22)
138#define OMAP24XX_EN_UART1_SHIFT 21 130#define OMAP24XX_EN_UART1_SHIFT 21
139#define OMAP24XX_EN_UART1 (1 << 21) 131#define OMAP24XX_EN_UART1_MASK (1 << 21)
140#define OMAP24XX_EN_MCSPI2_SHIFT 18 132#define OMAP24XX_EN_MCSPI2_SHIFT 18
141#define OMAP24XX_EN_MCSPI2 (1 << 18) 133#define OMAP24XX_EN_MCSPI2_MASK (1 << 18)
142#define OMAP24XX_EN_MCSPI1_SHIFT 17 134#define OMAP24XX_EN_MCSPI1_SHIFT 17
143#define OMAP24XX_EN_MCSPI1 (1 << 17) 135#define OMAP24XX_EN_MCSPI1_MASK (1 << 17)
144#define OMAP24XX_EN_MCBSP2_SHIFT 16 136#define OMAP24XX_EN_MCBSP2_SHIFT 16
145#define OMAP24XX_EN_MCBSP2 (1 << 16) 137#define OMAP24XX_EN_MCBSP2_MASK (1 << 16)
146#define OMAP24XX_EN_MCBSP1_SHIFT 15 138#define OMAP24XX_EN_MCBSP1_SHIFT 15
147#define OMAP24XX_EN_MCBSP1 (1 << 15) 139#define OMAP24XX_EN_MCBSP1_MASK (1 << 15)
148#define OMAP24XX_EN_GPT12_SHIFT 14 140#define OMAP24XX_EN_GPT12_SHIFT 14
149#define OMAP24XX_EN_GPT12 (1 << 14) 141#define OMAP24XX_EN_GPT12_MASK (1 << 14)
150#define OMAP24XX_EN_GPT11_SHIFT 13 142#define OMAP24XX_EN_GPT11_SHIFT 13
151#define OMAP24XX_EN_GPT11 (1 << 13) 143#define OMAP24XX_EN_GPT11_MASK (1 << 13)
152#define OMAP24XX_EN_GPT10_SHIFT 12 144#define OMAP24XX_EN_GPT10_SHIFT 12
153#define OMAP24XX_EN_GPT10 (1 << 12) 145#define OMAP24XX_EN_GPT10_MASK (1 << 12)
154#define OMAP24XX_EN_GPT9_SHIFT 11 146#define OMAP24XX_EN_GPT9_SHIFT 11
155#define OMAP24XX_EN_GPT9 (1 << 11) 147#define OMAP24XX_EN_GPT9_MASK (1 << 11)
156#define OMAP24XX_EN_GPT8_SHIFT 10 148#define OMAP24XX_EN_GPT8_SHIFT 10
157#define OMAP24XX_EN_GPT8 (1 << 10) 149#define OMAP24XX_EN_GPT8_MASK (1 << 10)
158#define OMAP24XX_EN_GPT7_SHIFT 9 150#define OMAP24XX_EN_GPT7_SHIFT 9
159#define OMAP24XX_EN_GPT7 (1 << 9) 151#define OMAP24XX_EN_GPT7_MASK (1 << 9)
160#define OMAP24XX_EN_GPT6_SHIFT 8 152#define OMAP24XX_EN_GPT6_SHIFT 8
161#define OMAP24XX_EN_GPT6 (1 << 8) 153#define OMAP24XX_EN_GPT6_MASK (1 << 8)
162#define OMAP24XX_EN_GPT5_SHIFT 7 154#define OMAP24XX_EN_GPT5_SHIFT 7
163#define OMAP24XX_EN_GPT5 (1 << 7) 155#define OMAP24XX_EN_GPT5_MASK (1 << 7)
164#define OMAP24XX_EN_GPT4_SHIFT 6 156#define OMAP24XX_EN_GPT4_SHIFT 6
165#define OMAP24XX_EN_GPT4 (1 << 6) 157#define OMAP24XX_EN_GPT4_MASK (1 << 6)
166#define OMAP24XX_EN_GPT3_SHIFT 5 158#define OMAP24XX_EN_GPT3_SHIFT 5
167#define OMAP24XX_EN_GPT3 (1 << 5) 159#define OMAP24XX_EN_GPT3_MASK (1 << 5)
168#define OMAP24XX_EN_GPT2_SHIFT 4 160#define OMAP24XX_EN_GPT2_SHIFT 4
169#define OMAP24XX_EN_GPT2 (1 << 4) 161#define OMAP24XX_EN_GPT2_MASK (1 << 4)
170#define OMAP2420_EN_VLYNQ_SHIFT 3 162#define OMAP2420_EN_VLYNQ_SHIFT 3
171#define OMAP2420_EN_VLYNQ (1 << 3) 163#define OMAP2420_EN_VLYNQ_MASK (1 << 3)
172 164
173/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ 165/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
174#define OMAP2430_EN_GPIO5_SHIFT 10 166#define OMAP2430_EN_GPIO5_SHIFT 10
175#define OMAP2430_EN_GPIO5 (1 << 10) 167#define OMAP2430_EN_GPIO5_MASK (1 << 10)
176#define OMAP2430_EN_MCSPI3_SHIFT 9 168#define OMAP2430_EN_MCSPI3_SHIFT 9
177#define OMAP2430_EN_MCSPI3 (1 << 9) 169#define OMAP2430_EN_MCSPI3_MASK (1 << 9)
178#define OMAP2430_EN_MMCHS2_SHIFT 8 170#define OMAP2430_EN_MMCHS2_SHIFT 8
179#define OMAP2430_EN_MMCHS2 (1 << 8) 171#define OMAP2430_EN_MMCHS2_MASK (1 << 8)
180#define OMAP2430_EN_MMCHS1_SHIFT 7 172#define OMAP2430_EN_MMCHS1_SHIFT 7
181#define OMAP2430_EN_MMCHS1 (1 << 7) 173#define OMAP2430_EN_MMCHS1_MASK (1 << 7)
182#define OMAP24XX_EN_UART3_SHIFT 2 174#define OMAP24XX_EN_UART3_SHIFT 2
183#define OMAP24XX_EN_UART3 (1 << 2) 175#define OMAP24XX_EN_UART3_MASK (1 << 2)
184#define OMAP24XX_EN_USB_SHIFT 0 176#define OMAP24XX_EN_USB_SHIFT 0
185#define OMAP24XX_EN_USB (1 << 0) 177#define OMAP24XX_EN_USB_MASK (1 << 0)
186 178
187/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ 179/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
188#define OMAP2430_EN_MDM_INTC_SHIFT 11 180#define OMAP2430_EN_MDM_INTC_SHIFT 11
189#define OMAP2430_EN_MDM_INTC (1 << 11) 181#define OMAP2430_EN_MDM_INTC_MASK (1 << 11)
190#define OMAP2430_EN_USBHS_SHIFT 6 182#define OMAP2430_EN_USBHS_SHIFT 6
191#define OMAP2430_EN_USBHS (1 << 6) 183#define OMAP2430_EN_USBHS_MASK (1 << 6)
192 184
193/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ 185/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
194#define OMAP2420_ST_MMC_SHIFT 26 186#define OMAP2420_ST_MMC_SHIFT 26
@@ -246,9 +238,9 @@
246 238
247/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ 239/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
248#define OMAP24XX_EN_GPIOS_SHIFT 2 240#define OMAP24XX_EN_GPIOS_SHIFT 2
249#define OMAP24XX_EN_GPIOS (1 << 2) 241#define OMAP24XX_EN_GPIOS_MASK (1 << 2)
250#define OMAP24XX_EN_GPT1_SHIFT 0 242#define OMAP24XX_EN_GPT1_SHIFT 0
251#define OMAP24XX_EN_GPT1 (1 << 0) 243#define OMAP24XX_EN_GPT1_MASK (1 << 0)
252 244
253/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ 245/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
254#define OMAP24XX_ST_GPIOS_SHIFT (1 << 2) 246#define OMAP24XX_ST_GPIOS_SHIFT (1 << 2)
@@ -267,47 +259,47 @@
267#define OMAP3430_REV_MASK (0xff << 0) 259#define OMAP3430_REV_MASK (0xff << 0)
268 260
269/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */ 261/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
270#define OMAP3430_AUTOIDLE (1 << 0) 262#define OMAP3430_AUTOIDLE_MASK (1 << 0)
271 263
272/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 264/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
273#define OMAP3430_EN_MMC2 (1 << 25) 265#define OMAP3430_EN_MMC2_MASK (1 << 25)
274#define OMAP3430_EN_MMC2_SHIFT 25 266#define OMAP3430_EN_MMC2_SHIFT 25
275#define OMAP3430_EN_MMC1 (1 << 24) 267#define OMAP3430_EN_MMC1_MASK (1 << 24)
276#define OMAP3430_EN_MMC1_SHIFT 24 268#define OMAP3430_EN_MMC1_SHIFT 24
277#define OMAP3430_EN_MCSPI4 (1 << 21) 269#define OMAP3430_EN_MCSPI4_MASK (1 << 21)
278#define OMAP3430_EN_MCSPI4_SHIFT 21 270#define OMAP3430_EN_MCSPI4_SHIFT 21
279#define OMAP3430_EN_MCSPI3 (1 << 20) 271#define OMAP3430_EN_MCSPI3_MASK (1 << 20)
280#define OMAP3430_EN_MCSPI3_SHIFT 20 272#define OMAP3430_EN_MCSPI3_SHIFT 20
281#define OMAP3430_EN_MCSPI2 (1 << 19) 273#define OMAP3430_EN_MCSPI2_MASK (1 << 19)
282#define OMAP3430_EN_MCSPI2_SHIFT 19 274#define OMAP3430_EN_MCSPI2_SHIFT 19
283#define OMAP3430_EN_MCSPI1 (1 << 18) 275#define OMAP3430_EN_MCSPI1_MASK (1 << 18)
284#define OMAP3430_EN_MCSPI1_SHIFT 18 276#define OMAP3430_EN_MCSPI1_SHIFT 18
285#define OMAP3430_EN_I2C3 (1 << 17) 277#define OMAP3430_EN_I2C3_MASK (1 << 17)
286#define OMAP3430_EN_I2C3_SHIFT 17 278#define OMAP3430_EN_I2C3_SHIFT 17
287#define OMAP3430_EN_I2C2 (1 << 16) 279#define OMAP3430_EN_I2C2_MASK (1 << 16)
288#define OMAP3430_EN_I2C2_SHIFT 16 280#define OMAP3430_EN_I2C2_SHIFT 16
289#define OMAP3430_EN_I2C1 (1 << 15) 281#define OMAP3430_EN_I2C1_MASK (1 << 15)
290#define OMAP3430_EN_I2C1_SHIFT 15 282#define OMAP3430_EN_I2C1_SHIFT 15
291#define OMAP3430_EN_UART2 (1 << 14) 283#define OMAP3430_EN_UART2_MASK (1 << 14)
292#define OMAP3430_EN_UART2_SHIFT 14 284#define OMAP3430_EN_UART2_SHIFT 14
293#define OMAP3430_EN_UART1 (1 << 13) 285#define OMAP3430_EN_UART1_MASK (1 << 13)
294#define OMAP3430_EN_UART1_SHIFT 13 286#define OMAP3430_EN_UART1_SHIFT 13
295#define OMAP3430_EN_GPT11 (1 << 12) 287#define OMAP3430_EN_GPT11_MASK (1 << 12)
296#define OMAP3430_EN_GPT11_SHIFT 12 288#define OMAP3430_EN_GPT11_SHIFT 12
297#define OMAP3430_EN_GPT10 (1 << 11) 289#define OMAP3430_EN_GPT10_MASK (1 << 11)
298#define OMAP3430_EN_GPT10_SHIFT 11 290#define OMAP3430_EN_GPT10_SHIFT 11
299#define OMAP3430_EN_MCBSP5 (1 << 10) 291#define OMAP3430_EN_MCBSP5_MASK (1 << 10)
300#define OMAP3430_EN_MCBSP5_SHIFT 10 292#define OMAP3430_EN_MCBSP5_SHIFT 10
301#define OMAP3430_EN_MCBSP1 (1 << 9) 293#define OMAP3430_EN_MCBSP1_MASK (1 << 9)
302#define OMAP3430_EN_MCBSP1_SHIFT 9 294#define OMAP3430_EN_MCBSP1_SHIFT 9
303#define OMAP3430_EN_FSHOSTUSB (1 << 5) 295#define OMAP3430_EN_FSHOSTUSB_MASK (1 << 5)
304#define OMAP3430_EN_FSHOSTUSB_SHIFT 5 296#define OMAP3430_EN_FSHOSTUSB_SHIFT 5
305#define OMAP3430_EN_D2D (1 << 3) 297#define OMAP3430_EN_D2D_MASK (1 << 3)
306#define OMAP3430_EN_D2D_SHIFT 3 298#define OMAP3430_EN_D2D_SHIFT 3
307 299
308/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 300/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
309#define OMAP3430_EN_HSOTGUSB (1 << 4) 301#define OMAP3430_EN_HSOTGUSB_MASK (1 << 4)
310#define OMAP3430_EN_HSOTGUSB_SHIFT 4 302#define OMAP3430_EN_HSOTGUSB_SHIFT 4
311 303
312/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ 304/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
313#define OMAP3430_ST_MMC2_SHIFT 25 305#define OMAP3430_ST_MMC2_SHIFT 25
@@ -352,21 +344,21 @@
352#define OMAP3430_ST_D2D_MASK (1 << 3) 344#define OMAP3430_ST_D2D_MASK (1 << 3)
353 345
354/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ 346/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
355#define OMAP3430_EN_GPIO1 (1 << 3) 347#define OMAP3430_EN_GPIO1_MASK (1 << 3)
356#define OMAP3430_EN_GPIO1_SHIFT 3 348#define OMAP3430_EN_GPIO1_SHIFT 3
357#define OMAP3430_EN_GPT12 (1 << 1) 349#define OMAP3430_EN_GPT12_MASK (1 << 1)
358#define OMAP3430_EN_GPT12_SHIFT 1 350#define OMAP3430_EN_GPT12_SHIFT 1
359#define OMAP3430_EN_GPT1 (1 << 0) 351#define OMAP3430_EN_GPT1_MASK (1 << 0)
360#define OMAP3430_EN_GPT1_SHIFT 0 352#define OMAP3430_EN_GPT1_SHIFT 0
361 353
362/* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */ 354/* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
363#define OMAP3430_EN_SR2 (1 << 7) 355#define OMAP3430_EN_SR2_MASK (1 << 7)
364#define OMAP3430_EN_SR2_SHIFT 7 356#define OMAP3430_EN_SR2_SHIFT 7
365#define OMAP3430_EN_SR1 (1 << 6) 357#define OMAP3430_EN_SR1_MASK (1 << 6)
366#define OMAP3430_EN_SR1_SHIFT 6 358#define OMAP3430_EN_SR1_SHIFT 6
367 359
368/* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ 360/* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
369#define OMAP3430_EN_GPT12 (1 << 1) 361#define OMAP3430_EN_GPT12_MASK (1 << 1)
370#define OMAP3430_EN_GPT12_SHIFT 1 362#define OMAP3430_EN_GPT12_SHIFT 1
371 363
372/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */ 364/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
@@ -386,47 +378,47 @@
386 * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX, 378 * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
387 * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits 379 * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
388 */ 380 */
389#define OMAP3430_EN_MPU (1 << 1) 381#define OMAP3430_EN_MPU_MASK (1 << 1)
390#define OMAP3430_EN_MPU_SHIFT 1 382#define OMAP3430_EN_MPU_SHIFT 1
391 383
392/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */ 384/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
393#define OMAP3430_EN_GPIO6 (1 << 17) 385#define OMAP3430_EN_GPIO6_MASK (1 << 17)
394#define OMAP3430_EN_GPIO6_SHIFT 17 386#define OMAP3430_EN_GPIO6_SHIFT 17
395#define OMAP3430_EN_GPIO5 (1 << 16) 387#define OMAP3430_EN_GPIO5_MASK (1 << 16)
396#define OMAP3430_EN_GPIO5_SHIFT 16 388#define OMAP3430_EN_GPIO5_SHIFT 16
397#define OMAP3430_EN_GPIO4 (1 << 15) 389#define OMAP3430_EN_GPIO4_MASK (1 << 15)
398#define OMAP3430_EN_GPIO4_SHIFT 15 390#define OMAP3430_EN_GPIO4_SHIFT 15
399#define OMAP3430_EN_GPIO3 (1 << 14) 391#define OMAP3430_EN_GPIO3_MASK (1 << 14)
400#define OMAP3430_EN_GPIO3_SHIFT 14 392#define OMAP3430_EN_GPIO3_SHIFT 14
401#define OMAP3430_EN_GPIO2 (1 << 13) 393#define OMAP3430_EN_GPIO2_MASK (1 << 13)
402#define OMAP3430_EN_GPIO2_SHIFT 13 394#define OMAP3430_EN_GPIO2_SHIFT 13
403#define OMAP3430_EN_UART3 (1 << 11) 395#define OMAP3430_EN_UART3_MASK (1 << 11)
404#define OMAP3430_EN_UART3_SHIFT 11 396#define OMAP3430_EN_UART3_SHIFT 11
405#define OMAP3430_EN_GPT9 (1 << 10) 397#define OMAP3430_EN_GPT9_MASK (1 << 10)
406#define OMAP3430_EN_GPT9_SHIFT 10 398#define OMAP3430_EN_GPT9_SHIFT 10
407#define OMAP3430_EN_GPT8 (1 << 9) 399#define OMAP3430_EN_GPT8_MASK (1 << 9)
408#define OMAP3430_EN_GPT8_SHIFT 9 400#define OMAP3430_EN_GPT8_SHIFT 9
409#define OMAP3430_EN_GPT7 (1 << 8) 401#define OMAP3430_EN_GPT7_MASK (1 << 8)
410#define OMAP3430_EN_GPT7_SHIFT 8 402#define OMAP3430_EN_GPT7_SHIFT 8
411#define OMAP3430_EN_GPT6 (1 << 7) 403#define OMAP3430_EN_GPT6_MASK (1 << 7)
412#define OMAP3430_EN_GPT6_SHIFT 7 404#define OMAP3430_EN_GPT6_SHIFT 7
413#define OMAP3430_EN_GPT5 (1 << 6) 405#define OMAP3430_EN_GPT5_MASK (1 << 6)
414#define OMAP3430_EN_GPT5_SHIFT 6 406#define OMAP3430_EN_GPT5_SHIFT 6
415#define OMAP3430_EN_GPT4 (1 << 5) 407#define OMAP3430_EN_GPT4_MASK (1 << 5)
416#define OMAP3430_EN_GPT4_SHIFT 5 408#define OMAP3430_EN_GPT4_SHIFT 5
417#define OMAP3430_EN_GPT3 (1 << 4) 409#define OMAP3430_EN_GPT3_MASK (1 << 4)
418#define OMAP3430_EN_GPT3_SHIFT 4 410#define OMAP3430_EN_GPT3_SHIFT 4
419#define OMAP3430_EN_GPT2 (1 << 3) 411#define OMAP3430_EN_GPT2_MASK (1 << 3)
420#define OMAP3430_EN_GPT2_SHIFT 3 412#define OMAP3430_EN_GPT2_SHIFT 3
421 413
422/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */ 414/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
423/* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits 415/* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
424 * be ST_* bits instead? */ 416 * be ST_* bits instead? */
425#define OMAP3430_EN_MCBSP4 (1 << 2) 417#define OMAP3430_EN_MCBSP4_MASK (1 << 2)
426#define OMAP3430_EN_MCBSP4_SHIFT 2 418#define OMAP3430_EN_MCBSP4_SHIFT 2
427#define OMAP3430_EN_MCBSP3 (1 << 1) 419#define OMAP3430_EN_MCBSP3_MASK (1 << 1)
428#define OMAP3430_EN_MCBSP3_SHIFT 1 420#define OMAP3430_EN_MCBSP3_SHIFT 1
429#define OMAP3430_EN_MCBSP2 (1 << 0) 421#define OMAP3430_EN_MCBSP2_MASK (1 << 0)
430#define OMAP3430_EN_MCBSP2_SHIFT 0 422#define OMAP3430_EN_MCBSP2_SHIFT 0
431 423
432/* CM_IDLEST_PER, PM_WKST_PER shared bits */ 424/* CM_IDLEST_PER, PM_WKST_PER shared bits */
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 07a60f1204ca..c20137497c92 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -158,10 +158,10 @@ void omap_prcm_arch_reset(char mode, const char *cmd)
158 WARN_ON(1); 158 WARN_ON(1);
159 159
160 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 160 if (cpu_is_omap24xx() || cpu_is_omap34xx())
161 prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, 161 prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
162 OMAP2_RM_RSTCTRL); 162 OMAP2_RM_RSTCTRL);
163 if (cpu_is_omap44xx()) 163 if (cpu_is_omap44xx())
164 prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, 164 prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
165 OMAP4_RM_RSTCTRL); 165 OMAP4_RM_RSTCTRL);
166} 166}
167 167
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
index 4002051c20b9..0b188ffa710e 100644
--- a/arch/arm/mach-omap2/prm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
@@ -19,14 +19,14 @@
19/* Bits shared between registers */ 19/* Bits shared between registers */
20 20
21/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */ 21/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */
22#define OMAP24XX_VOLTTRANS_ST (1 << 2) 22#define OMAP24XX_VOLTTRANS_ST_MASK (1 << 2)
23#define OMAP24XX_WKUP2_ST (1 << 1) 23#define OMAP24XX_WKUP2_ST_MASK (1 << 1)
24#define OMAP24XX_WKUP1_ST (1 << 0) 24#define OMAP24XX_WKUP1_ST_MASK (1 << 0)
25 25
26/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */ 26/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */
27#define OMAP24XX_VOLTTRANS_EN (1 << 2) 27#define OMAP24XX_VOLTTRANS_EN_MASK (1 << 2)
28#define OMAP24XX_WKUP2_EN (1 << 1) 28#define OMAP24XX_WKUP2_EN_MASK (1 << 1)
29#define OMAP24XX_WKUP1_EN (1 << 0) 29#define OMAP24XX_WKUP1_EN_MASK (1 << 0)
30 30
31/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */ 31/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
32#define OMAP24XX_EN_MPU_SHIFT 1 32#define OMAP24XX_EN_MPU_SHIFT 1
@@ -40,16 +40,16 @@
40 */ 40 */
41#define OMAP24XX_MEMONSTATE_SHIFT 10 41#define OMAP24XX_MEMONSTATE_SHIFT 10
42#define OMAP24XX_MEMONSTATE_MASK (0x3 << 10) 42#define OMAP24XX_MEMONSTATE_MASK (0x3 << 10)
43#define OMAP24XX_MEMRETSTATE (1 << 3) 43#define OMAP24XX_MEMRETSTATE_MASK (1 << 3)
44 44
45/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */ 45/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */
46#define OMAP24XX_FORCESTATE (1 << 18) 46#define OMAP24XX_FORCESTATE_MASK (1 << 18)
47 47
48/* 48/*
49 * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP, 49 * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP,
50 * PM_PWSTST_MDM shared bits 50 * PM_PWSTST_MDM shared bits
51 */ 51 */
52#define OMAP24XX_CLKACTIVITY (1 << 19) 52#define OMAP24XX_CLKACTIVITY_MASK (1 << 19)
53 53
54/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */ 54/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */
55#define OMAP24XX_LASTSTATEENTERED_SHIFT 4 55#define OMAP24XX_LASTSTATEENTERED_SHIFT 4
@@ -71,26 +71,26 @@
71#define OMAP24XX_REV_MASK (0xff << 0) 71#define OMAP24XX_REV_MASK (0xff << 0)
72 72
73/* PRCM_SYSCONFIG */ 73/* PRCM_SYSCONFIG */
74#define OMAP24XX_AUTOIDLE (1 << 0) 74#define OMAP24XX_AUTOIDLE_MASK (1 << 0)
75 75
76/* PRCM_IRQSTATUS_MPU specific bits */ 76/* PRCM_IRQSTATUS_MPU specific bits */
77#define OMAP2430_DPLL_RECAL_ST (1 << 6) 77#define OMAP2430_DPLL_RECAL_ST_MASK (1 << 6)
78#define OMAP24XX_TRANSITION_ST (1 << 5) 78#define OMAP24XX_TRANSITION_ST_MASK (1 << 5)
79#define OMAP24XX_EVGENOFF_ST (1 << 4) 79#define OMAP24XX_EVGENOFF_ST_MASK (1 << 4)
80#define OMAP24XX_EVGENON_ST (1 << 3) 80#define OMAP24XX_EVGENON_ST_MASK (1 << 3)
81 81
82/* PRCM_IRQENABLE_MPU specific bits */ 82/* PRCM_IRQENABLE_MPU specific bits */
83#define OMAP2430_DPLL_RECAL_EN (1 << 6) 83#define OMAP2430_DPLL_RECAL_EN_MASK (1 << 6)
84#define OMAP24XX_TRANSITION_EN (1 << 5) 84#define OMAP24XX_TRANSITION_EN_MASK (1 << 5)
85#define OMAP24XX_EVGENOFF_EN (1 << 4) 85#define OMAP24XX_EVGENOFF_EN_MASK (1 << 4)
86#define OMAP24XX_EVGENON_EN (1 << 3) 86#define OMAP24XX_EVGENON_EN_MASK (1 << 3)
87 87
88/* PRCM_VOLTCTRL */ 88/* PRCM_VOLTCTRL */
89#define OMAP24XX_AUTO_EXTVOLT (1 << 15) 89#define OMAP24XX_AUTO_EXTVOLT_MASK (1 << 15)
90#define OMAP24XX_FORCE_EXTVOLT (1 << 14) 90#define OMAP24XX_FORCE_EXTVOLT_MASK (1 << 14)
91#define OMAP24XX_SETOFF_LEVEL_SHIFT 12 91#define OMAP24XX_SETOFF_LEVEL_SHIFT 12
92#define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12) 92#define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12)
93#define OMAP24XX_MEMRETCTRL (1 << 8) 93#define OMAP24XX_MEMRETCTRL_MASK (1 << 8)
94#define OMAP24XX_SETRET_LEVEL_SHIFT 6 94#define OMAP24XX_SETRET_LEVEL_SHIFT 6
95#define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6) 95#define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6)
96#define OMAP24XX_VOLT_LEVEL_SHIFT 0 96#define OMAP24XX_VOLT_LEVEL_SHIFT 0
@@ -104,13 +104,13 @@
104 104
105/* PRCM_CLKOUT_CTRL */ 105/* PRCM_CLKOUT_CTRL */
106#define OMAP2420_CLKOUT2_EN_SHIFT 15 106#define OMAP2420_CLKOUT2_EN_SHIFT 15
107#define OMAP2420_CLKOUT2_EN (1 << 15) 107#define OMAP2420_CLKOUT2_EN_MASK (1 << 15)
108#define OMAP2420_CLKOUT2_DIV_SHIFT 11 108#define OMAP2420_CLKOUT2_DIV_SHIFT 11
109#define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11) 109#define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11)
110#define OMAP2420_CLKOUT2_SOURCE_SHIFT 8 110#define OMAP2420_CLKOUT2_SOURCE_SHIFT 8
111#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8) 111#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8)
112#define OMAP24XX_CLKOUT_EN_SHIFT 7 112#define OMAP24XX_CLKOUT_EN_SHIFT 7
113#define OMAP24XX_CLKOUT_EN (1 << 7) 113#define OMAP24XX_CLKOUT_EN_MASK (1 << 7)
114#define OMAP24XX_CLKOUT_DIV_SHIFT 3 114#define OMAP24XX_CLKOUT_DIV_SHIFT 3
115#define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3) 115#define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3)
116#define OMAP24XX_CLKOUT_SOURCE_SHIFT 0 116#define OMAP24XX_CLKOUT_SOURCE_SHIFT 0
@@ -118,25 +118,25 @@
118 118
119/* PRCM_CLKEMUL_CTRL */ 119/* PRCM_CLKEMUL_CTRL */
120#define OMAP24XX_EMULATION_EN_SHIFT 0 120#define OMAP24XX_EMULATION_EN_SHIFT 0
121#define OMAP24XX_EMULATION_EN (1 << 0) 121#define OMAP24XX_EMULATION_EN_MASK (1 << 0)
122 122
123/* PRCM_CLKCFG_CTRL */ 123/* PRCM_CLKCFG_CTRL */
124#define OMAP24XX_VALID_CONFIG (1 << 0) 124#define OMAP24XX_VALID_CONFIG_MASK (1 << 0)
125 125
126/* PRCM_CLKCFG_STATUS */ 126/* PRCM_CLKCFG_STATUS */
127#define OMAP24XX_CONFIG_STATUS (1 << 0) 127#define OMAP24XX_CONFIG_STATUS_MASK (1 << 0)
128 128
129/* PRCM_VOLTSETUP specific bits */ 129/* PRCM_VOLTSETUP specific bits */
130 130
131/* PRCM_CLKSSETUP specific bits */ 131/* PRCM_CLKSSETUP specific bits */
132 132
133/* PRCM_POLCTRL */ 133/* PRCM_POLCTRL */
134#define OMAP2420_CLKOUT2_POL (1 << 10) 134#define OMAP2420_CLKOUT2_POL_MASK (1 << 10)
135#define OMAP24XX_CLKOUT_POL (1 << 9) 135#define OMAP24XX_CLKOUT_POL_MASK (1 << 9)
136#define OMAP24XX_CLKREQ_POL (1 << 8) 136#define OMAP24XX_CLKREQ_POL_MASK (1 << 8)
137#define OMAP2430_USE_POWEROK (1 << 2) 137#define OMAP2430_USE_POWEROK_MASK (1 << 2)
138#define OMAP2430_POWEROK_POL (1 << 1) 138#define OMAP2430_POWEROK_POL_MASK (1 << 1)
139#define OMAP24XX_EXTVOL_POL (1 << 0) 139#define OMAP24XX_EXTVOL_POL_MASK (1 << 0)
140 140
141/* RM_RSTST_MPU specific bits */ 141/* RM_RSTST_MPU specific bits */
142/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */ 142/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
@@ -154,7 +154,7 @@
154/* PM_EVEGENOFFTIM_MPU specific bits */ 154/* PM_EVEGENOFFTIM_MPU specific bits */
155 155
156/* PM_PWSTCTRL_MPU specific bits */ 156/* PM_PWSTCTRL_MPU specific bits */
157#define OMAP2430_FORCESTATE (1 << 18) 157#define OMAP2430_FORCESTATE_MASK (1 << 18)
158 158
159/* PM_PWSTST_MPU specific bits */ 159/* PM_PWSTST_MPU specific bits */
160/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */ 160/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */
@@ -168,21 +168,21 @@
168/* PM_WKST2_CORE specific bits */ 168/* PM_WKST2_CORE specific bits */
169 169
170/* PM_WKDEP_CORE specific bits*/ 170/* PM_WKDEP_CORE specific bits*/
171#define OMAP2430_PM_WKDEP_CORE_EN_MDM (1 << 5) 171#define OMAP2430_PM_WKDEP_CORE_EN_MDM_MASK (1 << 5)
172#define OMAP24XX_PM_WKDEP_CORE_EN_GFX (1 << 3) 172#define OMAP24XX_PM_WKDEP_CORE_EN_GFX_MASK (1 << 3)
173#define OMAP24XX_PM_WKDEP_CORE_EN_DSP (1 << 2) 173#define OMAP24XX_PM_WKDEP_CORE_EN_DSP_MASK (1 << 2)
174 174
175/* PM_PWSTCTRL_CORE specific bits */ 175/* PM_PWSTCTRL_CORE specific bits */
176#define OMAP24XX_MEMORYCHANGE (1 << 20) 176#define OMAP24XX_MEMORYCHANGE_MASK (1 << 20)
177#define OMAP24XX_MEM3ONSTATE_SHIFT 14 177#define OMAP24XX_MEM3ONSTATE_SHIFT 14
178#define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14) 178#define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14)
179#define OMAP24XX_MEM2ONSTATE_SHIFT 12 179#define OMAP24XX_MEM2ONSTATE_SHIFT 12
180#define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12) 180#define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12)
181#define OMAP24XX_MEM1ONSTATE_SHIFT 10 181#define OMAP24XX_MEM1ONSTATE_SHIFT 10
182#define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10) 182#define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10)
183#define OMAP24XX_MEM3RETSTATE (1 << 5) 183#define OMAP24XX_MEM3RETSTATE_MASK (1 << 5)
184#define OMAP24XX_MEM2RETSTATE (1 << 4) 184#define OMAP24XX_MEM2RETSTATE_MASK (1 << 4)
185#define OMAP24XX_MEM1RETSTATE (1 << 3) 185#define OMAP24XX_MEM1RETSTATE_MASK (1 << 3)
186 186
187/* PM_PWSTST_CORE specific bits */ 187/* PM_PWSTST_CORE specific bits */
188#define OMAP24XX_MEM3STATEST_SHIFT 14 188#define OMAP24XX_MEM3STATEST_SHIFT 14
@@ -193,10 +193,10 @@
193#define OMAP24XX_MEM1STATEST_MASK (0x3 << 10) 193#define OMAP24XX_MEM1STATEST_MASK (0x3 << 10)
194 194
195/* RM_RSTCTRL_GFX */ 195/* RM_RSTCTRL_GFX */
196#define OMAP24XX_GFX_RST (1 << 0) 196#define OMAP24XX_GFX_RST_MASK (1 << 0)
197 197
198/* RM_RSTST_GFX specific bits */ 198/* RM_RSTST_GFX specific bits */
199#define OMAP24XX_GFX_SW_RST (1 << 4) 199#define OMAP24XX_GFX_SW_RST_MASK (1 << 4)
200 200
201/* PM_PWSTCTRL_GFX specific bits */ 201/* PM_PWSTCTRL_GFX specific bits */
202 202
@@ -209,25 +209,25 @@
209 209
210/* RM_RSTST_WKUP specific bits */ 210/* RM_RSTST_WKUP specific bits */
211/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */ 211/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
212#define OMAP24XX_EXTWMPU_RST (1 << 6) 212#define OMAP24XX_EXTWMPU_RST_MASK (1 << 6)
213#define OMAP24XX_SECU_WD_RST (1 << 5) 213#define OMAP24XX_SECU_WD_RST_MASK (1 << 5)
214#define OMAP24XX_MPU_WD_RST (1 << 4) 214#define OMAP24XX_MPU_WD_RST_MASK (1 << 4)
215#define OMAP24XX_SECU_VIOL_RST (1 << 3) 215#define OMAP24XX_SECU_VIOL_RST_MASK (1 << 3)
216 216
217/* PM_WKEN_WKUP specific bits */ 217/* PM_WKEN_WKUP specific bits */
218 218
219/* PM_WKST_WKUP specific bits */ 219/* PM_WKST_WKUP specific bits */
220 220
221/* RM_RSTCTRL_DSP */ 221/* RM_RSTCTRL_DSP */
222#define OMAP2420_RST_IVA (1 << 8) 222#define OMAP2420_RST_IVA_MASK (1 << 8)
223#define OMAP24XX_RST2_DSP (1 << 1) 223#define OMAP24XX_RST2_DSP_MASK (1 << 1)
224#define OMAP24XX_RST1_DSP (1 << 0) 224#define OMAP24XX_RST1_DSP_MASK (1 << 0)
225 225
226/* RM_RSTST_DSP specific bits */ 226/* RM_RSTST_DSP specific bits */
227/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */ 227/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */
228#define OMAP2420_IVA_SW_RST (1 << 8) 228#define OMAP2420_IVA_SW_RST_MASK (1 << 8)
229#define OMAP24XX_DSP_SW_RST2 (1 << 5) 229#define OMAP24XX_DSP_SW_RST2_MASK (1 << 5)
230#define OMAP24XX_DSP_SW_RST1 (1 << 4) 230#define OMAP24XX_DSP_SW_RST1_MASK (1 << 4)
231 231
232/* PM_WKDEP_DSP specific bits */ 232/* PM_WKDEP_DSP specific bits */
233 233
@@ -235,7 +235,7 @@
235/* 2430 only: MEMONSTATE, MEMRETSTATE */ 235/* 2430 only: MEMONSTATE, MEMRETSTATE */
236#define OMAP2420_MEMIONSTATE_SHIFT 12 236#define OMAP2420_MEMIONSTATE_SHIFT 12
237#define OMAP2420_MEMIONSTATE_MASK (0x3 << 12) 237#define OMAP2420_MEMIONSTATE_MASK (0x3 << 12)
238#define OMAP2420_MEMIRETSTATE (1 << 4) 238#define OMAP2420_MEMIRETSTATE_MASK (1 << 4)
239 239
240/* PM_PWSTST_DSP specific bits */ 240/* PM_PWSTST_DSP specific bits */
241/* MEMSTATEST is 2430 only */ 241/* MEMSTATEST is 2430 only */
@@ -248,18 +248,18 @@
248 248
249/* RM_RSTCTRL_MDM */ 249/* RM_RSTCTRL_MDM */
250/* 2430 only */ 250/* 2430 only */
251#define OMAP2430_PWRON1_MDM (1 << 1) 251#define OMAP2430_PWRON1_MDM_MASK (1 << 1)
252#define OMAP2430_RST1_MDM (1 << 0) 252#define OMAP2430_RST1_MDM_MASK (1 << 0)
253 253
254/* RM_RSTST_MDM specific bits */ 254/* RM_RSTST_MDM specific bits */
255/* 2430 only */ 255/* 2430 only */
256#define OMAP2430_MDM_SECU_VIOL (1 << 6) 256#define OMAP2430_MDM_SECU_VIOL_MASK (1 << 6)
257#define OMAP2430_MDM_SW_PWRON1 (1 << 5) 257#define OMAP2430_MDM_SW_PWRON1_MASK (1 << 5)
258#define OMAP2430_MDM_SW_RST1 (1 << 4) 258#define OMAP2430_MDM_SW_RST1_MASK (1 << 4)
259 259
260/* PM_WKEN_MDM */ 260/* PM_WKEN_MDM */
261/* 2430 only */ 261/* 2430 only */
262#define OMAP2430_PM_WKEN_MDM_EN_MDM (1 << 0) 262#define OMAP2430_PM_WKEN_MDM_EN_MDM_MASK (1 << 0)
263 263
264/* PM_WKST_MDM specific bits */ 264/* PM_WKST_MDM specific bits */
265/* 2430 only */ 265/* 2430 only */
@@ -269,7 +269,7 @@
269 269
270/* PM_PWSTCTRL_MDM specific bits */ 270/* PM_PWSTCTRL_MDM specific bits */
271/* 2430 only */ 271/* 2430 only */
272#define OMAP2430_KILLDOMAINWKUP (1 << 19) 272#define OMAP2430_KILLDOMAINWKUP_MASK (1 << 19)
273 273
274/* PM_PWSTST_MDM specific bits */ 274/* PM_PWSTST_MDM specific bits */
275/* 2430 only */ 275/* 2430 only */
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index 8f21bae6dc1c..7fd6023edf96 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -35,10 +35,10 @@
35#define OMAP3430_ERRORGAIN_MASK (0xff << 16) 35#define OMAP3430_ERRORGAIN_MASK (0xff << 16)
36#define OMAP3430_INITVOLTAGE_SHIFT 8 36#define OMAP3430_INITVOLTAGE_SHIFT 8
37#define OMAP3430_INITVOLTAGE_MASK (0xff << 8) 37#define OMAP3430_INITVOLTAGE_MASK (0xff << 8)
38#define OMAP3430_TIMEOUTEN (1 << 3) 38#define OMAP3430_TIMEOUTEN_MASK (1 << 3)
39#define OMAP3430_INITVDD (1 << 2) 39#define OMAP3430_INITVDD_MASK (1 << 2)
40#define OMAP3430_FORCEUPDATE (1 << 1) 40#define OMAP3430_FORCEUPDATE_MASK (1 << 1)
41#define OMAP3430_VPENABLE (1 << 0) 41#define OMAP3430_VPENABLE_MASK (1 << 0)
42 42
43/* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */ 43/* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
44#define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8 44#define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8
@@ -65,53 +65,53 @@
65#define OMAP3430_VPVOLTAGE_MASK (0xff << 0) 65#define OMAP3430_VPVOLTAGE_MASK (0xff << 0)
66 66
67/* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */ 67/* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
68#define OMAP3430_VPINIDLE (1 << 0) 68#define OMAP3430_VPINIDLE_MASK (1 << 0)
69 69
70/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */ 70/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
71#define OMAP3430_EN_PER_SHIFT 7 71#define OMAP3430_EN_PER_SHIFT 7
72#define OMAP3430_EN_PER_MASK (1 << 7) 72#define OMAP3430_EN_PER_MASK (1 << 7)
73 73
74/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */ 74/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
75#define OMAP3430_MEMORYCHANGE (1 << 3) 75#define OMAP3430_MEMORYCHANGE_MASK (1 << 3)
76 76
77/* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */ 77/* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
78#define OMAP3430_LOGICSTATEST (1 << 2) 78#define OMAP3430_LOGICSTATEST_MASK (1 << 2)
79 79
80/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */ 80/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
81#define OMAP3430_LASTLOGICSTATEENTERED (1 << 2) 81#define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2)
82 82
83/* 83/*
84 * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE, 84 * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
85 * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM, 85 * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
86 * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits 86 * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
87 */ 87 */
88#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0 88#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0
89#define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0) 89#define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0)
90 90
91/* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */ 91/* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
92#define OMAP3430_WKUP_ST (1 << 0) 92#define OMAP3430_WKUP_ST_MASK (1 << 0)
93 93
94/* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */ 94/* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
95#define OMAP3430_WKUP_EN (1 << 0) 95#define OMAP3430_WKUP_EN_MASK (1 << 0)
96 96
97/* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */ 97/* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
98#define OMAP3430_GRPSEL_MMC2 (1 << 25) 98#define OMAP3430_GRPSEL_MMC2_MASK (1 << 25)
99#define OMAP3430_GRPSEL_MMC1 (1 << 24) 99#define OMAP3430_GRPSEL_MMC1_MASK (1 << 24)
100#define OMAP3430_GRPSEL_MCSPI4 (1 << 21) 100#define OMAP3430_GRPSEL_MCSPI4_MASK (1 << 21)
101#define OMAP3430_GRPSEL_MCSPI3 (1 << 20) 101#define OMAP3430_GRPSEL_MCSPI3_MASK (1 << 20)
102#define OMAP3430_GRPSEL_MCSPI2 (1 << 19) 102#define OMAP3430_GRPSEL_MCSPI2_MASK (1 << 19)
103#define OMAP3430_GRPSEL_MCSPI1 (1 << 18) 103#define OMAP3430_GRPSEL_MCSPI1_MASK (1 << 18)
104#define OMAP3430_GRPSEL_I2C3 (1 << 17) 104#define OMAP3430_GRPSEL_I2C3_MASK (1 << 17)
105#define OMAP3430_GRPSEL_I2C2 (1 << 16) 105#define OMAP3430_GRPSEL_I2C2_MASK (1 << 16)
106#define OMAP3430_GRPSEL_I2C1 (1 << 15) 106#define OMAP3430_GRPSEL_I2C1_MASK (1 << 15)
107#define OMAP3430_GRPSEL_UART2 (1 << 14) 107#define OMAP3430_GRPSEL_UART2_MASK (1 << 14)
108#define OMAP3430_GRPSEL_UART1 (1 << 13) 108#define OMAP3430_GRPSEL_UART1_MASK (1 << 13)
109#define OMAP3430_GRPSEL_GPT11 (1 << 12) 109#define OMAP3430_GRPSEL_GPT11_MASK (1 << 12)
110#define OMAP3430_GRPSEL_GPT10 (1 << 11) 110#define OMAP3430_GRPSEL_GPT10_MASK (1 << 11)
111#define OMAP3430_GRPSEL_MCBSP5 (1 << 10) 111#define OMAP3430_GRPSEL_MCBSP5_MASK (1 << 10)
112#define OMAP3430_GRPSEL_MCBSP1 (1 << 9) 112#define OMAP3430_GRPSEL_MCBSP1_MASK (1 << 9)
113#define OMAP3430_GRPSEL_HSOTGUSB (1 << 4) 113#define OMAP3430_GRPSEL_HSOTGUSB_MASK (1 << 4)
114#define OMAP3430_GRPSEL_D2D (1 << 3) 114#define OMAP3430_GRPSEL_D2D_MASK (1 << 3)
115 115
116/* 116/*
117 * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, 117 * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
@@ -119,49 +119,49 @@
119 */ 119 */
120#define OMAP3430_MEMONSTATE_SHIFT 16 120#define OMAP3430_MEMONSTATE_SHIFT 16
121#define OMAP3430_MEMONSTATE_MASK (0x3 << 16) 121#define OMAP3430_MEMONSTATE_MASK (0x3 << 16)
122#define OMAP3430_MEMRETSTATE (1 << 8) 122#define OMAP3430_MEMRETSTATE_MASK (1 << 8)
123 123
124/* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */ 124/* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
125#define OMAP3430_GRPSEL_GPIO6 (1 << 17) 125#define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17)
126#define OMAP3430_GRPSEL_GPIO5 (1 << 16) 126#define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16)
127#define OMAP3430_GRPSEL_GPIO4 (1 << 15) 127#define OMAP3430_GRPSEL_GPIO4_MASK (1 << 15)
128#define OMAP3430_GRPSEL_GPIO3 (1 << 14) 128#define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14)
129#define OMAP3430_GRPSEL_GPIO2 (1 << 13) 129#define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13)
130#define OMAP3430_GRPSEL_UART3 (1 << 11) 130#define OMAP3430_GRPSEL_UART3_MASK (1 << 11)
131#define OMAP3430_GRPSEL_GPT9 (1 << 10) 131#define OMAP3430_GRPSEL_GPT9_MASK (1 << 10)
132#define OMAP3430_GRPSEL_GPT8 (1 << 9) 132#define OMAP3430_GRPSEL_GPT8_MASK (1 << 9)
133#define OMAP3430_GRPSEL_GPT7 (1 << 8) 133#define OMAP3430_GRPSEL_GPT7_MASK (1 << 8)
134#define OMAP3430_GRPSEL_GPT6 (1 << 7) 134#define OMAP3430_GRPSEL_GPT6_MASK (1 << 7)
135#define OMAP3430_GRPSEL_GPT5 (1 << 6) 135#define OMAP3430_GRPSEL_GPT5_MASK (1 << 6)
136#define OMAP3430_GRPSEL_GPT4 (1 << 5) 136#define OMAP3430_GRPSEL_GPT4_MASK (1 << 5)
137#define OMAP3430_GRPSEL_GPT3 (1 << 4) 137#define OMAP3430_GRPSEL_GPT3_MASK (1 << 4)
138#define OMAP3430_GRPSEL_GPT2 (1 << 3) 138#define OMAP3430_GRPSEL_GPT2_MASK (1 << 3)
139#define OMAP3430_GRPSEL_MCBSP4 (1 << 2) 139#define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2)
140#define OMAP3430_GRPSEL_MCBSP3 (1 << 1) 140#define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1)
141#define OMAP3430_GRPSEL_MCBSP2 (1 << 0) 141#define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0)
142 142
143/* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */ 143/* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
144#define OMAP3430_GRPSEL_IO (1 << 8) 144#define OMAP3430_GRPSEL_IO_MASK (1 << 8)
145#define OMAP3430_GRPSEL_SR2 (1 << 7) 145#define OMAP3430_GRPSEL_SR2_MASK (1 << 7)
146#define OMAP3430_GRPSEL_SR1 (1 << 6) 146#define OMAP3430_GRPSEL_SR1_MASK (1 << 6)
147#define OMAP3430_GRPSEL_GPIO1 (1 << 3) 147#define OMAP3430_GRPSEL_GPIO1_MASK (1 << 3)
148#define OMAP3430_GRPSEL_GPT12 (1 << 1) 148#define OMAP3430_GRPSEL_GPT12_MASK (1 << 1)
149#define OMAP3430_GRPSEL_GPT1 (1 << 0) 149#define OMAP3430_GRPSEL_GPT1_MASK (1 << 0)
150 150
151/* Bits specific to each register */ 151/* Bits specific to each register */
152 152
153/* RM_RSTCTRL_IVA2 */ 153/* RM_RSTCTRL_IVA2 */
154#define OMAP3430_RST3_IVA2 (1 << 2) 154#define OMAP3430_RST3_IVA2_MASK (1 << 2)
155#define OMAP3430_RST2_IVA2 (1 << 1) 155#define OMAP3430_RST2_IVA2_MASK (1 << 1)
156#define OMAP3430_RST1_IVA2 (1 << 0) 156#define OMAP3430_RST1_IVA2_MASK (1 << 0)
157 157
158/* RM_RSTST_IVA2 specific bits */ 158/* RM_RSTST_IVA2 specific bits */
159#define OMAP3430_EMULATION_VSEQ_RST (1 << 13) 159#define OMAP3430_EMULATION_VSEQ_RST_MASK (1 << 13)
160#define OMAP3430_EMULATION_VHWA_RST (1 << 12) 160#define OMAP3430_EMULATION_VHWA_RST_MASK (1 << 12)
161#define OMAP3430_EMULATION_IVA2_RST (1 << 11) 161#define OMAP3430_EMULATION_IVA2_RST_MASK (1 << 11)
162#define OMAP3430_IVA2_SW_RST3 (1 << 10) 162#define OMAP3430_IVA2_SW_RST3_MASK (1 << 10)
163#define OMAP3430_IVA2_SW_RST2 (1 << 9) 163#define OMAP3430_IVA2_SW_RST2_MASK (1 << 9)
164#define OMAP3430_IVA2_SW_RST1 (1 << 8) 164#define OMAP3430_IVA2_SW_RST1_MASK (1 << 8)
165 165
166/* PM_WKDEP_IVA2 specific bits */ 166/* PM_WKDEP_IVA2 specific bits */
167 167
@@ -174,10 +174,10 @@
174#define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18) 174#define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18)
175#define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16 175#define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16
176#define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16) 176#define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16)
177#define OMAP3430_L2FLATMEMRETSTATE (1 << 11) 177#define OMAP3430_L2FLATMEMRETSTATE_MASK (1 << 11)
178#define OMAP3430_SHAREDL2CACHEFLATRETSTATE (1 << 10) 178#define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK (1 << 10)
179#define OMAP3430_L1FLATMEMRETSTATE (1 << 9) 179#define OMAP3430_L1FLATMEMRETSTATE_MASK (1 << 9)
180#define OMAP3430_SHAREDL1CACHEFLATRETSTATE (1 << 8) 180#define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK (1 << 8)
181 181
182/* PM_PWSTST_IVA2 specific bits */ 182/* PM_PWSTST_IVA2 specific bits */
183#define OMAP3430_L2FLATMEMSTATEST_SHIFT 10 183#define OMAP3430_L2FLATMEMSTATEST_SHIFT 10
@@ -200,12 +200,12 @@
200#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4) 200#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4)
201 201
202/* PRM_IRQSTATUS_IVA2 specific bits */ 202/* PRM_IRQSTATUS_IVA2 specific bits */
203#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST (1 << 2) 203#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST_MASK (1 << 2)
204#define OMAP3430_FORCEWKUP_ST (1 << 1) 204#define OMAP3430_FORCEWKUP_ST_MASK (1 << 1)
205 205
206/* PRM_IRQENABLE_IVA2 specific bits */ 206/* PRM_IRQENABLE_IVA2 specific bits */
207#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN (1 << 2) 207#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN_MASK (1 << 2)
208#define OMAP3430_FORCEWKUP_EN (1 << 1) 208#define OMAP3430_FORCEWKUP_EN_MASK (1 << 1)
209 209
210/* PRM_REVISION specific bits */ 210/* PRM_REVISION specific bits */
211 211
@@ -213,70 +213,70 @@
213 213
214/* PRM_IRQSTATUS_MPU specific bits */ 214/* PRM_IRQSTATUS_MPU specific bits */
215#define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25 215#define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25
216#define OMAP3430ES2_SND_PERIPH_DPLL_ST (1 << 25) 216#define OMAP3430ES2_SND_PERIPH_DPLL_ST_MASK (1 << 25)
217#define OMAP3430_VC_TIMEOUTERR_ST (1 << 24) 217#define OMAP3430_VC_TIMEOUTERR_ST_MASK (1 << 24)
218#define OMAP3430_VC_RAERR_ST (1 << 23) 218#define OMAP3430_VC_RAERR_ST_MASK (1 << 23)
219#define OMAP3430_VC_SAERR_ST (1 << 22) 219#define OMAP3430_VC_SAERR_ST_MASK (1 << 22)
220#define OMAP3430_VP2_TRANXDONE_ST (1 << 21) 220#define OMAP3430_VP2_TRANXDONE_ST_MASK (1 << 21)
221#define OMAP3430_VP2_EQVALUE_ST (1 << 20) 221#define OMAP3430_VP2_EQVALUE_ST_MASK (1 << 20)
222#define OMAP3430_VP2_NOSMPSACK_ST (1 << 19) 222#define OMAP3430_VP2_NOSMPSACK_ST_MASK (1 << 19)
223#define OMAP3430_VP2_MAXVDD_ST (1 << 18) 223#define OMAP3430_VP2_MAXVDD_ST_MASK (1 << 18)
224#define OMAP3430_VP2_MINVDD_ST (1 << 17) 224#define OMAP3430_VP2_MINVDD_ST_MASK (1 << 17)
225#define OMAP3430_VP2_OPPCHANGEDONE_ST (1 << 16) 225#define OMAP3430_VP2_OPPCHANGEDONE_ST_MASK (1 << 16)
226#define OMAP3430_VP1_TRANXDONE_ST (1 << 15) 226#define OMAP3430_VP1_TRANXDONE_ST_MASK (1 << 15)
227#define OMAP3430_VP1_EQVALUE_ST (1 << 14) 227#define OMAP3430_VP1_EQVALUE_ST_MASK (1 << 14)
228#define OMAP3430_VP1_NOSMPSACK_ST (1 << 13) 228#define OMAP3430_VP1_NOSMPSACK_ST_MASK (1 << 13)
229#define OMAP3430_VP1_MAXVDD_ST (1 << 12) 229#define OMAP3430_VP1_MAXVDD_ST_MASK (1 << 12)
230#define OMAP3430_VP1_MINVDD_ST (1 << 11) 230#define OMAP3430_VP1_MINVDD_ST_MASK (1 << 11)
231#define OMAP3430_VP1_OPPCHANGEDONE_ST (1 << 10) 231#define OMAP3430_VP1_OPPCHANGEDONE_ST_MASK (1 << 10)
232#define OMAP3430_IO_ST (1 << 9) 232#define OMAP3430_IO_ST_MASK (1 << 9)
233#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST (1 << 8) 233#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_MASK (1 << 8)
234#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8 234#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8
235#define OMAP3430_MPU_DPLL_ST (1 << 7) 235#define OMAP3430_MPU_DPLL_ST_MASK (1 << 7)
236#define OMAP3430_MPU_DPLL_ST_SHIFT 7 236#define OMAP3430_MPU_DPLL_ST_SHIFT 7
237#define OMAP3430_PERIPH_DPLL_ST (1 << 6) 237#define OMAP3430_PERIPH_DPLL_ST_MASK (1 << 6)
238#define OMAP3430_PERIPH_DPLL_ST_SHIFT 6 238#define OMAP3430_PERIPH_DPLL_ST_SHIFT 6
239#define OMAP3430_CORE_DPLL_ST (1 << 5) 239#define OMAP3430_CORE_DPLL_ST_MASK (1 << 5)
240#define OMAP3430_CORE_DPLL_ST_SHIFT 5 240#define OMAP3430_CORE_DPLL_ST_SHIFT 5
241#define OMAP3430_TRANSITION_ST (1 << 4) 241#define OMAP3430_TRANSITION_ST_MASK (1 << 4)
242#define OMAP3430_EVGENOFF_ST (1 << 3) 242#define OMAP3430_EVGENOFF_ST_MASK (1 << 3)
243#define OMAP3430_EVGENON_ST (1 << 2) 243#define OMAP3430_EVGENON_ST_MASK (1 << 2)
244#define OMAP3430_FS_USB_WKUP_ST (1 << 1) 244#define OMAP3430_FS_USB_WKUP_ST_MASK (1 << 1)
245 245
246/* PRM_IRQENABLE_MPU specific bits */ 246/* PRM_IRQENABLE_MPU specific bits */
247#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25 247#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25
248#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN (1 << 25) 248#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_MASK (1 << 25)
249#define OMAP3430_VC_TIMEOUTERR_EN (1 << 24) 249#define OMAP3430_VC_TIMEOUTERR_EN_MASK (1 << 24)
250#define OMAP3430_VC_RAERR_EN (1 << 23) 250#define OMAP3430_VC_RAERR_EN_MASK (1 << 23)
251#define OMAP3430_VC_SAERR_EN (1 << 22) 251#define OMAP3430_VC_SAERR_EN_MASK (1 << 22)
252#define OMAP3430_VP2_TRANXDONE_EN (1 << 21) 252#define OMAP3430_VP2_TRANXDONE_EN_MASK (1 << 21)
253#define OMAP3430_VP2_EQVALUE_EN (1 << 20) 253#define OMAP3430_VP2_EQVALUE_EN_MASK (1 << 20)
254#define OMAP3430_VP2_NOSMPSACK_EN (1 << 19) 254#define OMAP3430_VP2_NOSMPSACK_EN_MASK (1 << 19)
255#define OMAP3430_VP2_MAXVDD_EN (1 << 18) 255#define OMAP3430_VP2_MAXVDD_EN_MASK (1 << 18)
256#define OMAP3430_VP2_MINVDD_EN (1 << 17) 256#define OMAP3430_VP2_MINVDD_EN_MASK (1 << 17)
257#define OMAP3430_VP2_OPPCHANGEDONE_EN (1 << 16) 257#define OMAP3430_VP2_OPPCHANGEDONE_EN_MASK (1 << 16)
258#define OMAP3430_VP1_TRANXDONE_EN (1 << 15) 258#define OMAP3430_VP1_TRANXDONE_EN_MASK (1 << 15)
259#define OMAP3430_VP1_EQVALUE_EN (1 << 14) 259#define OMAP3430_VP1_EQVALUE_EN_MASK (1 << 14)
260#define OMAP3430_VP1_NOSMPSACK_EN (1 << 13) 260#define OMAP3430_VP1_NOSMPSACK_EN_MASK (1 << 13)
261#define OMAP3430_VP1_MAXVDD_EN (1 << 12) 261#define OMAP3430_VP1_MAXVDD_EN_MASK (1 << 12)
262#define OMAP3430_VP1_MINVDD_EN (1 << 11) 262#define OMAP3430_VP1_MINVDD_EN_MASK (1 << 11)
263#define OMAP3430_VP1_OPPCHANGEDONE_EN (1 << 10) 263#define OMAP3430_VP1_OPPCHANGEDONE_EN_MASK (1 << 10)
264#define OMAP3430_IO_EN (1 << 9) 264#define OMAP3430_IO_EN_MASK (1 << 9)
265#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN (1 << 8) 265#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_MASK (1 << 8)
266#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8 266#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8
267#define OMAP3430_MPU_DPLL_RECAL_EN (1 << 7) 267#define OMAP3430_MPU_DPLL_RECAL_EN_MASK (1 << 7)
268#define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7 268#define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7
269#define OMAP3430_PERIPH_DPLL_RECAL_EN (1 << 6) 269#define OMAP3430_PERIPH_DPLL_RECAL_EN_MASK (1 << 6)
270#define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6 270#define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6
271#define OMAP3430_CORE_DPLL_RECAL_EN (1 << 5) 271#define OMAP3430_CORE_DPLL_RECAL_EN_MASK (1 << 5)
272#define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5 272#define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5
273#define OMAP3430_TRANSITION_EN (1 << 4) 273#define OMAP3430_TRANSITION_EN_MASK (1 << 4)
274#define OMAP3430_EVGENOFF_EN (1 << 3) 274#define OMAP3430_EVGENOFF_EN_MASK (1 << 3)
275#define OMAP3430_EVGENON_EN (1 << 2) 275#define OMAP3430_EVGENON_EN_MASK (1 << 2)
276#define OMAP3430_FS_USB_WKUP_EN (1 << 1) 276#define OMAP3430_FS_USB_WKUP_EN_MASK (1 << 1)
277 277
278/* RM_RSTST_MPU specific bits */ 278/* RM_RSTST_MPU specific bits */
279#define OMAP3430_EMULATION_MPU_RST (1 << 11) 279#define OMAP3430_EMULATION_MPU_RST_MASK (1 << 11)
280 280
281/* PM_WKDEP_MPU specific bits */ 281/* PM_WKDEP_MPU specific bits */
282#define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5 282#define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5
@@ -289,7 +289,7 @@
289#define OMAP3430_OFFLOADMODE_MASK (0x3 << 3) 289#define OMAP3430_OFFLOADMODE_MASK (0x3 << 3)
290#define OMAP3430_ONLOADMODE_SHIFT 1 290#define OMAP3430_ONLOADMODE_SHIFT 1
291#define OMAP3430_ONLOADMODE_MASK (0x3 << 1) 291#define OMAP3430_ONLOADMODE_MASK (0x3 << 1)
292#define OMAP3430_ENABLE (1 << 0) 292#define OMAP3430_ENABLE_MASK (1 << 0)
293 293
294/* PM_EVGENONTIM_MPU */ 294/* PM_EVGENONTIM_MPU */
295#define OMAP3430_ONTIMEVAL_SHIFT 0 295#define OMAP3430_ONTIMEVAL_SHIFT 0
@@ -302,32 +302,32 @@
302/* PM_PWSTCTRL_MPU specific bits */ 302/* PM_PWSTCTRL_MPU specific bits */
303#define OMAP3430_L2CACHEONSTATE_SHIFT 16 303#define OMAP3430_L2CACHEONSTATE_SHIFT 16
304#define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16) 304#define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16)
305#define OMAP3430_L2CACHERETSTATE (1 << 8) 305#define OMAP3430_L2CACHERETSTATE_MASK (1 << 8)
306#define OMAP3430_LOGICL1CACHERETSTATE (1 << 2) 306#define OMAP3430_LOGICL1CACHERETSTATE_MASK (1 << 2)
307 307
308/* PM_PWSTST_MPU specific bits */ 308/* PM_PWSTST_MPU specific bits */
309#define OMAP3430_L2CACHESTATEST_SHIFT 6 309#define OMAP3430_L2CACHESTATEST_SHIFT 6
310#define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6) 310#define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6)
311#define OMAP3430_LOGICL1CACHESTATEST (1 << 2) 311#define OMAP3430_LOGICL1CACHESTATEST_MASK (1 << 2)
312 312
313/* PM_PREPWSTST_MPU specific bits */ 313/* PM_PREPWSTST_MPU specific bits */
314#define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6 314#define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6
315#define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6) 315#define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6)
316#define OMAP3430_LASTLOGICL1CACHESTATEENTERED (1 << 2) 316#define OMAP3430_LASTLOGICL1CACHESTATEENTERED_MASK (1 << 2)
317 317
318/* RM_RSTCTRL_CORE */ 318/* RM_RSTCTRL_CORE */
319#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON (1 << 1) 319#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK (1 << 1)
320#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST (1 << 0) 320#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK (1 << 0)
321 321
322/* RM_RSTST_CORE specific bits */ 322/* RM_RSTST_CORE specific bits */
323#define OMAP3430_MODEM_SECURITY_VIOL_RST (1 << 10) 323#define OMAP3430_MODEM_SECURITY_VIOL_RST_MASK (1 << 10)
324#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON (1 << 9) 324#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON_MASK (1 << 9)
325#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST (1 << 8) 325#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST_MASK (1 << 8)
326 326
327/* PM_WKEN1_CORE specific bits */ 327/* PM_WKEN1_CORE specific bits */
328 328
329/* PM_MPUGRPSEL1_CORE specific bits */ 329/* PM_MPUGRPSEL1_CORE specific bits */
330#define OMAP3430_GRPSEL_FSHOSTUSB (1 << 5) 330#define OMAP3430_GRPSEL_FSHOSTUSB_MASK (1 << 5)
331 331
332/* PM_IVA2GRPSEL1_CORE specific bits */ 332/* PM_IVA2GRPSEL1_CORE specific bits */
333 333
@@ -338,8 +338,8 @@
338#define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18) 338#define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18)
339#define OMAP3430_MEM1ONSTATE_SHIFT 16 339#define OMAP3430_MEM1ONSTATE_SHIFT 16
340#define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16) 340#define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16)
341#define OMAP3430_MEM2RETSTATE (1 << 9) 341#define OMAP3430_MEM2RETSTATE_MASK (1 << 9)
342#define OMAP3430_MEM1RETSTATE (1 << 8) 342#define OMAP3430_MEM1RETSTATE_MASK (1 << 8)
343 343
344/* PM_PWSTST_CORE specific bits */ 344/* PM_PWSTST_CORE specific bits */
345#define OMAP3430_MEM2STATEST_SHIFT 6 345#define OMAP3430_MEM2STATEST_SHIFT 6
@@ -356,7 +356,7 @@
356/* RM_RSTST_GFX specific bits */ 356/* RM_RSTST_GFX specific bits */
357 357
358/* PM_WKDEP_GFX specific bits */ 358/* PM_WKDEP_GFX specific bits */
359#define OMAP3430_PM_WKDEP_GFX_EN_IVA2 (1 << 2) 359#define OMAP3430_PM_WKDEP_GFX_EN_IVA2_MASK (1 << 2)
360 360
361/* PM_PWSTCTRL_GFX specific bits */ 361/* PM_PWSTCTRL_GFX specific bits */
362 362
@@ -365,33 +365,33 @@
365/* PM_PREPWSTST_GFX specific bits */ 365/* PM_PREPWSTST_GFX specific bits */
366 366
367/* PM_WKEN_WKUP specific bits */ 367/* PM_WKEN_WKUP specific bits */
368#define OMAP3430_EN_IO_CHAIN (1 << 16) 368#define OMAP3430_EN_IO_CHAIN_MASK (1 << 16)
369#define OMAP3430_EN_IO (1 << 8) 369#define OMAP3430_EN_IO_MASK (1 << 8)
370#define OMAP3430_EN_GPIO1 (1 << 3) 370#define OMAP3430_EN_GPIO1_MASK (1 << 3)
371 371
372/* PM_MPUGRPSEL_WKUP specific bits */ 372/* PM_MPUGRPSEL_WKUP specific bits */
373 373
374/* PM_IVA2GRPSEL_WKUP specific bits */ 374/* PM_IVA2GRPSEL_WKUP specific bits */
375 375
376/* PM_WKST_WKUP specific bits */ 376/* PM_WKST_WKUP specific bits */
377#define OMAP3430_ST_IO_CHAIN (1 << 16) 377#define OMAP3430_ST_IO_CHAIN_MASK (1 << 16)
378#define OMAP3430_ST_IO (1 << 8) 378#define OMAP3430_ST_IO_MASK (1 << 8)
379 379
380/* PRM_CLKSEL */ 380/* PRM_CLKSEL */
381#define OMAP3430_SYS_CLKIN_SEL_SHIFT 0 381#define OMAP3430_SYS_CLKIN_SEL_SHIFT 0
382#define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0) 382#define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0)
383 383
384/* PRM_CLKOUT_CTRL */ 384/* PRM_CLKOUT_CTRL */
385#define OMAP3430_CLKOUT_EN (1 << 7) 385#define OMAP3430_CLKOUT_EN_MASK (1 << 7)
386#define OMAP3430_CLKOUT_EN_SHIFT 7 386#define OMAP3430_CLKOUT_EN_SHIFT 7
387 387
388/* RM_RSTST_DSS specific bits */ 388/* RM_RSTST_DSS specific bits */
389 389
390/* PM_WKEN_DSS */ 390/* PM_WKEN_DSS */
391#define OMAP3430_PM_WKEN_DSS_EN_DSS (1 << 0) 391#define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK (1 << 0)
392 392
393/* PM_WKDEP_DSS specific bits */ 393/* PM_WKDEP_DSS specific bits */
394#define OMAP3430_PM_WKDEP_DSS_EN_IVA2 (1 << 2) 394#define OMAP3430_PM_WKDEP_DSS_EN_IVA2_MASK (1 << 2)
395 395
396/* PM_PWSTCTRL_DSS specific bits */ 396/* PM_PWSTCTRL_DSS specific bits */
397 397
@@ -402,7 +402,7 @@
402/* RM_RSTST_CAM specific bits */ 402/* RM_RSTST_CAM specific bits */
403 403
404/* PM_WKDEP_CAM specific bits */ 404/* PM_WKDEP_CAM specific bits */
405#define OMAP3430_PM_WKDEP_CAM_EN_IVA2 (1 << 2) 405#define OMAP3430_PM_WKDEP_CAM_EN_IVA2_MASK (1 << 2)
406 406
407/* PM_PWSTCTRL_CAM specific bits */ 407/* PM_PWSTCTRL_CAM specific bits */
408 408
@@ -424,7 +424,7 @@
424/* PM_WKST_PER specific bits */ 424/* PM_WKST_PER specific bits */
425 425
426/* PM_WKDEP_PER specific bits */ 426/* PM_WKDEP_PER specific bits */
427#define OMAP3430_PM_WKDEP_PER_EN_IVA2 (1 << 2) 427#define OMAP3430_PM_WKDEP_PER_EN_IVA2_MASK (1 << 2)
428 428
429/* PM_PWSTCTRL_PER specific bits */ 429/* PM_PWSTCTRL_PER specific bits */
430 430
@@ -467,26 +467,26 @@
467/* PRM_VC_CMD_VAL_1 specific bits */ 467/* PRM_VC_CMD_VAL_1 specific bits */
468 468
469/* PRM_VC_CH_CONF */ 469/* PRM_VC_CH_CONF */
470#define OMAP3430_CMD1 (1 << 20) 470#define OMAP3430_CMD1_MASK (1 << 20)
471#define OMAP3430_RACEN1 (1 << 19) 471#define OMAP3430_RACEN1_MASK (1 << 19)
472#define OMAP3430_RAC1 (1 << 18) 472#define OMAP3430_RAC1_MASK (1 << 18)
473#define OMAP3430_RAV1 (1 << 17) 473#define OMAP3430_RAV1_MASK (1 << 17)
474#define OMAP3430_PRM_VC_CH_CONF_SA1 (1 << 16) 474#define OMAP3430_PRM_VC_CH_CONF_SA1_MASK (1 << 16)
475#define OMAP3430_CMD0 (1 << 4) 475#define OMAP3430_CMD0_MASK (1 << 4)
476#define OMAP3430_RACEN0 (1 << 3) 476#define OMAP3430_RACEN0_MASK (1 << 3)
477#define OMAP3430_RAC0 (1 << 2) 477#define OMAP3430_RAC0_MASK (1 << 2)
478#define OMAP3430_RAV0 (1 << 1) 478#define OMAP3430_RAV0_MASK (1 << 1)
479#define OMAP3430_PRM_VC_CH_CONF_SA0 (1 << 0) 479#define OMAP3430_PRM_VC_CH_CONF_SA0_MASK (1 << 0)
480 480
481/* PRM_VC_I2C_CFG */ 481/* PRM_VC_I2C_CFG */
482#define OMAP3430_HSMASTER (1 << 5) 482#define OMAP3430_HSMASTER_MASK (1 << 5)
483#define OMAP3430_SREN (1 << 4) 483#define OMAP3430_SREN_MASK (1 << 4)
484#define OMAP3430_HSEN (1 << 3) 484#define OMAP3430_HSEN_MASK (1 << 3)
485#define OMAP3430_MCODE_SHIFT 0 485#define OMAP3430_MCODE_SHIFT 0
486#define OMAP3430_MCODE_MASK (0x7 << 0) 486#define OMAP3430_MCODE_MASK (0x7 << 0)
487 487
488/* PRM_VC_BYPASS_VAL */ 488/* PRM_VC_BYPASS_VAL */
489#define OMAP3430_VALID (1 << 24) 489#define OMAP3430_VALID_MASK (1 << 24)
490#define OMAP3430_DATA_SHIFT 16 490#define OMAP3430_DATA_SHIFT 16
491#define OMAP3430_DATA_MASK (0xff << 16) 491#define OMAP3430_DATA_MASK (0xff << 16)
492#define OMAP3430_REGADDR_SHIFT 8 492#define OMAP3430_REGADDR_SHIFT 8
@@ -495,8 +495,8 @@
495#define OMAP3430_SLAVEADDR_MASK (0x7f << 0) 495#define OMAP3430_SLAVEADDR_MASK (0x7f << 0)
496 496
497/* PRM_RSTCTRL */ 497/* PRM_RSTCTRL */
498#define OMAP3430_RST_DPLL3 (1 << 2) 498#define OMAP3430_RST_DPLL3_MASK (1 << 2)
499#define OMAP3430_RST_GS (1 << 1) 499#define OMAP3430_RST_GS_MASK (1 << 1)
500 500
501/* PRM_RSTTIME */ 501/* PRM_RSTTIME */
502#define OMAP3430_RSTTIME2_SHIFT 8 502#define OMAP3430_RSTTIME2_SHIFT 8
@@ -505,23 +505,23 @@
505#define OMAP3430_RSTTIME1_MASK (0xff << 0) 505#define OMAP3430_RSTTIME1_MASK (0xff << 0)
506 506
507/* PRM_RSTST */ 507/* PRM_RSTST */
508#define OMAP3430_ICECRUSHER_RST (1 << 10) 508#define OMAP3430_ICECRUSHER_RST_MASK (1 << 10)
509#define OMAP3430_ICEPICK_RST (1 << 9) 509#define OMAP3430_ICEPICK_RST_MASK (1 << 9)
510#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST (1 << 8) 510#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK (1 << 8)
511#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST (1 << 7) 511#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK (1 << 7)
512#define OMAP3430_EXTERNAL_WARM_RST (1 << 6) 512#define OMAP3430_EXTERNAL_WARM_RST_MASK (1 << 6)
513#define OMAP3430_SECURE_WD_RST (1 << 5) 513#define OMAP3430_SECURE_WD_RST_MASK (1 << 5)
514#define OMAP3430_MPU_WD_RST (1 << 4) 514#define OMAP3430_MPU_WD_RST_MASK (1 << 4)
515#define OMAP3430_SECURITY_VIOL_RST (1 << 3) 515#define OMAP3430_SECURITY_VIOL_RST_MASK (1 << 3)
516#define OMAP3430_GLOBAL_SW_RST (1 << 1) 516#define OMAP3430_GLOBAL_SW_RST_MASK (1 << 1)
517#define OMAP3430_GLOBAL_COLD_RST (1 << 0) 517#define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0)
518 518
519/* PRM_VOLTCTRL */ 519/* PRM_VOLTCTRL */
520#define OMAP3430_SEL_VMODE (1 << 4) 520#define OMAP3430_SEL_VMODE_MASK (1 << 4)
521#define OMAP3430_SEL_OFF (1 << 3) 521#define OMAP3430_SEL_OFF_MASK (1 << 3)
522#define OMAP3430_AUTO_OFF (1 << 2) 522#define OMAP3430_AUTO_OFF_MASK (1 << 2)
523#define OMAP3430_AUTO_RET (1 << 1) 523#define OMAP3430_AUTO_RET_MASK (1 << 1)
524#define OMAP3430_AUTO_SLEEP (1 << 0) 524#define OMAP3430_AUTO_SLEEP_MASK (1 << 0)
525 525
526/* PRM_SRAM_PCHARGE */ 526/* PRM_SRAM_PCHARGE */
527#define OMAP3430_PCHARGE_TIME_SHIFT 0 527#define OMAP3430_PCHARGE_TIME_SHIFT 0
@@ -550,10 +550,10 @@
550#define OMAP3430_SETUP_TIME_MASK (0xffff << 0) 550#define OMAP3430_SETUP_TIME_MASK (0xffff << 0)
551 551
552/* PRM_POLCTRL */ 552/* PRM_POLCTRL */
553#define OMAP3430_OFFMODE_POL (1 << 3) 553#define OMAP3430_OFFMODE_POL_MASK (1 << 3)
554#define OMAP3430_CLKOUT_POL (1 << 2) 554#define OMAP3430_CLKOUT_POL_MASK (1 << 2)
555#define OMAP3430_CLKREQ_POL (1 << 1) 555#define OMAP3430_CLKREQ_POL_MASK (1 << 1)
556#define OMAP3430_EXTVOL_POL (1 << 0) 556#define OMAP3430_EXTVOL_POL_MASK (1 << 0)
557 557
558/* PRM_VOLTSETUP2 */ 558/* PRM_VOLTSETUP2 */
559#define OMAP3430_OFFMODESETUPTIME_SHIFT 0 559#define OMAP3430_OFFMODESETUPTIME_SHIFT 0
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 5fba2aa8932c..588873b9303a 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -24,8 +24,8 @@
24 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) 24 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
25#define OMAP44XX_PRM_REGADDR(module, reg) \ 25#define OMAP44XX_PRM_REGADDR(module, reg) \
26 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg)) 26 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
27#define OMAP44XX_CHIRONSS_REGADDR(module, reg) \ 27#define OMAP44XX_PRCM_MPU_REGADDR(module, reg) \
28 OMAP2_L4_IO_ADDRESS(OMAP4430_CHIRONSS_BASE + (module) + (reg)) 28 OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (module) + (reg))
29 29
30#include "prm44xx.h" 30#include "prm44xx.h"
31 31
@@ -284,7 +284,7 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
284#define OMAP_OFFLOADMODE_MASK (0x3 << 3) 284#define OMAP_OFFLOADMODE_MASK (0x3 << 3)
285#define OMAP_ONLOADMODE_SHIFT 1 285#define OMAP_ONLOADMODE_SHIFT 1
286#define OMAP_ONLOADMODE_MASK (0x3 << 1) 286#define OMAP_ONLOADMODE_MASK (0x3 << 1)
287#define OMAP_ENABLE (1 << 0) 287#define OMAP_ENABLE_MASK (1 << 0)
288 288
289/* PRM_RSTTIME */ 289/* PRM_RSTTIME */
290/* Named RM_RSTTIME_WKUP on the 24xx */ 290/* Named RM_RSTTIME_WKUP on the 24xx */
@@ -296,8 +296,8 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
296/* PRM_RSTCTRL */ 296/* PRM_RSTCTRL */
297/* Named RM_RSTCTRL_WKUP on the 24xx */ 297/* Named RM_RSTCTRL_WKUP on the 24xx */
298/* 2420 calls RST_DPLL3 'RST_DPLL' */ 298/* 2420 calls RST_DPLL3 'RST_DPLL' */
299#define OMAP_RST_DPLL3 (1 << 2) 299#define OMAP_RST_DPLL3_MASK (1 << 2)
300#define OMAP_RST_GS (1 << 1) 300#define OMAP_RST_GS_MASK (1 << 1)
301 301
302 302
303/* 303/*
@@ -316,7 +316,7 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
316 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, 316 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
317 * PM_PWSTST_NEON 317 * PM_PWSTST_NEON
318 */ 318 */
319#define OMAP_INTRANSITION (1 << 20) 319#define OMAP_INTRANSITION_MASK (1 << 20)
320 320
321 321
322/* 322/*
@@ -338,7 +338,7 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
338 * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS, 338 * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
339 * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON 339 * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
340 */ 340 */
341#define OMAP_COREDOMAINWKUP_RST (1 << 3) 341#define OMAP_COREDOMAINWKUP_RST_MASK (1 << 3)
342 342
343/* 343/*
344 * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP 344 * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
@@ -347,7 +347,7 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
347 * 347 *
348 * 3430: RM_RSTST_CORE, RM_RSTST_EMU 348 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
349 */ 349 */
350#define OMAP_DOMAINWKUP_RST (1 << 2) 350#define OMAP_DOMAINWKUP_RST_MASK (1 << 2)
351 351
352/* 352/*
353 * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP 353 * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
@@ -357,8 +357,8 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
357 * 357 *
358 * 3430: RM_RSTST_CORE, RM_RSTST_EMU 358 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
359 */ 359 */
360#define OMAP_GLOBALWARM_RST (1 << 1) 360#define OMAP_GLOBALWARM_RST_MASK (1 << 1)
361#define OMAP_GLOBALCOLD_RST (1 << 0) 361#define OMAP_GLOBALCOLD_RST_MASK (1 << 0)
362 362
363/* 363/*
364 * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP 364 * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
@@ -382,7 +382,7 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
382 * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, 382 * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
383 * PM_PWSTCTRL_NEON 383 * PM_PWSTCTRL_NEON
384 */ 384 */
385#define OMAP_LOGICRETSTATE (1 << 2) 385#define OMAP_LOGICRETSTATE_MASK (1 << 2)
386 386
387/* 387/*
388 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, 388 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index adb2558bb121..fe8ef26431e5 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -1,8 +1,8 @@
1/* 1/*
2 * OMAP44xx PRM instance offset macros 2 * OMAP44xx PRM instance offset macros
3 * 3 *
4 * Copyright (C) 2009 Texas Instruments, Inc. 4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009 Nokia Corporation 5 * Copyright (C) 2009-2010 Nokia Corporation
6 * 6 *
7 * Paul Walmsley (paul@pwsan.com) 7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com) 8 * Rajendra Nayak (rnayak@ti.com)
@@ -25,387 +25,726 @@
25 25
26/* PRM */ 26/* PRM */
27 27
28
29/* PRM.OCP_SOCKET_PRM register offsets */ 28/* PRM.OCP_SOCKET_PRM register offsets */
29#define OMAP4_REVISION_PRM_OFFSET 0x0000
30#define OMAP4430_REVISION_PRM OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0000) 30#define OMAP4430_REVISION_PRM OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0000)
31#define OMAP4_PRM_IRQSTATUS_MPU_OFFSET 0x0010
31#define OMAP4430_PRM_IRQSTATUS_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0010) 32#define OMAP4430_PRM_IRQSTATUS_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0010)
33#define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014
32#define OMAP4430_PRM_IRQSTATUS_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0014) 34#define OMAP4430_PRM_IRQSTATUS_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0014)
35#define OMAP4_PRM_IRQENABLE_MPU_OFFSET 0x0018
33#define OMAP4430_PRM_IRQENABLE_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0018) 36#define OMAP4430_PRM_IRQENABLE_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0018)
37#define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET 0x001c
34#define OMAP4430_PRM_IRQENABLE_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x001c) 38#define OMAP4430_PRM_IRQENABLE_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x001c)
39#define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET 0x0020
35#define OMAP4430_PRM_IRQSTATUS_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0020) 40#define OMAP4430_PRM_IRQSTATUS_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0020)
41#define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET 0x0028
36#define OMAP4430_PRM_IRQENABLE_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0028) 42#define OMAP4430_PRM_IRQENABLE_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0028)
43#define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET 0x0030
37#define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030) 44#define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030)
45#define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038
38#define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038) 46#define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038)
47#define OMAP4_PRM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040
39#define OMAP4430_PRM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040) 48#define OMAP4430_PRM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040)
40 49
41/* PRM.CKGEN_PRM register offsets */ 50/* PRM.CKGEN_PRM register offsets */
51#define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000
42#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000) 52#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000)
53#define OMAP4_CM_DPLL_SYS_REF_CLKSEL_OFFSET 0x0004
43#define OMAP4430_CM_DPLL_SYS_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0004) 54#define OMAP4430_CM_DPLL_SYS_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0004)
55#define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008
44#define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008) 56#define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008)
57#define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c
45#define OMAP4430_CM_ABE_PLL_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x000c) 58#define OMAP4430_CM_ABE_PLL_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x000c)
59#define OMAP4_CM_SYS_CLKSEL_OFFSET 0x0010
46#define OMAP4430_CM_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0010) 60#define OMAP4430_CM_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0010)
47 61
48/* PRM.MPU_PRM register offsets */ 62/* PRM.MPU_PRM register offsets */
63#define OMAP4_PM_MPU_PWRSTCTRL_OFFSET 0x0000
49#define OMAP4430_PM_MPU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0000) 64#define OMAP4430_PM_MPU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0000)
65#define OMAP4_PM_MPU_PWRSTST_OFFSET 0x0004
50#define OMAP4430_PM_MPU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0004) 66#define OMAP4430_PM_MPU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0004)
67#define OMAP4_RM_MPU_RSTST_OFFSET 0x0014
51#define OMAP4430_RM_MPU_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0014) 68#define OMAP4430_RM_MPU_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0014)
69#define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET 0x0024
52#define OMAP4430_RM_MPU_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0024) 70#define OMAP4430_RM_MPU_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0024)
53 71
54/* PRM.TESLA_PRM register offsets */ 72/* PRM.TESLA_PRM register offsets */
73#define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET 0x0000
55#define OMAP4430_PM_TESLA_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0000) 74#define OMAP4430_PM_TESLA_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0000)
75#define OMAP4_PM_TESLA_PWRSTST_OFFSET 0x0004
56#define OMAP4430_PM_TESLA_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0004) 76#define OMAP4430_PM_TESLA_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0004)
77#define OMAP4_RM_TESLA_RSTCTRL_OFFSET 0x0010
57#define OMAP4430_RM_TESLA_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0010) 78#define OMAP4430_RM_TESLA_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0010)
79#define OMAP4_RM_TESLA_RSTST_OFFSET 0x0014
58#define OMAP4430_RM_TESLA_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0014) 80#define OMAP4430_RM_TESLA_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0014)
81#define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET 0x0024
59#define OMAP4430_RM_TESLA_TESLA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0024) 82#define OMAP4430_RM_TESLA_TESLA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0024)
60 83
61/* PRM.ABE_PRM register offsets */ 84/* PRM.ABE_PRM register offsets */
85#define OMAP4_PM_ABE_PWRSTCTRL_OFFSET 0x0000
62#define OMAP4430_PM_ABE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0000) 86#define OMAP4430_PM_ABE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0000)
87#define OMAP4_PM_ABE_PWRSTST_OFFSET 0x0004
63#define OMAP4430_PM_ABE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0004) 88#define OMAP4430_PM_ABE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0004)
89#define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET 0x002c
64#define OMAP4430_RM_ABE_AESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x002c) 90#define OMAP4430_RM_ABE_AESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x002c)
91#define OMAP4_PM_ABE_PDM_WKDEP_OFFSET 0x0030
65#define OMAP4430_PM_ABE_PDM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0030) 92#define OMAP4430_PM_ABE_PDM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0030)
93#define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET 0x0034
66#define OMAP4430_RM_ABE_PDM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0034) 94#define OMAP4430_RM_ABE_PDM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0034)
95#define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET 0x0038
67#define OMAP4430_PM_ABE_DMIC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0038) 96#define OMAP4430_PM_ABE_DMIC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0038)
97#define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c
68#define OMAP4430_RM_ABE_DMIC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x003c) 98#define OMAP4430_RM_ABE_DMIC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x003c)
99#define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET 0x0040
69#define OMAP4430_PM_ABE_MCASP_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0040) 100#define OMAP4430_PM_ABE_MCASP_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0040)
101#define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044
70#define OMAP4430_RM_ABE_MCASP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0044) 102#define OMAP4430_RM_ABE_MCASP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0044)
103#define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048
71#define OMAP4430_PM_ABE_MCBSP1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0048) 104#define OMAP4430_PM_ABE_MCBSP1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0048)
105#define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c
72#define OMAP4430_RM_ABE_MCBSP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x004c) 106#define OMAP4430_RM_ABE_MCBSP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x004c)
107#define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050
73#define OMAP4430_PM_ABE_MCBSP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0050) 108#define OMAP4430_PM_ABE_MCBSP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0050)
109#define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054
74#define OMAP4430_RM_ABE_MCBSP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0054) 110#define OMAP4430_RM_ABE_MCBSP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0054)
111#define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058
75#define OMAP4430_PM_ABE_MCBSP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0058) 112#define OMAP4430_PM_ABE_MCBSP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0058)
113#define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c
76#define OMAP4430_RM_ABE_MCBSP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x005c) 114#define OMAP4430_RM_ABE_MCBSP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x005c)
115#define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET 0x0060
77#define OMAP4430_PM_ABE_SLIMBUS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0060) 116#define OMAP4430_PM_ABE_SLIMBUS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0060)
117#define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET 0x0064
78#define OMAP4430_RM_ABE_SLIMBUS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0064) 118#define OMAP4430_RM_ABE_SLIMBUS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0064)
119#define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068
79#define OMAP4430_PM_ABE_TIMER5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0068) 120#define OMAP4430_PM_ABE_TIMER5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0068)
121#define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c
80#define OMAP4430_RM_ABE_TIMER5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x006c) 122#define OMAP4430_RM_ABE_TIMER5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x006c)
123#define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070
81#define OMAP4430_PM_ABE_TIMER6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0070) 124#define OMAP4430_PM_ABE_TIMER6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0070)
125#define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074
82#define OMAP4430_RM_ABE_TIMER6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0074) 126#define OMAP4430_RM_ABE_TIMER6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0074)
127#define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078
83#define OMAP4430_PM_ABE_TIMER7_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0078) 128#define OMAP4430_PM_ABE_TIMER7_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0078)
129#define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c
84#define OMAP4430_RM_ABE_TIMER7_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x007c) 130#define OMAP4430_RM_ABE_TIMER7_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x007c)
131#define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080
85#define OMAP4430_PM_ABE_TIMER8_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0080) 132#define OMAP4430_PM_ABE_TIMER8_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0080)
133#define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084
86#define OMAP4430_RM_ABE_TIMER8_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0084) 134#define OMAP4430_RM_ABE_TIMER8_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0084)
135#define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET 0x0088
87#define OMAP4430_PM_ABE_WDT3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0088) 136#define OMAP4430_PM_ABE_WDT3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0088)
137#define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET 0x008c
88#define OMAP4430_RM_ABE_WDT3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x008c) 138#define OMAP4430_RM_ABE_WDT3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x008c)
89 139
90/* PRM.ALWAYS_ON_PRM register offsets */ 140/* PRM.ALWAYS_ON_PRM register offsets */
141#define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET 0x0024
91#define OMAP4430_RM_ALWON_MDMINTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0024) 142#define OMAP4430_RM_ALWON_MDMINTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0024)
143#define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET 0x0028
92#define OMAP4430_PM_ALWON_SR_MPU_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0028) 144#define OMAP4430_PM_ALWON_SR_MPU_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0028)
145#define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET 0x002c
93#define OMAP4430_RM_ALWON_SR_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x002c) 146#define OMAP4430_RM_ALWON_SR_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x002c)
147#define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET 0x0030
94#define OMAP4430_PM_ALWON_SR_IVA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0030) 148#define OMAP4430_PM_ALWON_SR_IVA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0030)
149#define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET 0x0034
95#define OMAP4430_RM_ALWON_SR_IVA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0034) 150#define OMAP4430_RM_ALWON_SR_IVA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0034)
151#define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET 0x0038
96#define OMAP4430_PM_ALWON_SR_CORE_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0038) 152#define OMAP4430_PM_ALWON_SR_CORE_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0038)
153#define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET 0x003c
97#define OMAP4430_RM_ALWON_SR_CORE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x003c) 154#define OMAP4430_RM_ALWON_SR_CORE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x003c)
98 155
99/* PRM.CORE_PRM register offsets */ 156/* PRM.CORE_PRM register offsets */
157#define OMAP4_PM_CORE_PWRSTCTRL_OFFSET 0x0000
100#define OMAP4430_PM_CORE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0000) 158#define OMAP4430_PM_CORE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0000)
159#define OMAP4_PM_CORE_PWRSTST_OFFSET 0x0004
101#define OMAP4430_PM_CORE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0004) 160#define OMAP4430_PM_CORE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0004)
161#define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET 0x0024
102#define OMAP4430_RM_L3_1_L3_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0024) 162#define OMAP4430_RM_L3_1_L3_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0024)
163#define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET 0x0124
103#define OMAP4430_RM_L3_2_L3_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0124) 164#define OMAP4430_RM_L3_2_L3_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0124)
165#define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET 0x012c
104#define OMAP4430_RM_L3_2_GPMC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x012c) 166#define OMAP4430_RM_L3_2_GPMC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x012c)
167#define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET 0x0134
105#define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0134) 168#define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0134)
169#define OMAP4_RM_DUCATI_RSTCTRL_OFFSET 0x0210
106#define OMAP4430_RM_DUCATI_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0210) 170#define OMAP4430_RM_DUCATI_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0210)
171#define OMAP4_RM_DUCATI_RSTST_OFFSET 0x0214
107#define OMAP4430_RM_DUCATI_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0214) 172#define OMAP4430_RM_DUCATI_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0214)
173#define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET 0x0224
108#define OMAP4430_RM_DUCATI_DUCATI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0224) 174#define OMAP4430_RM_DUCATI_DUCATI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0224)
175#define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET 0x0324
109#define OMAP4430_RM_SDMA_SDMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0324) 176#define OMAP4430_RM_SDMA_SDMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0324)
177#define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET 0x0424
110#define OMAP4430_RM_MEMIF_DMM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0424) 178#define OMAP4430_RM_MEMIF_DMM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0424)
179#define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET 0x042c
111#define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x042c) 180#define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x042c)
181#define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET 0x0434
112#define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0434) 182#define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0434)
183#define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET 0x043c
113#define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x043c) 184#define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x043c)
185#define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET 0x0444
114#define OMAP4430_RM_MEMIF_DLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0444) 186#define OMAP4430_RM_MEMIF_DLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0444)
187#define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET 0x0454
115#define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0454) 188#define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0454)
189#define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET 0x045c
116#define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x045c) 190#define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x045c)
191#define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET 0x0464
117#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0464) 192#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0464)
193#define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524
118#define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0524) 194#define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0524)
195#define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET 0x052c
119#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x052c) 196#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x052c)
197#define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534
120#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0534) 198#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0534)
199#define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624
121#define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0624) 200#define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0624)
201#define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET 0x062c
122#define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x062c) 202#define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x062c)
203#define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634
123#define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0634) 204#define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0634)
205#define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c
124#define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x063c) 206#define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x063c)
207#define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET 0x0724
125#define OMAP4430_RM_L3INSTR_L3_3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0724) 208#define OMAP4430_RM_L3INSTR_L3_3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0724)
209#define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c
126#define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x072c) 210#define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x072c)
211#define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET 0x0744
127#define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0744) 212#define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0744)
128 213
129/* PRM.IVAHD_PRM register offsets */ 214/* PRM.IVAHD_PRM register offsets */
215#define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET 0x0000
130#define OMAP4430_PM_IVAHD_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0000) 216#define OMAP4430_PM_IVAHD_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0000)
217#define OMAP4_PM_IVAHD_PWRSTST_OFFSET 0x0004
131#define OMAP4430_PM_IVAHD_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0004) 218#define OMAP4430_PM_IVAHD_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0004)
219#define OMAP4_RM_IVAHD_RSTCTRL_OFFSET 0x0010
132#define OMAP4430_RM_IVAHD_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0010) 220#define OMAP4430_RM_IVAHD_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0010)
221#define OMAP4_RM_IVAHD_RSTST_OFFSET 0x0014
133#define OMAP4430_RM_IVAHD_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0014) 222#define OMAP4430_RM_IVAHD_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0014)
223#define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET 0x0024
134#define OMAP4430_RM_IVAHD_IVAHD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0024) 224#define OMAP4430_RM_IVAHD_IVAHD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0024)
225#define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET 0x002c
135#define OMAP4430_RM_IVAHD_SL2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x002c) 226#define OMAP4430_RM_IVAHD_SL2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x002c)
136 227
137/* PRM.CAM_PRM register offsets */ 228/* PRM.CAM_PRM register offsets */
229#define OMAP4_PM_CAM_PWRSTCTRL_OFFSET 0x0000
138#define OMAP4430_PM_CAM_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0000) 230#define OMAP4430_PM_CAM_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0000)
231#define OMAP4_PM_CAM_PWRSTST_OFFSET 0x0004
139#define OMAP4430_PM_CAM_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0004) 232#define OMAP4430_PM_CAM_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0004)
233#define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET 0x0024
140#define OMAP4430_RM_CAM_ISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0024) 234#define OMAP4430_RM_CAM_ISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0024)
235#define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c
141#define OMAP4430_RM_CAM_FDIF_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x002c) 236#define OMAP4430_RM_CAM_FDIF_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x002c)
142 237
143/* PRM.DSS_PRM register offsets */ 238/* PRM.DSS_PRM register offsets */
239#define OMAP4_PM_DSS_PWRSTCTRL_OFFSET 0x0000
144#define OMAP4430_PM_DSS_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0000) 240#define OMAP4430_PM_DSS_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0000)
241#define OMAP4_PM_DSS_PWRSTST_OFFSET 0x0004
145#define OMAP4430_PM_DSS_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0004) 242#define OMAP4430_PM_DSS_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0004)
243#define OMAP4_PM_DSS_DSS_WKDEP_OFFSET 0x0020
146#define OMAP4430_PM_DSS_DSS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0020) 244#define OMAP4430_PM_DSS_DSS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0020)
245#define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET 0x0024
147#define OMAP4430_RM_DSS_DSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0024) 246#define OMAP4430_RM_DSS_DSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0024)
247#define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET 0x002c
148#define OMAP4430_RM_DSS_DEISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x002c) 248#define OMAP4430_RM_DSS_DEISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x002c)
149 249
150/* PRM.GFX_PRM register offsets */ 250/* PRM.GFX_PRM register offsets */
251#define OMAP4_PM_GFX_PWRSTCTRL_OFFSET 0x0000
151#define OMAP4430_PM_GFX_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0000) 252#define OMAP4430_PM_GFX_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0000)
253#define OMAP4_PM_GFX_PWRSTST_OFFSET 0x0004
152#define OMAP4430_PM_GFX_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0004) 254#define OMAP4430_PM_GFX_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0004)
255#define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET 0x0024
153#define OMAP4430_RM_GFX_GFX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0024) 256#define OMAP4430_RM_GFX_GFX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0024)
154 257
155/* PRM.L3INIT_PRM register offsets */ 258/* PRM.L3INIT_PRM register offsets */
259#define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000
156#define OMAP4430_PM_L3INIT_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0000) 260#define OMAP4430_PM_L3INIT_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0000)
261#define OMAP4_PM_L3INIT_PWRSTST_OFFSET 0x0004
157#define OMAP4430_PM_L3INIT_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0004) 262#define OMAP4430_PM_L3INIT_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0004)
263#define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028
158#define OMAP4430_PM_L3INIT_MMC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0028) 264#define OMAP4430_PM_L3INIT_MMC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0028)
265#define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c
159#define OMAP4430_RM_L3INIT_MMC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x002c) 266#define OMAP4430_RM_L3INIT_MMC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x002c)
267#define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030
160#define OMAP4430_PM_L3INIT_MMC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0030) 268#define OMAP4430_PM_L3INIT_MMC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0030)
269#define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034
161#define OMAP4430_RM_L3INIT_MMC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0034) 270#define OMAP4430_RM_L3INIT_MMC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0034)
271#define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038
162#define OMAP4430_PM_L3INIT_HSI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0038) 272#define OMAP4430_PM_L3INIT_HSI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0038)
273#define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c
163#define OMAP4430_RM_L3INIT_HSI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x003c) 274#define OMAP4430_RM_L3INIT_HSI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x003c)
275#define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET 0x0040
164#define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0040) 276#define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0040)
277#define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET 0x0044
165#define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0044) 278#define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0044)
279#define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET 0x0058
166#define OMAP4430_PM_L3INIT_USB_HOST_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0058) 280#define OMAP4430_PM_L3INIT_USB_HOST_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0058)
281#define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET 0x005c
167#define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x005c) 282#define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x005c)
283#define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET 0x0060
168#define OMAP4430_PM_L3INIT_USB_OTG_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0060) 284#define OMAP4430_PM_L3INIT_USB_OTG_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0060)
285#define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET 0x0064
169#define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0064) 286#define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0064)
287#define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET 0x0068
170#define OMAP4430_PM_L3INIT_USB_TLL_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0068) 288#define OMAP4430_PM_L3INIT_USB_TLL_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0068)
289#define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET 0x006c
171#define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x006c) 290#define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x006c)
291#define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET 0x007c
172#define OMAP4430_RM_L3INIT_P1500_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x007c) 292#define OMAP4430_RM_L3INIT_P1500_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x007c)
293#define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET 0x0084
173#define OMAP4430_RM_L3INIT_EMAC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0084) 294#define OMAP4430_RM_L3INIT_EMAC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0084)
295#define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
174#define OMAP4430_PM_L3INIT_SATA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0088) 296#define OMAP4430_PM_L3INIT_SATA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0088)
297#define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
175#define OMAP4430_RM_L3INIT_SATA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x008c) 298#define OMAP4430_RM_L3INIT_SATA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x008c)
299#define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET 0x0094
176#define OMAP4430_RM_L3INIT_TPPSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0094) 300#define OMAP4430_RM_L3INIT_TPPSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0094)
301#define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET 0x0098
177#define OMAP4430_PM_L3INIT_PCIESS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0098) 302#define OMAP4430_PM_L3INIT_PCIESS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0098)
303#define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET 0x009c
178#define OMAP4430_RM_L3INIT_PCIESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x009c) 304#define OMAP4430_RM_L3INIT_PCIESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x009c)
305#define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET 0x00ac
179#define OMAP4430_RM_L3INIT_CCPTX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00ac) 306#define OMAP4430_RM_L3INIT_CCPTX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00ac)
307#define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET 0x00c0
180#define OMAP4430_PM_L3INIT_XHPI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c0) 308#define OMAP4430_PM_L3INIT_XHPI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c0)
309#define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET 0x00c4
181#define OMAP4430_RM_L3INIT_XHPI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c4) 310#define OMAP4430_RM_L3INIT_XHPI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c4)
311#define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET 0x00c8
182#define OMAP4430_PM_L3INIT_MMC6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c8) 312#define OMAP4430_PM_L3INIT_MMC6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c8)
313#define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET 0x00cc
183#define OMAP4430_RM_L3INIT_MMC6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00cc) 314#define OMAP4430_RM_L3INIT_MMC6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00cc)
315#define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET 0x00d0
184#define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d0) 316#define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d0)
317#define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET 0x00d4
185#define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d4) 318#define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d4)
319#define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET 0x00e4
186#define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00e4) 320#define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00e4)
187 321
188/* PRM.L4PER_PRM register offsets */ 322/* PRM.L4PER_PRM register offsets */
323#define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET 0x0000
189#define OMAP4430_PM_L4PER_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0000) 324#define OMAP4430_PM_L4PER_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0000)
325#define OMAP4_PM_L4PER_PWRSTST_OFFSET 0x0004
190#define OMAP4430_PM_L4PER_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0004) 326#define OMAP4430_PM_L4PER_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0004)
327#define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET 0x0024
191#define OMAP4430_RM_L4PER_ADC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0024) 328#define OMAP4430_RM_L4PER_ADC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0024)
329#define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET 0x0028
192#define OMAP4430_PM_L4PER_DMTIMER10_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0028) 330#define OMAP4430_PM_L4PER_DMTIMER10_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0028)
331#define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET 0x002c
193#define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x002c) 332#define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x002c)
333#define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET 0x0030
194#define OMAP4430_PM_L4PER_DMTIMER11_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0030) 334#define OMAP4430_PM_L4PER_DMTIMER11_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0030)
335#define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET 0x0034
195#define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0034) 336#define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0034)
337#define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET 0x0038
196#define OMAP4430_PM_L4PER_DMTIMER2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0038) 338#define OMAP4430_PM_L4PER_DMTIMER2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0038)
339#define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET 0x003c
197#define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x003c) 340#define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x003c)
341#define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET 0x0040
198#define OMAP4430_PM_L4PER_DMTIMER3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0040) 342#define OMAP4430_PM_L4PER_DMTIMER3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0040)
343#define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET 0x0044
199#define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0044) 344#define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0044)
345#define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET 0x0048
200#define OMAP4430_PM_L4PER_DMTIMER4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0048) 346#define OMAP4430_PM_L4PER_DMTIMER4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0048)
347#define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET 0x004c
201#define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x004c) 348#define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x004c)
349#define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET 0x0050
202#define OMAP4430_PM_L4PER_DMTIMER9_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0050) 350#define OMAP4430_PM_L4PER_DMTIMER9_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0050)
351#define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET 0x0054
203#define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0054) 352#define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0054)
353#define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c
204#define OMAP4430_RM_L4PER_ELM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x005c) 354#define OMAP4430_RM_L4PER_ELM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x005c)
355#define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060
205#define OMAP4430_PM_L4PER_GPIO2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0060) 356#define OMAP4430_PM_L4PER_GPIO2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0060)
357#define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064
206#define OMAP4430_RM_L4PER_GPIO2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0064) 358#define OMAP4430_RM_L4PER_GPIO2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0064)
359#define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068
207#define OMAP4430_PM_L4PER_GPIO3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0068) 360#define OMAP4430_PM_L4PER_GPIO3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0068)
361#define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c
208#define OMAP4430_RM_L4PER_GPIO3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x006c) 362#define OMAP4430_RM_L4PER_GPIO3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x006c)
363#define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070
209#define OMAP4430_PM_L4PER_GPIO4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0070) 364#define OMAP4430_PM_L4PER_GPIO4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0070)
365#define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074
210#define OMAP4430_RM_L4PER_GPIO4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0074) 366#define OMAP4430_RM_L4PER_GPIO4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0074)
367#define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078
211#define OMAP4430_PM_L4PER_GPIO5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0078) 368#define OMAP4430_PM_L4PER_GPIO5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0078)
369#define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c
212#define OMAP4430_RM_L4PER_GPIO5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x007c) 370#define OMAP4430_RM_L4PER_GPIO5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x007c)
371#define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080
213#define OMAP4430_PM_L4PER_GPIO6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0080) 372#define OMAP4430_PM_L4PER_GPIO6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0080)
373#define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084
214#define OMAP4430_RM_L4PER_GPIO6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0084) 374#define OMAP4430_RM_L4PER_GPIO6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0084)
375#define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c
215#define OMAP4430_RM_L4PER_HDQ1W_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x008c) 376#define OMAP4430_RM_L4PER_HDQ1W_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x008c)
377#define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET 0x0090
216#define OMAP4430_PM_L4PER_HECC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0090) 378#define OMAP4430_PM_L4PER_HECC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0090)
379#define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET 0x0094
217#define OMAP4430_RM_L4PER_HECC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0094) 380#define OMAP4430_RM_L4PER_HECC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0094)
381#define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET 0x0098
218#define OMAP4430_PM_L4PER_HECC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0098) 382#define OMAP4430_PM_L4PER_HECC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0098)
383#define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET 0x009c
219#define OMAP4430_RM_L4PER_HECC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x009c) 384#define OMAP4430_RM_L4PER_HECC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x009c)
385#define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0
220#define OMAP4430_PM_L4PER_I2C1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a0) 386#define OMAP4430_PM_L4PER_I2C1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a0)
387#define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4
221#define OMAP4430_RM_L4PER_I2C1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a4) 388#define OMAP4430_RM_L4PER_I2C1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a4)
389#define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8
222#define OMAP4430_PM_L4PER_I2C2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a8) 390#define OMAP4430_PM_L4PER_I2C2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a8)
391#define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac
223#define OMAP4430_RM_L4PER_I2C2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ac) 392#define OMAP4430_RM_L4PER_I2C2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ac)
393#define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0
224#define OMAP4430_PM_L4PER_I2C3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b0) 394#define OMAP4430_PM_L4PER_I2C3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b0)
395#define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4
225#define OMAP4430_RM_L4PER_I2C3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b4) 396#define OMAP4430_RM_L4PER_I2C3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b4)
397#define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8
226#define OMAP4430_PM_L4PER_I2C4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b8) 398#define OMAP4430_PM_L4PER_I2C4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b8)
399#define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc
227#define OMAP4430_RM_L4PER_I2C4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00bc) 400#define OMAP4430_RM_L4PER_I2C4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00bc)
401#define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x00c0
228#define OMAP4430_RM_L4PER_L4_PER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00c0) 402#define OMAP4430_RM_L4PER_L4_PER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00c0)
403#define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET 0x00d0
229#define OMAP4430_PM_L4PER_MCASP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d0) 404#define OMAP4430_PM_L4PER_MCASP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d0)
405#define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET 0x00d4
230#define OMAP4430_RM_L4PER_MCASP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d4) 406#define OMAP4430_RM_L4PER_MCASP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d4)
407#define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET 0x00d8
231#define OMAP4430_PM_L4PER_MCASP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d8) 408#define OMAP4430_PM_L4PER_MCASP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d8)
409#define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET 0x00dc
232#define OMAP4430_RM_L4PER_MCASP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00dc) 410#define OMAP4430_RM_L4PER_MCASP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00dc)
411#define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET 0x00e0
233#define OMAP4430_PM_L4PER_MCBSP4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e0) 412#define OMAP4430_PM_L4PER_MCBSP4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e0)
413#define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET 0x00e4
234#define OMAP4430_RM_L4PER_MCBSP4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e4) 414#define OMAP4430_RM_L4PER_MCBSP4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e4)
415#define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET 0x00ec
235#define OMAP4430_RM_L4PER_MGATE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ec) 416#define OMAP4430_RM_L4PER_MGATE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ec)
417#define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0
236#define OMAP4430_PM_L4PER_MCSPI1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f0) 418#define OMAP4430_PM_L4PER_MCSPI1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f0)
419#define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4
237#define OMAP4430_RM_L4PER_MCSPI1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f4) 420#define OMAP4430_RM_L4PER_MCSPI1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f4)
421#define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8
238#define OMAP4430_PM_L4PER_MCSPI2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f8) 422#define OMAP4430_PM_L4PER_MCSPI2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f8)
423#define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc
239#define OMAP4430_RM_L4PER_MCSPI2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00fc) 424#define OMAP4430_RM_L4PER_MCSPI2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00fc)
425#define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100
240#define OMAP4430_PM_L4PER_MCSPI3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0100) 426#define OMAP4430_PM_L4PER_MCSPI3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0100)
427#define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104
241#define OMAP4430_RM_L4PER_MCSPI3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0104) 428#define OMAP4430_RM_L4PER_MCSPI3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0104)
429#define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108
242#define OMAP4430_PM_L4PER_MCSPI4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0108) 430#define OMAP4430_PM_L4PER_MCSPI4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0108)
431#define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c
243#define OMAP4430_RM_L4PER_MCSPI4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x010c) 432#define OMAP4430_RM_L4PER_MCSPI4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x010c)
433#define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET 0x0120
244#define OMAP4430_PM_L4PER_MMCSD3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0120) 434#define OMAP4430_PM_L4PER_MMCSD3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0120)
435#define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET 0x0124
245#define OMAP4430_RM_L4PER_MMCSD3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0124) 436#define OMAP4430_RM_L4PER_MMCSD3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0124)
437#define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET 0x0128
246#define OMAP4430_PM_L4PER_MMCSD4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0128) 438#define OMAP4430_PM_L4PER_MMCSD4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0128)
439#define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET 0x012c
247#define OMAP4430_RM_L4PER_MMCSD4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x012c) 440#define OMAP4430_RM_L4PER_MMCSD4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x012c)
441#define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET 0x0134
248#define OMAP4430_RM_L4PER_MSPROHG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0134) 442#define OMAP4430_RM_L4PER_MSPROHG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0134)
443#define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET 0x0138
249#define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0138) 444#define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0138)
445#define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET 0x013c
250#define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x013c) 446#define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x013c)
447#define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET 0x0140
251#define OMAP4430_PM_L4PER_UART1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0140) 448#define OMAP4430_PM_L4PER_UART1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0140)
449#define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144
252#define OMAP4430_RM_L4PER_UART1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0144) 450#define OMAP4430_RM_L4PER_UART1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0144)
451#define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET 0x0148
253#define OMAP4430_PM_L4PER_UART2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0148) 452#define OMAP4430_PM_L4PER_UART2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0148)
453#define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c
254#define OMAP4430_RM_L4PER_UART2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x014c) 454#define OMAP4430_RM_L4PER_UART2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x014c)
455#define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET 0x0150
255#define OMAP4430_PM_L4PER_UART3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0150) 456#define OMAP4430_PM_L4PER_UART3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0150)
457#define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154
256#define OMAP4430_RM_L4PER_UART3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0154) 458#define OMAP4430_RM_L4PER_UART3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0154)
459#define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET 0x0158
257#define OMAP4430_PM_L4PER_UART4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0158) 460#define OMAP4430_PM_L4PER_UART4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0158)
461#define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c
258#define OMAP4430_RM_L4PER_UART4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x015c) 462#define OMAP4430_RM_L4PER_UART4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x015c)
463#define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET 0x0160
259#define OMAP4430_PM_L4PER_MMCSD5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0160) 464#define OMAP4430_PM_L4PER_MMCSD5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0160)
465#define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET 0x0164
260#define OMAP4430_RM_L4PER_MMCSD5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0164) 466#define OMAP4430_RM_L4PER_MMCSD5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0164)
467#define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET 0x0168
261#define OMAP4430_PM_L4PER_I2C5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0168) 468#define OMAP4430_PM_L4PER_I2C5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0168)
469#define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET 0x016c
262#define OMAP4430_RM_L4PER_I2C5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x016c) 470#define OMAP4430_RM_L4PER_I2C5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x016c)
471#define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4
263#define OMAP4430_RM_L4SEC_AES1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01a4) 472#define OMAP4430_RM_L4SEC_AES1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01a4)
473#define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac
264#define OMAP4430_RM_L4SEC_AES2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01ac) 474#define OMAP4430_RM_L4SEC_AES2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01ac)
475#define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4
265#define OMAP4430_RM_L4SEC_DES3DES_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01b4) 476#define OMAP4430_RM_L4SEC_DES3DES_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01b4)
477#define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET 0x01bc
266#define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01bc) 478#define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01bc)
479#define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4
267#define OMAP4430_RM_L4SEC_RNG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01c4) 480#define OMAP4430_RM_L4SEC_RNG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01c4)
481#define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc
268#define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01cc) 482#define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01cc)
483#define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET 0x01dc
269#define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01dc) 484#define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01dc)
270 485
271/* PRM.CEFUSE_PRM register offsets */ 486/* PRM.CEFUSE_PRM register offsets */
487#define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000
272#define OMAP4430_PM_CEFUSE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0000) 488#define OMAP4430_PM_CEFUSE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0000)
489#define OMAP4_PM_CEFUSE_PWRSTST_OFFSET 0x0004
273#define OMAP4430_PM_CEFUSE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0004) 490#define OMAP4430_PM_CEFUSE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0004)
491#define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET 0x0024
274#define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0024) 492#define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0024)
275 493
276/* PRM.WKUP_PRM register offsets */ 494/* PRM.WKUP_PRM register offsets */
495#define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET 0x0024
277#define OMAP4430_RM_WKUP_L4WKUP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0024) 496#define OMAP4430_RM_WKUP_L4WKUP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0024)
497#define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET 0x002c
278#define OMAP4430_RM_WKUP_WDT1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x002c) 498#define OMAP4430_RM_WKUP_WDT1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x002c)
499#define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET 0x0030
279#define OMAP4430_PM_WKUP_WDT2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0030) 500#define OMAP4430_PM_WKUP_WDT2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0030)
501#define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET 0x0034
280#define OMAP4430_RM_WKUP_WDT2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0034) 502#define OMAP4430_RM_WKUP_WDT2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0034)
503#define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET 0x0038
281#define OMAP4430_PM_WKUP_GPIO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0038) 504#define OMAP4430_PM_WKUP_GPIO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0038)
505#define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET 0x003c
282#define OMAP4430_RM_WKUP_GPIO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x003c) 506#define OMAP4430_RM_WKUP_GPIO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x003c)
507#define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET 0x0040
283#define OMAP4430_PM_WKUP_TIMER1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0040) 508#define OMAP4430_PM_WKUP_TIMER1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0040)
509#define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET 0x0044
284#define OMAP4430_RM_WKUP_TIMER1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0044) 510#define OMAP4430_RM_WKUP_TIMER1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0044)
511#define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET 0x0048
285#define OMAP4430_PM_WKUP_TIMER12_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0048) 512#define OMAP4430_PM_WKUP_TIMER12_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0048)
513#define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET 0x004c
286#define OMAP4430_RM_WKUP_TIMER12_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x004c) 514#define OMAP4430_RM_WKUP_TIMER12_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x004c)
515#define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET 0x0054
287#define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0054) 516#define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0054)
517#define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET 0x0058
288#define OMAP4430_PM_WKUP_USIM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0058) 518#define OMAP4430_PM_WKUP_USIM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0058)
519#define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET 0x005c
289#define OMAP4430_RM_WKUP_USIM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x005c) 520#define OMAP4430_RM_WKUP_USIM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x005c)
521#define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET 0x0064
290#define OMAP4430_RM_WKUP_SARRAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0064) 522#define OMAP4430_RM_WKUP_SARRAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0064)
523#define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET 0x0078
291#define OMAP4430_PM_WKUP_KEYBOARD_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0078) 524#define OMAP4430_PM_WKUP_KEYBOARD_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0078)
525#define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET 0x007c
292#define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x007c) 526#define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x007c)
527#define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET 0x0080
293#define OMAP4430_PM_WKUP_RTC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0080) 528#define OMAP4430_PM_WKUP_RTC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0080)
529#define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET 0x0084
294#define OMAP4430_RM_WKUP_RTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0084) 530#define OMAP4430_RM_WKUP_RTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0084)
295 531
296/* PRM.WKUP_CM register offsets */ 532/* PRM.WKUP_CM register offsets */
533#define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET 0x0000
297#define OMAP4430_CM_WKUP_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0000) 534#define OMAP4430_CM_WKUP_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0000)
535#define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0020
298#define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0020) 536#define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0020)
537#define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0028
299#define OMAP4430_CM_WKUP_WDT1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0028) 538#define OMAP4430_CM_WKUP_WDT1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0028)
539#define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET 0x0030
300#define OMAP4430_CM_WKUP_WDT2_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0030) 540#define OMAP4430_CM_WKUP_WDT2_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0030)
541#define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET 0x0038
301#define OMAP4430_CM_WKUP_GPIO1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0038) 542#define OMAP4430_CM_WKUP_GPIO1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0038)
543#define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0040
302#define OMAP4430_CM_WKUP_TIMER1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0040) 544#define OMAP4430_CM_WKUP_TIMER1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0040)
545#define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET 0x0048
303#define OMAP4430_CM_WKUP_TIMER12_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0048) 546#define OMAP4430_CM_WKUP_TIMER12_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0048)
547#define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0050
304#define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0050) 548#define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0050)
549#define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET 0x0058
305#define OMAP4430_CM_WKUP_USIM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0058) 550#define OMAP4430_CM_WKUP_USIM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0058)
551#define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET 0x0060
306#define OMAP4430_CM_WKUP_SARRAM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0060) 552#define OMAP4430_CM_WKUP_SARRAM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0060)
553#define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET 0x0078
307#define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0078) 554#define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0078)
555#define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET 0x0080
308#define OMAP4430_CM_WKUP_RTC_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0080) 556#define OMAP4430_CM_WKUP_RTC_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0080)
557#define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET 0x0088
309#define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0088) 558#define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0088)
310 559
311/* PRM.EMU_PRM register offsets */ 560/* PRM.EMU_PRM register offsets */
561#define OMAP4_PM_EMU_PWRSTCTRL_OFFSET 0x0000
312#define OMAP4430_PM_EMU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0000) 562#define OMAP4430_PM_EMU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0000)
563#define OMAP4_PM_EMU_PWRSTST_OFFSET 0x0004
313#define OMAP4430_PM_EMU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0004) 564#define OMAP4430_PM_EMU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0004)
565#define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024
314#define OMAP4430_RM_EMU_DEBUGSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0024) 566#define OMAP4430_RM_EMU_DEBUGSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0024)
315 567
316/* PRM.EMU_CM register offsets */ 568/* PRM.EMU_CM register offsets */
569#define OMAP4_CM_EMU_CLKSTCTRL_OFFSET 0x0000
317#define OMAP4430_CM_EMU_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0000) 570#define OMAP4430_CM_EMU_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0000)
571#define OMAP4_CM_EMU_DYNAMICDEP_OFFSET 0x0008
318#define OMAP4430_CM_EMU_DYNAMICDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0008) 572#define OMAP4430_CM_EMU_DYNAMICDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0008)
573#define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020
319#define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0020) 574#define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0020)
320 575
321/* PRM.DEVICE_PRM register offsets */ 576/* PRM.DEVICE_PRM register offsets */
577#define OMAP4_PRM_RSTCTRL_OFFSET 0x0000
322#define OMAP4430_PRM_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0000) 578#define OMAP4430_PRM_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0000)
579#define OMAP4_PRM_RSTST_OFFSET 0x0004
323#define OMAP4430_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0004) 580#define OMAP4430_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0004)
581#define OMAP4_PRM_RSTTIME_OFFSET 0x0008
324#define OMAP4430_PRM_RSTTIME OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0008) 582#define OMAP4430_PRM_RSTTIME OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0008)
583#define OMAP4_PRM_CLKREQCTRL_OFFSET 0x000c
325#define OMAP4430_PRM_CLKREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x000c) 584#define OMAP4430_PRM_CLKREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x000c)
585#define OMAP4_PRM_VOLTCTRL_OFFSET 0x0010
326#define OMAP4430_PRM_VOLTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0010) 586#define OMAP4430_PRM_VOLTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0010)
587#define OMAP4_PRM_PWRREQCTRL_OFFSET 0x0014
327#define OMAP4430_PRM_PWRREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0014) 588#define OMAP4430_PRM_PWRREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0014)
589#define OMAP4_PRM_PSCON_COUNT_OFFSET 0x0018
328#define OMAP4430_PRM_PSCON_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0018) 590#define OMAP4430_PRM_PSCON_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0018)
591#define OMAP4_PRM_IO_COUNT_OFFSET 0x001c
329#define OMAP4430_PRM_IO_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x001c) 592#define OMAP4430_PRM_IO_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x001c)
593#define OMAP4_PRM_IO_PMCTRL_OFFSET 0x0020
330#define OMAP4430_PRM_IO_PMCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0020) 594#define OMAP4430_PRM_IO_PMCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0020)
595#define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024
331#define OMAP4430_PRM_VOLTSETUP_WARMRESET OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0024) 596#define OMAP4430_PRM_VOLTSETUP_WARMRESET OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0024)
597#define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028
332#define OMAP4430_PRM_VOLTSETUP_CORE_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0028) 598#define OMAP4430_PRM_VOLTSETUP_CORE_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0028)
599#define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c
333#define OMAP4430_PRM_VOLTSETUP_MPU_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x002c) 600#define OMAP4430_PRM_VOLTSETUP_MPU_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x002c)
601#define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET 0x0030
334#define OMAP4430_PRM_VOLTSETUP_IVA_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0030) 602#define OMAP4430_PRM_VOLTSETUP_IVA_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0030)
603#define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034
335#define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0034) 604#define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0034)
605#define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038
336#define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0038) 606#define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0038)
607#define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET 0x003c
337#define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x003c) 608#define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x003c)
609#define OMAP4_PRM_VP_CORE_CONFIG_OFFSET 0x0040
338#define OMAP4430_PRM_VP_CORE_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0040) 610#define OMAP4430_PRM_VP_CORE_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0040)
611#define OMAP4_PRM_VP_CORE_STATUS_OFFSET 0x0044
339#define OMAP4430_PRM_VP_CORE_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0044) 612#define OMAP4430_PRM_VP_CORE_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0044)
613#define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048
340#define OMAP4430_PRM_VP_CORE_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0048) 614#define OMAP4430_PRM_VP_CORE_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0048)
615#define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c
341#define OMAP4430_PRM_VP_CORE_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x004c) 616#define OMAP4430_PRM_VP_CORE_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x004c)
617#define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050
342#define OMAP4430_PRM_VP_CORE_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0050) 618#define OMAP4430_PRM_VP_CORE_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0050)
619#define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054
343#define OMAP4430_PRM_VP_CORE_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0054) 620#define OMAP4430_PRM_VP_CORE_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0054)
621#define OMAP4_PRM_VP_MPU_CONFIG_OFFSET 0x0058
344#define OMAP4430_PRM_VP_MPU_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0058) 622#define OMAP4430_PRM_VP_MPU_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0058)
623#define OMAP4_PRM_VP_MPU_STATUS_OFFSET 0x005c
345#define OMAP4430_PRM_VP_MPU_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x005c) 624#define OMAP4430_PRM_VP_MPU_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x005c)
625#define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060
346#define OMAP4430_PRM_VP_MPU_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0060) 626#define OMAP4430_PRM_VP_MPU_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0060)
627#define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064
347#define OMAP4430_PRM_VP_MPU_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0064) 628#define OMAP4430_PRM_VP_MPU_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0064)
629#define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068
348#define OMAP4430_PRM_VP_MPU_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0068) 630#define OMAP4430_PRM_VP_MPU_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0068)
631#define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c
349#define OMAP4430_PRM_VP_MPU_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x006c) 632#define OMAP4430_PRM_VP_MPU_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x006c)
633#define OMAP4_PRM_VP_IVA_CONFIG_OFFSET 0x0070
350#define OMAP4430_PRM_VP_IVA_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0070) 634#define OMAP4430_PRM_VP_IVA_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0070)
635#define OMAP4_PRM_VP_IVA_STATUS_OFFSET 0x0074
351#define OMAP4430_PRM_VP_IVA_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0074) 636#define OMAP4430_PRM_VP_IVA_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0074)
637#define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET 0x0078
352#define OMAP4430_PRM_VP_IVA_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0078) 638#define OMAP4430_PRM_VP_IVA_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0078)
639#define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET 0x007c
353#define OMAP4430_PRM_VP_IVA_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x007c) 640#define OMAP4430_PRM_VP_IVA_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x007c)
641#define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET 0x0080
354#define OMAP4430_PRM_VP_IVA_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0080) 642#define OMAP4430_PRM_VP_IVA_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0080)
643#define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET 0x0084
355#define OMAP4430_PRM_VP_IVA_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0084) 644#define OMAP4430_PRM_VP_IVA_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0084)
645#define OMAP4_PRM_VC_SMPS_SA_OFFSET 0x0088
356#define OMAP4430_PRM_VC_SMPS_SA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0088) 646#define OMAP4430_PRM_VC_SMPS_SA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0088)
647#define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET 0x008c
357#define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x008c) 648#define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x008c)
649#define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET 0x0090
358#define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0090) 650#define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0090)
651#define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094
359#define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0094) 652#define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0094)
653#define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x0098
360#define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0098) 654#define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0098)
655#define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET 0x009c
361#define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x009c) 656#define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x009c)
657#define OMAP4_PRM_VC_VAL_BYPASS_OFFSET 0x00a0
362#define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a0) 658#define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a0)
659#define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4
363#define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a4) 660#define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a4)
661#define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET 0x00a8
364#define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a8) 662#define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a8)
663#define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac
365#define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ac) 664#define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ac)
665#define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0
366#define OMAP4430_PRM_SRAM_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b0) 666#define OMAP4430_PRM_SRAM_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b0)
667#define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET 0x00b4
367#define OMAP4430_PRM_SRAM_WKUP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b4) 668#define OMAP4430_PRM_SRAM_WKUP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b4)
669#define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x00b8
368#define OMAP4430_PRM_LDO_SRAM_CORE_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b8) 670#define OMAP4430_PRM_LDO_SRAM_CORE_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b8)
671#define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x00bc
369#define OMAP4430_PRM_LDO_SRAM_CORE_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00bc) 672#define OMAP4430_PRM_LDO_SRAM_CORE_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00bc)
673#define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x00c0
370#define OMAP4430_PRM_LDO_SRAM_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c0) 674#define OMAP4430_PRM_LDO_SRAM_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c0)
675#define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x00c4
371#define OMAP4430_PRM_LDO_SRAM_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c4) 676#define OMAP4430_PRM_LDO_SRAM_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c4)
677#define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET 0x00c8
372#define OMAP4430_PRM_LDO_SRAM_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c8) 678#define OMAP4430_PRM_LDO_SRAM_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c8)
679#define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET 0x00cc
373#define OMAP4430_PRM_LDO_SRAM_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00cc) 680#define OMAP4430_PRM_LDO_SRAM_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00cc)
681#define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET 0x00d0
374#define OMAP4430_PRM_LDO_ABB_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d0) 682#define OMAP4430_PRM_LDO_ABB_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d0)
683#define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET 0x00d4
375#define OMAP4430_PRM_LDO_ABB_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d4) 684#define OMAP4430_PRM_LDO_ABB_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d4)
685#define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET 0x00d8
376#define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8) 686#define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8)
687#define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc
377#define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc) 688#define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc)
689#define OMAP4_PRM_LDO_BANDGAP_CTRL_OFFSET 0x00e0
378#define OMAP4430_PRM_LDO_BANDGAP_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0) 690#define OMAP4430_PRM_LDO_BANDGAP_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0)
691#define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4
379#define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4) 692#define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4)
693#define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8
380#define OMAP4430_PRM_PHASE1_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e8) 694#define OMAP4430_PRM_PHASE1_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e8)
695#define OMAP4_PRM_PHASE2A_CNDP_OFFSET 0x00ec
381#define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ec) 696#define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ec)
697#define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0
382#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0) 698#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0)
699#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4
383#define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4) 700#define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4)
384 701
385/* CHIRON_PRCM */ 702/*
386 703 * PRCM_MPU
704 *
705 * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
706 * point of view the PRCM_MPU is a single entity. It shares the same
707 * programming model as the global PRCM and thus can be assimilate as two new
708 * MOD inside the PRCM
709 */
387 710
388/* CHIRON_PRCM.CHIRONSS_OCP_SOCKET_PRCM register offsets */ 711/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
389#define OMAP4430_REVISION_PRCM OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000) 712#define OMAP4_REVISION_PRCM_OFFSET 0x0000
713#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD, 0x0000)
390 714
391/* CHIRON_PRCM.CHIRONSS_DEVICE_PRM register offsets */ 715/* PRCM_MPU.DEVICE_PRM register offsets */
392#define OMAP4430_CHIRON_PRCM_PRM_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000) 716#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
717#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000)
393 718
394/* CHIRON_PRCM.CHIRONSS_CPU0 register offsets */ 719/* PRCM_MPU.CPU0 register offsets */
395#define OMAP4430_PM_PDA_CPU0_PWRSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000) 720#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
396#define OMAP4430_PM_PDA_CPU0_PWRSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004) 721#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0000)
397#define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008) 722#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
398#define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c) 723#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0004)
399#define OMAP4430_RM_PDA_CPU0_CPU0_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010) 724#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
400#define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014) 725#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0008)
401#define OMAP4430_CM_PDA_CPU0_CLKSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018) 726#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
727#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x000c)
728#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
729#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0010)
730#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
731#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0014)
732#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
733#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0018)
402 734
403/* CHIRON_PRCM.CHIRONSS_CPU1 register offsets */ 735/* PRCM_MPU.CPU1 register offsets */
404#define OMAP4430_PM_PDA_CPU1_PWRSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000) 736#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
405#define OMAP4430_PM_PDA_CPU1_PWRSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004) 737#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0000)
406#define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008) 738#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
407#define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c) 739#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0004)
408#define OMAP4430_RM_PDA_CPU1_CPU1_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010) 740#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
409#define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014) 741#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0008)
410#define OMAP4430_CM_PDA_CPU1_CLKSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018) 742#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
743#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x000c)
744#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
745#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0010)
746#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
747#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0014)
748#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
749#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0018)
411#endif 750#endif
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 6da796ef82bd..78b49a626d06 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -110,8 +110,13 @@ config OMAP_IOMMU
110 tristate 110 tristate
111 111
112config OMAP_IOMMU_DEBUG 112config OMAP_IOMMU_DEBUG
113 depends on OMAP_IOMMU 113 tristate "Export OMAP IOMMU internals in DebugFS"
114 tristate 114 depends on OMAP_IOMMU && DEBUG_FS
115 help
116 Select this to see extensive information about
117 the internal state of OMAP IOMMU in debugfs.
118
119 Say N unless you know you need this.
115 120
116choice 121choice
117 prompt "System timer" 122 prompt "System timer"
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 5261a0923691..7190cbd92620 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -12,14 +12,12 @@
12 */ 12 */
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/list.h> 15#include <linux/list.h>
17#include <linux/errno.h> 16#include <linux/errno.h>
18#include <linux/err.h> 17#include <linux/err.h>
19#include <linux/string.h> 18#include <linux/string.h>
20#include <linux/clk.h> 19#include <linux/clk.h>
21#include <linux/mutex.h> 20#include <linux/mutex.h>
22#include <linux/platform_device.h>
23#include <linux/cpufreq.h> 21#include <linux/cpufreq.h>
24#include <linux/debugfs.h> 22#include <linux/debugfs.h>
25#include <linux/io.h> 23#include <linux/io.h>
@@ -32,9 +30,9 @@ static DEFINE_SPINLOCK(clockfw_lock);
32 30
33static struct clk_functions *arch_clock; 31static struct clk_functions *arch_clock;
34 32
35/*------------------------------------------------------------------------- 33/*
36 * Standard clock functions defined in include/linux/clk.h 34 * Standard clock functions defined in include/linux/clk.h
37 *-------------------------------------------------------------------------*/ 35 */
38 36
39int clk_enable(struct clk *clk) 37int clk_enable(struct clk *clk)
40{ 38{
@@ -92,9 +90,9 @@ unsigned long clk_get_rate(struct clk *clk)
92} 90}
93EXPORT_SYMBOL(clk_get_rate); 91EXPORT_SYMBOL(clk_get_rate);
94 92
95/*------------------------------------------------------------------------- 93/*
96 * Optional clock functions defined in include/linux/clk.h 94 * Optional clock functions defined in include/linux/clk.h
97 *-------------------------------------------------------------------------*/ 95 */
98 96
99long clk_round_rate(struct clk *clk, unsigned long rate) 97long clk_round_rate(struct clk *clk, unsigned long rate)
100{ 98{
@@ -140,9 +138,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
140 unsigned long flags; 138 unsigned long flags;
141 int ret = -EINVAL; 139 int ret = -EINVAL;
142 140
143 if (cpu_is_omap44xx())
144 /* OMAP4 clk framework not supported yet */
145 return 0;
146 if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent)) 141 if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
147 return ret; 142 return ret;
148 143
@@ -169,9 +164,9 @@ struct clk *clk_get_parent(struct clk *clk)
169} 164}
170EXPORT_SYMBOL(clk_get_parent); 165EXPORT_SYMBOL(clk_get_parent);
171 166
172/*------------------------------------------------------------------------- 167/*
173 * OMAP specific clock functions shared between omap1 and omap2 168 * OMAP specific clock functions shared between omap1 and omap2
174 *-------------------------------------------------------------------------*/ 169 */
175 170
176int __initdata mpurate; 171int __initdata mpurate;
177 172
@@ -222,7 +217,7 @@ void clk_reparent(struct clk *child, struct clk *parent)
222} 217}
223 218
224/* Propagate rate to children */ 219/* Propagate rate to children */
225void propagate_rate(struct clk * tclk) 220void propagate_rate(struct clk *tclk)
226{ 221{
227 struct clk *clkp; 222 struct clk *clkp;
228 223
@@ -389,7 +384,9 @@ void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
389} 384}
390#endif 385#endif
391 386
392/*-------------------------------------------------------------------------*/ 387/*
388 *
389 */
393 390
394#ifdef CONFIG_OMAP_RESET_CLOCKS 391#ifdef CONFIG_OMAP_RESET_CLOCKS
395/* 392/*
@@ -404,7 +401,7 @@ static int __init clk_disable_unused(void)
404 if (ck->ops == &clkops_null) 401 if (ck->ops == &clkops_null)
405 continue; 402 continue;
406 403
407 if (ck->usecount > 0 || ck->enable_reg == 0) 404 if (ck->usecount > 0 || !ck->enable_reg)
408 continue; 405 continue;
409 406
410 spin_lock_irqsave(&clockfw_lock, flags); 407 spin_lock_irqsave(&clockfw_lock, flags);
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index f12f0e39ddf2..219c01e82bc5 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -47,9 +47,6 @@
47struct omap_board_config_kernel *omap_board_config; 47struct omap_board_config_kernel *omap_board_config;
48int omap_board_config_size; 48int omap_board_config_size;
49 49
50/* used by omap-smp.c and board-4430sdp.c */
51void __iomem *gic_cpu_base_addr;
52
53static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out) 50static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
54{ 51{
55 struct omap_board_config_kernel *kinfo = NULL; 52 struct omap_board_config_kernel *kinfo = NULL;
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 1d959965ff52..f7f571e7987e 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -501,7 +501,8 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
501 burst = 0x2; 501 burst = 0x2;
502 break; 502 break;
503 } 503 }
504 /* not supported by current hardware on OMAP1 504 /*
505 * not supported by current hardware on OMAP1
505 * w |= (0x03 << 7); 506 * w |= (0x03 << 7);
506 * fall through 507 * fall through
507 */ 508 */
@@ -510,7 +511,8 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
510 burst = 0x3; 511 burst = 0x3;
511 break; 512 break;
512 } 513 }
513 /* OMAP1 don't support burst 16 514 /*
515 * OMAP1 don't support burst 16
514 * fall through 516 * fall through
515 */ 517 */
516 default: 518 default:
@@ -604,7 +606,8 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
604 burst = 0x3; 606 burst = 0x3;
605 break; 607 break;
606 } 608 }
607 /* OMAP1 don't support burst 16 609 /*
610 * OMAP1 don't support burst 16
608 * fall through 611 * fall through
609 */ 612 */
610 default: 613 default:
@@ -709,6 +712,21 @@ static inline void omap2_enable_irq_lch(int lch)
709 spin_unlock_irqrestore(&dma_chan_lock, flags); 712 spin_unlock_irqrestore(&dma_chan_lock, flags);
710} 713}
711 714
715static inline void omap2_disable_irq_lch(int lch)
716{
717 u32 val;
718 unsigned long flags;
719
720 if (!cpu_class_is_omap2())
721 return;
722
723 spin_lock_irqsave(&dma_chan_lock, flags);
724 val = dma_read(IRQENABLE_L0);
725 val &= ~(1 << lch);
726 dma_write(val, IRQENABLE_L0);
727 spin_unlock_irqrestore(&dma_chan_lock, flags);
728}
729
712int omap_request_dma(int dev_id, const char *dev_name, 730int omap_request_dma(int dev_id, const char *dev_name,
713 void (*callback)(int lch, u16 ch_status, void *data), 731 void (*callback)(int lch, u16 ch_status, void *data),
714 void *data, int *dma_ch_out) 732 void *data, int *dma_ch_out)
@@ -807,14 +825,7 @@ void omap_free_dma(int lch)
807 } 825 }
808 826
809 if (cpu_class_is_omap2()) { 827 if (cpu_class_is_omap2()) {
810 u32 val; 828 omap2_disable_irq_lch(lch);
811
812 spin_lock_irqsave(&dma_chan_lock, flags);
813 /* Disable interrupts */
814 val = dma_read(IRQENABLE_L0);
815 val &= ~(1 << lch);
816 dma_write(val, IRQENABLE_L0);
817 spin_unlock_irqrestore(&dma_chan_lock, flags);
818 829
819 /* Clear the CSR register and IRQ status register */ 830 /* Clear the CSR register and IRQ status register */
820 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch)); 831 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
@@ -1277,8 +1288,10 @@ int omap_request_dma_chain(int dev_id, const char *dev_name,
1277 return -EINVAL; 1288 return -EINVAL;
1278 } 1289 }
1279 1290
1280 /* Allocate a queue to maintain the status of the channels 1291 /*
1281 * in the chain */ 1292 * Allocate a queue to maintain the status of the channels
1293 * in the chain
1294 */
1282 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL); 1295 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1283 if (channels == NULL) { 1296 if (channels == NULL) {
1284 printk(KERN_ERR "omap_dma: No memory for channel queue\n"); 1297 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
@@ -1907,7 +1920,8 @@ static int omap2_dma_handle_ch(int ch)
1907 printk(KERN_INFO "DMA transaction error with device %d\n", 1920 printk(KERN_INFO "DMA transaction error with device %d\n",
1908 dma_chan[ch].dev_id); 1921 dma_chan[ch].dev_id);
1909 if (cpu_class_is_omap2()) { 1922 if (cpu_class_is_omap2()) {
1910 /* Errata: sDMA Channel is not disabled 1923 /*
1924 * Errata: sDMA Channel is not disabled
1911 * after a transaction error. So we explicitely 1925 * after a transaction error. So we explicitely
1912 * disable the channel 1926 * disable the channel
1913 */ 1927 */
@@ -2107,6 +2121,9 @@ static int __init omap_init_dma(void)
2107 2121
2108 for (ch = 0; ch < dma_chan_count; ch++) { 2122 for (ch = 0; ch < dma_chan_count; ch++) {
2109 omap_clear_dma(ch); 2123 omap_clear_dma(ch);
2124 if (cpu_class_is_omap2())
2125 omap2_disable_irq_lch(ch);
2126
2110 dma_chan[ch].dev_id = -1; 2127 dma_chan[ch].dev_id = -1;
2111 dma_chan[ch].next_lch = -1; 2128 dma_chan[ch].next_lch = -1;
2112 2129
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 4d99dfbc8bef..c64875f11fac 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -264,8 +264,8 @@ static struct omap_dm_timer omap4_dm_timers[] = {
264 { .phys_base = 0x4a320000, .irq = OMAP44XX_IRQ_GPT12 }, 264 { .phys_base = 0x4a320000, .irq = OMAP44XX_IRQ_GPT12 },
265}; 265};
266static const char *omap4_dm_source_names[] __initdata = { 266static const char *omap4_dm_source_names[] __initdata = {
267 "sys_ck", 267 "sys_clkin_ck",
268 "omap_32k_fck", 268 "sys_32k_ck",
269 NULL 269 NULL
270}; 270};
271static struct clk *omap4_dm_source_clocks[2]; 271static struct clk *omap4_dm_source_clocks[2];
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 45a225d09125..dc2ac42d6319 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -27,6 +27,7 @@
27#include <mach/irqs.h> 27#include <mach/irqs.h>
28#include <mach/gpio.h> 28#include <mach/gpio.h>
29#include <asm/mach/irq.h> 29#include <asm/mach/irq.h>
30#include <plat/powerdomain.h>
30 31
31/* 32/*
32 * OMAP1510 GPIO registers 33 * OMAP1510 GPIO registers
@@ -137,7 +138,11 @@
137#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040 138#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
138#define OMAP4_GPIO_IRQWAKEN0 0x0044 139#define OMAP4_GPIO_IRQWAKEN0 0x0044
139#define OMAP4_GPIO_IRQWAKEN1 0x0048 140#define OMAP4_GPIO_IRQWAKEN1 0x0048
140#define OMAP4_GPIO_SYSSTATUS 0x0104 141#define OMAP4_GPIO_SYSSTATUS 0x0114
142#define OMAP4_GPIO_IRQENABLE1 0x011c
143#define OMAP4_GPIO_WAKE_EN 0x0120
144#define OMAP4_GPIO_IRQSTATUS2 0x0128
145#define OMAP4_GPIO_IRQENABLE2 0x012c
141#define OMAP4_GPIO_CTRL 0x0130 146#define OMAP4_GPIO_CTRL 0x0130
142#define OMAP4_GPIO_OE 0x0134 147#define OMAP4_GPIO_OE 0x0134
143#define OMAP4_GPIO_DATAIN 0x0138 148#define OMAP4_GPIO_DATAIN 0x0138
@@ -148,6 +153,10 @@
148#define OMAP4_GPIO_FALLINGDETECT 0x014c 153#define OMAP4_GPIO_FALLINGDETECT 0x014c
149#define OMAP4_GPIO_DEBOUNCENABLE 0x0150 154#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
150#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154 155#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
156#define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
157#define OMAP4_GPIO_SETIRQENABLE1 0x0164
158#define OMAP4_GPIO_CLEARWKUENA 0x0180
159#define OMAP4_GPIO_SETWKUENA 0x0184
151#define OMAP4_GPIO_CLEARDATAOUT 0x0190 160#define OMAP4_GPIO_CLEARDATAOUT 0x0190
152#define OMAP4_GPIO_SETDATAOUT 0x0194 161#define OMAP4_GPIO_SETDATAOUT 0x0194
153/* 162/*
@@ -195,6 +204,7 @@ struct gpio_bank {
195 struct gpio_chip chip; 204 struct gpio_chip chip;
196 struct clk *dbck; 205 struct clk *dbck;
197 u32 mod_usage; 206 u32 mod_usage;
207 u32 dbck_enable_mask;
198}; 208};
199 209
200#define METHOD_MPUIO 0 210#define METHOD_MPUIO 0
@@ -303,8 +313,6 @@ struct omap3_gpio_regs {
303 u32 risingdetect; 313 u32 risingdetect;
304 u32 fallingdetect; 314 u32 fallingdetect;
305 u32 dataout; 315 u32 dataout;
306 u32 setwkuena;
307 u32 setdataout;
308}; 316};
309 317
310static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS]; 318static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
@@ -591,12 +599,16 @@ static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
591 reg += OMAP7XX_GPIO_DATA_OUTPUT; 599 reg += OMAP7XX_GPIO_DATA_OUTPUT;
592 break; 600 break;
593#endif 601#endif
594#ifdef CONFIG_ARCH_OMAP2PLUS 602#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
595 case METHOD_GPIO_24XX: 603 case METHOD_GPIO_24XX:
596 case METHOD_GPIO_44XX:
597 reg += OMAP24XX_GPIO_DATAOUT; 604 reg += OMAP24XX_GPIO_DATAOUT;
598 break; 605 break;
599#endif 606#endif
607#ifdef CONFIG_ARCH_OMAP4
608 case METHOD_GPIO_44XX:
609 reg += OMAP4_GPIO_DATAOUT;
610 break;
611#endif
600 default: 612 default:
601 return -EINVAL; 613 return -EINVAL;
602 } 614 }
@@ -646,6 +658,7 @@ void omap_set_gpio_debounce(int gpio, int enable)
646 goto done; 658 goto done;
647 659
648 if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 660 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
661 bank->dbck_enable_mask = val;
649 if (enable) 662 if (enable)
650 clk_enable(bank->dbck); 663 clk_enable(bank->dbck);
651 else 664 else
@@ -724,15 +737,27 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
724 OMAP4_GPIO_IRQWAKEN0); 737 OMAP4_GPIO_IRQWAKEN0);
725 } 738 }
726 } else { 739 } else {
727 if (trigger != 0) 740 /*
741 * GPIO wakeup request can only be generated on edge
742 * transitions
743 */
744 if (trigger & IRQ_TYPE_EDGE_BOTH)
728 __raw_writel(1 << gpio, bank->base 745 __raw_writel(1 << gpio, bank->base
729 + OMAP24XX_GPIO_SETWKUENA); 746 + OMAP24XX_GPIO_SETWKUENA);
730 else 747 else
731 __raw_writel(1 << gpio, bank->base 748 __raw_writel(1 << gpio, bank->base
732 + OMAP24XX_GPIO_CLEARWKUENA); 749 + OMAP24XX_GPIO_CLEARWKUENA);
733 } 750 }
734 } else { 751 }
735 if (trigger != 0) 752 /* This part needs to be executed always for OMAP34xx */
753 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
754 /*
755 * Log the edge gpio and manually trigger the IRQ
756 * after resume if the input level changes
757 * to avoid irq lost during PER RET/OFF mode
758 * Applies for omap2 non-wakeup gpio and all omap3 gpios
759 */
760 if (trigger & IRQ_TYPE_EDGE_BOTH)
736 bank->enabled_non_wakeup_gpios |= gpio_bit; 761 bank->enabled_non_wakeup_gpios |= gpio_bit;
737 else 762 else
738 bank->enabled_non_wakeup_gpios &= ~gpio_bit; 763 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
@@ -1200,11 +1225,17 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1200#endif 1225#endif
1201 if (!cpu_class_is_omap1()) { 1226 if (!cpu_class_is_omap1()) {
1202 if (!bank->mod_usage) { 1227 if (!bank->mod_usage) {
1228 void __iomem *reg = bank->base;
1203 u32 ctrl; 1229 u32 ctrl;
1204 ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL); 1230
1205 ctrl &= 0xFFFFFFFE; 1231 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1232 reg += OMAP24XX_GPIO_CTRL;
1233 else if (cpu_is_omap44xx())
1234 reg += OMAP4_GPIO_CTRL;
1235 ctrl = __raw_readl(reg);
1206 /* Module is enabled, clocks are not gated */ 1236 /* Module is enabled, clocks are not gated */
1207 __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL); 1237 ctrl &= 0xFFFFFFFE;
1238 __raw_writel(ctrl, reg);
1208 } 1239 }
1209 bank->mod_usage |= 1 << offset; 1240 bank->mod_usage |= 1 << offset;
1210 } 1241 }
@@ -1226,22 +1257,34 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1226 __raw_writel(1 << offset, reg); 1257 __raw_writel(1 << offset, reg);
1227 } 1258 }
1228#endif 1259#endif
1229#ifdef CONFIG_ARCH_OMAP2PLUS 1260#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1230 if ((bank->method == METHOD_GPIO_24XX) || 1261 if (bank->method == METHOD_GPIO_24XX) {
1231 (bank->method == METHOD_GPIO_44XX)) {
1232 /* Disable wake-up during idle for dynamic tick */ 1262 /* Disable wake-up during idle for dynamic tick */
1233 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1263 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1234 __raw_writel(1 << offset, reg); 1264 __raw_writel(1 << offset, reg);
1235 } 1265 }
1236#endif 1266#endif
1267#ifdef CONFIG_ARCH_OMAP4
1268 if (bank->method == METHOD_GPIO_44XX) {
1269 /* Disable wake-up during idle for dynamic tick */
1270 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
1271 __raw_writel(1 << offset, reg);
1272 }
1273#endif
1237 if (!cpu_class_is_omap1()) { 1274 if (!cpu_class_is_omap1()) {
1238 bank->mod_usage &= ~(1 << offset); 1275 bank->mod_usage &= ~(1 << offset);
1239 if (!bank->mod_usage) { 1276 if (!bank->mod_usage) {
1277 void __iomem *reg = bank->base;
1240 u32 ctrl; 1278 u32 ctrl;
1241 ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL); 1279
1280 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1281 reg += OMAP24XX_GPIO_CTRL;
1282 else if (cpu_is_omap44xx())
1283 reg += OMAP4_GPIO_CTRL;
1284 ctrl = __raw_readl(reg);
1242 /* Module is disabled, clocks are gated */ 1285 /* Module is disabled, clocks are gated */
1243 ctrl |= 1; 1286 ctrl |= 1;
1244 __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL); 1287 __raw_writel(ctrl, reg);
1245 } 1288 }
1246 } 1289 }
1247 _reset_gpio(bank, bank->chip.base + offset); 1290 _reset_gpio(bank, bank->chip.base + offset);
@@ -1570,9 +1613,14 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
1570 reg += OMAP7XX_GPIO_DIR_CONTROL; 1613 reg += OMAP7XX_GPIO_DIR_CONTROL;
1571 break; 1614 break;
1572 case METHOD_GPIO_24XX: 1615 case METHOD_GPIO_24XX:
1573 case METHOD_GPIO_44XX:
1574 reg += OMAP24XX_GPIO_OE; 1616 reg += OMAP24XX_GPIO_OE;
1575 break; 1617 break;
1618 case METHOD_GPIO_44XX:
1619 reg += OMAP4_GPIO_OE;
1620 break;
1621 default:
1622 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1623 return -EINVAL;
1576 } 1624 }
1577 return __raw_readl(reg) & mask; 1625 return __raw_readl(reg) & mask;
1578} 1626}
@@ -1845,7 +1893,8 @@ static int __init _omap_gpio_init(void)
1845 __raw_writel(0, bank->base + 1893 __raw_writel(0, bank->base +
1846 OMAP24XX_GPIO_CTRL); 1894 OMAP24XX_GPIO_CTRL);
1847 } 1895 }
1848 if (i < ARRAY_SIZE(non_wakeup_gpios)) 1896 if (cpu_is_omap24xx() &&
1897 i < ARRAY_SIZE(non_wakeup_gpios))
1849 bank->non_wakeup_gpios = non_wakeup_gpios[i]; 1898 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1850 gpio_count = 32; 1899 gpio_count = 32;
1851 } 1900 }
@@ -2028,16 +2077,27 @@ static struct sys_device omap_gpio_device = {
2028 2077
2029static int workaround_enabled; 2078static int workaround_enabled;
2030 2079
2031void omap2_gpio_prepare_for_retention(void) 2080void omap2_gpio_prepare_for_idle(int power_state)
2032{ 2081{
2033 int i, c = 0; 2082 int i, c = 0;
2083 int min = 0;
2034 2084
2035 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious 2085 if (cpu_is_omap34xx())
2036 * IRQs will be generated. See OMAP2420 Errata item 1.101. */ 2086 min = 1;
2037 for (i = 0; i < gpio_bank_count; i++) { 2087
2088 for (i = min; i < gpio_bank_count; i++) {
2038 struct gpio_bank *bank = &gpio_bank[i]; 2089 struct gpio_bank *bank = &gpio_bank[i];
2039 u32 l1, l2; 2090 u32 l1, l2;
2040 2091
2092 if (bank->dbck_enable_mask)
2093 clk_disable(bank->dbck);
2094
2095 if (power_state > PWRDM_POWER_OFF)
2096 continue;
2097
2098 /* If going to OFF, remove triggering for all
2099 * non-wakeup GPIOs. Otherwise spurious IRQs will be
2100 * generated. See OMAP2420 Errata item 1.101. */
2041 if (!(bank->enabled_non_wakeup_gpios)) 2101 if (!(bank->enabled_non_wakeup_gpios))
2042 continue; 2102 continue;
2043 2103
@@ -2085,16 +2145,23 @@ void omap2_gpio_prepare_for_retention(void)
2085 workaround_enabled = 1; 2145 workaround_enabled = 1;
2086} 2146}
2087 2147
2088void omap2_gpio_resume_after_retention(void) 2148void omap2_gpio_resume_after_idle(void)
2089{ 2149{
2090 int i; 2150 int i;
2151 int min = 0;
2091 2152
2092 if (!workaround_enabled) 2153 if (cpu_is_omap34xx())
2093 return; 2154 min = 1;
2094 for (i = 0; i < gpio_bank_count; i++) { 2155 for (i = min; i < gpio_bank_count; i++) {
2095 struct gpio_bank *bank = &gpio_bank[i]; 2156 struct gpio_bank *bank = &gpio_bank[i];
2096 u32 l, gen, gen0, gen1; 2157 u32 l, gen, gen0, gen1;
2097 2158
2159 if (bank->dbck_enable_mask)
2160 clk_enable(bank->dbck);
2161
2162 if (!workaround_enabled)
2163 continue;
2164
2098 if (!(bank->enabled_non_wakeup_gpios)) 2165 if (!(bank->enabled_non_wakeup_gpios))
2099 continue; 2166 continue;
2100 2167
@@ -2119,7 +2186,7 @@ void omap2_gpio_resume_after_retention(void)
2119 * horribly racy, but it's the best we can do to work around 2186 * horribly racy, but it's the best we can do to work around
2120 * this silicon bug. */ 2187 * this silicon bug. */
2121 l ^= bank->saved_datain; 2188 l ^= bank->saved_datain;
2122 l &= bank->non_wakeup_gpios; 2189 l &= bank->enabled_non_wakeup_gpios;
2123 2190
2124 /* 2191 /*
2125 * No need to generate IRQs for the rising edge for gpio IRQs 2192 * No need to generate IRQs for the rising edge for gpio IRQs
@@ -2207,10 +2274,6 @@ void omap_gpio_save_context(void)
2207 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); 2274 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2208 gpio_context[i].dataout = 2275 gpio_context[i].dataout =
2209 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT); 2276 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
2210 gpio_context[i].setwkuena =
2211 __raw_readl(bank->base + OMAP24XX_GPIO_SETWKUENA);
2212 gpio_context[i].setdataout =
2213 __raw_readl(bank->base + OMAP24XX_GPIO_SETDATAOUT);
2214 } 2277 }
2215} 2278}
2216 2279
@@ -2243,10 +2306,6 @@ void omap_gpio_restore_context(void)
2243 bank->base + OMAP24XX_GPIO_FALLINGDETECT); 2306 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2244 __raw_writel(gpio_context[i].dataout, 2307 __raw_writel(gpio_context[i].dataout,
2245 bank->base + OMAP24XX_GPIO_DATAOUT); 2308 bank->base + OMAP24XX_GPIO_DATAOUT);
2246 __raw_writel(gpio_context[i].setwkuena,
2247 bank->base + OMAP24XX_GPIO_SETWKUENA);
2248 __raw_writel(gpio_context[i].setdataout,
2249 bank->base + OMAP24XX_GPIO_SETDATAOUT);
2250 } 2309 }
2251} 2310}
2252#endif 2311#endif
@@ -2286,110 +2345,3 @@ static int __init omap_gpio_sysinit(void)
2286} 2345}
2287 2346
2288arch_initcall(omap_gpio_sysinit); 2347arch_initcall(omap_gpio_sysinit);
2289
2290
2291#ifdef CONFIG_DEBUG_FS
2292
2293#include <linux/debugfs.h>
2294#include <linux/seq_file.h>
2295
2296static int dbg_gpio_show(struct seq_file *s, void *unused)
2297{
2298 unsigned i, j, gpio;
2299
2300 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
2301 struct gpio_bank *bank = gpio_bank + i;
2302 unsigned bankwidth = 16;
2303 u32 mask = 1;
2304
2305 if (bank_is_mpuio(bank))
2306 gpio = OMAP_MPUIO(0);
2307 else if (cpu_class_is_omap2() || cpu_is_omap7xx())
2308 bankwidth = 32;
2309
2310 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
2311 unsigned irq, value, is_in, irqstat;
2312 const char *label;
2313
2314 label = gpiochip_is_requested(&bank->chip, j);
2315 if (!label)
2316 continue;
2317
2318 irq = bank->virtual_irq_start + j;
2319 value = gpio_get_value(gpio);
2320 is_in = gpio_is_input(bank, mask);
2321
2322 if (bank_is_mpuio(bank))
2323 seq_printf(s, "MPUIO %2d ", j);
2324 else
2325 seq_printf(s, "GPIO %3d ", gpio);
2326 seq_printf(s, "(%-20.20s): %s %s",
2327 label,
2328 is_in ? "in " : "out",
2329 value ? "hi" : "lo");
2330
2331/* FIXME for at least omap2, show pullup/pulldown state */
2332
2333 irqstat = irq_desc[irq].status;
2334#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2335 if (is_in && ((bank->suspend_wakeup & mask)
2336 || irqstat & IRQ_TYPE_SENSE_MASK)) {
2337 char *trigger = NULL;
2338
2339 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
2340 case IRQ_TYPE_EDGE_FALLING:
2341 trigger = "falling";
2342 break;
2343 case IRQ_TYPE_EDGE_RISING:
2344 trigger = "rising";
2345 break;
2346 case IRQ_TYPE_EDGE_BOTH:
2347 trigger = "bothedge";
2348 break;
2349 case IRQ_TYPE_LEVEL_LOW:
2350 trigger = "low";
2351 break;
2352 case IRQ_TYPE_LEVEL_HIGH:
2353 trigger = "high";
2354 break;
2355 case IRQ_TYPE_NONE:
2356 trigger = "(?)";
2357 break;
2358 }
2359 seq_printf(s, ", irq-%d %-8s%s",
2360 irq, trigger,
2361 (bank->suspend_wakeup & mask)
2362 ? " wakeup" : "");
2363 }
2364#endif
2365 seq_printf(s, "\n");
2366 }
2367
2368 if (bank_is_mpuio(bank)) {
2369 seq_printf(s, "\n");
2370 gpio = 0;
2371 }
2372 }
2373 return 0;
2374}
2375
2376static int dbg_gpio_open(struct inode *inode, struct file *file)
2377{
2378 return single_open(file, dbg_gpio_show, &inode->i_private);
2379}
2380
2381static const struct file_operations debug_fops = {
2382 .open = dbg_gpio_open,
2383 .read = seq_read,
2384 .llseek = seq_lseek,
2385 .release = single_release,
2386};
2387
2388static int __init omap_gpio_debuginit(void)
2389{
2390 (void) debugfs_create_file("omap_gpio", S_IRUGO,
2391 NULL, NULL, &debug_fops);
2392 return 0;
2393}
2394late_initcall(omap_gpio_debuginit);
2395#endif
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index f044b5927508..eec2b4993c69 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -38,6 +38,7 @@
38#define OMAP2_I2C_BASE1 0x48070000 38#define OMAP2_I2C_BASE1 0x48070000
39#define OMAP2_I2C_BASE2 0x48072000 39#define OMAP2_I2C_BASE2 0x48072000
40#define OMAP2_I2C_BASE3 0x48060000 40#define OMAP2_I2C_BASE3 0x48060000
41#define OMAP4_I2C_BASE4 0x48350000
41 42
42static const char name[] = "i2c_omap"; 43static const char name[] = "i2c_omap";
43 44
@@ -54,11 +55,14 @@ static const char name[] = "i2c_omap";
54 55
55static struct resource i2c_resources[][2] = { 56static struct resource i2c_resources[][2] = {
56 { I2C_RESOURCE_BUILDER(0, 0) }, 57 { I2C_RESOURCE_BUILDER(0, 0) },
57#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 58#if defined(CONFIG_ARCH_OMAP2PLUS)
58 { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, INT_24XX_I2C2_IRQ) }, 59 { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, 0) },
59#endif 60#endif
60#if defined(CONFIG_ARCH_OMAP3) 61#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
61 { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, INT_34XX_I2C3_IRQ) }, 62 { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, 0) },
63#endif
64#if defined(CONFIG_ARCH_OMAP4)
65 { I2C_RESOURCE_BUILDER(OMAP4_I2C_BASE4, 0) },
62#endif 66#endif
63}; 67};
64 68
@@ -76,12 +80,15 @@ static struct resource i2c_resources[][2] = {
76static struct omap_i2c_bus_platform_data i2c_pdata[ARRAY_SIZE(i2c_resources)]; 80static struct omap_i2c_bus_platform_data i2c_pdata[ARRAY_SIZE(i2c_resources)];
77static struct platform_device omap_i2c_devices[] = { 81static struct platform_device omap_i2c_devices[] = {
78 I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]), 82 I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]),
79#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 83#if defined(CONFIG_ARCH_OMAP2PLUS)
80 I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_pdata[1]), 84 I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_pdata[1]),
81#endif 85#endif
82#if defined(CONFIG_ARCH_OMAP3) 86#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
83 I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_pdata[2]), 87 I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_pdata[2]),
84#endif 88#endif
89#if defined(CONFIG_ARCH_OMAP4)
90 I2C_DEV_BUILDER(4, i2c_resources[3], &i2c_pdata[3]),
91#endif
85}; 92};
86 93
87#define OMAP_I2C_CMDLINE_SETUP (BIT(31)) 94#define OMAP_I2C_CMDLINE_SETUP (BIT(31))
@@ -96,37 +103,60 @@ static int __init omap_i2c_nr_ports(void)
96 ports = 2; 103 ports = 2;
97 else if (cpu_is_omap34xx()) 104 else if (cpu_is_omap34xx())
98 ports = 3; 105 ports = 3;
106 else if (cpu_is_omap44xx())
107 ports = 4;
99 108
100 return ports; 109 return ports;
101} 110}
102 111
103static int __init omap_i2c_add_bus(int bus_id) 112/* Shared between omap2 and 3 */
113static resource_size_t omap2_i2c_irq[3] __initdata = {
114 INT_24XX_I2C1_IRQ,
115 INT_24XX_I2C2_IRQ,
116 INT_34XX_I2C3_IRQ,
117};
118
119static resource_size_t omap4_i2c_irq[4] __initdata = {
120 OMAP44XX_IRQ_I2C1,
121 OMAP44XX_IRQ_I2C2,
122 OMAP44XX_IRQ_I2C3,
123 OMAP44XX_IRQ_I2C4,
124};
125
126static inline int omap1_i2c_add_bus(struct platform_device *pdev, int bus_id)
104{ 127{
105 struct platform_device *pdev;
106 struct omap_i2c_bus_platform_data *pd; 128 struct omap_i2c_bus_platform_data *pd;
107 struct resource *res; 129 struct resource *res;
108 resource_size_t base, irq;
109 130
110 pdev = &omap_i2c_devices[bus_id - 1];
111 pd = pdev->dev.platform_data; 131 pd = pdev->dev.platform_data;
132 res = pdev->resource;
133 res[0].start = OMAP1_I2C_BASE;
134 res[0].end = res[0].start + OMAP_I2C_SIZE;
135 res[1].start = INT_I2C;
136 omap1_i2c_mux_pins(bus_id);
137
138 return platform_device_register(pdev);
139}
140
141static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id)
142{
143 struct resource *res;
144 resource_size_t *irq;
145
146 res = pdev->resource;
147
148 if (!cpu_is_omap44xx())
149 irq = omap2_i2c_irq;
150 else
151 irq = omap4_i2c_irq;
152
112 if (bus_id == 1) { 153 if (bus_id == 1) {
113 res = pdev->resource; 154 res[0].start = OMAP2_I2C_BASE1;
114 if (cpu_class_is_omap1()) { 155 res[0].end = res[0].start + OMAP_I2C_SIZE;
115 base = OMAP1_I2C_BASE;
116 irq = INT_I2C;
117 } else {
118 base = OMAP2_I2C_BASE1;
119 irq = INT_24XX_I2C1_IRQ;
120 }
121 res[0].start = base;
122 res[0].end = base + OMAP_I2C_SIZE;
123 res[1].start = irq;
124 } 156 }
125 157
126 if (cpu_class_is_omap1()) 158 res[1].start = irq[bus_id - 1];
127 omap1_i2c_mux_pins(bus_id); 159 omap2_i2c_mux_pins(bus_id);
128 if (cpu_class_is_omap2())
129 omap2_i2c_mux_pins(bus_id);
130 160
131 /* 161 /*
132 * When waiting for completion of a i2c transfer, we need to 162 * When waiting for completion of a i2c transfer, we need to
@@ -134,12 +164,28 @@ static int __init omap_i2c_add_bus(int bus_id)
134 * ensure quick enough wakeup from idle, when transfer 164 * ensure quick enough wakeup from idle, when transfer
135 * completes. 165 * completes.
136 */ 166 */
137 if (cpu_is_omap34xx()) 167 if (cpu_is_omap34xx()) {
168 struct omap_i2c_bus_platform_data *pd;
169
170 pd = pdev->dev.platform_data;
138 pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat; 171 pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat;
172 }
139 173
140 return platform_device_register(pdev); 174 return platform_device_register(pdev);
141} 175}
142 176
177static int __init omap_i2c_add_bus(int bus_id)
178{
179 struct platform_device *pdev;
180
181 pdev = &omap_i2c_devices[bus_id - 1];
182
183 if (cpu_class_is_omap1())
184 return omap1_i2c_add_bus(pdev, bus_id);
185 else
186 return omap2_i2c_add_bus(pdev, bus_id);
187}
188
143/** 189/**
144 * omap_i2c_bus_setup - Process command line options for the I2C bus speed 190 * omap_i2c_bus_setup - Process command line options for the I2C bus speed
145 * @str: String of options 191 * @str: String of options
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 34f7fa9ad4c0..dfc472ca0cc4 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -196,15 +196,15 @@ extern struct clk dummy_ck;
196#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ 196#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
197 197
198/* Clksel_rate flags */ 198/* Clksel_rate flags */
199#define DEFAULT_RATE (1 << 0) 199#define RATE_IN_242X (1 << 0)
200#define RATE_IN_242X (1 << 1) 200#define RATE_IN_243X (1 << 1)
201#define RATE_IN_243X (1 << 2) 201#define RATE_IN_3XXX (1 << 2) /* rates common to all OMAP3 */
202#define RATE_IN_343X (1 << 3) /* rates common to all 343X */ 202#define RATE_IN_3430ES2 (1 << 3) /* 3430ES2 rates only */
203#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ 203#define RATE_IN_36XX (1 << 4)
204#define RATE_IN_36XX (1 << 5) 204#define RATE_IN_4430 (1 << 5)
205#define RATE_IN_4430 (1 << 6)
206 205
207#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) 206#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
208 207
208#define RATE_IN_3430ES2PLUS (RATE_IN_3430ES2 | RATE_IN_36XX)
209 209
210#endif 210#endif
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 7556e271942e..d265018f5e6b 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -31,9 +31,6 @@
31 31
32struct sys_timer; 32struct sys_timer;
33 33
34/* used by omap-smp.c and board-4430sdp.c */
35extern void __iomem *gic_cpu_base_addr;
36
37extern void omap_map_common_io(void); 34extern void omap_map_common_io(void);
38extern struct sys_timer omap_timer; 35extern struct sys_timer omap_timer;
39 36
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
index a56deee97676..131bf405c2f6 100644
--- a/arch/arm/plat-omap/include/plat/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -207,6 +207,9 @@
207/* 44xx control status register offset */ 207/* 44xx control status register offset */
208#define OMAP44XX_CONTROL_STATUS 0x2c4 208#define OMAP44XX_CONTROL_STATUS 0x2c4
209 209
210/* 44xx-only CONTROL_GENERAL register offsets */
211#define OMAP44XX_CONTROL_MMC1 0x628
212#define OMAP44XX_CONTROL_PBIAS_LITE 0x600
210/* 213/*
211 * REVISIT: This list of registers is not comprehensive - there are more 214 * REVISIT: This list of registers is not comprehensive - there are more
212 * that should be added. 215 * that should be added.
@@ -252,6 +255,23 @@
252#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) 255#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
253#define OMAP2_PBIASLITEVMODE0 (1 << 0) 256#define OMAP2_PBIASLITEVMODE0 (1 << 0)
254 257
258/* CONTROL_PBIAS_LITE bits for OMAP4 */
259#define OMAP4_MMC1_PWRDNZ (1 << 26)
260#define OMAP4_MMC1_PBIASLITE_HIZ_MODE (1 << 25)
261#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT (1 << 24)
262#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR (1 << 23)
263#define OMAP4_MMC1_PBIASLITE_PWRDNZ (1 << 22)
264#define OMAP4_MMC1_PBIASLITE_VMODE (1 << 21)
265#define OMAP4_USBC1_ICUSB_PWRDNZ (1 << 20)
266
267#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 (1 << 31)
268#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1 (1 << 30)
269#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 (1 << 29)
270#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3 (1 << 28)
271#define OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL (1 << 27)
272#define OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL (1 << 26)
273#define OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL (1 << 25)
274
255/* CONTROL_PROG_IO1 bits */ 275/* CONTROL_PROG_IO1 bits */
256#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) 276#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
257 277
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index de7c54731cbe..de1c604962eb 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -72,8 +72,8 @@
72 IH_GPIO_BASE + (nr)) 72 IH_GPIO_BASE + (nr))
73 73
74extern int omap_gpio_init(void); /* Call from board init only */ 74extern int omap_gpio_init(void); /* Call from board init only */
75extern void omap2_gpio_prepare_for_retention(void); 75extern void omap2_gpio_prepare_for_idle(int power_state);
76extern void omap2_gpio_resume_after_retention(void); 76extern void omap2_gpio_resume_after_idle(void);
77extern void omap_set_gpio_debounce(int gpio, int enable); 77extern void omap_set_gpio_debounce(int gpio, int enable);
78extern void omap_set_gpio_debounce_time(int gpio, int enable); 78extern void omap_set_gpio_debounce_time(int gpio, int enable);
79extern void omap_gpio_save_context(void); 79extern void omap_gpio_save_context(void);
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 401701977dbb..c01d9f08a198 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -428,4 +428,8 @@ void omap3_intc_resume_idle(void);
428 428
429#include <mach/hardware.h> 429#include <mach/hardware.h>
430 430
431#ifdef CONFIG_FIQ
432#define FIQ_START 1024
433#endif
434
431#endif 435#endif
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index a1bac07c89eb..c835f1e994c6 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -102,6 +102,10 @@ struct omap_mmc_platform_data {
102 /* Regulator off remapped to sleep */ 102 /* Regulator off remapped to sleep */
103 unsigned vcc_aux_disable_is_sleep:1; 103 unsigned vcc_aux_disable_is_sleep:1;
104 104
105 /* we can put the features above into this variable */
106#define HSMMC_HAS_PBIAS (1 << 0)
107 unsigned features;
108
105 int switch_pin; /* gpio (card detect) */ 109 int switch_pin; /* gpio (card detect) */
106 int gpio_wp; /* gpio (write protect) */ 110 int gpio_wp; /* gpio (write protect) */
107 111
diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
index f235d32cd942..ffd909fa5287 100644
--- a/arch/arm/plat-omap/include/plat/multi.h
+++ b/arch/arm/plat-omap/include/plat/multi.h
@@ -61,9 +61,9 @@
61# define OMAP_NAME omap16xx 61# define OMAP_NAME omap16xx
62# endif 62# endif
63#endif 63#endif
64#if (defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)) 64#ifdef CONFIG_ARCH_OMAP2PLUS
65# if (defined(OMAP_NAME) || defined(MULTI_OMAP1)) 65# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
66# error "OMAP1 and OMAP2 can't be selected at the same time" 66# error "OMAP1 and OMAP2PLUS can't be selected at the same time"
67# endif 67# endif
68#endif 68#endif
69#ifdef CONFIG_ARCH_OMAP2420 69#ifdef CONFIG_ARCH_OMAP2420
@@ -82,12 +82,20 @@
82# define OMAP_NAME omap2430 82# define OMAP_NAME omap2430
83# endif 83# endif
84#endif 84#endif
85#ifdef CONFIG_ARCH_OMAP3430 85#ifdef CONFIG_ARCH_OMAP3
86# ifdef OMAP_NAME 86# ifdef OMAP_NAME
87# undef MULTI_OMAP2 87# undef MULTI_OMAP2
88# define MULTI_OMAP2 88# define MULTI_OMAP2
89# else 89# else
90# define OMAP_NAME omap3430 90# define OMAP_NAME omap3
91# endif
92#endif
93#ifdef CONFIG_ARCH_OMAP4
94# ifdef OMAP_NAME
95# undef MULTI_OMAP2
96# define MULTI_OMAP2
97# else
98# define OMAP_NAME omap4
91# endif 99# endif
92#endif 100#endif
93 101
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index b3ef1a7f53cc..8b3f12ff5cbc 100644
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -30,6 +30,7 @@
30#define OMAP4430_CM_BASE OMAP4430_CM1_BASE 30#define OMAP4430_CM_BASE OMAP4430_CM1_BASE
31#define OMAP4430_CM2_BASE 0x4a008000 31#define OMAP4430_CM2_BASE 0x4a008000
32#define OMAP4430_PRM_BASE 0x4a306000 32#define OMAP4430_PRM_BASE 0x4a306000
33#define OMAP4430_PRCM_MPU_BASE 0x48243000
33#define OMAP44XX_GPMC_BASE 0x50000000 34#define OMAP44XX_GPMC_BASE 0x50000000
34#define OMAP443X_SCM_BASE 0x4a002000 35#define OMAP443X_SCM_BASE 0x4a002000
35#define OMAP443X_CTRL_BASE 0x4a100000 36#define OMAP443X_CTRL_BASE 0x4a100000
@@ -48,5 +49,8 @@
48#define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000) 49#define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000)
49#define OMAP44XX_HSUSB_OTG_BASE (L4_44XX_BASE + 0xAB000) 50#define OMAP44XX_HSUSB_OTG_BASE (L4_44XX_BASE + 0xAB000)
50 51
52#define OMAP4_MMU1_BASE 0x55082000
53#define OMAP4_MMU2_BASE 0x4A066000
54
51#endif /* __ASM_ARCH_OMAP44XX_H */ 55#endif /* __ASM_ARCH_OMAP44XX_H */
52 56
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 36d6ea56ab51..0eccc09ac4a9 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -176,9 +176,8 @@ struct omap_hwmod_addr_space {
176#define OCP_USER_SDMA (1 << 1) 176#define OCP_USER_SDMA (1 << 1)
177 177
178/* omap_hwmod_ocp_if.flags bits */ 178/* omap_hwmod_ocp_if.flags bits */
179#define OCPIF_HAS_IDLEST (1 << 0) 179#define OCPIF_SWSUP_IDLE (1 << 0)
180#define OCPIF_SWSUP_IDLE (1 << 1) 180#define OCPIF_CAN_BURST (1 << 1)
181#define OCPIF_CAN_BURST (1 << 2)
182 181
183/** 182/**
184 * struct omap_hwmod_ocp_if - OCP interface data 183 * struct omap_hwmod_ocp_if - OCP interface data
@@ -327,14 +326,12 @@ struct omap_hwmod_omap2_prcm {
327 326
328/** 327/**
329 * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data 328 * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
330 * @module_offs: PRCM submodule offset from the start of the PRM/CM1/CM2 329 * @clkctrl_reg: PRCM address of the clock control register
331 * @device_offs: device register offset from @module_offs
332 * @submodule_wkdep_bit: bit shift of the WKDEP range 330 * @submodule_wkdep_bit: bit shift of the WKDEP range
333 */ 331 */
334struct omap_hwmod_omap4_prcm { 332struct omap_hwmod_omap4_prcm {
335 u32 module_offs; 333 void __iomem *clkctrl_reg;
336 u16 device_offs; 334 u8 submodule_wkdep_bit;
337 u8 submodule_wkdep_bit;
338}; 335};
339 336
340 337
@@ -353,6 +350,8 @@ struct omap_hwmod_omap4_prcm {
353 * when module is enabled, rather than the default, which is to 350 * when module is enabled, rather than the default, which is to
354 * enable autoidle 351 * enable autoidle
355 * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup 352 * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
353 * HWMOD_NO_IDLEST : this module does not have idle status - this is the case
354 * only for few initiator modules on OMAP2 & 3.
356 */ 355 */
357#define HWMOD_SWSUP_SIDLE (1 << 0) 356#define HWMOD_SWSUP_SIDLE (1 << 0)
358#define HWMOD_SWSUP_MSTANDBY (1 << 1) 357#define HWMOD_SWSUP_MSTANDBY (1 << 1)
@@ -360,6 +359,7 @@ struct omap_hwmod_omap4_prcm {
360#define HWMOD_INIT_NO_IDLE (1 << 3) 359#define HWMOD_INIT_NO_IDLE (1 << 3)
361#define HWMOD_NO_OCP_AUTOIDLE (1 << 4) 360#define HWMOD_NO_OCP_AUTOIDLE (1 << 4)
362#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5) 361#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5)
362#define HWMOD_NO_IDLEST (1 << 6)
363 363
364/* 364/*
365 * omap_hwmod._int_flags definitions 365 * omap_hwmod._int_flags definitions
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index d82b2c00d4f1..fb6ec74fe39e 100644
--- a/arch/arm/plat-omap/include/plat/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -31,6 +31,7 @@
31#define PWRDM_MAX_PWRSTS 4 31#define PWRDM_MAX_PWRSTS 4
32 32
33/* Powerdomain allowable state bitfields */ 33/* Powerdomain allowable state bitfields */
34#define PWRSTS_ON (1 << PWRDM_POWER_ON)
34#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ 35#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
35 (1 << PWRDM_POWER_ON)) 36 (1 << PWRDM_POWER_ON))
36 37
@@ -49,6 +50,12 @@
49 * in MEM bank 1 position. This is 50 * in MEM bank 1 position. This is
50 * true for OMAP3430 51 * true for OMAP3430
51 */ 52 */
53#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /*
54 * support to transition from a
55 * sleep state to a lower sleep
56 * state without waking up the
57 * powerdomain
58 */
52 59
53/* 60/*
54 * Number of memory banks that are power-controllable. On OMAP4430, the 61 * Number of memory banks that are power-controllable. On OMAP4430, the
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index 83dce4c4f7e6..19145f5c32ba 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -15,6 +15,20 @@
15 15
16#include <linux/init.h> 16#include <linux/init.h>
17 17
18/*
19 * Memory entry used for the DEBUG_LL UART configuration. See also
20 * uncompress.h and debug-macro.S.
21 *
22 * Note that using a memory location for storing the UART configuration
23 * has at least two limitations:
24 *
25 * 1. Kernel uncompress code cannot overlap OMAP_UART_INFO as the
26 * uncompress code could then partially overwrite itself
27 * 2. We assume printascii is called at least once before paging_init,
28 * and addruart has a chance to read OMAP_UART_INFO
29 */
30#define OMAP_UART_INFO (PHYS_OFFSET + 0x3ffc)
31
18/* OMAP1 serial ports */ 32/* OMAP1 serial ports */
19#define OMAP1_UART1_BASE 0xfffb0000 33#define OMAP1_UART1_BASE 0xfffb0000
20#define OMAP1_UART2_BASE 0xfffb0800 34#define OMAP1_UART2_BASE 0xfffb0800
@@ -39,7 +53,7 @@
39 53
40/* External port on Zoom2/3 */ 54/* External port on Zoom2/3 */
41#define ZOOM_UART_BASE 0x10000000 55#define ZOOM_UART_BASE 0x10000000
42#define ZOOM_UART_VIRT 0xfb000000 56#define ZOOM_UART_VIRT 0xfa400000
43 57
44#define OMAP_PORT_SHIFT 2 58#define OMAP_PORT_SHIFT 2
45#define OMAP7XX_PORT_SHIFT 0 59#define OMAP7XX_PORT_SHIFT 0
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 81d9ec540fcf..bbedd71943f6 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -20,27 +20,21 @@
20#include <linux/types.h> 20#include <linux/types.h>
21#include <linux/serial_reg.h> 21#include <linux/serial_reg.h>
22 22
23#include <asm/memory.h>
23#include <asm/mach-types.h> 24#include <asm/mach-types.h>
24 25
25#include <plat/serial.h> 26#include <plat/serial.h>
26 27
27static volatile u8 *uart1_base;
28static int uart1_shift;
29
30static volatile u8 *uart_base; 28static volatile u8 *uart_base;
31static int uart_shift; 29static int uart_shift;
32 30
33/* 31/*
34 * Store the DEBUG_LL uart number into UART1 scratchpad register. 32 * Store the DEBUG_LL uart number into memory.
35 * See also debug-macro.S, and serial.c for related code. 33 * See also debug-macro.S, and serial.c for related code.
36 *
37 * Please note that we currently assume that:
38 * - UART1 clocks are enabled for register access
39 * - UART1 scratchpad register can be used
40 */ 34 */
41static void set_uart1_scratchpad(unsigned char port) 35static void set_omap_uart_info(unsigned char port)
42{ 36{
43 uart1_base[UART_SCR << uart1_shift] = port; 37 *(volatile u32 *)OMAP_UART_INFO = port;
44} 38}
45 39
46static void putc(int c) 40static void putc(int c)
@@ -60,42 +54,38 @@ static inline void flush(void)
60/* 54/*
61 * Macros to configure UART1 and debug UART 55 * Macros to configure UART1 and debug UART
62 */ 56 */
63#define _DEBUG_LL_ENTRY(mach, uart1_phys, uart1_shft, \ 57#define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id) \
64 dbg_uart, dbg_shft, dbg_id) \
65 if (machine_is_##mach()) { \ 58 if (machine_is_##mach()) { \
66 uart1_base = (volatile u8 *)(uart1_phys); \
67 uart1_shift = (uart1_shft); \
68 uart_base = (volatile u8 *)(dbg_uart); \ 59 uart_base = (volatile u8 *)(dbg_uart); \
69 uart_shift = (dbg_shft); \ 60 uart_shift = (dbg_shft); \
70 port = (dbg_id); \ 61 port = (dbg_id); \
71 set_uart1_scratchpad(port); \ 62 set_omap_uart_info(port); \
72 break; \ 63 break; \
73 } 64 }
74 65
75#define DEBUG_LL_OMAP7XX(p, mach) \ 66#define DEBUG_LL_OMAP7XX(p, mach) \
76 _DEBUG_LL_ENTRY(mach, OMAP1_UART1_BASE, OMAP7XX_PORT_SHIFT, \ 67 _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, \
77 OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, OMAP1UART##p) 68 OMAP1UART##p)
78 69
79#define DEBUG_LL_OMAP1(p, mach) \ 70#define DEBUG_LL_OMAP1(p, mach) \
80 _DEBUG_LL_ENTRY(mach, OMAP1_UART1_BASE, OMAP_PORT_SHIFT, \ 71 _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT, \
81 OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP1UART##p) 72 OMAP1UART##p)
82 73
83#define DEBUG_LL_OMAP2(p, mach) \ 74#define DEBUG_LL_OMAP2(p, mach) \
84 _DEBUG_LL_ENTRY(mach, OMAP2_UART1_BASE, OMAP_PORT_SHIFT, \ 75 _DEBUG_LL_ENTRY(mach, OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT, \
85 OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP2UART##p) 76 OMAP2UART##p)
86 77
87#define DEBUG_LL_OMAP3(p, mach) \ 78#define DEBUG_LL_OMAP3(p, mach) \
88 _DEBUG_LL_ENTRY(mach, OMAP3_UART1_BASE, OMAP_PORT_SHIFT, \ 79 _DEBUG_LL_ENTRY(mach, OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT, \
89 OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP3UART##p) 80 OMAP3UART##p)
90 81
91#define DEBUG_LL_OMAP4(p, mach) \ 82#define DEBUG_LL_OMAP4(p, mach) \
92 _DEBUG_LL_ENTRY(mach, OMAP4_UART1_BASE, OMAP_PORT_SHIFT, \ 83 _DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, \
93 OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP4UART##p) 84 OMAP4UART##p)
94 85
95/* Zoom2/3 shift is different for UART1 and external port */ 86/* Zoom2/3 shift is different for UART1 and external port */
96#define DEBUG_LL_ZOOM(mach) \ 87#define DEBUG_LL_ZOOM(mach) \
97 _DEBUG_LL_ENTRY(mach, OMAP2_UART1_BASE, OMAP_PORT_SHIFT, \ 88 _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
98 ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
99 89
100static inline void __arch_decomp_setup(unsigned long arch_id) 90static inline void __arch_decomp_setup(unsigned long arch_id)
101{ 91{
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index 0e137663349c..bc094dbacee6 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -25,6 +25,11 @@
25 25
26#include "iopgtable.h" 26#include "iopgtable.h"
27 27
28#define for_each_iotlb_cr(obj, n, __i, cr) \
29 for (__i = 0; \
30 (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \
31 __i++)
32
28/* accommodate the difference between omap1 and omap2/3 */ 33/* accommodate the difference between omap1 and omap2/3 */
29static const struct iommu_functions *arch_iommu; 34static const struct iommu_functions *arch_iommu;
30 35
@@ -172,15 +177,12 @@ static void iotlb_lock_get(struct iommu *obj, struct iotlb_lock *l)
172 l->base = MMU_LOCK_BASE(val); 177 l->base = MMU_LOCK_BASE(val);
173 l->vict = MMU_LOCK_VICT(val); 178 l->vict = MMU_LOCK_VICT(val);
174 179
175 BUG_ON(l->base != 0); /* Currently no preservation is used */
176} 180}
177 181
178static void iotlb_lock_set(struct iommu *obj, struct iotlb_lock *l) 182static void iotlb_lock_set(struct iommu *obj, struct iotlb_lock *l)
179{ 183{
180 u32 val; 184 u32 val;
181 185
182 BUG_ON(l->base != 0); /* Currently no preservation is used */
183
184 val = (l->base << MMU_LOCK_BASE_SHIFT); 186 val = (l->base << MMU_LOCK_BASE_SHIFT);
185 val |= (l->vict << MMU_LOCK_VICT_SHIFT); 187 val |= (l->vict << MMU_LOCK_VICT_SHIFT);
186 188
@@ -214,6 +216,20 @@ static inline ssize_t iotlb_dump_cr(struct iommu *obj, struct cr_regs *cr,
214 return arch_iommu->dump_cr(obj, cr, buf); 216 return arch_iommu->dump_cr(obj, cr, buf);
215} 217}
216 218
219/* only used in iotlb iteration for-loop */
220static struct cr_regs __iotlb_read_cr(struct iommu *obj, int n)
221{
222 struct cr_regs cr;
223 struct iotlb_lock l;
224
225 iotlb_lock_get(obj, &l);
226 l.vict = n;
227 iotlb_lock_set(obj, &l);
228 iotlb_read_cr(obj, &cr);
229
230 return cr;
231}
232
217/** 233/**
218 * load_iotlb_entry - Set an iommu tlb entry 234 * load_iotlb_entry - Set an iommu tlb entry
219 * @obj: target iommu 235 * @obj: target iommu
@@ -221,7 +237,6 @@ static inline ssize_t iotlb_dump_cr(struct iommu *obj, struct cr_regs *cr,
221 **/ 237 **/
222int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e) 238int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e)
223{ 239{
224 int i;
225 int err = 0; 240 int err = 0;
226 struct iotlb_lock l; 241 struct iotlb_lock l;
227 struct cr_regs *cr; 242 struct cr_regs *cr;
@@ -231,21 +246,30 @@ int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e)
231 246
232 clk_enable(obj->clk); 247 clk_enable(obj->clk);
233 248
234 for (i = 0; i < obj->nr_tlb_entries; i++) { 249 iotlb_lock_get(obj, &l);
250 if (l.base == obj->nr_tlb_entries) {
251 dev_warn(obj->dev, "%s: preserve entries full\n", __func__);
252 err = -EBUSY;
253 goto out;
254 }
255 if (!e->prsvd) {
256 int i;
235 struct cr_regs tmp; 257 struct cr_regs tmp;
236 258
259 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp)
260 if (!iotlb_cr_valid(&tmp))
261 break;
262
263 if (i == obj->nr_tlb_entries) {
264 dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
265 err = -EBUSY;
266 goto out;
267 }
268
237 iotlb_lock_get(obj, &l); 269 iotlb_lock_get(obj, &l);
238 l.vict = i; 270 } else {
271 l.vict = l.base;
239 iotlb_lock_set(obj, &l); 272 iotlb_lock_set(obj, &l);
240 iotlb_read_cr(obj, &tmp);
241 if (!iotlb_cr_valid(&tmp))
242 break;
243 }
244
245 if (i == obj->nr_tlb_entries) {
246 dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
247 err = -EBUSY;
248 goto out;
249 } 273 }
250 274
251 cr = iotlb_alloc_cr(obj, e); 275 cr = iotlb_alloc_cr(obj, e);
@@ -257,9 +281,11 @@ int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e)
257 iotlb_load_cr(obj, cr); 281 iotlb_load_cr(obj, cr);
258 kfree(cr); 282 kfree(cr);
259 283
284 if (e->prsvd)
285 l.base++;
260 /* increment victim for next tlb load */ 286 /* increment victim for next tlb load */
261 if (++l.vict == obj->nr_tlb_entries) 287 if (++l.vict == obj->nr_tlb_entries)
262 l.vict = 0; 288 l.vict = l.base;
263 iotlb_lock_set(obj, &l); 289 iotlb_lock_set(obj, &l);
264out: 290out:
265 clk_disable(obj->clk); 291 clk_disable(obj->clk);
@@ -276,20 +302,15 @@ EXPORT_SYMBOL_GPL(load_iotlb_entry);
276 **/ 302 **/
277void flush_iotlb_page(struct iommu *obj, u32 da) 303void flush_iotlb_page(struct iommu *obj, u32 da)
278{ 304{
279 struct iotlb_lock l;
280 int i; 305 int i;
306 struct cr_regs cr;
281 307
282 clk_enable(obj->clk); 308 clk_enable(obj->clk);
283 309
284 for (i = 0; i < obj->nr_tlb_entries; i++) { 310 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) {
285 struct cr_regs cr;
286 u32 start; 311 u32 start;
287 size_t bytes; 312 size_t bytes;
288 313
289 iotlb_lock_get(obj, &l);
290 l.vict = i;
291 iotlb_lock_set(obj, &l);
292 iotlb_read_cr(obj, &cr);
293 if (!iotlb_cr_valid(&cr)) 314 if (!iotlb_cr_valid(&cr))
294 continue; 315 continue;
295 316
@@ -299,7 +320,6 @@ void flush_iotlb_page(struct iommu *obj, u32 da)
299 if ((start <= da) && (da < start + bytes)) { 320 if ((start <= da) && (da < start + bytes)) {
300 dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", 321 dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
301 __func__, start, da, bytes); 322 __func__, start, da, bytes);
302 iotlb_load_cr(obj, &cr);
303 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); 323 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
304 } 324 }
305 } 325 }
@@ -370,26 +390,19 @@ EXPORT_SYMBOL_GPL(iommu_dump_ctx);
370static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs, int num) 390static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs, int num)
371{ 391{
372 int i; 392 int i;
373 struct iotlb_lock saved, l; 393 struct iotlb_lock saved;
394 struct cr_regs tmp;
374 struct cr_regs *p = crs; 395 struct cr_regs *p = crs;
375 396
376 clk_enable(obj->clk); 397 clk_enable(obj->clk);
377
378 iotlb_lock_get(obj, &saved); 398 iotlb_lock_get(obj, &saved);
379 memcpy(&l, &saved, sizeof(saved));
380 399
381 for (i = 0; i < num; i++) { 400 for_each_iotlb_cr(obj, num, i, tmp) {
382 struct cr_regs tmp;
383
384 iotlb_lock_get(obj, &l);
385 l.vict = i;
386 iotlb_lock_set(obj, &l);
387 iotlb_read_cr(obj, &tmp);
388 if (!iotlb_cr_valid(&tmp)) 401 if (!iotlb_cr_valid(&tmp))
389 continue; 402 continue;
390
391 *p++ = tmp; 403 *p++ = tmp;
392 } 404 }
405
393 iotlb_lock_set(obj, &saved); 406 iotlb_lock_set(obj, &saved);
394 clk_disable(obj->clk); 407 clk_disable(obj->clk);
395 408
@@ -503,6 +516,12 @@ static int iopgd_alloc_section(struct iommu *obj, u32 da, u32 pa, u32 prot)
503{ 516{
504 u32 *iopgd = iopgd_offset(obj, da); 517 u32 *iopgd = iopgd_offset(obj, da);
505 518
519 if ((da | pa) & ~IOSECTION_MASK) {
520 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
521 __func__, da, pa, IOSECTION_SIZE);
522 return -EINVAL;
523 }
524
506 *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; 525 *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
507 flush_iopgd_range(iopgd, iopgd); 526 flush_iopgd_range(iopgd, iopgd);
508 return 0; 527 return 0;
@@ -513,6 +532,12 @@ static int iopgd_alloc_super(struct iommu *obj, u32 da, u32 pa, u32 prot)
513 u32 *iopgd = iopgd_offset(obj, da); 532 u32 *iopgd = iopgd_offset(obj, da);
514 int i; 533 int i;
515 534
535 if ((da | pa) & ~IOSUPER_MASK) {
536 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
537 __func__, da, pa, IOSUPER_SIZE);
538 return -EINVAL;
539 }
540
516 for (i = 0; i < 16; i++) 541 for (i = 0; i < 16; i++)
517 *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; 542 *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
518 flush_iopgd_range(iopgd, iopgd + 15); 543 flush_iopgd_range(iopgd, iopgd + 15);
@@ -542,6 +567,12 @@ static int iopte_alloc_large(struct iommu *obj, u32 da, u32 pa, u32 prot)
542 u32 *iopte = iopte_alloc(obj, iopgd, da); 567 u32 *iopte = iopte_alloc(obj, iopgd, da);
543 int i; 568 int i;
544 569
570 if ((da | pa) & ~IOLARGE_MASK) {
571 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
572 __func__, da, pa, IOLARGE_SIZE);
573 return -EINVAL;
574 }
575
545 if (IS_ERR(iopte)) 576 if (IS_ERR(iopte))
546 return PTR_ERR(iopte); 577 return PTR_ERR(iopte);
547 578
diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c
index 65c6d1ff7237..e43983ba59c5 100644
--- a/arch/arm/plat-omap/iovmm.c
+++ b/arch/arm/plat-omap/iovmm.c
@@ -287,16 +287,19 @@ static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da,
287 prev_end = 0; 287 prev_end = 0;
288 list_for_each_entry(tmp, &obj->mmap, list) { 288 list_for_each_entry(tmp, &obj->mmap, list) {
289 289
290 if ((prev_end <= start) && (start + bytes < tmp->da_start)) 290 if (prev_end >= start)
291 break;
292
293 if (start + bytes < tmp->da_start)
291 goto found; 294 goto found;
292 295
293 if (flags & IOVMF_DA_ANON) 296 if (flags & IOVMF_DA_ANON)
294 start = roundup(tmp->da_end, alignement); 297 start = roundup(tmp->da_end + 1, alignement);
295 298
296 prev_end = tmp->da_end; 299 prev_end = tmp->da_end;
297 } 300 }
298 301
299 if ((start >= prev_end) && (ULONG_MAX - start >= bytes)) 302 if ((start > prev_end) && (ULONG_MAX - start >= bytes))
300 goto found; 303 goto found;
301 304
302 dev_dbg(obj->dev, "%s: no space to fit %08x(%x) flags: %08x\n", 305 dev_dbg(obj->dev, "%s: no space to fit %08x(%x) flags: %08x\n",
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 0f5197479513..f899603051ac 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -2,10 +2,10 @@
2 * omap_device implementation 2 * omap_device implementation
3 * 3 *
4 * Copyright (C) 2009 Nokia Corporation 4 * Copyright (C) 2009 Nokia Corporation
5 * Paul Walmsley 5 * Paul Walmsley, Kevin Hilman
6 * 6 *
7 * Developed in collaboration with (alphabetical order): Benoit 7 * Developed in collaboration with (alphabetical order): Benoit
8 * Cousson, Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram 8 * Cousson, Thara Gopinath, Tony Lindgren, Rajendra Nayak, Vikram
9 * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard 9 * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard
10 * Woodruff 10 * Woodruff
11 * 11 *
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 51f4dfb82e2b..226b2e858d6c 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -437,6 +437,20 @@ static inline int omap34xx_sram_init(void)
437} 437}
438#endif 438#endif
439 439
440#ifdef CONFIG_ARCH_OMAP4
441int __init omap44xx_sram_init(void)
442{
443 printk(KERN_ERR "FIXME: %s not implemented\n", __func__);
444
445 return -ENODEV;
446}
447#else
448static inline int omap44xx_sram_init(void)
449{
450 return 0;
451}
452#endif
453
440int __init omap_sram_init(void) 454int __init omap_sram_init(void)
441{ 455{
442 omap_detect_sram(); 456 omap_detect_sram();
@@ -451,7 +465,7 @@ int __init omap_sram_init(void)
451 else if (cpu_is_omap34xx()) 465 else if (cpu_is_omap34xx())
452 omap34xx_sram_init(); 466 omap34xx_sram_init();
453 else if (cpu_is_omap44xx()) 467 else if (cpu_is_omap44xx())
454 omap34xx_sram_init(); /* FIXME: */ 468 omap44xx_sram_init();
455 469
456 return 0; 470 return 0;
457} 471}
diff --git a/drivers/input/serio/Kconfig b/drivers/input/serio/Kconfig
index 7e319d65ec57..f34f1dbeb577 100644
--- a/drivers/input/serio/Kconfig
+++ b/drivers/input/serio/Kconfig
@@ -209,4 +209,20 @@ config SERIO_ALTERA_PS2
209 To compile this driver as a module, choose M here: the 209 To compile this driver as a module, choose M here: the
210 module will be called altera_ps2. 210 module will be called altera_ps2.
211 211
212config SERIO_AMS_DELTA
213 tristate "Amstrad Delta (E3) mailboard support"
214 depends on MACH_AMS_DELTA
215 default y
216 select AMS_DELTA_FIQ
217 ---help---
218 Say Y here if you have an E3 and want to use its mailboard,
219 or any standard AT keyboard connected to the mailboard port.
220
221 When used for the E3 mailboard, a non-standard key table
222 must be loaded from userspace, possibly using udev extras
223 provided keymap helper utility.
224
225 To compile this driver as a module, choose M here;
226 the module will be called ams_delta_serio.
227
212endif 228endif
diff --git a/drivers/input/serio/Makefile b/drivers/input/serio/Makefile
index bf945f789d05..84c80bf7185e 100644
--- a/drivers/input/serio/Makefile
+++ b/drivers/input/serio/Makefile
@@ -21,5 +21,6 @@ obj-$(CONFIG_SERIO_PCIPS2) += pcips2.o
21obj-$(CONFIG_SERIO_MACEPS2) += maceps2.o 21obj-$(CONFIG_SERIO_MACEPS2) += maceps2.o
22obj-$(CONFIG_SERIO_LIBPS2) += libps2.o 22obj-$(CONFIG_SERIO_LIBPS2) += libps2.o
23obj-$(CONFIG_SERIO_RAW) += serio_raw.o 23obj-$(CONFIG_SERIO_RAW) += serio_raw.o
24obj-$(CONFIG_SERIO_AMS_DELTA) += ams_delta_serio.o
24obj-$(CONFIG_SERIO_XILINX_XPS_PS2) += xilinx_ps2.o 25obj-$(CONFIG_SERIO_XILINX_XPS_PS2) += xilinx_ps2.o
25obj-$(CONFIG_SERIO_ALTERA_PS2) += altera_ps2.o 26obj-$(CONFIG_SERIO_ALTERA_PS2) += altera_ps2.o
diff --git a/drivers/input/serio/ams_delta_serio.c b/drivers/input/serio/ams_delta_serio.c
new file mode 100644
index 000000000000..8f1770e1e08b
--- /dev/null
+++ b/drivers/input/serio/ams_delta_serio.c
@@ -0,0 +1,177 @@
1/*
2 * Amstrad E3 (Delta) keyboard port driver
3 *
4 * Copyright (c) 2006 Matt Callow
5 * Copyright (c) 2010 Janusz Krzysztofik
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * Thanks to Cliff Lawson for his help
12 *
13 * The Amstrad Delta keyboard (aka mailboard) uses normal PC-AT style serial
14 * transmission. The keyboard port is formed of two GPIO lines, for clock
15 * and data. Due to strict timing requirements of the interface,
16 * the serial data stream is read and processed by a FIQ handler.
17 * The resulting words are fetched by this driver from a circular buffer.
18 *
19 * Standard AT keyboard driver (atkbd) is used for handling the keyboard data.
20 * However, when used with the E3 mailboard that producecs non-standard
21 * scancodes, a custom key table must be prepared and loaded from userspace.
22 */
23#include <linux/gpio.h>
24#include <linux/irq.h>
25#include <linux/serio.h>
26#include <linux/slab.h>
27
28#include <asm/mach-types.h>
29#include <plat/board-ams-delta.h>
30
31#include <mach/ams-delta-fiq.h>
32
33MODULE_AUTHOR("Matt Callow");
34MODULE_DESCRIPTION("AMS Delta (E3) keyboard port driver");
35MODULE_LICENSE("GPL");
36
37static struct serio *ams_delta_serio;
38
39static int check_data(int data)
40{
41 int i, parity = 0;
42
43 /* check valid stop bit */
44 if (!(data & 0x400)) {
45 dev_warn(&ams_delta_serio->dev,
46 "invalid stop bit, data=0x%X\n",
47 data);
48 return SERIO_FRAME;
49 }
50 /* calculate the parity */
51 for (i = 1; i < 10; i++) {
52 if (data & (1 << i))
53 parity++;
54 }
55 /* it should be odd */
56 if (!(parity & 0x01)) {
57 dev_warn(&ams_delta_serio->dev,
58 "paritiy check failed, data=0x%X parity=0x%X\n",
59 data, parity);
60 return SERIO_PARITY;
61 }
62 return 0;
63}
64
65static irqreturn_t ams_delta_serio_interrupt(int irq, void *dev_id)
66{
67 int *circ_buff = &fiq_buffer[FIQ_CIRC_BUFF];
68 int data, dfl;
69 u8 scancode;
70
71 fiq_buffer[FIQ_IRQ_PEND] = 0;
72
73 /*
74 * Read data from the circular buffer, check it
75 * and then pass it on the serio
76 */
77 while (fiq_buffer[FIQ_KEYS_CNT] > 0) {
78
79 data = circ_buff[fiq_buffer[FIQ_HEAD_OFFSET]++];
80 fiq_buffer[FIQ_KEYS_CNT]--;
81 if (fiq_buffer[FIQ_HEAD_OFFSET] == fiq_buffer[FIQ_BUF_LEN])
82 fiq_buffer[FIQ_HEAD_OFFSET] = 0;
83
84 dfl = check_data(data);
85 scancode = (u8) (data >> 1) & 0xFF;
86 serio_interrupt(ams_delta_serio, scancode, dfl);
87 }
88 return IRQ_HANDLED;
89}
90
91static int ams_delta_serio_open(struct serio *serio)
92{
93 /* enable keyboard */
94 ams_delta_latch2_write(AMD_DELTA_LATCH2_KEYBRD_PWR,
95 AMD_DELTA_LATCH2_KEYBRD_PWR);
96
97 return 0;
98}
99
100static void ams_delta_serio_close(struct serio *serio)
101{
102 /* disable keyboard */
103 ams_delta_latch2_write(AMD_DELTA_LATCH2_KEYBRD_PWR, 0);
104}
105
106static int __init ams_delta_serio_init(void)
107{
108 int err;
109
110 if (!machine_is_ams_delta())
111 return -ENODEV;
112
113 ams_delta_serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
114 if (!ams_delta_serio)
115 return -ENOMEM;
116
117 ams_delta_serio->id.type = SERIO_8042;
118 ams_delta_serio->open = ams_delta_serio_open;
119 ams_delta_serio->close = ams_delta_serio_close;
120 strlcpy(ams_delta_serio->name, "AMS DELTA keyboard adapter",
121 sizeof(ams_delta_serio->name));
122 strlcpy(ams_delta_serio->phys, "GPIO/serio0",
123 sizeof(ams_delta_serio->phys));
124
125 err = gpio_request(AMS_DELTA_GPIO_PIN_KEYBRD_DATA, "serio-data");
126 if (err) {
127 pr_err("ams_delta_serio: Couldn't request gpio pin for data\n");
128 goto serio;
129 }
130 gpio_direction_input(AMS_DELTA_GPIO_PIN_KEYBRD_DATA);
131
132 err = gpio_request(AMS_DELTA_GPIO_PIN_KEYBRD_CLK, "serio-clock");
133 if (err) {
134 pr_err("ams_delta_serio: couldn't request gpio pin for clock\n");
135 goto gpio_data;
136 }
137 gpio_direction_input(AMS_DELTA_GPIO_PIN_KEYBRD_CLK);
138
139 err = request_irq(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK),
140 ams_delta_serio_interrupt, IRQ_TYPE_EDGE_RISING,
141 "ams-delta-serio", 0);
142 if (err < 0) {
143 pr_err("ams_delta_serio: couldn't request gpio interrupt %d\n",
144 gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK));
145 goto gpio_clk;
146 }
147 /*
148 * Since GPIO register handling for keyboard clock pin is performed
149 * at FIQ level, switch back from edge to simple interrupt handler
150 * to avoid bad interaction.
151 */
152 set_irq_handler(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK),
153 handle_simple_irq);
154
155 serio_register_port(ams_delta_serio);
156 dev_info(&ams_delta_serio->dev, "%s\n", ams_delta_serio->name);
157
158 return 0;
159gpio_clk:
160 gpio_free(AMS_DELTA_GPIO_PIN_KEYBRD_CLK);
161gpio_data:
162 gpio_free(AMS_DELTA_GPIO_PIN_KEYBRD_DATA);
163serio:
164 kfree(ams_delta_serio);
165 return err;
166}
167module_init(ams_delta_serio_init);
168
169static void __exit ams_delta_serio_exit(void)
170{
171 serio_unregister_port(ams_delta_serio);
172 free_irq(OMAP_GPIO_IRQ(AMS_DELTA_GPIO_PIN_KEYBRD_CLK), 0);
173 gpio_free(AMS_DELTA_GPIO_PIN_KEYBRD_CLK);
174 gpio_free(AMS_DELTA_GPIO_PIN_KEYBRD_DATA);
175 kfree(ams_delta_serio);
176}
177module_exit(ams_delta_serio_exit);
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index a191fa2be7c5..f950b6316949 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -180,10 +180,10 @@ config SPI_OMAP_UWIRE
180 This hooks up to the MicroWire controller on OMAP1 chips. 180 This hooks up to the MicroWire controller on OMAP1 chips.
181 181
182config SPI_OMAP24XX 182config SPI_OMAP24XX
183 tristate "McSPI driver for OMAP24xx/OMAP34xx" 183 tristate "McSPI driver for OMAP"
184 depends on ARCH_OMAP2 || ARCH_OMAP3 184 depends on ARCH_OMAP2PLUS
185 help 185 help
186 SPI master controller for OMAP24xx/OMAP34xx Multichannel SPI 186 SPI master controller for OMAP24XX and later Multichannel SPI
187 (McSPI) modules. 187 (McSPI) modules.
188 188
189config SPI_OMAP_100K 189config SPI_OMAP_100K
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-31 05:31:37 -0500