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authorMaciej W. Rozycki <macro@linux-mips.org>2005-07-01 12:10:40 -0400
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:31:35 -0400
commita5fc9c0bbee8b91025993a49a9176a88380aef3c (patch)
treee68ee45e852028ddde712abb18531777dba6e468
parent7d7ee221213609319401d1b9d6dc4bf22ab928ea (diff)
Use physical addresses at the interface level, letting drivers remap
them as appropriate. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/dec/ecc-berr.c14
-rw-r--r--arch/mips/dec/int-handler.S18
-rw-r--r--arch/mips/dec/kn01-berr.c9
-rw-r--r--arch/mips/dec/kn02-irq.c9
-rw-r--r--arch/mips/dec/kn02xa-berr.c11
-rw-r--r--arch/mips/dec/prom/identify.c28
-rw-r--r--arch/mips/dec/setup.c16
-rw-r--r--drivers/tc/tc.c80
-rw-r--r--drivers/tc/zs.c20
-rw-r--r--include/asm-mips/dec/ioasic_addrs.h3
-rw-r--r--include/asm-mips/dec/kn01.h14
-rw-r--r--include/asm-mips/dec/kn02.h14
-rw-r--r--include/asm-mips/dec/kn02xa.h22
-rw-r--r--include/asm-mips/dec/kn03.h13
-rw-r--r--include/asm-mips/dec/kn05.h3
-rw-r--r--include/asm-mips/dec/system.h18
-rw-r--r--include/asm-mips/dec/tc.h10
-rw-r--r--include/asm-mips/mach-dec/mc146818rtc.h11
18 files changed, 149 insertions, 164 deletions
diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c
index 8f3498aa43ab..cc24c5ed0c05 100644
--- a/arch/mips/dec/ecc-berr.c
+++ b/arch/mips/dec/ecc-berr.c
@@ -227,11 +227,11 @@ irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs)
227 */ 227 */
228static inline void dec_kn02_be_init(void) 228static inline void dec_kn02_be_init(void)
229{ 229{
230 volatile u32 *csr = (void *)KN02_CSR_BASE; 230 volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);
231 unsigned long flags; 231 unsigned long flags;
232 232
233 kn0x_erraddr = (void *)(KN02_SLOT_BASE + KN02_ERRADDR); 233 kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR);
234 kn0x_chksyn = (void *)(KN02_SLOT_BASE + KN02_CHKSYN); 234 kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN);
235 235
236 spin_lock_irqsave(&kn02_lock, flags); 236 spin_lock_irqsave(&kn02_lock, flags);
237 237
@@ -250,11 +250,11 @@ static inline void dec_kn02_be_init(void)
250 250
251static inline void dec_kn03_be_init(void) 251static inline void dec_kn03_be_init(void)
252{ 252{
253 volatile u32 *mcr = (void *)(KN03_SLOT_BASE + IOASIC_MCR); 253 volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR);
254 volatile u32 *mbcs = (void *)(KN4K_SLOT_BASE + KN4K_MB_CSR); 254 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
255 255
256 kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR); 256 kn0x_erraddr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_ERRADDR);
257 kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN); 257 kn0x_chksyn = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_CHKSYN);
258 258
259 /* 259 /*
260 * Set normal ECC detection and generation, enable ECC correction. 260 * Set normal ECC detection and generation, enable ECC correction.
diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S
index c89768d5c4e5..41fa372007bf 100644
--- a/arch/mips/dec/int-handler.S
+++ b/arch/mips/dec/int-handler.S
@@ -2,9 +2,9 @@
2 * arch/mips/dec/int-handler.S 2 * arch/mips/dec/int-handler.S
3 * 3 *
4 * Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen 4 * Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen
5 * Copyright (C) 2000, 2001, 2002, 2003 Maciej W. Rozycki 5 * Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki
6 * 6 *
7 * Written by Ralf Baechle and Andreas Busse, modified for DECStation 7 * Written by Ralf Baechle and Andreas Busse, modified for DECstation
8 * support by Paul Antoine and Harald Koerfgen. 8 * support by Paul Antoine and Harald Koerfgen.
9 * 9 *
10 * completly rewritten: 10 * completly rewritten:
@@ -14,11 +14,12 @@
14 * by Maciej W. Rozycki. 14 * by Maciej W. Rozycki.
15 */ 15 */
16#include <linux/config.h> 16#include <linux/config.h>
17
18#include <asm/addrspace.h>
17#include <asm/asm.h> 19#include <asm/asm.h>
18#include <asm/regdef.h>
19#include <asm/mipsregs.h> 20#include <asm/mipsregs.h>
21#include <asm/regdef.h>
20#include <asm/stackframe.h> 22#include <asm/stackframe.h>
21#include <asm/addrspace.h>
22 23
23#include <asm/dec/interrupts.h> 24#include <asm/dec/interrupts.h>
24#include <asm/dec/ioasic_addrs.h> 25#include <asm/dec/ioasic_addrs.h>
@@ -28,11 +29,14 @@
28#include <asm/dec/kn02xa.h> 29#include <asm/dec/kn02xa.h>
29#include <asm/dec/kn03.h> 30#include <asm/dec/kn03.h>
30 31
32#define KN02_CSR_BASE CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR)
33#define KN02XA_IOASIC_BASE CKSEG1ADDR(KN02XA_SLOT_BASE + IOASIC_IOCTL)
34#define KN03_IOASIC_BASE CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_IOCTL)
31 35
32 .text 36 .text
33 .set noreorder 37 .set noreorder
34/* 38/*
35 * decstation_handle_int: Interrupt handler for DECStations 39 * decstation_handle_int: Interrupt handler for DECstations
36 * 40 *
37 * We follow the model in the Indy interrupt code by David Miller, where he 41 * We follow the model in the Indy interrupt code by David Miller, where he
38 * says: a lot of complication here is taken away because: 42 * says: a lot of complication here is taken away because:
@@ -48,7 +52,7 @@
48 * 3) Linux only thinks in terms of all IRQs on or all IRQs 52 * 3) Linux only thinks in terms of all IRQs on or all IRQs
49 * off, nothing in between like BSD spl() brain-damage. 53 * off, nothing in between like BSD spl() brain-damage.
50 * 54 *
51 * Furthermore, the IRQs on the DECStations look basically (barring 55 * Furthermore, the IRQs on the DECstations look basically (barring
52 * software IRQs which we don't use at all) like... 56 * software IRQs which we don't use at all) like...
53 * 57 *
54 * DS2100/3100's, aka kn01, aka Pmax: 58 * DS2100/3100's, aka kn01, aka Pmax:
@@ -61,7 +65,7 @@
61 * 3 Lance Ethernet 65 * 3 Lance Ethernet
62 * 4 DZ11 serial 66 * 4 DZ11 serial
63 * 5 RTC 67 * 5 RTC
64 * 6 Memory Controller 68 * 6 Memory Controller & Video
65 * 7 FPU 69 * 7 FPU
66 * 70 *
67 * DS5000/200, aka kn02, aka 3max: 71 * DS5000/200, aka kn02, aka 3max:
diff --git a/arch/mips/dec/kn01-berr.c b/arch/mips/dec/kn01-berr.c
index 8ec7b30a90c1..b9271db9bc76 100644
--- a/arch/mips/dec/kn01-berr.c
+++ b/arch/mips/dec/kn01-berr.c
@@ -51,7 +51,7 @@ DEFINE_SPINLOCK(kn01_lock);
51 51
52static inline void dec_kn01_be_ack(void) 52static inline void dec_kn01_be_ack(void)
53{ 53{
54 volatile u16 *csr = (void *)(KN01_SLOT_BASE + KN01_CSR); 54 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
55 unsigned long flags; 55 unsigned long flags;
56 56
57 spin_lock_irqsave(&kn01_lock, flags); 57 spin_lock_irqsave(&kn01_lock, flags);
@@ -64,7 +64,8 @@ static inline void dec_kn01_be_ack(void)
64 64
65static int dec_kn01_be_backend(struct pt_regs *regs, int is_fixup, int invoker) 65static int dec_kn01_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
66{ 66{
67 volatile u32 *kn01_erraddr = (void *)(KN01_SLOT_BASE + KN01_ERRADDR); 67 volatile u32 *kn01_erraddr = (void *)CKSEG1ADDR(KN01_SLOT_BASE +
68 KN01_ERRADDR);
68 69
69 static const char excstr[] = "exception"; 70 static const char excstr[] = "exception";
70 static const char intstr[] = "interrupt"; 71 static const char intstr[] = "interrupt";
@@ -152,7 +153,7 @@ int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup)
152irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id, 153irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id,
153 struct pt_regs *regs) 154 struct pt_regs *regs)
154{ 155{
155 volatile u16 *csr = (void *)(KN01_SLOT_BASE + KN01_CSR); 156 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
156 int action; 157 int action;
157 158
158 if (!(*csr & KN01_CSR_MEMERR)) 159 if (!(*csr & KN01_CSR_MEMERR))
@@ -178,7 +179,7 @@ irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id,
178 179
179void __init dec_kn01_be_init(void) 180void __init dec_kn01_be_init(void)
180{ 181{
181 volatile u16 *csr = (void *)(KN01_SLOT_BASE + KN01_CSR); 182 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
182 unsigned long flags; 183 unsigned long flags;
183 184
184 spin_lock_irqsave(&kn01_lock, flags); 185 spin_lock_irqsave(&kn01_lock, flags);
diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c
index 644085e10403..898bed502a34 100644
--- a/arch/mips/dec/kn02-irq.c
+++ b/arch/mips/dec/kn02-irq.c
@@ -37,7 +37,8 @@ static int kn02_irq_base;
37 37
38static inline void unmask_kn02_irq(unsigned int irq) 38static inline void unmask_kn02_irq(unsigned int irq)
39{ 39{
40 volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; 40 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
41 KN02_CSR);
41 42
42 cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16)); 43 cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16));
43 *csr = cached_kn02_csr; 44 *csr = cached_kn02_csr;
@@ -45,7 +46,8 @@ static inline void unmask_kn02_irq(unsigned int irq)
45 46
46static inline void mask_kn02_irq(unsigned int irq) 47static inline void mask_kn02_irq(unsigned int irq)
47{ 48{
48 volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; 49 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
50 KN02_CSR);
49 51
50 cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16)); 52 cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16));
51 *csr = cached_kn02_csr; 53 *csr = cached_kn02_csr;
@@ -105,7 +107,8 @@ static struct hw_interrupt_type kn02_irq_type = {
105 107
106void __init init_kn02_irqs(int base) 108void __init init_kn02_irqs(int base)
107{ 109{
108 volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; 110 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
111 KN02_CSR);
109 unsigned long flags; 112 unsigned long flags;
110 int i; 113 int i;
111 114
diff --git a/arch/mips/dec/kn02xa-berr.c b/arch/mips/dec/kn02xa-berr.c
index c29909566628..6cd3f94f79fe 100644
--- a/arch/mips/dec/kn02xa-berr.c
+++ b/arch/mips/dec/kn02xa-berr.c
@@ -20,6 +20,7 @@
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/types.h> 21#include <linux/types.h>
22 22
23#include <asm/addrspace.h>
23#include <asm/system.h> 24#include <asm/system.h>
24#include <asm/traps.h> 25#include <asm/traps.h>
25 26
@@ -29,8 +30,8 @@
29 30
30static inline void dec_kn02xa_be_ack(void) 31static inline void dec_kn02xa_be_ack(void)
31{ 32{
32 volatile u32 *mer = (void *)KN02XA_MER; 33 volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER);
33 volatile u32 *mem_intr = (void *)KN02XA_MEM_INTR; 34 volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR);
34 35
35 *mer = KN02CA_MER_INTR; /* Clear errors; keep the ARC IRQ. */ 36 *mer = KN02CA_MER_INTR; /* Clear errors; keep the ARC IRQ. */
36 *mem_intr = 0; /* Any write clears the bus IRQ. */ 37 *mem_intr = 0; /* Any write clears the bus IRQ. */
@@ -40,8 +41,8 @@ static inline void dec_kn02xa_be_ack(void)
40static int dec_kn02xa_be_backend(struct pt_regs *regs, int is_fixup, 41static int dec_kn02xa_be_backend(struct pt_regs *regs, int is_fixup,
41 int invoker) 42 int invoker)
42{ 43{
43 volatile u32 *kn02xa_mer = (void *)KN02XA_MER; 44 volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER);
44 volatile u32 *kn02xa_ear = (void *)KN02XA_EAR; 45 volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR);
45 46
46 static const char excstr[] = "exception"; 47 static const char excstr[] = "exception";
47 static const char intstr[] = "interrupt"; 48 static const char intstr[] = "interrupt";
@@ -126,7 +127,7 @@ irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id,
126 127
127void __init dec_kn02xa_be_init(void) 128void __init dec_kn02xa_be_init(void)
128{ 129{
129 volatile u32 *mbcs = (void *)(KN4K_SLOT_BASE + KN4K_MB_CSR); 130 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
130 131
131 /* For KN04 we need to make sure EE (?) is enabled in the MB. */ 132 /* For KN04 we need to make sure EE (?) is enabled in the MB. */
132 if (current_cpu_data.cputype == CPU_R4000SC) 133 if (current_cpu_data.cputype == CPU_R4000SC)
diff --git a/arch/mips/dec/prom/identify.c b/arch/mips/dec/prom/identify.c
index 9380588cb15c..81d5e878ddce 100644
--- a/arch/mips/dec/prom/identify.c
+++ b/arch/mips/dec/prom/identify.c
@@ -2,7 +2,7 @@
2 * identify.c: machine identification code. 2 * identify.c: machine identification code.
3 * 3 *
4 * Copyright (C) 1998 Harald Koerfgen and Paul M. Antoine 4 * Copyright (C) 1998 Harald Koerfgen and Paul M. Antoine
5 * Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki 5 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
6 */ 6 */
7#include <linux/init.h> 7#include <linux/init.h>
8#include <linux/kernel.h> 8#include <linux/kernel.h>
@@ -12,6 +12,7 @@
12#include <linux/types.h> 12#include <linux/types.h>
13 13
14#include <asm/bootinfo.h> 14#include <asm/bootinfo.h>
15
15#include <asm/dec/ioasic.h> 16#include <asm/dec/ioasic.h>
16#include <asm/dec/ioasic_addrs.h> 17#include <asm/dec/ioasic_addrs.h>
17#include <asm/dec/kn01.h> 18#include <asm/dec/kn01.h>
@@ -21,6 +22,7 @@
21#include <asm/dec/kn03.h> 22#include <asm/dec/kn03.h>
22#include <asm/dec/kn230.h> 23#include <asm/dec/kn230.h>
23#include <asm/dec/prom.h> 24#include <asm/dec/prom.h>
25#include <asm/dec/system.h>
24 26
25#include "dectypes.h" 27#include "dectypes.h"
26 28
@@ -68,34 +70,44 @@ EXPORT_SYMBOL(dec_rtc_base);
68 70
69static inline void prom_init_kn01(void) 71static inline void prom_init_kn01(void)
70{ 72{
71 dec_rtc_base = (void *)KN01_RTC_BASE; 73 dec_kn_slot_base = KN01_SLOT_BASE;
72 dec_kn_slot_size = KN01_SLOT_SIZE; 74 dec_kn_slot_size = KN01_SLOT_SIZE;
75
76 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC);
73} 77}
74 78
75static inline void prom_init_kn230(void) 79static inline void prom_init_kn230(void)
76{ 80{
77 dec_rtc_base = (void *)KN01_RTC_BASE; 81 dec_kn_slot_base = KN01_SLOT_BASE;
78 dec_kn_slot_size = KN01_SLOT_SIZE; 82 dec_kn_slot_size = KN01_SLOT_SIZE;
83
84 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC);
79} 85}
80 86
81static inline void prom_init_kn02(void) 87static inline void prom_init_kn02(void)
82{ 88{
83 dec_rtc_base = (void *)KN02_RTC_BASE; 89 dec_kn_slot_base = KN02_SLOT_BASE;
84 dec_kn_slot_size = KN02_SLOT_SIZE; 90 dec_kn_slot_size = KN02_SLOT_SIZE;
91
92 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN02_RTC);
85} 93}
86 94
87static inline void prom_init_kn02xa(void) 95static inline void prom_init_kn02xa(void)
88{ 96{
89 ioasic_base = (void *)KN02XA_IOASIC_BASE; 97 dec_kn_slot_base = KN02XA_SLOT_BASE;
90 dec_rtc_base = (void *)KN02XA_RTC_BASE;
91 dec_kn_slot_size = IOASIC_SLOT_SIZE; 98 dec_kn_slot_size = IOASIC_SLOT_SIZE;
99
100 ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL);
101 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY);
92} 102}
93 103
94static inline void prom_init_kn03(void) 104static inline void prom_init_kn03(void)
95{ 105{
96 ioasic_base = (void *)KN03_IOASIC_BASE; 106 dec_kn_slot_base = KN03_SLOT_BASE;
97 dec_rtc_base = (void *)KN03_RTC_BASE;
98 dec_kn_slot_size = IOASIC_SLOT_SIZE; 107 dec_kn_slot_size = IOASIC_SLOT_SIZE;
108
109 ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL);
110 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY);
99} 111}
100 112
101 113
diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c
index f63fb9cd43c6..8861c3b22e4b 100644
--- a/arch/mips/dec/setup.c
+++ b/arch/mips/dec/setup.c
@@ -39,6 +39,7 @@
39#include <asm/dec/kn02ca.h> 39#include <asm/dec/kn02ca.h>
40#include <asm/dec/kn03.h> 40#include <asm/dec/kn03.h>
41#include <asm/dec/kn230.h> 41#include <asm/dec/kn230.h>
42#include <asm/dec/system.h>
42 43
43 44
44extern void dec_machine_restart(char *command); 45extern void dec_machine_restart(char *command);
@@ -48,10 +49,16 @@ extern irqreturn_t dec_intr_halt(int irq, void *dev_id, struct pt_regs *regs);
48 49
49extern asmlinkage void decstation_handle_int(void); 50extern asmlinkage void decstation_handle_int(void);
50 51
52unsigned long dec_kn_slot_base, dec_kn_slot_size;
53
54EXPORT_SYMBOL(dec_kn_slot_base);
55EXPORT_SYMBOL(dec_kn_slot_size);
56
51spinlock_t ioasic_ssr_lock; 57spinlock_t ioasic_ssr_lock;
52 58
53volatile u32 *ioasic_base; 59volatile u32 *ioasic_base;
54unsigned long dec_kn_slot_size; 60
61EXPORT_SYMBOL(ioasic_base);
55 62
56/* 63/*
57 * IRQ routing and priority tables. Priorites are set as follows: 64 * IRQ routing and priority tables. Priorites are set as follows:
@@ -78,6 +85,9 @@ unsigned long dec_kn_slot_size;
78int dec_interrupt[DEC_NR_INTS] = { 85int dec_interrupt[DEC_NR_INTS] = {
79 [0 ... DEC_NR_INTS - 1] = -1 86 [0 ... DEC_NR_INTS - 1] = -1
80}; 87};
88
89EXPORT_SYMBOL(dec_interrupt);
90
81int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = { 91int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
82 { { .i = ~0 }, { .p = dec_intr_unimplemented } }, 92 { { .i = ~0 }, { .p = dec_intr_unimplemented } },
83}; 93};
@@ -755,7 +765,3 @@ void __init arch_init_irq(void)
755 if (dec_interrupt[DEC_IRQ_HALT] >= 0) 765 if (dec_interrupt[DEC_IRQ_HALT] >= 0)
756 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq); 766 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
757} 767}
758
759EXPORT_SYMBOL(ioasic_base);
760EXPORT_SYMBOL(dec_kn_slot_size);
761EXPORT_SYMBOL(dec_interrupt);
diff --git a/drivers/tc/tc.c b/drivers/tc/tc.c
index d742c3a90b23..a0e5af638e0e 100644
--- a/drivers/tc/tc.c
+++ b/drivers/tc/tc.c
@@ -10,31 +10,29 @@
10 * Copyright (c) Harald Koerfgen, 1998 10 * Copyright (c) Harald Koerfgen, 1998
11 * Copyright (c) 2001, 2003, 2005 Maciej W. Rozycki 11 * Copyright (c) 2001, 2003, 2005 Maciej W. Rozycki
12 */ 12 */
13#include <linux/string.h>
14#include <linux/init.h> 13#include <linux/init.h>
15#include <linux/ioport.h>
16#include <linux/kernel.h> 14#include <linux/kernel.h>
17#include <linux/module.h> 15#include <linux/module.h>
16#include <linux/string.h>
17#include <linux/types.h>
18 18
19#include <asm/addrspace.h> 19#include <asm/addrspace.h>
20#include <asm/bug.h>
20#include <asm/errno.h> 21#include <asm/errno.h>
22#include <asm/io.h>
23#include <asm/paccess.h>
24
21#include <asm/dec/machtype.h> 25#include <asm/dec/machtype.h>
22#include <asm/dec/prom.h> 26#include <asm/dec/prom.h>
23#include <asm/dec/tcinfo.h> 27#include <asm/dec/tcinfo.h>
24#include <asm/dec/tcmodule.h> 28#include <asm/dec/tcmodule.h>
25#include <asm/dec/interrupts.h> 29#include <asm/dec/interrupts.h>
26#include <asm/paccess.h>
27#include <asm/ptrace.h>
28
29#define TC_DEBUG
30 30
31MODULE_LICENSE("GPL"); 31MODULE_LICENSE("GPL");
32slot_info tc_bus[MAX_SLOT]; 32slot_info tc_bus[MAX_SLOT];
33static int num_tcslots; 33static int num_tcslots;
34static tcinfo *info; 34static tcinfo *info;
35 35
36unsigned long system_base;
37
38/* 36/*
39 * Interface to the world. Read comment in include/asm-mips/tc.h. 37 * Interface to the world. Read comment in include/asm-mips/tc.h.
40 */ 38 */
@@ -97,13 +95,16 @@ unsigned long get_tc_speed(void)
97static void __init tc_probe(unsigned long startaddr, unsigned long size, 95static void __init tc_probe(unsigned long startaddr, unsigned long size,
98 int slots) 96 int slots)
99{ 97{
98 unsigned long slotaddr;
100 int i, slot, err; 99 int i, slot, err;
101 long offset; 100 long offset;
102 unsigned char pattern[4]; 101 u8 pattern[4];
103 unsigned char *module; 102 volatile u8 *module;
104 103
105 for (slot = 0; slot < slots; slot++) { 104 for (slot = 0; slot < slots; slot++) {
106 module = (char *)(startaddr + slot * size); 105 slotaddr = startaddr + slot * size;
106 module = ioremap_nocache(slotaddr, size);
107 BUG_ON(!module);
107 108
108 offset = OLDCARD; 109 offset = OLDCARD;
109 110
@@ -112,8 +113,10 @@ static void __init tc_probe(unsigned long startaddr, unsigned long size,
112 err |= get_dbe(pattern[1], module + OLDCARD + TC_PATTERN1); 113 err |= get_dbe(pattern[1], module + OLDCARD + TC_PATTERN1);
113 err |= get_dbe(pattern[2], module + OLDCARD + TC_PATTERN2); 114 err |= get_dbe(pattern[2], module + OLDCARD + TC_PATTERN2);
114 err |= get_dbe(pattern[3], module + OLDCARD + TC_PATTERN3); 115 err |= get_dbe(pattern[3], module + OLDCARD + TC_PATTERN3);
115 if (err) 116 if (err) {
117 iounmap(module);
116 continue; 118 continue;
119 }
117 120
118 if (pattern[0] != 0x55 || pattern[1] != 0x00 || 121 if (pattern[0] != 0x55 || pattern[1] != 0x00 ||
119 pattern[2] != 0xaa || pattern[3] != 0xff) { 122 pattern[2] != 0xaa || pattern[3] != 0xff) {
@@ -124,16 +127,20 @@ static void __init tc_probe(unsigned long startaddr, unsigned long size,
124 err |= get_dbe(pattern[1], module + TC_PATTERN1); 127 err |= get_dbe(pattern[1], module + TC_PATTERN1);
125 err |= get_dbe(pattern[2], module + TC_PATTERN2); 128 err |= get_dbe(pattern[2], module + TC_PATTERN2);
126 err |= get_dbe(pattern[3], module + TC_PATTERN3); 129 err |= get_dbe(pattern[3], module + TC_PATTERN3);
127 if (err) 130 if (err) {
131 iounmap(module);
128 continue; 132 continue;
133 }
129 } 134 }
130 135
131 if (pattern[0] != 0x55 || pattern[1] != 0x00 || 136 if (pattern[0] != 0x55 || pattern[1] != 0x00 ||
132 pattern[2] != 0xaa || pattern[3] != 0xff) 137 pattern[2] != 0xaa || pattern[3] != 0xff) {
138 iounmap(module);
133 continue; 139 continue;
140 }
134 141
135 tc_bus[slot].base_addr = (unsigned long)module; 142 tc_bus[slot].base_addr = slotaddr;
136 for(i = 0; i < 8; i++) { 143 for (i = 0; i < 8; i++) {
137 tc_bus[slot].firmware[i] = 144 tc_bus[slot].firmware[i] =
138 module[TC_FIRM_VER + offset + 4 * i]; 145 module[TC_FIRM_VER + offset + 4 * i];
139 tc_bus[slot].vendor[i] = 146 tc_bus[slot].vendor[i] =
@@ -171,6 +178,8 @@ static void __init tc_probe(unsigned long startaddr, unsigned long size,
171 tc_bus[slot].interrupt = -1; 178 tc_bus[slot].interrupt = -1;
172 break; 179 break;
173 } 180 }
181
182 iounmap(module);
174 } 183 }
175} 184}
176 185
@@ -196,8 +205,8 @@ static int __init tc_init(void)
196 tc_bus[i].flags = FREE; 205 tc_bus[i].flags = FREE;
197 } 206 }
198 207
199 info = (tcinfo *) rex_gettcinfo(); 208 info = rex_gettcinfo();
200 slot0addr = (unsigned long)CKSEG1ADDR(rex_slot_address(0)); 209 slot0addr = CPHYSADDR((long)rex_slot_address(0));
201 210
202 switch (mips_machtype) { 211 switch (mips_machtype) {
203 case MACH_DS5000_200: 212 case MACH_DS5000_200:
@@ -216,35 +225,21 @@ static int __init tc_init(void)
216 225
217 tc_clock = 10000 / info->clk_period; 226 tc_clock = 10000 / info->clk_period;
218 227
219 if (TURBOCHANNEL && info->slot_size && slot0addr) { 228 if (info->slot_size && slot0addr) {
220 printk("TURBOchannel rev. %1d at %2d.%1d MHz ", info->revision, 229 pr_info("TURBOchannel rev. %d at %d.%d MHz (with%s parity)\n",
221 tc_clock / 10, tc_clock % 10); 230 info->revision, tc_clock / 10, tc_clock % 10,
222 printk("(with%s parity)\n", info->parity ? "" : "out"); 231 info->parity ? "" : "out");
223 232
224 slot_size = info->slot_size << 20; 233 slot_size = info->slot_size << 20;
225 234
226 tc_probe(slot0addr, slot_size, num_tcslots); 235 tc_probe(slot0addr, slot_size, num_tcslots);
227 236
228 /* 237 for (i = 0; i < num_tcslots; i++) {
229 * All TURBOchannel DECstations have the onboard devices 238 if (!tc_bus[i].base_addr)
230 * where the (num_tcslots + 0 or 1 on DS5k/xx) Option Module 239 continue;
231 * would be. 240 pr_info(" slot %d: %s %s %s\n", i, tc_bus[i].vendor,
232 */ 241 tc_bus[i].name, tc_bus[i].firmware);
233 if(mips_machtype == MACH_DS5000_XX) 242 }
234 i = 1;
235 else
236 i = 0;
237
238 system_base = slot0addr + slot_size * (num_tcslots + i);
239
240#ifdef TC_DEBUG
241 for (i = 0; i < num_tcslots; i++)
242 if (tc_bus[i].base_addr) {
243 printk(" slot %d: ", i);
244 printk("%s %s %s\n", tc_bus[i].vendor,
245 tc_bus[i].name, tc_bus[i].firmware);
246 }
247#endif
248 } 243 }
249 244
250 return 0; 245 return 0;
@@ -258,4 +253,3 @@ EXPORT_SYMBOL(release_tc_card);
258EXPORT_SYMBOL(get_tc_base_addr); 253EXPORT_SYMBOL(get_tc_base_addr);
259EXPORT_SYMBOL(get_tc_irq_nr); 254EXPORT_SYMBOL(get_tc_irq_nr);
260EXPORT_SYMBOL(get_tc_speed); 255EXPORT_SYMBOL(get_tc_speed);
261EXPORT_SYMBOL(system_base);
diff --git a/drivers/tc/zs.c b/drivers/tc/zs.c
index 0e302ae5924c..c52af73a251b 100644
--- a/drivers/tc/zs.c
+++ b/drivers/tc/zs.c
@@ -65,14 +65,14 @@
65#include <asm/system.h> 65#include <asm/system.h>
66#include <asm/uaccess.h> 66#include <asm/uaccess.h>
67#include <asm/bootinfo.h> 67#include <asm/bootinfo.h>
68#include <asm/dec/serial.h>
69 68
70#ifdef CONFIG_MACH_DECSTATION
71#include <asm/dec/interrupts.h> 69#include <asm/dec/interrupts.h>
70#include <asm/dec/ioasic_addrs.h>
72#include <asm/dec/machtype.h> 71#include <asm/dec/machtype.h>
72#include <asm/dec/serial.h>
73#include <asm/dec/system.h>
73#include <asm/dec/tc.h> 74#include <asm/dec/tc.h>
74#include <asm/dec/ioasic_addrs.h> 75
75#endif
76#ifdef CONFIG_KGDB 76#ifdef CONFIG_KGDB
77#include <asm/kgdb.h> 77#include <asm/kgdb.h>
78#endif 78#endif
@@ -1616,30 +1616,22 @@ static void __init probe_sccs(void)
1616 return; 1616 return;
1617 } 1617 }
1618 1618
1619 /*
1620 * When serial console is activated, tc_init has not been called yet
1621 * and system_base is undefined. Unfortunately we have to hardcode
1622 * system_base for this case :-(. HK
1623 */
1624 switch(mips_machtype) { 1619 switch(mips_machtype) {
1625#ifdef CONFIG_MACH_DECSTATION 1620#ifdef CONFIG_MACH_DECSTATION
1626 case MACH_DS5000_2X0: 1621 case MACH_DS5000_2X0:
1627 case MACH_DS5900: 1622 case MACH_DS5900:
1628 system_base = CKSEG1ADDR(0x1f800000);
1629 n_chips = 2; 1623 n_chips = 2;
1630 zs_parms = &ds_parms; 1624 zs_parms = &ds_parms;
1631 zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0]; 1625 zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0];
1632 zs_parms->irq1 = dec_interrupt[DEC_IRQ_SCC1]; 1626 zs_parms->irq1 = dec_interrupt[DEC_IRQ_SCC1];
1633 break; 1627 break;
1634 case MACH_DS5000_1XX: 1628 case MACH_DS5000_1XX:
1635 system_base = CKSEG1ADDR(0x1c000000);
1636 n_chips = 2; 1629 n_chips = 2;
1637 zs_parms = &ds_parms; 1630 zs_parms = &ds_parms;
1638 zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0]; 1631 zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0];
1639 zs_parms->irq1 = dec_interrupt[DEC_IRQ_SCC1]; 1632 zs_parms->irq1 = dec_interrupt[DEC_IRQ_SCC1];
1640 break; 1633 break;
1641 case MACH_DS5000_XX: 1634 case MACH_DS5000_XX:
1642 system_base = CKSEG1ADDR(0x1c000000);
1643 n_chips = 1; 1635 n_chips = 1;
1644 zs_parms = &ds_parms; 1636 zs_parms = &ds_parms;
1645 zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0]; 1637 zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0];
@@ -1661,10 +1653,10 @@ static void __init probe_sccs(void)
1661 * The sccs reside on the high byte of the 16 bit IOBUS 1653 * The sccs reside on the high byte of the 16 bit IOBUS
1662 */ 1654 */
1663 zs_channels[n_channels].control = 1655 zs_channels[n_channels].control =
1664 (volatile unsigned char *)system_base + 1656 (volatile void *)CKSEG1ADDR(dec_kn_slot_base +
1665 (0 == chip ? zs_parms->scc0 : zs_parms->scc1) + 1657 (0 == chip ? zs_parms->scc0 : zs_parms->scc1) +
1666 (0 == channel ? zs_parms->channel_a_offset : 1658 (0 == channel ? zs_parms->channel_a_offset :
1667 zs_parms->channel_b_offset); 1659 zs_parms->channel_b_offset));
1668 zs_channels[n_channels].data = 1660 zs_channels[n_channels].data =
1669 zs_channels[n_channels].control + 4; 1661 zs_channels[n_channels].control + 4;
1670 1662
diff --git a/include/asm-mips/dec/ioasic_addrs.h b/include/asm-mips/dec/ioasic_addrs.h
index 5e18a7510592..4cbc1f8a1129 100644
--- a/include/asm-mips/dec/ioasic_addrs.h
+++ b/include/asm-mips/dec/ioasic_addrs.h
@@ -45,7 +45,8 @@
45 45
46 46
47/* 47/*
48 * Offsets for I/O ASIC registers (relative to (system_base + IOASIC_IOCTL)). 48 * Offsets for I/O ASIC registers
49 * (relative to (dec_kn_slot_base + IOASIC_IOCTL)).
49 */ 50 */
50 /* all systems */ 51 /* all systems */
51#define IO_REG_SCSI_DMA_P 0x00 /* SCSI DMA Pointer */ 52#define IO_REG_SCSI_DMA_P 0x00 /* SCSI DMA Pointer */
diff --git a/include/asm-mips/dec/kn01.h b/include/asm-mips/dec/kn01.h
index 607a385ffd8a..eb522aa1e226 100644
--- a/include/asm-mips/dec/kn01.h
+++ b/include/asm-mips/dec/kn01.h
@@ -13,9 +13,7 @@
13#ifndef __ASM_MIPS_DEC_KN01_H 13#ifndef __ASM_MIPS_DEC_KN01_H
14#define __ASM_MIPS_DEC_KN01_H 14#define __ASM_MIPS_DEC_KN01_H
15 15
16#include <asm/addrspace.h> 16#define KN01_SLOT_BASE 0x10000000
17
18#define KN01_SLOT_BASE CKSEG1ADDR(0x10000000)
19#define KN01_SLOT_SIZE 0x01000000 17#define KN01_SLOT_SIZE 0x01000000
20 18
21/* 19/*
@@ -41,17 +39,9 @@
41 39
42 40
43/* 41/*
44 * Some port addresses...
45 */
46#define KN01_LANCE_BASE (KN01_SLOT_BASE + KN01_LANCE) /* 0xB8000000 */
47#define KN01_DZ11_BASE (KN01_SLOT_BASE + KN01_DZ11) /* 0xBC000000 */
48#define KN01_RTC_BASE (KN01_SLOT_BASE + KN01_RTC) /* 0xBD000000 */
49
50
51/*
52 * Frame buffer memory address. 42 * Frame buffer memory address.
53 */ 43 */
54#define KN01_VFB_MEM CKSEG1ADDR(0x0fc00000) 44#define KN01_VFB_MEM 0x0fc00000
55 45
56/* 46/*
57 * CPU interrupt bits. 47 * CPU interrupt bits.
diff --git a/include/asm-mips/dec/kn02.h b/include/asm-mips/dec/kn02.h
index 83a042e90687..8319ad77b250 100644
--- a/include/asm-mips/dec/kn02.h
+++ b/include/asm-mips/dec/kn02.h
@@ -13,11 +13,7 @@
13#ifndef __ASM_MIPS_DEC_KN02_H 13#ifndef __ASM_MIPS_DEC_KN02_H
14#define __ASM_MIPS_DEC_KN02_H 14#define __ASM_MIPS_DEC_KN02_H
15 15
16#include <asm/addrspace.h> 16#define KN02_SLOT_BASE 0x1fc00000
17#include <asm/dec/ecc.h>
18
19
20#define KN02_SLOT_BASE CKSEG1ADDR(0x1fc00000)
21#define KN02_SLOT_SIZE 0x00080000 17#define KN02_SLOT_SIZE 0x00080000
22 18
23/* 19/*
@@ -34,14 +30,6 @@
34 30
35 31
36/* 32/*
37 * Some port addresses...
38 */
39#define KN02_DZ11_BASE (KN02_SLOT_BASE + KN02_DZ11) /* DZ11 */
40#define KN02_RTC_BASE (KN02_SLOT_BASE + KN02_RTC) /* RTC */
41#define KN02_CSR_BASE (KN02_SLOT_BASE + KN02_CSR) /* CSR */
42
43
44/*
45 * System Control & Status Register bits. 33 * System Control & Status Register bits.
46 */ 34 */
47#define KN02_CSR_RES_28 (0xf<<28) /* unused */ 35#define KN02_CSR_RES_28 (0xf<<28) /* unused */
diff --git a/include/asm-mips/dec/kn02xa.h b/include/asm-mips/dec/kn02xa.h
index 3c25a3346f3f..a25f3d7da7f7 100644
--- a/include/asm-mips/dec/kn02xa.h
+++ b/include/asm-mips/dec/kn02xa.h
@@ -17,31 +17,23 @@
17#ifndef __ASM_MIPS_DEC_KN02XA_H 17#ifndef __ASM_MIPS_DEC_KN02XA_H
18#define __ASM_MIPS_DEC_KN02XA_H 18#define __ASM_MIPS_DEC_KN02XA_H
19 19
20#include <asm/addrspace.h>
21#include <asm/dec/ioasic_addrs.h> 20#include <asm/dec/ioasic_addrs.h>
22 21
23#define KN02XA_SLOT_BASE CKSEG1ADDR(0x1c000000) 22#define KN02XA_SLOT_BASE 0x1c000000
24
25/*
26 * Some port addresses...
27 */
28#define KN02XA_IOASIC_BASE (KN02XA_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */
29#define KN02XA_RTC_BASE (KN02XA_SLOT_BASE + IOASIC_TOY) /* RTC */
30
31 23
32/* 24/*
33 * Memory control ASIC registers. 25 * Memory control ASIC registers.
34 */ 26 */
35#define KN02XA_MER CKSEG1ADDR(0x0c400000) /* memory error register */ 27#define KN02XA_MER 0x0c400000 /* memory error register */
36#define KN02XA_MSR CKSEG1ADDR(0x0c800000) /* memory size register */ 28#define KN02XA_MSR 0x0c800000 /* memory size register */
37 29
38/* 30/*
39 * CPU control ASIC registers. 31 * CPU control ASIC registers.
40 */ 32 */
41#define KN02XA_MEM_CONF CKSEG1ADDR(0x0e000000) /* write timeout config */ 33#define KN02XA_MEM_CONF 0x0e000000 /* write timeout config */
42#define KN02XA_EAR CKSEG1ADDR(0x0e000004) /* error address register */ 34#define KN02XA_EAR 0x0e000004 /* error address register */
43#define KN02XA_BOOT0 CKSEG1ADDR(0x0e000008) /* boot 0 register */ 35#define KN02XA_BOOT0 0x0e000008 /* boot 0 register */
44#define KN02XA_MEM_INTR CKSEG1ADDR(0x0e00000c) /* write err IRQ stat & ack */ 36#define KN02XA_MEM_INTR 0x0e00000c /* write err IRQ stat & ack */
45 37
46/* 38/*
47 * Memory Error Register bits, common definitions. 39 * Memory Error Register bits, common definitions.
diff --git a/include/asm-mips/dec/kn03.h b/include/asm-mips/dec/kn03.h
index 9d787cc26353..edede923ffb8 100644
--- a/include/asm-mips/dec/kn03.h
+++ b/include/asm-mips/dec/kn03.h
@@ -10,24 +10,15 @@
10 * 10 *
11 * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions 11 * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
12 * are by courtesy of Chris Fraser. 12 * are by courtesy of Chris Fraser.
13 * Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki 13 * Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki
14 */ 14 */
15#ifndef __ASM_MIPS_DEC_KN03_H 15#ifndef __ASM_MIPS_DEC_KN03_H
16#define __ASM_MIPS_DEC_KN03_H 16#define __ASM_MIPS_DEC_KN03_H
17 17
18#include <asm/addrspace.h>
19#include <asm/dec/ecc.h> 18#include <asm/dec/ecc.h>
20#include <asm/dec/ioasic_addrs.h> 19#include <asm/dec/ioasic_addrs.h>
21 20
22#define KN03_SLOT_BASE CKSEG1ADDR(0x1f800000) 21#define KN03_SLOT_BASE 0x1f800000
23
24/*
25 * Some port addresses...
26 */
27#define KN03_IOASIC_BASE (KN03_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */
28#define KN03_RTC_BASE (KN03_SLOT_BASE + IOASIC_TOY) /* RTC */
29#define KN03_MCR_BASE (KN03_SLOT_BASE + IOASIC_MCR) /* MCR */
30
31 22
32/* 23/*
33 * CPU interrupt bits. 24 * CPU interrupt bits.
diff --git a/include/asm-mips/dec/kn05.h b/include/asm-mips/dec/kn05.h
index 61feac382efb..15fe8f881e60 100644
--- a/include/asm-mips/dec/kn05.h
+++ b/include/asm-mips/dec/kn05.h
@@ -21,7 +21,6 @@
21#ifndef __ASM_MIPS_DEC_KN05_H 21#ifndef __ASM_MIPS_DEC_KN05_H
22#define __ASM_MIPS_DEC_KN05_H 22#define __ASM_MIPS_DEC_KN05_H
23 23
24#include <asm/addrspace.h>
25#include <asm/dec/ioasic_addrs.h> 24#include <asm/dec/ioasic_addrs.h>
26 25
27/* 26/*
@@ -30,7 +29,7 @@
30 * passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA. 29 * passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA.
31 * Others are handled locally. "Low" slots are always passed. 30 * Others are handled locally. "Low" slots are always passed.
32 */ 31 */
33#define KN4K_SLOT_BASE KSEG1ADDR(0x1fc00000) 32#define KN4K_SLOT_BASE 0x1fc00000
34 33
35#define KN4K_MB_ROM (0*IOASIC_SLOT_SIZE) /* KN05/KN04 card ROM */ 34#define KN4K_MB_ROM (0*IOASIC_SLOT_SIZE) /* KN05/KN04 card ROM */
36#define KN4K_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */ 35#define KN4K_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */
diff --git a/include/asm-mips/dec/system.h b/include/asm-mips/dec/system.h
new file mode 100644
index 000000000000..78af51fbc797
--- /dev/null
+++ b/include/asm-mips/dec/system.h
@@ -0,0 +1,18 @@
1/*
2 * include/asm-mips/dec/system.h
3 *
4 * Generic DECstation/DECsystem bits.
5 *
6 * Copyright (C) 2005 Maciej W. Rozycki
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13#ifndef __ASM_DEC_SYSTEM_H
14#define __ASM_DEC_SYSTEM_H
15
16extern unsigned long dec_kn_slot_base, dec_kn_slot_size;
17
18#endif /* __ASM_DEC_SYSTEM_H */
diff --git a/include/asm-mips/dec/tc.h b/include/asm-mips/dec/tc.h
index d7bba43f863a..9cb51f24d42c 100644
--- a/include/asm-mips/dec/tc.h
+++ b/include/asm-mips/dec/tc.h
@@ -7,10 +7,8 @@
7 * 7 *
8 * Copyright (c) 1998 Harald Koerfgen 8 * Copyright (c) 1998 Harald Koerfgen
9 */ 9 */
10#ifndef ASM_TC_H 10#ifndef __ASM_DEC_TC_H
11#define ASM_TC_H 11#define __ASM_DEC_TC_H
12
13extern unsigned long system_base;
14 12
15/* 13/*
16 * Search for a TURBOchannel Option Module 14 * Search for a TURBOchannel Option Module
@@ -36,8 +34,8 @@ extern unsigned long get_tc_base_addr(int);
36 */ 34 */
37extern unsigned long get_tc_irq_nr(int); 35extern unsigned long get_tc_irq_nr(int);
38/* 36/*
39 * Return TURBOchannel clock frequency in hz 37 * Return TURBOchannel clock frequency in Hz
40 */ 38 */
41extern unsigned long get_tc_speed(void); 39extern unsigned long get_tc_speed(void);
42 40
43#endif 41#endif /* __ASM_DEC_TC_H */
diff --git a/include/asm-mips/mach-dec/mc146818rtc.h b/include/asm-mips/mach-dec/mc146818rtc.h
index a326f451253b..6d37a5675803 100644
--- a/include/asm-mips/mach-dec/mc146818rtc.h
+++ b/include/asm-mips/mach-dec/mc146818rtc.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright (C) 1998, 2001 by Ralf Baechle 4 * Copyright (C) 1998, 2001 by Ralf Baechle
5 * Copyright (C) 1998 by Harald Koerfgen 5 * Copyright (C) 1998 by Harald Koerfgen
6 * Copyright (C) 2002 Maciej W. Rozycki 6 * Copyright (C) 2002, 2005 Maciej W. Rozycki
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License 9 * modify it under the terms of the GNU General Public License
@@ -14,23 +14,18 @@
14#define __ASM_MIPS_DEC_RTC_DEC_H 14#define __ASM_MIPS_DEC_RTC_DEC_H
15 15
16#include <linux/types.h> 16#include <linux/types.h>
17
18#include <asm/addrspace.h> 17#include <asm/addrspace.h>
18#include <asm/dec/system.h>
19 19
20extern volatile u8 *dec_rtc_base; 20extern volatile u8 *dec_rtc_base;
21extern unsigned long dec_kn_slot_size;
22 21
23#define RTC_PORT(x) CPHYSADDR(dec_rtc_base) 22#define RTC_PORT(x) CPHYSADDR((long)dec_rtc_base)
24#define RTC_IO_EXTENT dec_kn_slot_size 23#define RTC_IO_EXTENT dec_kn_slot_size
25#define RTC_IOMAPPED 0 24#define RTC_IOMAPPED 0
26#undef RTC_IRQ 25#undef RTC_IRQ
27 26
28#define RTC_DEC_YEAR 0x3f /* Where we store the real year on DECs. */ 27#define RTC_DEC_YEAR 0x3f /* Where we store the real year on DECs. */
29 28
30#include <linux/mc146818rtc.h>
31#include <linux/module.h>
32#include <linux/types.h>
33
34static inline unsigned char CMOS_READ(unsigned long addr) 29static inline unsigned char CMOS_READ(unsigned long addr)
35{ 30{
36 return dec_rtc_base[addr * 4]; 31 return dec_rtc_base[addr * 4];