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authorLinus Torvalds <torvalds@linux-foundation.org>2009-03-30 13:36:35 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-03-30 13:36:35 -0400
commit915db32ddbc967f023fbf7d7f01cca9e05606a9b (patch)
tree1634540805af363e1514d132d9140aa585f9cc9d
parentebc8eca169be0283d5a7ab54c4411dd59cfb0f27 (diff)
parent91e8a30e90144bcd0fead02dc57976f304c3b3f7 (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (21 commits) MIPS: Alchemy: PB1200: use SMC91X platform data. MIPS: Alchemy: MIPS hazard workarounds are not required. MIPS: Alchemy: provide cpu feature overrides. MIPS: Alchemy: unify CPU model constants. MIPS: Make a needlessly global symbol static in arch/mips/kernel/smp.c MIPS: Fix global namespace pollution in arch/mips/kernel/smp-up.c MIPS: Malta: make a needlessly global integer variable static MIPS: Use BUG_ON() where possible. MIPS: Convert obsolete irq_desc_t to struct irq_desc MIPS: Enable GENERIC_HARDIRQS_NO__DO_IRQ for all platforms MIPS: EMMA2RH: Set UART mapbase MIPS: EMMA2RH: Use set_irq_chip_and_handler_name MIPS: EMMA2RH: Use handle_edge_irq() handler for GPIO interrupts MIPS: Mark Eins: Fix cascading interrupt dispatcher MIPS: Au1000: convert to using gpiolib MIPS: Stop using <asm-generic/int-l64.h>. MIPS: Cavium: Add -Werror MIPS: Makefile: Add simple make install target. MIPS: Compat: Zero upper 32-bit of offset_high and offset_low. MIPS: __raw_spin_lock() may spin forever on ticket wrap. ...
Diffstat
-rw-r--r--arch/mips/Kconfig12
-rw-r--r--arch/mips/Makefile6
-rw-r--r--arch/mips/alchemy/Kconfig2
-rw-r--r--arch/mips/alchemy/common/gpio.c203
-rw-r--r--arch/mips/alchemy/devboards/pb1200/platform.c10
-rw-r--r--arch/mips/cavium-octeon/Makefile2
-rw-r--r--arch/mips/cavium-octeon/flash_setup.c2
-rw-r--r--arch/mips/cavium-octeon/octeon-irq.c2
-rw-r--r--arch/mips/emma/markeins/irq.c50
-rw-r--r--arch/mips/emma/markeins/platform.c3
-rw-r--r--arch/mips/include/asm/cpu.h3
-rw-r--r--arch/mips/include/asm/hazards.h4
-rw-r--r--arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h49
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio.h70
-rw-r--r--arch/mips/include/asm/mips-boards/generic.h2
-rw-r--r--arch/mips/include/asm/smp-ops.h2
-rw-r--r--arch/mips/include/asm/spinlock.h8
-rw-r--r--arch/mips/include/asm/types.h8
-rw-r--r--arch/mips/jazz/jazzdma.c3
-rw-r--r--arch/mips/kernel/cpu-probe.c21
-rw-r--r--arch/mips/kernel/irq-msc01.c6
-rw-r--r--arch/mips/kernel/irq_cpu.c3
-rw-r--r--arch/mips/kernel/linux32.c6
-rw-r--r--arch/mips/kernel/setup.c3
-rw-r--r--arch/mips/kernel/smp-up.c14
-rw-r--r--arch/mips/kernel/smp.c2
-rw-r--r--arch/mips/kernel/traps.c3
-rw-r--r--arch/mips/mm/c-r4k.c17
-rw-r--r--arch/mips/mm/highmem.c9
-rw-r--r--arch/mips/mm/init.c3
-rw-r--r--arch/mips/mm/ioremap.c9
-rw-r--r--arch/mips/mm/tlbex.c8
-rw-r--r--arch/mips/mti-malta/malta-init.c2
-rw-r--r--arch/mips/sgi-ip27/ip27-berr.c2
-rw-r--r--arch/mips/sgi-ip27/ip27-nmi.c4
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c63
-rw-r--r--arch/mips/sgi-ip32/ip32-memory.c2
-rw-r--r--arch/mips/sibyte/bcm1480/irq.c2
-rw-r--r--arch/mips/sibyte/sb1250/irq.c2
-rw-r--r--arch/mips/sni/a20r.c2
-rw-r--r--arch/mips/sni/pcimt.c2
-rw-r--r--arch/mips/sni/pcit.c4
-rw-r--r--arch/mips/sni/rm200.c2
-rw-r--r--arch/mips/txx9/Kconfig1
-rw-r--r--drivers/net/meth.c2
-rw-r--r--drivers/net/smc91x.h32
46 files changed, 353 insertions, 314 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 206cb7953b0c..dc787190430a 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -77,7 +77,6 @@ config MIPS_COBALT
77 select SYS_SUPPORTS_32BIT_KERNEL 77 select SYS_SUPPORTS_32BIT_KERNEL
78 select SYS_SUPPORTS_64BIT_KERNEL 78 select SYS_SUPPORTS_64BIT_KERNEL
79 select SYS_SUPPORTS_LITTLE_ENDIAN 79 select SYS_SUPPORTS_LITTLE_ENDIAN
80 select GENERIC_HARDIRQS_NO__DO_IRQ
81 80
82config MACH_DECSTATION 81config MACH_DECSTATION
83 bool "DECstations" 82 bool "DECstations"
@@ -132,7 +131,6 @@ config MACH_JAZZ
132 select SYS_SUPPORTS_32BIT_KERNEL 131 select SYS_SUPPORTS_32BIT_KERNEL
133 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL 132 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
134 select SYS_SUPPORTS_100HZ 133 select SYS_SUPPORTS_100HZ
135 select GENERIC_HARDIRQS_NO__DO_IRQ
136 help 134 help
137 This a family of machines based on the MIPS R4030 chipset which was 135 This a family of machines based on the MIPS R4030 chipset which was
138 used by several vendors to build RISC/os and Windows NT workstations. 136 used by several vendors to build RISC/os and Windows NT workstations.
@@ -154,7 +152,6 @@ config LASAT
154 select SYS_SUPPORTS_32BIT_KERNEL 152 select SYS_SUPPORTS_32BIT_KERNEL
155 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN 153 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
156 select SYS_SUPPORTS_LITTLE_ENDIAN 154 select SYS_SUPPORTS_LITTLE_ENDIAN
157 select GENERIC_HARDIRQS_NO__DO_IRQ
158 155
159config LEMOTE_FULONG 156config LEMOTE_FULONG
160 bool "Lemote Fulong mini-PC" 157 bool "Lemote Fulong mini-PC"
@@ -175,7 +172,6 @@ config LEMOTE_FULONG
175 select SYS_SUPPORTS_LITTLE_ENDIAN 172 select SYS_SUPPORTS_LITTLE_ENDIAN
176 select SYS_SUPPORTS_HIGHMEM 173 select SYS_SUPPORTS_HIGHMEM
177 select SYS_HAS_EARLY_PRINTK 174 select SYS_HAS_EARLY_PRINTK
178 select GENERIC_HARDIRQS_NO__DO_IRQ
179 select GENERIC_ISA_DMA_SUPPORT_BROKEN 175 select GENERIC_ISA_DMA_SUPPORT_BROKEN
180 select CPU_HAS_WB 176 select CPU_HAS_WB
181 help 177 help
@@ -250,7 +246,6 @@ config MACH_VR41XX
250 select CEVT_R4K 246 select CEVT_R4K
251 select CSRC_R4K 247 select CSRC_R4K
252 select SYS_HAS_CPU_VR41XX 248 select SYS_HAS_CPU_VR41XX
253 select GENERIC_HARDIRQS_NO__DO_IRQ
254 249
255config NXP_STB220 250config NXP_STB220
256 bool "NXP STB220 board" 251 bool "NXP STB220 board"
@@ -364,7 +359,6 @@ config SGI_IP27
364 select SYS_SUPPORTS_BIG_ENDIAN 359 select SYS_SUPPORTS_BIG_ENDIAN
365 select SYS_SUPPORTS_NUMA 360 select SYS_SUPPORTS_NUMA
366 select SYS_SUPPORTS_SMP 361 select SYS_SUPPORTS_SMP
367 select GENERIC_HARDIRQS_NO__DO_IRQ
368 help 362 help
369 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics 363 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
370 workstations. To compile a Linux kernel that runs on these, say Y 364 workstations. To compile a Linux kernel that runs on these, say Y
@@ -563,7 +557,6 @@ config MIKROTIK_RB532
563 select CEVT_R4K 557 select CEVT_R4K
564 select CSRC_R4K 558 select CSRC_R4K
565 select DMA_NONCOHERENT 559 select DMA_NONCOHERENT
566 select GENERIC_HARDIRQS_NO__DO_IRQ
567 select HW_HAS_PCI 560 select HW_HAS_PCI
568 select IRQ_CPU 561 select IRQ_CPU
569 select SYS_HAS_CPU_MIPS32_R1 562 select SYS_HAS_CPU_MIPS32_R1
@@ -700,8 +693,7 @@ config SCHED_OMIT_FRAME_POINTER
700 default y 693 default y
701 694
702config GENERIC_HARDIRQS_NO__DO_IRQ 695config GENERIC_HARDIRQS_NO__DO_IRQ
703 bool 696 def_bool y
704 default n
705 697
706# 698#
707# Select some configuration options automatically based on user selections. 699# Select some configuration options automatically based on user selections.
@@ -920,7 +912,6 @@ config SOC_PNX833X
920 select SYS_SUPPORTS_32BIT_KERNEL 912 select SYS_SUPPORTS_32BIT_KERNEL
921 select SYS_SUPPORTS_LITTLE_ENDIAN 913 select SYS_SUPPORTS_LITTLE_ENDIAN
922 select SYS_SUPPORTS_BIG_ENDIAN 914 select SYS_SUPPORTS_BIG_ENDIAN
923 select GENERIC_HARDIRQS_NO__DO_IRQ
924 select GENERIC_GPIO 915 select GENERIC_GPIO
925 select CPU_MIPSR2_IRQ_VI 916 select CPU_MIPSR2_IRQ_VI
926 917
@@ -939,7 +930,6 @@ config SOC_PNX8550
939 select SYS_HAS_CPU_MIPS32_R1 930 select SYS_HAS_CPU_MIPS32_R1
940 select SYS_HAS_EARLY_PRINTK 931 select SYS_HAS_EARLY_PRINTK
941 select SYS_SUPPORTS_32BIT_KERNEL 932 select SYS_SUPPORTS_32BIT_KERNEL
942 select GENERIC_HARDIRQS_NO__DO_IRQ
943 select GENERIC_GPIO 933 select GENERIC_GPIO
944 934
945config SWAP_IO_SPACE 935config SWAP_IO_SPACE
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 22dab2e14348..8d544c7c9fe9 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -720,11 +720,17 @@ ifdef CONFIG_MIPS32_O32
720 $(Q)$(MAKE) $(build)=. missing-syscalls EXTRA_CFLAGS="-mabi=32" 720 $(Q)$(MAKE) $(build)=. missing-syscalls EXTRA_CFLAGS="-mabi=32"
721endif 721endif
722 722
723install:
724 $(Q)install -D -m 755 vmlinux $(INSTALL_PATH)/vmlinux-$(KERNELRELEASE)
725 $(Q)install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE)
726 $(Q)install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE)
727
723archclean: 728archclean:
724 @$(MAKE) $(clean)=arch/mips/boot 729 @$(MAKE) $(clean)=arch/mips/boot
725 @$(MAKE) $(clean)=arch/mips/lasat 730 @$(MAKE) $(clean)=arch/mips/lasat
726 731
727define archhelp 732define archhelp
733 echo ' install - install kernel into $(INSTALL_PATH)'
728 echo ' vmlinux.ecoff - ECOFF boot image' 734 echo ' vmlinux.ecoff - ECOFF boot image'
729 echo ' vmlinux.bin - Raw binary boot image' 735 echo ' vmlinux.bin - Raw binary boot image'
730 echo ' vmlinux.srec - SREC boot image' 736 echo ' vmlinux.srec - SREC boot image'
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index 7f8ef13d0014..8128aebfb155 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -134,4 +134,4 @@ config SOC_AU1X00
134 select SYS_HAS_CPU_MIPS32_R1 134 select SYS_HAS_CPU_MIPS32_R1
135 select SYS_SUPPORTS_32BIT_KERNEL 135 select SYS_SUPPORTS_32BIT_KERNEL
136 select SYS_SUPPORTS_APM_EMULATION 136 select SYS_SUPPORTS_APM_EMULATION
137 select GENERIC_HARDIRQS_NO__DO_IRQ 137 select ARCH_REQUIRE_GPIOLIB
diff --git a/arch/mips/alchemy/common/gpio.c b/arch/mips/alchemy/common/gpio.c
index e660ddd611c4..91a9c4436c39 100644
--- a/arch/mips/alchemy/common/gpio.c
+++ b/arch/mips/alchemy/common/gpio.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2007, OpenWrt.org, Florian Fainelli <florian@openwrt.org> 2 * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
3 * Architecture specific GPIO support 3 * Architecture specific GPIO support
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
@@ -27,122 +27,175 @@
27 * others have a second one : GPIO2 27 * others have a second one : GPIO2
28 */ 28 */
29 29
30#include <linux/kernel.h>
30#include <linux/module.h> 31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/platform_device.h>
34#include <linux/gpio.h>
31 35
32#include <asm/mach-au1x00/au1000.h> 36#include <asm/mach-au1x00/au1000.h>
33#include <asm/gpio.h> 37#include <asm/gpio.h>
34 38
35#define gpio1 sys 39struct au1000_gpio_chip {
36#if !defined(CONFIG_SOC_AU1000) 40 struct gpio_chip chip;
37 41 void __iomem *regbase;
38static struct au1x00_gpio2 *const gpio2 = (struct au1x00_gpio2 *) GPIO2_BASE; 42};
39#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000
40 43
41static int au1xxx_gpio2_read(unsigned gpio) 44#if !defined(CONFIG_SOC_AU1000)
45static int au1000_gpio2_get(struct gpio_chip *chip, unsigned offset)
42{ 46{
43 gpio -= AU1XXX_GPIO_BASE; 47 u32 mask = 1 << offset;
44 return ((gpio2->pinstate >> gpio) & 0x01); 48 struct au1000_gpio_chip *gpch;
49
50 gpch = container_of(chip, struct au1000_gpio_chip, chip);
51 return readl(gpch->regbase + AU1000_GPIO2_ST) & mask;
45} 52}
46 53
47static void au1xxx_gpio2_write(unsigned gpio, int value) 54static void au1000_gpio2_set(struct gpio_chip *chip,
55 unsigned offset, int value)
48{ 56{
49 gpio -= AU1XXX_GPIO_BASE; 57 u32 mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset));
58 struct au1000_gpio_chip *gpch;
59 unsigned long flags;
60
61 gpch = container_of(chip, struct au1000_gpio_chip, chip);
50 62
51 gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio); 63 local_irq_save(flags);
64 writel(mask, gpch->regbase + AU1000_GPIO2_OUT);
65 local_irq_restore(flags);
52} 66}
53 67
54static int au1xxx_gpio2_direction_input(unsigned gpio) 68static int au1000_gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
55{ 69{
56 gpio -= AU1XXX_GPIO_BASE; 70 u32 mask = 1 << offset;
57 gpio2->dir &= ~(0x01 << gpio); 71 u32 tmp;
72 struct au1000_gpio_chip *gpch;
73 unsigned long flags;
74
75 gpch = container_of(chip, struct au1000_gpio_chip, chip);
76
77 local_irq_save(flags);
78 tmp = readl(gpch->regbase + AU1000_GPIO2_DIR);
79 tmp &= ~mask;
80 writel(tmp, gpch->regbase + AU1000_GPIO2_DIR);
81 local_irq_restore(flags);
82
58 return 0; 83 return 0;
59} 84}
60 85
61static int au1xxx_gpio2_direction_output(unsigned gpio, int value) 86static int au1000_gpio2_direction_output(struct gpio_chip *chip,
87 unsigned offset, int value)
62{ 88{
63 gpio -= AU1XXX_GPIO_BASE; 89 u32 mask = 1 << offset;
64 gpio2->dir |= 0x01 << gpio; 90 u32 out_mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset));
65 gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio); 91 u32 tmp;
92 struct au1000_gpio_chip *gpch;
93 unsigned long flags;
94
95 gpch = container_of(chip, struct au1000_gpio_chip, chip);
96
97 local_irq_save(flags);
98 tmp = readl(gpch->regbase + AU1000_GPIO2_DIR);
99 tmp |= mask;
100 writel(tmp, gpch->regbase + AU1000_GPIO2_DIR);
101 writel(out_mask, gpch->regbase + AU1000_GPIO2_OUT);
102 local_irq_restore(flags);
103
66 return 0; 104 return 0;
67} 105}
68
69#endif /* !defined(CONFIG_SOC_AU1000) */ 106#endif /* !defined(CONFIG_SOC_AU1000) */
70 107
71static int au1xxx_gpio1_read(unsigned gpio) 108static int au1000_gpio1_get(struct gpio_chip *chip, unsigned offset)
72{ 109{
73 return (gpio1->pinstaterd >> gpio) & 0x01; 110 u32 mask = 1 << offset;
111 struct au1000_gpio_chip *gpch;
112
113 gpch = container_of(chip, struct au1000_gpio_chip, chip);
114 return readl(gpch->regbase + AU1000_GPIO1_ST) & mask;
74} 115}
75 116
76static void au1xxx_gpio1_write(unsigned gpio, int value) 117static void au1000_gpio1_set(struct gpio_chip *chip,
118 unsigned offset, int value)
77{ 119{
120 u32 mask = 1 << offset;
121 u32 reg_offset;
122 struct au1000_gpio_chip *gpch;
123 unsigned long flags;
124
125 gpch = container_of(chip, struct au1000_gpio_chip, chip);
126
78 if (value) 127 if (value)
79 gpio1->outputset = (0x01 << gpio); 128 reg_offset = AU1000_GPIO1_OUT;
80 else 129 else
81 /* Output a zero */ 130 reg_offset = AU1000_GPIO1_CLR;
82 gpio1->outputclr = (0x01 << gpio);
83}
84 131
85static int au1xxx_gpio1_direction_input(unsigned gpio) 132 local_irq_save(flags);
86{ 133 writel(mask, gpch->regbase + reg_offset);
87 gpio1->pininputen = (0x01 << gpio); 134 local_irq_restore(flags);
88 return 0;
89} 135}
90 136
91static int au1xxx_gpio1_direction_output(unsigned gpio, int value) 137static int au1000_gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
92{ 138{
93 gpio1->trioutclr = (0x01 & gpio); 139 u32 mask = 1 << offset;
94 au1xxx_gpio1_write(gpio, value); 140 struct au1000_gpio_chip *gpch;
141
142 gpch = container_of(chip, struct au1000_gpio_chip, chip);
143 writel(mask, gpch->regbase + AU1000_GPIO1_ST);
144
95 return 0; 145 return 0;
96} 146}
97 147
98int au1xxx_gpio_get_value(unsigned gpio) 148static int au1000_gpio1_direction_output(struct gpio_chip *chip,
149 unsigned offset, int value)
99{ 150{
100 if (gpio >= AU1XXX_GPIO_BASE) 151 u32 mask = 1 << offset;
101#if defined(CONFIG_SOC_AU1000) 152 struct au1000_gpio_chip *gpch;
102 return 0;
103#else
104 return au1xxx_gpio2_read(gpio);
105#endif
106 else
107 return au1xxx_gpio1_read(gpio);
108}
109EXPORT_SYMBOL(au1xxx_gpio_get_value);
110 153
111void au1xxx_gpio_set_value(unsigned gpio, int value) 154 gpch = container_of(chip, struct au1000_gpio_chip, chip);
112{
113 if (gpio >= AU1XXX_GPIO_BASE)
114#if defined(CONFIG_SOC_AU1000)
115 ;
116#else
117 au1xxx_gpio2_write(gpio, value);
118#endif
119 else
120 au1xxx_gpio1_write(gpio, value);
121}
122EXPORT_SYMBOL(au1xxx_gpio_set_value);
123 155
124int au1xxx_gpio_direction_input(unsigned gpio) 156 writel(mask, gpch->regbase + AU1000_GPIO1_TRI_OUT);
125{ 157 au1000_gpio1_set(chip, offset, value);
126 if (gpio >= AU1XXX_GPIO_BASE)
127#if defined(CONFIG_SOC_AU1000)
128 return -ENODEV;
129#else
130 return au1xxx_gpio2_direction_input(gpio);
131#endif
132 158
133 return au1xxx_gpio1_direction_input(gpio); 159 return 0;
134} 160}
135EXPORT_SYMBOL(au1xxx_gpio_direction_input);
136 161
137int au1xxx_gpio_direction_output(unsigned gpio, int value) 162struct au1000_gpio_chip au1000_gpio_chip[] = {
163 [0] = {
164 .regbase = (void __iomem *)SYS_BASE,
165 .chip = {
166 .label = "au1000-gpio1",
167 .direction_input = au1000_gpio1_direction_input,
168 .direction_output = au1000_gpio1_direction_output,
169 .get = au1000_gpio1_get,
170 .set = au1000_gpio1_set,
171 .base = 0,
172 .ngpio = 32,
173 },
174 },
175#if !defined(CONFIG_SOC_AU1000)
176 [1] = {
177 .regbase = (void __iomem *)GPIO2_BASE,
178 .chip = {
179 .label = "au1000-gpio2",
180 .direction_input = au1000_gpio2_direction_input,
181 .direction_output = au1000_gpio2_direction_output,
182 .get = au1000_gpio2_get,
183 .set = au1000_gpio2_set,
184 .base = AU1XXX_GPIO_BASE,
185 .ngpio = 32,
186 },
187 },
188#endif
189};
190
191static int __init au1000_gpio_init(void)
138{ 192{
139 if (gpio >= AU1XXX_GPIO_BASE) 193 gpiochip_add(&au1000_gpio_chip[0].chip);
140#if defined(CONFIG_SOC_AU1000) 194#if !defined(CONFIG_SOC_AU1000)
141 return -ENODEV; 195 gpiochip_add(&au1000_gpio_chip[1].chip);
142#else
143 return au1xxx_gpio2_direction_output(gpio, value);
144#endif 196#endif
145 197
146 return au1xxx_gpio1_direction_output(gpio, value); 198 return 0;
147} 199}
148EXPORT_SYMBOL(au1xxx_gpio_direction_output); 200arch_initcall(au1000_gpio_init);
201
diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c
index 95303297c534..0d68e1985ffd 100644
--- a/arch/mips/alchemy/devboards/pb1200/platform.c
+++ b/arch/mips/alchemy/devboards/pb1200/platform.c
@@ -22,6 +22,7 @@
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/leds.h> 23#include <linux/leds.h>
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <linux/smc91x.h>
25 26
26#include <asm/mach-au1x00/au1xxx.h> 27#include <asm/mach-au1x00/au1xxx.h>
27#include <asm/mach-au1x00/au1100_mmc.h> 28#include <asm/mach-au1x00/au1100_mmc.h>
@@ -131,6 +132,12 @@ static struct platform_device ide_device = {
131 .resource = ide_resources 132 .resource = ide_resources
132}; 133};
133 134
135static struct smc91x_platdata smc_data = {
136 .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT,
137 .leda = RPC_LED_100_10,
138 .ledb = RPC_LED_TX_RX,
139};
140
134static struct resource smc91c111_resources[] = { 141static struct resource smc91c111_resources[] = {
135 [0] = { 142 [0] = {
136 .name = "smc91x-regs", 143 .name = "smc91x-regs",
@@ -146,6 +153,9 @@ static struct resource smc91c111_resources[] = {
146}; 153};
147 154
148static struct platform_device smc91c111_device = { 155static struct platform_device smc91c111_device = {
156 .dev = {
157 .platform_data = &smc_data,
158 },
149 .name = "smc91x", 159 .name = "smc91x",
150 .id = -1, 160 .id = -1,
151 .num_resources = ARRAY_SIZE(smc91c111_resources), 161 .num_resources = ARRAY_SIZE(smc91c111_resources),
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 1c2a7faf5881..d6903c3f3d51 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -14,3 +14,5 @@ obj-y += dma-octeon.o flash_setup.o
14obj-y += octeon-memcpy.o 14obj-y += octeon-memcpy.o
15 15
16obj-$(CONFIG_SMP) += smp.o 16obj-$(CONFIG_SMP) += smp.o
17
18EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/cavium-octeon/flash_setup.c b/arch/mips/cavium-octeon/flash_setup.c
index 553d36cbcc42..008f657116eb 100644
--- a/arch/mips/cavium-octeon/flash_setup.c
+++ b/arch/mips/cavium-octeon/flash_setup.c
@@ -57,7 +57,7 @@ static int __init flash_init(void)
57 flash_map.bankwidth = 1; 57 flash_map.bankwidth = 1;
58 flash_map.virt = ioremap(flash_map.phys, flash_map.size); 58 flash_map.virt = ioremap(flash_map.phys, flash_map.size);
59 pr_notice("Bootbus flash: Setting flash for %luMB flash at " 59 pr_notice("Bootbus flash: Setting flash for %luMB flash at "
60 "0x%08lx\n", flash_map.size >> 20, flash_map.phys); 60 "0x%08llx\n", flash_map.size >> 20, flash_map.phys);
61 simple_map_init(&flash_map); 61 simple_map_init(&flash_map);
62 mymtd = do_map_probe("cfi_probe", &flash_map); 62 mymtd = do_map_probe("cfi_probe", &flash_map);
63 if (mymtd) { 63 if (mymtd) {
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index fc72984a5dae..1c19af8daa62 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -31,7 +31,7 @@ static void octeon_irq_core_ack(unsigned int irq)
31 31
32static void octeon_irq_core_eoi(unsigned int irq) 32static void octeon_irq_core_eoi(unsigned int irq)
33{ 33{
34 irq_desc_t *desc = irq_desc + irq; 34 struct irq_desc *desc = irq_desc + irq;
35 unsigned int bit = irq - OCTEON_IRQ_SW0; 35 unsigned int bit = irq - OCTEON_IRQ_SW0;
36 /* 36 /*
37 * If an IRQ is being processed while we are disabling it the 37 * If an IRQ is being processed while we are disabling it the
diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c
index c2583ecc93cf..2bbc41a1623c 100644
--- a/arch/mips/emma/markeins/irq.c
+++ b/arch/mips/emma/markeins/irq.c
@@ -80,9 +80,9 @@ void emma2rh_irq_init(void)
80 u32 i; 80 u32 i;
81 81
82 for (i = 0; i < NUM_EMMA2RH_IRQ; i++) 82 for (i = 0; i < NUM_EMMA2RH_IRQ; i++)
83 set_irq_chip_and_handler(EMMA2RH_IRQ_BASE + i, 83 set_irq_chip_and_handler_name(EMMA2RH_IRQ_BASE + i,
84 &emma2rh_irq_controller, 84 &emma2rh_irq_controller,
85 handle_level_irq); 85 handle_level_irq, "level");
86} 86}
87 87
88static void emma2rh_sw_irq_enable(unsigned int irq) 88static void emma2rh_sw_irq_enable(unsigned int irq)
@@ -120,9 +120,9 @@ void emma2rh_sw_irq_init(void)
120 u32 i; 120 u32 i;
121 121
122 for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++) 122 for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++)
123 set_irq_chip_and_handler(EMMA2RH_SW_IRQ_BASE + i, 123 set_irq_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i,
124 &emma2rh_sw_irq_controller, 124 &emma2rh_sw_irq_controller,
125 handle_level_irq); 125 handle_level_irq, "level");
126} 126}
127 127
128static void emma2rh_gpio_irq_enable(unsigned int irq) 128static void emma2rh_gpio_irq_enable(unsigned int irq)
@@ -149,37 +149,28 @@ static void emma2rh_gpio_irq_disable(unsigned int irq)
149 149
150static void emma2rh_gpio_irq_ack(unsigned int irq) 150static void emma2rh_gpio_irq_ack(unsigned int irq)
151{ 151{
152 u32 reg;
153
154 irq -= EMMA2RH_GPIO_IRQ_BASE; 152 irq -= EMMA2RH_GPIO_IRQ_BASE;
155 emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); 153 emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
156
157 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
158 reg &= ~(1 << irq);
159 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
160} 154}
161 155
162static void emma2rh_gpio_irq_end(unsigned int irq) 156static void emma2rh_gpio_irq_mask_ack(unsigned int irq)
163{ 157{
164 u32 reg; 158 u32 reg;
165 159
166 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 160 irq -= EMMA2RH_GPIO_IRQ_BASE;
167 161 emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
168 irq -= EMMA2RH_GPIO_IRQ_BASE;
169 162
170 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); 163 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
171 reg |= 1 << irq; 164 reg &= ~(1 << irq);
172 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); 165 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
173 }
174} 166}
175 167
176struct irq_chip emma2rh_gpio_irq_controller = { 168struct irq_chip emma2rh_gpio_irq_controller = {
177 .name = "emma2rh_gpio_irq", 169 .name = "emma2rh_gpio_irq",
178 .ack = emma2rh_gpio_irq_ack, 170 .ack = emma2rh_gpio_irq_ack,
179 .mask = emma2rh_gpio_irq_disable, 171 .mask = emma2rh_gpio_irq_disable,
180 .mask_ack = emma2rh_gpio_irq_ack, 172 .mask_ack = emma2rh_gpio_irq_mask_ack,
181 .unmask = emma2rh_gpio_irq_enable, 173 .unmask = emma2rh_gpio_irq_enable,
182 .end = emma2rh_gpio_irq_end,
183}; 174};
184 175
185void emma2rh_gpio_irq_init(void) 176void emma2rh_gpio_irq_init(void)
@@ -187,8 +178,9 @@ void emma2rh_gpio_irq_init(void)
187 u32 i; 178 u32 i;
188 179
189 for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++) 180 for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++)
190 set_irq_chip(EMMA2RH_GPIO_IRQ_BASE + i, 181 set_irq_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i,
191 &emma2rh_gpio_irq_controller); 182 &emma2rh_gpio_irq_controller,
183 handle_edge_irq, "edge");
192} 184}
193 185
194static struct irqaction irq_cascade = { 186static struct irqaction irq_cascade = {
@@ -213,8 +205,7 @@ void emma2rh_irq_dispatch(void)
213 emma2rh_in32(EMMA2RH_BHIF_INT_EN_0); 205 emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);
214 206
215#ifdef EMMA2RH_SW_CASCADE 207#ifdef EMMA2RH_SW_CASCADE
216 if (intStatus & 208 if (intStatus & (1UL << EMMA2RH_SW_CASCADE)) {
217 (1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
218 u32 swIntStatus; 209 u32 swIntStatus;
219 swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT) 210 swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT)
220 & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); 211 & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
@@ -225,6 +216,8 @@ void emma2rh_irq_dispatch(void)
225 } 216 }
226 } 217 }
227 } 218 }
219 /* Skip S/W interrupt */
220 intStatus &= ~(1UL << EMMA2RH_SW_CASCADE);
228#endif 221#endif
229 222
230 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { 223 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
@@ -238,8 +231,7 @@ void emma2rh_irq_dispatch(void)
238 emma2rh_in32(EMMA2RH_BHIF_INT_EN_1); 231 emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);
239 232
240#ifdef EMMA2RH_GPIO_CASCADE 233#ifdef EMMA2RH_GPIO_CASCADE
241 if (intStatus & 234 if (intStatus & (1UL << (EMMA2RH_GPIO_CASCADE % 32))) {
242 (1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
243 u32 gpioIntStatus; 235 u32 gpioIntStatus;
244 gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST) 236 gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST)
245 & emma2rh_in32(EMMA2RH_GPIO_INT_MASK); 237 & emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
@@ -250,6 +242,8 @@ void emma2rh_irq_dispatch(void)
250 } 242 }
251 } 243 }
252 } 244 }
245 /* Skip GPIO interrupt */
246 intStatus &= ~(1UL << (EMMA2RH_GPIO_CASCADE % 32));
253#endif 247#endif
254 248
255 for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) { 249 for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
diff --git a/arch/mips/emma/markeins/platform.c b/arch/mips/emma/markeins/platform.c
index d5f47e4f0d18..80ae12ef87db 100644
--- a/arch/mips/emma/markeins/platform.c
+++ b/arch/mips/emma/markeins/platform.c
@@ -110,6 +110,7 @@ struct platform_device i2c_emma_devices[] = {
110static struct plat_serial8250_port platform_serial_ports[] = { 110static struct plat_serial8250_port platform_serial_ports[] = {
111 [0] = { 111 [0] = {
112 .membase= (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3), 112 .membase= (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3),
113 .mapbase = EMMA2RH_PFUR0_BASE + 3,
113 .irq = EMMA2RH_IRQ_PFUR0, 114 .irq = EMMA2RH_IRQ_PFUR0,
114 .uartclk = EMMA2RH_SERIAL_CLOCK, 115 .uartclk = EMMA2RH_SERIAL_CLOCK,
115 .regshift = 4, 116 .regshift = 4,
@@ -117,6 +118,7 @@ static struct plat_serial8250_port platform_serial_ports[] = {
117 .flags = EMMA2RH_SERIAL_FLAGS, 118 .flags = EMMA2RH_SERIAL_FLAGS,
118 }, [1] = { 119 }, [1] = {
119 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3), 120 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3),
121 .mapbase = EMMA2RH_PFUR1_BASE + 3,
120 .irq = EMMA2RH_IRQ_PFUR1, 122 .irq = EMMA2RH_IRQ_PFUR1,
121 .uartclk = EMMA2RH_SERIAL_CLOCK, 123 .uartclk = EMMA2RH_SERIAL_CLOCK,
122 .regshift = 4, 124 .regshift = 4,
@@ -124,6 +126,7 @@ static struct plat_serial8250_port platform_serial_ports[] = {
124 .flags = EMMA2RH_SERIAL_FLAGS, 126 .flags = EMMA2RH_SERIAL_FLAGS,
125 }, [2] = { 127 }, [2] = {
126 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR2_BASE + 3), 128 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR2_BASE + 3),
129 .mapbase = EMMA2RH_PFUR2_BASE + 3,
127 .irq = EMMA2RH_IRQ_PFUR2, 130 .irq = EMMA2RH_IRQ_PFUR2,
128 .uartclk = EMMA2RH_SERIAL_CLOCK, 131 .uartclk = EMMA2RH_SERIAL_CLOCK,
129 .regshift = 4, 132 .regshift = 4,
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index c018727c7ddc..3bdc0e3d89cc 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -209,8 +209,7 @@ enum cpu_type_enum {
209 * MIPS32 class processors 209 * MIPS32 class processors
210 */ 210 */
211 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 211 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
212 CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500, 212 CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
213 CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
214 213
215 /* 214 /*
216 * MIPS64 class processors 215 * MIPS64 class processors
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 134e1fc8f4d6..a12d971db4f9 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -87,7 +87,7 @@ do { \
87 : "=r" (tmp)); \ 87 : "=r" (tmp)); \
88} while (0) 88} while (0)
89 89
90#elif defined(CONFIG_CPU_MIPSR1) 90#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MACH_ALCHEMY)
91 91
92/* 92/*
93 * These are slightly complicated by the fact that we guarantee R1 kernels to 93 * These are slightly complicated by the fact that we guarantee R1 kernels to
@@ -139,7 +139,7 @@ do { \
139} while (0) 139} while (0)
140 140
141#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ 141#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
142 defined(CONFIG_CPU_R5500) 142 defined(CONFIG_CPU_R5500) || defined(CONFIG_MACH_ALCHEMY)
143 143
144/* 144/*
145 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. 145 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
diff --git a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
new file mode 100644
index 000000000000..d5df0cab9b87
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
@@ -0,0 +1,49 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 */
6
7#ifndef __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H
8#define __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H
9
10#define cpu_has_tlb 1
11#define cpu_has_4kex 1
12#define cpu_has_3k_cache 0
13#define cpu_has_4k_cache 1
14#define cpu_has_tx39_cache 0
15#define cpu_has_fpu 0
16#define cpu_has_counter 1
17#define cpu_has_watch 1
18#define cpu_has_divec 1
19#define cpu_has_vce 0
20#define cpu_has_cache_cdex_p 0
21#define cpu_has_cache_cdex_s 0
22#define cpu_has_mcheck 1
23#define cpu_has_ejtag 1
24#define cpu_has_llsc 1
25#define cpu_has_mips16 0
26#define cpu_has_mdmx 0
27#define cpu_has_mips3d 0
28#define cpu_has_smartmips 0
29#define cpu_has_vtag_icache 0
30#define cpu_has_dc_aliases 0
31#define cpu_has_ic_fills_f_dc 1
32#define cpu_has_mips32r1 1
33#define cpu_has_mips32r2 0
34#define cpu_has_mips64r1 0
35#define cpu_has_mips64r2 0
36#define cpu_has_dsp 0
37#define cpu_has_mipsmt 0
38#define cpu_has_userlocal 0
39#define cpu_has_nofpuex 0
40#define cpu_has_64bits 0
41#define cpu_has_64bit_zero_reg 0
42#define cpu_has_vint 0
43#define cpu_has_veic 0
44#define cpu_has_inclusive_pcaches 0
45
46#define cpu_dcache_line_size() 32
47#define cpu_icache_line_size() 32
48
49#endif /* __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h
index 2dc61e009a08..34d9b7279024 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio.h
@@ -5,65 +5,29 @@
5 5
6#define AU1XXX_GPIO_BASE 200 6#define AU1XXX_GPIO_BASE 200
7 7
8struct au1x00_gpio2 { 8/* GPIO bank 1 offsets */
9 u32 dir; 9#define AU1000_GPIO1_TRI_OUT 0x0100
10 u32 reserved; 10#define AU1000_GPIO1_OUT 0x0108
11 u32 output; 11#define AU1000_GPIO1_ST 0x0110
12 u32 pinstate; 12#define AU1000_GPIO1_CLR 0x010C
13 u32 inten;
14 u32 enable;
15};
16 13
17extern int au1xxx_gpio_get_value(unsigned gpio); 14/* GPIO bank 2 offsets */
18extern void au1xxx_gpio_set_value(unsigned gpio, int value); 15#define AU1000_GPIO2_DIR 0x00
19extern int au1xxx_gpio_direction_input(unsigned gpio); 16#define AU1000_GPIO2_RSVD 0x04
20extern int au1xxx_gpio_direction_output(unsigned gpio, int value); 17#define AU1000_GPIO2_OUT 0x08
18#define AU1000_GPIO2_ST 0x0C
19#define AU1000_GPIO2_INT 0x10
20#define AU1000_GPIO2_EN 0x14
21 21
22#define GPIO2_OUT_EN_MASK 0x00010000
22 23
23/* Wrappers for the arch-neutral GPIO API */ 24#define gpio_to_irq(gpio) NULL
24 25
25static inline int gpio_request(unsigned gpio, const char *label) 26#define gpio_get_value __gpio_get_value
26{ 27#define gpio_set_value __gpio_set_value
27 /* Not yet implemented */
28 return 0;
29}
30 28
31static inline void gpio_free(unsigned gpio) 29#define gpio_cansleep __gpio_cansleep
32{
33 /* Not yet implemented */
34}
35 30
36static inline int gpio_direction_input(unsigned gpio)
37{
38 return au1xxx_gpio_direction_input(gpio);
39}
40
41static inline int gpio_direction_output(unsigned gpio, int value)
42{
43 return au1xxx_gpio_direction_output(gpio, value);
44}
45
46static inline int gpio_get_value(unsigned gpio)
47{
48 return au1xxx_gpio_get_value(gpio);
49}
50
51static inline void gpio_set_value(unsigned gpio, int value)
52{
53 au1xxx_gpio_set_value(gpio, value);
54}
55
56static inline int gpio_to_irq(unsigned gpio)
57{
58 return gpio;
59}
60
61static inline int irq_to_gpio(unsigned irq)
62{
63 return irq;
64}
65
66/* For cansleep */
67#include <asm-generic/gpio.h> 31#include <asm-generic/gpio.h>
68 32
69#endif /* _AU1XXX_GPIO_H_ */ 33#endif /* _AU1XXX_GPIO_H_ */
diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h
index 7f0b034dd9a5..c0da1a881e3d 100644
--- a/arch/mips/include/asm/mips-boards/generic.h
+++ b/arch/mips/include/asm/mips-boards/generic.h
@@ -71,8 +71,6 @@
71 71
72#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f) 72#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f)
73 73
74extern int mips_revision_corid;
75
76#define MIPS_REVISION_SCON_OTHER 0 74#define MIPS_REVISION_SCON_OTHER 0
77#define MIPS_REVISION_SCON_SOCITSC 1 75#define MIPS_REVISION_SCON_SOCITSC 1
78#define MIPS_REVISION_SCON_SOCITSCP 2 76#define MIPS_REVISION_SCON_SOCITSCP 2
diff --git a/arch/mips/include/asm/smp-ops.h b/arch/mips/include/asm/smp-ops.h
index 43c207e72a63..64ffc0290b84 100644
--- a/arch/mips/include/asm/smp-ops.h
+++ b/arch/mips/include/asm/smp-ops.h
@@ -15,6 +15,8 @@
15 15
16#include <linux/cpumask.h> 16#include <linux/cpumask.h>
17 17
18struct task_struct;
19
18struct plat_smp_ops { 20struct plat_smp_ops {
19 void (*send_ipi_single)(int cpu, unsigned int action); 21 void (*send_ipi_single)(int cpu, unsigned int action);
20 void (*send_ipi_mask)(cpumask_t mask, unsigned int action); 22 void (*send_ipi_mask)(cpumask_t mask, unsigned int action);
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
index 0884947ebe27..10e82441b496 100644
--- a/arch/mips/include/asm/spinlock.h
+++ b/arch/mips/include/asm/spinlock.h
@@ -76,7 +76,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
76 "2: \n" 76 "2: \n"
77 " .subsection 2 \n" 77 " .subsection 2 \n"
78 "4: andi %[ticket], %[ticket], 0x1fff \n" 78 "4: andi %[ticket], %[ticket], 0x1fff \n"
79 "5: sll %[ticket], 5 \n" 79 " sll %[ticket], 5 \n"
80 " \n" 80 " \n"
81 "6: bnez %[ticket], 6b \n" 81 "6: bnez %[ticket], 6b \n"
82 " subu %[ticket], 1 \n" 82 " subu %[ticket], 1 \n"
@@ -85,7 +85,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
85 " andi %[ticket], %[ticket], 0x1fff \n" 85 " andi %[ticket], %[ticket], 0x1fff \n"
86 " beq %[ticket], %[my_ticket], 2b \n" 86 " beq %[ticket], %[my_ticket], 2b \n"
87 " subu %[ticket], %[my_ticket], %[ticket] \n" 87 " subu %[ticket], %[my_ticket], %[ticket] \n"
88 " b 5b \n" 88 " b 4b \n"
89 " subu %[ticket], %[ticket], 1 \n" 89 " subu %[ticket], %[ticket], 1 \n"
90 " .previous \n" 90 " .previous \n"
91 " .set pop \n" 91 " .set pop \n"
@@ -113,7 +113,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
113 " ll %[ticket], %[ticket_ptr] \n" 113 " ll %[ticket], %[ticket_ptr] \n"
114 " \n" 114 " \n"
115 "4: andi %[ticket], %[ticket], 0x1fff \n" 115 "4: andi %[ticket], %[ticket], 0x1fff \n"
116 "5: sll %[ticket], 5 \n" 116 " sll %[ticket], 5 \n"
117 " \n" 117 " \n"
118 "6: bnez %[ticket], 6b \n" 118 "6: bnez %[ticket], 6b \n"
119 " subu %[ticket], 1 \n" 119 " subu %[ticket], 1 \n"
@@ -122,7 +122,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
122 " andi %[ticket], %[ticket], 0x1fff \n" 122 " andi %[ticket], %[ticket], 0x1fff \n"
123 " beq %[ticket], %[my_ticket], 2b \n" 123 " beq %[ticket], %[my_ticket], 2b \n"
124 " subu %[ticket], %[my_ticket], %[ticket] \n" 124 " subu %[ticket], %[my_ticket], %[ticket] \n"
125 " b 5b \n" 125 " b 4b \n"
126 " subu %[ticket], %[ticket], 1 \n" 126 " subu %[ticket], %[ticket], 1 \n"
127 " .previous \n" 127 " .previous \n"
128 " .set pop \n" 128 " .set pop \n"
diff --git a/arch/mips/include/asm/types.h b/arch/mips/include/asm/types.h
index bcbb8d675af5..7956e69a3bd5 100644
--- a/arch/mips/include/asm/types.h
+++ b/arch/mips/include/asm/types.h
@@ -4,12 +4,18 @@
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle 6 * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
7 * Copyright (C) 2008 Wind River Systems,
8 * written by Ralf Baechle
7 * Copyright (C) 1999 Silicon Graphics, Inc. 9 * Copyright (C) 1999 Silicon Graphics, Inc.
8 */ 10 */
9#ifndef _ASM_TYPES_H 11#ifndef _ASM_TYPES_H
10#define _ASM_TYPES_H 12#define _ASM_TYPES_H
11 13
12#if _MIPS_SZLONG == 64 14/*
15 * We don't use int-l64.h for the kernel anymore but still use it for
16 * userspace to avoid code changes.
17 */
18#if (_MIPS_SZLONG == 64) && !defined(__KERNEL__)
13# include <asm-generic/int-l64.h> 19# include <asm-generic/int-l64.h>
14#else 20#else
15# include <asm-generic/int-ll64.h> 21# include <asm-generic/int-ll64.h>
diff --git a/arch/mips/jazz/jazzdma.c b/arch/mips/jazz/jazzdma.c
index c672c08d49e5..f0fd636723be 100644
--- a/arch/mips/jazz/jazzdma.c
+++ b/arch/mips/jazz/jazzdma.c
@@ -68,8 +68,7 @@ static int __init vdma_init(void)
68 */ 68 */
69 pgtbl = (VDMA_PGTBL_ENTRY *)__get_free_pages(GFP_KERNEL | GFP_DMA, 69 pgtbl = (VDMA_PGTBL_ENTRY *)__get_free_pages(GFP_KERNEL | GFP_DMA,
70 get_order(VDMA_PGTBL_SIZE)); 70 get_order(VDMA_PGTBL_SIZE));
71 if (!pgtbl) 71 BUG_ON(!pgtbl);
72 BUG();
73 dma_cache_wback_inv((unsigned long)pgtbl, VDMA_PGTBL_SIZE); 72 dma_cache_wback_inv((unsigned long)pgtbl, VDMA_PGTBL_SIZE);
74 pgtbl = (VDMA_PGTBL_ENTRY *)KSEG1ADDR(pgtbl); 73 pgtbl = (VDMA_PGTBL_ENTRY *)KSEG1ADDR(pgtbl);
75 74
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 1bdbcad3bb74..b13b8eb30596 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -183,13 +183,7 @@ void __init check_wait(void)
183 case CPU_TX49XX: 183 case CPU_TX49XX:
184 cpu_wait = r4k_wait_irqoff; 184 cpu_wait = r4k_wait_irqoff;
185 break; 185 break;
186 case CPU_AU1000: 186 case CPU_ALCHEMY:
187 case CPU_AU1100:
188 case CPU_AU1500:
189 case CPU_AU1550:
190 case CPU_AU1200:
191 case CPU_AU1210:
192 case CPU_AU1250:
193 cpu_wait = au1k_wait; 187 cpu_wait = au1k_wait;
194 break; 188 break;
195 case CPU_20KC: 189 case CPU_20KC:
@@ -783,37 +777,30 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
783 switch (c->processor_id & 0xff00) { 777 switch (c->processor_id & 0xff00) {
784 case PRID_IMP_AU1_REV1: 778 case PRID_IMP_AU1_REV1:
785 case PRID_IMP_AU1_REV2: 779 case PRID_IMP_AU1_REV2:
780 c->cputype = CPU_ALCHEMY;
786 switch ((c->processor_id >> 24) & 0xff) { 781 switch ((c->processor_id >> 24) & 0xff) {
787 case 0: 782 case 0:
788 c->cputype = CPU_AU1000;
789 __cpu_name[cpu] = "Au1000"; 783 __cpu_name[cpu] = "Au1000";
790 break; 784 break;
791 case 1: 785 case 1:
792 c->cputype = CPU_AU1500;
793 __cpu_name[cpu] = "Au1500"; 786 __cpu_name[cpu] = "Au1500";
794 break; 787 break;
795 case 2: 788 case 2:
796 c->cputype = CPU_AU1100;
797 __cpu_name[cpu] = "Au1100"; 789 __cpu_name[cpu] = "Au1100";
798 break; 790 break;
799 case 3: 791 case 3:
800 c->cputype = CPU_AU1550;
801 __cpu_name[cpu] = "Au1550"; 792 __cpu_name[cpu] = "Au1550";
802 break; 793 break;
803 case 4: 794 case 4:
804 c->cputype = CPU_AU1200;
805 __cpu_name[cpu] = "Au1200"; 795 __cpu_name[cpu] = "Au1200";
806 if ((c->processor_id & 0xff) == 2) { 796 if ((c->processor_id & 0xff) == 2)
807 c->cputype = CPU_AU1250;
808 __cpu_name[cpu] = "Au1250"; 797 __cpu_name[cpu] = "Au1250";
809 }
810 break; 798 break;
811 case 5: 799 case 5:
812 c->cputype = CPU_AU1210;
813 __cpu_name[cpu] = "Au1210"; 800 __cpu_name[cpu] = "Au1210";
814 break; 801 break;
815 default: 802 default:
816 panic("Unknown Au Core!"); 803 __cpu_name[cpu] = "Au1xxx";
817 break; 804 break;
818 } 805 }
819 break; 806 break;
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index 963c16d266ab..6a8cd28133d5 100644
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -140,14 +140,16 @@ void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqma
140 140
141 switch (imp->im_type) { 141 switch (imp->im_type) {
142 case MSC01_IRQ_EDGE: 142 case MSC01_IRQ_EDGE:
143 set_irq_chip(irqbase+n, &msc_edgeirq_type); 143 set_irq_chip_and_handler_name(irqbase + n,
144 &msc_edgeirq_type, handle_edge_irq, "edge");
144 if (cpu_has_veic) 145 if (cpu_has_veic)
145 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); 146 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
146 else 147 else
147 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); 148 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
148 break; 149 break;
149 case MSC01_IRQ_LEVEL: 150 case MSC01_IRQ_LEVEL:
150 set_irq_chip(irqbase+n, &msc_levelirq_type); 151 set_irq_chip_and_handler_name(irqbase+n,
152 &msc_levelirq_type, handle_level_irq, "level");
151 if (cpu_has_veic) 153 if (cpu_has_veic)
152 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); 154 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
153 else 155 else
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 0ee2567b780d..55c8a3ca507b 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -112,7 +112,8 @@ void __init mips_cpu_irq_init(void)
112 */ 112 */
113 if (cpu_has_mipsmt) 113 if (cpu_has_mipsmt)
114 for (i = irq_base; i < irq_base + 2; i++) 114 for (i = irq_base; i < irq_base + 2; i++)
115 set_irq_chip(i, &mips_mt_cpu_irq_controller); 115 set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller,
116 handle_percpu_irq);
116 117
117 for (i = irq_base + 2; i < irq_base + 8; i++) 118 for (i = irq_base + 2; i < irq_base + 8; i++)
118 set_irq_chip_and_handler(i, &mips_cpu_irq_controller, 119 set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 2a472713de8e..6242bc68add7 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -133,9 +133,9 @@ SYSCALL_DEFINE4(32_ftruncate64, unsigned long, fd, unsigned long, __dummy,
133 return sys_ftruncate(fd, merge_64(a2, a3)); 133 return sys_ftruncate(fd, merge_64(a2, a3));
134} 134}
135 135
136SYSCALL_DEFINE5(32_llseek, unsigned long, fd, unsigned long, offset_high, 136SYSCALL_DEFINE5(32_llseek, unsigned int, fd, unsigned int, offset_high,
137 unsigned long, offset_low, loff_t __user *, result, 137 unsigned int, offset_low, loff_t __user *, result,
138 unsigned long, origin) 138 unsigned int, origin)
139{ 139{
140 return sys_llseek(fd, offset_high, offset_low, result, origin); 140 return sys_llseek(fd, offset_high, offset_low, result, origin);
141} 141}
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 4430a1f8fdf1..2950b97253b7 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -277,7 +277,8 @@ static void __init bootmem_init(void)
277 * not selected. Once that done we can determine the low bound 277 * not selected. Once that done we can determine the low bound
278 * of usable memory. 278 * of usable memory.
279 */ 279 */
280 reserved_end = max(init_initrd(), PFN_UP(__pa_symbol(&_end))); 280 reserved_end = max(init_initrd(),
281 (unsigned long) PFN_UP(__pa_symbol(&_end)));
281 282
282 /* 283 /*
283 * max_low_pfn is not a number of pages. The number of pages 284 * max_low_pfn is not a number of pages. The number of pages
diff --git a/arch/mips/kernel/smp-up.c b/arch/mips/kernel/smp-up.c
index ead6c30eeb14..878e3733bbb2 100644
--- a/arch/mips/kernel/smp-up.c
+++ b/arch/mips/kernel/smp-up.c
@@ -13,7 +13,7 @@
13/* 13/*
14 * Send inter-processor interrupt 14 * Send inter-processor interrupt
15 */ 15 */
16void up_send_ipi_single(int cpu, unsigned int action) 16static void up_send_ipi_single(int cpu, unsigned int action)
17{ 17{
18 panic(KERN_ERR "%s called", __func__); 18 panic(KERN_ERR "%s called", __func__);
19} 19}
@@ -27,31 +27,31 @@ static inline void up_send_ipi_mask(cpumask_t mask, unsigned int action)
27 * After we've done initial boot, this function is called to allow the 27 * After we've done initial boot, this function is called to allow the
28 * board code to clean up state, if needed 28 * board code to clean up state, if needed
29 */ 29 */
30void __cpuinit up_init_secondary(void) 30static void __cpuinit up_init_secondary(void)
31{ 31{
32} 32}
33 33
34void __cpuinit up_smp_finish(void) 34static void __cpuinit up_smp_finish(void)
35{ 35{
36} 36}
37 37
38/* Hook for after all CPUs are online */ 38/* Hook for after all CPUs are online */
39void up_cpus_done(void) 39static void up_cpus_done(void)
40{ 40{
41} 41}
42 42
43/* 43/*
44 * Firmware CPU startup hook 44 * Firmware CPU startup hook
45 */ 45 */
46void __cpuinit up_boot_secondary(int cpu, struct task_struct *idle) 46static void __cpuinit up_boot_secondary(int cpu, struct task_struct *idle)
47{ 47{
48} 48}
49 49
50void __init up_smp_setup(void) 50static void __init up_smp_setup(void)
51{ 51{
52} 52}
53 53
54void __init up_prepare_cpus(unsigned int max_cpus) 54static void __init up_prepare_cpus(unsigned int max_cpus)
55{ 55{
56} 56}
57 57
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 3da94704f816..c937506a03aa 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -44,7 +44,7 @@
44#include <asm/mipsmtregs.h> 44#include <asm/mipsmtregs.h>
45#endif /* CONFIG_MIPS_MT_SMTC */ 45#endif /* CONFIG_MIPS_MT_SMTC */
46 46
47volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ 47static volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */
48int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ 48int __cpu_number_map[NR_CPUS]; /* Map physical to logical */
49int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ 49int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */
50 50
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 29fadaccecdd..e83da174b533 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1277,8 +1277,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1277 u32 *w; 1277 u32 *w;
1278 unsigned char *b; 1278 unsigned char *b;
1279 1279
1280 if (!cpu_has_veic && !cpu_has_vint) 1280 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1281 BUG();
1282 1281
1283 if (addr == NULL) { 1282 if (addr == NULL) {
1284 handler = (unsigned long) do_default_vi; 1283 handler = (unsigned long) do_default_vi;
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 871e828bc62a..58d9075e86fe 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1026,13 +1026,7 @@ static void __cpuinit probe_pcache(void)
1026 c->icache.flags |= MIPS_CACHE_VTAG; 1026 c->icache.flags |= MIPS_CACHE_VTAG;
1027 break; 1027 break;
1028 1028
1029 case CPU_AU1000: 1029 case CPU_ALCHEMY:
1030 case CPU_AU1500:
1031 case CPU_AU1100:
1032 case CPU_AU1550:
1033 case CPU_AU1200:
1034 case CPU_AU1210:
1035 case CPU_AU1250:
1036 c->icache.flags |= MIPS_CACHE_IC_F_DC; 1030 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1037 break; 1031 break;
1038 } 1032 }
@@ -1244,7 +1238,7 @@ void au1x00_fixup_config_od(void)
1244 /* 1238 /*
1245 * Au1100 errata actually keeps silence about this bit, so we set it 1239 * Au1100 errata actually keeps silence about this bit, so we set it
1246 * just in case for those revisions that require it to be set according 1240 * just in case for those revisions that require it to be set according
1247 * to arch/mips/au1000/common/cputable.c 1241 * to the (now gone) cpu table.
1248 */ 1242 */
1249 case 0x02030200: /* Au1100 AB */ 1243 case 0x02030200: /* Au1100 AB */
1250 case 0x02030201: /* Au1100 BA */ 1244 case 0x02030201: /* Au1100 BA */
@@ -1314,11 +1308,10 @@ static void __cpuinit coherency_setup(void)
1314 break; 1308 break;
1315 /* 1309 /*
1316 * We need to catch the early Alchemy SOCs with 1310 * We need to catch the early Alchemy SOCs with
1317 * the write-only co_config.od bit and set it back to one... 1311 * the write-only co_config.od bit and set it back to one on:
1312 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB
1318 */ 1313 */
1319 case CPU_AU1000: /* rev. DA, HA, HB */ 1314 case CPU_ALCHEMY:
1320 case CPU_AU1100: /* rev. AB, BA, BC ?? */
1321 case CPU_AU1500: /* rev. AB */
1322 au1x00_fixup_config_od(); 1315 au1x00_fixup_config_od();
1323 break; 1316 break;
1324 1317
diff --git a/arch/mips/mm/highmem.c b/arch/mips/mm/highmem.c
index 8f2cd8eda741..060d28dca8a8 100644
--- a/arch/mips/mm/highmem.c
+++ b/arch/mips/mm/highmem.c
@@ -17,8 +17,7 @@ void *__kmap(struct page *page)
17 17
18void __kunmap(struct page *page) 18void __kunmap(struct page *page)
19{ 19{
20 if (in_interrupt()) 20 BUG_ON(in_interrupt());
21 BUG();
22 if (!PageHighMem(page)) 21 if (!PageHighMem(page))
23 return; 22 return;
24 kunmap_high(page); 23 kunmap_high(page);
@@ -46,8 +45,7 @@ void *__kmap_atomic(struct page *page, enum km_type type)
46 idx = type + KM_TYPE_NR*smp_processor_id(); 45 idx = type + KM_TYPE_NR*smp_processor_id();
47 vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); 46 vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
48#ifdef CONFIG_DEBUG_HIGHMEM 47#ifdef CONFIG_DEBUG_HIGHMEM
49 if (!pte_none(*(kmap_pte-idx))) 48 BUG_ON(!pte_none(*(kmap_pte - idx)));
50 BUG();
51#endif 49#endif
52 set_pte(kmap_pte-idx, mk_pte(page, kmap_prot)); 50 set_pte(kmap_pte-idx, mk_pte(page, kmap_prot));
53 local_flush_tlb_one((unsigned long)vaddr); 51 local_flush_tlb_one((unsigned long)vaddr);
@@ -66,8 +64,7 @@ void __kunmap_atomic(void *kvaddr, enum km_type type)
66 return; 64 return;
67 } 65 }
68 66
69 if (vaddr != __fix_to_virt(FIX_KMAP_BEGIN+idx)) 67 BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx));
70 BUG();
71 68
72 /* 69 /*
73 * force other mappings to Oops if they'll try to access 70 * force other mappings to Oops if they'll try to access
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 137c14bafd6b..d9348946a19e 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -307,8 +307,7 @@ void __init fixrange_init(unsigned long start, unsigned long end,
307 if (pmd_none(*pmd)) { 307 if (pmd_none(*pmd)) {
308 pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE); 308 pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
309 set_pmd(pmd, __pmd((unsigned long)pte)); 309 set_pmd(pmd, __pmd((unsigned long)pte));
310 if (pte != pte_offset_kernel(pmd, 0)) 310 BUG_ON(pte != pte_offset_kernel(pmd, 0));
311 BUG();
312 } 311 }
313 vaddr += PMD_SIZE; 312 vaddr += PMD_SIZE;
314 } 313 }
diff --git a/arch/mips/mm/ioremap.c b/arch/mips/mm/ioremap.c
index 59945b9ee23c..0c43248347bd 100644
--- a/arch/mips/mm/ioremap.c
+++ b/arch/mips/mm/ioremap.c
@@ -27,8 +27,7 @@ static inline void remap_area_pte(pte_t * pte, unsigned long address,
27 end = address + size; 27 end = address + size;
28 if (end > PMD_SIZE) 28 if (end > PMD_SIZE)
29 end = PMD_SIZE; 29 end = PMD_SIZE;
30 if (address >= end) 30 BUG_ON(address >= end);
31 BUG();
32 pfn = phys_addr >> PAGE_SHIFT; 31 pfn = phys_addr >> PAGE_SHIFT;
33 do { 32 do {
34 if (!pte_none(*pte)) { 33 if (!pte_none(*pte)) {
@@ -52,8 +51,7 @@ static inline int remap_area_pmd(pmd_t * pmd, unsigned long address,
52 if (end > PGDIR_SIZE) 51 if (end > PGDIR_SIZE)
53 end = PGDIR_SIZE; 52 end = PGDIR_SIZE;
54 phys_addr -= address; 53 phys_addr -= address;
55 if (address >= end) 54 BUG_ON(address >= end);
56 BUG();
57 do { 55 do {
58 pte_t * pte = pte_alloc_kernel(pmd, address); 56 pte_t * pte = pte_alloc_kernel(pmd, address);
59 if (!pte) 57 if (!pte)
@@ -75,8 +73,7 @@ static int remap_area_pages(unsigned long address, phys_t phys_addr,
75 phys_addr -= address; 73 phys_addr -= address;
76 dir = pgd_offset(&init_mm, address); 74 dir = pgd_offset(&init_mm, address);
77 flush_cache_all(); 75 flush_cache_all();
78 if (address >= end) 76 BUG_ON(address >= end);
79 BUG();
80 do { 77 do {
81 pud_t *pud; 78 pud_t *pud;
82 pmd_t *pmd; 79 pmd_t *pmd;
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index f335cf6cdd78..0615b62efd6d 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -292,13 +292,6 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
292 case CPU_R4300: 292 case CPU_R4300:
293 case CPU_5KC: 293 case CPU_5KC:
294 case CPU_TX49XX: 294 case CPU_TX49XX:
295 case CPU_AU1000:
296 case CPU_AU1100:
297 case CPU_AU1500:
298 case CPU_AU1550:
299 case CPU_AU1200:
300 case CPU_AU1210:
301 case CPU_AU1250:
302 case CPU_PR4450: 295 case CPU_PR4450:
303 uasm_i_nop(p); 296 uasm_i_nop(p);
304 tlbw(p); 297 tlbw(p);
@@ -321,6 +314,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
321 case CPU_R5500: 314 case CPU_R5500:
322 if (m4kc_tlbp_war()) 315 if (m4kc_tlbp_war())
323 uasm_i_nop(p); 316 uasm_i_nop(p);
317 case CPU_ALCHEMY:
324 tlbw(p); 318 tlbw(p);
325 break; 319 break;
326 320
diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c
index 4832af251668..475038a141a6 100644
--- a/arch/mips/mti-malta/malta-init.c
+++ b/arch/mips/mti-malta/malta-init.c
@@ -48,7 +48,7 @@ int *_prom_argv, *_prom_envp;
48 48
49int init_debug = 0; 49int init_debug = 0;
50 50
51int mips_revision_corid; 51static int mips_revision_corid;
52int mips_revision_sconid; 52int mips_revision_sconid;
53 53
54/* Bonito64 system controller register base. */ 54/* Bonito64 system controller register base. */
diff --git a/arch/mips/sgi-ip27/ip27-berr.c b/arch/mips/sgi-ip27/ip27-berr.c
index 7d05e68fdc77..04cebadc2b3c 100644
--- a/arch/mips/sgi-ip27/ip27-berr.c
+++ b/arch/mips/sgi-ip27/ip27-berr.c
@@ -66,7 +66,7 @@ int ip27_be_handler(struct pt_regs *regs, int is_fixup)
66 printk("Slice %c got %cbe at 0x%lx\n", 'A' + cpu, data ? 'd' : 'i', 66 printk("Slice %c got %cbe at 0x%lx\n", 'A' + cpu, data ? 'd' : 'i',
67 regs->cp0_epc); 67 regs->cp0_epc);
68 printk("Hub information:\n"); 68 printk("Hub information:\n");
69 printk("ERR_INT_PEND = 0x%06lx\n", LOCAL_HUB_L(PI_ERR_INT_PEND)); 69 printk("ERR_INT_PEND = 0x%06llx\n", LOCAL_HUB_L(PI_ERR_INT_PEND));
70 errst0 = LOCAL_HUB_L(cpu ? PI_ERR_STATUS0_B : PI_ERR_STATUS0_A); 70 errst0 = LOCAL_HUB_L(cpu ? PI_ERR_STATUS0_B : PI_ERR_STATUS0_A);
71 errst1 = LOCAL_HUB_L(cpu ? PI_ERR_STATUS1_B : PI_ERR_STATUS1_A); 71 errst1 = LOCAL_HUB_L(cpu ? PI_ERR_STATUS1_B : PI_ERR_STATUS1_A);
72 dump_hub_information(errst0, errst1); 72 dump_hub_information(errst0, errst1);
diff --git a/arch/mips/sgi-ip27/ip27-nmi.c b/arch/mips/sgi-ip27/ip27-nmi.c
index 64459e7d891b..a1f21d9421e8 100644
--- a/arch/mips/sgi-ip27/ip27-nmi.c
+++ b/arch/mips/sgi-ip27/ip27-nmi.c
@@ -143,8 +143,8 @@ void nmi_dump_hub_irq(nasid_t nasid, int slice)
143 pend0 = REMOTE_HUB_L(nasid, PI_INT_PEND0); 143 pend0 = REMOTE_HUB_L(nasid, PI_INT_PEND0);
144 pend1 = REMOTE_HUB_L(nasid, PI_INT_PEND1); 144 pend1 = REMOTE_HUB_L(nasid, PI_INT_PEND1);
145 145
146 printk("PI_INT_MASK0: %16lx PI_INT_MASK1: %16lx\n", mask0, mask1); 146 printk("PI_INT_MASK0: %16Lx PI_INT_MASK1: %16Lx\n", mask0, mask1);
147 printk("PI_INT_PEND0: %16lx PI_INT_PEND1: %16lx\n", pend0, pend1); 147 printk("PI_INT_PEND0: %16Lx PI_INT_PEND1: %16Lx\n", pend0, pend1);
148 printk("\n\n"); 148 printk("\n\n");
149} 149}
150 150
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index 0d6b6663d5f6..0aefc5319a03 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -325,16 +325,11 @@ static void mask_and_ack_maceisa_irq(unsigned int irq)
325{ 325{
326 unsigned long mace_int; 326 unsigned long mace_int;
327 327
328 switch (irq) { 328 /* edge triggered */
329 case MACEISA_PARALLEL_IRQ: 329 mace_int = mace->perif.ctrl.istat;
330 case MACEISA_SERIAL1_TDMAPR_IRQ: 330 mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
331 case MACEISA_SERIAL2_TDMAPR_IRQ: 331 mace->perif.ctrl.istat = mace_int;
332 /* edge triggered */ 332
333 mace_int = mace->perif.ctrl.istat;
334 mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
335 mace->perif.ctrl.istat = mace_int;
336 break;
337 }
338 disable_maceisa_irq(irq); 333 disable_maceisa_irq(irq);
339} 334}
340 335
@@ -344,7 +339,16 @@ static void end_maceisa_irq(unsigned irq)
344 enable_maceisa_irq(irq); 339 enable_maceisa_irq(irq);
345} 340}
346 341
347static struct irq_chip ip32_maceisa_interrupt = { 342static struct irq_chip ip32_maceisa_level_interrupt = {
343 .name = "IP32 MACE ISA",
344 .ack = disable_maceisa_irq,
345 .mask = disable_maceisa_irq,
346 .mask_ack = disable_maceisa_irq,
347 .unmask = enable_maceisa_irq,
348 .end = end_maceisa_irq,
349};
350
351static struct irq_chip ip32_maceisa_edge_interrupt = {
348 .name = "IP32 MACE ISA", 352 .name = "IP32 MACE ISA",
349 .ack = mask_and_ack_maceisa_irq, 353 .ack = mask_and_ack_maceisa_irq,
350 .mask = disable_maceisa_irq, 354 .mask = disable_maceisa_irq,
@@ -500,27 +504,50 @@ void __init arch_init_irq(void)
500 for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) { 504 for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
501 switch (irq) { 505 switch (irq) {
502 case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ: 506 case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
503 set_irq_chip(irq, &ip32_mace_interrupt); 507 set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt,
508 handle_level_irq, "level");
504 break; 509 break;
510
505 case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ: 511 case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ:
506 set_irq_chip(irq, &ip32_macepci_interrupt); 512 set_irq_chip_and_handler_name(irq,
513 &ip32_macepci_interrupt, handle_level_irq,
514 "level");
507 break; 515 break;
516
508 case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ: 517 case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
509 set_irq_chip(irq, &crime_edge_interrupt); 518 set_irq_chip_and_handler_name(irq,
519 &crime_edge_interrupt, handle_edge_irq, "edge");
510 break; 520 break;
511 case CRIME_CPUERR_IRQ: 521 case CRIME_CPUERR_IRQ:
512 case CRIME_MEMERR_IRQ: 522 case CRIME_MEMERR_IRQ:
513 set_irq_chip(irq, &crime_level_interrupt); 523 set_irq_chip_and_handler_name(irq,
524 &crime_level_interrupt, handle_level_irq,
525 "level");
514 break; 526 break;
527
515 case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ: 528 case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
516 case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ: 529 case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
517 set_irq_chip(irq, &crime_edge_interrupt); 530 set_irq_chip_and_handler_name(irq,
531 &crime_edge_interrupt, handle_edge_irq, "edge");
518 break; 532 break;
533
519 case CRIME_VICE_IRQ: 534 case CRIME_VICE_IRQ:
520 set_irq_chip(irq, &crime_edge_interrupt); 535 set_irq_chip_and_handler_name(irq,
536 &crime_edge_interrupt, handle_edge_irq, "edge");
537 break;
538
539 case MACEISA_PARALLEL_IRQ:
540 case MACEISA_SERIAL1_TDMAPR_IRQ:
541 case MACEISA_SERIAL2_TDMAPR_IRQ:
542 set_irq_chip_and_handler_name(irq,
543 &ip32_maceisa_edge_interrupt, handle_edge_irq,
544 "edge");
521 break; 545 break;
546
522 default: 547 default:
523 set_irq_chip(irq, &ip32_maceisa_interrupt); 548 set_irq_chip_and_handler_name(irq,
549 &ip32_maceisa_level_interrupt, handle_level_irq,
550 "level");
524 break; 551 break;
525 } 552 }
526 } 553 }
diff --git a/arch/mips/sgi-ip32/ip32-memory.c b/arch/mips/sgi-ip32/ip32-memory.c
index ca93ecf825ae..828ce131c228 100644
--- a/arch/mips/sgi-ip32/ip32-memory.c
+++ b/arch/mips/sgi-ip32/ip32-memory.c
@@ -36,7 +36,7 @@ void __init prom_meminit(void)
36 if (base + size > (256 << 20)) 36 if (base + size > (256 << 20))
37 base += CRIME_HI_MEM_BASE; 37 base += CRIME_HI_MEM_BASE;
38 38
39 printk("CRIME MC: bank %u base 0x%016lx size %luMiB\n", 39 printk("CRIME MC: bank %u base 0x%016Lx size %LuMiB\n",
40 bank, base, size >> 20); 40 bank, base, size >> 20);
41 add_memory_region(base, size, BOOT_MEM_RAM); 41 add_memory_region(base, size, BOOT_MEM_RAM);
42 } 42 }
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 12b465d404df..352352b3cb2f 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -236,7 +236,7 @@ void __init init_bcm1480_irqs(void)
236 int i; 236 int i;
237 237
238 for (i = 0; i < BCM1480_NR_IRQS; i++) { 238 for (i = 0; i < BCM1480_NR_IRQS; i++) {
239 set_irq_chip(i, &bcm1480_irq_type); 239 set_irq_chip_and_handler(i, &bcm1480_irq_type, handle_level_irq);
240 bcm1480_irq_owner[i] = 0; 240 bcm1480_irq_owner[i] = 0;
241 } 241 }
242} 242}
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 808ac2959b8c..c08ff582da6f 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -220,7 +220,7 @@ void __init init_sb1250_irqs(void)
220 int i; 220 int i;
221 221
222 for (i = 0; i < SB1250_NR_IRQS; i++) { 222 for (i = 0; i < SB1250_NR_IRQS; i++) {
223 set_irq_chip(i, &sb1250_irq_type); 223 set_irq_chip_and_handler(i, &sb1250_irq_type, handle_level_irq);
224 sb1250_irq_owner[i] = 0; 224 sb1250_irq_owner[i] = 0;
225 } 225 }
226} 226}
diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c
index 3f8cf5eb2f06..7dd76fb3b645 100644
--- a/arch/mips/sni/a20r.c
+++ b/arch/mips/sni/a20r.c
@@ -219,7 +219,7 @@ void __init sni_a20r_irq_init(void)
219 int i; 219 int i;
220 220
221 for (i = SNI_A20R_IRQ_BASE + 2 ; i < SNI_A20R_IRQ_BASE + 8; i++) 221 for (i = SNI_A20R_IRQ_BASE + 2 ; i < SNI_A20R_IRQ_BASE + 8; i++)
222 set_irq_chip(i, &a20r_irq_type); 222 set_irq_chip_and_handler(i, &a20r_irq_type, handle_level_irq);
223 sni_hwint = a20r_hwint; 223 sni_hwint = a20r_hwint;
224 change_c0_status(ST0_IM, IE_IRQ0); 224 change_c0_status(ST0_IM, IE_IRQ0);
225 setup_irq(SNI_A20R_IRQ_BASE + 3, &sni_isa_irq); 225 setup_irq(SNI_A20R_IRQ_BASE + 3, &sni_isa_irq);
diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c
index 834650f371e0..74e6c67982fb 100644
--- a/arch/mips/sni/pcimt.c
+++ b/arch/mips/sni/pcimt.c
@@ -304,7 +304,7 @@ void __init sni_pcimt_irq_init(void)
304 mips_cpu_irq_init(); 304 mips_cpu_irq_init();
305 /* Actually we've got more interrupts to handle ... */ 305 /* Actually we've got more interrupts to handle ... */
306 for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_SCSI; i++) 306 for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_SCSI; i++)
307 set_irq_chip(i, &pcimt_irq_type); 307 set_irq_chip_and_handler(i, &pcimt_irq_type, handle_level_irq);
308 sni_hwint = sni_pcimt_hwint; 308 sni_hwint = sni_pcimt_hwint;
309 change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3); 309 change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3);
310} 310}
diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c
index e5f12cf96e8e..071a9573ac7f 100644
--- a/arch/mips/sni/pcit.c
+++ b/arch/mips/sni/pcit.c
@@ -246,7 +246,7 @@ void __init sni_pcit_irq_init(void)
246 246
247 mips_cpu_irq_init(); 247 mips_cpu_irq_init();
248 for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++) 248 for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
249 set_irq_chip(i, &pcit_irq_type); 249 set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
250 *(volatile u32 *)SNI_PCIT_INT_REG = 0; 250 *(volatile u32 *)SNI_PCIT_INT_REG = 0;
251 sni_hwint = sni_pcit_hwint; 251 sni_hwint = sni_pcit_hwint;
252 change_c0_status(ST0_IM, IE_IRQ1); 252 change_c0_status(ST0_IM, IE_IRQ1);
@@ -259,7 +259,7 @@ void __init sni_pcit_cplus_irq_init(void)
259 259
260 mips_cpu_irq_init(); 260 mips_cpu_irq_init();
261 for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++) 261 for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
262 set_irq_chip(i, &pcit_irq_type); 262 set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
263 *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000; 263 *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000;
264 sni_hwint = sni_pcit_hwint_cplus; 264 sni_hwint = sni_pcit_hwint_cplus;
265 change_c0_status(ST0_IM, IE_IRQ0); 265 change_c0_status(ST0_IM, IE_IRQ0);
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index 5310aa75afa4..b4352a0c8151 100644
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -487,7 +487,7 @@ void __init sni_rm200_irq_init(void)
487 mips_cpu_irq_init(); 487 mips_cpu_irq_init();
488 /* Actually we've got more interrupts to handle ... */ 488 /* Actually we've got more interrupts to handle ... */
489 for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++) 489 for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++)
490 set_irq_chip(i, &rm200_irq_type); 490 set_irq_chip_and_handler(i, &rm200_irq_type, handle_level_irq);
491 sni_hwint = sni_rm200_hwint; 491 sni_hwint = sni_rm200_hwint;
492 change_c0_status(ST0_IM, IE_IRQ0); 492 change_c0_status(ST0_IM, IE_IRQ0);
493 setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq); 493 setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq);
diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig
index 226e8bb2f0a1..0db7cf38ed8b 100644
--- a/arch/mips/txx9/Kconfig
+++ b/arch/mips/txx9/Kconfig
@@ -20,7 +20,6 @@ config MACH_TXX9
20 select SYS_SUPPORTS_32BIT_KERNEL 20 select SYS_SUPPORTS_32BIT_KERNEL
21 select SYS_SUPPORTS_LITTLE_ENDIAN 21 select SYS_SUPPORTS_LITTLE_ENDIAN
22 select SYS_SUPPORTS_BIG_ENDIAN 22 select SYS_SUPPORTS_BIG_ENDIAN
23 select GENERIC_HARDIRQS_NO__DO_IRQ
24 23
25config TOSHIBA_JMR3927 24config TOSHIBA_JMR3927
26 bool "Toshiba JMR-TX3927 board" 25 bool "Toshiba JMR-TX3927 board"
diff --git a/drivers/net/meth.c b/drivers/net/meth.c
index c336a1f42510..aa08987f6e81 100644
--- a/drivers/net/meth.c
+++ b/drivers/net/meth.c
@@ -398,7 +398,7 @@ static void meth_rx(struct net_device* dev, unsigned long int_status)
398 int len = (status & 0xffff) - 4; /* omit CRC */ 398 int len = (status & 0xffff) - 4; /* omit CRC */
399 /* length sanity check */ 399 /* length sanity check */
400 if (len < 60 || len > 1518) { 400 if (len < 60 || len > 1518) {
401 printk(KERN_DEBUG "%s: bogus packet size: %ld, status=%#2lx.\n", 401 printk(KERN_DEBUG "%s: bogus packet size: %ld, status=%#2Lx.\n",
402 dev->name, priv->rx_write, 402 dev->name, priv->rx_write,
403 priv->rx_ring[priv->rx_write]->status.raw); 403 priv->rx_ring[priv->rx_write]->status.raw);
404 dev->stats.rx_errors++; 404 dev->stats.rx_errors++;
diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h
index 6c44f86ae3fd..912308eec865 100644
--- a/drivers/net/smc91x.h
+++ b/drivers/net/smc91x.h
@@ -346,38 +346,6 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r,
346#define RPC_LSA_DEFAULT RPC_LED_TX_RX 346#define RPC_LSA_DEFAULT RPC_LED_TX_RX
347#define RPC_LSB_DEFAULT RPC_LED_100_10 347#define RPC_LSB_DEFAULT RPC_LED_100_10
348 348
349#elif defined(CONFIG_SOC_AU1X00)
350
351#include <au1xxx.h>
352
353/* We can only do 16-bit reads and writes in the static memory space. */
354#define SMC_CAN_USE_8BIT 0
355#define SMC_CAN_USE_16BIT 1
356#define SMC_CAN_USE_32BIT 0
357#define SMC_IO_SHIFT 0
358#define SMC_NOWAIT 1
359
360#define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
361#define SMC_insw(a, r, p, l) \
362 do { \
363 unsigned long _a = (unsigned long)((a) + (r)); \
364 int _l = (l); \
365 u16 *_p = (u16 *)(p); \
366 while (_l-- > 0) \
367 *_p++ = au_readw(_a); \
368 } while(0)
369#define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
370#define SMC_outsw(a, r, p, l) \
371 do { \
372 unsigned long _a = (unsigned long)((a) + (r)); \
373 int _l = (l); \
374 const u16 *_p = (const u16 *)(p); \
375 while (_l-- > 0) \
376 au_writew(*_p++ , _a); \
377 } while(0)
378
379#define SMC_IRQ_FLAGS (0)
380
381#elif defined(CONFIG_ARCH_VERSATILE) 349#elif defined(CONFIG_ARCH_VERSATILE)
382 350
383#define SMC_CAN_USE_8BIT 1 351#define SMC_CAN_USE_8BIT 1
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-26 18:46:30 -0500